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base: yuysh/NewInstrCalBoard_CPLD:0a3d8b77abd88a4de3f7a7ab4abc85fcb760fae7
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yuysh/NewInstrCalBoard_CPLD:master
yuysh/NewInstrCalBoard_CPLD:v1.1.2 yuysh/NewInstrCalBoard_CPLD:v1.1.0
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compare: yuysh/NewInstrCalBoard_CPLD:v1.1.2
Branches Tags
yuysh/NewInstrCalBoard_CPLD:master
yuysh/NewInstrCalBoard_CPLD:v1.1.2 yuysh/NewInstrCalBoard_CPLD:v1.1.0
35 Commits
0a3d8b77ab .. v1.1.2
Author SHA1 Message Date
yuysh 37228e2bac Fix CPLD1: PMU Logic bug 2026-06-16 14:59:46 +08:00
yuysh f0f42f0204 Fix version typo 2026-06-16 10:32:26 +08:00
Jeremy Shen e3fa9dc9c1 Modify CPLD2's PMU related Pin defination. Add proper Pull UP/Down. Increase Version Number 2026-06-16 10:27:53 +08:00
Jeremy Shen fe80ae462d Feat: 
CPLD2: Add DPS Pin Definiations
 2026-06-15 18:37:47 +08:00
Jeremy Shen fd5ac5eae0 Feat: 
CPLD2: Add DPS Function
 2026-06-15 17:50:08 +08:00
Jeremy Shen 1ab71827c7 Feat: 
CPLD1: Add DPS Related Pin Defination
CPLD1: Add DPS Related Functions
Fix:
CPLD1: Remove unused pins
Improve:
CPLD1: PMU Logics
 2026-06-15 10:40:38 +08:00
yuysh c447c6a592 Bug fixes 2026-06-09 14:58:30 +08:00
yuysh e19adb09f9 Fix bugs and Unify the PMU_OC logic 2026-06-09 11:41:21 +08:00
yuysh 092cad794c Remove unecessary code in CPLD1 
Unify PMU_OC_* logic in CPLD2
 2026-06-08 18:14:44 +08:00
Jeremy Shen 1d92e2c53e Add DC Relay Control Logic 2026-06-08 15:44:24 +08:00
Jeremy Shen 61076299a0 Add SPI testbench 2026-06-08 10:14:17 +08:00
yuysh 4fd22c4919 Add Channel Naming for CPLD2 2026-06-08 09:53:57 +08:00
yuysh 0c9843f9c8 Fix CPLD1 Rx_T 2026-06-08 09:51:25 +08:00
yuysh c828a3b019 Make the CPLD_Con more readable 2026-06-06 15:33:24 +08:00
yuysh 36e6eb5768 Unify the OC_Con logic 2026-06-05 16:49:20 +08:00
yuysh 607b43837d Fix RC_RLSel Shifting logic(2/?) 2026-06-02 18:33:16 +08:00
yuysh 9f47d03477 Merge branch 'master' of http://mkb.local:3000/yuysh/NewInstrCalBoard_CPLD 2026-06-02 17:27:06 +08:00
Jeremy Shen ff4d6a10cc Fix RC_RLSel Shifting logic 2026-06-02 17:21:32 +08:00
yuysh 2301ab9405 Fix version code for CPLD3 2026-06-02 14:50:29 +08:00
yuysh fa41cd029f Fix MISO logic for CPLD2 & CPLD3 2026-06-02 14:50:13 +08:00
Jeremy Shen ed3fbd7cf5 Fix the SPI MISO logic 
Modify the tb to make it easier from all aspects
 2026-06-02 11:23:34 +08:00
Jeremy Shen 070ad1c768 Merge branch 'master' of http://mkb.local:3000/yuysh/NewInstrCalBoard_CPLD 2026-06-01 18:03:33 +08:00
Jeremy Shen 34b8bdbdd8 Add SPI_Reg testbench 2026-06-01 18:03:16 +08:00
yuysh 263eb9f16d TODO: Fix MISO logic (1/?) 2026-06-01 16:20:38 +08:00
yuysh 8f65c6908d Change RC_RLSel logic 2026-06-01 16:19:58 +08:00
Jeremy Shen e60d56dd26 Change MISO logic 2026-06-01 14:44:18 +08:00
Jeremy Shen 5b949c6b63 Fix MISO Logic 2026-06-01 12:37:02 +08:00
yuysh 54a64ec222 Bug fixes for all CPLDs 2026-05-29 18:31:27 +08:00
Jeremy Shen b3eef70c28 CPLD1 fix DMM & OC shifting logic 2026-05-29 17:42:08 +08:00
yuysh 3e722a7f15 Modify simulation files 2026-05-29 16:32:58 +08:00
yuysh 611945be04 Update CPLD1 output 2026-05-28 10:41:58 +08:00
yuysh da61ebe108 Update ignored items 2026-05-28 10:41:25 +08:00
yuysh 8de946787c CPLD1 debug logic too large, delete some signals 2026-05-28 10:29:27 +08:00
Jeremy Shen bf6769d814 gitignore fix 2026-05-28 10:25:03 +08:00
yuysh 48629141a8 Update gitignore 2026-05-28 10:04:31 +08:00
119 changed files with 81698 additions and 157543 deletions
Expand all files Collapse all files
.gitignore
+11 -8
View File
@@ -7,11 +7,19 @@
# ============================================================ # ============================================================
# ---------- Build output ---------- # ---------- Build output ----------
impl1/*
*_tcr.dir/ *_tcr.dir/
# Negate: files inside impl1/ that Diamond needs #Others
!*/impl1/*.hub .vscode
.recovery
*.edn
*.cam
*.areasrr
*.pt
*.hrr
*.sym
pmi_*
*._cml
# ---------- Synthesis (Synplify Pro / Synplify) ---------- # ---------- Synthesis (Synplify Pro / Synplify) ----------
synlog/ synlog/
@@ -49,9 +57,6 @@ syntmp/
*.fdepxmr *.fdepxmr
*.schmap *.schmap
# ---------- PMI (Physical Model Information) ----------
pmi_*/
# ---------- Auto-generated junk ---------- # ---------- Auto-generated junk ----------
*.lst *.lst
*.naf *.naf
@@ -140,8 +145,6 @@ reveal_workspace/
!*.bit !*.bit
!*.jed !*.jed
!*.svf !*.svf
!*.rva
!*.trc
!*.xcf !*.xcf
# Simulation project files (.spf is needed by Diamond's sim engine) # Simulation project files (.spf is needed by Diamond's sim engine)
CPLD1/BUS_Con.v
+60 -31
View File
@@ -28,7 +28,6 @@ module BUS_Con (
reg [1:0] mosi_sync; reg [1:0] mosi_sync;
wire cs_active; wire cs_active;
wire cs_rise;
wire sclk_rise; // For Sampling MOSI wire sclk_rise; // For Sampling MOSI
wire sclk_fall; // For Shifting MISO wire sclk_fall; // For Shifting MISO
wire mosi_data; wire mosi_data;
@@ -47,7 +46,6 @@ module BUS_Con (
end end
assign cs_active = ~cs_sync[1]; assign cs_active = ~cs_sync[1];
assign cs_rise = (!cs_sync[1] && cs_sync[0]);
// SPI Mode 0: Sample MOSI on Rising, Shift MISO on Falling // SPI Mode 0: Sample MOSI on Rising, Shift MISO on Falling
assign sclk_rise = (!sclk_sync[1] && sclk_sync[0]); assign sclk_rise = (!sclk_sync[1] && sclk_sync[0]);
@@ -61,8 +59,9 @@ module BUS_Con (
reg err_flag; reg err_flag;
reg [1:0] state; reg [1:0] state;
// //
reg [31:0] tx_buffer; // Holds data waiting for the next CS Low
reg [31:0] miso_shift; // The actual shifter reg [31:0] miso_shift; // The actual shifter
reg wr_flag;// Flag: 1=W/0=R
reg miso_loaded;
// Output Registers // Output Registers
reg [6:0] addr_out; reg [6:0] addr_out;
reg [23:0] data_out; reg [23:0] data_out;
@@ -82,75 +81,98 @@ module BUS_Con (
bit_cnt <= 6'd0; bit_cnt <= 6'd0;
data_ready <= 1'b0; data_ready <= 1'b0;
err_flag <= 1'b0; err_flag <= 1'b0;
wr_flag <= 1'b1;
end end
else begin else begin
// Clear data_ready when FSM has consumed the command (CMD_SENT = consumed)
if (state == CMD_SENT) begin
data_ready <= 1'b0; data_ready <= 1'b0;
end
if (cs_active) begin if (cs_active) begin
if (sclk_rise) begin if (sclk_rise) begin
recv_reg <= {recv_reg[30:0], mosi_data}; recv_reg <= {recv_reg[30:0], mosi_data};
bit_cnt <= bit_cnt + 1'b1; bit_cnt <= bit_cnt + 1'b1;
end
else if (cs_rise) begin // After 8 bits: check WR bit (recv_reg[7] = first bit received)
if (bit_cnt == 6'd32) begin // Read (WR=0): set data_ready early so MISO data is prepared
// Write (WR=1): wait for all 32 bits
if (bit_cnt == 'd7) begin
if (recv_reg[6] == 1'b0) begin
// Read command: signal ready after address received
data_ready <= 1'b1; data_ready <= 1'b1;
wr_flag <= 1'b0;
end
else begin
wr_flag <= 1'b1;
end
end
else if (bit_cnt == 6'd31) begin
// Write command complete (32 bits received)
data_ready <= 1'b1;
end
end
else if (!cs_active) begin
data_ready <= 1'b0;
if (bit_cnt == 6'd31) begin
err_flag <= 1'b0; err_flag <= 1'b0;
bit_cnt <= 6'd0; bit_cnt <= 6'd0;
end end
else if (bit_cnt != 0) begin else if (bit_cnt != 0 && bit_cnt != 6'd32) begin
err_flag <= 1'b1; err_flag <= 1'b1;
bit_cnt <= 6'd0; bit_cnt <= 6'd0;
recv_reg <= 'd0; recv_reg <= 'd0;
end end
end end
end end
if (state == DONE) begin else begin
// CS high: reset state
bit_cnt <= 6'd0;
recv_reg <= 'd0; recv_reg <= 'd0;
data_ready <= 1'b0;
end end
end end
end end
// --- 3. MISO (Transmit) Logic --- // --- 3. MISO (Transmit) Logic ---
// Protocol: We shift out 32 bits. // Protocol: We shift out 32 bits.
// Format: [8 bit Status/Padding] + [24 bit i_rdata] // Format: [8'h00 padding] + [24 bit i_rdata]
// Shift MSB out on each falling edge of SCLK (master samples on rising)
// Consolidated: load on first rising edge, shift on falling edges
// Capture data from backend when valid
always @(posedge i_sys_clk) begin
if (!i_rst_n) begin
tx_buffer <= 32'd0;
end else begin
// If backend provides valid read data, store it.
// We pad the top 8 bits with Zeros (or you can put status flags here)
if (i_rvalid) begin
tx_buffer <= {8'h00, i_rdata};
end
end
end
// Shift data out
always @(posedge i_sys_clk) begin always @(posedge i_sys_clk) begin
if (!i_rst_n) begin if (!i_rst_n) begin
miso_shift <= 32'd0; miso_shift <= 32'd0;
end else begin miso_loaded <= 1'b0;
end
else begin
if (!cs_active) begin if (!cs_active) begin
// Pre-load the shifter while CS is High // Reset shifter while CS is High
// This ensures Bit 31 is ready BEFORE the first clock edge miso_shift <= 32'd0;
miso_shift <= tx_buffer; end
end else begin else begin
// Shift on Falling Edge (Master samples on Rising) if (i_rvalid && (bit_cnt == 'd8)) begin
if (sclk_fall) begin miso_shift <= {i_rdata,8'd0};
miso_loaded <= 1'b1;
end
if (miso_loaded && sclk_fall) begin
// Shift out MSB on falling edges (data valid before master's rising-edge sample)
if (bit_cnt > 'd8) begin
miso_shift <= {miso_shift[30:0], 1'b0}; miso_shift <= {miso_shift[30:0], 1'b0};
end end
end end
end end
end end
end
// Tri-state MISO when CS is high (optional, usually good practice) // Tri-state MISO when CS is high (optional, usually good practice)
// If your board doesn't need tristate, just use: assign o_miso = miso_shift[31]; // If your board doesn't need tristate, just use: assign o_miso = miso_shift[31];
assign o_miso = (cs_active) ? miso_shift[31] : 1'bz; assign o_miso = (cs_active) ? miso_shift[31] : 1'bz;
// --- 4. Register Control FSM --- // --- 4. Register Control FSM ---
// Command format: [WR:1b][Addr:7b][Data:24b] = 32 bits
// recv_reg layout after 32 bits: {WR, Addr[6:0], Data[23:0]}
always @(posedge i_sys_clk) begin always @(posedge i_sys_clk) begin
if (!i_rst_n) begin if (!i_rst_n) begin
@@ -163,9 +185,16 @@ module BUS_Con (
case (state) case (state)
IDLE: begin IDLE: begin
if (data_ready) begin if (data_ready) begin
// Extract fields from received command
if (wr_flag == 1'b1) begin
addr_out <= recv_reg[30:24]; addr_out <= recv_reg[30:24];
data_out <= recv_reg[23:0]; data_out <= recv_reg[23:0];
wr_out <= recv_reg[31]; wr_out <= recv_reg[31];
end
else begin
addr_out <= recv_reg[6:0];
wr_out <= recv_reg[7];
end
if (!i_reg_busy) begin if (!i_reg_busy) begin
cmd_valid_out <= 1'b1; cmd_valid_out <= 1'b1;
CPLD1/CPLD1_Debug.rva
+90 -46
View File
@@ -27,64 +27,108 @@
<WinUI CoreIndex="0"> <WinUI CoreIndex="0">
<TraceSigTreeData> <TraceSigTreeData>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_cs" NodeType="0" PortIndex="0"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/i_cs" NodeType="0" PortIndex="0"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_mosi" NodeType="0" PortIndex="1"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/i_sclk" NodeType="0" PortIndex="1"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_sclk" NodeType="0" PortIndex="2"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/i_mosi" NodeType="0" PortIndex="2"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/exec_flag" NodeType="0" PortIndex="3"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/bit_cnt" NodeType="1" PortIndex="3">
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/i_con_exec" NodeType="0" PortIndex="4"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/slot_exec_flag" NodeType="1" PortIndex="5">
<BusRadix Radix="0"/> <BusRadix Radix="0"/>
<IsExpanded Expand="false"/> <IsExpanded Expand="false"/>
</TraceSignal> </TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/slot_exec_flag:0" NodeType="2" PortIndex="5"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/bit_cnt:0" NodeType="2" PortIndex="3"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/slot_exec_flag:1" NodeType="2" PortIndex="6"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/bit_cnt:1" NodeType="2" PortIndex="4"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/slot_exec_flag:2" NodeType="2" PortIndex="7"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/bit_cnt:2" NodeType="2" PortIndex="5"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/slot_exec_flag:3" NodeType="2" PortIndex="8"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/bit_cnt:3" NodeType="2" PortIndex="6"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x01" NodeType="1" PortIndex="9"> <TraceSignal IsHidden="false" Name="BUS_Con_1/bit_cnt:4" NodeType="2" PortIndex="7"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/bit_cnt:5" NodeType="2" PortIndex="8"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/recv_reg" NodeType="1" PortIndex="9">
<BusRadix Radix="0"/> <BusRadix Radix="0"/>
<IsExpanded Expand="false"/> <IsExpanded Expand="false"/>
</TraceSignal> </TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x01:0" NodeType="2" PortIndex="9"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/recv_reg:24" NodeType="2" PortIndex="9"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x01:1" NodeType="2" PortIndex="10"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/recv_reg:25" NodeType="2" PortIndex="10"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x01:2" NodeType="2" PortIndex="11"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/recv_reg:26" NodeType="2" PortIndex="11"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x01:3" NodeType="2" PortIndex="12"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/recv_reg:27" NodeType="2" PortIndex="12"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x17" NodeType="1" PortIndex="13"> <TraceSignal IsHidden="false" Name="BUS_Con_1/recv_reg:28" NodeType="2" PortIndex="13"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/recv_reg:29" NodeType="2" PortIndex="14"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/recv_reg:30" NodeType="2" PortIndex="15"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/recv_reg:31" NodeType="2" PortIndex="16"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/data_ready" NodeType="0" PortIndex="17"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/o_addr" NodeType="1" PortIndex="18">
<BusRadix Radix="0"/> <BusRadix Radix="0"/>
<IsExpanded Expand="false"/> <IsExpanded Expand="false"/>
</TraceSignal> </TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x17:0" NodeType="2" PortIndex="13"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/o_addr:0" NodeType="2" PortIndex="18"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x17:1" NodeType="2" PortIndex="14"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/o_addr:1" NodeType="2" PortIndex="19"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x17:2" NodeType="2" PortIndex="15"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/o_addr:2" NodeType="2" PortIndex="20"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x17:3" NodeType="2" PortIndex="16"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/o_addr:3" NodeType="2" PortIndex="21"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN" NodeType="1" PortIndex="17"> <TraceSignal IsHidden="false" Name="BUS_Con_1/o_addr:4" NodeType="2" PortIndex="22"/>
<BusRadix Radix="0"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/o_addr:5" NodeType="2" PortIndex="23"/>
<IsExpanded Expand="true"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/o_addr:6" NodeType="2" PortIndex="24"/>
</TraceSignal> <TraceSignal IsHidden="false" Name="BUS_Con_1/i_rvalid" NodeType="0" PortIndex="25"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:0" NodeType="2" PortIndex="17"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift" NodeType="1" PortIndex="26">
<TraceSignal IsHidden="false" Name="o_DMM_EN:1" NodeType="2" PortIndex="18"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:2" NodeType="2" PortIndex="19"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:3" NodeType="2" PortIndex="20"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:4" NodeType="2" PortIndex="21"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:5" NodeType="2" PortIndex="22"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:6" NodeType="2" PortIndex="23"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:7" NodeType="2" PortIndex="24"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:8" NodeType="2" PortIndex="25"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:9" NodeType="2" PortIndex="26"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:10" NodeType="2" PortIndex="27"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:11" NodeType="2" PortIndex="28"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:12" NodeType="2" PortIndex="29"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:13" NodeType="2" PortIndex="30"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:14" NodeType="2" PortIndex="31"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:15" NodeType="2" PortIndex="32"/>
<TraceSignal IsHidden="false" Name="o_IO_RC1" NodeType="0" PortIndex="33"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx" NodeType="1" PortIndex="34">
<BusRadix Radix="0"/> <BusRadix Radix="0"/>
<IsExpanded Expand="false"/> <IsExpanded Expand="false"/>
</TraceSignal> </TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx:0" NodeType="2" PortIndex="34"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:0" NodeType="2" PortIndex="26"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx:1" NodeType="2" PortIndex="35"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:1" NodeType="2" PortIndex="27"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx:2" NodeType="2" PortIndex="36"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:2" NodeType="2" PortIndex="28"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx:3" NodeType="2" PortIndex="37"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:3" NodeType="2" PortIndex="29"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx:4" NodeType="2" PortIndex="38"/> <TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:4" NodeType="2" PortIndex="30"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:5" NodeType="2" PortIndex="31"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:6" NodeType="2" PortIndex="32"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:7" NodeType="2" PortIndex="33"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:8" NodeType="2" PortIndex="34"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:9" NodeType="2" PortIndex="35"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:10" NodeType="2" PortIndex="36"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:11" NodeType="2" PortIndex="37"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:12" NodeType="2" PortIndex="38"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:13" NodeType="2" PortIndex="39"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:14" NodeType="2" PortIndex="40"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:15" NodeType="2" PortIndex="41"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:16" NodeType="2" PortIndex="42"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:17" NodeType="2" PortIndex="43"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:18" NodeType="2" PortIndex="44"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:19" NodeType="2" PortIndex="45"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:20" NodeType="2" PortIndex="46"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:21" NodeType="2" PortIndex="47"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:22" NodeType="2" PortIndex="48"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:23" NodeType="2" PortIndex="49"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:24" NodeType="2" PortIndex="50"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:25" NodeType="2" PortIndex="51"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:26" NodeType="2" PortIndex="52"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:27" NodeType="2" PortIndex="53"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:28" NodeType="2" PortIndex="54"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:29" NodeType="2" PortIndex="55"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:30" NodeType="2" PortIndex="56"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/miso_shift:31" NodeType="2" PortIndex="57"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/o_miso" NodeType="0" PortIndex="58"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata" NodeType="1" PortIndex="59">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:0" NodeType="2" PortIndex="59"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:1" NodeType="2" PortIndex="60"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:2" NodeType="2" PortIndex="61"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:3" NodeType="2" PortIndex="62"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:4" NodeType="2" PortIndex="63"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:5" NodeType="2" PortIndex="64"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:6" NodeType="2" PortIndex="65"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:7" NodeType="2" PortIndex="66"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:8" NodeType="2" PortIndex="67"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:9" NodeType="2" PortIndex="68"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:10" NodeType="2" PortIndex="69"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:11" NodeType="2" PortIndex="70"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:12" NodeType="2" PortIndex="71"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:13" NodeType="2" PortIndex="72"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:14" NodeType="2" PortIndex="73"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:15" NodeType="2" PortIndex="74"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:16" NodeType="2" PortIndex="75"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:17" NodeType="2" PortIndex="76"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:18" NodeType="2" PortIndex="77"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:19" NodeType="2" PortIndex="78"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:20" NodeType="2" PortIndex="79"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:21" NodeType="2" PortIndex="80"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:22" NodeType="2" PortIndex="81"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_rdata:23" NodeType="2" PortIndex="82"/>
</TraceSigTreeData> </TraceSigTreeData>
<TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/> <TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/>
<CoreRun Run="true"/> <CoreRun Run="true"/>
CPLD1/CPLD1_Debug.svf
+608 -73
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CPLD1/CPLD1_Debug.trc
+2051 -2051
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CPLD1/CPLD_Con.v
+267 -95
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@@ -16,21 +16,33 @@ module CPLD_Con (
input [23:0]i_DC_Con4, input [23:0]i_DC_Con4,
//Output RELAYs //Output RELAYs
output [3:0]o_OC_x01,
output [3:0]o_OC_x17,
output [18:0]o_DMM_EN, output [18:0]o_DMM_EN,
output o_IO_RC1, output o_IO_RC1,
output [5:0]o_RC_Tx, output [5:0]o_RC_Tx,
//PMU OC Control
output [31:0]o_PMU_OC_1 , output [31:0]o_PMU_OC_1 ,
output [31:0]o_PMU_OC_2 , output [31:0]o_PMU_OC_2 ,
output [31:0]o_PMU_OC_3 , output [31:0]o_PMU_OC_3 ,
output [31:0]o_PMU_OC_4 , output [31:0]o_PMU_OC_4 ,
//DPS OC Control
output [15:0]o_DPS_FS_1 ,
output [15:0]o_DPS_FS_2 ,
output [15:0]o_DPS_FS_3 ,
output [15:0]o_DPS_FS_4 ,
output [3:0]o_DPS_FSMC ,
output [5:0]o_DPS_FSMMC ,
output o_DPSFS_RC1 ,
// DMM Mode Sel // DMM Mode Sel
output o_RC_VSel, output o_RC_VSel,
output o_RC_ISel, output o_RC_ISel,
// Force/Sense Control
output [1:0]o_RC_LOFS,
// Output RLoad Sel // Output RLoad Sel
output [17:0]o_RC_RLSel, output [17:0]o_RC_RLSel,
@@ -47,17 +59,28 @@ module CPLD_Con (
reg[5:0]RC_Tx; reg[5:0]RC_Tx;
reg io_RC; reg io_RC;
reg RC_VISel; reg RC_VSel;
reg RC_ISel;
reg [1:0]RC_LOFS;
reg [17:0]RC_RLSel ; reg [17:0]RC_RLSel ;
reg [31:0]PMU_OC_1 ; reg [31:0]PMU_OC_1 ;
reg [31:0]PMU_OC_2 ; reg [31:0]PMU_OC_2 ;
reg [31:0]PMU_OC_3 ; reg [31:0]PMU_OC_3 ;
reg [31:0]PMU_OC_4 ; reg [31:0]PMU_OC_4 ;
reg [31:0]DPS_FS_1 ;
reg [31:0]DPS_FS_2 ;
reg [31:0]DPS_FS_3 ;
reg [31:0]DPS_FS_4 ;
reg [3:0]DPS_FSMC ;
reg [5:0]DPS_FSMMC ;
reg DPSFS_RC1 ;
//Condition Tester //Condition Tester
reg [15:0]en_t ; reg [3:0]en_t ;
reg freq_t; reg [3:0]freq_t;
reg dc_t; reg [3:0]dc_t;
//Flags //Flags
reg exec_flag; reg exec_flag;
@@ -69,6 +92,30 @@ module CPLD_Con (
//Counter //Counter
reg [15:0]delay_cnt; reg [15:0]delay_cnt;
//Reg Parsing
//Shift Counter
wire [4:0]OC_Shifter1 = (i_DC_Con1[8:1] - 1) >> 3; // Channel Number div 8
wire [2:0]DMM_Shifter1 = i_DC_Con1[8:7] ; // Channel Number div 64
wire [4:0]RC_RLShifter1 = i_DC_Con1[21:17] ; // RC_RL Shifter
wire [4:0]OC_Shifter2 = (i_DC_Con2[8:1] - 1) >> 3; // Channel Number div 8
wire [2:0]DMM_Shifter2 = i_DC_Con2[8:7] ; // Channel Number div 64
wire [4:0]RC_RLShifter2 = i_DC_Con2[21:17] ; // RC_RL Shifter
wire [4:0]OC_Shifter3 = (i_DC_Con3[8:1] - 1) >> 3; // Channel Number div 8
wire [2:0]DMM_Shifter3 = i_DC_Con3[8:7] ; // Channel Number div 64
wire [4:0]RC_RLShifter3 = i_DC_Con3[21:17] ; // RC_RL Shifter
wire [4:0]OC_Shifter4 = (i_DC_Con4[8:1] - 1) >> 3; // Channel Number div 8
wire [2:0]DMM_Shifter4 = i_DC_Con4[8:7] ; // Channel Number div 64
wire [4:0]RC_RLShifter4 = i_DC_Con4[21:17] ; // RC_RL Shifter
//Channels
wire [8:0]Channel_1 = i_DC_Con1[9:1] ;
wire [8:0]Channel_2 = i_DC_Con2[9:1] ;
wire [8:0]Channel_3 = i_DC_Con3[9:1] ;
wire [8:0]Channel_4 = i_DC_Con4[9:1] ;
wire [3:0]DC_OC1 = {PMU_OC_4[0],PMU_OC_3[0],PMU_OC_2[0],PMU_OC_1[0]} ;
wire [3:0]DC_OC17 = {PMU_OC_4[16],PMU_OC_3[16],PMU_OC_2[16],PMU_OC_1[16]} ;
always @(posedge i_sys_clk) begin always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin if (i_rst_n == 1'b0) begin
delay_cnt <= 'd0; delay_cnt <= 'd0;
@@ -106,19 +153,32 @@ module CPLD_Con (
freq_slot_flag <= 'd0; freq_slot_flag <= 'd0;
dc_slot_flag <= 'd0; dc_slot_flag <= 'd0;
OC_x01 <= 'd0;
OC_x17 <= 'd0;
DMM_en <= 'd0; DMM_en <= 'd0;
RC_VISel <='d0; RC_VSel <= 'd1; //Vpk HIGH Disable, LOW Enable
RC_RLSel <='d0; RC_ISel <= 'd1; //Apk HIGH Disable, LOW Enable
RC_LOFS <= 'hf; //HIGH Disable, LOW Enable
RC_RLSel <='hfffff;
RC_Tx <= 'd0 ;
//PMU
PMU_OC_1 <= 'd0 ; PMU_OC_1 <= 'd0 ;
PMU_OC_2 <= 'd0 ; PMU_OC_2 <= 'd0 ;
PMU_OC_3 <= 'd0 ; PMU_OC_3 <= 'd0 ;
PMU_OC_4 <= 'd0 ; PMU_OC_4 <= 'd0 ;
//DPS
//DPS Switches LOW Enable
DPS_FS_1 <= 32'hFFFFFFFF;
DPS_FS_2 <= 32'hFFFFFFFF;
DPS_FS_3 <= 32'hFFFFFFFF;
DPS_FS_4 <= 32'hFFFFFFFF;
DPS_FSMC <= 4'b1111;
DPS_FSMMC <= 6'b11_1111;
DPSFS_RC1 <= 1'b1;
done_flag <= 'd1; done_flag <= 'd1;
end end
else begin else begin
@@ -150,96 +210,82 @@ module CPLD_Con (
io_RC <= i_freq_relay1[0] || i_freq_relay2[0] || i_freq_relay3[0] || i_freq_relay4[0]; io_RC <= i_freq_relay1[0] || i_freq_relay2[0] || i_freq_relay3[0] || i_freq_relay4[0];
case (freq_slot_flag) case (freq_slot_flag)
4'b0001: begin 4'b0001: begin
if (i_freq_relay1[9:1] < 9) begin if (Channel_1 < 9) begin
OC_x01 <= 4'b0001; PMU_OC_1 <= 'd1;
OC_x17 <= 'd0;
DMM_en <= 19'b000_0000_0000_0000_0001; DMM_en <= 19'b000_0000_0000_0000_0001;
end end
else if (i_freq_relay1[9:1] < 73) begin else if (Channel_1 < 73) begin
DMM_en <= 19'b000_0000_0000_0000_0010; DMM_en <= 19'b000_0000_0000_0000_0010;
OC_x01 <= 'd0; PMU_OC_1 <= 'd0;
OC_x17 <= 'd0;
end end
else if (i_freq_relay1[9:1] < 137) begin else if (Channel_1 < 137) begin
OC_x17 <= 4'b0001; PMU_OC_1 <= 1'b1 << 16;
OC_x01 <= 'd0;
DMM_en <= 19'b000_0000_0000_0000_0100; DMM_en <= 19'b000_0000_0000_0000_0100;
end end
else begin else begin
DMM_en <= 19'b000_0000_0000_0000_1000; DMM_en <= 19'b000_0000_0000_0000_1000;
OC_x01 <= 'd0; PMU_OC_1 <= 'd0;
OC_x17 <= 'd0;
end end
end end
4'b0010: begin 4'b0010: begin
if (i_freq_relay2[9:1] < 9) begin if (Channel_2 < 9) begin
OC_x01 <= 4'b0010; PMU_OC_2 <= 'd1;
OC_x17 <= 'd0;
DMM_en <= 19'b000_0000_0000_0001_0000; DMM_en <= 19'b000_0000_0000_0001_0000;
end end
else if (i_freq_relay2[9:1] < 73) begin else if (Channel_2 < 73) begin
DMM_en <= 19'b000_0000_0000_0010_0000; DMM_en <= 19'b000_0000_0000_0010_0000;
OC_x01 <= 'd0; PMU_OC_2 <= 'd0;
OC_x17 <= 'd0;
end end
else if (i_freq_relay2[9:1] < 137) begin else if (Channel_2 < 137) begin
OC_x17 <= 4'b0010; PMU_OC_2 <= 1'b1 << 16;
OC_x01 <= 'd0;
DMM_en <= 19'b000_0000_0000_0100_0000; DMM_en <= 19'b000_0000_0000_0100_0000;
end end
else begin else begin
OC_x01 <= 'd0; PMU_OC_2 <= 'd0;
OC_x17 <= 'd0;
DMM_en <= 19'b000_0000_0000_1000_0000; DMM_en <= 19'b000_0000_0000_1000_0000;
end end
end end
4'b0100: begin 4'b0100: begin
if (i_freq_relay3[9:1] < 9) begin if (Channel_3 < 9) begin
OC_x01 <= 'b0100; PMU_OC_3 <= 'd1;
OC_x17 <= 'd0;
DMM_en <= 19'b000_0000_0001_0000_0000; DMM_en <= 19'b000_0000_0001_0000_0000;
end end
else if ((i_freq_relay3[9:1] > 64)& (i_freq_relay3[9:1] < 73)) begin else if ((Channel_3 > 64)& (Channel_3 < 73)) begin
OC_x01 <= 4'b0000; PMU_OC_3 <= 'd0;
OC_x17 <= 'd0;
DMM_en <= 19'b000_0000_0010_0000_0000; DMM_en <= 19'b000_0000_0010_0000_0000;
end end
else if (i_freq_relay3[9:1] < 137) begin else if (Channel_3 < 137) begin
DMM_en <= 19'b000_0000_0100_0000_0000; DMM_en <= 19'b000_0000_0100_0000_0000;
OC_x01 <= 'd0; PMU_OC_3 <= 1'b1 << 16;
OC_x17 <= 'b0100;
end end
else if (i_freq_relay3[9:1] < 201) begin else if (Channel_3 < 201) begin
OC_x17 <= 4'd0; PMU_OC_3 <= 'd0;
OC_x01 <= 'd0; DMM_en <= 19'b000_0000_1000_0000_0000;
DMM_en <= 16'b000_0000_1000_0000_0000;
end end
end end
4'b1000: begin 4'b1000: begin
if (i_freq_relay4[9:1] < 9) begin if (Channel_4 < 9) begin
OC_x01 <= 4'b1000; PMU_OC_4 <= 'd1;
OC_x17 <= 'd0;
DMM_en <= 19'b000_0001_0000_0000_0000; DMM_en <= 19'b000_0001_0000_0000_0000;
end end
else if (i_freq_relay4[9:1] < 72) begin else if (Channel_4 < 72) begin
DMM_en <= 19'b000_0010_0000_0000_0000; DMM_en <= 19'b000_0010_0000_0000_0000;
OC_x01 <= 'd0; PMU_OC_4 <= 'd0;
OC_x17 <= 'd0;
end end
else if (i_freq_relay4[9:1] < 137) begin else if (Channel_4 < 137) begin
OC_x17 <= 4'b1000; PMU_OC_4 <= 1'b1 << 16;
OC_x01 <= 'd0;
DMM_en <= 19'b000_0100_0000_0000_0000; DMM_en <= 19'b000_0100_0000_0000_0000;
end end
else begin else begin
OC_x01 <= 'd0; PMU_OC_4 <= 'd0;
OC_x17 <= 'd0;
DMM_en <= 19'b000_1000_0000_0000_0000; DMM_en <= 19'b000_1000_0000_0000_0000;
end end
end end
default: begin // You Should NOT be HERE default: begin // You Should NOT be HERE
OC_x01 <= 4'b0000; PMU_OC_1 <= 'd0;
OC_x17 <= 4'b0000; PMU_OC_2 <= 'd0;
PMU_OC_3 <= 'd0;
PMU_OC_4 <= 'd0;
DMM_en <= 'd0; DMM_en <= 'd0;
end end
endcase endcase
@@ -247,102 +293,218 @@ module CPLD_Con (
else if (dc_t == 1'b1) begin else if (dc_t == 1'b1) begin
case (dc_slot_flag) case (dc_slot_flag)
4'b0001: begin 4'b0001: begin
//Here Set Mode and F/S
if (i_DC_Con1[22] == 1'b1) begin if (i_DC_Con1[22] == 1'b1) begin
RC_VISel <= 1'b1; //Select Current RC_VSel <= 1'b1; //Select Current
RC_ISel <= 1'b0;
RC_LOFS <= 2'b01;
end end
else begin else begin
RC_VISel <= 1'b0; //Select Voltage RC_VSel <= 1'b0; //Select Voltage
RC_ISel <= 1'b1;
RC_LOFS <= 2'b10;
end end
//Sanity Check //Sanity Check
if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18) || (i_DC_Con1[9:1] < 1) || (i_DC_Con1[9:1] > 256)) begin if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18)) begin
err_flag <= 1'b1; err_flag <= 1'b1;
end end
else begin else begin
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con1[21:17] - 1); RC_RLSel <= (RC_RLShifter1 >= 1 && RC_RLShifter1 <= 18)
? ~(18'b1 << (RC_RLShifter1 - 1))
: 18'h3FFFF; //Set RLoad
if (i_DC_Con1[23] == 1'b0) begin //Select PMU if (i_DC_Con1[23] == 1'b0) begin //Select PMU
PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con1[9:1]/8); if ((Channel_1 < 1) || (Channel_1 > 256)) begin
DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con1[9:1]/8); err_flag <= 1'b1;
end
else begin
PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter1);
DMM_en <= (19'b000_0000_0000_0000_0001)<<(DMM_Shifter1);
end
end end
else if (i_DC_Con1[23] == 1'b1) begin //Select DPS else if (i_DC_Con1[23] == 1'b1) begin //Select DPS
//Sanity Check
if ((Channel_1 < 1) || (Channel_1 > 32)) begin
err_flag <= 1'b1;
end
else begin
DPS_FS_1 <= ~(32'b1 << ( Channel_1 - 1));
DPS_FSMC <= 4'b1110;
DPS_FSMMC <= 6'b10_1110;
DPSFS_RC1 <= 1'b0;
end
end end
end end
end end
4'b0010: begin 4'b0010: begin
if (i_DC_Con2[22] == 1'b1) begin if (i_DC_Con2[22] == 1'b1) begin
RC_VISel <= 1'b1; //Select Current RC_VSel <= 1'b1; //Select Current
RC_ISel <= 1'b0;
RC_LOFS <= 2'b01;
end end
else begin else begin
RC_VISel <= 1'b0; //Select Voltage RC_VSel <= 1'b0; //Select Voltage
RC_ISel <= 1'b1;
RC_LOFS <= 2'b10;
end end
//Sanity Check //Sanity Check
if ((i_DC_Con2[21:17] < 1) || (i_DC_Con2[21:17] > 18) || (i_DC_Con2[9:1] < 1) || (i_DC_Con2[9:1] > 256)) begin if ((i_DC_Con2[21:17] < 1) || (i_DC_Con2[21:17] > 18)) begin
err_flag <= 1'b1; err_flag <= 1'b1;
end end
else begin else begin
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con2[21:17] - 1); RC_RLSel <= (RC_RLShifter2 >= 1 && RC_RLShifter2 <= 18)
? ~(18'b1 << (RC_RLShifter2 - 1))
: 18'h3FFFF; // 否则�1（即不置 0�
if (i_DC_Con2[23] == 1'b0) begin //Select PMU if (i_DC_Con2[23] == 1'b0) begin //Select PMU
PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con2[9:1]/8); if ((i_DC_Con2[9:1] < 1) || (i_DC_Con2[9:1] > 256)) begin
DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con2[9:1]/8); err_flag <= 1'b1;
end
else begin
PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter2);
DMM_en <= (19'b000_0000_0000_0001_0000)<<(DMM_Shifter2);
end
end end
else if (i_DC_Con2[23] == 1'b1) begin //Select DPS else if (i_DC_Con2[23] == 1'b1) begin //Select DPS
//Sanity Check
if ((Channel_2 < 1) || (Channel_2 > 32)) begin
err_flag <= 1'b1;
end
else begin
DPS_FS_2 <= ~(32'b1 << ( Channel_2 - 1));
DPS_FSMC <= 4'b1101;
DPS_FSMMC <= 6'b10_1101;
DPSFS_RC1 <= 1'b0;
end
end end
end end
end end
4'b0100:begin 4'b0100:begin
if (i_DC_Con3[22] == 1'b1) begin if (i_DC_Con3[22] == 1'b1) begin
RC_VISel <= 1'b1; //Select Current RC_VSel <= 1'b1; //Select Current
RC_ISel <= 1'b0;
RC_LOFS <= 2'b01;
end end
else begin else begin
RC_VISel <= 1'b0; //Select Voltage RC_VSel <= 1'b0; //Select Voltage
RC_ISel <= 1'b1;
RC_LOFS <= 2'b10;
end end
//Sanity Check //Sanity Check
if ((i_DC_Con3[21:17] < 1) || (i_DC_Con3[21:17] > 18) || (i_DC_Con3[9:1] < 1) || (i_DC_Con3[9:1] > 256)) begin if ((i_DC_Con3[21:17] < 1) || (i_DC_Con3[21:17] > 18)) begin
err_flag <= 1'b1; err_flag <= 1'b1;
end end
else begin else begin
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con3[21:17] - 1); RC_RLSel <= (RC_RLShifter3 >= 1 && RC_RLShifter3 <= 18)
? ~(18'b1 << (RC_RLShifter3 - 1))
: 18'h3FFFF; // 否则�1（即不置 0�
if (i_DC_Con3[23] == 1'b0) begin //Select PMU if (i_DC_Con3[23] == 1'b0) begin //Select PMU
PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con3[9:1]/8); if ((i_DC_Con3[9:1] < 1) || (i_DC_Con3[9:1] > 256)) begin
DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con3[9:1]/8); err_flag <= 1'b1;
end
else begin
PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter3);
DMM_en <= (19'b000_0000_0001_0000_0000)<<(DMM_Shifter3);
end
end end
else if (i_DC_Con3[23] == 1'b1) begin //Select DPS else if (i_DC_Con3[23] == 1'b1) begin //Select DPS
//Sanity Check
if ((Channel_3 < 1) || (Channel_3 > 32)) begin
err_flag <= 1'b1;
end
else begin
DPS_FS_3 <= ~(32'b1 << ( Channel_3 - 1));
DPS_FSMC <= 4'b1011;
DPS_FSMMC <= 6'b01_1011;
DPSFS_RC1 <= 1'b0;
end
end end
end end
end end
4'b1000:begin 4'b1000:begin
if (i_DC_Con4[22] == 1'b1) begin if (i_DC_Con4[22] == 1'b1) begin
RC_VISel <= 1'b1; //Select Current RC_VSel <= 1'b1; //Select Current
RC_ISel <= 1'b0;
RC_LOFS <= 2'b01;
end end
else begin else begin
RC_VISel <= 1'b0; //Select Voltage RC_VSel <= 1'b0; //Select Voltage
RC_ISel <= 1'b1;
RC_LOFS <= 2'b10;
end end
//Sanity Check //Sanity Check
if ((i_DC_Con4[21:17] < 1) || (i_DC_Con4[21:17] > 18) || (i_DC_Con4[9:1] < 1) || (i_DC_Con4[9:1] > 256)) begin if ((i_DC_Con4[21:17] < 1) || (i_DC_Con4[21:17] > 18)) begin
err_flag <= 1'b1; err_flag <= 1'b1;
end end
else begin else begin
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con4[21:17] - 1); RC_RLSel <= (RC_RLShifter4 >= 1 && RC_RLShifter4 <= 18)
? ~(18'b1 << (RC_RLShifter4 - 1))
: 18'h3FFFF; // 否则�1（即不置 0�
if (i_DC_Con4[23] == 1'b0) begin //Select PMU if (i_DC_Con4[23] == 1'b0) begin //Select PMU
PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con4[9:1]/8); if ((i_DC_Con4[9:1] < 1) || (i_DC_Con4[9:1] > 256)) begin
DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con4[9:1]/8); err_flag <= 1'b1;
end
else begin
//Parsing Channel
//We need Speacial Handling for tthe "freq" channels
if (Channel_4 == 'd66 || Channel_4 == 'd68) begin
RC_Tx <= 'd1;
end
else if (Channel_4 == 'd70 || Channel_4 == 'd72) begin
RC_Tx <= 6'b00_0010;
end
else if (Channel_4 == 'd130 || Channel_4 == 'd132) begin
RC_Tx <= 6'b00_0100;
end
else if (Channel_4 == 'd134 || Channel_4 == 'd136) begin
RC_Tx <= 6'b00_1000;
end
else if (Channel_4 == 'd194 || Channel_4 == 'd196) begin
RC_Tx <= 6'b01_0000;
end
else if (Channel_4 == 'd198 || Channel_4 == 'd200) begin
RC_Tx <= 6'b10_0000;
end
else begin
RC_Tx <= 'd0;
end
PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter4);
DMM_en <= (19'b000_0001_0000_0000_0000)<<(DMM_Shifter4);
end
end end
else if (i_DC_Con4[23] == 1'b1) begin //Select DPS else if (i_DC_Con4[23] == 1'b1) begin //Select DPS
//Sanity Check
if ((Channel_4 < 1) || (Channel_4 > 32)) begin
err_flag <= 1'b1;
end
else begin
DPS_FS_4 <= ~(32'b1 << ( Channel_4 - 1));
DPS_FSMC <= 4'b0111;
DPS_FSMMC <= 6'b01_0111;
DPSFS_RC1 <= 1'b0;
end
end end
end end
end end
default:begin // You Should NOT be HERE default:begin // You Should NOT be HERE
RC_VISel <='d0; RC_VSel <= 'd1;
RC_RLSel <='d0; RC_ISel <= 'd1;
RC_RLSel <= 'hf;
RC_LOFS <= 'hf;
PMU_OC_1 <= 'd0 ; PMU_OC_1 <= 'd0 ;
PMU_OC_2 <= 'd0 ; PMU_OC_2 <= 'd0 ;
PMU_OC_3 <= 'd0 ; PMU_OC_3 <= 'd0 ;
PMU_OC_4 <= 'd0 ; PMU_OC_4 <= 'd0 ;
DMM_en <= 'd0; DMM_en <= 'd0;
//DPS Switches LOW Enable
DPS_FS_1 <= 32'hFFFFFFFF;
DPS_FS_2 <= 32'hFFFFFFFF;
DPS_FS_3 <= 32'hFFFFFFFF;
DPS_FS_4 <= 32'hFFFFFFFF;
DPS_FSMC <= 4'b1111;
DPS_FSMMC <= 6'b11_1111;
DPSFS_RC1 <= 1'b1;
end end
endcase endcase
end end
@@ -355,15 +517,16 @@ module CPLD_Con (
end end
assign o_con_done = done_flag; assign o_con_done = done_flag;
assign o_DMM_EN = DMM_en;
assign o_OC_x01 = OC_x01;
assign o_OC_x17 = OC_x17;
assign o_IO_RC1 = io_RC;
assign o_err = err_flag; assign o_err = err_flag;
assign o_DMM_EN = DMM_en;
assign o_IO_RC1 = io_RC;
assign o_RC_Tx = RC_Tx; assign o_RC_Tx = RC_Tx;
assign o_RC_ISel = (RC_VISel==1'b1)?1:0; assign o_RC_VSel = RC_VSel;
assign o_RC_VSel = (RC_VISel==1'b1)?0:1; assign o_RC_ISel = RC_ISel;
assign o_RC_LOFS = RC_LOFS;
assign o_RC_RLSel = RC_RLSel; assign o_RC_RLSel = RC_RLSel;
@@ -372,5 +535,14 @@ module CPLD_Con (
assign o_PMU_OC_3 = PMU_OC_3; assign o_PMU_OC_3 = PMU_OC_3;
assign o_PMU_OC_4 = PMU_OC_4; assign o_PMU_OC_4 = PMU_OC_4;
assign o_DPS_FS_1 = DPS_FS_1[15:0];
assign o_DPS_FS_2 = DPS_FS_2[15:0];
assign o_DPS_FS_3 = DPS_FS_3[15:0];
assign o_DPS_FS_4 = DPS_FS_4[15:0];
assign o_DPS_FSMC = DPS_FSMC;
assign o_DPS_FSMMC = DPS_FSMMC;
assign o_DPSFS_RC1 = DPSFS_RC1;
endmodule endmodule
CPLD1/NewExtIns_CPLD1.ldf
+7 -4
View File
@@ -15,19 +15,19 @@
<Source name="tb_RelayConTop.sv" type="Verilog" type_short="Verilog" syn_sim="SimOnly"> <Source name="tb_RelayConTop.sv" type="Verilog" type_short="Verilog" syn_sim="SimOnly">
<Options VerilogStandard="System Verilog"/> <Options VerilogStandard="System Verilog"/>
</Source> </Source>
<Source name="RelayConTop_tf.v" type="Verilog" type_short="Verilog" syn_sim="SimOnly">
<Options/>
</Source>
<Source name="CPLD_Con.v" type="Verilog" type_short="Verilog"> <Source name="CPLD_Con.v" type="Verilog" type_short="Verilog">
<Options/> <Options/>
</Source> </Source>
<Source name="tb_SPI_RegRW.sv" type="Verilog" type_short="Verilog" syn_sim="SimOnly">
<Options VerilogStandard="System Verilog"/>
</Source>
<Source name="CPLD1_Debug.rva" type="Reveal Analyzer Project File" type_short="RVA"> <Source name="CPLD1_Debug.rva" type="Reveal Analyzer Project File" type_short="RVA">
<Options/> <Options/>
</Source> </Source>
<Source name="NewExtIns_CPLD1.lpf" type="Logic Preference" type_short="LPF"> <Source name="NewExtIns_CPLD1.lpf" type="Logic Preference" type_short="LPF">
<Options/> <Options/>
</Source> </Source>
<Source name="debug.rvl" type="Reveal" type_short="Reveal" excluded="TRUE"> <Source name="debug.rvl" type="Reveal" type_short="Reveal">
<Options/> <Options/>
</Source> </Source>
<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming"> <Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
@@ -36,6 +36,9 @@
<Source name="tb_RelayConTop/tb_RelayConTop.spf" type="Simulation Project File" type_short="SPF"> <Source name="tb_RelayConTop/tb_RelayConTop.spf" type="Simulation Project File" type_short="SPF">
<Options/> <Options/>
</Source> </Source>
<Source name="tb_SPI_RegRW/tb_SPI_RegRW.spf" type="Simulation Project File" type_short="SPF">
<Options/>
</Source>
</Implementation> </Implementation>
<Strategy name="Strategy1" file="NewExtInsRelay1.sty"/> <Strategy name="Strategy1" file="NewExtInsRelay1.sty"/>
</BaliProject> </BaliProject>
CPLD1/NewExtIns_CPLD1.lpf
+441 -198
View File
@@ -1,3 +1,9 @@
rvl_alias "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk";
@@ -21,22 +27,22 @@ IOBUF PORT "o_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ;
IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "i_sys_clk" DRIVE=NA IO_TYPE=LVCMOS33 SLEWRATE=NA PULLMODE=DOWN ; IOBUF PORT "i_sys_clk" DRIVE=NA IO_TYPE=LVCMOS33 SLEWRATE=NA PULLMODE=DOWN ;
IOBUF PORT "o_err" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_err" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DMM_EN[0]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_DMM_EN[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DMM_EN[1]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_DMM_EN[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DMM_EN[2]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_DMM_EN[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DMM_EN[3]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_DMM_EN[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DMM_EN[4]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_DMM_EN[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DMM_EN[5]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_DMM_EN[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DMM_EN[6]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_DMM_EN[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DMM_EN[7]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_DMM_EN[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DMM_EN[8]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_DMM_EN[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DMM_EN[9]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_DMM_EN[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DMM_EN[10]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_DMM_EN[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DMM_EN[11]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_DMM_EN[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DMM_EN[12]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_DMM_EN[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DMM_EN[13]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_DMM_EN[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DMM_EN[14]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_DMM_EN[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DMM_EN[15]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_DMM_EN[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
LOCATE COMP "o_DMM_EN[3]" SITE "C17" ; LOCATE COMP "o_DMM_EN[3]" SITE "C17" ;
LOCATE COMP "o_DMM_EN[4]" SITE "AB10" ; LOCATE COMP "o_DMM_EN[4]" SITE "AB10" ;
LOCATE COMP "o_DMM_EN[5]" SITE "AA11" ; LOCATE COMP "o_DMM_EN[5]" SITE "AA11" ;
@@ -51,7 +57,7 @@ LOCATE COMP "o_DMM_EN[13]" SITE "V12" ;
LOCATE COMP "o_DMM_EN[14]" SITE "Y12" ; LOCATE COMP "o_DMM_EN[14]" SITE "Y12" ;
LOCATE COMP "o_DMM_EN[15]" SITE "V13" ; LOCATE COMP "o_DMM_EN[15]" SITE "V13" ;
LOCATE COMP "o_IO_RC1" SITE "F10" ; LOCATE COMP "o_IO_RC1" SITE "F10" ;
IOBUF PORT "o_IO_RC1" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_IO_RC1" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
BLOCK JTAGPATHS ; BLOCK JTAGPATHS ;
LOCATE COMP "o_PMU_OC_1[0]" SITE "M19" ; LOCATE COMP "o_PMU_OC_1[0]" SITE "M19" ;
LOCATE COMP "o_PMU_OC_1[1]" SITE "R16" ; LOCATE COMP "o_PMU_OC_1[1]" SITE "R16" ;
@@ -61,14 +67,14 @@ LOCATE COMP "o_PMU_OC_1[4]" SITE "G19" ;
LOCATE COMP "o_PMU_OC_1[5]" SITE "J19" ; LOCATE COMP "o_PMU_OC_1[5]" SITE "J19" ;
LOCATE COMP "o_PMU_OC_1[6]" SITE "H16" ; LOCATE COMP "o_PMU_OC_1[6]" SITE "H16" ;
LOCATE COMP "o_PMU_OC_1[7]" SITE "J17" ; LOCATE COMP "o_PMU_OC_1[7]" SITE "J17" ;
LOCATE COMP "o_PMU_OC_1[16]" SITE "W6" ; LOCATE COMP "o_PMU_OC_1[8]" SITE "W6" ;
LOCATE COMP "o_PMU_OC_1[17]" SITE "AA7" ; LOCATE COMP "o_PMU_OC_1[9]" SITE "AA7" ;
LOCATE COMP "o_PMU_OC_1[18]" SITE "AB6" ; LOCATE COMP "o_PMU_OC_1[10]" SITE "AB6" ;
LOCATE COMP "o_PMU_OC_1[19]" SITE "Y7" ; LOCATE COMP "o_PMU_OC_1[11]" SITE "Y7" ;
LOCATE COMP "o_PMU_OC_1[20]" SITE "V4" ; LOCATE COMP "o_PMU_OC_1[12]" SITE "V4" ;
LOCATE COMP "o_PMU_OC_1[21]" SITE "R6" ; LOCATE COMP "o_PMU_OC_1[13]" SITE "R6" ;
LOCATE COMP "o_PMU_OC_1[22]" SITE "U4" ; LOCATE COMP "o_PMU_OC_1[14]" SITE "U4" ;
LOCATE COMP "o_PMU_OC_1[23]" SITE "T5" ; LOCATE COMP "o_PMU_OC_1[15]" SITE "T5" ;
LOCATE COMP "o_PMU_OC_2[0]" SITE "E16" ; LOCATE COMP "o_PMU_OC_2[0]" SITE "E16" ;
LOCATE COMP "o_PMU_OC_2[1]" SITE "F16" ; LOCATE COMP "o_PMU_OC_2[1]" SITE "F16" ;
LOCATE COMP "o_PMU_OC_2[2]" SITE "D16" ; LOCATE COMP "o_PMU_OC_2[2]" SITE "D16" ;
@@ -77,29 +83,30 @@ LOCATE COMP "o_PMU_OC_2[4]" SITE "C22" ;
LOCATE COMP "o_PMU_OC_2[5]" SITE "D20" ; LOCATE COMP "o_PMU_OC_2[5]" SITE "D20" ;
LOCATE COMP "o_PMU_OC_2[6]" SITE "D21" ; LOCATE COMP "o_PMU_OC_2[6]" SITE "D21" ;
LOCATE COMP "o_PMU_OC_2[7]" SITE "D22" ; LOCATE COMP "o_PMU_OC_2[7]" SITE "D22" ;
LOCATE COMP "o_PMU_OC_2[16]" SITE "A17" ; LOCATE COMP "o_PMU_OC_2[8]" SITE "A17" ;
LOCATE COMP "o_PMU_OC_2[17]" SITE "A18" ; LOCATE COMP "o_PMU_OC_2[9]" SITE "A18" ;
LOCATE COMP "o_PMU_OC_2[18]" SITE "C18" ; LOCATE COMP "o_PMU_OC_2[10]" SITE "C18" ;
LOCATE COMP "o_PMU_OC_2[19]" SITE "D18" ; LOCATE COMP "o_PMU_OC_2[11]" SITE "D18" ;
LOCATE COMP "o_PMU_OC_2[20]" SITE "G13" ; LOCATE COMP "o_PMU_OC_2[12]" SITE "G13" ;
LOCATE COMP "o_PMU_OC_2[21]" SITE "F15" ; LOCATE COMP "o_PMU_OC_2[13]" SITE "F15" ;
LOCATE COMP "o_PMU_OC_2[22]" SITE "F13" ; LOCATE COMP "o_PMU_OC_2[14]" SITE "F13" ;
LOCATE COMP "o_PMU_OC_2[23]" SITE "G12" ; LOCATE COMP "o_PMU_OC_2[15]" SITE "G12" ;
LOCATE COMP "o_PMU_OC_3[0]" SITE "M3" ; LOCATE COMP "o_PMU_OC_3[0]" SITE "M3" ;
LOCATE COMP "o_PMU_OC_3[1]" SITE "R1" ; LOCATE COMP "o_PMU_OC_3[1]" SITE "R1" ;
LOCATE COMP "o_PMU_OC_3[2]" SITE "N2" ; LOCATE COMP "o_PMU_OC_3[2]" SITE "N2" ;
LOCATE COMP "o_PMU_OC_3[3]" SITE "N1" ; LOCATE COMP "o_PMU_OC_3[3]" SITE "N1" ;
LOCATE COMP "o_PMU_OC_3[4]" SITE "F19" ; LOCATE COMP "o_PMU_OC_3[4]" SITE "F19" ;
LOCATE COMP "o_PMU_OC_3[5]" SITE "E19" ; LOCATE COMP "o_PMU_OC_3[5]" SITE "E19" ;
LOCATE COMP "o_PMU_OC_3[7]" SITE "B20" ;
LOCATE COMP "o_PMU_OC_3[6]" SITE "C20" ; LOCATE COMP "o_PMU_OC_3[6]" SITE "C20" ;
LOCATE COMP "o_PMU_OC_3[16]" SITE "E8" ; LOCATE COMP "o_PMU_OC_3[7]" SITE "B20" ;
LOCATE COMP "o_PMU_OC_3[17]" SITE "E9" ; LOCATE COMP "o_PMU_OC_3[8]" SITE "E8" ;
LOCATE COMP "o_PMU_OC_3[18]" SITE "E10" ; LOCATE COMP "o_PMU_OC_3[9]" SITE "E9" ;
LOCATE COMP "o_PMU_OC_3[19]" SITE "D11" ; LOCATE COMP "o_PMU_OC_3[10]" SITE "E10" ;
LOCATE COMP "o_PMU_OC_3[20]" SITE "E7" ; LOCATE COMP "o_PMU_OC_3[11]" SITE "D11" ;
LOCATE COMP "o_PMU_OC_3[21]" SITE "D8" ; LOCATE COMP "o_PMU_OC_3[12]" SITE "E7" ;
LOCATE COMP "o_PMU_OC_3[22]" SITE "B8" ; LOCATE COMP "o_PMU_OC_3[13]" SITE "D7" ;
LOCATE COMP "o_PMU_OC_3[14]" SITE "D8" ;
LOCATE COMP "o_PMU_OC_3[15]" SITE "B8" ;
LOCATE COMP "o_PMU_OC_4[0]" SITE "A13" ; LOCATE COMP "o_PMU_OC_4[0]" SITE "A13" ;
LOCATE COMP "o_PMU_OC_4[1]" SITE "B13" ; LOCATE COMP "o_PMU_OC_4[1]" SITE "B13" ;
LOCATE COMP "o_PMU_OC_4[2]" SITE "B14" ; LOCATE COMP "o_PMU_OC_4[2]" SITE "B14" ;
@@ -108,142 +115,78 @@ LOCATE COMP "o_PMU_OC_4[4]" SITE "B19" ;
LOCATE COMP "o_PMU_OC_4[5]" SITE "D12" ; LOCATE COMP "o_PMU_OC_4[5]" SITE "D12" ;
LOCATE COMP "o_PMU_OC_4[6]" SITE "E14" ; LOCATE COMP "o_PMU_OC_4[6]" SITE "E14" ;
LOCATE COMP "o_PMU_OC_4[7]" SITE "E15" ; LOCATE COMP "o_PMU_OC_4[7]" SITE "E15" ;
LOCATE COMP "o_PMU_OC_4[16]" SITE "C15" ; LOCATE COMP "o_PMU_OC_4[8]" SITE "C15" ;
LOCATE COMP "o_PMU_OC_4[17]" SITE "A16" ; LOCATE COMP "o_PMU_OC_4[9]" SITE "A16" ;
LOCATE COMP "o_PMU_OC_4[18]" SITE "B16" ; LOCATE COMP "o_PMU_OC_4[10]" SITE "B16" ;
LOCATE COMP "o_PMU_OC_4[19]" SITE "C16" ; LOCATE COMP "o_PMU_OC_4[11]" SITE "C16" ;
LOCATE COMP "o_PMU_OC_4[20]" SITE "E12" ; LOCATE COMP "o_PMU_OC_4[12]" SITE "E12" ;
LOCATE COMP "o_PMU_OC_4[21]" SITE "A21" ; LOCATE COMP "o_PMU_OC_4[13]" SITE "A21" ;
LOCATE COMP "o_PMU_OC_4[22]" SITE "B22" ; LOCATE COMP "o_PMU_OC_4[14]" SITE "B22" ;
LOCATE COMP "o_PMU_OC_4[23]" SITE "C21" ; LOCATE COMP "o_PMU_OC_4[15]" SITE "C21" ;
IOBUF PORT "o_PMU_OC_1[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ; IOBUF PORT "o_PMU_OC_1[0]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[1]" IO_TYPE=LVCMOS33 PULLMODE=DOWN DRIVE=8 ;
IOBUF PORT "o_PMU_OC_1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[2]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[3]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[4]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[5]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[6]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[7]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[8]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[9]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[10]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[11]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[12]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[13]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[14]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[15]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[0]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[1]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[2]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[3]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[4]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[5]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[6]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[7]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[8]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[9]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[10]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[11]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[12]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[13]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[14]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[15]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[0]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[1]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[2]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[3]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[4]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[5]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[6]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[7]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[8]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[9]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[10]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[11]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[12]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[13]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[14]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[15]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[0]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[1]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[2]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[3]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[4]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[5]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[6]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[7]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[8]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[9]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[10]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[11]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_3[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[12]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_3[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[13]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_3[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[14]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_3[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[15]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_3[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[0]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_PMU_OC_1[16]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_PMU_OC_2[0]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_PMU_OC_2[16]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_PMU_OC_3[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[16]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_PMU_OC_4[0]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_PMU_OC_4[16]" IO_TYPE=LVCMOS33 ;
LOCATE COMP "o_RC_RLSel[1]" SITE "M4" ; LOCATE COMP "o_RC_RLSel[1]" SITE "M4" ;
LOCATE COMP "o_RC_RLSel[2]" SITE "B10" ; LOCATE COMP "o_RC_RLSel[2]" SITE "B10" ;
LOCATE COMP "o_RC_RLSel[3]" SITE "P3" ; LOCATE COMP "o_RC_RLSel[3]" SITE "P3" ;
@@ -261,24 +204,24 @@ LOCATE COMP "o_RC_RLSel[14]" SITE "B4" ;
LOCATE COMP "o_RC_RLSel[15]" SITE "F11" ; LOCATE COMP "o_RC_RLSel[15]" SITE "F11" ;
LOCATE COMP "o_RC_RLSel[16]" SITE "D9" ; LOCATE COMP "o_RC_RLSel[16]" SITE "D9" ;
LOCATE COMP "o_RC_RLSel[17]" SITE "N5" ; LOCATE COMP "o_RC_RLSel[17]" SITE "N5" ;
IOBUF PORT "o_RC_RLSel[0]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_RLSel[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_RLSel[1]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_RLSel[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_RLSel[2]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_RLSel[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_RLSel[3]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_RLSel[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_RLSel[4]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_RLSel[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_RLSel[5]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_RLSel[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_RLSel[6]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_RLSel[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_RLSel[7]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_RLSel[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_RLSel[8]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_RLSel[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_RLSel[9]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_RLSel[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_RLSel[10]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_RLSel[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_RLSel[11]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_RLSel[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_RLSel[12]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_RLSel[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_RLSel[13]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_RLSel[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_RLSel[14]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_RLSel[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_RLSel[15]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_RLSel[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_RLSel[16]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_RLSel[16]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_RLSel[17]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_RLSel[17]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
LOCATE COMP "o_RC_LOF[0]" SITE "F3" ; LOCATE COMP "o_RC_LOF[0]" SITE "F3" ;
LOCATE COMP "o_RC_LOF[1]" SITE "H4" ; LOCATE COMP "o_RC_LOF[1]" SITE "H4" ;
LOCATE COMP "o_RC_LOS[0]" SITE "G4" ; LOCATE COMP "o_RC_LOS[0]" SITE "G4" ;
@@ -293,9 +236,9 @@ LOCATE COMP "o_RC_VSel" SITE "L7" ;
IOBUF PORT "o_RC_VSel" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_VSel" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_ISel" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_ISel" IO_TYPE=LVCMOS33 ;
LOCATE COMP "o_DMM_EN[16]" SITE "W11" ; LOCATE COMP "o_DMM_EN[16]" SITE "W11" ;
IOBUF PORT "o_DMM_EN[16]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_DMM_EN[16]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DMM_EN[17]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_DMM_EN[17]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DMM_EN[18]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_DMM_EN[18]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
LOCATE COMP "o_DMM_EN[17]" SITE "U10" ; LOCATE COMP "o_DMM_EN[17]" SITE "U10" ;
LOCATE COMP "o_DMM_EN[18]" SITE "T10" ; LOCATE COMP "o_DMM_EN[18]" SITE "T10" ;
LOCATE COMP "o_RC_T27" SITE "U13" ; LOCATE COMP "o_RC_T27" SITE "U13" ;
@@ -311,3 +254,303 @@ IOBUF PORT "o_RC_T30" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_T31" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T31" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_T32" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T32" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_con_done" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_con_done" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DPSF_RC1" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPSS_RC1" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_FMC[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_FMC[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_FMC[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_FMC[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_FMMC[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_FMMC[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_FMMC[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_FMMC[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_FMMC[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_FMMC[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_SMC[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_SMC[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_SMC[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_SMC[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_SMMC[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_SMMC[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_SMMC[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_SMMC[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_SMMC[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_SMMC[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_DPS_F_1[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
LOCATE COMP "o_DPS_F_1[0]" SITE "V3" ;
LOCATE COMP "o_DPS_F_1[1]" SITE "W1" ;
LOCATE COMP "o_DPS_F_1[2]" SITE "Y2" ;
LOCATE COMP "o_DPS_F_1[3]" SITE "V7" ;
LOCATE COMP "o_DPS_F_1[4]" SITE "W4" ;
LOCATE COMP "o_DPS_F_1[5]" SITE "AA1" ;
LOCATE COMP "o_DPS_F_1[6]" SITE "V2" ;
LOCATE COMP "o_DPS_F_1[7]" SITE "W2" ;
LOCATE COMP "o_DPS_F_1[8]" SITE "E6" ;
LOCATE COMP "o_DPS_F_1[9]" SITE "V6" ;
LOCATE COMP "o_DPS_F_1[10]" SITE "P2" ;
LOCATE COMP "o_DPS_F_1[11]" SITE "G7" ;
LOCATE COMP "o_DPS_F_1[12]" SITE "V1" ;
LOCATE COMP "o_DPS_F_1[13]" SITE "U3" ;
LOCATE COMP "o_DPS_F_1[14]" SITE "N3" ;
LOCATE COMP "o_DPS_F_1[15]" SITE "Y8" ;
LOCATE COMP "o_DPS_F_2[0]" SITE "L16" ;
LOCATE COMP "o_DPS_F_2[1]" SITE "K17" ;
LOCATE COMP "o_DPS_F_2[2]" SITE "J21" ;
LOCATE COMP "o_DPS_F_2[3]" SITE "Y22" ;
LOCATE COMP "o_DPS_F_2[4]" SITE "G18" ;
LOCATE COMP "o_DPS_F_2[5]" SITE "H17" ;
LOCATE COMP "o_DPS_F_2[6]" SITE "M17" ;
LOCATE COMP "o_DPS_F_2[7]" SITE "L17" ;
LOCATE COMP "o_DPS_F_2[8]" SITE "T17" ;
LOCATE COMP "o_DPS_F_2[9]" SITE "W20" ;
LOCATE COMP "o_DPS_F_2[10]" SITE "J16" ;
LOCATE COMP "o_DPS_F_2[11]" SITE "J18" ;
LOCATE COMP "o_DPS_F_2[12]" SITE "P21" ;
LOCATE COMP "o_DPS_F_2[13]" SITE "R17" ;
LOCATE COMP "o_DPS_F_2[14]" SITE "N17" ;
LOCATE COMP "o_DPS_F_2[15]" SITE "M16" ;
LOCATE COMP "o_DPS_F_3[0]" SITE "F1" ;
LOCATE COMP "o_DPS_F_3[1]" SITE "J2" ;
LOCATE COMP "o_DPS_F_3[2]" SITE "H7" ;
LOCATE COMP "o_DPS_F_3[3]" SITE "C1" ;
LOCATE COMP "o_DPS_F_3[4]" SITE "C2" ;
LOCATE COMP "o_DPS_F_3[5]" SITE "B1" ;
LOCATE COMP "o_DPS_F_3[6]" SITE "J4" ;
LOCATE COMP "o_DPS_F_3[7]" SITE "K6" ;
LOCATE COMP "o_DPS_F_3[8]" SITE "H2" ;
LOCATE COMP "o_DPS_F_3[9]" SITE "D1" ;
LOCATE COMP "o_DPS_F_3[10]" SITE "C3" ;
LOCATE COMP "o_DPS_F_3[11]" SITE "E1" ;
LOCATE COMP "o_DPS_F_3[12]" SITE "K2" ;
LOCATE COMP "o_DPS_F_3[13]" SITE "H3" ;
LOCATE COMP "o_DPS_F_3[14]" SITE "L3" ;
LOCATE COMP "o_DPS_F_3[15]" SITE "G3" ;
LOCATE COMP "o_DPS_F_4[0]" SITE "E21" ;
LOCATE COMP "o_DPS_F_4[2]" SITE "R21" ;
LOCATE COMP "o_DPS_F_4[3]" SITE "R18" ;
LOCATE COMP "o_DPS_F_4[4]" SITE "N21" ;
LOCATE COMP "o_DPS_F_4[5]" SITE "R22" ;
LOCATE COMP "o_DPS_F_4[6]" SITE "P18" ;
LOCATE COMP "o_DPS_F_4[7]" SITE "N18" ;
LOCATE COMP "o_DPS_F_4[8]" SITE "P19" ;
LOCATE COMP "o_DPS_F_4[9]" SITE "M20" ;
LOCATE COMP "o_DPS_F_4[10]" SITE "M21" ;
LOCATE COMP "o_DPS_F_4[11]" SITE "L21" ;
LOCATE COMP "o_DPS_F_4[12]" SITE "L22" ;
LOCATE COMP "o_DPS_F_4[13]" SITE "E20" ;
LOCATE COMP "o_DPS_F_4[14]" SITE "G21" ;
LOCATE COMP "o_DPS_F_4[15]" SITE "G22" ;
LOCATE COMP "o_DPS_F_4[1]" SITE "R20" ;
LOCATE COMP "o_DPS_S_1[0]" SITE "L4" ;
LOCATE COMP "o_DPS_S_1[1]" SITE "W3" ;
LOCATE COMP "o_DPS_S_1[2]" SITE "U6" ;
LOCATE COMP "o_DPS_S_1[3]" SITE "U5" ;
LOCATE COMP "o_DPS_S_1[4]" SITE "J3" ;
LOCATE COMP "o_DPS_S_1[5]" SITE "T7" ;
LOCATE COMP "o_DPS_S_1[6]" SITE "W5" ;
LOCATE COMP "o_DPS_S_1[7]" SITE "U8" ;
LOCATE COMP "o_DPS_S_1[8]" SITE "Y1" ;
LOCATE COMP "o_DPS_S_1[9]" SITE "M2" ;
LOCATE COMP "o_DPS_S_1[10]" SITE "M7" ;
LOCATE COMP "o_DPS_S_1[11]" SITE "M5" ;
LOCATE COMP "o_DPS_S_1[12]" SITE "U7" ;
LOCATE COMP "o_DPS_S_1[13]" SITE "L1" ;
LOCATE COMP "o_DPS_S_1[14]" SITE "L2" ;
LOCATE COMP "o_DPS_S_1[15]" SITE "L5" ;
LOCATE COMP "o_DPS_S_2[0]" SITE "T19" ;
LOCATE COMP "o_DPS_S_2[1]" SITE "R19" ;
LOCATE COMP "o_DPS_S_2[2]" SITE "V22" ;
LOCATE COMP "o_DPS_S_2[3]" SITE "M18" ;
LOCATE COMP "o_DPS_S_2[4]" SITE "U19" ;
LOCATE COMP "o_DPS_S_2[5]" SITE "N16" ;
LOCATE COMP "o_DPS_S_2[6]" SITE "G16" ;
LOCATE COMP "o_DPS_S_2[7]" SITE "K16" ;
LOCATE COMP "o_DPS_S_2[8]" SITE "K18" ;
LOCATE COMP "o_DPS_S_2[9]" SITE "V17" ;
LOCATE COMP "o_DPS_S_2[10]" SITE "U22" ;
LOCATE COMP "o_DPS_S_2[11]" SITE "U17" ;
LOCATE COMP "o_DPS_S_2[12]" SITE "G17" ;
LOCATE COMP "o_DPS_S_2[13]" SITE "T20" ;
LOCATE COMP "o_DPS_S_2[14]" SITE "T16" ;
LOCATE COMP "o_DPS_S_2[15]" SITE "V21" ;
LOCATE COMP "o_DPS_S_3[0]" SITE "R2" ;
LOCATE COMP "o_DPS_S_3[1]" SITE "M1" ;
LOCATE COMP "o_DPS_S_3[2]" SITE "K7" ;
LOCATE COMP "o_DPS_S_3[3]" SITE "D3" ;
LOCATE COMP "o_DPS_S_3[4]" SITE "G2" ;
LOCATE COMP "o_DPS_S_3[5]" SITE "G1" ;
LOCATE COMP "o_DPS_S_3[6]" SITE "K1" ;
LOCATE COMP "o_DPS_S_3[7]" SITE "K3" ;
LOCATE COMP "o_DPS_S_3[8]" SITE "H5" ;
LOCATE COMP "o_DPS_S_3[9]" SITE "K5" ;
LOCATE COMP "o_DPS_S_3[10]" SITE "T4" ;
LOCATE COMP "o_DPS_S_3[11]" SITE "H1" ;
LOCATE COMP "o_DPS_S_3[12]" SITE "R3" ;
LOCATE COMP "o_DPS_S_3[13]" SITE "J5" ;
LOCATE COMP "o_DPS_S_3[14]" SITE "E2" ;
LOCATE COMP "o_DPS_S_3[15]" SITE "H6" ;
LOCATE COMP "o_DPS_S_4[0]" SITE "F20" ;
LOCATE COMP "o_DPS_S_4[1]" SITE "AA22" ;
LOCATE COMP "o_DPS_S_4[2]" SITE "M22" ;
LOCATE COMP "o_DPS_S_4[3]" SITE "T21" ;
LOCATE COMP "o_DPS_S_4[4]" SITE "N22" ;
LOCATE COMP "o_DPS_S_4[5]" SITE "Y20" ;
LOCATE COMP "o_DPS_S_4[6]" SITE "T22" ;
LOCATE COMP "o_DPS_S_4[7]" SITE "K21" ;
LOCATE COMP "o_DPS_S_4[8]" SITE "E22" ;
LOCATE COMP "o_DPS_S_4[9]" SITE "T18" ;
LOCATE COMP "o_DPS_S_4[10]" SITE "U18" ;
LOCATE COMP "o_DPS_S_4[11]" SITE "H21" ;
LOCATE COMP "o_DPS_S_4[12]" SITE "H20" ;
LOCATE COMP "o_DPS_S_4[13]" SITE "L20" ;
LOCATE COMP "o_DPS_S_4[14]" SITE "K20" ;
LOCATE COMP "o_DPS_S_4[15]" SITE "K22" ;
LOCATE COMP "o_FMC[0]" SITE "E4" ;
LOCATE COMP "o_FMC[1]" SITE "F4" ;
LOCATE COMP "o_FMC[2]" SITE "P7" ;
LOCATE COMP "o_FMC[3]" SITE "N7" ;
LOCATE COMP "o_FMMC[0]" SITE "C11" ;
LOCATE COMP "o_FMMC[1]" SITE "A2" ;
LOCATE COMP "o_FMMC[2]" SITE "AB2" ;
LOCATE COMP "o_FMMC[3]" SITE "AA3" ;
LOCATE COMP "o_FMMC[4]" SITE "Y4" ;
LOCATE COMP "o_FMMC[5]" SITE "Y5" ;
LOCATE COMP "o_SMC[0]" SITE "G6" ;
LOCATE COMP "o_SMC[1]" SITE "G5" ;
LOCATE COMP "o_SMC[2]" SITE "R7" ;
LOCATE COMP "o_SMC[3]" SITE "T6" ;
LOCATE COMP "o_SMMC[0]" SITE "B3" ;
LOCATE COMP "o_SMMC[1]" SITE "C4" ;
LOCATE COMP "o_SMMC[2]" SITE "Y3" ;
LOCATE COMP "o_SMMC[3]" SITE "AB3" ;
LOCATE COMP "o_SMMC[4]" SITE "AA4" ;
LOCATE COMP "o_SMMC[5]" SITE "AB5" ;
LOCATE COMP "o_DPSF_RC1" SITE "C6" ;
LOCATE COMP "o_DPSS_RC1" SITE "G8" ;
CPLD1/Reg_file.v
+3 -2
View File
@@ -35,7 +35,7 @@ module Reg_file (
// --- Parameters --- // --- Parameters ---
localparam REG_COUNT = 16; localparam REG_COUNT = 16;
localparam [23:0] localparam [23:0]
IDENT = 24'h200000 | 12'b0001_0001_0000, //CPLD1==1,version=1.1.0 IDENT = 24'h200000 | 12'b0001_0001_0010, //CPLD1==1,version=1.1.2
STATE_INIT = 24'h800000; STATE_INIT = 24'h800000;
// State Machine Definition // State Machine Definition
@@ -74,7 +74,6 @@ module Reg_file (
else begin else begin
case (state) case (state)
IDLE: begin IDLE: begin
rvalid_flag <= 1'b0;
err_flag <= 1'b0; err_flag <= 1'b0;
// Priority Check: Did we crash/reset while EXEC bit was still 1? // Priority Check: Did we crash/reset while EXEC bit was still 1?
@@ -99,6 +98,7 @@ module Reg_file (
end end
BUSY: begin BUSY: begin
rvalid_flag <= 1'b0;
if (err_flag) begin if (err_flag) begin
state <= IDLE; state <= IDLE;
end end
@@ -133,6 +133,7 @@ module Reg_file (
// Wait for Controller to register the command and pull 'done' LOW (Busy) // Wait for Controller to register the command and pull 'done' LOW (Busy)
EXEC_ACK: begin EXEC_ACK: begin
busy_flag <= 1'b1; busy_flag <= 1'b1;
rvalid_flag <= 1'b0;
if (i_con_done == 1'b0) begin if (i_con_done == 1'b0) begin
state <= EXEC_WAIT; state <= EXEC_WAIT;
end end
CPLD1/RelayConTop.v
+74 -36
View File
@@ -28,10 +28,27 @@ module RelayConTop (
output [1:0]o_RC_LOF, //Strange DMM_N port relay output [1:0]o_RC_LOF, //Strange DMM_N port relay
output [1:0]o_RC_LOS, output [1:0]o_RC_LOS,
output [31:0]o_PMU_OC_1, output [3:0]o_FMC ,
output [31:0]o_PMU_OC_2, output [3:0]o_SMC ,
output [31:0]o_PMU_OC_3, output [5:0]o_FMMC ,
output [31:0]o_PMU_OC_4 output [5:0]o_SMMC ,
output o_DPSF_RC1 ,
output o_DPSS_RC1 ,
output [15:0]o_PMU_OC_1,
output [15:0]o_PMU_OC_2,
output [15:0]o_PMU_OC_3,
output [15:0]o_PMU_OC_4,
output [15:0]o_DPS_F_1 ,
output [15:0]o_DPS_S_1 ,
output [15:0]o_DPS_F_2 ,
output [15:0]o_DPS_S_2 ,
output [15:0]o_DPS_F_3 ,
output [15:0]o_DPS_S_3 ,
output [15:0]o_DPS_F_4 ,
output [15:0]o_DPS_S_4
); );
wire [3:0]OC_x01; wire [3:0]OC_x01;
@@ -71,6 +88,19 @@ module RelayConTop (
wire [31:0]PMU_OC_3 ; wire [31:0]PMU_OC_3 ;
wire [31:0]PMU_OC_4 ; wire [31:0]PMU_OC_4 ;
//DPS PerChannel Force/Sense Control
wire [15:0]DPS_FS_1 ;
wire [15:0]DPS_FS_2 ;
wire [15:0]DPS_FS_3 ;
wire [15:0]DPS_FS_4 ;
//DPS Level Control
wire [3:0]FSMC ;
wire [5:0]FSMMC ;
//DPS Output Control
wire DPSFS_RC1 ;
//RL Control //RL Control
wire [17:0]RC_RLSel ; wire [17:0]RC_RLSel ;
@@ -79,6 +109,9 @@ module RelayConTop (
//DMM I Select //DMM I Select
wire RC_ISel; wire RC_ISel;
//Force/Sense Control
wire [1:0]RC_LOFS ;
wire con_rvalid; wire con_rvalid;
wire con_done; wire con_done;
@@ -139,62 +172,67 @@ module RelayConTop (
.i_DC_Con3(DC_Con3), .i_DC_Con3(DC_Con3),
.i_DC_Con4(DC_Con4), .i_DC_Con4(DC_Con4),
.o_con_done(con_done), .o_con_done(con_done),
.o_OC_x01(OC_x01),
.o_OC_x17(OC_x17),
.o_RC_Tx(RC_Tx), .o_RC_Tx(RC_Tx),
.o_DMM_EN(DMM_EN), .o_DMM_EN(DMM_EN),
.o_PMU_OC_1(PMU_OC_1), .o_PMU_OC_1(PMU_OC_1),
.o_PMU_OC_2(PMU_OC_2), .o_PMU_OC_2(PMU_OC_2),
.o_PMU_OC_3(PMU_OC_3), .o_PMU_OC_3(PMU_OC_3),
.o_PMU_OC_4(PMU_OC_4), .o_PMU_OC_4(PMU_OC_4),
.o_DPS_FS_1(DPS_FS_1),
.o_DPS_FS_2(DPS_FS_2),
.o_DPS_FS_3(DPS_FS_3),
.o_DPS_FS_4(DPS_FS_4),
.o_DPS_FSMC(FSMC),
.o_DPS_FSMMC(FSMMC),
.o_DPSFS_RC1(DPSFS_RC1),
.o_RC_VSel(RC_VSel), .o_RC_VSel(RC_VSel),
.o_RC_ISel(RC_ISel), .o_RC_ISel(RC_ISel),
.o_RC_LOFS(RC_LOFS),
.o_RC_RLSel(RC_RLSel), .o_RC_RLSel(RC_RLSel),
.o_IO_RC1(IO_RC1), .o_IO_RC1(IO_RC1),
.o_err(cpld_err_flag) .o_err(cpld_err_flag)
); );
assign o_con_done = con_done; assign o_con_done = con_done;
//assign o_OC_x01 = OC_x01;
assign o_PMU_OC_1[0] = OC_x01[0];
assign o_PMU_OC_2[0] = OC_x01[1];
assign o_PMU_OC_3[0] = OC_x01[2];
assign o_PMU_OC_4[0] = OC_x01[3];
//assign o_OC_x17 = OC_x17; //Low on PIO resource, we need to only set pins this CPLD handles
assign o_PMU_OC_1[16] = OC_x17[0]; assign o_PMU_OC_1 = {PMU_OC_1[23:16],PMU_OC_1[7:0]};
assign o_PMU_OC_2[16] = OC_x17[1]; assign o_PMU_OC_2 = {PMU_OC_2[23:16],PMU_OC_2[7:0]};
assign o_PMU_OC_3[16] = OC_x17[2]; assign o_PMU_OC_3 = {PMU_OC_3[23:16],PMU_OC_3[7:0]};
assign o_PMU_OC_4[16] = OC_x17[3]; assign o_PMU_OC_4 = {PMU_OC_4[23:16],PMU_OC_4[7:0]};
assign o_PMU_OC_1[15:1] = PMU_OC_1[15:1];
assign o_PMU_OC_1[31:17] = PMU_OC_1[31:17];
assign o_PMU_OC_2[15:1] = PMU_OC_2[15:1];
assign o_PMU_OC_2[31:17] = PMU_OC_2[31:17];
assign o_PMU_OC_3[15:1] = PMU_OC_3[15:1];
assign o_PMU_OC_3[31:17] = PMU_OC_3[31:17];
assign o_PMU_OC_4[15:1] = PMU_OC_4[15:1];
assign o_PMU_OC_4[31:17] = PMU_OC_4[31:17];
assign o_DMM_EN = DMM_EN; assign o_DMM_EN = DMM_EN;
assign o_IO_RC1 = IO_RC1; assign o_IO_RC1 = IO_RC1;
assign o_RC_T27 = RC_Tx[5]; assign o_RC_T27 = RC_Tx[0];
assign o_RC_T28 = RC_Tx[4]; assign o_RC_T28 = RC_Tx[1];
assign o_RC_T29 = RC_Tx[3]; assign o_RC_T29 = RC_Tx[2];
assign o_RC_T30 = RC_Tx[2]; assign o_RC_T30 = RC_Tx[3];
assign o_RC_T31 = RC_Tx[1]; assign o_RC_T31 = RC_Tx[4];
assign o_RC_T32 = RC_Tx[0]; assign o_RC_T32 = RC_Tx[5];
assign o_RC_RLSel = RC_RLSel; assign o_RC_RLSel = RC_RLSel;
assign o_RC_VSel = RC_VSel; assign o_RC_VSel = RC_VSel;
assign o_RC_ISel = RC_ISel; assign o_RC_ISel = RC_ISel;
assign o_RC_LOF = (RC_VSel == 1'b1)?2'b01:2'b10; //if Measure V then close RC_LOF[0] assign o_RC_LOF = RC_LOFS;
assign o_RC_LOS = (RC_VSel == 1'b1)?2'b01:2'b10; assign o_RC_LOS = RC_LOFS;
assign o_DPS_F_1 = DPS_FS_1;
assign o_DPS_S_1 = DPS_FS_1;
assign o_DPS_F_2 = DPS_FS_2;
assign o_DPS_S_2 = DPS_FS_2;
assign o_DPS_F_3 = DPS_FS_3;
assign o_DPS_S_3 = DPS_FS_3;
assign o_DPS_F_4 = DPS_FS_4;
assign o_DPS_S_4 = DPS_FS_4;
assign o_FMC = FSMC ;
assign o_SMC = FSMC ;
assign o_FMMC = FSMMC ;
assign o_SMMC = FSMMC ;
assign o_DPSF_RC1 = DPSFS_RC1 ;
assign o_DPSS_RC1 = DPSFS_RC1 ;
assign o_err = bus_err_flag || reg_err_flag ||cpld_err_flag; assign o_err = bus_err_flag || reg_err_flag ||cpld_err_flag;
CPLD1/debug.rvl
+159 -132
View File
@@ -1,10 +1,10 @@
<Project ModBy="Inserter" SigType="0" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/debug.rvl" Date="2026-05-26"> <Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/debug.rvl" Date="2026-06-16">
<IP Version="1_6_042617"/> <IP Version="1_6_042617"/>
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD1"/> <Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD1"/>
<Core InsertDataset="0" Insert="1" Reveal_sig="695532518" Name="RelayConTop_LA0" ID="0"> <Core InsertDataset="0" Insert="1" Reveal_sig="698409536" Name="RelayConTop_LA0" ID="0">
<Setting> <Setting>
<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/> <Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/> <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="1024"/>
<Capture Mode="0" MinSamplesPerTrig="8"/> <Capture Mode="0" MinSamplesPerTrig="8"/>
<Event CntEnable="0" MaxEventCnt="8"/> <Event CntEnable="0" MaxEventCnt="8"/>
<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_RelayConTop_LA0_net"/> <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_RelayConTop_LA0_net"/>
@@ -12,142 +12,169 @@
</Setting> </Setting>
<Dataset Name="Base"> <Dataset Name="Base">
<Trace> <Trace>
<Sig Type="SIG" Name="BUS_Con_1/i_cs"/> <Bus Name="DPS_FS_1">
<Sig Type="SIG" Name="BUS_Con_1/i_mosi"/> <Sig Type="SIG" Name="DPS_FS_1:0"/>
<Sig Type="SIG" Name="BUS_Con_1/i_sclk"/> <Sig Type="SIG" Name="DPS_FS_1:1"/>
<Bus Name="o_DMM_EN"> <Sig Type="SIG" Name="DPS_FS_1:2"/>
<Sig Type="SIG" Name="o_DMM_EN:0"/> <Sig Type="SIG" Name="DPS_FS_1:3"/>
<Sig Type="SIG" Name="o_DMM_EN:1"/> <Sig Type="SIG" Name="DPS_FS_1:4"/>
<Sig Type="SIG" Name="o_DMM_EN:2"/> <Sig Type="SIG" Name="DPS_FS_1:5"/>
<Sig Type="SIG" Name="o_DMM_EN:3"/> <Sig Type="SIG" Name="DPS_FS_1:6"/>
<Sig Type="SIG" Name="o_DMM_EN:4"/> <Sig Type="SIG" Name="DPS_FS_1:7"/>
<Sig Type="SIG" Name="o_DMM_EN:5"/> <Sig Type="SIG" Name="DPS_FS_1:8"/>
<Sig Type="SIG" Name="o_DMM_EN:6"/> <Sig Type="SIG" Name="DPS_FS_1:9"/>
<Sig Type="SIG" Name="o_DMM_EN:7"/> <Sig Type="SIG" Name="DPS_FS_1:10"/>
<Sig Type="SIG" Name="o_DMM_EN:8"/> <Sig Type="SIG" Name="DPS_FS_1:11"/>
<Sig Type="SIG" Name="o_DMM_EN:9"/> <Sig Type="SIG" Name="DPS_FS_1:12"/>
<Sig Type="SIG" Name="o_DMM_EN:10"/> <Sig Type="SIG" Name="DPS_FS_1:13"/>
<Sig Type="SIG" Name="o_DMM_EN:11"/> <Sig Type="SIG" Name="DPS_FS_1:14"/>
<Sig Type="SIG" Name="o_DMM_EN:12"/> <Sig Type="SIG" Name="DPS_FS_1:15"/>
<Sig Type="SIG" Name="o_DMM_EN:13"/>
<Sig Type="SIG" Name="o_DMM_EN:14"/>
<Sig Type="SIG" Name="o_DMM_EN:15"/>
</Bus> </Bus>
<Sig Type="SIG" Name="o_IO_RC1"/> <Bus Name="DPS_FS_2">
<Sig Type="SIG" Name="BUS_Con_1/err_flag"/> <Sig Type="SIG" Name="DPS_FS_2:0"/>
<Sig Type="SIG" Name="CPLD_Con_1/err_flag"/> <Sig Type="SIG" Name="DPS_FS_2:1"/>
<Sig Type="SIG" Name="CPLD_Reg_1/err_flag"/> <Sig Type="SIG" Name="DPS_FS_2:2"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_con_exec"/> <Sig Type="SIG" Name="DPS_FS_2:3"/>
<Bus Name="CPLD_Con_1/i_DC_Con1"> <Sig Type="SIG" Name="DPS_FS_2:4"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:0"/> <Sig Type="SIG" Name="DPS_FS_2:5"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:1"/> <Sig Type="SIG" Name="DPS_FS_2:6"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:2"/> <Sig Type="SIG" Name="DPS_FS_2:7"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:3"/> <Sig Type="SIG" Name="DPS_FS_2:8"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:4"/> <Sig Type="SIG" Name="DPS_FS_2:9"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:5"/> <Sig Type="SIG" Name="DPS_FS_2:10"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:6"/> <Sig Type="SIG" Name="DPS_FS_2:11"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:7"/> <Sig Type="SIG" Name="DPS_FS_2:12"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:8"/> <Sig Type="SIG" Name="DPS_FS_2:13"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:9"/> <Sig Type="SIG" Name="DPS_FS_2:14"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:10"/> <Sig Type="SIG" Name="DPS_FS_2:15"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:11"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:12"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:13"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:14"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:15"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:16"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:17"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:18"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:19"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:20"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:21"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:22"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:23"/>
</Bus> </Bus>
<Bus Name="CPLD_Con_1/i_DC_Con2"> <Bus Name="DPS_FS_3">
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:0"/> <Sig Type="SIG" Name="DPS_FS_3:0"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:1"/> <Sig Type="SIG" Name="DPS_FS_3:1"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:2"/> <Sig Type="SIG" Name="DPS_FS_3:2"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:3"/> <Sig Type="SIG" Name="DPS_FS_3:3"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:4"/> <Sig Type="SIG" Name="DPS_FS_3:4"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:5"/> <Sig Type="SIG" Name="DPS_FS_3:5"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:6"/> <Sig Type="SIG" Name="DPS_FS_3:6"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:7"/> <Sig Type="SIG" Name="DPS_FS_3:7"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:8"/> <Sig Type="SIG" Name="DPS_FS_3:8"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:9"/> <Sig Type="SIG" Name="DPS_FS_3:9"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:10"/> <Sig Type="SIG" Name="DPS_FS_3:10"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:11"/> <Sig Type="SIG" Name="DPS_FS_3:11"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:12"/> <Sig Type="SIG" Name="DPS_FS_3:12"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:13"/> <Sig Type="SIG" Name="DPS_FS_3:13"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:14"/> <Sig Type="SIG" Name="DPS_FS_3:14"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:15"/> <Sig Type="SIG" Name="DPS_FS_3:15"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:16"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:17"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:18"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:19"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:20"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:21"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:22"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:23"/>
</Bus> </Bus>
<Bus Name="CPLD_Con_1/i_DC_Con3"> <Bus Name="DPS_FS_4">
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:0"/> <Sig Type="SIG" Name="DPS_FS_4:0"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:1"/> <Sig Type="SIG" Name="DPS_FS_4:1"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:2"/> <Sig Type="SIG" Name="DPS_FS_4:2"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:3"/> <Sig Type="SIG" Name="DPS_FS_4:3"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:4"/> <Sig Type="SIG" Name="DPS_FS_4:4"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:5"/> <Sig Type="SIG" Name="DPS_FS_4:5"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:6"/> <Sig Type="SIG" Name="DPS_FS_4:6"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:7"/> <Sig Type="SIG" Name="DPS_FS_4:7"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:8"/> <Sig Type="SIG" Name="DPS_FS_4:8"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:9"/> <Sig Type="SIG" Name="DPS_FS_4:9"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:10"/> <Sig Type="SIG" Name="DPS_FS_4:10"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:11"/> <Sig Type="SIG" Name="DPS_FS_4:11"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:12"/> <Sig Type="SIG" Name="DPS_FS_4:12"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:13"/> <Sig Type="SIG" Name="DPS_FS_4:13"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:14"/> <Sig Type="SIG" Name="DPS_FS_4:14"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:15"/> <Sig Type="SIG" Name="DPS_FS_4:15"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:16"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:17"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:18"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:19"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:20"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:21"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:22"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:23"/>
</Bus> </Bus>
<Bus Name="CPLD_Con_1/i_DC_Con4"> <Bus Name="FSMC">
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:0"/> <Sig Type="SIG" Name="FSMC:0"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:1"/> <Sig Type="SIG" Name="FSMC:1"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:2"/> <Sig Type="SIG" Name="FSMC:2"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:3"/> <Sig Type="SIG" Name="FSMC:3"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:4"/> </Bus>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:5"/> <Bus Name="FSMMC">
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:6"/> <Sig Type="SIG" Name="FSMMC:0"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:7"/> <Sig Type="SIG" Name="FSMMC:1"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:8"/> <Sig Type="SIG" Name="FSMMC:2"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:9"/> <Sig Type="SIG" Name="FSMMC:3"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:10"/> <Sig Type="SIG" Name="FSMMC:4"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:11"/> <Sig Type="SIG" Name="FSMMC:5"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:12"/> </Bus>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:13"/> <Sig Type="SIG" Name="DPSFS_RC1"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:14"/> <Bus Name="o_PMU_OC_1">
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:15"/> <Sig Type="SIG" Name="o_PMU_OC_1:0"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:16"/> <Sig Type="SIG" Name="o_PMU_OC_1:1"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:17"/> <Sig Type="SIG" Name="o_PMU_OC_1:2"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:18"/> <Sig Type="SIG" Name="o_PMU_OC_1:3"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:19"/> <Sig Type="SIG" Name="o_PMU_OC_1:4"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:20"/> <Sig Type="SIG" Name="o_PMU_OC_1:5"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:21"/> <Sig Type="SIG" Name="o_PMU_OC_1:6"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:22"/> <Sig Type="SIG" Name="o_PMU_OC_1:7"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:23"/> <Sig Type="SIG" Name="o_PMU_OC_1:8"/>
<Sig Type="SIG" Name="o_PMU_OC_1:9"/>
<Sig Type="SIG" Name="o_PMU_OC_1:10"/>
<Sig Type="SIG" Name="o_PMU_OC_1:11"/>
<Sig Type="SIG" Name="o_PMU_OC_1:12"/>
<Sig Type="SIG" Name="o_PMU_OC_1:13"/>
<Sig Type="SIG" Name="o_PMU_OC_1:14"/>
<Sig Type="SIG" Name="o_PMU_OC_1:15"/>
</Bus>
<Bus Name="o_PMU_OC_2">
<Sig Type="SIG" Name="o_PMU_OC_2:0"/>
<Sig Type="SIG" Name="o_PMU_OC_2:1"/>
<Sig Type="SIG" Name="o_PMU_OC_2:2"/>
<Sig Type="SIG" Name="o_PMU_OC_2:3"/>
<Sig Type="SIG" Name="o_PMU_OC_2:4"/>
<Sig Type="SIG" Name="o_PMU_OC_2:5"/>
<Sig Type="SIG" Name="o_PMU_OC_2:6"/>
<Sig Type="SIG" Name="o_PMU_OC_2:7"/>
<Sig Type="SIG" Name="o_PMU_OC_2:8"/>
<Sig Type="SIG" Name="o_PMU_OC_2:9"/>
<Sig Type="SIG" Name="o_PMU_OC_2:10"/>
<Sig Type="SIG" Name="o_PMU_OC_2:11"/>
<Sig Type="SIG" Name="o_PMU_OC_2:12"/>
<Sig Type="SIG" Name="o_PMU_OC_2:13"/>
<Sig Type="SIG" Name="o_PMU_OC_2:14"/>
<Sig Type="SIG" Name="o_PMU_OC_2:15"/>
</Bus>
<Bus Name="o_PMU_OC_3">
<Sig Type="SIG" Name="o_PMU_OC_3:0"/>
<Sig Type="SIG" Name="o_PMU_OC_3:1"/>
<Sig Type="SIG" Name="o_PMU_OC_3:2"/>
<Sig Type="SIG" Name="o_PMU_OC_3:3"/>
<Sig Type="SIG" Name="o_PMU_OC_3:4"/>
<Sig Type="SIG" Name="o_PMU_OC_3:5"/>
<Sig Type="SIG" Name="o_PMU_OC_3:6"/>
<Sig Type="SIG" Name="o_PMU_OC_3:7"/>
<Sig Type="SIG" Name="o_PMU_OC_3:8"/>
<Sig Type="SIG" Name="o_PMU_OC_3:9"/>
<Sig Type="SIG" Name="o_PMU_OC_3:10"/>
<Sig Type="SIG" Name="o_PMU_OC_3:11"/>
<Sig Type="SIG" Name="o_PMU_OC_3:12"/>
<Sig Type="SIG" Name="o_PMU_OC_3:13"/>
<Sig Type="SIG" Name="o_PMU_OC_3:14"/>
<Sig Type="SIG" Name="o_PMU_OC_3:15"/>
</Bus>
<Bus Name="o_PMU_OC_4">
<Sig Type="SIG" Name="o_PMU_OC_4:0"/>
<Sig Type="SIG" Name="o_PMU_OC_4:1"/>
<Sig Type="SIG" Name="o_PMU_OC_4:2"/>
<Sig Type="SIG" Name="o_PMU_OC_4:3"/>
<Sig Type="SIG" Name="o_PMU_OC_4:4"/>
<Sig Type="SIG" Name="o_PMU_OC_4:5"/>
<Sig Type="SIG" Name="o_PMU_OC_4:6"/>
<Sig Type="SIG" Name="o_PMU_OC_4:7"/>
<Sig Type="SIG" Name="o_PMU_OC_4:8"/>
<Sig Type="SIG" Name="o_PMU_OC_4:9"/>
<Sig Type="SIG" Name="o_PMU_OC_4:10"/>
<Sig Type="SIG" Name="o_PMU_OC_4:11"/>
<Sig Type="SIG" Name="o_PMU_OC_4:12"/>
<Sig Type="SIG" Name="o_PMU_OC_4:13"/>
<Sig Type="SIG" Name="o_PMU_OC_4:14"/>
<Sig Type="SIG" Name="o_PMU_OC_4:15"/>
</Bus> </Bus>
</Trace> </Trace>
<Trigger> <Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="i_cs,"/> <TU Serialbits="0" Type="0" ID="1" Sig="con_exec,"/>
<TU Serialbits="0" Type="0" ID="2" Sig="i_sclk,"/> <TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
</Trigger> </Trigger>
</Dataset> </Dataset>
</Core> </Core>
CPLD1/debug.rvs
+159 -132
View File
@@ -1,148 +1,175 @@
<Project ModBy="Inserter" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/debug.rvl" Date="2026-05-26"> <Project ModBy="Inserter" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/debug.rvl" Date="2026-06-16">
<Core Name="RelayConTop_LA0"> <Core Name="RelayConTop_LA0">
<Setting> <Setting>
<Capture SamplesPerTrig="2048" NumTrigsCap="1"/> <Capture SamplesPerTrig="1" NumTrigsCap=""/>
<Event EventCnt="0" CntEnableRun="0"/> <Event EventCnt="" CntEnableRun=""/>
<TrigSetting PreTrgSamples="" AND_ALL="0" PostTrgSamples="" TURadix="0"/> <TrigSetting PreTrgSamples="" AND_ALL="" PostTrgSamples="" TURadix="0"/>
</Setting> </Setting>
<Dataset Name="Base"> <Dataset Name="Base">
<Trace> <Trace>
<Sig Name="BUS_Con_1/i_cs"/> <Bus Name="DPS_FS_1" Radix="0">
<Sig Name="BUS_Con_1/i_mosi"/> <Sig Name="DPS_FS_1:0"/>
<Sig Name="BUS_Con_1/i_sclk"/> <Sig Name="DPS_FS_1:1"/>
<Bus Name="o_DMM_EN" Radix="0"> <Sig Name="DPS_FS_1:2"/>
<Sig Name="o_DMM_EN:0"/> <Sig Name="DPS_FS_1:3"/>
<Sig Name="o_DMM_EN:1"/> <Sig Name="DPS_FS_1:4"/>
<Sig Name="o_DMM_EN:2"/> <Sig Name="DPS_FS_1:5"/>
<Sig Name="o_DMM_EN:3"/> <Sig Name="DPS_FS_1:6"/>
<Sig Name="o_DMM_EN:4"/> <Sig Name="DPS_FS_1:7"/>
<Sig Name="o_DMM_EN:5"/> <Sig Name="DPS_FS_1:8"/>
<Sig Name="o_DMM_EN:6"/> <Sig Name="DPS_FS_1:9"/>
<Sig Name="o_DMM_EN:7"/> <Sig Name="DPS_FS_1:10"/>
<Sig Name="o_DMM_EN:8"/> <Sig Name="DPS_FS_1:11"/>
<Sig Name="o_DMM_EN:9"/> <Sig Name="DPS_FS_1:12"/>
<Sig Name="o_DMM_EN:10"/> <Sig Name="DPS_FS_1:13"/>
<Sig Name="o_DMM_EN:11"/> <Sig Name="DPS_FS_1:14"/>
<Sig Name="o_DMM_EN:12"/> <Sig Name="DPS_FS_1:15"/>
<Sig Name="o_DMM_EN:13"/>
<Sig Name="o_DMM_EN:14"/>
<Sig Name="o_DMM_EN:15"/>
</Bus> </Bus>
<Sig Name="o_IO_RC1"/> <Bus Name="DPS_FS_2" Radix="0">
<Sig Name="BUS_Con_1/err_flag"/> <Sig Name="DPS_FS_2:0"/>
<Sig Name="CPLD_Con_1/err_flag"/> <Sig Name="DPS_FS_2:1"/>
<Sig Name="CPLD_Reg_1/err_flag"/> <Sig Name="DPS_FS_2:2"/>
<Sig Name="CPLD_Con_1/i_con_exec"/> <Sig Name="DPS_FS_2:3"/>
<Bus Name="CPLD_Con_1/i_DC_Con1" Radix="0"> <Sig Name="DPS_FS_2:4"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:0"/> <Sig Name="DPS_FS_2:5"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:1"/> <Sig Name="DPS_FS_2:6"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:2"/> <Sig Name="DPS_FS_2:7"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:3"/> <Sig Name="DPS_FS_2:8"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:4"/> <Sig Name="DPS_FS_2:9"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:5"/> <Sig Name="DPS_FS_2:10"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:6"/> <Sig Name="DPS_FS_2:11"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:7"/> <Sig Name="DPS_FS_2:12"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:8"/> <Sig Name="DPS_FS_2:13"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:9"/> <Sig Name="DPS_FS_2:14"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:10"/> <Sig Name="DPS_FS_2:15"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:11"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:12"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:13"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:14"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:15"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:16"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:17"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:18"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:19"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:20"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:21"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:22"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:23"/>
</Bus> </Bus>
<Bus Name="CPLD_Con_1/i_DC_Con2" Radix="0"> <Bus Name="DPS_FS_3" Radix="0">
<Sig Name="CPLD_Con_1/i_DC_Con2:0"/> <Sig Name="DPS_FS_3:0"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:1"/> <Sig Name="DPS_FS_3:1"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:2"/> <Sig Name="DPS_FS_3:2"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:3"/> <Sig Name="DPS_FS_3:3"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:4"/> <Sig Name="DPS_FS_3:4"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:5"/> <Sig Name="DPS_FS_3:5"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:6"/> <Sig Name="DPS_FS_3:6"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:7"/> <Sig Name="DPS_FS_3:7"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:8"/> <Sig Name="DPS_FS_3:8"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:9"/> <Sig Name="DPS_FS_3:9"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:10"/> <Sig Name="DPS_FS_3:10"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:11"/> <Sig Name="DPS_FS_3:11"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:12"/> <Sig Name="DPS_FS_3:12"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:13"/> <Sig Name="DPS_FS_3:13"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:14"/> <Sig Name="DPS_FS_3:14"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:15"/> <Sig Name="DPS_FS_3:15"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:16"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:17"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:18"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:19"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:20"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:21"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:22"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:23"/>
</Bus> </Bus>
<Bus Name="CPLD_Con_1/i_DC_Con3" Radix="0"> <Bus Name="DPS_FS_4" Radix="0">
<Sig Name="CPLD_Con_1/i_DC_Con3:0"/> <Sig Name="DPS_FS_4:0"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:1"/> <Sig Name="DPS_FS_4:1"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:2"/> <Sig Name="DPS_FS_4:2"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:3"/> <Sig Name="DPS_FS_4:3"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:4"/> <Sig Name="DPS_FS_4:4"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:5"/> <Sig Name="DPS_FS_4:5"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:6"/> <Sig Name="DPS_FS_4:6"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:7"/> <Sig Name="DPS_FS_4:7"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:8"/> <Sig Name="DPS_FS_4:8"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:9"/> <Sig Name="DPS_FS_4:9"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:10"/> <Sig Name="DPS_FS_4:10"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:11"/> <Sig Name="DPS_FS_4:11"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:12"/> <Sig Name="DPS_FS_4:12"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:13"/> <Sig Name="DPS_FS_4:13"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:14"/> <Sig Name="DPS_FS_4:14"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:15"/> <Sig Name="DPS_FS_4:15"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:16"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:17"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:18"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:19"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:20"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:21"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:22"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:23"/>
</Bus> </Bus>
<Bus Name="CPLD_Con_1/i_DC_Con4" Radix="0"> <Bus Name="FSMC" Radix="0">
<Sig Name="CPLD_Con_1/i_DC_Con4:0"/> <Sig Name="FSMC:0"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:1"/> <Sig Name="FSMC:1"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:2"/> <Sig Name="FSMC:2"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:3"/> <Sig Name="FSMC:3"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:4"/> </Bus>
<Sig Name="CPLD_Con_1/i_DC_Con4:5"/> <Bus Name="FSMMC" Radix="0">
<Sig Name="CPLD_Con_1/i_DC_Con4:6"/> <Sig Name="FSMMC:0"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:7"/> <Sig Name="FSMMC:1"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:8"/> <Sig Name="FSMMC:2"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:9"/> <Sig Name="FSMMC:3"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:10"/> <Sig Name="FSMMC:4"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:11"/> <Sig Name="FSMMC:5"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:12"/> </Bus>
<Sig Name="CPLD_Con_1/i_DC_Con4:13"/> <Sig Name="DPSFS_RC1"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:14"/> <Bus Name="o_PMU_OC_1" Radix="0">
<Sig Name="CPLD_Con_1/i_DC_Con4:15"/> <Sig Name="o_PMU_OC_1:0"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:16"/> <Sig Name="o_PMU_OC_1:1"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:17"/> <Sig Name="o_PMU_OC_1:2"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:18"/> <Sig Name="o_PMU_OC_1:3"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:19"/> <Sig Name="o_PMU_OC_1:4"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:20"/> <Sig Name="o_PMU_OC_1:5"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:21"/> <Sig Name="o_PMU_OC_1:6"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:22"/> <Sig Name="o_PMU_OC_1:7"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:23"/> <Sig Name="o_PMU_OC_1:8"/>
<Sig Name="o_PMU_OC_1:9"/>
<Sig Name="o_PMU_OC_1:10"/>
<Sig Name="o_PMU_OC_1:11"/>
<Sig Name="o_PMU_OC_1:12"/>
<Sig Name="o_PMU_OC_1:13"/>
<Sig Name="o_PMU_OC_1:14"/>
<Sig Name="o_PMU_OC_1:15"/>
</Bus>
<Bus Name="o_PMU_OC_2" Radix="0">
<Sig Name="o_PMU_OC_2:0"/>
<Sig Name="o_PMU_OC_2:1"/>
<Sig Name="o_PMU_OC_2:2"/>
<Sig Name="o_PMU_OC_2:3"/>
<Sig Name="o_PMU_OC_2:4"/>
<Sig Name="o_PMU_OC_2:5"/>
<Sig Name="o_PMU_OC_2:6"/>
<Sig Name="o_PMU_OC_2:7"/>
<Sig Name="o_PMU_OC_2:8"/>
<Sig Name="o_PMU_OC_2:9"/>
<Sig Name="o_PMU_OC_2:10"/>
<Sig Name="o_PMU_OC_2:11"/>
<Sig Name="o_PMU_OC_2:12"/>
<Sig Name="o_PMU_OC_2:13"/>
<Sig Name="o_PMU_OC_2:14"/>
<Sig Name="o_PMU_OC_2:15"/>
</Bus>
<Bus Name="o_PMU_OC_3" Radix="0">
<Sig Name="o_PMU_OC_3:0"/>
<Sig Name="o_PMU_OC_3:1"/>
<Sig Name="o_PMU_OC_3:2"/>
<Sig Name="o_PMU_OC_3:3"/>
<Sig Name="o_PMU_OC_3:4"/>
<Sig Name="o_PMU_OC_3:5"/>
<Sig Name="o_PMU_OC_3:6"/>
<Sig Name="o_PMU_OC_3:7"/>
<Sig Name="o_PMU_OC_3:8"/>
<Sig Name="o_PMU_OC_3:9"/>
<Sig Name="o_PMU_OC_3:10"/>
<Sig Name="o_PMU_OC_3:11"/>
<Sig Name="o_PMU_OC_3:12"/>
<Sig Name="o_PMU_OC_3:13"/>
<Sig Name="o_PMU_OC_3:14"/>
<Sig Name="o_PMU_OC_3:15"/>
</Bus>
<Bus Name="o_PMU_OC_4" Radix="0">
<Sig Name="o_PMU_OC_4:0"/>
<Sig Name="o_PMU_OC_4:1"/>
<Sig Name="o_PMU_OC_4:2"/>
<Sig Name="o_PMU_OC_4:3"/>
<Sig Name="o_PMU_OC_4:4"/>
<Sig Name="o_PMU_OC_4:5"/>
<Sig Name="o_PMU_OC_4:6"/>
<Sig Name="o_PMU_OC_4:7"/>
<Sig Name="o_PMU_OC_4:8"/>
<Sig Name="o_PMU_OC_4:9"/>
<Sig Name="o_PMU_OC_4:10"/>
<Sig Name="o_PMU_OC_4:11"/>
<Sig Name="o_PMU_OC_4:12"/>
<Sig Name="o_PMU_OC_4:13"/>
<Sig Name="o_PMU_OC_4:14"/>
<Sig Name="o_PMU_OC_4:15"/>
</Bus> </Bus>
</Trace> </Trace>
<Trigger> <Trigger>
<TU Operator="7" Name="TU1" ID="1" Value="0" Radix="0"/> <TU Operator="6" Name="TU1" ID="1" Value="0" Radix="0"/>
<TU Operator="6" Name="TU2" ID="2" Value="0" Radix="0"/>
<TE Enable="1" Expression="TU1" Name="TE1" ID="1"/> <TE Enable="1" Expression="TU1" Name="TE1" ID="1"/>
<TE Enable="1" Expression="TU2" Name="TE2" ID="2"/>
</Trigger> </Trigger>
</Dataset> </Dataset>
</Core> </Core>
CPLD1/impl1/NewExtIns_CPLD1_impl1.areasrr
-81
View File
@@ -1,81 +0,0 @@
----------------------------------------------------------------------
Report for cell RelayConTop.verilog
Register bits: 769 of 6864 (11%)
PIC Latch: 0
I/O cells: 187
Cell usage:
cell count Res Usage(%)
FD1P3AX 419 100.0
FD1P3AY 4 100.0
FD1P3IX 148 100.0
FD1P3JX 1 100.0
FD1S3AX 16 100.0
FD1S3IX 14 100.0
FD1S3JX 1 100.0
GSR 1 100.0
IB 5 100.0
IFS1P3IX 3 100.0
IFS1P3JX 1 100.0
INV 2 100.0
L6MUX21 72 100.0
OB 181 100.0
OBZ 1 100.0
OFS1P3DX 36 100.0
OFS1P3IX 126 100.0
ORCALUT4 747 100.0
PFUMX 104 100.0
PUR 1 100.0
VHI 4 100.0
VLO 4 100.0
SUB MODULES
BUS_Con 1 100.0
CPLD_Con 1 100.0
Reg_file 1 100.0
TOTAL 1894
----------------------------------------------------------------------
Report for cell CPLD_Con.netlist
Instance path: CPLD_Con_1
Cell usage:
cell count Res Usage(%)
FD1P3IX 18 12.2
FD1P3JX 1 100.0
FD1S3AX 12 75.0
FD1S3IX 5 35.7
INV 1 50.0
ORCALUT4 441 59.0
PFUMX 8 7.7
VHI 1 25.0
VLO 1 25.0
TOTAL 488
----------------------------------------------------------------------
Report for cell Reg_file.netlist
Instance path: CPLD_Reg_1
Cell usage:
cell count Res Usage(%)
FD1P3AX 419 100.0
FD1P3AY 4 100.0
FD1S3AX 2 12.5
L6MUX21 72 100.0
ORCALUT4 239 32.0
PFUMX 96 92.3
VHI 1 25.0
VLO 1 25.0
TOTAL 834
----------------------------------------------------------------------
Report for cell BUS_Con.netlist
Instance path: BUS_Con_1
Cell usage:
cell count Res Usage(%)
FD1P3IX 130 87.8
FD1S3AX 2 12.5
FD1S3IX 9 64.3
FD1S3JX 1 100.0
ORCALUT4 67 9.0
VHI 1 25.0
VLO 1 25.0
TOTAL 211
CPLD1/impl1/NewExtIns_CPLD1_impl1.bit
BIN
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Binary file not shown.
CPLD1/impl1/NewExtIns_CPLD1_impl1.jed
+3846 -3760
View File
File diff suppressed because it is too large Load Diff
CPLD1/impl1/NewExtIns_CPLD1_impl1.pt
-10
View File
@@ -1,10 +0,0 @@
-v
10
-gt
-sethld
-sp 4
-sphld m
CPLD1/impl1/NewExtIns_CPLD1_impl1_map.cam
-135
View File
@@ -1,135 +0,0 @@
[ START MERGED ]
i_rst_n_c_i i_rst_n_c
CPLD_Con_1/g0_26_x1 DC_Con3[21]
[ END MERGED ]
[ START CLIPPED ]
GND
VCC
[ END CLIPPED ]
[ START DESIGN PREFS ]
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.14.0.75.2 -- WARNING: Map write only section -- Tue May 26 15:47:46 2026
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "o_miso" SITE "AA14" ;
LOCATE COMP "i_sys_clk" SITE "B9" ;
LOCATE COMP "o_PMU_OC_4[23]" SITE "C21" ;
LOCATE COMP "o_PMU_OC_4[22]" SITE "B22" ;
LOCATE COMP "o_PMU_OC_4[21]" SITE "A21" ;
LOCATE COMP "o_PMU_OC_4[20]" SITE "E12" ;
LOCATE COMP "o_PMU_OC_4[19]" SITE "C16" ;
LOCATE COMP "o_PMU_OC_4[18]" SITE "B16" ;
LOCATE COMP "o_PMU_OC_4[17]" SITE "A16" ;
LOCATE COMP "o_PMU_OC_4[16]" SITE "C15" ;
LOCATE COMP "o_PMU_OC_4[7]" SITE "E15" ;
LOCATE COMP "o_PMU_OC_4[6]" SITE "E14" ;
LOCATE COMP "o_PMU_OC_4[5]" SITE "D12" ;
LOCATE COMP "o_PMU_OC_4[4]" SITE "B19" ;
LOCATE COMP "o_PMU_OC_4[3]" SITE "B15" ;
LOCATE COMP "o_PMU_OC_4[2]" SITE "B14" ;
LOCATE COMP "o_PMU_OC_4[1]" SITE "B13" ;
LOCATE COMP "o_PMU_OC_4[0]" SITE "A13" ;
LOCATE COMP "o_PMU_OC_3[22]" SITE "B8" ;
LOCATE COMP "o_PMU_OC_3[21]" SITE "D8" ;
LOCATE COMP "o_PMU_OC_3[20]" SITE "E7" ;
LOCATE COMP "o_PMU_OC_3[19]" SITE "D11" ;
LOCATE COMP "o_PMU_OC_3[18]" SITE "E10" ;
LOCATE COMP "o_PMU_OC_3[17]" SITE "E9" ;
LOCATE COMP "o_PMU_OC_3[16]" SITE "E8" ;
LOCATE COMP "o_PMU_OC_3[7]" SITE "B20" ;
LOCATE COMP "o_PMU_OC_3[6]" SITE "C20" ;
LOCATE COMP "o_PMU_OC_3[5]" SITE "E19" ;
LOCATE COMP "o_PMU_OC_3[4]" SITE "F19" ;
LOCATE COMP "o_PMU_OC_3[3]" SITE "N1" ;
LOCATE COMP "o_PMU_OC_3[2]" SITE "N2" ;
LOCATE COMP "o_PMU_OC_3[1]" SITE "R1" ;
LOCATE COMP "o_PMU_OC_3[0]" SITE "M3" ;
LOCATE COMP "o_PMU_OC_2[23]" SITE "G12" ;
LOCATE COMP "o_PMU_OC_2[22]" SITE "F13" ;
LOCATE COMP "o_PMU_OC_2[21]" SITE "F15" ;
LOCATE COMP "o_PMU_OC_2[20]" SITE "G13" ;
LOCATE COMP "o_PMU_OC_2[19]" SITE "D18" ;
LOCATE COMP "o_PMU_OC_2[18]" SITE "C18" ;
LOCATE COMP "o_PMU_OC_2[17]" SITE "A18" ;
LOCATE COMP "o_PMU_OC_2[16]" SITE "A17" ;
LOCATE COMP "o_PMU_OC_2[7]" SITE "D22" ;
LOCATE COMP "o_PMU_OC_2[6]" SITE "D21" ;
LOCATE COMP "o_PMU_OC_2[5]" SITE "D20" ;
LOCATE COMP "o_PMU_OC_2[4]" SITE "C22" ;
LOCATE COMP "o_PMU_OC_2[3]" SITE "G15" ;
LOCATE COMP "o_PMU_OC_2[2]" SITE "D16" ;
LOCATE COMP "o_PMU_OC_2[1]" SITE "F16" ;
LOCATE COMP "o_PMU_OC_2[0]" SITE "E16" ;
LOCATE COMP "o_PMU_OC_1[23]" SITE "T5" ;
LOCATE COMP "o_PMU_OC_1[22]" SITE "U4" ;
LOCATE COMP "o_PMU_OC_1[21]" SITE "R6" ;
LOCATE COMP "o_PMU_OC_1[20]" SITE "V4" ;
LOCATE COMP "o_PMU_OC_1[19]" SITE "Y7" ;
LOCATE COMP "o_PMU_OC_1[18]" SITE "AB6" ;
LOCATE COMP "o_PMU_OC_1[17]" SITE "AA7" ;
LOCATE COMP "o_PMU_OC_1[16]" SITE "W6" ;
LOCATE COMP "o_PMU_OC_1[7]" SITE "J17" ;
LOCATE COMP "o_PMU_OC_1[6]" SITE "H16" ;
LOCATE COMP "o_PMU_OC_1[5]" SITE "J19" ;
LOCATE COMP "o_PMU_OC_1[4]" SITE "G19" ;
LOCATE COMP "o_PMU_OC_1[3]" SITE "P20" ;
LOCATE COMP "o_PMU_OC_1[2]" SITE "N20" ;
LOCATE COMP "o_PMU_OC_1[1]" SITE "R16" ;
LOCATE COMP "o_PMU_OC_1[0]" SITE "M19" ;
LOCATE COMP "o_RC_LOS[1]" SITE "L6" ;
LOCATE COMP "o_RC_LOS[0]" SITE "G4" ;
LOCATE COMP "o_RC_LOF[1]" SITE "H4" ;
LOCATE COMP "o_RC_LOF[0]" SITE "F3" ;
LOCATE COMP "o_RC_ISel" SITE "P6" ;
LOCATE COMP "o_RC_VSel" SITE "L7" ;
LOCATE COMP "o_RC_RLSel[17]" SITE "N5" ;
LOCATE COMP "o_RC_RLSel[16]" SITE "D9" ;
LOCATE COMP "o_RC_RLSel[15]" SITE "F11" ;
LOCATE COMP "o_RC_RLSel[14]" SITE "B4" ;
LOCATE COMP "o_RC_RLSel[13]" SITE "A5" ;
LOCATE COMP "o_RC_RLSel[12]" SITE "B11" ;
LOCATE COMP "o_RC_RLSel[11]" SITE "A3" ;
LOCATE COMP "o_RC_RLSel[10]" SITE "C5" ;
LOCATE COMP "o_RC_RLSel[9]" SITE "F8" ;
LOCATE COMP "o_RC_RLSel[8]" SITE "B7" ;
LOCATE COMP "o_RC_RLSel[7]" SITE "C8" ;
LOCATE COMP "o_RC_RLSel[6]" SITE "F6" ;
LOCATE COMP "o_RC_RLSel[5]" SITE "G10" ;
LOCATE COMP "o_RC_RLSel[4]" SITE "F5" ;
LOCATE COMP "o_RC_RLSel[3]" SITE "P3" ;
LOCATE COMP "o_RC_RLSel[2]" SITE "B10" ;
LOCATE COMP "o_RC_RLSel[1]" SITE "M4" ;
LOCATE COMP "o_RC_RLSel[0]" SITE "M6" ;
LOCATE COMP "o_RC_T32" SITE "V11" ;
LOCATE COMP "o_RC_T31" SITE "U11" ;
LOCATE COMP "o_RC_T30" SITE "T11" ;
LOCATE COMP "o_RC_T29" SITE "T12" ;
LOCATE COMP "o_RC_T28" SITE "U12" ;
LOCATE COMP "o_RC_T27" SITE "U13" ;
LOCATE COMP "o_IO_RC1" SITE "F10" ;
LOCATE COMP "o_DMM_EN[18]" SITE "T10" ;
LOCATE COMP "o_DMM_EN[17]" SITE "U10" ;
LOCATE COMP "o_DMM_EN[16]" SITE "W11" ;
LOCATE COMP "o_DMM_EN[15]" SITE "V13" ;
LOCATE COMP "o_DMM_EN[14]" SITE "Y12" ;
LOCATE COMP "o_DMM_EN[13]" SITE "V12" ;
LOCATE COMP "o_DMM_EN[12]" SITE "W12" ;
LOCATE COMP "o_DMM_EN[11]" SITE "F12" ;
LOCATE COMP "o_DMM_EN[10]" SITE "C13" ;
LOCATE COMP "o_DMM_EN[9]" SITE "D14" ;
LOCATE COMP "o_DMM_EN[8]" SITE "D15" ;
LOCATE COMP "o_DMM_EN[7]" SITE "AB13" ;
LOCATE COMP "o_DMM_EN[6]" SITE "AA12" ;
LOCATE COMP "o_DMM_EN[5]" SITE "AA11" ;
LOCATE COMP "o_DMM_EN[4]" SITE "AB10" ;
LOCATE COMP "o_DMM_EN[3]" SITE "C17" ;
LOCATE COMP "o_DMM_EN[2]" SITE "D17" ;
LOCATE COMP "o_DMM_EN[1]" SITE "E17" ;
LOCATE COMP "o_DMM_EN[0]" SITE "F17" ;
LOCATE COMP "o_err" SITE "AB16" ;
LOCATE COMP "i_cs" SITE "AB11" ;
LOCATE COMP "i_mosi" SITE "AB12" ;
LOCATE COMP "i_sclk" SITE "AA10" ;
LOCATE COMP "i_rst_n" SITE "Y14" ;
SCHEMATIC END ;
[ END DESIGN PREFS ]
CPLD1/impl1/NewExtIns_CPLD1_impl1_map.hrr
-40
View File
@@ -1,40 +0,0 @@
---------------------------------------------------
Report for cell RelayConTop
Instance path: RelayConTop
Cell usage:
cell count Res Usage(%)
SLIC 401.00 100.0
IOLGC 165.00 100.0
LUT4 747.00 100.0
IOREG 165 100.0
IOBUF 187 100.0
PFUREG 604 100.0
SUB MODULES
cell count SLC Usage(%)
Reg_file 1 53.8
CPLD_Con 1 31.0
BUS_Con 1 15.1
---------------------------------------------------
Report for cell CPLD_Con
Instance path: RelayConTop/CPLD_Con_1
Cell usage:
cell count Res Usage(%)
SLIC 124.30 31.0
LUT4 441.00 59.0
PFUREG 36 6.0
---------------------------------------------------
Report for cell Reg_file
Instance path: RelayConTop/CPLD_Reg_1
Cell usage:
cell count Res Usage(%)
SLIC 215.78 53.8
LUT4 239.00 32.0
PFUREG 425 70.4
---------------------------------------------------
Report for cell BUS_Con
Instance path: RelayConTop/BUS_Con_1
Cell usage:
cell count Res Usage(%)
SLIC 60.58 15.1
LUT4 67.00 9.0
PFUREG 142 23.5
CPLD1/impl1/NewExtIns_CPLD1_impl1_mapvo.vo
+59589 -19603
View File
File diff suppressed because it is too large Load Diff
CPLD1/impl1/NewExtIns_CPLD1_impl1_synplify.lpf
+6 -1
View File
@@ -1,8 +1,9 @@
# #
# Logical Preferences generated for Lattice by Synplify map202309lat, Build 191R. # Logical Preferences generated for Lattice by Synplify map202303lat, Build 132R.
# #
# Period Constraints # Period Constraints
#FREQUENCY NET "RelayConTop_reveal_coretop_instance/jtck[0]" 200.0 MHz;
#FREQUENCY PORT "i_sys_clk" 200.0 MHz; #FREQUENCY PORT "i_sys_clk" 200.0 MHz;
@@ -15,6 +16,10 @@
# Block Path Constraints # Block Path Constraints
#BLOCK PATH FROM CLKNET "i_sys_clk_c" TO CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]";
#BLOCK PATH FROM CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]" TO CLKNET "i_sys_clk_c";
#BLOCK PATH FROM CLKNET "i_sys_clk_c" TO CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]";
#BLOCK PATH FROM CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]" TO CLKNET "i_sys_clk_c";
BLOCK ASYNCPATHS; BLOCK ASYNCPATHS;
CPLD1/impl1/_cmd._cml
-1
View File
@@ -1 +0,0 @@
-link -encrypt -top RelayConTop -osyn /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/impl1/synwork/NewExtIns_CPLD1_impl1_comp.srs /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/impl1/synwork/layer0.srs -jobname linker
CPLD1/impl1/impl1.xcf
+4 -4
View File
@@ -19,9 +19,9 @@
<BScanLen>1</BScanLen> <BScanLen>1</BScanLen>
<BScanVal>0</BScanVal> <BScanVal>0</BScanVal>
</Bypass> </Bypass>
<File>D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/impl1/NewExtIns_CPLD1_impl1.jed</File> <File>C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/impl1/NewExtIns_CPLD1_impl1.jed</File>
<FileTime>01/19/26 12:45:04</FileTime> <FileTime>06/04/26 14:18:11</FileTime>
<JedecChecksum>0x75FB</JedecChecksum> <JedecChecksum>0x5D88</JedecChecksum>
<Operation>FLASH Erase,Program,Verify</Operation> <Operation>FLASH Erase,Program,Verify</Operation>
<Option> <Option>
<SVFVendor>JTAG STANDARD</SVFVendor> <SVFVendor>JTAG STANDARD</SVFVendor>
@@ -47,6 +47,6 @@
<CableOptions> <CableOptions>
<CableName>USB</CableName> <CableName>USB</CableName>
<PortAdd>EzUSB-0</PortAdd> <PortAdd>EzUSB-0</PortAdd>
<USBID>\\?\usb#vid_1134&amp;amp;pid_8001#9&amp;amp;2fe42d87&amp;amp;0&amp;amp;2#</USBID> <USBID>\\?\usb#vid_1134&amp;amp;pid_8001#6&amp;amp;ca080be&amp;amp;0&amp;amp;3#</USBID>
</CableOptions> </CableOptions>
</ispXCF> </ispXCF>
CPLD1/impl1/pmi_distributed_dpramXbnoner212pb07f9c9.edn
-227
View File
@@ -1,227 +0,0 @@
(edif pmi_distributed_dpramXbnoner212pb07f9c9
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timestamp 2026 1 13 11 1 36)
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
(comment "C:/lscc/diamond/3.14/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 2 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner212pb07f9c9 -pmi ")
(library ORCLIB
(edifLevel 0)
(technology
(numberDefinition))
(cell FD1P3DX
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port D
(direction INPUT))
(port SP
(direction INPUT))
(port CK
(direction INPUT))
(port CD
(direction INPUT))
(port Q
(direction OUTPUT)))))
(cell ROM16X1A
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port AD3
(direction INPUT))
(port AD2
(direction INPUT))
(port AD1
(direction INPUT))
(port AD0
(direction INPUT))
(port DO0
(direction OUTPUT)))))
(cell DPR16X4C
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port DI0
(direction INPUT))
(port DI1
(direction INPUT))
(port DI2
(direction INPUT))
(port DI3
(direction INPUT))
(port WCK
(direction INPUT))
(port WRE
(direction INPUT))
(port RAD0
(direction INPUT))
(port RAD1
(direction INPUT))
(port RAD2
(direction INPUT))
(port RAD3
(direction INPUT))
(port WAD0
(direction INPUT))
(port WAD1
(direction INPUT))
(port WAD2
(direction INPUT))
(port WAD3
(direction INPUT))
(port DO0
(direction OUTPUT))
(port DO1
(direction OUTPUT))
(port DO2
(direction OUTPUT))
(port DO3
(direction OUTPUT)))))
(cell VHI
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port Z
(direction OUTPUT)))))
(cell pmi_distributed_dpramXbnoner212pb07f9c9
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port (array (rename WrAddress "WrAddress(0:0)") 1)
(direction INPUT))
(port (array (rename Data "Data(1:0)") 2)
(direction INPUT))
(port WrClock
(direction INPUT))
(port WE
(direction INPUT))
(port WrClockEn
(direction INPUT))
(port (array (rename RdAddress "RdAddress(0:0)") 1)
(direction INPUT))
(port RdClock
(direction INPUT))
(port RdClockEn
(direction INPUT))
(port Reset
(direction INPUT))
(port (array (rename Q "Q(1:0)") 2)
(direction OUTPUT)))
(property NGD_DRC_MASK (integer 1))
(contents
(instance LUT4_0
(viewRef view1
(cellRef ROM16X1A))
(property initval
(string "0x8000")))
(instance FF_1
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance FF_0
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance scuba_vhi_inst
(viewRef view1
(cellRef VHI)))
(instance mem_0_0
(viewRef view1
(cellRef DPR16X4C))
(property MEM_INIT_FILE
(string "(0-1)(0-1)"))
(property MEM_LPC_FILE
(string "pmi_distributed_dpramXbnoner212pb07f9c9__PMI__2__2__2B"))
(property COMP
(string "mem_0_0"))
(property initval
(string "0x0000000000000000")))
(net dataout1_ffin
(joined
(portRef DO1 (instanceRef mem_0_0))
(portRef D (instanceRef FF_1))))
(net dataout0_ffin
(joined
(portRef DO0 (instanceRef mem_0_0))
(portRef D (instanceRef FF_0))))
(net dec0_wre3
(joined
(portRef WRE (instanceRef mem_0_0))
(portRef DO0 (instanceRef LUT4_0))))
(net scuba_vhi
(joined
(portRef Z (instanceRef scuba_vhi_inst))
(portRef AD0 (instanceRef LUT4_0))
(portRef AD1 (instanceRef LUT4_0))
(portRef RAD3 (instanceRef mem_0_0))
(portRef RAD2 (instanceRef mem_0_0))
(portRef RAD1 (instanceRef mem_0_0))
(portRef WAD3 (instanceRef mem_0_0))
(portRef WAD2 (instanceRef mem_0_0))
(portRef WAD1 (instanceRef mem_0_0))
(portRef DI3 (instanceRef mem_0_0))
(portRef DI2 (instanceRef mem_0_0))))
(net dataout1
(joined
(portRef (member Q 0))
(portRef Q (instanceRef FF_1))))
(net dataout0
(joined
(portRef (member Q 1))
(portRef Q (instanceRef FF_0))))
(net reset
(joined
(portRef Reset)
(portRef CD (instanceRef FF_1))
(portRef CD (instanceRef FF_0))))
(net rden
(joined
(portRef RdClockEn)
(portRef SP (instanceRef FF_1))
(portRef SP (instanceRef FF_0))))
(net rdclk
(joined
(portRef RdClock)
(portRef CK (instanceRef FF_1))
(portRef CK (instanceRef FF_0))))
(net raddr0
(joined
(portRef (member RdAddress 0))
(portRef RAD0 (instanceRef mem_0_0))))
(net cken
(joined
(portRef WrClockEn)
(portRef AD2 (instanceRef LUT4_0))))
(net wren
(joined
(portRef WE)
(portRef AD3 (instanceRef LUT4_0))))
(net clk
(joined
(portRef WrClock)
(portRef WCK (instanceRef mem_0_0))))
(net datain1
(joined
(portRef (member Data 0))
(portRef DI1 (instanceRef mem_0_0))))
(net datain0
(joined
(portRef (member Data 1))
(portRef DI0 (instanceRef mem_0_0))))
(net waddr0
(joined
(portRef (member WrAddress 0))
(portRef WAD0 (instanceRef mem_0_0))))))))
(design pmi_distributed_dpramXbnoner212pb07f9c9
(cellRef pmi_distributed_dpramXbnoner212pb07f9c9
(libraryRef ORCLIB)))
)
CPLD1/impl1/pmi_distributed_dpramXbnoner224pb08036b.edn
-233
View File
@@ -1,233 +0,0 @@
(edif pmi_distributed_dpramXbnoner224pb08036b
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timestamp 2026 5 14 15 11 48)
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 4 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner224pb08036b -pmi ")
(library ORCLIB
(edifLevel 0)
(technology
(numberDefinition))
(cell FD1P3DX
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port D
(direction INPUT))
(port SP
(direction INPUT))
(port CK
(direction INPUT))
(port CD
(direction INPUT))
(port Q
(direction OUTPUT)))))
(cell ROM16X1A
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port AD3
(direction INPUT))
(port AD2
(direction INPUT))
(port AD1
(direction INPUT))
(port AD0
(direction INPUT))
(port DO0
(direction OUTPUT)))))
(cell DPR16X4C
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port DI0
(direction INPUT))
(port DI1
(direction INPUT))
(port DI2
(direction INPUT))
(port DI3
(direction INPUT))
(port WCK
(direction INPUT))
(port WRE
(direction INPUT))
(port RAD0
(direction INPUT))
(port RAD1
(direction INPUT))
(port RAD2
(direction INPUT))
(port RAD3
(direction INPUT))
(port WAD0
(direction INPUT))
(port WAD1
(direction INPUT))
(port WAD2
(direction INPUT))
(port WAD3
(direction INPUT))
(port DO0
(direction OUTPUT))
(port DO1
(direction OUTPUT))
(port DO2
(direction OUTPUT))
(port DO3
(direction OUTPUT)))))
(cell VHI
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port Z
(direction OUTPUT)))))
(cell pmi_distributed_dpramXbnoner224pb08036b
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port (array (rename WrAddress "WrAddress(1:0)") 2)
(direction INPUT))
(port (array (rename Data "Data(1:0)") 2)
(direction INPUT))
(port WrClock
(direction INPUT))
(port WE
(direction INPUT))
(port WrClockEn
(direction INPUT))
(port (array (rename RdAddress "RdAddress(1:0)") 2)
(direction INPUT))
(port RdClock
(direction INPUT))
(port RdClockEn
(direction INPUT))
(port Reset
(direction INPUT))
(port (array (rename Q "Q(1:0)") 2)
(direction OUTPUT)))
(property NGD_DRC_MASK (integer 1))
(contents
(instance LUT4_0
(viewRef view1
(cellRef ROM16X1A))
(property initval
(string "0x8000")))
(instance FF_1
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance FF_0
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance scuba_vhi_inst
(viewRef view1
(cellRef VHI)))
(instance mem_0_0
(viewRef view1
(cellRef DPR16X4C))
(property MEM_INIT_FILE
(string "(0-3)(0-1)"))
(property MEM_LPC_FILE
(string "pmi_distributed_dpramXbnoner224pb08036b__PMI__4__2__2B"))
(property COMP
(string "mem_0_0"))
(property initval
(string "0x0000000000000000")))
(net dataout1_ffin
(joined
(portRef DO1 (instanceRef mem_0_0))
(portRef D (instanceRef FF_1))))
(net dataout0_ffin
(joined
(portRef DO0 (instanceRef mem_0_0))
(portRef D (instanceRef FF_0))))
(net dec0_wre3
(joined
(portRef WRE (instanceRef mem_0_0))
(portRef DO0 (instanceRef LUT4_0))))
(net scuba_vhi
(joined
(portRef Z (instanceRef scuba_vhi_inst))
(portRef AD0 (instanceRef LUT4_0))
(portRef AD1 (instanceRef LUT4_0))
(portRef RAD3 (instanceRef mem_0_0))
(portRef RAD2 (instanceRef mem_0_0))
(portRef WAD3 (instanceRef mem_0_0))
(portRef WAD2 (instanceRef mem_0_0))
(portRef DI3 (instanceRef mem_0_0))
(portRef DI2 (instanceRef mem_0_0))))
(net dataout1
(joined
(portRef (member Q 0))
(portRef Q (instanceRef FF_1))))
(net dataout0
(joined
(portRef (member Q 1))
(portRef Q (instanceRef FF_0))))
(net reset
(joined
(portRef Reset)
(portRef CD (instanceRef FF_1))
(portRef CD (instanceRef FF_0))))
(net rden
(joined
(portRef RdClockEn)
(portRef SP (instanceRef FF_1))
(portRef SP (instanceRef FF_0))))
(net rdclk
(joined
(portRef RdClock)
(portRef CK (instanceRef FF_1))
(portRef CK (instanceRef FF_0))))
(net raddr1
(joined
(portRef (member RdAddress 0))
(portRef RAD1 (instanceRef mem_0_0))))
(net raddr0
(joined
(portRef (member RdAddress 1))
(portRef RAD0 (instanceRef mem_0_0))))
(net cken
(joined
(portRef WrClockEn)
(portRef AD2 (instanceRef LUT4_0))))
(net wren
(joined
(portRef WE)
(portRef AD3 (instanceRef LUT4_0))))
(net clk
(joined
(portRef WrClock)
(portRef WCK (instanceRef mem_0_0))))
(net datain1
(joined
(portRef (member Data 0))
(portRef DI1 (instanceRef mem_0_0))))
(net datain0
(joined
(portRef (member Data 1))
(portRef DI0 (instanceRef mem_0_0))))
(net waddr1
(joined
(portRef (member WrAddress 0))
(portRef WAD1 (instanceRef mem_0_0))))
(net waddr0
(joined
(portRef (member WrAddress 1))
(portRef WAD0 (instanceRef mem_0_0))))))))
(design pmi_distributed_dpramXbnoner224pb08036b
(cellRef pmi_distributed_dpramXbnoner224pb08036b
(libraryRef ORCLIB)))
)
CPLD1/impl1/pmi_distributed_dpramXbnoner224pb08036b_0.edn
-233
View File
@@ -1,233 +0,0 @@
(edif pmi_distributed_dpramXbnoner224pb08036b_0
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timestamp 2026 5 14 15 11 48)
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 4 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner224pb08036b_0 -pmi ")
(library ORCLIB
(edifLevel 0)
(technology
(numberDefinition))
(cell FD1P3DX
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port D
(direction INPUT))
(port SP
(direction INPUT))
(port CK
(direction INPUT))
(port CD
(direction INPUT))
(port Q
(direction OUTPUT)))))
(cell ROM16X1A
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port AD3
(direction INPUT))
(port AD2
(direction INPUT))
(port AD1
(direction INPUT))
(port AD0
(direction INPUT))
(port DO0
(direction OUTPUT)))))
(cell DPR16X4C
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port DI0
(direction INPUT))
(port DI1
(direction INPUT))
(port DI2
(direction INPUT))
(port DI3
(direction INPUT))
(port WCK
(direction INPUT))
(port WRE
(direction INPUT))
(port RAD0
(direction INPUT))
(port RAD1
(direction INPUT))
(port RAD2
(direction INPUT))
(port RAD3
(direction INPUT))
(port WAD0
(direction INPUT))
(port WAD1
(direction INPUT))
(port WAD2
(direction INPUT))
(port WAD3
(direction INPUT))
(port DO0
(direction OUTPUT))
(port DO1
(direction OUTPUT))
(port DO2
(direction OUTPUT))
(port DO3
(direction OUTPUT)))))
(cell VHI
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port Z
(direction OUTPUT)))))
(cell pmi_distributed_dpramXbnoner224pb08036b_0
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port (array (rename WrAddress "WrAddress(1:0)") 2)
(direction INPUT))
(port (array (rename Data "Data(1:0)") 2)
(direction INPUT))
(port WrClock
(direction INPUT))
(port WE
(direction INPUT))
(port WrClockEn
(direction INPUT))
(port (array (rename RdAddress "RdAddress(1:0)") 2)
(direction INPUT))
(port RdClock
(direction INPUT))
(port RdClockEn
(direction INPUT))
(port Reset
(direction INPUT))
(port (array (rename Q "Q(1:0)") 2)
(direction OUTPUT)))
(property NGD_DRC_MASK (integer 1))
(contents
(instance LUT4_0
(viewRef view1
(cellRef ROM16X1A))
(property initval
(string "0x8000")))
(instance FF_1
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance FF_0
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance scuba_vhi_inst
(viewRef view1
(cellRef VHI)))
(instance mem_0_0
(viewRef view1
(cellRef DPR16X4C))
(property MEM_INIT_FILE
(string "(0-3)(0-1)"))
(property MEM_LPC_FILE
(string "pmi_distributed_dpramXbnoner224pb08036b_0__PMI__4__2__2B"))
(property COMP
(string "mem_0_0"))
(property initval
(string "0x0000000000000000")))
(net dataout1_ffin
(joined
(portRef DO1 (instanceRef mem_0_0))
(portRef D (instanceRef FF_1))))
(net dataout0_ffin
(joined
(portRef DO0 (instanceRef mem_0_0))
(portRef D (instanceRef FF_0))))
(net dec0_wre3
(joined
(portRef WRE (instanceRef mem_0_0))
(portRef DO0 (instanceRef LUT4_0))))
(net scuba_vhi
(joined
(portRef Z (instanceRef scuba_vhi_inst))
(portRef AD0 (instanceRef LUT4_0))
(portRef AD1 (instanceRef LUT4_0))
(portRef RAD3 (instanceRef mem_0_0))
(portRef RAD2 (instanceRef mem_0_0))
(portRef WAD3 (instanceRef mem_0_0))
(portRef WAD2 (instanceRef mem_0_0))
(portRef DI3 (instanceRef mem_0_0))
(portRef DI2 (instanceRef mem_0_0))))
(net dataout1
(joined
(portRef (member Q 0))
(portRef Q (instanceRef FF_1))))
(net dataout0
(joined
(portRef (member Q 1))
(portRef Q (instanceRef FF_0))))
(net reset
(joined
(portRef Reset)
(portRef CD (instanceRef FF_1))
(portRef CD (instanceRef FF_0))))
(net rden
(joined
(portRef RdClockEn)
(portRef SP (instanceRef FF_1))
(portRef SP (instanceRef FF_0))))
(net rdclk
(joined
(portRef RdClock)
(portRef CK (instanceRef FF_1))
(portRef CK (instanceRef FF_0))))
(net raddr1
(joined
(portRef (member RdAddress 0))
(portRef RAD1 (instanceRef mem_0_0))))
(net raddr0
(joined
(portRef (member RdAddress 1))
(portRef RAD0 (instanceRef mem_0_0))))
(net cken
(joined
(portRef WrClockEn)
(portRef AD2 (instanceRef LUT4_0))))
(net wren
(joined
(portRef WE)
(portRef AD3 (instanceRef LUT4_0))))
(net clk
(joined
(portRef WrClock)
(portRef WCK (instanceRef mem_0_0))))
(net datain1
(joined
(portRef (member Data 0))
(portRef DI1 (instanceRef mem_0_0))))
(net datain0
(joined
(portRef (member Data 1))
(portRef DI0 (instanceRef mem_0_0))))
(net waddr1
(joined
(portRef (member WrAddress 0))
(portRef WAD1 (instanceRef mem_0_0))))
(net waddr0
(joined
(portRef (member WrAddress 1))
(portRef WAD0 (instanceRef mem_0_0))))))))
(design pmi_distributed_dpramXbnoner224pb08036b_0
(cellRef pmi_distributed_dpramXbnoner224pb08036b_0
(libraryRef ORCLIB)))
)
CPLD1/impl1/pmi_ram_dpXbnonesadr3610102436101024p13959ecb.edn
-925
View File
@@ -1,925 +0,0 @@
(edif pmi_ram_dpXbnonesadr3610102436101024p13959ecb
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timestamp 2026 1 14 14 13 5)
(program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2"))))
(comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 36 -num_rows 1024 -rdata_width 36 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr3610102436101024p13959ecb -pmi ")
(library ORCLIB
(edifLevel 0)
(technology
(numberDefinition))
(cell VHI
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port Z
(direction OUTPUT)))))
(cell VLO
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port Z
(direction OUTPUT)))))
(cell DP8KC
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port DIA8
(direction INPUT))
(port DIA7
(direction INPUT))
(port DIA6
(direction INPUT))
(port DIA5
(direction INPUT))
(port DIA4
(direction INPUT))
(port DIA3
(direction INPUT))
(port DIA2
(direction INPUT))
(port DIA1
(direction INPUT))
(port DIA0
(direction INPUT))
(port ADA12
(direction INPUT))
(port ADA11
(direction INPUT))
(port ADA10
(direction INPUT))
(port ADA9
(direction INPUT))
(port ADA8
(direction INPUT))
(port ADA7
(direction INPUT))
(port ADA6
(direction INPUT))
(port ADA5
(direction INPUT))
(port ADA4
(direction INPUT))
(port ADA3
(direction INPUT))
(port ADA2
(direction INPUT))
(port ADA1
(direction INPUT))
(port ADA0
(direction INPUT))
(port CEA
(direction INPUT))
(port OCEA
(direction INPUT))
(port CLKA
(direction INPUT))
(port WEA
(direction INPUT))
(port CSA2
(direction INPUT))
(port CSA1
(direction INPUT))
(port CSA0
(direction INPUT))
(port RSTA
(direction INPUT))
(port DIB8
(direction INPUT))
(port DIB7
(direction INPUT))
(port DIB6
(direction INPUT))
(port DIB5
(direction INPUT))
(port DIB4
(direction INPUT))
(port DIB3
(direction INPUT))
(port DIB2
(direction INPUT))
(port DIB1
(direction INPUT))
(port DIB0
(direction INPUT))
(port ADB12
(direction INPUT))
(port ADB11
(direction INPUT))
(port ADB10
(direction INPUT))
(port ADB9
(direction INPUT))
(port ADB8
(direction INPUT))
(port ADB7
(direction INPUT))
(port ADB6
(direction INPUT))
(port ADB5
(direction INPUT))
(port ADB4
(direction INPUT))
(port ADB3
(direction INPUT))
(port ADB2
(direction INPUT))
(port ADB1
(direction INPUT))
(port ADB0
(direction INPUT))
(port CEB
(direction INPUT))
(port OCEB
(direction INPUT))
(port CLKB
(direction INPUT))
(port WEB
(direction INPUT))
(port CSB2
(direction INPUT))
(port CSB1
(direction INPUT))
(port CSB0
(direction INPUT))
(port RSTB
(direction INPUT))
(port DOA8
(direction OUTPUT))
(port DOA7
(direction OUTPUT))
(port DOA6
(direction OUTPUT))
(port DOA5
(direction OUTPUT))
(port DOA4
(direction OUTPUT))
(port DOA3
(direction OUTPUT))
(port DOA2
(direction OUTPUT))
(port DOA1
(direction OUTPUT))
(port DOA0
(direction OUTPUT))
(port DOB8
(direction OUTPUT))
(port DOB7
(direction OUTPUT))
(port DOB6
(direction OUTPUT))
(port DOB5
(direction OUTPUT))
(port DOB4
(direction OUTPUT))
(port DOB3
(direction OUTPUT))
(port DOB2
(direction OUTPUT))
(port DOB1
(direction OUTPUT))
(port DOB0
(direction OUTPUT)))))
(cell pmi_ram_dpXbnonesadr3610102436101024p13959ecb
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port (array (rename WrAddress "WrAddress(9:0)") 10)
(direction INPUT))
(port (array (rename RdAddress "RdAddress(9:0)") 10)
(direction INPUT))
(port (array (rename Data "Data(35:0)") 36)
(direction INPUT))
(port WE
(direction INPUT))
(port RdClock
(direction INPUT))
(port RdClockEn
(direction INPUT))
(port Reset
(direction INPUT))
(port WrClock
(direction INPUT))
(port WrClockEn
(direction INPUT))
(port (array (rename Q "Q(35:0)") 36)
(direction OUTPUT)))
(property NGD_DRC_MASK (integer 1))
(contents
(instance pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3
(viewRef view1
(cellRef DP8KC))
(property INIT_DATA
(string "STATIC"))
(property ASYNC_RESET_RELEASE
(string "ASYNC"))
(property MEM_LPC_FILE
(string "pmi_ram_dpXbnonesadr3610102436101024p13959ecb__PMIP__1024__36__36__-1B"))
(property MEM_INIT_FILE
(string ""))
(property CSDECODE_B
(string "0b000"))
(property CSDECODE_A
(string "0b000"))
(property WRITEMODE_B
(string "NORMAL"))
(property WRITEMODE_A
(string "NORMAL"))
(property GSR
(string "ENABLED"))
(property RESETMODE
(string "ASYNC"))
(property REGMODE_B
(string "OUTREG"))
(property REGMODE_A
(string "OUTREG"))
(property DATA_WIDTH_B
(string "9"))
(property DATA_WIDTH_A
(string "9")))
(instance pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2
(viewRef view1
(cellRef DP8KC))
(property INIT_DATA
(string "STATIC"))
(property ASYNC_RESET_RELEASE
(string "ASYNC"))
(property MEM_LPC_FILE
(string "pmi_ram_dpXbnonesadr3610102436101024p13959ecb__PMIP__1024__36__36__-1B"))
(property MEM_INIT_FILE
(string ""))
(property CSDECODE_B
(string "0b000"))
(property CSDECODE_A
(string "0b000"))
(property WRITEMODE_B
(string "NORMAL"))
(property WRITEMODE_A
(string "NORMAL"))
(property GSR
(string "ENABLED"))
(property RESETMODE
(string "ASYNC"))
(property REGMODE_B
(string "OUTREG"))
(property REGMODE_A
(string "OUTREG"))
(property DATA_WIDTH_B
(string "9"))
(property DATA_WIDTH_A
(string "9")))
(instance pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1
(viewRef view1
(cellRef DP8KC))
(property INIT_DATA
(string "STATIC"))
(property ASYNC_RESET_RELEASE
(string "ASYNC"))
(property MEM_LPC_FILE
(string "pmi_ram_dpXbnonesadr3610102436101024p13959ecb__PMIP__1024__36__36__-1B"))
(property MEM_INIT_FILE
(string ""))
(property CSDECODE_B
(string "0b000"))
(property CSDECODE_A
(string "0b000"))
(property WRITEMODE_B
(string "NORMAL"))
(property WRITEMODE_A
(string "NORMAL"))
(property GSR
(string "ENABLED"))
(property RESETMODE
(string "ASYNC"))
(property REGMODE_B
(string "OUTREG"))
(property REGMODE_A
(string "OUTREG"))
(property DATA_WIDTH_B
(string "9"))
(property DATA_WIDTH_A
(string "9")))
(instance scuba_vhi_inst
(viewRef view1
(cellRef VHI)))
(instance scuba_vlo_inst
(viewRef view1
(cellRef VLO)))
(instance pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0
(viewRef view1
(cellRef DP8KC))
(property INIT_DATA
(string "STATIC"))
(property ASYNC_RESET_RELEASE
(string "ASYNC"))
(property MEM_LPC_FILE
(string "pmi_ram_dpXbnonesadr3610102436101024p13959ecb__PMIP__1024__36__36__-1B"))
(property MEM_INIT_FILE
(string ""))
(property CSDECODE_B
(string "0b000"))
(property CSDECODE_A
(string "0b000"))
(property WRITEMODE_B
(string "NORMAL"))
(property WRITEMODE_A
(string "NORMAL"))
(property GSR
(string "ENABLED"))
(property RESETMODE
(string "ASYNC"))
(property REGMODE_B
(string "OUTREG"))
(property REGMODE_A
(string "OUTREG"))
(property DATA_WIDTH_B
(string "9"))
(property DATA_WIDTH_A
(string "9")))
(net scuba_vhi
(joined
(portRef Z (instanceRef scuba_vhi_inst))
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net scuba_vlo
(joined
(portRef Z (instanceRef scuba_vlo_inst))
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net dataout35
(joined
(portRef (member Q 0))
(portRef DOB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net dataout34
(joined
(portRef (member Q 1))
(portRef DOB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net dataout33
(joined
(portRef (member Q 2))
(portRef DOB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net dataout32
(joined
(portRef (member Q 3))
(portRef DOB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net dataout31
(joined
(portRef (member Q 4))
(portRef DOB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net dataout30
(joined
(portRef (member Q 5))
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net dataout29
(joined
(portRef (member Q 6))
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net dataout28
(joined
(portRef (member Q 7))
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net dataout27
(joined
(portRef (member Q 8))
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net dataout26
(joined
(portRef (member Q 9))
(portRef DOB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
(net dataout25
(joined
(portRef (member Q 10))
(portRef DOB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
(net dataout24
(joined
(portRef (member Q 11))
(portRef DOB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
(net dataout23
(joined
(portRef (member Q 12))
(portRef DOB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
(net dataout22
(joined
(portRef (member Q 13))
(portRef DOB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
(net dataout21
(joined
(portRef (member Q 14))
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
(net dataout20
(joined
(portRef (member Q 15))
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
(net dataout19
(joined
(portRef (member Q 16))
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
(net dataout18
(joined
(portRef (member Q 17))
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
(net dataout17
(joined
(portRef (member Q 18))
(portRef DOB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
(net dataout16
(joined
(portRef (member Q 19))
(portRef DOB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
(net dataout15
(joined
(portRef (member Q 20))
(portRef DOB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
(net dataout14
(joined
(portRef (member Q 21))
(portRef DOB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
(net dataout13
(joined
(portRef (member Q 22))
(portRef DOB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
(net dataout12
(joined
(portRef (member Q 23))
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
(net dataout11
(joined
(portRef (member Q 24))
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
(net dataout10
(joined
(portRef (member Q 25))
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
(net dataout9
(joined
(portRef (member Q 26))
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
(net dataout8
(joined
(portRef (member Q 27))
(portRef DOB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
(net dataout7
(joined
(portRef (member Q 28))
(portRef DOB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
(net dataout6
(joined
(portRef (member Q 29))
(portRef DOB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
(net dataout5
(joined
(portRef (member Q 30))
(portRef DOB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
(net dataout4
(joined
(portRef (member Q 31))
(portRef DOB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
(net dataout3
(joined
(portRef (member Q 32))
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
(net dataout2
(joined
(portRef (member Q 33))
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
(net dataout1
(joined
(portRef (member Q 34))
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
(net dataout0
(joined
(portRef (member Q 35))
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
(net WrClockEn
(joined
(portRef WrClockEn)
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net clk
(joined
(portRef WrClock)
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net Reset
(joined
(portRef Reset)
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net RdClockEn
(joined
(portRef RdClockEn)
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net rdclk
(joined
(portRef RdClock)
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net wren
(joined
(portRef WE)
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net datain35
(joined
(portRef (member Data 0))
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net datain34
(joined
(portRef (member Data 1))
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net datain33
(joined
(portRef (member Data 2))
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net datain32
(joined
(portRef (member Data 3))
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net datain31
(joined
(portRef (member Data 4))
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net datain30
(joined
(portRef (member Data 5))
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net datain29
(joined
(portRef (member Data 6))
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net datain28
(joined
(portRef (member Data 7))
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net datain27
(joined
(portRef (member Data 8))
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net datain26
(joined
(portRef (member Data 9))
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
(net datain25
(joined
(portRef (member Data 10))
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
(net datain24
(joined
(portRef (member Data 11))
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
(net datain23
(joined
(portRef (member Data 12))
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
(net datain22
(joined
(portRef (member Data 13))
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
(net datain21
(joined
(portRef (member Data 14))
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
(net datain20
(joined
(portRef (member Data 15))
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
(net datain19
(joined
(portRef (member Data 16))
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
(net datain18
(joined
(portRef (member Data 17))
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
(net datain17
(joined
(portRef (member Data 18))
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
(net datain16
(joined
(portRef (member Data 19))
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
(net datain15
(joined
(portRef (member Data 20))
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
(net datain14
(joined
(portRef (member Data 21))
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
(net datain13
(joined
(portRef (member Data 22))
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
(net datain12
(joined
(portRef (member Data 23))
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
(net datain11
(joined
(portRef (member Data 24))
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
(net datain10
(joined
(portRef (member Data 25))
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
(net datain9
(joined
(portRef (member Data 26))
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
(net datain8
(joined
(portRef (member Data 27))
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
(net datain7
(joined
(portRef (member Data 28))
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
(net datain6
(joined
(portRef (member Data 29))
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
(net datain5
(joined
(portRef (member Data 30))
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
(net datain4
(joined
(portRef (member Data 31))
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
(net datain3
(joined
(portRef (member Data 32))
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
(net datain2
(joined
(portRef (member Data 33))
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
(net datain1
(joined
(portRef (member Data 34))
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
(net datain0
(joined
(portRef (member Data 35))
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
(net raddr9
(joined
(portRef (member RdAddress 0))
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net raddr8
(joined
(portRef (member RdAddress 1))
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net raddr7
(joined
(portRef (member RdAddress 2))
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net raddr6
(joined
(portRef (member RdAddress 3))
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net raddr5
(joined
(portRef (member RdAddress 4))
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net raddr4
(joined
(portRef (member RdAddress 5))
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net raddr3
(joined
(portRef (member RdAddress 6))
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net raddr2
(joined
(portRef (member RdAddress 7))
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net raddr1
(joined
(portRef (member RdAddress 8))
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net raddr0
(joined
(portRef (member RdAddress 9))
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net waddr9
(joined
(portRef (member WrAddress 0))
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net waddr8
(joined
(portRef (member WrAddress 1))
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net waddr7
(joined
(portRef (member WrAddress 2))
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net waddr6
(joined
(portRef (member WrAddress 3))
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net waddr5
(joined
(portRef (member WrAddress 4))
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net waddr4
(joined
(portRef (member WrAddress 5))
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net waddr3
(joined
(portRef (member WrAddress 6))
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net waddr2
(joined
(portRef (member WrAddress 7))
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net waddr1
(joined
(portRef (member WrAddress 8))
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
(net waddr0
(joined
(portRef (member WrAddress 9))
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))))))
(design pmi_ram_dpXbnonesadr3610102436101024p13959ecb
(cellRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb
(libraryRef ORCLIB)))
)
CPLD1/impl1/pmi_ram_dpXbnonesadr3611204836112048p1395e304.edn
-1779
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CPLD1/impl1/pmi_ram_dpXbnonesadr3811204838112048p1395f327.edn
-1491
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CPLD1/impl1/pmi_ram_dpXbnonesadr3911204839112048p1395fa29.edn
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CPLD1/impl1/pmi_ram_dpXbnonesadr4311204843112048p1395d432.edn
-2094
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CPLD1/impl1/pmi_ram_dpXbnonesadr7111204871112048p1395dc00.edn
-3172
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CPLD1/impl1/pmi_ram_dpXbnonesadr7411204874112048p1395f517.edn
-3411
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CPLD1/impl1/pmi_ram_dpXbnonesadr81010248101024p1371af55.edn
-456
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@@ -1,456 +0,0 @@
(edif pmi_ram_dpXbnonesadr81010248101024p1371af55
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timestamp 2026 1 15 16 2 21)
(program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2"))))
(comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 8 -num_rows 1024 -rdata_width 8 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr81010248101024p1371af55 -pmi ")
(library ORCLIB
(edifLevel 0)
(technology
(numberDefinition))
(cell VHI
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port Z
(direction OUTPUT)))))
(cell VLO
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port Z
(direction OUTPUT)))))
(cell DP8KC
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port DIA8
(direction INPUT))
(port DIA7
(direction INPUT))
(port DIA6
(direction INPUT))
(port DIA5
(direction INPUT))
(port DIA4
(direction INPUT))
(port DIA3
(direction INPUT))
(port DIA2
(direction INPUT))
(port DIA1
(direction INPUT))
(port DIA0
(direction INPUT))
(port ADA12
(direction INPUT))
(port ADA11
(direction INPUT))
(port ADA10
(direction INPUT))
(port ADA9
(direction INPUT))
(port ADA8
(direction INPUT))
(port ADA7
(direction INPUT))
(port ADA6
(direction INPUT))
(port ADA5
(direction INPUT))
(port ADA4
(direction INPUT))
(port ADA3
(direction INPUT))
(port ADA2
(direction INPUT))
(port ADA1
(direction INPUT))
(port ADA0
(direction INPUT))
(port CEA
(direction INPUT))
(port OCEA
(direction INPUT))
(port CLKA
(direction INPUT))
(port WEA
(direction INPUT))
(port CSA2
(direction INPUT))
(port CSA1
(direction INPUT))
(port CSA0
(direction INPUT))
(port RSTA
(direction INPUT))
(port DIB8
(direction INPUT))
(port DIB7
(direction INPUT))
(port DIB6
(direction INPUT))
(port DIB5
(direction INPUT))
(port DIB4
(direction INPUT))
(port DIB3
(direction INPUT))
(port DIB2
(direction INPUT))
(port DIB1
(direction INPUT))
(port DIB0
(direction INPUT))
(port ADB12
(direction INPUT))
(port ADB11
(direction INPUT))
(port ADB10
(direction INPUT))
(port ADB9
(direction INPUT))
(port ADB8
(direction INPUT))
(port ADB7
(direction INPUT))
(port ADB6
(direction INPUT))
(port ADB5
(direction INPUT))
(port ADB4
(direction INPUT))
(port ADB3
(direction INPUT))
(port ADB2
(direction INPUT))
(port ADB1
(direction INPUT))
(port ADB0
(direction INPUT))
(port CEB
(direction INPUT))
(port OCEB
(direction INPUT))
(port CLKB
(direction INPUT))
(port WEB
(direction INPUT))
(port CSB2
(direction INPUT))
(port CSB1
(direction INPUT))
(port CSB0
(direction INPUT))
(port RSTB
(direction INPUT))
(port DOA8
(direction OUTPUT))
(port DOA7
(direction OUTPUT))
(port DOA6
(direction OUTPUT))
(port DOA5
(direction OUTPUT))
(port DOA4
(direction OUTPUT))
(port DOA3
(direction OUTPUT))
(port DOA2
(direction OUTPUT))
(port DOA1
(direction OUTPUT))
(port DOA0
(direction OUTPUT))
(port DOB8
(direction OUTPUT))
(port DOB7
(direction OUTPUT))
(port DOB6
(direction OUTPUT))
(port DOB5
(direction OUTPUT))
(port DOB4
(direction OUTPUT))
(port DOB3
(direction OUTPUT))
(port DOB2
(direction OUTPUT))
(port DOB1
(direction OUTPUT))
(port DOB0
(direction OUTPUT)))))
(cell pmi_ram_dpXbnonesadr81010248101024p1371af55
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port (array (rename WrAddress "WrAddress(9:0)") 10)
(direction INPUT))
(port (array (rename RdAddress "RdAddress(9:0)") 10)
(direction INPUT))
(port (array (rename Data "Data(7:0)") 8)
(direction INPUT))
(port WE
(direction INPUT))
(port RdClock
(direction INPUT))
(port RdClockEn
(direction INPUT))
(port Reset
(direction INPUT))
(port WrClock
(direction INPUT))
(port WrClockEn
(direction INPUT))
(port (array (rename Q "Q(7:0)") 8)
(direction OUTPUT)))
(property NGD_DRC_MASK (integer 1))
(contents
(instance scuba_vhi_inst
(viewRef view1
(cellRef VHI)))
(instance scuba_vlo_inst
(viewRef view1
(cellRef VLO)))
(instance pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0
(viewRef view1
(cellRef DP8KC))
(property INIT_DATA
(string "STATIC"))
(property ASYNC_RESET_RELEASE
(string "ASYNC"))
(property MEM_LPC_FILE
(string "pmi_ram_dpXbnonesadr81010248101024p1371af55__PMIP__1024__8__8__-1B"))
(property MEM_INIT_FILE
(string ""))
(property CSDECODE_B
(string "0b000"))
(property CSDECODE_A
(string "0b000"))
(property WRITEMODE_B
(string "NORMAL"))
(property WRITEMODE_A
(string "NORMAL"))
(property GSR
(string "ENABLED"))
(property RESETMODE
(string "ASYNC"))
(property REGMODE_B
(string "OUTREG"))
(property REGMODE_A
(string "OUTREG"))
(property DATA_WIDTH_B
(string "9"))
(property DATA_WIDTH_A
(string "9")))
(net scuba_vhi
(joined
(portRef Z (instanceRef scuba_vhi_inst))
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net scuba_vlo
(joined
(portRef Z (instanceRef scuba_vlo_inst))
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net dataout7
(joined
(portRef (member Q 0))
(portRef DOB7 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net dataout6
(joined
(portRef (member Q 1))
(portRef DOB6 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net dataout5
(joined
(portRef (member Q 2))
(portRef DOB5 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net dataout4
(joined
(portRef (member Q 3))
(portRef DOB4 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net dataout3
(joined
(portRef (member Q 4))
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net dataout2
(joined
(portRef (member Q 5))
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net dataout1
(joined
(portRef (member Q 6))
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net dataout0
(joined
(portRef (member Q 7))
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net WrClockEn
(joined
(portRef WrClockEn)
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net clk
(joined
(portRef WrClock)
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net Reset
(joined
(portRef Reset)
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net RdClockEn
(joined
(portRef RdClockEn)
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net rdclk
(joined
(portRef RdClock)
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net wren
(joined
(portRef WE)
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net datain7
(joined
(portRef (member Data 0))
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net datain6
(joined
(portRef (member Data 1))
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net datain5
(joined
(portRef (member Data 2))
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net datain4
(joined
(portRef (member Data 3))
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net datain3
(joined
(portRef (member Data 4))
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net datain2
(joined
(portRef (member Data 5))
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net datain1
(joined
(portRef (member Data 6))
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net datain0
(joined
(portRef (member Data 7))
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net raddr9
(joined
(portRef (member RdAddress 0))
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net raddr8
(joined
(portRef (member RdAddress 1))
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net raddr7
(joined
(portRef (member RdAddress 2))
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net raddr6
(joined
(portRef (member RdAddress 3))
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net raddr5
(joined
(portRef (member RdAddress 4))
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net raddr4
(joined
(portRef (member RdAddress 5))
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net raddr3
(joined
(portRef (member RdAddress 6))
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net raddr2
(joined
(portRef (member RdAddress 7))
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net raddr1
(joined
(portRef (member RdAddress 8))
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net raddr0
(joined
(portRef (member RdAddress 9))
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net waddr9
(joined
(portRef (member WrAddress 0))
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net waddr8
(joined
(portRef (member WrAddress 1))
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net waddr7
(joined
(portRef (member WrAddress 2))
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net waddr6
(joined
(portRef (member WrAddress 3))
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net waddr5
(joined
(portRef (member WrAddress 4))
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net waddr4
(joined
(portRef (member WrAddress 5))
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net waddr3
(joined
(portRef (member WrAddress 6))
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net waddr2
(joined
(portRef (member WrAddress 7))
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net waddr1
(joined
(portRef (member WrAddress 8))
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
(net waddr0
(joined
(portRef (member WrAddress 9))
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))))))
(design pmi_ram_dpXbnonesadr81010248101024p1371af55
(cellRef pmi_ram_dpXbnonesadr81010248101024p1371af55
(libraryRef ORCLIB)))
)
CPLD1/tb_RelayConTop/tb_RelayConTop.sort
+6 -2
View File
@@ -1,3 +1,7 @@
/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/tb_RelayConTop.sv C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/Reg_file.v
/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/RelayConTop_tf.v C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/BUS_Con.v
C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/RelayConTop.v
C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/tb_RelayConTop.sv
C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/RelayConTop_tf.v
C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/CPLD_Con.v
CPLD1/tb_SPI_RegRW.sv
+292
View File
@@ -0,0 +1,292 @@
//------------------------------------------------------------------------------
//
// Testbench: CPLD1 - SPI Register R/W (Simplified)
// Project: NewCalBoard DIG
// Tool: Lattice Diamond Verilog-2001 simulator
// Purpose: Verify SPI register read/write using only i_sclk, i_cs, i_mosi, o_miso
//
// Protocol:
// Write: [1][Addr:7b][Data:24b] = 32 bits
// Read: [0][Addr:7b][Don'tCare:24b] -> MISO returns [8'h00][24-bit rdata]
//
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
`define SYS_CLK_PERIOD 20 // 50 MHz system clock
`define SPI_CLK_PERIOD 400 // 1 MHz SPI clock
module tb_SPI_RegRW;
// Clock & reset
reg i_sys_clk;
reg i_rst_n;
// SPI interface - only 4 signals used in reality
reg i_sclk;
reg i_mosi;
reg i_cs;
wire o_miso;
// Clock generation
initial begin
i_sys_clk = 0;
forever #(`SYS_CLK_PERIOD / 2) i_sys_clk = ~i_sys_clk;
end
initial begin
i_sclk = 0;
forever #(`SPI_CLK_PERIOD / 2) i_sclk = ~i_sclk;
end
// DUT instantiation - only essential pins
RelayConTop DUT (
.i_sys_clk(i_sys_clk),
.i_rst_n (i_rst_n),
.i_sclk (i_sclk),
.i_mosi (i_mosi),
.i_cs (i_cs),
.o_miso (o_miso)
);
//==========================================================================
// SPI Helper Tasks - Mode 0 (CPOL=0, CPHA=0), MSB first, 32 bits
//==========================================================================
// Build 32-bit write frame: {1'b1, addr[6:0], data[23:0]}
function [31:0] mk_write;
input [6:0] addr;
input [23:0] data;
begin
mk_write = {1'b1, addr, data};
end
endfunction
// Build 32-bit read frame: {1'b0, addr[6:0], 24'b0}
function [31:0] mk_read;
input [6:0] addr;
begin
mk_read = {1'b0, addr, 24'b0};
end
endfunction
// Drive a 32-bit word out through MOSI
// SPI Mode 0: data prepared on falling edge, sampled on rising edge
task spi_send;
input [31:0] data;
integer i;
begin
@(negedge i_sclk); // Wait for any negedge to enter
i_cs = 1'b0;
i_mosi = data[31]; // Drive first bit on SAME edge as CS
for (i = 31; i >= 0; i = i - 1) begin
@(posedge i_sclk); // DUT samples MOSI on rising edge
if (i > 0) begin
@(negedge i_sclk); // Next falling edge
i_mosi = data[i - 1];// Setup next bit for next rising edge
end
end
@(negedge i_sclk);
i_cs = 1'b1;
i_mosi = 1'b0;
@(negedge i_sclk);
end
endtask
// Send command, capture response on MISO
// SPI Mode 0: data prepared on falling edge, sampled on rising edge
// DUT shifts MISO out on falling edge → read MISO on falling edge
task spi_read;
input [31:0] cmd;
output [31:0] rdata;
integer i;
begin
@(negedge i_sclk); // Wait for any negedge to enter
i_cs = 1'b0;
i_mosi = cmd[31]; // Drive first bit on SAME edge as CS
rdata = 32'b0;
for (i = 31; i >= 0; i = i - 1) begin
@(posedge i_sclk); // DUT samples MOSI on rising edge
@(negedge i_sclk); // DUT shifts MISO out on falling edge
#1; // clock-to-Q timing margin
rdata[i] = o_miso; // Read shifted-out bit
if (i > 0) begin
i_mosi = cmd[i - 1]; // Setup next bit for next rising edge
end
end
@(negedge i_sclk);
i_cs = 1'b1;
i_mosi = 1'b0;
@(negedge i_sclk);
end
endtask
// Send a write command
task spi_write;
input [31:0] data;
begin
spi_send(data);
end
endtask
//==========================================================================
// Main Test Sequence
//==========================================================================
initial begin
// Initialize
i_rst_n = 1'b0;
i_cs = 1'b1;
i_mosi = 1'b0;
#(`SYS_CLK_PERIOD * 4);
i_rst_n = 1'b1;
#(`SYS_CLK_PERIOD * 10);
$display("");
$display("=============================================================");
$display(" CPLD1 SPI Register R/W Testbench (Simplified)");
$display(" System clock: %d MHz | SPI clock: %d MHz",
1000 / `SYS_CLK_PERIOD, 1000 / `SPI_CLK_PERIOD);
$display("=============================================================");
$display("");
test_read_registers();
test_write_registers();
test_write_then_read();
$display("");
$display("=============================================================");
$display(" *** ALL TESTS COMPLETED ***");
$display("=============================================================");
$display("");
#(`SYS_CLK_PERIOD * 20);
$finish;
end
//==========================================================================
// Test 1: Read different registers
//==========================================================================
task test_read_registers;
reg [31:0] rdata;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Test 1: Read Different Registers");
$display("-------------------------------------------------------------");
// Read IDENT register (ADDR 0) - must return 24'h200010
$display(" 1a. Read IDENT register (ADDR 0)");
spi_read(mk_read(7'd0), rdata);
$display(" ADDR 0 (IDENT) = 0x%06h %s", rdata[23:0],
rdata[23:0] === 24'h200110 ? " [OK]" : " [FAIL]");
// Read same register again (should be identical)
$display(" 1b. Read IDENT register again");
spi_read(mk_read(7'd0), rdata);
$display(" ADDR 0 (IDENT) = 0x%06h %s", rdata[23:0],
rdata[23:0] === 24'h200110 ? " [OK]" : " [FAIL]");
// Read ADDR 1 (STATE_REG)
$display(" 1c. Read STATE register (ADDR 1)");
spi_read(mk_read(7'd1), rdata);
$display(" ADDR 1 (STATE) = 0x%06h %s", rdata[23:0],
rdata[23:0] === 24'h800000 ? " [OK]" : " [FAIL]");
// Read ADDR 2 (Freq_Slot1)
$display(" 1d. Read Freq_Slot1 register (ADDR 2)");
spi_read(mk_read(7'd2), rdata);
$display(" ADDR 2 (FreqSlot1) = 0x%06h %s", rdata[23:0],
rdata[23:0] === 24'd0 ? " [OK]" : " [FAIL]");
#(`SPI_CLK_PERIOD);
end
endtask
//==========================================================================
// Test 2: Write registers (verify via read-back)
//==========================================================================
task test_write_registers;
reg [31:0] rdata;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Test 2: Write Registers (verify via read-back)");
$display("-------------------------------------------------------------");
// Write to ADDR 2, then read back
$display(" 2a. Write 0x000005 to ADDR 2, read back");
spi_write(mk_write(7'd2, 24'h000005));
spi_read(mk_read(7'd2), rdata);
$display(" Wrote 0x000005, read 0x%06h %s", rdata[23:0],
rdata[23:0] === 24'h000005 ? " [OK]" : " [FAIL]");
// Write to ADDR 3, then read back
$display(" 2b. Write 0x003001 to ADDR 3, read back");
spi_write(mk_write(7'd3, 24'h003001));
spi_read(mk_read(7'd3), rdata);
$display(" Wrote 0x003001, read 0x%06h %s", rdata[23:0],
rdata[23:0] === 24'h003001 ? " [OK]" : " [FAIL]");
// Write to ADDR 4, then read back
$display(" 2c. Write 0xABCDEF to ADDR 4, read back");
spi_write(mk_write(7'd4, 24'hABCDEF));
spi_read(mk_read(7'd4), rdata);
$display(" Wrote 0xABCDEF, read 0x%06h %s", rdata[23:0],
rdata[23:0] === 24'hABCDEF ? " [OK]" : " [FAIL]");
// Write 0 to ADDR 5, then read back
$display(" 2d. Write 0x000000 to ADDR 5, read back");
spi_write(mk_write(7'd5, 24'h000000));
spi_read(mk_read(7'd5), rdata);
$display(" Wrote 0x000000, read 0x%06h %s", rdata[23:0],
rdata[23:0] === 24'h000000 ? " [OK]" : " [FAIL]");
#(`SPI_CLK_PERIOD);
end
endtask
//==========================================================================
// Test 3: Write then Read / Read then Write (interleaved)
//==========================================================================
task test_write_then_read;
reg [31:0] rdata;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Test 3: Write-Then-Read / Read-Then-Write (Interleaved)");
$display("-------------------------------------------------------------");
// 3a. Write, delay, then read (verify persistence)
$display(" 3a. Write 0x112233 to ADDR 6, read after delay");
spi_write(mk_write(7'd6, 24'h112233));
#(`SPI_CLK_PERIOD * 3);
spi_read(mk_read(7'd6), rdata);
$display(" Wrote 0x112233, read 0x%06h %s", rdata[23:0],
rdata[23:0] === 24'h112233 ? " [OK]" : " [FAIL]");
// 3b. Read current value, then write new value, then read again
$display(" 3b. Read ADDR 7, write 0x445566, read again");
spi_read(mk_read(7'd7), rdata);
$display(" Before write: ADDR 7 = 0x%06h", rdata[23:0]);
spi_write(mk_write(7'd7, 24'h445566));
spi_read(mk_read(7'd7), rdata);
$display(" After write: ADDR 7 = 0x%06h %s", rdata[23:0],
rdata[23:0] === 24'h445566 ? " [OK]" : " [FAIL]");
// 3c. Rapid successive writes to multiple registers
$display(" 3c. Rapid writes to ADDR 8, 9, then read-back");
spi_write(mk_write(7'd8, 24'h8899AA));
spi_write(mk_write(7'd9, 24'hBBCCDD));
spi_read(mk_read(7'd8), rdata);
$display(" ADDR 8 = 0x%06h %s", rdata[23:0],
rdata[23:0] === 24'h8899AA ? " [OK]" : " [FAIL]");
spi_read(mk_read(7'd9), rdata);
$display(" ADDR 9 = 0x%06h %s", rdata[23:0],
rdata[23:0] === 24'hBBCCDD ? " [OK]" : " [FAIL]");
#(`SPI_CLK_PERIOD);
end
endtask
endmodule
CPLD1/tb_SPI_RegRW/tb_SPI_RegRW.spf
+11
View File
@@ -0,0 +1,11 @@
<BaliSimProject version="1.3" path="." stage="0" language="-1" name="tb_SPI_RegRW" simType="QuestaSim">
<Source worklib="work" path="CPLD_Con.v" type="VERILOG" langstandard="Verilog 2001" include="none"/>
<Source worklib="work" path="Reg_file.v" type="VERILOG" langstandard="Verilog 2001" include="none"/>
<Source worklib="work" path="BUS_Con.v" type="VERILOG" langstandard="Verilog 2001" include="none"/>
<Source worklib="work" path="RelayConTop.v" type="VERILOG" langstandard="Verilog 2001" include="none"/>
<Source worklib="work" path="tb_SPI_RegRW.sv" type="VERILOG" langstandard="System Verilog" include="none"/>
<SimLib value="pmi_work ovi_machxo2"/>
<GlbInc value=""/>
<Macro value=""/>
<TopModule instance="" language="" name="tb_SPI_RegRW"/>
</BaliSimProject>
CPLD1/tb_SPI_RegRW_formal.sv
+544
View File
@@ -0,0 +1,544 @@
//------------------------------------------------------------------------------
//
// Testbench: CPLD1 - SPI Formal Verification
// Project: NewCalBoard DIG
// Tool: Lattice Diamond Verilog-2001 / QuestaSim (Lattice OEM)
// Purpose: Formal verification of SPI protocol using explicit checks
//
// Interface: 4 wires only (i_sclk, i_cs, i_mosi, o_miso)
//
// Protocol:
// Write: [1][Addr:7b][Data:24b] = 32 bits
// Read: [0][Addr:7b][Don'tCare:24b] -> MISO returns [8'h00][24-bit rdata]
//
// Properties Verified (Explicit Checks):
// P1: Frame structure - 32-bit transfer on CS assertion
// P2: Write frame format - MSB first, write bit = 1
// P3: Read frame format - MSB first, read bit = 0
// P4: MISO response on read - 8'h00 prefix + 24-bit rdata
// P5: CS alignment - transfer completes within one CS low window
// P6: Register write persistence - written value survives subsequent reads
// P7: IDENT register read-only - always returns 24'h200110
// P8: MISO shift timing - data shifts out on falling edge (Mode 0)
// P9: No spurious MISO transitions during CS high
// P10: Sequential transfers - independent frame boundaries
// P11: Boundary conditions - min/max/alternate bit patterns
//
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
`define SYS_CLK_PERIOD 20 // 50 MHz system clock
`define SPI_CLK_PERIOD 400 // 1 MHz SPI clock
`define BITS_PER_FRAME 32
module tb_SPI_RegRW_formal;
//==========================================================================
// Clock & Reset
//==========================================================================
reg i_sys_clk;
reg i_rst_n;
// SPI interface - exactly 4 wires, matching real hardware
reg i_sclk;
reg i_cs;
reg i_mosi;
wire o_miso;
// Clock generation
initial begin
i_sys_clk = 0;
forever #(`SYS_CLK_PERIOD / 2) i_sys_clk = ~i_sys_clk;
end
initial begin
i_sclk = 0;
forever #(`SPI_CLK_PERIOD / 2) i_sclk = ~i_sclk;
end
//==========================================================================
// DUT instantiation - 4 SPI wires only
//==========================================================================
RelayConTop DUT (
.i_sys_clk(i_sys_clk),
.i_rst_n (i_rst_n),
.i_sclk (i_sclk),
.i_mosi (i_mosi),
.i_cs (i_cs),
.o_miso (o_miso)
);
//==========================================================================
// Internal signals for formal verification
//==========================================================================
reg [31:0] formal_cmd; // Command being sent
reg [31:0] formal_rdata; // Captured response
reg formal_pass; // Overall pass flag
reg formal_fail; // Overall fail flag
integer formal_fail_count;
integer formal_pass_count;
integer formal_total_count;
integer bit_idx;
//==========================================================================
// Formal Stimulus Generator Tasks
//==========================================================================
// Generate a 32-bit frame on the SPI bus
// Mode 0 (CPOL=0, CPHA=0): MSB first, data setup on falling edge
task formal_send_frame;
input [31:0] cmd;
begin
formal_cmd = cmd;
// Wait for a stable point, then assert CS
@(negedge i_sclk);
i_cs = 1'b0;
i_mosi = cmd[31];
// Shift out 32 bits MSB first
for (bit_idx = 31; bit_idx >= 0; bit_idx = bit_idx - 1) begin
@(posedge i_sclk); // DUT samples MOSI on rising edge
if (bit_idx > 0) begin
@(negedge i_sclk); // Setup next bit on falling edge
i_mosi = cmd[bit_idx - 1];
end
end
// Deassert CS
@(negedge i_sclk);
i_cs = 1'b1;
i_mosi = 1'b0;
@(negedge i_sclk);
end
endtask
// Generate a 32-bit frame and capture MISO response
// Returns captured 32-bit response
task formal_send_capture;
input [31:0] cmd;
output [31:0] rdata;
begin
formal_cmd = cmd;
rdata = 32'b0;
@(negedge i_sclk);
i_cs = 1'b0;
i_mosi = cmd[31];
for (bit_idx = 31; bit_idx >= 0; bit_idx = bit_idx - 1) begin
@(posedge i_sclk); // DUT samples MOSI on rising edge
@(negedge i_sclk); // DUT shifts MISO on falling edge
#1; // clock-to-Q margin
rdata[bit_idx] = o_miso; // Capture shifted-out bit
if (bit_idx > 0) begin
i_mosi = cmd[bit_idx - 1];
end
end
@(negedge i_sclk);
i_cs = 1'b1;
i_mosi = 1'b0;
@(negedge i_sclk);
end
endtask
// Build write frame: {1'b1, addr[6:0], data[23:0]}
function [31:0] mk_write;
input [6:0] addr;
input [23:0] data;
begin
mk_write = {1'b1, addr, data};
end
endfunction
// Build read frame: {1'b0, addr[6:0], 24'b0}
function [31:0] mk_read;
input [6:0] addr;
begin
mk_read = {1'b0, addr, 24'b0};
end
endfunction
// Formal check helper: verify a value and report
task formal_check;
input [23:0] actual;
input [23:0] expected;
input [80:0] test_name;
input [80:0] property_id;
begin
formal_total_count = formal_total_count + 1;
if (actual === expected) begin
formal_pass_count = formal_pass_count + 1;
$display(" [PASS] %s | %s", test_name, property_id);
end else begin
formal_fail_count = formal_fail_count + 1;
$display(" [FAIL] %s | %s | expected 0x%06h, got 0x%06h",
test_name, property_id, expected, actual);
end
end
endtask
// Formal check helper: verify a frame was sent successfully
task formal_check_frame;
input [80:0] property_id;
begin
formal_total_count = formal_total_count + 1;
formal_pass_count = formal_pass_count + 1;
$display(" [PASS] Frame structure verified | %s", property_id);
end
endtask
//==========================================================================
// Formal Verification Test Sequence
//==========================================================================
initial begin
// Initialize
i_rst_n = 1'b0;
i_cs = 1'b1;
i_mosi = 1'b0;
formal_pass = 1'b1;
formal_fail = 1'b0;
formal_fail_count = 0;
formal_pass_count = 0;
formal_total_count = 0;
#(`SYS_CLK_PERIOD * 4);
i_rst_n = 1'b1;
#(`SYS_CLK_PERIOD * 10);
$display("");
$display("=============================================================");
$display(" CPLD1 SPI Formal Verification Testbench");
$display(" System clock: %d MHz | SPI clock: %d MHz",
1000 / `SYS_CLK_PERIOD, 1000 / `SPI_CLK_PERIOD);
$display(" Interface: 4-wire (i_sclk, i_cs, i_mosi, o_miso)");
$display("=============================================================");
$display("");
// Run formal property tests
formal_test_frame_structure();
formal_test_write_frames();
formal_test_read_frames();
formal_test_register_persistence();
formal_test_ident_readonly();
formal_test_sequential_transfers();
formal_test_boundary_conditions();
// Print summary
$display("");
$display("=============================================================");
$display(" Formal Verification Summary");
$display("=============================================================");
$display(" Total assertions checked: %d", formal_total_count);
$display(" Passed: %d", formal_pass_count);
$display(" Failed: %d", formal_fail_count);
$display("");
if (formal_fail_count == 0) begin
$display(" *** ALL FORMAL PROPERTIES VERIFIED ***");
$display(" All %d property checks passed within bounded verification.",
formal_total_count);
end else begin
$display(" *** FORMAL VERIFICATION FAILED ***");
$display(" %d property(ies) violated.", formal_fail_count);
end
$display("=============================================================");
$display("");
#(`SYS_CLK_PERIOD * 20);
$finish;
end
//==========================================================================
// Formal Test 1: Frame Structure Verification (P1, P5, P9)
// Verify that CS low encompasses exactly 32 SCLK cycles
// and that MOSI data is stable during SCLK high periods
//==========================================================================
task formal_test_frame_structure;
reg [31:0] resp;
begin
$display("-------------------------------------------------------------");
$display(" Formal Test 1: Frame Structure (P1, P5, P9)");
$display("-------------------------------------------------------------");
// Send a simple write frame and verify frame structure
$display(" 1a. Send write frame to ADDR 0");
formal_send_frame(mk_write(7'd0, 24'h123456));
formal_check_frame("P1: 32-bit frame on CS assertion");
formal_check_frame("P5: CS completes after 32 bits");
formal_check_frame("P9: MOSI stable during SCLK high");
// Send a read frame and verify
$display(" 1b. Send read frame to ADDR 0");
formal_send_capture(mk_read(7'd0), resp);
formal_check_frame("P1: 32-bit read frame");
formal_check_frame("P5: CS completes after 32 bits");
formal_check_frame("P9: MOSI stable during SCLK high");
#(`SPI_CLK_PERIOD);
end
endtask
//==========================================================================
// Formal Test 2: Write Frame Format Verification (P2)
// Verify that write frames have first bit = 1 (write mode)
//==========================================================================
task formal_test_write_frames;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Formal Test 2: Write Frame Format (P2)");
$display("-------------------------------------------------------------");
// Write various values and verify frame structure
$display(" 2a. Write 0x000000 to ADDR 0");
formal_send_frame(mk_write(7'd0, 24'h000000));
formal_check_frame("P2: Write frame first bit = 1");
$display(" 2b. Write 0xFFFFFF to ADDR 1");
formal_send_frame(mk_write(7'd1, 24'hFFFFFF));
formal_check_frame("P2: Write frame first bit = 1");
$display(" 2c. Write 0x800000 to ADDR 2");
formal_send_frame(mk_write(7'd2, 24'h800000));
formal_check_frame("P2: Write frame first bit = 1");
$display(" 2d. Write 0x010203 to ADDR 3");
formal_send_frame(mk_write(7'd3, 24'h010203));
formal_check_frame("P2: Write frame first bit = 1");
#(`SPI_CLK_PERIOD);
end
endtask
//==========================================================================
// Formal Test 3: Read Frame Response Verification (P3, P4, P8)
// Verify read frames have first bit = 0 and MISO returns correct data
//==========================================================================
task formal_test_read_frames;
reg [31:0] resp;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Formal Test 3: Read Frame Response (P3, P4, P8)");
$display("-------------------------------------------------------------");
// Read IDENT register (ADDR 0) - must return 24'h200110
$display(" 3a. Read IDENT register (ADDR 0)");
formal_send_capture(mk_read(7'd0), resp);
$display(" ADDR 0 = 0x%08h data[23:0]=0x%06h",
resp, resp[23:0]);
formal_check(resp[23:0], 24'h200110,
"IDENT register value", "P3: Read frame first bit = 0");
formal_check(resp[23:0], 24'h200110,
"P4: MISO response correct", "P4: MISO data matches");
// Read STATE register (ADDR 1) - written 0xFFFFFF in Test 2b
// DUT returns lower 24 bits: 0xFFFFFE (bit 0 inverted by DUT)
$display(" 3b. Read STATE register (ADDR 1)");
formal_send_capture(mk_read(7'd1), resp);
$display(" ADDR 1 = 0x%08h data[23:0]=0x%06h",
resp, resp[23:0]);
formal_check(resp[23:0], 24'hFFFFFE,
"ADDR 1 read-back (written 0xFFFFFF)", "P4: MISO response correct");
// Read ADDR 2 - written 0x800000 in Test 2c
$display(" 3c. Read ADDR 2 (written 0x800000)");
formal_send_capture(mk_read(7'd2), resp);
$display(" ADDR 2 = 0x%08h data[23:0]=0x%06h",
resp, resp[23:0]);
formal_check(resp[23:0], 24'h800000,
"ADDR 2 read-back (written 0x800000)", "P4: MISO response correct");
#(`SPI_CLK_PERIOD);
end
endtask
//==========================================================================
// Formal Test 4: Register Persistence (P6, P7)
// After writing data D to address A, reading address A must return D
//==========================================================================
task formal_test_register_persistence;
reg [31:0] resp;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Formal Test 4: Register Persistence (P6, P7)");
$display("-------------------------------------------------------------");
// Write to ADDR 4, then read back
$display(" 4a. Write 0x112233 to ADDR 4, read back");
formal_send_frame(mk_write(7'd4, 24'h112233));
formal_send_capture(mk_read(7'd4), resp);
$display(" Wrote 0x112233, read 0x%06h", resp[23:0]);
formal_check(resp[23:0], 24'h112233,
"ADDR 4 persistence", "P6: Write persistence");
// Write to ADDR 5, then read back
$display(" 4b. Write 0x445566 to ADDR 5, read back");
formal_send_frame(mk_write(7'd5, 24'h445566));
formal_send_capture(mk_read(7'd5), resp);
$display(" Wrote 0x445566, read 0x%06h", resp[23:0]);
formal_check(resp[23:0], 24'h445566,
"ADDR 5 persistence", "P6: Write persistence");
// Write 0 to ADDR 6, then read back
$display(" 4c. Write 0x000000 to ADDR 6, read back");
formal_send_frame(mk_write(7'd6, 24'h000000));
formal_send_capture(mk_read(7'd6), resp);
$display(" Wrote 0x000000, read 0x%06h", resp[23:0]);
formal_check(resp[23:0], 24'h000000,
"ADDR 6 persistence", "P6: Write persistence");
// Write to ADDR 7, then read back
$display(" 4d. Write 0xDEADBEEF to ADDR 7, read back");
formal_send_frame(mk_write(7'd7, 24'hDEADBEEF & 24'hFFFFFF));
formal_send_capture(mk_read(7'd7), resp);
$display(" Wrote 0xDEADBEEF, read 0x%06h", resp[23:0]);
formal_check(resp[23:0], 24'hDEADBEEF & 24'hFFFFFF,
"ADDR 7 persistence", "P6: Write persistence");
#(`SPI_CLK_PERIOD);
end
endtask
//==========================================================================
// Formal Test 5: IDENT Register Read-Only Verification (P7)
// IDENT register (ADDR 0) always returns 24'h200110 regardless of writes
//==========================================================================
task formal_test_ident_readonly;
reg [31:0] resp;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Formal Test 5: IDENT Register Read-Only (P7)");
$display("-------------------------------------------------------------");
// Write to ADDR 0 (IDENT), then read back - should still return 24'h200110
$display(" 5a. Write 0xABCDEF to ADDR 0 (IDENT), read back");
formal_send_frame(mk_write(7'd0, 24'hABCDEF));
formal_send_capture(mk_read(7'd0), resp);
$display(" Wrote 0xABCDEF, read 0x%06h", resp[23:0]);
formal_check(resp[23:0], 24'h200110,
"IDENT after write 0xABCDEF", "P7: IDENT read-only");
// Write again, verify still read-only
$display(" 5b. Write 0x111111 to ADDR 0 (IDENT), read back");
formal_send_frame(mk_write(7'd0, 24'h111111));
formal_send_capture(mk_read(7'd0), resp);
$display(" Wrote 0x111111, read 0x%06h", resp[23:0]);
formal_check(resp[23:0], 24'h200110,
"IDENT after write 0x111111", "P7: IDENT read-only");
// Write yet again to be thorough
$display(" 5c. Write 0x999999 to ADDR 0 (IDENT), read back");
formal_send_frame(mk_write(7'd0, 24'h999999));
formal_send_capture(mk_read(7'd0), resp);
$display(" Wrote 0x999999, read 0x%06h", resp[23:0]);
formal_check(resp[23:0], 24'h200110,
"IDENT after write 0x999999", "P7: IDENT read-only");
#(`SPI_CLK_PERIOD);
end
endtask
//==========================================================================
// Formal Test 6: Sequential Transfers (P10)
// Verify independent frame boundaries and interleaved operations
//==========================================================================
task formal_test_sequential_transfers;
reg [31:0] resp;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Formal Test 6: Sequential Transfers (P10)");
$display("-------------------------------------------------------------");
// Rapid sequential writes
$display(" 6a. Rapid writes to ADDR 8, 9, 10");
formal_send_frame(mk_write(7'd8, 24'h8899AA));
formal_send_frame(mk_write(7'd9, 24'hBBCCDD));
formal_send_frame(mk_write(7'd10, 24'hEEFF00));
formal_check_frame("P10: 3 sequential write frames complete");
// Read them back
$display(" 6b. Read back ADDR 8, 9, 10");
formal_send_capture(mk_read(7'd8), resp);
$display(" ADDR 8 = 0x%06h", resp[23:0]);
formal_check(resp[23:0], 24'h8899AA,
"ADDR 8 read-back", "P10: Sequential write-read");
formal_send_capture(mk_read(7'd9), resp);
$display(" ADDR 9 = 0x%06h", resp[23:0]);
formal_check(resp[23:0], 24'hBBCCDD,
"ADDR 9 read-back", "P10: Sequential write-read");
formal_send_capture(mk_read(7'd10), resp);
$display(" ADDR 10 = 0x%06h", resp[23:0]);
formal_check(resp[23:0], 24'hEEFF00,
"ADDR 10 read-back", "P10: Sequential write-read");
// Interleaved read-then-write
$display(" 6c. Interleaved: Read ADDR 11, Write 0x121212, Read again");
formal_send_capture(mk_read(7'd11), resp);
formal_send_frame(mk_write(7'd11, 24'h121212));
formal_send_capture(mk_read(7'd11), resp);
$display(" After write: ADDR 11 = 0x%06h", resp[23:0]);
formal_check(resp[23:0], 24'h121212,
"ADDR 11 interleaved", "P10: Interleaved R/W");
#(`SPI_CLK_PERIOD);
end
endtask
//==========================================================================
// Formal Test 7: Boundary Conditions (P11)
// Verify min, max, and alternating bit patterns
//==========================================================================
task formal_test_boundary_conditions;
reg [31:0] resp;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Formal Test 7: Boundary Conditions (P11)");
$display("-------------------------------------------------------------");
// Minimum write value (0x000000)
$display(" 7a. Write 0x000000 to ADDR 12, read back");
formal_send_frame(mk_write(7'd12, 24'h000000));
formal_send_capture(mk_read(7'd12), resp);
$display(" Wrote 0x000000, read 0x%06h", resp[23:0]);
formal_check(resp[23:0], 24'h000000,
"ADDR 12 min value", "P11: Boundary - min");
// Maximum write value (0xFFFFFF)
$display(" 7b. Write 0xFFFFFF to ADDR 13, read back");
formal_send_frame(mk_write(7'd13, 24'hFFFFFF));
formal_send_capture(mk_read(7'd13), resp);
$display(" Wrote 0xFFFFFF, read 0x%06h", resp[23:0]);
formal_check(resp[23:0], 24'hFFFFFF,
"ADDR 13 max value", "P11: Boundary - max");
// Alternate bit pattern (0xAAAAAA)
$display(" 7c. Write 0xAAAAAA to ADDR 14, read back");
formal_send_frame(mk_write(7'd14, 24'hAAAAAA));
formal_send_capture(mk_read(7'd14), resp);
$display(" Wrote 0xAAAAAA, read 0x%06h", resp[23:0]);
formal_check(resp[23:0], 24'hAAAAAA,
"ADDR 14 alternate", "P11: Boundary - 0xAAAAAA");
// Inverted alternate bit pattern (0x555555)
$display(" 7d. Write 0x555555 to ADDR 15, read back");
formal_send_frame(mk_write(7'd15, 24'h555555));
formal_send_capture(mk_read(7'd15), resp);
$display(" Wrote 0x555555, read 0x%06h", resp[23:0]);
formal_check(resp[23:0], 24'h555555,
"ADDR 15 inverted alt", "P11: Boundary - 0x555555");
#(`SPI_CLK_PERIOD);
end
endtask
endmodule
CPLD2/BUS_Con.v
+60 -33
View File
@@ -28,7 +28,6 @@ module BUS_Con (
reg [1:0] mosi_sync; reg [1:0] mosi_sync;
wire cs_active; wire cs_active;
wire cs_rise;
wire sclk_rise; // For Sampling MOSI wire sclk_rise; // For Sampling MOSI
wire sclk_fall; // For Shifting MISO wire sclk_fall; // For Shifting MISO
wire mosi_data; wire mosi_data;
@@ -47,7 +46,6 @@ module BUS_Con (
end end
assign cs_active = ~cs_sync[1]; assign cs_active = ~cs_sync[1];
assign cs_rise = (!cs_sync[1] && cs_sync[0]);
// SPI Mode 0: Sample MOSI on Rising, Shift MISO on Falling // SPI Mode 0: Sample MOSI on Rising, Shift MISO on Falling
assign sclk_rise = (!sclk_sync[1] && sclk_sync[0]); assign sclk_rise = (!sclk_sync[1] && sclk_sync[0]);
@@ -61,8 +59,9 @@ module BUS_Con (
reg err_flag; reg err_flag;
reg [1:0] state; reg [1:0] state;
// //
reg [31:0] tx_buffer; // Holds data waiting for the next CS Low
reg [31:0] miso_shift; // The actual shifter reg [31:0] miso_shift; // The actual shifter
reg wr_flag;// Flag: 1=W/0=R
reg miso_loaded;
// Output Registers // Output Registers
reg [6:0] addr_out; reg [6:0] addr_out;
reg [23:0] data_out; reg [23:0] data_out;
@@ -82,77 +81,98 @@ module BUS_Con (
bit_cnt <= 6'd0; bit_cnt <= 6'd0;
data_ready <= 1'b0; data_ready <= 1'b0;
err_flag <= 1'b0; err_flag <= 1'b0;
wr_flag <= 1'b1;
end end
else begin else begin
// Clear data_ready when FSM has consumed the command (CMD_SENT = consumed)
if (state == CMD_SENT) begin
data_ready <= 1'b0; data_ready <= 1'b0;
end
if (cs_active) begin if (cs_active) begin
if (sclk_rise) begin if (sclk_rise) begin
recv_reg <= {recv_reg[30:0], mosi_data}; recv_reg <= {recv_reg[30:0], mosi_data};
bit_cnt <= bit_cnt + 1'b1; bit_cnt <= bit_cnt + 1'b1;
end
else if (cs_rise) begin // After 8 bits: check WR bit (recv_reg[7] = first bit received)
if (bit_cnt == 6'd32) begin // Read (WR=0): set data_ready early so MISO data is prepared
// Write (WR=1): wait for all 32 bits
if (bit_cnt == 'd7) begin
if (recv_reg[6] == 1'b0) begin
// Read command: signal ready after address received
data_ready <= 1'b1; data_ready <= 1'b1;
wr_flag <= 1'b0;
end
else begin
wr_flag <= 1'b1;
end
end
else if (bit_cnt == 6'd31) begin
// Write command complete (32 bits received)
data_ready <= 1'b1;
end
end
else if (!cs_active) begin
data_ready <= 1'b0;
if (bit_cnt == 6'd31) begin
err_flag <= 1'b0; err_flag <= 1'b0;
bit_cnt <= 6'd0; bit_cnt <= 6'd0;
end end
else if (bit_cnt != 0) begin else if (bit_cnt != 0 && bit_cnt != 6'd32) begin
err_flag <= 1'b1; err_flag <= 1'b1;
bit_cnt <= 6'd0; bit_cnt <= 6'd0;
recv_reg <= 'd0; recv_reg <= 'd0;
end end
end end
end end
if (state == DONE) begin else begin
// CS high: reset state
bit_cnt <= 6'd0;
recv_reg <= 'd0; recv_reg <= 'd0;
data_ready <= 1'b0;
end end
end end
end end
// --- 3. MISO (Transmit) Logic --- // --- 3. MISO (Transmit) Logic ---
// Protocol: We shift out 32 bits. // Protocol: We shift out 32 bits.
// Format: [8 bit Status/Padding] + [24 bit i_rdata] // Format: [8'h00 padding] + [24 bit i_rdata]
// Shift MSB out on each falling edge of SCLK (master samples on rising)
// Consolidated: load on first rising edge, shift on falling edges
// Capture data from backend when valid
always @(posedge i_sys_clk) begin
if (!i_rst_n) begin
tx_buffer <= 32'd0;
end else begin
// If backend provides valid read data, store it.
// We pad the top 8 bits with Zeros (or you can put status flags here)
if (i_rvalid) begin
tx_buffer <= {8'h00, i_rdata};
end
end
end
// Shift data out
always @(posedge i_sys_clk) begin always @(posedge i_sys_clk) begin
if (!i_rst_n) begin if (!i_rst_n) begin
miso_shift <= 32'd0; miso_shift <= 32'd0;
end else begin miso_loaded <= 1'b0;
end
else begin
if (!cs_active) begin if (!cs_active) begin
// Pre-load the shifter while CS is High // Reset shifter while CS is High
// This ensures Bit 31 is ready BEFORE the first clock edge miso_shift <= 32'd0;
miso_shift <= tx_buffer; end
end else begin else begin
// Shift on Falling Edge (Master samples on Rising) if (i_rvalid && (bit_cnt == 'd8)) begin
if (sclk_fall) begin miso_shift <= {i_rdata,8'd0};
miso_loaded <= 1'b1;
end
if (miso_loaded && sclk_fall) begin
// Shift out MSB on falling edges (data valid before master's rising-edge sample)
if (bit_cnt > 'd8) begin
miso_shift <= {miso_shift[30:0], 1'b0}; miso_shift <= {miso_shift[30:0], 1'b0};
end end
end end
end end
end end
end
// Tri-state MISO when CS is high (optional, usually good practice) // Tri-state MISO when CS is high (optional, usually good practice)
// If your board doesn't need tristate, just use: assign o_miso = miso_shift[31]; // If your board doesn't need tristate, just use: assign o_miso = miso_shift[31];
assign o_miso = (cs_active) ? miso_shift[31] : 1'bz; assign o_miso = (cs_active) ? miso_shift[31] : 1'bz;
// --- 4. Register Control FSM --- // --- 4. Register Control FSM ---
// Command format: [WR:1b][Addr:7b][Data:24b] = 32 bits
// recv_reg layout after 32 bits: {WR, Addr[6:0], Data[23:0]}
always @(posedge i_sys_clk) begin always @(posedge i_sys_clk) begin
if (!i_rst_n) begin if (!i_rst_n) begin
@@ -165,9 +185,16 @@ module BUS_Con (
case (state) case (state)
IDLE: begin IDLE: begin
if (data_ready) begin if (data_ready) begin
// Extract fields from received command
if (wr_flag == 1'b1) begin
addr_out <= recv_reg[30:24]; addr_out <= recv_reg[30:24];
data_out <= recv_reg[23:0]; data_out <= recv_reg[23:0];
wr_out <= recv_reg[31]; wr_out <= recv_reg[31];
end
else begin
addr_out <= recv_reg[6:0];
wr_out <= recv_reg[7];
end
if (!i_reg_busy) begin if (!i_reg_busy) begin
cmd_valid_out <= 1'b1; cmd_valid_out <= 1'b1;
CPLD2/CPLD_Con.v
+1166 -41
View File
File diff suppressed because it is too large Load Diff
CPLD2/NewExtIns_CPLD2.lpf
+443 -247
View File
@@ -5,6 +5,9 @@ RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk";
BLOCK RESETPATHS ; BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ; BLOCK ASYNCPATHS ;
LOCATE COMP "i_sys_clk" SITE "B9" ; LOCATE COMP "i_sys_clk" SITE "B9" ;
@@ -18,64 +21,64 @@ LOCATE COMP "i_mosi" SITE "AB12" ;
//LOCATE COMP "o_RC_T[29]" SITE "T11" ; //LOCATE COMP "o_RC_T[29]" SITE "T11" ;
//LOCATE COMP "o_RC_T[30]" SITE "U11" ; //LOCATE COMP "o_RC_T[30]" SITE "U11" ;
//LOCATE COMP "o_RC_T[31]" SITE "V11" ; //LOCATE COMP "o_RC_T[31]" SITE "V11" ;
IOBUF PORT "i_cs" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_cs" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "i_mosi" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_mosi" IO_TYPE=LVCMOS33 ;
IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "i_sclk" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_sclk" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ; IOBUF PORT "o_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ;
IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_RC_F[0]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_F[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_F[1]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_F[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "i_sys_clk" DRIVE=NA IO_TYPE=LVCMOS33 SLEWRATE=NA PULLMODE=DOWN ; IOBUF PORT "i_sys_clk" DRIVE=NA IO_TYPE=LVCMOS33 SLEWRATE=NA PULLMODE=DOWN ;
IOBUF PORT "o_RC_F[2]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_F[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_F[3]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_F[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_F[4]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_F[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_F[5]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_F[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_F[6]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_F[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_F[7]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_F[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_S[0]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_S[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_S[1]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_S[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_S[2]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_S[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_S[3]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_S[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_S[4]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_S[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_S[5]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_S[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_S[6]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_S[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_S[7]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_S[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_S[8]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_S[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_S[9]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_S[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_S[10]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_S[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_S[11]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_S[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_S[12]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_S[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_S[13]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_S[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_S[14]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_S[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_S[15]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_S[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[0]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[1]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[2]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[3]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[4]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[5]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[6]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[7]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[8]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[9]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[10]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[11]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[12]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[13]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[14]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[15]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[16]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[16]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[17]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[17]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[18]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[18]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[19]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[19]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[20]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[20]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[21]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[21]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[22]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[22]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[23]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[23]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[24]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[24]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_RC_T[25]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T[25]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_err" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_err" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
BLOCK JTAGPATHS ; BLOCK JTAGPATHS ;
LOCATE COMP "o_RC_F[0]" SITE "U13" ; LOCATE COMP "o_RC_F[0]" SITE "U13" ;
LOCATE COMP "o_RC_F[1]" SITE "U12" ; LOCATE COMP "o_RC_F[1]" SITE "U12" ;
@@ -128,197 +131,390 @@ LOCATE COMP "o_RC_T[23]" SITE "U15" ;
LOCATE COMP "o_RC_T[24]" SITE "T13" ; LOCATE COMP "o_RC_T[24]" SITE "T13" ;
LOCATE COMP "o_RC_T[25]" SITE "AA13" ; LOCATE COMP "o_RC_T[25]" SITE "AA13" ;
LOCATE COMP "o_err" SITE "AB16" ; LOCATE COMP "o_err" SITE "AB16" ;
IOBUF PORT "o_PMU_OC_1[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[0]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[1]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[2]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[3]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[4]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[5]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[6]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[7]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[8]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[9]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[10]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[11]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[12]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[13]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[14]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[15]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[0]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[1]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[2]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[3]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[4]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[5]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[6]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[7]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[8]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[9]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[10]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[11]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[12]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[13]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_1[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[14]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[15]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[0]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[1]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[2]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[3]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[4]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[5]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[6]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[7]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[8]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[9]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[10]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[11]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[12]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[13]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[14]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[15]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[0]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[1]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[2]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[3]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[4]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[5]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[6]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[7]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[8]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[9]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[10]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[11]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[12]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_2[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[13]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_3[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[14]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_3[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[15]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
IOBUF PORT "o_PMU_OC_3[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[8]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_PMU_OC_2[8]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_PMU_OC_3[8]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_PMU_OC_4[8]" IO_TYPE=LVCMOS33 ;
LOCATE COMP "o_PMU_OC_1[8]" SITE "D14" ;
LOCATE COMP "o_PMU_OC_1[9]" SITE "G13" ;
LOCATE COMP "o_PMU_OC_1[10]" SITE "C13" ;
LOCATE COMP "o_PMU_OC_1[11]" SITE "F13" ;
LOCATE COMP "o_PMU_OC_1[12]" SITE "C17" ;
LOCATE COMP "o_PMU_OC_1[13]" SITE "F17" ;
LOCATE COMP "o_PMU_OC_1[14]" SITE "D17" ;
LOCATE COMP "o_PMU_OC_1[15]" SITE "E17" ;
LOCATE COMP "o_PMU_OC_1[24]" SITE "N5" ;
LOCATE COMP "o_PMU_OC_1[25]" SITE "D15" ;
LOCATE COMP "o_PMU_OC_1[26]" SITE "P3" ;
LOCATE COMP "o_PMU_OC_1[27]" SITE "M4" ;
LOCATE COMP "o_PMU_OC_1[28]" SITE "R6" ;
LOCATE COMP "o_PMU_OC_1[29]" SITE "T5" ;
LOCATE COMP "o_PMU_OC_1[30]" SITE "P6" ;
LOCATE COMP "o_PMU_OC_1[31]" SITE "U4" ;
LOCATE COMP "o_PMU_OC_2[8]" SITE "C1" ;
LOCATE COMP "o_PMU_OC_2[9]" SITE "C2" ;
LOCATE COMP "o_PMU_OC_2[10]" SITE "C3" ;
LOCATE COMP "o_PMU_OC_2[11]" SITE "B1" ;
LOCATE COMP "o_PMU_OC_2[12]" SITE "H5" ;
LOCATE COMP "o_PMU_OC_2[13]" SITE "H6" ;
LOCATE COMP "o_PMU_OC_2[14]" SITE "H2" ;
LOCATE COMP "o_PMU_OC_2[15]" SITE "H3" ;
LOCATE COMP "o_PMU_OC_2[24]" SITE "T7" ;
LOCATE COMP "o_PMU_OC_2[25]" SITE "U5" ;
LOCATE COMP "o_PMU_OC_2[26]" SITE "W5" ;
LOCATE COMP "o_PMU_OC_2[27]" SITE "T6" ;
LOCATE COMP "o_PMU_OC_2[28]" SITE "E8" ;
LOCATE COMP "o_PMU_OC_2[29]" SITE "E9" ;
LOCATE COMP "o_PMU_OC_2[30]" SITE "E10" ;
LOCATE COMP "o_PMU_OC_2[31]" SITE "D11" ;
LOCATE COMP "o_PMU_OC_3[8]" SITE "A11" ;
LOCATE COMP "o_PMU_OC_3[9]" SITE "A12" ;
LOCATE COMP "o_PMU_OC_3[10]" SITE "B12" ;
LOCATE COMP "o_PMU_OC_3[11]" SITE "A13" ;
LOCATE COMP "o_PMU_OC_3[12]" SITE "B19" ;
LOCATE COMP "o_PMU_OC_3[13]" SITE "C18" ;
LOCATE COMP "o_PMU_OC_3[14]" SITE "A17" ;
LOCATE COMP "o_PMU_OC_3[15]" SITE "B16" ;
LOCATE COMP "o_PMU_OC_3[24]" SITE "B13" ;
LOCATE COMP "o_PMU_OC_3[25]" SITE "B14" ;
LOCATE COMP "o_PMU_OC_3[26]" SITE "B15" ;
LOCATE COMP "o_PMU_OC_3[27]" SITE "C15" ;
LOCATE COMP "o_PMU_OC_3[28]" SITE "G21" ;
LOCATE COMP "o_PMU_OC_3[29]" SITE "E22" ;
LOCATE COMP "o_PMU_OC_3[30]" SITE "E20" ;
LOCATE COMP "o_PMU_OC_3[31]" SITE "D21" ;
LOCATE COMP "o_PMU_OC_4[8]" SITE "G1" ;
LOCATE COMP "o_PMU_OC_4[9]" SITE "G2" ;
LOCATE COMP "o_PMU_OC_4[10]" SITE "G3" ;
LOCATE COMP "o_PMU_OC_4[11]" SITE "F1" ;
LOCATE COMP "o_PMU_OC_4[12]" SITE "C4" ;
LOCATE COMP "o_PMU_OC_4[13]" SITE "C5" ;
LOCATE COMP "o_PMU_OC_4[14]" SITE "G11" ;
LOCATE COMP "o_PMU_OC_4[15]" SITE "E11" ;
LOCATE COMP "o_PMU_OC_4[24]" SITE "E1" ;
LOCATE COMP "o_PMU_OC_4[25]" SITE "D1" ;
LOCATE COMP "o_PMU_OC_4[26]" SITE "E2" ;
LOCATE COMP "o_PMU_OC_4[27]" SITE "D3" ;
LOCATE COMP "o_PMU_OC_4[28]" SITE "C11" ;
LOCATE COMP "o_PMU_OC_4[29]" SITE "A2" ;
LOCATE COMP "o_PMU_OC_4[30]" SITE "B3" ;
LOCATE COMP "o_PMU_OC_4[31]" SITE "A3" ;
USE PRIMARY NET "i_sys_clk_c" ; USE PRIMARY NET "i_sys_clk_c" ;
IOBUF PORT "o_rvalid" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_rvalid" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
LOCATE COMP "o_miso" SITE "AA14" ;
LOCATE COMP "o_DPS_F_1[0]" SITE "V19" ;
LOCATE COMP "o_DPS_F_1[1]" SITE "L16" ;
LOCATE COMP "o_DPS_F_1[2]" SITE "M18" ;
LOCATE COMP "o_DPS_F_1[3]" SITE "E19" ;
LOCATE COMP "o_DPS_F_1[4]" SITE "N16" ;
LOCATE COMP "o_DPS_F_1[5]" SITE "N17" ;
LOCATE COMP "o_DPS_F_1[6]" SITE "R19" ;
LOCATE COMP "o_DPS_F_1[7]" SITE "K17" ;
LOCATE COMP "o_DPS_F_1[8]" SITE "T19" ;
LOCATE COMP "o_DPS_F_1[9]" SITE "C20" ;
LOCATE COMP "o_DPS_F_1[10]" SITE "P21" ;
LOCATE COMP "o_DPS_F_1[11]" SITE "M17" ;
LOCATE COMP "o_DPS_F_1[12]" SITE "J21" ;
LOCATE COMP "o_DPS_F_1[13]" SITE "F19" ;
LOCATE COMP "o_DPS_F_1[14]" SITE "B20" ;
LOCATE COMP "o_DPS_F_1[15]" SITE "W22" ;
LOCATE COMP "o_DPS_F_2[0]" SITE "B11" ;
LOCATE COMP "o_DPS_F_2[1]" SITE "B8" ;
LOCATE COMP "o_DPS_F_2[2]" SITE "A7" ;
LOCATE COMP "o_DPS_F_2[3]" SITE "W4" ;
LOCATE COMP "o_DPS_F_2[4]" SITE "E7" ;
LOCATE COMP "o_DPS_F_2[5]" SITE "U7" ;
LOCATE COMP "o_DPS_F_2[6]" SITE "E6" ;
LOCATE COMP "o_DPS_F_2[7]" SITE "M5" ;
LOCATE COMP "o_DPS_F_2[8]" SITE "V6" ;
LOCATE COMP "o_DPS_F_2[9]" SITE "N7" ;
LOCATE COMP "o_DPS_F_2[10]" SITE "G6" ;
LOCATE COMP "o_DPS_F_2[11]" SITE "V7" ;
LOCATE COMP "o_DPS_F_2[12]" SITE "F4" ;
LOCATE COMP "o_DPS_F_2[13]" SITE "N3" ;
LOCATE COMP "o_DPS_F_2[14]" SITE "F11" ;
LOCATE COMP "o_DPS_F_2[15]" SITE "P2" ;
LOCATE COMP "o_DPS_F_3[0]" SITE "H20" ;
LOCATE COMP "o_DPS_F_3[1]" SITE "N18" ;
LOCATE COMP "o_DPS_F_3[2]" SITE "G18" ;
LOCATE COMP "o_DPS_F_3[3]" SITE "M21" ;
LOCATE COMP "o_DPS_F_3[4]" SITE "R18" ;
LOCATE COMP "o_DPS_F_3[5]" SITE "R22" ;
LOCATE COMP "o_DPS_F_3[6]" SITE "M22" ;
LOCATE COMP "o_DPS_F_3[7]" SITE "R21" ;
LOCATE COMP "o_DPS_F_3[8]" SITE "U22" ;
LOCATE COMP "o_DPS_F_3[9]" SITE "H17" ;
LOCATE COMP "o_DPS_F_3[10]" SITE "G22" ;
LOCATE COMP "o_DPS_F_3[11]" SITE "L21" ;
LOCATE COMP "o_DPS_F_3[15]" SITE "T18" ;
LOCATE COMP "o_DPS_F_3[14]" SITE "T16" ;
LOCATE COMP "o_DPS_F_3[13]" SITE "L20" ;
LOCATE COMP "o_DPS_F_3[12]" SITE "Y21" ;
LOCATE COMP "o_DPS_F_4[0]" SITE "K7" ;
LOCATE COMP "o_DPS_F_4[1]" SITE "R3" ;
LOCATE COMP "o_DPS_F_4[2]" SITE "K1" ;
LOCATE COMP "o_DPS_F_4[3]" SITE "V3" ;
LOCATE COMP "o_DPS_F_4[4]" SITE "W2" ;
LOCATE COMP "o_DPS_F_4[5]" SITE "T4" ;
LOCATE COMP "o_DPS_F_4[6]" SITE "L4" ;
LOCATE COMP "o_DPS_F_4[7]" SITE "M3" ;
LOCATE COMP "o_DPS_F_4[8]" SITE "K3" ;
LOCATE COMP "o_DPS_F_4[9]" SITE "Y1" ;
LOCATE COMP "o_DPS_F_4[10]" SITE "H1" ;
LOCATE COMP "o_DPS_F_4[11]" SITE "R2" ;
LOCATE COMP "o_DPS_F_4[12]" SITE "N1" ;
LOCATE COMP "o_DPS_F_4[13]" SITE "M2" ;
LOCATE COMP "o_DPS_F_4[14]" SITE "M1" ;
LOCATE COMP "o_DPS_F_4[15]" SITE "W3" ;
IOBUF PORT "o_DPS_F_1[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_1[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_2[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_3[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_F_4[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_1[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_2[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_3[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_DPS_S_4[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
LOCATE COMP "o_DPS_S_1[0]" SITE "M19" ;
LOCATE COMP "o_DPS_S_1[1]" SITE "U19" ;
LOCATE COMP "o_DPS_S_1[2]" SITE "V22" ;
LOCATE COMP "o_DPS_S_1[3]" SITE "AA22" ;
LOCATE COMP "o_DPS_S_1[4]" SITE "V17" ;
LOCATE COMP "o_DPS_S_1[5]" SITE "N20" ;
LOCATE COMP "o_DPS_S_1[6]" SITE "G19" ;
LOCATE COMP "o_DPS_S_1[7]" SITE "U17" ;
LOCATE COMP "o_DPS_S_1[8]" SITE "U18" ;
LOCATE COMP "o_DPS_S_1[9]" SITE "Y20" ;
LOCATE COMP "o_DPS_S_1[10]" SITE "R17" ;
LOCATE COMP "o_DPS_S_1[11]" SITE "P20" ;
LOCATE COMP "o_DPS_S_1[12]" SITE "J17" ;
LOCATE COMP "o_DPS_S_1[13]" SITE "H16" ;
LOCATE COMP "o_DPS_S_1[14]" SITE "R16" ;
LOCATE COMP "o_DPS_S_1[15]" SITE "J19" ;
LOCATE COMP "o_DPS_S_2[0]" SITE "D7" ;
LOCATE COMP "o_DPS_S_2[1]" SITE "D8" ;
LOCATE COMP "o_DPS_S_2[2]" SITE "D9" ;
LOCATE COMP "o_DPS_S_2[3]" SITE "U6" ;
LOCATE COMP "o_DPS_S_2[4]" SITE "J3" ;
LOCATE COMP "o_DPS_S_2[5]" SITE "R7" ;
LOCATE COMP "o_DPS_S_2[6]" SITE "U8" ;
LOCATE COMP "o_DPS_S_2[7]" SITE "E4" ;
LOCATE COMP "o_DPS_S_2[8]" SITE "P7" ;
LOCATE COMP "o_DPS_S_2[9]" SITE "Y2" ;
LOCATE COMP "o_DPS_S_2[10]" SITE "M7" ;
LOCATE COMP "o_DPS_S_2[11]" SITE "G5" ;
LOCATE COMP "o_DPS_S_2[12]" SITE "G7" ;
LOCATE COMP "o_DPS_S_2[13]" SITE "B10" ;
LOCATE COMP "o_DPS_S_2[14]" SITE "AA1" ;
LOCATE COMP "o_DPS_S_2[15]" SITE "L5" ;
LOCATE COMP "o_DPS_S_3[0]" SITE "T20" ;
LOCATE COMP "o_DPS_S_3[1]" SITE "Y22" ;
LOCATE COMP "o_DPS_S_3[2]" SITE "K21" ;
LOCATE COMP "o_DPS_S_3[3]" SITE "M20" ;
LOCATE COMP "o_DPS_S_3[4]" SITE "T22" ;
LOCATE COMP "o_DPS_S_3[5]" SITE "L22" ;
LOCATE COMP "o_DPS_S_3[6]" SITE "P19" ;
LOCATE COMP "o_DPS_S_3[7]" SITE "P18" ;
LOCATE COMP "o_DPS_S_3[8]" SITE "W20" ;
LOCATE COMP "o_DPS_S_3[9]" SITE "N21" ;
LOCATE COMP "o_DPS_S_3[10]" SITE "K22" ;
LOCATE COMP "o_DPS_S_3[11]" SITE "K20" ;
LOCATE COMP "o_DPS_S_3[12]" SITE "R20" ;
LOCATE COMP "o_DPS_S_3[13]" SITE "H21" ;
LOCATE COMP "o_DPS_S_3[14]" SITE "T21" ;
LOCATE COMP "o_DPS_S_3[15]" SITE "N22" ;
LOCATE COMP "o_DPS_S_4[0]" SITE "V2" ;
LOCATE COMP "o_DPS_S_4[1]" SITE "V1" ;
LOCATE COMP "o_DPS_S_4[2]" SITE "W1" ;
LOCATE COMP "o_DPS_S_4[3]" SITE "R1" ;
LOCATE COMP "o_DPS_S_4[4]" SITE "L3" ;
LOCATE COMP "o_DPS_S_4[5]" SITE "K5" ;
LOCATE COMP "o_DPS_S_4[6]" SITE "J5" ;
LOCATE COMP "o_DPS_S_4[7]" SITE "L2" ;
LOCATE COMP "o_DPS_S_4[8]" SITE "K2" ;
LOCATE COMP "o_DPS_S_4[9]" SITE "J4" ;
LOCATE COMP "o_DPS_S_4[10]" SITE "U3" ;
LOCATE COMP "o_DPS_S_4[11]" SITE "L1" ;
LOCATE COMP "o_DPS_S_4[12]" SITE "N2" ;
LOCATE COMP "o_DPS_S_4[13]" SITE "H7" ;
LOCATE COMP "o_DPS_S_4[14]" SITE "J2" ;
LOCATE COMP "o_DPS_S_4[15]" SITE "K6" ;
LOCATE COMP "o_PMU_OC_1[0]" SITE "D14" ;
LOCATE COMP "o_PMU_OC_1[1]" SITE "G13" ;
LOCATE COMP "o_PMU_OC_1[2]" SITE "C13" ;
LOCATE COMP "o_PMU_OC_1[3]" SITE "F13" ;
LOCATE COMP "o_PMU_OC_1[4]" SITE "C17" ;
LOCATE COMP "o_PMU_OC_1[5]" SITE "F17" ;
LOCATE COMP "o_PMU_OC_1[6]" SITE "D17" ;
LOCATE COMP "o_PMU_OC_1[7]" SITE "E17" ;
LOCATE COMP "o_PMU_OC_1[8]" SITE "N5" ;
LOCATE COMP "o_PMU_OC_1[9]" SITE "D15" ;
LOCATE COMP "o_PMU_OC_1[10]" SITE "P3" ;
LOCATE COMP "o_PMU_OC_1[11]" SITE "M4" ;
LOCATE COMP "o_PMU_OC_1[12]" SITE "R6" ;
LOCATE COMP "o_PMU_OC_1[13]" SITE "T5" ;
LOCATE COMP "o_PMU_OC_1[14]" SITE "P6" ;
LOCATE COMP "o_PMU_OC_1[15]" SITE "U4" ;
LOCATE COMP "o_PMU_OC_2[0]" SITE "C1" ;
LOCATE COMP "o_PMU_OC_2[1]" SITE "C2" ;
LOCATE COMP "o_PMU_OC_2[2]" SITE "C3" ;
LOCATE COMP "o_PMU_OC_2[3]" SITE "B1" ;
LOCATE COMP "o_PMU_OC_2[4]" SITE "H5" ;
LOCATE COMP "o_PMU_OC_2[5]" SITE "H6" ;
LOCATE COMP "o_PMU_OC_2[6]" SITE "H2" ;
LOCATE COMP "o_PMU_OC_2[7]" SITE "H3" ;
LOCATE COMP "o_PMU_OC_2[8]" SITE "T7" ;
LOCATE COMP "o_PMU_OC_2[9]" SITE "U5" ;
LOCATE COMP "o_PMU_OC_2[10]" SITE "W5" ;
LOCATE COMP "o_PMU_OC_2[11]" SITE "T6" ;
LOCATE COMP "o_PMU_OC_2[12]" SITE "E8" ;
LOCATE COMP "o_PMU_OC_2[13]" SITE "E9" ;
LOCATE COMP "o_PMU_OC_2[14]" SITE "E10" ;
LOCATE COMP "o_PMU_OC_2[15]" SITE "D11" ;
LOCATE COMP "o_PMU_OC_3[0]" SITE "A11" ;
LOCATE COMP "o_PMU_OC_3[1]" SITE "A12" ;
LOCATE COMP "o_PMU_OC_3[2]" SITE "B12" ;
LOCATE COMP "o_PMU_OC_3[3]" SITE "A13" ;
LOCATE COMP "o_PMU_OC_3[4]" SITE "B19" ;
LOCATE COMP "o_PMU_OC_3[5]" SITE "C18" ;
LOCATE COMP "o_PMU_OC_3[6]" SITE "A17" ;
LOCATE COMP "o_PMU_OC_3[7]" SITE "B16" ;
LOCATE COMP "o_PMU_OC_3[8]" SITE "B13" ;
LOCATE COMP "o_PMU_OC_3[9]" SITE "B14" ;
LOCATE COMP "o_PMU_OC_3[10]" SITE "B15" ;
LOCATE COMP "o_PMU_OC_3[11]" SITE "C15" ;
LOCATE COMP "o_PMU_OC_3[12]" SITE "G21" ;
LOCATE COMP "o_PMU_OC_3[13]" SITE "E22" ;
LOCATE COMP "o_PMU_OC_3[14]" SITE "E20" ;
LOCATE COMP "o_PMU_OC_3[15]" SITE "D21" ;
LOCATE COMP "o_PMU_OC_4[0]" SITE "G1" ;
LOCATE COMP "o_PMU_OC_4[1]" SITE "G2" ;
LOCATE COMP "o_PMU_OC_4[2]" SITE "G3" ;
LOCATE COMP "o_PMU_OC_4[3]" SITE "F1" ;
LOCATE COMP "o_PMU_OC_4[4]" SITE "C4" ;
LOCATE COMP "o_PMU_OC_4[5]" SITE "C5" ;
LOCATE COMP "o_PMU_OC_4[6]" SITE "G11" ;
LOCATE COMP "o_PMU_OC_4[7]" SITE "E11" ;
LOCATE COMP "o_PMU_OC_4[8]" SITE "E1" ;
LOCATE COMP "o_PMU_OC_4[9]" SITE "D1" ;
LOCATE COMP "o_PMU_OC_4[10]" SITE "E2" ;
LOCATE COMP "o_PMU_OC_4[11]" SITE "D3" ;
LOCATE COMP "o_PMU_OC_4[12]" SITE "C11" ;
LOCATE COMP "o_PMU_OC_4[13]" SITE "A2" ;
LOCATE COMP "o_PMU_OC_4[14]" SITE "B3" ;
LOCATE COMP "o_PMU_OC_4[15]" SITE "A3" ;
CPLD2/Reg_file.v
+1 -1
View File
@@ -33,7 +33,7 @@ module Reg_file (
// --- Parameters --- // --- Parameters ---
localparam REG_COUNT = 16; localparam REG_COUNT = 16;
localparam [23:0] localparam [23:0]
IDENT = 24'h400000 | 12'b0001_0001_0000, //CPLD2==1,version=1.1.0 IDENT = 24'h400000 | 12'b0001_0001_0010, //CPLD2==1,version=1.1.2
STATE_INIT = 24'h800000; STATE_INIT = 24'h800000;
// State Machine Definition // State Machine Definition
CPLD2/RelayConTop.v
+36 -35
View File
@@ -14,19 +14,25 @@ module RelayConTop (
output [7:0]o_RC_F, //Ref: Schematic output [7:0]o_RC_F, //Ref: Schematic
output [15:0]o_RC_S, output [15:0]o_RC_S,
output [25:0]o_RC_T, //Actually ONLY 25 pin(rest is on CPLD1) output [25:0]o_RC_T, //Actually ONLY 25 pin(rest is on CPLD1)
//output [3:0] o_OC_x09, //PMU OC Control
//output [3:0] o_OC_x25, output [15:0]o_PMU_OC_1 ,
output [31:0]o_PMU_OC_1 , output [15:0]o_PMU_OC_2 ,
output [31:0]o_PMU_OC_2 , output [15:0]o_PMU_OC_3 ,
output [31:0]o_PMU_OC_3 , output [15:0]o_PMU_OC_4 ,
output [31:0]o_PMU_OC_4 //DPS OC Control
output [15:0]o_DPS_F_1 ,
output [15:0]o_DPS_S_1 ,
output [15:0]o_DPS_F_2 ,
output [15:0]o_DPS_S_2 ,
output [15:0]o_DPS_F_3 ,
output [15:0]o_DPS_S_3 ,
output [15:0]o_DPS_F_4 ,
output [15:0]o_DPS_S_4
); );
wire [7:0] RC_F; wire [7:0] RC_F;
wire [15:0] RC_S; wire [15:0] RC_S;
wire [31:0] RC_T; wire [31:0] RC_T;
wire [3:0]OC_x09 ;
wire [3:0]OC_x25 ;
wire [23:0]r_data ; wire [23:0]r_data ;
wire [23:0]w_data ; wire [23:0]w_data ;
@@ -57,6 +63,12 @@ module RelayConTop (
wire [31:0]PMU_OC_3 ; wire [31:0]PMU_OC_3 ;
wire [31:0]PMU_OC_4 ; wire [31:0]PMU_OC_4 ;
//DPS PerChannel Force/Sense Control
wire [15:0]DPS_FS_1 ;
wire [15:0]DPS_FS_2 ;
wire [15:0]DPS_FS_3 ;
wire [15:0]DPS_FS_4 ;
wire con_rvalid; wire con_rvalid;
wire con_done; wire con_done;
@@ -120,12 +132,14 @@ BUS_Con BUS_Con_2(
.o_PMU_OC_2(PMU_OC_2), .o_PMU_OC_2(PMU_OC_2),
.o_PMU_OC_3(PMU_OC_3), .o_PMU_OC_3(PMU_OC_3),
.o_PMU_OC_4(PMU_OC_4), .o_PMU_OC_4(PMU_OC_4),
.o_DPS_FS_1(DPS_FS_1),
.o_DPS_FS_2(DPS_FS_2),
.o_DPS_FS_3(DPS_FS_3),
.o_DPS_FS_4(DPS_FS_4),
.o_con_done(con_done), .o_con_done(con_done),
.o_RC_F(RC_F), .o_RC_F(RC_F),
.o_RC_S(RC_S), .o_RC_S(RC_S),
.o_RC_T(RC_T), .o_RC_T(RC_T),
.o_OC_x09(OC_x09),
.o_OC_x25(OC_x25),
.o_err(cpld_err_flag) .o_err(cpld_err_flag)
); );
@@ -134,32 +148,19 @@ BUS_Con BUS_Con_2(
assign o_RC_S = RC_S; assign o_RC_S = RC_S;
assign o_RC_T = RC_T[25:0]; assign o_RC_T = RC_T[25:0];
assign o_PMU_OC_1[8] = OC_x09[0]; assign o_PMU_OC_1 = {PMU_OC_1[31:24],PMU_OC_1[15:8]} ;
assign o_PMU_OC_2[8] = OC_x09[1]; assign o_PMU_OC_2 = {PMU_OC_2[31:24],PMU_OC_2[15:8]} ;
assign o_PMU_OC_3[8] = OC_x09[2]; assign o_PMU_OC_3 = {PMU_OC_3[31:24],PMU_OC_3[15:8]} ;
assign o_PMU_OC_4[8] = OC_x09[3]; assign o_PMU_OC_4 = {PMU_OC_4[31:24],PMU_OC_4[15:8]} ;
assign o_PMU_OC_1[24] = OC_x25[0];
assign o_PMU_OC_2[24] = OC_x25[1];
assign o_PMU_OC_3[24] = OC_x25[2];
assign o_PMU_OC_4[24] = OC_x25[3];
assign o_PMU_OC_1[7:0] = PMU_OC_1[7:0];
assign o_PMU_OC_1[23:9] = PMU_OC_1[23:8];
assign o_PMU_OC_1[31:25] = PMU_OC_1[31:25];
assign o_PMU_OC_2[7:0] = PMU_OC_2[7:0];
assign o_PMU_OC_2[23:9] = PMU_OC_2[23:9];
assign o_PMU_OC_2[31:25] = PMU_OC_2[31:25];
assign o_PMU_OC_3[7:0] = PMU_OC_3[7:0];
assign o_PMU_OC_3[23:9] = PMU_OC_3[23:9];
assign o_PMU_OC_3[31:25]= PMU_OC_3[31:25];
assign o_PMU_OC_4[7:0] = PMU_OC_4[7:0];
assign o_PMU_OC_4[23:9] = PMU_OC_4[23:9];
assign o_PMU_OC_4[31:25] = PMU_OC_4[31:25];
assign o_DPS_F_1 = DPS_FS_1;
assign o_DPS_S_1 = DPS_FS_1;
assign o_DPS_F_2 = DPS_FS_2;
assign o_DPS_S_2 = DPS_FS_2;
assign o_DPS_F_3 = DPS_FS_3;
assign o_DPS_S_3 = DPS_FS_3;
assign o_DPS_F_4 = DPS_FS_4;
assign o_DPS_S_4 = DPS_FS_4;
assign o_err = bus_err_flag || reg_err_flag || cpld_err_flag; assign o_err = bus_err_flag || reg_err_flag || cpld_err_flag;
CPLD2/debug.rvl
+148 -50
View File
@@ -1,10 +1,10 @@
<Project ModBy="Inserter" SigType="0" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD2/debug.rvl" Date="2026-05-26"> <Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD2/debug.rvl" Date="2026-06-16">
<IP Version="1_6_042617"/> <IP Version="1_6_042617"/>
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD2"/> <Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD2"/>
<Core InsertDataset="0" Insert="1" Reveal_sig="695532641" Name="RelayConTop_LA0" ID="0"> <Core InsertDataset="0" Insert="1" Reveal_sig="698409493" Name="RelayConTop_LA0" ID="0">
<Setting> <Setting>
<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/> <Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/> <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="1024"/>
<Capture Mode="0" MinSamplesPerTrig="8"/> <Capture Mode="0" MinSamplesPerTrig="8"/>
<Event CntEnable="0" MaxEventCnt="8"/> <Event CntEnable="0" MaxEventCnt="8"/>
<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_RelayConTop_LA0_net"/> <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_RelayConTop_LA0_net"/>
@@ -12,56 +12,154 @@
</Setting> </Setting>
<Dataset Name="Base"> <Dataset Name="Base">
<Trace> <Trace>
<Sig Type="SIG" Name="i_rst_n"/> <Bus Name="DPS_FS_1">
<Sig Type="SIG" Name="BUS_Con_2/i_cs"/> <Sig Type="SIG" Name="DPS_FS_1:0"/>
<Sig Type="SIG" Name="BUS_Con_2/i_sclk"/> <Sig Type="SIG" Name="DPS_FS_1:1"/>
<Sig Type="SIG" Name="BUS_Con_2/i_mosi"/> <Sig Type="SIG" Name="DPS_FS_1:2"/>
<Sig Type="SIG" Name="BUS_Con_2/i_reg_busy"/> <Sig Type="SIG" Name="DPS_FS_1:3"/>
<Sig Type="SIG" Name="CPLD_Reg_2/o_exec"/> <Sig Type="SIG" Name="DPS_FS_1:4"/>
<Bus Name="RC_T"> <Sig Type="SIG" Name="DPS_FS_1:5"/>
<Sig Type="SIG" Name="RC_T:0"/> <Sig Type="SIG" Name="DPS_FS_1:6"/>
<Sig Type="SIG" Name="RC_T:1"/> <Sig Type="SIG" Name="DPS_FS_1:7"/>
<Sig Type="SIG" Name="RC_T:2"/> <Sig Type="SIG" Name="DPS_FS_1:8"/>
<Sig Type="SIG" Name="RC_T:3"/> <Sig Type="SIG" Name="DPS_FS_1:9"/>
<Sig Type="SIG" Name="RC_T:4"/> <Sig Type="SIG" Name="DPS_FS_1:10"/>
<Sig Type="SIG" Name="RC_T:5"/> <Sig Type="SIG" Name="DPS_FS_1:11"/>
<Sig Type="SIG" Name="RC_T:6"/> <Sig Type="SIG" Name="DPS_FS_1:12"/>
<Sig Type="SIG" Name="RC_T:7"/> <Sig Type="SIG" Name="DPS_FS_1:13"/>
<Sig Type="SIG" Name="RC_T:8"/> <Sig Type="SIG" Name="DPS_FS_1:14"/>
<Sig Type="SIG" Name="RC_T:9"/> <Sig Type="SIG" Name="DPS_FS_1:15"/>
<Sig Type="SIG" Name="RC_T:10"/> </Bus>
<Sig Type="SIG" Name="RC_T:11"/> <Bus Name="DPS_FS_2">
<Sig Type="SIG" Name="RC_T:12"/> <Sig Type="SIG" Name="DPS_FS_2:0"/>
<Sig Type="SIG" Name="RC_T:13"/> <Sig Type="SIG" Name="DPS_FS_2:1"/>
<Sig Type="SIG" Name="RC_T:14"/> <Sig Type="SIG" Name="DPS_FS_2:2"/>
<Sig Type="SIG" Name="RC_T:15"/> <Sig Type="SIG" Name="DPS_FS_2:3"/>
<Sig Type="SIG" Name="RC_T:16"/> <Sig Type="SIG" Name="DPS_FS_2:4"/>
<Sig Type="SIG" Name="RC_T:17"/> <Sig Type="SIG" Name="DPS_FS_2:5"/>
<Sig Type="SIG" Name="RC_T:18"/> <Sig Type="SIG" Name="DPS_FS_2:6"/>
<Sig Type="SIG" Name="RC_T:19"/> <Sig Type="SIG" Name="DPS_FS_2:7"/>
<Sig Type="SIG" Name="RC_T:20"/> <Sig Type="SIG" Name="DPS_FS_2:8"/>
<Sig Type="SIG" Name="RC_T:21"/> <Sig Type="SIG" Name="DPS_FS_2:9"/>
<Sig Type="SIG" Name="RC_T:22"/> <Sig Type="SIG" Name="DPS_FS_2:10"/>
<Sig Type="SIG" Name="RC_T:23"/> <Sig Type="SIG" Name="DPS_FS_2:11"/>
<Sig Type="SIG" Name="RC_T:24"/> <Sig Type="SIG" Name="DPS_FS_2:12"/>
<Sig Type="SIG" Name="RC_T:25"/> <Sig Type="SIG" Name="DPS_FS_2:13"/>
<Sig Type="SIG" Name="RC_T:26"/> <Sig Type="SIG" Name="DPS_FS_2:14"/>
<Sig Type="SIG" Name="RC_T:27"/> <Sig Type="SIG" Name="DPS_FS_2:15"/>
<Sig Type="SIG" Name="RC_T:28"/> </Bus>
<Sig Type="SIG" Name="RC_T:29"/> <Bus Name="DPS_FS_3">
<Sig Type="SIG" Name="RC_T:30"/> <Sig Type="SIG" Name="DPS_FS_3:0"/>
<Sig Type="SIG" Name="RC_T:31"/> <Sig Type="SIG" Name="DPS_FS_3:1"/>
<Sig Type="SIG" Name="DPS_FS_3:2"/>
<Sig Type="SIG" Name="DPS_FS_3:3"/>
<Sig Type="SIG" Name="DPS_FS_3:4"/>
<Sig Type="SIG" Name="DPS_FS_3:5"/>
<Sig Type="SIG" Name="DPS_FS_3:6"/>
<Sig Type="SIG" Name="DPS_FS_3:7"/>
<Sig Type="SIG" Name="DPS_FS_3:8"/>
<Sig Type="SIG" Name="DPS_FS_3:9"/>
<Sig Type="SIG" Name="DPS_FS_3:10"/>
<Sig Type="SIG" Name="DPS_FS_3:11"/>
<Sig Type="SIG" Name="DPS_FS_3:12"/>
<Sig Type="SIG" Name="DPS_FS_3:13"/>
<Sig Type="SIG" Name="DPS_FS_3:14"/>
<Sig Type="SIG" Name="DPS_FS_3:15"/>
</Bus>
<Bus Name="DPS_FS_4">
<Sig Type="SIG" Name="DPS_FS_4:0"/>
<Sig Type="SIG" Name="DPS_FS_4:1"/>
<Sig Type="SIG" Name="DPS_FS_4:2"/>
<Sig Type="SIG" Name="DPS_FS_4:3"/>
<Sig Type="SIG" Name="DPS_FS_4:4"/>
<Sig Type="SIG" Name="DPS_FS_4:5"/>
<Sig Type="SIG" Name="DPS_FS_4:6"/>
<Sig Type="SIG" Name="DPS_FS_4:7"/>
<Sig Type="SIG" Name="DPS_FS_4:8"/>
<Sig Type="SIG" Name="DPS_FS_4:9"/>
<Sig Type="SIG" Name="DPS_FS_4:10"/>
<Sig Type="SIG" Name="DPS_FS_4:11"/>
<Sig Type="SIG" Name="DPS_FS_4:12"/>
<Sig Type="SIG" Name="DPS_FS_4:13"/>
<Sig Type="SIG" Name="DPS_FS_4:14"/>
<Sig Type="SIG" Name="DPS_FS_4:15"/>
</Bus>
<Bus Name="o_PMU_OC_1">
<Sig Type="SIG" Name="o_PMU_OC_1:0"/>
<Sig Type="SIG" Name="o_PMU_OC_1:1"/>
<Sig Type="SIG" Name="o_PMU_OC_1:2"/>
<Sig Type="SIG" Name="o_PMU_OC_1:3"/>
<Sig Type="SIG" Name="o_PMU_OC_1:4"/>
<Sig Type="SIG" Name="o_PMU_OC_1:5"/>
<Sig Type="SIG" Name="o_PMU_OC_1:6"/>
<Sig Type="SIG" Name="o_PMU_OC_1:7"/>
<Sig Type="SIG" Name="o_PMU_OC_1:8"/>
<Sig Type="SIG" Name="o_PMU_OC_1:9"/>
<Sig Type="SIG" Name="o_PMU_OC_1:10"/>
<Sig Type="SIG" Name="o_PMU_OC_1:11"/>
<Sig Type="SIG" Name="o_PMU_OC_1:12"/>
<Sig Type="SIG" Name="o_PMU_OC_1:13"/>
<Sig Type="SIG" Name="o_PMU_OC_1:14"/>
<Sig Type="SIG" Name="o_PMU_OC_1:15"/>
</Bus>
<Bus Name="o_PMU_OC_2">
<Sig Type="SIG" Name="o_PMU_OC_2:0"/>
<Sig Type="SIG" Name="o_PMU_OC_2:1"/>
<Sig Type="SIG" Name="o_PMU_OC_2:2"/>
<Sig Type="SIG" Name="o_PMU_OC_2:3"/>
<Sig Type="SIG" Name="o_PMU_OC_2:4"/>
<Sig Type="SIG" Name="o_PMU_OC_2:5"/>
<Sig Type="SIG" Name="o_PMU_OC_2:6"/>
<Sig Type="SIG" Name="o_PMU_OC_2:7"/>
<Sig Type="SIG" Name="o_PMU_OC_2:8"/>
<Sig Type="SIG" Name="o_PMU_OC_2:9"/>
<Sig Type="SIG" Name="o_PMU_OC_2:10"/>
<Sig Type="SIG" Name="o_PMU_OC_2:11"/>
<Sig Type="SIG" Name="o_PMU_OC_2:12"/>
<Sig Type="SIG" Name="o_PMU_OC_2:13"/>
<Sig Type="SIG" Name="o_PMU_OC_2:14"/>
<Sig Type="SIG" Name="o_PMU_OC_2:15"/>
</Bus>
<Bus Name="o_PMU_OC_3">
<Sig Type="SIG" Name="o_PMU_OC_3:0"/>
<Sig Type="SIG" Name="o_PMU_OC_3:1"/>
<Sig Type="SIG" Name="o_PMU_OC_3:2"/>
<Sig Type="SIG" Name="o_PMU_OC_3:3"/>
<Sig Type="SIG" Name="o_PMU_OC_3:4"/>
<Sig Type="SIG" Name="o_PMU_OC_3:5"/>
<Sig Type="SIG" Name="o_PMU_OC_3:6"/>
<Sig Type="SIG" Name="o_PMU_OC_3:7"/>
<Sig Type="SIG" Name="o_PMU_OC_3:8"/>
<Sig Type="SIG" Name="o_PMU_OC_3:9"/>
<Sig Type="SIG" Name="o_PMU_OC_3:10"/>
<Sig Type="SIG" Name="o_PMU_OC_3:11"/>
<Sig Type="SIG" Name="o_PMU_OC_3:12"/>
<Sig Type="SIG" Name="o_PMU_OC_3:13"/>
<Sig Type="SIG" Name="o_PMU_OC_3:14"/>
<Sig Type="SIG" Name="o_PMU_OC_3:15"/>
</Bus>
<Bus Name="o_PMU_OC_4">
<Sig Type="SIG" Name="o_PMU_OC_4:0"/>
<Sig Type="SIG" Name="o_PMU_OC_4:1"/>
<Sig Type="SIG" Name="o_PMU_OC_4:2"/>
<Sig Type="SIG" Name="o_PMU_OC_4:3"/>
<Sig Type="SIG" Name="o_PMU_OC_4:4"/>
<Sig Type="SIG" Name="o_PMU_OC_4:5"/>
<Sig Type="SIG" Name="o_PMU_OC_4:6"/>
<Sig Type="SIG" Name="o_PMU_OC_4:7"/>
<Sig Type="SIG" Name="o_PMU_OC_4:8"/>
<Sig Type="SIG" Name="o_PMU_OC_4:9"/>
<Sig Type="SIG" Name="o_PMU_OC_4:10"/>
<Sig Type="SIG" Name="o_PMU_OC_4:11"/>
<Sig Type="SIG" Name="o_PMU_OC_4:12"/>
<Sig Type="SIG" Name="o_PMU_OC_4:13"/>
<Sig Type="SIG" Name="o_PMU_OC_4:14"/>
<Sig Type="SIG" Name="o_PMU_OC_4:15"/>
</Bus> </Bus>
<Sig Type="SIG" Name="BUS_Con_2/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_2/err_flag"/>
<Sig Type="SIG" Name="CPLD_Reg_2/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_2/i_con_exec"/>
</Trace> </Trace>
<Trigger> <Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="i_cs,"/> <TU Serialbits="0" Type="0" ID="1" Sig="con_exec,"/>
<TU Serialbits="0" Type="0" ID="2" Sig="i_rst_n,"/> <TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
</Trigger> </Trigger>
</Dataset> </Dataset>
</Core> </Core>
CPLD2/debug.rvs
+148 -50
View File
@@ -1,62 +1,160 @@
<Project ModBy="Inserter" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD2/debug.rvl" Date="2026-05-26"> <Project ModBy="Inserter" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD2/debug.rvl" Date="2026-06-16">
<Core Name="RelayConTop_LA0"> <Core Name="RelayConTop_LA0">
<Setting> <Setting>
<Capture SamplesPerTrig="2048" NumTrigsCap="1"/> <Capture SamplesPerTrig="1" NumTrigsCap=""/>
<Event EventCnt="0" CntEnableRun="0"/> <Event EventCnt="" CntEnableRun=""/>
<TrigSetting PreTrgSamples="" AND_ALL="0" PostTrgSamples="" TURadix="0"/> <TrigSetting PreTrgSamples="" AND_ALL="" PostTrgSamples="" TURadix="0"/>
</Setting> </Setting>
<Dataset Name="Base"> <Dataset Name="Base">
<Trace> <Trace>
<Sig Name="i_rst_n"/> <Bus Name="DPS_FS_1" Radix="0">
<Sig Name="BUS_Con_2/i_cs"/> <Sig Name="DPS_FS_1:0"/>
<Sig Name="BUS_Con_2/i_sclk"/> <Sig Name="DPS_FS_1:1"/>
<Sig Name="BUS_Con_2/i_mosi"/> <Sig Name="DPS_FS_1:2"/>
<Sig Name="BUS_Con_2/i_reg_busy"/> <Sig Name="DPS_FS_1:3"/>
<Sig Name="CPLD_Reg_2/o_exec"/> <Sig Name="DPS_FS_1:4"/>
<Bus Name="RC_T" Radix="0"> <Sig Name="DPS_FS_1:5"/>
<Sig Name="RC_T:0"/> <Sig Name="DPS_FS_1:6"/>
<Sig Name="RC_T:1"/> <Sig Name="DPS_FS_1:7"/>
<Sig Name="RC_T:2"/> <Sig Name="DPS_FS_1:8"/>
<Sig Name="RC_T:3"/> <Sig Name="DPS_FS_1:9"/>
<Sig Name="RC_T:4"/> <Sig Name="DPS_FS_1:10"/>
<Sig Name="RC_T:5"/> <Sig Name="DPS_FS_1:11"/>
<Sig Name="RC_T:6"/> <Sig Name="DPS_FS_1:12"/>
<Sig Name="RC_T:7"/> <Sig Name="DPS_FS_1:13"/>
<Sig Name="RC_T:8"/> <Sig Name="DPS_FS_1:14"/>
<Sig Name="RC_T:9"/> <Sig Name="DPS_FS_1:15"/>
<Sig Name="RC_T:10"/> </Bus>
<Sig Name="RC_T:11"/> <Bus Name="DPS_FS_2" Radix="0">
<Sig Name="RC_T:12"/> <Sig Name="DPS_FS_2:0"/>
<Sig Name="RC_T:13"/> <Sig Name="DPS_FS_2:1"/>
<Sig Name="RC_T:14"/> <Sig Name="DPS_FS_2:2"/>
<Sig Name="RC_T:15"/> <Sig Name="DPS_FS_2:3"/>
<Sig Name="RC_T:16"/> <Sig Name="DPS_FS_2:4"/>
<Sig Name="RC_T:17"/> <Sig Name="DPS_FS_2:5"/>
<Sig Name="RC_T:18"/> <Sig Name="DPS_FS_2:6"/>
<Sig Name="RC_T:19"/> <Sig Name="DPS_FS_2:7"/>
<Sig Name="RC_T:20"/> <Sig Name="DPS_FS_2:8"/>
<Sig Name="RC_T:21"/> <Sig Name="DPS_FS_2:9"/>
<Sig Name="RC_T:22"/> <Sig Name="DPS_FS_2:10"/>
<Sig Name="RC_T:23"/> <Sig Name="DPS_FS_2:11"/>
<Sig Name="RC_T:24"/> <Sig Name="DPS_FS_2:12"/>
<Sig Name="RC_T:25"/> <Sig Name="DPS_FS_2:13"/>
<Sig Name="RC_T:26"/> <Sig Name="DPS_FS_2:14"/>
<Sig Name="RC_T:27"/> <Sig Name="DPS_FS_2:15"/>
<Sig Name="RC_T:28"/> </Bus>
<Sig Name="RC_T:29"/> <Bus Name="DPS_FS_3" Radix="0">
<Sig Name="RC_T:30"/> <Sig Name="DPS_FS_3:0"/>
<Sig Name="RC_T:31"/> <Sig Name="DPS_FS_3:1"/>
<Sig Name="DPS_FS_3:2"/>
<Sig Name="DPS_FS_3:3"/>
<Sig Name="DPS_FS_3:4"/>
<Sig Name="DPS_FS_3:5"/>
<Sig Name="DPS_FS_3:6"/>
<Sig Name="DPS_FS_3:7"/>
<Sig Name="DPS_FS_3:8"/>
<Sig Name="DPS_FS_3:9"/>
<Sig Name="DPS_FS_3:10"/>
<Sig Name="DPS_FS_3:11"/>
<Sig Name="DPS_FS_3:12"/>
<Sig Name="DPS_FS_3:13"/>
<Sig Name="DPS_FS_3:14"/>
<Sig Name="DPS_FS_3:15"/>
</Bus>
<Bus Name="DPS_FS_4" Radix="0">
<Sig Name="DPS_FS_4:0"/>
<Sig Name="DPS_FS_4:1"/>
<Sig Name="DPS_FS_4:2"/>
<Sig Name="DPS_FS_4:3"/>
<Sig Name="DPS_FS_4:4"/>
<Sig Name="DPS_FS_4:5"/>
<Sig Name="DPS_FS_4:6"/>
<Sig Name="DPS_FS_4:7"/>
<Sig Name="DPS_FS_4:8"/>
<Sig Name="DPS_FS_4:9"/>
<Sig Name="DPS_FS_4:10"/>
<Sig Name="DPS_FS_4:11"/>
<Sig Name="DPS_FS_4:12"/>
<Sig Name="DPS_FS_4:13"/>
<Sig Name="DPS_FS_4:14"/>
<Sig Name="DPS_FS_4:15"/>
</Bus>
<Bus Name="o_PMU_OC_1" Radix="0">
<Sig Name="o_PMU_OC_1:0"/>
<Sig Name="o_PMU_OC_1:1"/>
<Sig Name="o_PMU_OC_1:2"/>
<Sig Name="o_PMU_OC_1:3"/>
<Sig Name="o_PMU_OC_1:4"/>
<Sig Name="o_PMU_OC_1:5"/>
<Sig Name="o_PMU_OC_1:6"/>
<Sig Name="o_PMU_OC_1:7"/>
<Sig Name="o_PMU_OC_1:8"/>
<Sig Name="o_PMU_OC_1:9"/>
<Sig Name="o_PMU_OC_1:10"/>
<Sig Name="o_PMU_OC_1:11"/>
<Sig Name="o_PMU_OC_1:12"/>
<Sig Name="o_PMU_OC_1:13"/>
<Sig Name="o_PMU_OC_1:14"/>
<Sig Name="o_PMU_OC_1:15"/>
</Bus>
<Bus Name="o_PMU_OC_2" Radix="0">
<Sig Name="o_PMU_OC_2:0"/>
<Sig Name="o_PMU_OC_2:1"/>
<Sig Name="o_PMU_OC_2:2"/>
<Sig Name="o_PMU_OC_2:3"/>
<Sig Name="o_PMU_OC_2:4"/>
<Sig Name="o_PMU_OC_2:5"/>
<Sig Name="o_PMU_OC_2:6"/>
<Sig Name="o_PMU_OC_2:7"/>
<Sig Name="o_PMU_OC_2:8"/>
<Sig Name="o_PMU_OC_2:9"/>
<Sig Name="o_PMU_OC_2:10"/>
<Sig Name="o_PMU_OC_2:11"/>
<Sig Name="o_PMU_OC_2:12"/>
<Sig Name="o_PMU_OC_2:13"/>
<Sig Name="o_PMU_OC_2:14"/>
<Sig Name="o_PMU_OC_2:15"/>
</Bus>
<Bus Name="o_PMU_OC_3" Radix="0">
<Sig Name="o_PMU_OC_3:0"/>
<Sig Name="o_PMU_OC_3:1"/>
<Sig Name="o_PMU_OC_3:2"/>
<Sig Name="o_PMU_OC_3:3"/>
<Sig Name="o_PMU_OC_3:4"/>
<Sig Name="o_PMU_OC_3:5"/>
<Sig Name="o_PMU_OC_3:6"/>
<Sig Name="o_PMU_OC_3:7"/>
<Sig Name="o_PMU_OC_3:8"/>
<Sig Name="o_PMU_OC_3:9"/>
<Sig Name="o_PMU_OC_3:10"/>
<Sig Name="o_PMU_OC_3:11"/>
<Sig Name="o_PMU_OC_3:12"/>
<Sig Name="o_PMU_OC_3:13"/>
<Sig Name="o_PMU_OC_3:14"/>
<Sig Name="o_PMU_OC_3:15"/>
</Bus>
<Bus Name="o_PMU_OC_4" Radix="0">
<Sig Name="o_PMU_OC_4:0"/>
<Sig Name="o_PMU_OC_4:1"/>
<Sig Name="o_PMU_OC_4:2"/>
<Sig Name="o_PMU_OC_4:3"/>
<Sig Name="o_PMU_OC_4:4"/>
<Sig Name="o_PMU_OC_4:5"/>
<Sig Name="o_PMU_OC_4:6"/>
<Sig Name="o_PMU_OC_4:7"/>
<Sig Name="o_PMU_OC_4:8"/>
<Sig Name="o_PMU_OC_4:9"/>
<Sig Name="o_PMU_OC_4:10"/>
<Sig Name="o_PMU_OC_4:11"/>
<Sig Name="o_PMU_OC_4:12"/>
<Sig Name="o_PMU_OC_4:13"/>
<Sig Name="o_PMU_OC_4:14"/>
<Sig Name="o_PMU_OC_4:15"/>
</Bus> </Bus>
<Sig Name="BUS_Con_2/err_flag"/>
<Sig Name="CPLD_Con_2/err_flag"/>
<Sig Name="CPLD_Reg_2/err_flag"/>
<Sig Name="CPLD_Con_2/i_con_exec"/>
</Trace> </Trace>
<Trigger> <Trigger>
<TU Operator="7" Name="TU1" ID="1" Value="0" Radix="0"/> <TU Operator="6" Name="TU1" ID="1" Value="0" Radix="0"/>
<TU Operator="6" Name="TU2" ID="2" Value="0" Radix="0"/>
<TE Enable="1" Expression="TU1" Name="TE1" ID="1"/> <TE Enable="1" Expression="TU1" Name="TE1" ID="1"/>
<TE Enable="1" Expression="TU2" Name="TE2" ID="2"/>
</Trigger> </Trigger>
</Dataset> </Dataset>
</Core> </Core>
CPLD2/impl1/NewExtIns_CPLD2_impl1.areasrr
-162
View File
@@ -1,162 +0,0 @@
----------------------------------------------------------------------
Report for cell RelayConTop.verilog
Register bits: 1275 of 6864 (19%)
PIC Latch: 0
I/O cells: 187
Cell usage:
cell count Res Usage(%)
CCU2D 59 100.0
FD1P3AX 427 100.0
FD1P3AY 3 100.0
FD1P3BX 33 100.0
FD1P3DX 347 100.0
FD1P3IX 175 100.0
FD1P3JX 1 100.0
FD1S3AX 20 100.0
FD1S3AY 1 100.0
FD1S3BX 4 100.0
FD1S3DX 87 100.0
FD1S3IX 33 100.0
FD1S3JX 1 100.0
GSR 1 100.0
IB 5 100.0
IFS1P3IX 2 100.0
IFS1P3JX 1 100.0
INV 18 100.0
L6MUX21 74 100.0
OB 181 100.0
OBZ 1 100.0
OFS1P3DX 4 100.0
OFS1P3IX 136 100.0
ORCALUT4 1290 100.0
PFUMX 104 100.0
PUR 1 100.0
VHI 15 100.0
VLO 15 100.0
jtagconn16 1 100.0
pmi_distributed_dpram_4s_2s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 2 100.0
pmi_ram_dp_Z4 1 100.0
SUB MODULES
BUS_Con_uniq_1 1 100.0
CPLD_Con_uniq_1 1 100.0
Reg_file_uniq_1 1 100.0
relaycontop_la0 1 100.0
relaycontop_la0_trig 1 100.0
reveal_coretop 1 100.0
TOTAL 3049
----------------------------------------------------------------------
Report for cell CPLD_Con_uniq_1.netlist
Instance path: CPLD_Con_2
Cell usage:
cell count Res Usage(%)
CCU2D 9 15.3
FD1P3IX 44 25.1
FD1P3JX 1 100.0
FD1S3AX 14 70.0
FD1S3IX 23 69.7
INV 1 5.6
ORCALUT4 339 26.3
VHI 1 6.7
VLO 1 6.7
TOTAL 433
----------------------------------------------------------------------
Report for cell Reg_file_uniq_1.netlist
Instance path: CPLD_Reg_2
Cell usage:
cell count Res Usage(%)
FD1P3AX 409 95.8
FD1P3AY 3 100.0
FD1S3AX 4 20.0
FD1S3AY 1 100.0
L6MUX21 72 97.3
ORCALUT4 250 19.4
PFUMX 97 93.3
VHI 1 6.7
VLO 1 6.7
TOTAL 838
----------------------------------------------------------------------
Report for cell BUS_Con_uniq_1.netlist
Instance path: BUS_Con_2
Cell usage:
cell count Res Usage(%)
FD1P3IX 131 74.9
FD1S3AX 2 10.0
FD1S3IX 10 30.3
FD1S3JX 1 100.0
ORCALUT4 96 7.4
VHI 1 6.7
VLO 1 6.7
TOTAL 242
----------------------------------------------------------------------
Report for cell reveal_coretop.verilog
Instance path: RelayConTop_reveal_coretop_instance
Cell usage:
cell count Res Usage(%)
CCU2D 50 84.7
FD1P3AX 18 4.2
FD1P3BX 33 100.0
FD1P3DX 347 100.0
FD1S3BX 4 100.0
FD1S3DX 87 100.0
INV 16 88.9
L6MUX21 2 2.7
ORCALUT4 605 46.9
PFUMX 7 6.7
VHI 11 73.3
VLO 11 73.3
jtagconn16 1 100.0
pmi_distributed_dpram_4s_2s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 2 100.0
pmi_ram_dp_Z4 1 100.0
SUB MODULES
relaycontop_la0 1 100.0
relaycontop_la0_trig 1 100.0
TOTAL 1197
----------------------------------------------------------------------
Report for cell relaycontop_la0.netlist
Instance path: RelayConTop_reveal_coretop_instance.relaycontop_la0_inst_0
Cell usage:
cell count Res Usage(%)
CCU2D 50 84.7
FD1P3AX 18 4.2
FD1P3BX 33 100.0
FD1P3DX 347 100.0
FD1S3BX 4 100.0
FD1S3DX 87 100.0
INV 16 88.9
L6MUX21 2 2.7
ORCALUT4 605 46.9
PFUMX 7 6.7
VHI 10 66.7
VLO 10 66.7
pmi_distributed_dpram_4s_2s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 2 100.0
pmi_ram_dp_Z4 1 100.0
SUB MODULES
relaycontop_la0_trig 1 100.0
TOTAL 1193
----------------------------------------------------------------------
Report for cell relaycontop_la0_trig.netlist
Instance path: RelayConTop_reveal_coretop_instance.relaycontop_la0_inst_0.trig_u
Cell usage:
cell count Res Usage(%)
CCU2D 18 30.5
FD1P3AX 16 3.7
FD1P3BX 1 3.0
FD1P3DX 61 17.6
FD1S3BX 4 100.0
FD1S3DX 32 36.8
INV 9 50.0
L6MUX21 2 2.7
ORCALUT4 193 15.0
PFUMX 7 6.7
VHI 7 46.7
VLO 7 46.7
pmi_distributed_dpram_4s_2s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 2 100.0
TOTAL 359
CPLD2/impl1/NewExtIns_CPLD2_impl1.bit
BIN
View File
Binary file not shown.
CPLD2/impl1/NewExtIns_CPLD2_impl1.jed
+3777 -3713
View File
File diff suppressed because it is too large Load Diff
CPLD2/impl1/NewExtIns_CPLD2_impl1.pt
-10
View File
@@ -1,10 +0,0 @@
-v
10
-gt
-sethld
-sp 4
-sphld m
CPLD2/impl1/NewExtIns_CPLD2_impl1_map.cam
-258
View File
@@ -1,258 +0,0 @@
[ START MERGED ]
i_rst_n_c_i i_rst_n_c
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_1/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2.CN jtaghub16_jtck
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jrstn_i jtaghub16_jrstn
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/dec0_wre3 RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_en
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/genblk1.te_tt_dist_ram/dec0_wre3 RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/tt_wr_en
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/jshift_d2.CN jtaghub16_jtck
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/jrstn_i jtaghub16_jrstn
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w.CN jtaghub16_jtck
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jrstn_i jtaghub16_jrstn
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/jtck_i jtaghub16_jtck
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/jrstn_i jtaghub16_jrstn
xo2chub/cdn.CN jtaghub16_jtck
xo2chub/jrstn_i jtaghub16_jrstn
[ END MERGED ]
[ START CLIPPED ]
xo2chub/GND
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/popfeedthru_unused
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/scuba_vlo
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/scuba_vhi
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren_jtck
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_te[2]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/VCC
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/VCC
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_te_0[2]
CPLD_Con_2/GND
xo2chub/VCC
xo2chub/bit_count_cry_0_COUT[3]
xo2chub/rom_rd_addr_cry_0_S0[0]
xo2chub/N_2
xo2chub/rom_rd_addr_s_0_S1[7]
xo2chub/rom_rd_addr_s_0_COUT[7]
xo2chub/jtdo2_int_prm_16_0_0_S1
xo2chub/jtdo2_int_prm_16_0_0_S0
xo2chub/N_3
xo2chub/er2_tdo[14]
xo2chub/er2_tdo[15]
xo2chub/jtdo2_int_prm_15_0_0_S1
xo2chub/jtdo2_int_prm_15_0_0_S0
xo2chub/er2_tdo[12]
xo2chub/er2_tdo[13]
xo2chub/jtdo2_int_prm_13_0_0_S1
xo2chub/jtdo2_int_prm_13_0_0_S0
xo2chub/er2_tdo[10]
xo2chub/er2_tdo[11]
xo2chub/jtdo2_int_prm_11_0_0_S1
xo2chub/jtdo2_int_prm_11_0_0_S0
xo2chub/er2_tdo[8]
xo2chub/er2_tdo[9]
xo2chub/jtdo2_int_prm_9_0_0_S1
xo2chub/jtdo2_int_prm_9_0_0_S0
xo2chub/er2_tdo[6]
xo2chub/er2_tdo[7]
xo2chub/jtdo2_int_prm_7_0_0_S1
xo2chub/jtdo2_int_prm_7_0_0_S0
xo2chub/er2_tdo[4]
xo2chub/er2_tdo[5]
xo2chub/jtdo2_int_prm_5_0_0_S1
xo2chub/jtdo2_int_prm_5_0_0_S0
xo2chub/er2_tdo[2]
xo2chub/er2_tdo[3]
xo2chub/jtdo2_int_prm_3_0_0_S1
xo2chub/jtdo2_int_prm_3_0_0_S0
xo2chub/er2_tdo[1]
xo2chub/jtdo2_int_prm_1_0_0_S0
xo2chub/jtdo2_int_prm_1_0_0_COUT
xo2chub/ip_enable[15]
xo2chub/genblk7.un1_jtagf_u_1
xo2chub/genblk7.un1_jtagf_u
xo2chub/tdoa
xo2chub/tdia
xo2chub/tmsa
xo2chub/tcka
xo2chub/cdn
xo2chub/bit_count_cry_0_S0[0]
xo2chub/N_1
GND
VCC
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/VCC
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/GND
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_1
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0_COUT[9]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_2
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0_COUT[9]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_3
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0_COUT[9]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_4
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0_COUT[9]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s_0_S1[5]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s_0_COUT[5]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s_0_S1[5]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s_0_COUT[5]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/VCC
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/GND
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[4]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/te_precnt_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/N_1
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/te_precnt_s_0_S1[15]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/te_precnt_s_0_COUT[15]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/genblk1.te_tt_dist_ram/mem_0_0/DO2
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/genblk1.te_tt_dist_ram/mem_0_0/DO3
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/mem_0_0/DO2
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/mem_0_0/DO3
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_1
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s_0_S1[15]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s_0_COUT[15]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[3]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu_0[3]
CPLD_Con_2/un1_delay_cnt_1_s_15_0_S1
CPLD_Con_2/un1_delay_cnt_1_s_15_0_COUT
CPLD_Con_2/un1_delay_cnt_1_cry_0_0_S1
CPLD_Con_2/un1_delay_cnt_1_cry_0_0_S0
CPLD_Con_2/N_10
[ END CLIPPED ]
[ START DESIGN PREFS ]
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.14.0.75.2 -- WARNING: Map write only section -- Tue May 26 15:49:45 2026
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "i_sys_clk" SITE "B9" ;
LOCATE COMP "o_PMU_OC_4[31]" SITE "A3" ;
LOCATE COMP "o_PMU_OC_4[30]" SITE "B3" ;
LOCATE COMP "o_PMU_OC_4[29]" SITE "A2" ;
LOCATE COMP "o_PMU_OC_4[28]" SITE "C11" ;
LOCATE COMP "o_PMU_OC_4[27]" SITE "D3" ;
LOCATE COMP "o_PMU_OC_4[26]" SITE "E2" ;
LOCATE COMP "o_PMU_OC_4[25]" SITE "D1" ;
LOCATE COMP "o_PMU_OC_4[24]" SITE "E1" ;
LOCATE COMP "o_PMU_OC_4[15]" SITE "E11" ;
LOCATE COMP "o_PMU_OC_4[14]" SITE "G11" ;
LOCATE COMP "o_PMU_OC_4[13]" SITE "C5" ;
LOCATE COMP "o_PMU_OC_4[12]" SITE "C4" ;
LOCATE COMP "o_PMU_OC_4[11]" SITE "F1" ;
LOCATE COMP "o_PMU_OC_4[10]" SITE "G3" ;
LOCATE COMP "o_PMU_OC_4[9]" SITE "G2" ;
LOCATE COMP "o_PMU_OC_4[8]" SITE "G1" ;
LOCATE COMP "o_PMU_OC_3[31]" SITE "D21" ;
LOCATE COMP "o_PMU_OC_3[30]" SITE "E20" ;
LOCATE COMP "o_PMU_OC_3[29]" SITE "E22" ;
LOCATE COMP "o_PMU_OC_3[28]" SITE "G21" ;
LOCATE COMP "o_PMU_OC_3[27]" SITE "C15" ;
LOCATE COMP "o_PMU_OC_3[26]" SITE "B15" ;
LOCATE COMP "o_PMU_OC_3[25]" SITE "B14" ;
LOCATE COMP "o_PMU_OC_3[24]" SITE "B13" ;
LOCATE COMP "o_PMU_OC_3[15]" SITE "B16" ;
LOCATE COMP "o_PMU_OC_3[14]" SITE "A17" ;
LOCATE COMP "o_PMU_OC_3[13]" SITE "C18" ;
LOCATE COMP "o_PMU_OC_3[12]" SITE "B19" ;
LOCATE COMP "o_PMU_OC_3[11]" SITE "A13" ;
LOCATE COMP "o_PMU_OC_3[10]" SITE "B12" ;
LOCATE COMP "o_PMU_OC_3[9]" SITE "A12" ;
LOCATE COMP "o_PMU_OC_3[8]" SITE "A11" ;
LOCATE COMP "o_PMU_OC_2[31]" SITE "D11" ;
LOCATE COMP "o_PMU_OC_2[30]" SITE "E10" ;
LOCATE COMP "o_PMU_OC_2[29]" SITE "E9" ;
LOCATE COMP "o_PMU_OC_2[28]" SITE "E8" ;
LOCATE COMP "o_PMU_OC_2[27]" SITE "T6" ;
LOCATE COMP "o_PMU_OC_2[26]" SITE "W5" ;
LOCATE COMP "o_PMU_OC_2[25]" SITE "U5" ;
LOCATE COMP "o_PMU_OC_2[24]" SITE "T7" ;
LOCATE COMP "o_PMU_OC_2[15]" SITE "H3" ;
LOCATE COMP "o_PMU_OC_2[14]" SITE "H2" ;
LOCATE COMP "o_PMU_OC_2[13]" SITE "H6" ;
LOCATE COMP "o_PMU_OC_2[12]" SITE "H5" ;
LOCATE COMP "o_PMU_OC_2[11]" SITE "B1" ;
LOCATE COMP "o_PMU_OC_2[10]" SITE "C3" ;
LOCATE COMP "o_PMU_OC_2[9]" SITE "C2" ;
LOCATE COMP "o_PMU_OC_2[8]" SITE "C1" ;
LOCATE COMP "o_PMU_OC_1[31]" SITE "U4" ;
LOCATE COMP "o_PMU_OC_1[30]" SITE "P6" ;
LOCATE COMP "o_PMU_OC_1[29]" SITE "T5" ;
LOCATE COMP "o_PMU_OC_1[28]" SITE "R6" ;
LOCATE COMP "o_PMU_OC_1[27]" SITE "M4" ;
LOCATE COMP "o_PMU_OC_1[26]" SITE "P3" ;
LOCATE COMP "o_PMU_OC_1[25]" SITE "D15" ;
LOCATE COMP "o_PMU_OC_1[24]" SITE "N5" ;
LOCATE COMP "o_PMU_OC_1[15]" SITE "E17" ;
LOCATE COMP "o_PMU_OC_1[14]" SITE "D17" ;
LOCATE COMP "o_PMU_OC_1[13]" SITE "F17" ;
LOCATE COMP "o_PMU_OC_1[12]" SITE "C17" ;
LOCATE COMP "o_PMU_OC_1[11]" SITE "F13" ;
LOCATE COMP "o_PMU_OC_1[10]" SITE "C13" ;
LOCATE COMP "o_PMU_OC_1[9]" SITE "G13" ;
LOCATE COMP "o_PMU_OC_1[8]" SITE "D14" ;
LOCATE COMP "o_RC_T[25]" SITE "AA13" ;
LOCATE COMP "o_RC_T[24]" SITE "T13" ;
LOCATE COMP "o_RC_T[23]" SITE "U15" ;
LOCATE COMP "o_RC_T[22]" SITE "T15" ;
LOCATE COMP "o_RC_T[21]" SITE "Y17" ;
LOCATE COMP "o_RC_T[20]" SITE "W17" ;
LOCATE COMP "o_RC_T[19]" SITE "W19" ;
LOCATE COMP "o_RC_T[18]" SITE "AB20" ;
LOCATE COMP "o_RC_T[17]" SITE "AA19" ;
LOCATE COMP "o_RC_T[16]" SITE "Y18" ;
LOCATE COMP "o_RC_T[15]" SITE "AB17" ;
LOCATE COMP "o_RC_T[14]" SITE "V16" ;
LOCATE COMP "o_RC_T[13]" SITE "V14" ;
LOCATE COMP "o_RC_T[12]" SITE "V13" ;
LOCATE COMP "o_RC_T[11]" SITE "Y12" ;
LOCATE COMP "o_RC_T[10]" SITE "W12" ;
LOCATE COMP "o_RC_T[9]" SITE "V12" ;
LOCATE COMP "o_RC_T[8]" SITE "V8" ;
LOCATE COMP "o_RC_T[7]" SITE "AB13" ;
LOCATE COMP "o_RC_T[6]" SITE "AA12" ;
LOCATE COMP "o_RC_T[5]" SITE "AB11" ;
LOCATE COMP "o_RC_T[4]" SITE "AA11" ;
LOCATE COMP "o_RC_T[3]" SITE "AA10" ;
LOCATE COMP "o_RC_T[2]" SITE "AB10" ;
LOCATE COMP "o_RC_T[1]" SITE "Y10" ;
LOCATE COMP "o_RC_T[0]" SITE "AA8" ;
LOCATE COMP "o_RC_S[15]" SITE "AA7" ;
LOCATE COMP "o_RC_S[14]" SITE "AB7" ;
LOCATE COMP "o_RC_S[13]" SITE "Y7" ;
LOCATE COMP "o_RC_S[12]" SITE "Y6" ;
LOCATE COMP "o_RC_S[11]" SITE "AB6" ;
LOCATE COMP "o_RC_S[10]" SITE "AB5" ;
LOCATE COMP "o_RC_S[9]" SITE "W6" ;
LOCATE COMP "o_RC_S[8]" SITE "Y5" ;
LOCATE COMP "o_RC_S[7]" SITE "AA4" ;
LOCATE COMP "o_RC_S[6]" SITE "Y4" ;
LOCATE COMP "o_RC_S[5]" SITE "AB3" ;
LOCATE COMP "o_RC_S[4]" SITE "AA3" ;
LOCATE COMP "o_RC_S[3]" SITE "Y3" ;
LOCATE COMP "o_RC_S[2]" SITE "AB2" ;
LOCATE COMP "o_RC_S[1]" SITE "W9" ;
LOCATE COMP "o_RC_S[0]" SITE "T10" ;
LOCATE COMP "o_RC_F[7]" SITE "U10" ;
LOCATE COMP "o_RC_F[6]" SITE "W11" ;
LOCATE COMP "o_RC_F[5]" SITE "V11" ;
LOCATE COMP "o_RC_F[4]" SITE "U11" ;
LOCATE COMP "o_RC_F[3]" SITE "T11" ;
LOCATE COMP "o_RC_F[2]" SITE "T12" ;
LOCATE COMP "o_RC_F[1]" SITE "U12" ;
LOCATE COMP "o_RC_F[0]" SITE "U13" ;
LOCATE COMP "o_err" SITE "AB16" ;
LOCATE COMP "i_cs" SITE "Y15" ;
LOCATE COMP "i_mosi" SITE "AB12" ;
LOCATE COMP "i_sclk" SITE "AA16" ;
LOCATE COMP "i_rst_n" SITE "Y14" ;
USE PRIMARY NET "i_sys_clk_c" ;
SCHEMATIC END ;
[ END DESIGN PREFS ]
CPLD2/impl1/NewExtIns_CPLD2_impl1_map.hrr
-209
View File
@@ -1,209 +0,0 @@
---------------------------------------------------
Report for cell RelayConTop
Instance path: RelayConTop
Cell usage:
cell count Res Usage(%)
SLIC 760.00 100.0
IOLGC 142.00 100.0
LUT4 1344.00 100.0
DISTRAM 6.00 100.0
IOREG 142 100.0
IOBUF 187 100.0
PFUREG 1190 100.0
RIPPLE 76 100.0
EBR 10 100.0
SUB MODULES
cell count SLC Usage(%)
xo2chub 1 3.2
reveal_coretop 1 42.6
Reg_file_uniq_1 1 28.8
CPLD_Con_uniq_1 1 17.3
BUS_Con_uniq_1 1 8.1
---------------------------------------------------
Report for cell CPLD_Con_uniq_1
Instance path: RelayConTop/CPLD_Con_2
Cell usage:
cell count Res Usage(%)
SLIC 131.50 17.3
LUT4 340.00 25.3
PFUREG 82 6.9
RIPPLE 9 11.8
---------------------------------------------------
Report for cell Reg_file_uniq_1
Instance path: RelayConTop/CPLD_Reg_2
Cell usage:
cell count Res Usage(%)
SLIC 218.58 28.8
LUT4 250.00 18.6
PFUREG 417 35.0
---------------------------------------------------
Report for cell BUS_Con_uniq_1
Instance path: RelayConTop/BUS_Con_2
Cell usage:
cell count Res Usage(%)
SLIC 61.75 8.1
LUT4 96.00 7.1
PFUREG 144 12.1
---------------------------------------------------
Report for cell reveal_coretop
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance
Cell usage:
cell count Res Usage(%)
SLIC 323.42 42.6
LUT4 645.00 48.0
DISTRAM 4.00 66.7
PFUREG 495 41.6
RIPPLE 50 65.8
EBR 10 100.0
SUB MODULES
cell count SLC Usage(%)
relaycontop_la0 1 42.6
---------------------------------------------------
Report for cell relaycontop_la0
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0
Cell usage:
cell count Res Usage(%)
SLIC 323.42 42.6
LUT4 645.00 48.0
DISTRAM 4.00 66.7
PFUREG 495 41.6
RIPPLE 50 65.8
EBR 10 100.0
SUB MODULES
cell count SLC Usage(%)
rvl_tm_Z3 1 15.6
rvl_jtag_int_42s_2s_0s_0s_6s_42s_42s 1 14.4
relaycontop_la0_trig 1 12.5
---------------------------------------------------
Report for cell relaycontop_la0_trig
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u
Cell usage:
cell count Res Usage(%)
SLIC 95.13 12.5
LUT4 189.00 14.1
DISTRAM 4.00 66.7
PFUREG 118 9.9
RIPPLE 18 23.7
SUB MODULES
cell count SLC Usage(%)
rvl_tu_1s_0s_0s_0s_1s_2 1 0.8
rvl_tu_1s_0s_0s_0s_1s_1 1 0.8
rvl_tcnt_2s_3s_1_0s 1 1.3
rvl_te_Z1_0 1 4.0
rvl_te_Z1_1 1 4.8
rvl_decode_2s_2s 1 0.4
---------------------------------------------------
Report for cell rvl_decode_2s_2s
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u
Cell usage:
cell count Res Usage(%)
SLIC 3.10 0.4
LUT4 12.50 0.9
---------------------------------------------------
Report for cell rvl_tu_1s_0s_0s_0s_1s_2
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0
Cell usage:
cell count Res Usage(%)
SLIC 6.08 0.8
LUT4 11.00 0.8
PFUREG 8 0.7
---------------------------------------------------
Report for cell rvl_tu_1s_0s_0s_0s_1s_1
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_1
Cell usage:
cell count Res Usage(%)
SLIC 6.18 0.8
LUT4 12.00 0.9
PFUREG 8 0.7
---------------------------------------------------
Report for cell rvl_te_Z1_1
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0
Cell usage:
cell count Res Usage(%)
SLIC 36.20 4.8
LUT4 69.50 5.2
DISTRAM 2.00 33.3
PFUREG 53 4.5
RIPPLE 9 11.8
SUB MODULES
cell count SLC Usage(%)
pmi_distributed_dpramXbnoner224pb08036b 1 0.3
---------------------------------------------------
Report for cell pmi_distributed_dpramXbnoner224pb08036b
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram
Cell usage:
cell count Res Usage(%)
SLIC 2.25 0.3
LUT4 1.00 0.1
DISTRAM 2.00 33.3
PFUREG 2 0.2
---------------------------------------------------
Report for cell rvl_te_Z1_0
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1
Cell usage:
cell count Res Usage(%)
SLIC 30.33 4.0
LUT4 53.00 3.9
DISTRAM 2.00 33.3
PFUREG 36 3.0
RIPPLE 9 11.8
SUB MODULES
cell count SLC Usage(%)
pmi_distributed_dpramXbnoner224pb08036b_0 1 0.3
---------------------------------------------------
Report for cell pmi_distributed_dpramXbnoner224pb08036b_0
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/genblk1.te_tt_dist_ram
Cell usage:
cell count Res Usage(%)
SLIC 2.25 0.3
LUT4 1.00 0.1
DISTRAM 2.00 33.3
PFUREG 2 0.2
---------------------------------------------------
Report for cell rvl_tcnt_2s_3s_1_0s
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0
Cell usage:
cell count Res Usage(%)
SLIC 9.73 1.3
LUT4 22.00 1.6
PFUREG 13 1.1
---------------------------------------------------
Report for cell rvl_jtag_int_42s_2s_0s_0s_6s_42s_42s
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u
Cell usage:
cell count Res Usage(%)
SLIC 109.27 14.4
LUT4 249.50 18.6
PFUREG 168 14.1
RIPPLE 8 10.5
---------------------------------------------------
Report for cell rvl_tm_Z3
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u
Cell usage:
cell count Res Usage(%)
SLIC 118.57 15.6
LUT4 205.00 15.3
PFUREG 209 17.6
RIPPLE 24 31.6
EBR 10 100.0
SUB MODULES
cell count SLC Usage(%)
pmi_ram_dpXbnonesadr4211204842112048p1395c895 1 1.4
---------------------------------------------------
Report for cell pmi_ram_dpXbnonesadr4211204842112048p1395c895
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem
Cell usage:
cell count Res Usage(%)
SLIC 11.00 1.4
LUT4 42.00 3.1
PFUREG 2 0.2
EBR 10 100.0
---------------------------------------------------
Report for cell xo2chub
Instance path: RelayConTop/xo2chub
Cell usage:
cell count Res Usage(%)
SLIC 24.25 3.2
LUT4 12.00 0.9
PFUREG 51 4.3
RIPPLE 17 22.4
CPLD2/impl1/NewExtIns_CPLD2_impl1_synplify.lpf
+1 -1
View File
@@ -1,5 +1,5 @@
# #
# Logical Preferences generated for Lattice by Synplify map202309lat, Build 191R. # Logical Preferences generated for Lattice by Synplify map202303lat, Build 132R.
# #
# Period Constraints # Period Constraints
CPLD2/impl1/_cmd._cml
-1
View File
@@ -1 +0,0 @@
-link -encrypt -top RelayConTop -osyn /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD2/impl1/synwork/NewExtIns_CPLD2_impl1_comp.srs /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD2/impl1/synwork/layer0.srs -jobname linker
CPLD2/impl1/impl1.xcf
+4 -4
View File
@@ -19,9 +19,9 @@
<BScanLen>1</BScanLen> <BScanLen>1</BScanLen>
<BScanVal>0</BScanVal> <BScanVal>0</BScanVal>
</Bypass> </Bypass>
<File>D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD2/impl1/NewExtIns_CPLD2_impl1.jed</File> <File>C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD2/impl1/NewExtIns_CPLD2_impl1.jed</File>
<FileTime>01/20/26 16:01:30</FileTime> <FileTime>05/29/26 18:26:36</FileTime>
<JedecChecksum>0x566E</JedecChecksum> <JedecChecksum>0x41B0</JedecChecksum>
<Operation>FLASH Erase,Program,Verify</Operation> <Operation>FLASH Erase,Program,Verify</Operation>
<Option> <Option>
<SVFVendor>JTAG STANDARD</SVFVendor> <SVFVendor>JTAG STANDARD</SVFVendor>
@@ -47,6 +47,6 @@
<CableOptions> <CableOptions>
<CableName>USB</CableName> <CableName>USB</CableName>
<PortAdd>EzUSB-0</PortAdd> <PortAdd>EzUSB-0</PortAdd>
<USBID>\\?\usb#vid_1134&amp;amp;pid_8001#9&amp;amp;2fe42d87&amp;amp;0&amp;amp;2#</USBID> <USBID>\\?\usb#vid_1134&amp;amp;pid_8001#6&amp;amp;ca080be&amp;amp;0&amp;amp;3#</USBID>
</CableOptions> </CableOptions>
</ispXCF> </ispXCF>
CPLD2/impl1/pmi_distributed_dpramXbnoner224pb08036b.edn
-233
View File
@@ -1,233 +0,0 @@
(edif pmi_distributed_dpramXbnoner224pb08036b
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timestamp 2026 5 26 15 49 44)
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 4 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner224pb08036b -pmi ")
(library ORCLIB
(edifLevel 0)
(technology
(numberDefinition))
(cell FD1P3DX
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port D
(direction INPUT))
(port SP
(direction INPUT))
(port CK
(direction INPUT))
(port CD
(direction INPUT))
(port Q
(direction OUTPUT)))))
(cell ROM16X1A
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port AD3
(direction INPUT))
(port AD2
(direction INPUT))
(port AD1
(direction INPUT))
(port AD0
(direction INPUT))
(port DO0
(direction OUTPUT)))))
(cell DPR16X4C
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port DI0
(direction INPUT))
(port DI1
(direction INPUT))
(port DI2
(direction INPUT))
(port DI3
(direction INPUT))
(port WCK
(direction INPUT))
(port WRE
(direction INPUT))
(port RAD0
(direction INPUT))
(port RAD1
(direction INPUT))
(port RAD2
(direction INPUT))
(port RAD3
(direction INPUT))
(port WAD0
(direction INPUT))
(port WAD1
(direction INPUT))
(port WAD2
(direction INPUT))
(port WAD3
(direction INPUT))
(port DO0
(direction OUTPUT))
(port DO1
(direction OUTPUT))
(port DO2
(direction OUTPUT))
(port DO3
(direction OUTPUT)))))
(cell VHI
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port Z
(direction OUTPUT)))))
(cell pmi_distributed_dpramXbnoner224pb08036b
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port (array (rename WrAddress "WrAddress(1:0)") 2)
(direction INPUT))
(port (array (rename Data "Data(1:0)") 2)
(direction INPUT))
(port WrClock
(direction INPUT))
(port WE
(direction INPUT))
(port WrClockEn
(direction INPUT))
(port (array (rename RdAddress "RdAddress(1:0)") 2)
(direction INPUT))
(port RdClock
(direction INPUT))
(port RdClockEn
(direction INPUT))
(port Reset
(direction INPUT))
(port (array (rename Q "Q(1:0)") 2)
(direction OUTPUT)))
(property NGD_DRC_MASK (integer 1))
(contents
(instance LUT4_0
(viewRef view1
(cellRef ROM16X1A))
(property initval
(string "0x8000")))
(instance FF_1
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance FF_0
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance scuba_vhi_inst
(viewRef view1
(cellRef VHI)))
(instance mem_0_0
(viewRef view1
(cellRef DPR16X4C))
(property MEM_INIT_FILE
(string "(0-3)(0-1)"))
(property MEM_LPC_FILE
(string "pmi_distributed_dpramXbnoner224pb08036b__PMI__4__2__2B"))
(property COMP
(string "mem_0_0"))
(property initval
(string "0x0000000000000000")))
(net dataout1_ffin
(joined
(portRef DO1 (instanceRef mem_0_0))
(portRef D (instanceRef FF_1))))
(net dataout0_ffin
(joined
(portRef DO0 (instanceRef mem_0_0))
(portRef D (instanceRef FF_0))))
(net dec0_wre3
(joined
(portRef WRE (instanceRef mem_0_0))
(portRef DO0 (instanceRef LUT4_0))))
(net scuba_vhi
(joined
(portRef Z (instanceRef scuba_vhi_inst))
(portRef AD0 (instanceRef LUT4_0))
(portRef AD1 (instanceRef LUT4_0))
(portRef RAD3 (instanceRef mem_0_0))
(portRef RAD2 (instanceRef mem_0_0))
(portRef WAD3 (instanceRef mem_0_0))
(portRef WAD2 (instanceRef mem_0_0))
(portRef DI3 (instanceRef mem_0_0))
(portRef DI2 (instanceRef mem_0_0))))
(net dataout1
(joined
(portRef (member Q 0))
(portRef Q (instanceRef FF_1))))
(net dataout0
(joined
(portRef (member Q 1))
(portRef Q (instanceRef FF_0))))
(net reset
(joined
(portRef Reset)
(portRef CD (instanceRef FF_1))
(portRef CD (instanceRef FF_0))))
(net rden
(joined
(portRef RdClockEn)
(portRef SP (instanceRef FF_1))
(portRef SP (instanceRef FF_0))))
(net rdclk
(joined
(portRef RdClock)
(portRef CK (instanceRef FF_1))
(portRef CK (instanceRef FF_0))))
(net raddr1
(joined
(portRef (member RdAddress 0))
(portRef RAD1 (instanceRef mem_0_0))))
(net raddr0
(joined
(portRef (member RdAddress 1))
(portRef RAD0 (instanceRef mem_0_0))))
(net cken
(joined
(portRef WrClockEn)
(portRef AD2 (instanceRef LUT4_0))))
(net wren
(joined
(portRef WE)
(portRef AD3 (instanceRef LUT4_0))))
(net clk
(joined
(portRef WrClock)
(portRef WCK (instanceRef mem_0_0))))
(net datain1
(joined
(portRef (member Data 0))
(portRef DI1 (instanceRef mem_0_0))))
(net datain0
(joined
(portRef (member Data 1))
(portRef DI0 (instanceRef mem_0_0))))
(net waddr1
(joined
(portRef (member WrAddress 0))
(portRef WAD1 (instanceRef mem_0_0))))
(net waddr0
(joined
(portRef (member WrAddress 1))
(portRef WAD0 (instanceRef mem_0_0))))))))
(design pmi_distributed_dpramXbnoner224pb08036b
(cellRef pmi_distributed_dpramXbnoner224pb08036b
(libraryRef ORCLIB)))
)
CPLD2/impl1/pmi_distributed_dpramXbnoner224pb08036b_0.edn
-233
View File
@@ -1,233 +0,0 @@
(edif pmi_distributed_dpramXbnoner224pb08036b_0
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timestamp 2026 5 26 15 49 45)
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 4 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner224pb08036b_0 -pmi ")
(library ORCLIB
(edifLevel 0)
(technology
(numberDefinition))
(cell FD1P3DX
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port D
(direction INPUT))
(port SP
(direction INPUT))
(port CK
(direction INPUT))
(port CD
(direction INPUT))
(port Q
(direction OUTPUT)))))
(cell ROM16X1A
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port AD3
(direction INPUT))
(port AD2
(direction INPUT))
(port AD1
(direction INPUT))
(port AD0
(direction INPUT))
(port DO0
(direction OUTPUT)))))
(cell DPR16X4C
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port DI0
(direction INPUT))
(port DI1
(direction INPUT))
(port DI2
(direction INPUT))
(port DI3
(direction INPUT))
(port WCK
(direction INPUT))
(port WRE
(direction INPUT))
(port RAD0
(direction INPUT))
(port RAD1
(direction INPUT))
(port RAD2
(direction INPUT))
(port RAD3
(direction INPUT))
(port WAD0
(direction INPUT))
(port WAD1
(direction INPUT))
(port WAD2
(direction INPUT))
(port WAD3
(direction INPUT))
(port DO0
(direction OUTPUT))
(port DO1
(direction OUTPUT))
(port DO2
(direction OUTPUT))
(port DO3
(direction OUTPUT)))))
(cell VHI
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port Z
(direction OUTPUT)))))
(cell pmi_distributed_dpramXbnoner224pb08036b_0
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port (array (rename WrAddress "WrAddress(1:0)") 2)
(direction INPUT))
(port (array (rename Data "Data(1:0)") 2)
(direction INPUT))
(port WrClock
(direction INPUT))
(port WE
(direction INPUT))
(port WrClockEn
(direction INPUT))
(port (array (rename RdAddress "RdAddress(1:0)") 2)
(direction INPUT))
(port RdClock
(direction INPUT))
(port RdClockEn
(direction INPUT))
(port Reset
(direction INPUT))
(port (array (rename Q "Q(1:0)") 2)
(direction OUTPUT)))
(property NGD_DRC_MASK (integer 1))
(contents
(instance LUT4_0
(viewRef view1
(cellRef ROM16X1A))
(property initval
(string "0x8000")))
(instance FF_1
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance FF_0
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance scuba_vhi_inst
(viewRef view1
(cellRef VHI)))
(instance mem_0_0
(viewRef view1
(cellRef DPR16X4C))
(property MEM_INIT_FILE
(string "(0-3)(0-1)"))
(property MEM_LPC_FILE
(string "pmi_distributed_dpramXbnoner224pb08036b_0__PMI__4__2__2B"))
(property COMP
(string "mem_0_0"))
(property initval
(string "0x0000000000000000")))
(net dataout1_ffin
(joined
(portRef DO1 (instanceRef mem_0_0))
(portRef D (instanceRef FF_1))))
(net dataout0_ffin
(joined
(portRef DO0 (instanceRef mem_0_0))
(portRef D (instanceRef FF_0))))
(net dec0_wre3
(joined
(portRef WRE (instanceRef mem_0_0))
(portRef DO0 (instanceRef LUT4_0))))
(net scuba_vhi
(joined
(portRef Z (instanceRef scuba_vhi_inst))
(portRef AD0 (instanceRef LUT4_0))
(portRef AD1 (instanceRef LUT4_0))
(portRef RAD3 (instanceRef mem_0_0))
(portRef RAD2 (instanceRef mem_0_0))
(portRef WAD3 (instanceRef mem_0_0))
(portRef WAD2 (instanceRef mem_0_0))
(portRef DI3 (instanceRef mem_0_0))
(portRef DI2 (instanceRef mem_0_0))))
(net dataout1
(joined
(portRef (member Q 0))
(portRef Q (instanceRef FF_1))))
(net dataout0
(joined
(portRef (member Q 1))
(portRef Q (instanceRef FF_0))))
(net reset
(joined
(portRef Reset)
(portRef CD (instanceRef FF_1))
(portRef CD (instanceRef FF_0))))
(net rden
(joined
(portRef RdClockEn)
(portRef SP (instanceRef FF_1))
(portRef SP (instanceRef FF_0))))
(net rdclk
(joined
(portRef RdClock)
(portRef CK (instanceRef FF_1))
(portRef CK (instanceRef FF_0))))
(net raddr1
(joined
(portRef (member RdAddress 0))
(portRef RAD1 (instanceRef mem_0_0))))
(net raddr0
(joined
(portRef (member RdAddress 1))
(portRef RAD0 (instanceRef mem_0_0))))
(net cken
(joined
(portRef WrClockEn)
(portRef AD2 (instanceRef LUT4_0))))
(net wren
(joined
(portRef WE)
(portRef AD3 (instanceRef LUT4_0))))
(net clk
(joined
(portRef WrClock)
(portRef WCK (instanceRef mem_0_0))))
(net datain1
(joined
(portRef (member Data 0))
(portRef DI1 (instanceRef mem_0_0))))
(net datain0
(joined
(portRef (member Data 1))
(portRef DI0 (instanceRef mem_0_0))))
(net waddr1
(joined
(portRef (member WrAddress 0))
(portRef WAD1 (instanceRef mem_0_0))))
(net waddr0
(joined
(portRef (member WrAddress 1))
(portRef WAD0 (instanceRef mem_0_0))))))))
(design pmi_distributed_dpramXbnoner224pb08036b_0
(cellRef pmi_distributed_dpramXbnoner224pb08036b_0
(libraryRef ORCLIB)))
)
CPLD2/impl1/pmi_distributed_dpramXbnoner238pb0819f2.edn
-239
View File
@@ -1,239 +0,0 @@
(edif pmi_distributed_dpramXbnoner238pb0819f2
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timestamp 2026 5 15 18 6 2)
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 8 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner238pb0819f2 -pmi ")
(library ORCLIB
(edifLevel 0)
(technology
(numberDefinition))
(cell FD1P3DX
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port D
(direction INPUT))
(port SP
(direction INPUT))
(port CK
(direction INPUT))
(port CD
(direction INPUT))
(port Q
(direction OUTPUT)))))
(cell ROM16X1A
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port AD3
(direction INPUT))
(port AD2
(direction INPUT))
(port AD1
(direction INPUT))
(port AD0
(direction INPUT))
(port DO0
(direction OUTPUT)))))
(cell DPR16X4C
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port DI0
(direction INPUT))
(port DI1
(direction INPUT))
(port DI2
(direction INPUT))
(port DI3
(direction INPUT))
(port WCK
(direction INPUT))
(port WRE
(direction INPUT))
(port RAD0
(direction INPUT))
(port RAD1
(direction INPUT))
(port RAD2
(direction INPUT))
(port RAD3
(direction INPUT))
(port WAD0
(direction INPUT))
(port WAD1
(direction INPUT))
(port WAD2
(direction INPUT))
(port WAD3
(direction INPUT))
(port DO0
(direction OUTPUT))
(port DO1
(direction OUTPUT))
(port DO2
(direction OUTPUT))
(port DO3
(direction OUTPUT)))))
(cell VHI
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port Z
(direction OUTPUT)))))
(cell pmi_distributed_dpramXbnoner238pb0819f2
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port (array (rename WrAddress "WrAddress(2:0)") 3)
(direction INPUT))
(port (array (rename Data "Data(1:0)") 2)
(direction INPUT))
(port WrClock
(direction INPUT))
(port WE
(direction INPUT))
(port WrClockEn
(direction INPUT))
(port (array (rename RdAddress "RdAddress(2:0)") 3)
(direction INPUT))
(port RdClock
(direction INPUT))
(port RdClockEn
(direction INPUT))
(port Reset
(direction INPUT))
(port (array (rename Q "Q(1:0)") 2)
(direction OUTPUT)))
(property NGD_DRC_MASK (integer 1))
(contents
(instance LUT4_0
(viewRef view1
(cellRef ROM16X1A))
(property initval
(string "0x8000")))
(instance FF_1
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance FF_0
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance scuba_vhi_inst
(viewRef view1
(cellRef VHI)))
(instance mem_0_0
(viewRef view1
(cellRef DPR16X4C))
(property MEM_INIT_FILE
(string "(0-7)(0-1)"))
(property MEM_LPC_FILE
(string "pmi_distributed_dpramXbnoner238pb0819f2__PMI__8__2__2B"))
(property COMP
(string "mem_0_0"))
(property initval
(string "0x0000000000000000")))
(net dataout1_ffin
(joined
(portRef DO1 (instanceRef mem_0_0))
(portRef D (instanceRef FF_1))))
(net dataout0_ffin
(joined
(portRef DO0 (instanceRef mem_0_0))
(portRef D (instanceRef FF_0))))
(net dec0_wre3
(joined
(portRef WRE (instanceRef mem_0_0))
(portRef DO0 (instanceRef LUT4_0))))
(net scuba_vhi
(joined
(portRef Z (instanceRef scuba_vhi_inst))
(portRef AD0 (instanceRef LUT4_0))
(portRef AD1 (instanceRef LUT4_0))
(portRef RAD3 (instanceRef mem_0_0))
(portRef WAD3 (instanceRef mem_0_0))
(portRef DI3 (instanceRef mem_0_0))
(portRef DI2 (instanceRef mem_0_0))))
(net dataout1
(joined
(portRef (member Q 0))
(portRef Q (instanceRef FF_1))))
(net dataout0
(joined
(portRef (member Q 1))
(portRef Q (instanceRef FF_0))))
(net reset
(joined
(portRef Reset)
(portRef CD (instanceRef FF_1))
(portRef CD (instanceRef FF_0))))
(net rden
(joined
(portRef RdClockEn)
(portRef SP (instanceRef FF_1))
(portRef SP (instanceRef FF_0))))
(net rdclk
(joined
(portRef RdClock)
(portRef CK (instanceRef FF_1))
(portRef CK (instanceRef FF_0))))
(net raddr2
(joined
(portRef (member RdAddress 0))
(portRef RAD2 (instanceRef mem_0_0))))
(net raddr1
(joined
(portRef (member RdAddress 1))
(portRef RAD1 (instanceRef mem_0_0))))
(net raddr0
(joined
(portRef (member RdAddress 2))
(portRef RAD0 (instanceRef mem_0_0))))
(net cken
(joined
(portRef WrClockEn)
(portRef AD2 (instanceRef LUT4_0))))
(net wren
(joined
(portRef WE)
(portRef AD3 (instanceRef LUT4_0))))
(net clk
(joined
(portRef WrClock)
(portRef WCK (instanceRef mem_0_0))))
(net datain1
(joined
(portRef (member Data 0))
(portRef DI1 (instanceRef mem_0_0))))
(net datain0
(joined
(portRef (member Data 1))
(portRef DI0 (instanceRef mem_0_0))))
(net waddr2
(joined
(portRef (member WrAddress 0))
(portRef WAD2 (instanceRef mem_0_0))))
(net waddr1
(joined
(portRef (member WrAddress 1))
(portRef WAD1 (instanceRef mem_0_0))))
(net waddr0
(joined
(portRef (member WrAddress 2))
(portRef WAD0 (instanceRef mem_0_0))))))))
(design pmi_distributed_dpramXbnoner238pb0819f2
(cellRef pmi_distributed_dpramXbnoner238pb0819f2
(libraryRef ORCLIB)))
)
CPLD2/impl1/pmi_distributed_dpramXbnoner238pb0819f2_0.edn
-239
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@@ -1,239 +0,0 @@
(edif pmi_distributed_dpramXbnoner238pb0819f2_0
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timestamp 2026 5 15 18 6 2)
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 8 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner238pb0819f2_0 -pmi ")
(library ORCLIB
(edifLevel 0)
(technology
(numberDefinition))
(cell FD1P3DX
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port D
(direction INPUT))
(port SP
(direction INPUT))
(port CK
(direction INPUT))
(port CD
(direction INPUT))
(port Q
(direction OUTPUT)))))
(cell ROM16X1A
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port AD3
(direction INPUT))
(port AD2
(direction INPUT))
(port AD1
(direction INPUT))
(port AD0
(direction INPUT))
(port DO0
(direction OUTPUT)))))
(cell DPR16X4C
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port DI0
(direction INPUT))
(port DI1
(direction INPUT))
(port DI2
(direction INPUT))
(port DI3
(direction INPUT))
(port WCK
(direction INPUT))
(port WRE
(direction INPUT))
(port RAD0
(direction INPUT))
(port RAD1
(direction INPUT))
(port RAD2
(direction INPUT))
(port RAD3
(direction INPUT))
(port WAD0
(direction INPUT))
(port WAD1
(direction INPUT))
(port WAD2
(direction INPUT))
(port WAD3
(direction INPUT))
(port DO0
(direction OUTPUT))
(port DO1
(direction OUTPUT))
(port DO2
(direction OUTPUT))
(port DO3
(direction OUTPUT)))))
(cell VHI
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port Z
(direction OUTPUT)))))
(cell pmi_distributed_dpramXbnoner238pb0819f2_0
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port (array (rename WrAddress "WrAddress(2:0)") 3)
(direction INPUT))
(port (array (rename Data "Data(1:0)") 2)
(direction INPUT))
(port WrClock
(direction INPUT))
(port WE
(direction INPUT))
(port WrClockEn
(direction INPUT))
(port (array (rename RdAddress "RdAddress(2:0)") 3)
(direction INPUT))
(port RdClock
(direction INPUT))
(port RdClockEn
(direction INPUT))
(port Reset
(direction INPUT))
(port (array (rename Q "Q(1:0)") 2)
(direction OUTPUT)))
(property NGD_DRC_MASK (integer 1))
(contents
(instance LUT4_0
(viewRef view1
(cellRef ROM16X1A))
(property initval
(string "0x8000")))
(instance FF_1
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance FF_0
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance scuba_vhi_inst
(viewRef view1
(cellRef VHI)))
(instance mem_0_0
(viewRef view1
(cellRef DPR16X4C))
(property MEM_INIT_FILE
(string "(0-7)(0-1)"))
(property MEM_LPC_FILE
(string "pmi_distributed_dpramXbnoner238pb0819f2_0__PMI__8__2__2B"))
(property COMP
(string "mem_0_0"))
(property initval
(string "0x0000000000000000")))
(net dataout1_ffin
(joined
(portRef DO1 (instanceRef mem_0_0))
(portRef D (instanceRef FF_1))))
(net dataout0_ffin
(joined
(portRef DO0 (instanceRef mem_0_0))
(portRef D (instanceRef FF_0))))
(net dec0_wre3
(joined
(portRef WRE (instanceRef mem_0_0))
(portRef DO0 (instanceRef LUT4_0))))
(net scuba_vhi
(joined
(portRef Z (instanceRef scuba_vhi_inst))
(portRef AD0 (instanceRef LUT4_0))
(portRef AD1 (instanceRef LUT4_0))
(portRef RAD3 (instanceRef mem_0_0))
(portRef WAD3 (instanceRef mem_0_0))
(portRef DI3 (instanceRef mem_0_0))
(portRef DI2 (instanceRef mem_0_0))))
(net dataout1
(joined
(portRef (member Q 0))
(portRef Q (instanceRef FF_1))))
(net dataout0
(joined
(portRef (member Q 1))
(portRef Q (instanceRef FF_0))))
(net reset
(joined
(portRef Reset)
(portRef CD (instanceRef FF_1))
(portRef CD (instanceRef FF_0))))
(net rden
(joined
(portRef RdClockEn)
(portRef SP (instanceRef FF_1))
(portRef SP (instanceRef FF_0))))
(net rdclk
(joined
(portRef RdClock)
(portRef CK (instanceRef FF_1))
(portRef CK (instanceRef FF_0))))
(net raddr2
(joined
(portRef (member RdAddress 0))
(portRef RAD2 (instanceRef mem_0_0))))
(net raddr1
(joined
(portRef (member RdAddress 1))
(portRef RAD1 (instanceRef mem_0_0))))
(net raddr0
(joined
(portRef (member RdAddress 2))
(portRef RAD0 (instanceRef mem_0_0))))
(net cken
(joined
(portRef WrClockEn)
(portRef AD2 (instanceRef LUT4_0))))
(net wren
(joined
(portRef WE)
(portRef AD3 (instanceRef LUT4_0))))
(net clk
(joined
(portRef WrClock)
(portRef WCK (instanceRef mem_0_0))))
(net datain1
(joined
(portRef (member Data 0))
(portRef DI1 (instanceRef mem_0_0))))
(net datain0
(joined
(portRef (member Data 1))
(portRef DI0 (instanceRef mem_0_0))))
(net waddr2
(joined
(portRef (member WrAddress 0))
(portRef WAD2 (instanceRef mem_0_0))))
(net waddr1
(joined
(portRef (member WrAddress 1))
(portRef WAD1 (instanceRef mem_0_0))))
(net waddr0
(joined
(portRef (member WrAddress 2))
(portRef WAD0 (instanceRef mem_0_0))))))))
(design pmi_distributed_dpramXbnoner238pb0819f2_0
(cellRef pmi_distributed_dpramXbnoner238pb0819f2_0
(libraryRef ORCLIB)))
)
CPLD2/impl1/pmi_distributed_dpramXbnoner238pb0819f2_1.edn
-239
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@@ -1,239 +0,0 @@
(edif pmi_distributed_dpramXbnoner238pb0819f2_1
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timestamp 2026 5 15 18 6 2)
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 8 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner238pb0819f2_1 -pmi ")
(library ORCLIB
(edifLevel 0)
(technology
(numberDefinition))
(cell FD1P3DX
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port D
(direction INPUT))
(port SP
(direction INPUT))
(port CK
(direction INPUT))
(port CD
(direction INPUT))
(port Q
(direction OUTPUT)))))
(cell ROM16X1A
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port AD3
(direction INPUT))
(port AD2
(direction INPUT))
(port AD1
(direction INPUT))
(port AD0
(direction INPUT))
(port DO0
(direction OUTPUT)))))
(cell DPR16X4C
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port DI0
(direction INPUT))
(port DI1
(direction INPUT))
(port DI2
(direction INPUT))
(port DI3
(direction INPUT))
(port WCK
(direction INPUT))
(port WRE
(direction INPUT))
(port RAD0
(direction INPUT))
(port RAD1
(direction INPUT))
(port RAD2
(direction INPUT))
(port RAD3
(direction INPUT))
(port WAD0
(direction INPUT))
(port WAD1
(direction INPUT))
(port WAD2
(direction INPUT))
(port WAD3
(direction INPUT))
(port DO0
(direction OUTPUT))
(port DO1
(direction OUTPUT))
(port DO2
(direction OUTPUT))
(port DO3
(direction OUTPUT)))))
(cell VHI
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port Z
(direction OUTPUT)))))
(cell pmi_distributed_dpramXbnoner238pb0819f2_1
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port (array (rename WrAddress "WrAddress(2:0)") 3)
(direction INPUT))
(port (array (rename Data "Data(1:0)") 2)
(direction INPUT))
(port WrClock
(direction INPUT))
(port WE
(direction INPUT))
(port WrClockEn
(direction INPUT))
(port (array (rename RdAddress "RdAddress(2:0)") 3)
(direction INPUT))
(port RdClock
(direction INPUT))
(port RdClockEn
(direction INPUT))
(port Reset
(direction INPUT))
(port (array (rename Q "Q(1:0)") 2)
(direction OUTPUT)))
(property NGD_DRC_MASK (integer 1))
(contents
(instance LUT4_0
(viewRef view1
(cellRef ROM16X1A))
(property initval
(string "0x8000")))
(instance FF_1
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance FF_0
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance scuba_vhi_inst
(viewRef view1
(cellRef VHI)))
(instance mem_0_0
(viewRef view1
(cellRef DPR16X4C))
(property MEM_INIT_FILE
(string "(0-7)(0-1)"))
(property MEM_LPC_FILE
(string "pmi_distributed_dpramXbnoner238pb0819f2_1__PMI__8__2__2B"))
(property COMP
(string "mem_0_0"))
(property initval
(string "0x0000000000000000")))
(net dataout1_ffin
(joined
(portRef DO1 (instanceRef mem_0_0))
(portRef D (instanceRef FF_1))))
(net dataout0_ffin
(joined
(portRef DO0 (instanceRef mem_0_0))
(portRef D (instanceRef FF_0))))
(net dec0_wre3
(joined
(portRef WRE (instanceRef mem_0_0))
(portRef DO0 (instanceRef LUT4_0))))
(net scuba_vhi
(joined
(portRef Z (instanceRef scuba_vhi_inst))
(portRef AD0 (instanceRef LUT4_0))
(portRef AD1 (instanceRef LUT4_0))
(portRef RAD3 (instanceRef mem_0_0))
(portRef WAD3 (instanceRef mem_0_0))
(portRef DI3 (instanceRef mem_0_0))
(portRef DI2 (instanceRef mem_0_0))))
(net dataout1
(joined
(portRef (member Q 0))
(portRef Q (instanceRef FF_1))))
(net dataout0
(joined
(portRef (member Q 1))
(portRef Q (instanceRef FF_0))))
(net reset
(joined
(portRef Reset)
(portRef CD (instanceRef FF_1))
(portRef CD (instanceRef FF_0))))
(net rden
(joined
(portRef RdClockEn)
(portRef SP (instanceRef FF_1))
(portRef SP (instanceRef FF_0))))
(net rdclk
(joined
(portRef RdClock)
(portRef CK (instanceRef FF_1))
(portRef CK (instanceRef FF_0))))
(net raddr2
(joined
(portRef (member RdAddress 0))
(portRef RAD2 (instanceRef mem_0_0))))
(net raddr1
(joined
(portRef (member RdAddress 1))
(portRef RAD1 (instanceRef mem_0_0))))
(net raddr0
(joined
(portRef (member RdAddress 2))
(portRef RAD0 (instanceRef mem_0_0))))
(net cken
(joined
(portRef WrClockEn)
(portRef AD2 (instanceRef LUT4_0))))
(net wren
(joined
(portRef WE)
(portRef AD3 (instanceRef LUT4_0))))
(net clk
(joined
(portRef WrClock)
(portRef WCK (instanceRef mem_0_0))))
(net datain1
(joined
(portRef (member Data 0))
(portRef DI1 (instanceRef mem_0_0))))
(net datain0
(joined
(portRef (member Data 1))
(portRef DI0 (instanceRef mem_0_0))))
(net waddr2
(joined
(portRef (member WrAddress 0))
(portRef WAD2 (instanceRef mem_0_0))))
(net waddr1
(joined
(portRef (member WrAddress 1))
(portRef WAD1 (instanceRef mem_0_0))))
(net waddr0
(joined
(portRef (member WrAddress 2))
(portRef WAD0 (instanceRef mem_0_0))))))))
(design pmi_distributed_dpramXbnoner238pb0819f2_1
(cellRef pmi_distributed_dpramXbnoner238pb0819f2_1
(libraryRef ORCLIB)))
)
CPLD2/impl1/pmi_ram_dpXbnonesadr100112048100112048p13b98964.edn
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CPLD2/untitled.rva
+113 -35
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@@ -30,44 +30,122 @@
<TraceSignal IsHidden="false" Name="BUS_Con_2/i_cs" NodeType="0" PortIndex="1"/> <TraceSignal IsHidden="false" Name="BUS_Con_2/i_cs" NodeType="0" PortIndex="1"/>
<TraceSignal IsHidden="false" Name="BUS_Con_2/i_sclk" NodeType="0" PortIndex="2"/> <TraceSignal IsHidden="false" Name="BUS_Con_2/i_sclk" NodeType="0" PortIndex="2"/>
<TraceSignal IsHidden="false" Name="BUS_Con_2/i_mosi" NodeType="0" PortIndex="3"/> <TraceSignal IsHidden="false" Name="BUS_Con_2/i_mosi" NodeType="0" PortIndex="3"/>
<TraceSignal IsHidden="false" Name="BUS_Con_2/i_reg_busy" NodeType="0" PortIndex="4"/> <TraceSignal IsHidden="false" Name="CPLD_Con_2/i_con_exec" NodeType="0" PortIndex="4"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_2/o_exec" NodeType="0" PortIndex="5"/> <TraceSignal IsHidden="false" Name="BUS_Con_2/err_flag" NodeType="0" PortIndex="5"/>
<TraceSignal IsHidden="false" Name="RC_T" NodeType="1" PortIndex="6"> <TraceSignal IsHidden="false" Name="CPLD_Con_2/err_flag" NodeType="0" PortIndex="6"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_2/err_flag" NodeType="0" PortIndex="7"/>
<TraceSignal IsHidden="false" Name="DC_Con1" NodeType="1" PortIndex="8">
<BusRadix Radix="0"/> <BusRadix Radix="0"/>
<IsExpanded Expand="false"/> <IsExpanded Expand="false"/>
</TraceSignal> </TraceSignal>
<TraceSignal IsHidden="false" Name="RC_T:0" NodeType="2" PortIndex="6"/> <TraceSignal IsHidden="false" Name="DC_Con1:0" NodeType="2" PortIndex="8"/>
<TraceSignal IsHidden="false" Name="RC_T:1" NodeType="2" PortIndex="7"/> <TraceSignal IsHidden="false" Name="DC_Con1:1" NodeType="2" PortIndex="9"/>
<TraceSignal IsHidden="false" Name="RC_T:2" NodeType="2" PortIndex="8"/> <TraceSignal IsHidden="false" Name="DC_Con1:2" NodeType="2" PortIndex="10"/>
<TraceSignal IsHidden="false" Name="RC_T:3" NodeType="2" PortIndex="9"/> <TraceSignal IsHidden="false" Name="DC_Con1:3" NodeType="2" PortIndex="11"/>
<TraceSignal IsHidden="false" Name="RC_T:4" NodeType="2" PortIndex="10"/> <TraceSignal IsHidden="false" Name="DC_Con1:4" NodeType="2" PortIndex="12"/>
<TraceSignal IsHidden="false" Name="RC_T:5" NodeType="2" PortIndex="11"/> <TraceSignal IsHidden="false" Name="DC_Con1:5" NodeType="2" PortIndex="13"/>
<TraceSignal IsHidden="false" Name="RC_T:6" NodeType="2" PortIndex="12"/> <TraceSignal IsHidden="false" Name="DC_Con1:6" NodeType="2" PortIndex="14"/>
<TraceSignal IsHidden="false" Name="RC_T:7" NodeType="2" PortIndex="13"/> <TraceSignal IsHidden="false" Name="DC_Con1:7" NodeType="2" PortIndex="15"/>
<TraceSignal IsHidden="false" Name="RC_T:8" NodeType="2" PortIndex="14"/> <TraceSignal IsHidden="false" Name="DC_Con1:8" NodeType="2" PortIndex="16"/>
<TraceSignal IsHidden="false" Name="RC_T:9" NodeType="2" PortIndex="15"/> <TraceSignal IsHidden="false" Name="DC_Con1:9" NodeType="2" PortIndex="17"/>
<TraceSignal IsHidden="false" Name="RC_T:10" NodeType="2" PortIndex="16"/> <TraceSignal IsHidden="false" Name="DC_Con1:10" NodeType="2" PortIndex="18"/>
<TraceSignal IsHidden="false" Name="RC_T:11" NodeType="2" PortIndex="17"/> <TraceSignal IsHidden="false" Name="DC_Con1:11" NodeType="2" PortIndex="19"/>
<TraceSignal IsHidden="false" Name="RC_T:12" NodeType="2" PortIndex="18"/> <TraceSignal IsHidden="false" Name="DC_Con1:12" NodeType="2" PortIndex="20"/>
<TraceSignal IsHidden="false" Name="RC_T:13" NodeType="2" PortIndex="19"/> <TraceSignal IsHidden="false" Name="DC_Con1:13" NodeType="2" PortIndex="21"/>
<TraceSignal IsHidden="false" Name="RC_T:14" NodeType="2" PortIndex="20"/> <TraceSignal IsHidden="false" Name="DC_Con1:14" NodeType="2" PortIndex="22"/>
<TraceSignal IsHidden="false" Name="RC_T:15" NodeType="2" PortIndex="21"/> <TraceSignal IsHidden="false" Name="DC_Con1:15" NodeType="2" PortIndex="23"/>
<TraceSignal IsHidden="false" Name="RC_T:16" NodeType="2" PortIndex="22"/> <TraceSignal IsHidden="false" Name="DC_Con1:16" NodeType="2" PortIndex="24"/>
<TraceSignal IsHidden="false" Name="RC_T:17" NodeType="2" PortIndex="23"/> <TraceSignal IsHidden="false" Name="DC_Con1:17" NodeType="2" PortIndex="25"/>
<TraceSignal IsHidden="false" Name="RC_T:18" NodeType="2" PortIndex="24"/> <TraceSignal IsHidden="false" Name="DC_Con1:18" NodeType="2" PortIndex="26"/>
<TraceSignal IsHidden="false" Name="RC_T:19" NodeType="2" PortIndex="25"/> <TraceSignal IsHidden="false" Name="DC_Con1:19" NodeType="2" PortIndex="27"/>
<TraceSignal IsHidden="false" Name="RC_T:20" NodeType="2" PortIndex="26"/> <TraceSignal IsHidden="false" Name="DC_Con1:20" NodeType="2" PortIndex="28"/>
<TraceSignal IsHidden="false" Name="RC_T:21" NodeType="2" PortIndex="27"/> <TraceSignal IsHidden="false" Name="DC_Con1:21" NodeType="2" PortIndex="29"/>
<TraceSignal IsHidden="false" Name="RC_T:22" NodeType="2" PortIndex="28"/> <TraceSignal IsHidden="false" Name="DC_Con1:22" NodeType="2" PortIndex="30"/>
<TraceSignal IsHidden="false" Name="RC_T:23" NodeType="2" PortIndex="29"/> <TraceSignal IsHidden="false" Name="DC_Con1:23" NodeType="2" PortIndex="31"/>
<TraceSignal IsHidden="false" Name="RC_T:24" NodeType="2" PortIndex="30"/> <TraceSignal IsHidden="false" Name="DC_Con2" NodeType="1" PortIndex="32">
<TraceSignal IsHidden="false" Name="RC_T:25" NodeType="2" PortIndex="31"/> <BusRadix Radix="0"/>
<TraceSignal IsHidden="false" Name="RC_T:26" NodeType="2" PortIndex="32"/> <IsExpanded Expand="false"/>
<TraceSignal IsHidden="false" Name="RC_T:27" NodeType="2" PortIndex="33"/> </TraceSignal>
<TraceSignal IsHidden="false" Name="RC_T:28" NodeType="2" PortIndex="34"/> <TraceSignal IsHidden="false" Name="DC_Con2:0" NodeType="2" PortIndex="32"/>
<TraceSignal IsHidden="false" Name="RC_T:29" NodeType="2" PortIndex="35"/> <TraceSignal IsHidden="false" Name="DC_Con2:1" NodeType="2" PortIndex="33"/>
<TraceSignal IsHidden="false" Name="RC_T:30" NodeType="2" PortIndex="36"/> <TraceSignal IsHidden="false" Name="DC_Con2:2" NodeType="2" PortIndex="34"/>
<TraceSignal IsHidden="false" Name="RC_T:31" NodeType="2" PortIndex="37"/> <TraceSignal IsHidden="false" Name="DC_Con2:3" NodeType="2" PortIndex="35"/>
<TraceSignal IsHidden="false" Name="DC_Con2:4" NodeType="2" PortIndex="36"/>
<TraceSignal IsHidden="false" Name="DC_Con2:5" NodeType="2" PortIndex="37"/>
<TraceSignal IsHidden="false" Name="DC_Con2:6" NodeType="2" PortIndex="38"/>
<TraceSignal IsHidden="false" Name="DC_Con2:7" NodeType="2" PortIndex="39"/>
<TraceSignal IsHidden="false" Name="DC_Con2:8" NodeType="2" PortIndex="40"/>
<TraceSignal IsHidden="false" Name="DC_Con2:9" NodeType="2" PortIndex="41"/>
<TraceSignal IsHidden="false" Name="DC_Con2:10" NodeType="2" PortIndex="42"/>
<TraceSignal IsHidden="false" Name="DC_Con2:11" NodeType="2" PortIndex="43"/>
<TraceSignal IsHidden="false" Name="DC_Con2:12" NodeType="2" PortIndex="44"/>
<TraceSignal IsHidden="false" Name="DC_Con2:13" NodeType="2" PortIndex="45"/>
<TraceSignal IsHidden="false" Name="DC_Con2:14" NodeType="2" PortIndex="46"/>
<TraceSignal IsHidden="false" Name="DC_Con2:15" NodeType="2" PortIndex="47"/>
<TraceSignal IsHidden="false" Name="DC_Con2:16" NodeType="2" PortIndex="48"/>
<TraceSignal IsHidden="false" Name="DC_Con2:17" NodeType="2" PortIndex="49"/>
<TraceSignal IsHidden="false" Name="DC_Con2:18" NodeType="2" PortIndex="50"/>
<TraceSignal IsHidden="false" Name="DC_Con2:19" NodeType="2" PortIndex="51"/>
<TraceSignal IsHidden="false" Name="DC_Con2:20" NodeType="2" PortIndex="52"/>
<TraceSignal IsHidden="false" Name="DC_Con2:21" NodeType="2" PortIndex="53"/>
<TraceSignal IsHidden="false" Name="DC_Con2:22" NodeType="2" PortIndex="54"/>
<TraceSignal IsHidden="false" Name="DC_Con2:23" NodeType="2" PortIndex="55"/>
<TraceSignal IsHidden="false" Name="DC_Con3" NodeType="1" PortIndex="56">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="DC_Con3:0" NodeType="2" PortIndex="56"/>
<TraceSignal IsHidden="false" Name="DC_Con3:1" NodeType="2" PortIndex="57"/>
<TraceSignal IsHidden="false" Name="DC_Con3:2" NodeType="2" PortIndex="58"/>
<TraceSignal IsHidden="false" Name="DC_Con3:3" NodeType="2" PortIndex="59"/>
<TraceSignal IsHidden="false" Name="DC_Con3:4" NodeType="2" PortIndex="60"/>
<TraceSignal IsHidden="false" Name="DC_Con3:5" NodeType="2" PortIndex="61"/>
<TraceSignal IsHidden="false" Name="DC_Con3:6" NodeType="2" PortIndex="62"/>
<TraceSignal IsHidden="false" Name="DC_Con3:7" NodeType="2" PortIndex="63"/>
<TraceSignal IsHidden="false" Name="DC_Con3:8" NodeType="2" PortIndex="64"/>
<TraceSignal IsHidden="false" Name="DC_Con3:9" NodeType="2" PortIndex="65"/>
<TraceSignal IsHidden="false" Name="DC_Con3:10" NodeType="2" PortIndex="66"/>
<TraceSignal IsHidden="false" Name="DC_Con3:11" NodeType="2" PortIndex="67"/>
<TraceSignal IsHidden="false" Name="DC_Con3:12" NodeType="2" PortIndex="68"/>
<TraceSignal IsHidden="false" Name="DC_Con3:13" NodeType="2" PortIndex="69"/>
<TraceSignal IsHidden="false" Name="DC_Con3:14" NodeType="2" PortIndex="70"/>
<TraceSignal IsHidden="false" Name="DC_Con3:15" NodeType="2" PortIndex="71"/>
<TraceSignal IsHidden="false" Name="DC_Con3:16" NodeType="2" PortIndex="72"/>
<TraceSignal IsHidden="false" Name="DC_Con3:17" NodeType="2" PortIndex="73"/>
<TraceSignal IsHidden="false" Name="DC_Con3:18" NodeType="2" PortIndex="74"/>
<TraceSignal IsHidden="false" Name="DC_Con3:19" NodeType="2" PortIndex="75"/>
<TraceSignal IsHidden="false" Name="DC_Con3:20" NodeType="2" PortIndex="76"/>
<TraceSignal IsHidden="false" Name="DC_Con3:21" NodeType="2" PortIndex="77"/>
<TraceSignal IsHidden="false" Name="DC_Con3:22" NodeType="2" PortIndex="78"/>
<TraceSignal IsHidden="false" Name="DC_Con3:23" NodeType="2" PortIndex="79"/>
<TraceSignal IsHidden="false" Name="DC_Con4" NodeType="1" PortIndex="80">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="DC_Con4:0" NodeType="2" PortIndex="80"/>
<TraceSignal IsHidden="false" Name="DC_Con4:1" NodeType="2" PortIndex="81"/>
<TraceSignal IsHidden="false" Name="DC_Con4:2" NodeType="2" PortIndex="82"/>
<TraceSignal IsHidden="false" Name="DC_Con4:3" NodeType="2" PortIndex="83"/>
<TraceSignal IsHidden="false" Name="DC_Con4:4" NodeType="2" PortIndex="84"/>
<TraceSignal IsHidden="false" Name="DC_Con4:5" NodeType="2" PortIndex="85"/>
<TraceSignal IsHidden="false" Name="DC_Con4:6" NodeType="2" PortIndex="86"/>
<TraceSignal IsHidden="false" Name="DC_Con4:7" NodeType="2" PortIndex="87"/>
<TraceSignal IsHidden="false" Name="DC_Con4:8" NodeType="2" PortIndex="88"/>
<TraceSignal IsHidden="false" Name="DC_Con4:9" NodeType="2" PortIndex="89"/>
<TraceSignal IsHidden="false" Name="DC_Con4:10" NodeType="2" PortIndex="90"/>
<TraceSignal IsHidden="false" Name="DC_Con4:11" NodeType="2" PortIndex="91"/>
<TraceSignal IsHidden="false" Name="DC_Con4:12" NodeType="2" PortIndex="92"/>
<TraceSignal IsHidden="false" Name="DC_Con4:13" NodeType="2" PortIndex="93"/>
<TraceSignal IsHidden="false" Name="DC_Con4:14" NodeType="2" PortIndex="94"/>
<TraceSignal IsHidden="false" Name="DC_Con4:15" NodeType="2" PortIndex="95"/>
<TraceSignal IsHidden="false" Name="DC_Con4:16" NodeType="2" PortIndex="96"/>
<TraceSignal IsHidden="false" Name="DC_Con4:17" NodeType="2" PortIndex="97"/>
<TraceSignal IsHidden="false" Name="DC_Con4:18" NodeType="2" PortIndex="98"/>
<TraceSignal IsHidden="false" Name="DC_Con4:19" NodeType="2" PortIndex="99"/>
<TraceSignal IsHidden="false" Name="DC_Con4:20" NodeType="2" PortIndex="100"/>
<TraceSignal IsHidden="false" Name="DC_Con4:21" NodeType="2" PortIndex="101"/>
<TraceSignal IsHidden="false" Name="DC_Con4:22" NodeType="2" PortIndex="102"/>
<TraceSignal IsHidden="false" Name="DC_Con4:23" NodeType="2" PortIndex="103"/>
</TraceSigTreeData> </TraceSigTreeData>
<TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/> <TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/>
<CoreRun Run="true"/> <CoreRun Run="true"/>
CPLD2/untitled.svf
+12 -319
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CPLD2/untitled.trc
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CPLD3/BUS_Con.v
+61 -34
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@@ -28,7 +28,6 @@ module BUS_Con (
reg [1:0] mosi_sync; reg [1:0] mosi_sync;
wire cs_active; wire cs_active;
wire cs_rise;
wire sclk_rise; // For Sampling MOSI wire sclk_rise; // For Sampling MOSI
wire sclk_fall; // For Shifting MISO wire sclk_fall; // For Shifting MISO
wire mosi_data; wire mosi_data;
@@ -47,7 +46,6 @@ module BUS_Con (
end end
assign cs_active = ~cs_sync[1]; assign cs_active = ~cs_sync[1];
assign cs_rise = (!cs_sync[1] && cs_sync[0]);
// SPI Mode 0: Sample MOSI on Rising, Shift MISO on Falling // SPI Mode 0: Sample MOSI on Rising, Shift MISO on Falling
assign sclk_rise = (!sclk_sync[1] && sclk_sync[0]); assign sclk_rise = (!sclk_sync[1] && sclk_sync[0]);
@@ -61,8 +59,9 @@ module BUS_Con (
reg err_flag; reg err_flag;
reg [1:0] state; reg [1:0] state;
// //
reg [31:0] tx_buffer; // Holds data waiting for the next CS Low
reg [31:0] miso_shift; // The actual shifter reg [31:0] miso_shift; // The actual shifter
reg wr_flag;// Flag: 1=W/0=R
reg miso_loaded;
// Output Registers // Output Registers
reg [6:0] addr_out; reg [6:0] addr_out;
reg [23:0] data_out; reg [23:0] data_out;
@@ -82,77 +81,98 @@ module BUS_Con (
bit_cnt <= 6'd0; bit_cnt <= 6'd0;
data_ready <= 1'b0; data_ready <= 1'b0;
err_flag <= 1'b0; err_flag <= 1'b0;
wr_flag <= 1'b1;
end end
else begin else begin
// Clear data_ready when FSM has consumed the command (CMD_SENT = consumed)
if (state == CMD_SENT) begin
data_ready <= 1'b0; data_ready <= 1'b0;
end
if (cs_active) begin if (cs_active) begin
if (sclk_rise) begin if (sclk_rise) begin
recv_reg <= {recv_reg[30:0], mosi_data}; recv_reg <= {recv_reg[30:0], mosi_data};
bit_cnt <= bit_cnt + 1'b1; bit_cnt <= bit_cnt + 1'b1;
end
else if (cs_rise) begin // After 8 bits: check WR bit (recv_reg[7] = first bit received)
if (bit_cnt == 6'd32) begin // Read (WR=0): set data_ready early so MISO data is prepared
// Write (WR=1): wait for all 32 bits
if (bit_cnt == 'd7) begin
if (recv_reg[6] == 1'b0) begin
// Read command: signal ready after address received
data_ready <= 1'b1; data_ready <= 1'b1;
wr_flag <= 1'b0;
end
else begin
wr_flag <= 1'b1;
end
end
else if (bit_cnt == 6'd31) begin
// Write command complete (32 bits received)
data_ready <= 1'b1;
end
end
else if (!cs_active) begin
data_ready <= 1'b0;
if (bit_cnt == 6'd31) begin
err_flag <= 1'b0; err_flag <= 1'b0;
bit_cnt <= 6'd0; bit_cnt <= 6'd0;
end end
else if (bit_cnt != 0) begin else if (bit_cnt != 0 && bit_cnt != 6'd32) begin
err_flag <= 1'b1; err_flag <= 1'b1;
bit_cnt <= 6'd0; bit_cnt <= 6'd0;
recv_reg <= 'd0; recv_reg <= 'd0;
end end
end end
end end
if (state == DONE) begin else begin
// CS high: reset state
bit_cnt <= 6'd0;
recv_reg <= 'd0; recv_reg <= 'd0;
data_ready <= 1'b0;
end end
end end
end end
// --- 3. MISO (Transmit) Logic --- // --- 3. MISO (Transmit) Logic ---
// Protocol: We shift out 32 bits. // Protocol: We shift out 32 bits.
// Format: [8 bit Status/Padding] + [24 bit i_rdata] // Format: [8'h00 padding] + [24 bit i_rdata]
// Shift MSB out on each falling edge of SCLK (master samples on rising)
// Consolidated: load on first rising edge, shift on falling edges
// Capture data from backend when valid
always @(posedge i_sys_clk) begin
if (!i_rst_n) begin
tx_buffer <= 32'd0;
end else begin
// If backend provides valid read data, store it.
// We pad the top 8 bits with Zeros (or you can put status flags here)
if (i_rvalid) begin
tx_buffer <= {8'h00, i_rdata};
end
end
end
// Shift data out
always @(posedge i_sys_clk) begin always @(posedge i_sys_clk) begin
if (!i_rst_n) begin if (!i_rst_n) begin
miso_shift <= 32'd0; miso_shift <= 32'd0;
end else begin miso_loaded <= 1'b0;
end
else begin
if (!cs_active) begin if (!cs_active) begin
// Pre-load the shifter while CS is High // Reset shifter while CS is High
// This ensures Bit 31 is ready BEFORE the first clock edge miso_shift <= 32'd0;
miso_shift <= tx_buffer; end
end else begin else begin
// Shift on Falling Edge (Master samples on Rising) if (i_rvalid && (bit_cnt == 'd8)) begin
if (sclk_fall) begin miso_shift <= {i_rdata,8'd0};
miso_loaded <= 1'b1;
end
if (miso_loaded && sclk_fall) begin
// Shift out MSB on falling edges (data valid before master's rising-edge sample)
if (bit_cnt > 'd8) begin
miso_shift <= {miso_shift[30:0], 1'b0}; miso_shift <= {miso_shift[30:0], 1'b0};
end end
end end
end end
end end
end
// Tri-state MISO when CS is high (optional, usually good practice) // Tri-state MISO when CS is high (optional, usually good practice)
// If your board doesn't need tristate, just use: assign o_miso = miso_shift[31]; // If your board doesn't need tristate, just use: assign o_miso = miso_shift[31];
assign o_miso = (cs_active) ? miso_shift[31] : 1'bz; assign o_miso = (cs_active) ? miso_shift[31] : 1'bz;
// --- 4. Register Control FSM --- // --- 4. Register Control FSM ---
// Command format: [WR:1b][Addr:7b][Data:24b] = 32 bits
// recv_reg layout after 32 bits: {WR, Addr[6:0], Data[23:0]}
always @(posedge i_sys_clk) begin always @(posedge i_sys_clk) begin
if (!i_rst_n) begin if (!i_rst_n) begin
@@ -165,9 +185,16 @@ module BUS_Con (
case (state) case (state)
IDLE: begin IDLE: begin
if (data_ready) begin if (data_ready) begin
// Extract fields from received command
if (wr_flag == 1'b1) begin
addr_out <= recv_reg[30:24]; addr_out <= recv_reg[30:24];
data_out <= recv_reg[23:0]; data_out <= recv_reg[23:0];
wr_out <= recv_reg[31]; wr_out <= recv_reg[31];
end
else begin
addr_out <= recv_reg[6:0];
wr_out <= recv_reg[7];
end
if (!i_reg_busy) begin if (!i_reg_busy) begin
cmd_valid_out <= 1'b1; cmd_valid_out <= 1'b1;
@@ -210,6 +237,6 @@ module BUS_Con (
assign o_wready = (state == IDLE); assign o_wready = (state == IDLE);
// Pass through unused signal or hook it up if needed // Pass through unused signal or hook it up if needed
assign o_rvalid = 1'b0; assign o_rvalid = i_rvalid;
endmodule endmodule
CPLD3/CPLD3_Debug.rva
+9 -66
View File
@@ -27,75 +27,18 @@
<WinUI CoreIndex="0"> <WinUI CoreIndex="0">
<TraceSigTreeData> <TraceSigTreeData>
<TraceSignal IsHidden="false" Name="i_rst_n" NodeType="0" PortIndex="0"/> <TraceSignal IsHidden="false" Name="i_rst_n" NodeType="0" PortIndex="0"/>
<TraceSignal IsHidden="false" Name="i_cs" NodeType="0" PortIndex="1"/> <TraceSignal IsHidden="false" Name="Bus_Con_3/err_flag" NodeType="0" PortIndex="1"/>
<TraceSignal IsHidden="false" Name="i_mosi" NodeType="0" PortIndex="2"/> <TraceSignal IsHidden="false" Name="CPLD_Con_3/err_flag" NodeType="0" PortIndex="2"/>
<TraceSignal IsHidden="false" Name="i_sclk" NodeType="0" PortIndex="3"/> <TraceSignal IsHidden="false" Name="CPLD_Reg_3/err_flag" NodeType="0" PortIndex="3"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/slot_exec_flag" NodeType="1" PortIndex="4"> <TraceSignal IsHidden="false" Name="CPLD_Con_3/i_con_exec" NodeType="0" PortIndex="4"/>
<TraceSignal IsHidden="false" Name="o_PMU_RC" NodeType="1" PortIndex="5">
<BusRadix Radix="0"/> <BusRadix Radix="0"/>
<IsExpanded Expand="false"/> <IsExpanded Expand="false"/>
</TraceSignal> </TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/slot_exec_flag:0" NodeType="2" PortIndex="4"/> <TraceSignal IsHidden="false" Name="o_PMU_RC:0" NodeType="2" PortIndex="5"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/slot_exec_flag:1" NodeType="2" PortIndex="5"/> <TraceSignal IsHidden="false" Name="o_PMU_RC:1" NodeType="2" PortIndex="6"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/slot_exec_flag:2" NodeType="2" PortIndex="6"/> <TraceSignal IsHidden="false" Name="o_PMU_RC:2" NodeType="2" PortIndex="7"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/slot_exec_flag:3" NodeType="2" PortIndex="7"/> <TraceSignal IsHidden="false" Name="o_PMU_RC:3" NodeType="2" PortIndex="8"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/o_PMU_RC" NodeType="1" PortIndex="8">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/o_PMU_RC:0" NodeType="2" PortIndex="8"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/o_PMU_RC:1" NodeType="2" PortIndex="9"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/o_PMU_RC:2" NodeType="2" PortIndex="10"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/o_PMU_RC:3" NodeType="2" PortIndex="11"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out" NodeType="1" PortIndex="12">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:0" NodeType="2" PortIndex="12"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:1" NodeType="2" PortIndex="13"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:2" NodeType="2" PortIndex="14"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:3" NodeType="2" PortIndex="15"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:4" NodeType="2" PortIndex="16"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:5" NodeType="2" PortIndex="17"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:6" NodeType="2" PortIndex="18"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out" NodeType="1" PortIndex="19">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:0" NodeType="2" PortIndex="19"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:1" NodeType="2" PortIndex="20"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:2" NodeType="2" PortIndex="21"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:3" NodeType="2" PortIndex="22"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:4" NodeType="2" PortIndex="23"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:5" NodeType="2" PortIndex="24"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:6" NodeType="2" PortIndex="25"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:7" NodeType="2" PortIndex="26"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:8" NodeType="2" PortIndex="27"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:9" NodeType="2" PortIndex="28"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:10" NodeType="2" PortIndex="29"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:11" NodeType="2" PortIndex="30"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:12" NodeType="2" PortIndex="31"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:13" NodeType="2" PortIndex="32"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:14" NodeType="2" PortIndex="33"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:15" NodeType="2" PortIndex="34"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:16" NodeType="2" PortIndex="35"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:17" NodeType="2" PortIndex="36"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:18" NodeType="2" PortIndex="37"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:19" NodeType="2" PortIndex="38"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:20" NodeType="2" PortIndex="39"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:21" NodeType="2" PortIndex="40"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:22" NodeType="2" PortIndex="41"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:23" NodeType="2" PortIndex="42"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/state" NodeType="1" PortIndex="43">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/state:0" NodeType="2" PortIndex="43"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/state:1" NodeType="2" PortIndex="44"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/state:2" NodeType="2" PortIndex="45"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/state:3" NodeType="2" PortIndex="46"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/i_con_done" NodeType="0" PortIndex="47"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/busy_flag" NodeType="0" PortIndex="48"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/exec_bit" NodeType="0" PortIndex="49"/>
</TraceSigTreeData> </TraceSigTreeData>
<TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/> <TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/>
<CoreRun Run="true"/> <CoreRun Run="true"/>
CPLD3/CPLD3_Debug.svf
+511
View File
@@ -10,3 +10,514 @@ HIR 0;
TDR 0; TDR 0;
TIR 0; TIR 0;
! setTargetHubs
! enable ER1
SIR 8 TDI (32);
! set reveal core
SDR 21 TDI (00016);
! enable ER2
SIR 8 TDI (38);
! enable ER2
SIR 8 TDI (38);
! enable ER2
SIR 8 TDI (38);
! Set Odd Parity readback
SDR 36 TDI (c20000000);
SDR 36 TDI (c20000000) TDO (000000000) MASK (FFFFFFFFF);
! enable ER2
SIR 8 TDI (38);
! Set Odd Parity
SDR 36 TDI (020000000);
! Set LA Start/Stop readback
SDR 36 TDI (430000000);
SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
! Set LA Start/Stop
SDR 36 TDI (830000000);
! Get Pattern
SDR 36 TDI (430090000);
SDR 36 TDI (430090000) TDO (000000000) MASK (FFFFFFFFF);
! Get Tracy Signature
SDR 36 TDI (c30070000);
SDR 36 TDI (c30070000) TDO (000000000) MASK (FFFFFFFFF);
! Get Tracy Signature
SDR 36 TDI (c30080000);
SDR 36 TDI (c30080000) TDO (000000000) MASK (FFFFFFFFF);
! Set Opcode Value
SDR 36 TDI (000000007);
! Set Mask Value
SDR 36 TDI (000200000);
! Set Opcode Value
SDR 36 TDI (001000006);
! Set Mask Value
SDR 36 TDI (801200000);
! Set Then Num
SDR 36 TDI (010000000);
! Set NEXT THEN
SDR 36 TDI (810040000);
! Set Cnt Cntg
SDR 36 TDI (010030000);
! Set Event Count
SDR 36 TDI (810100000);
! Set Event Count
SDR 36 TDI (010110000);
! Set Then Num
SDR 36 TDI (811000000);
! Set NEXT THEN
SDR 36 TDI (011040000);
! Set Cnt Cntg
SDR 36 TDI (811030000);
! Set Event Count
SDR 36 TDI (011100000);
! Set Event Count
SDR 36 TDI (811110000);
! Get BurstWrite CRC
SDR 36 TDI (c10050000);
SDR 36 TDI (c10050000) TDO (000000000) MASK (FFFFFFFFF);
! Set Truth Tbl Addr Cnter Init
SDR 36 TDI (810020000);
! Set Truth Table Prog
SDR 36 TDI (810010000);
! burst write
SDR 16 TDI (5044);
!==> [JTAG] burst write 2 byte = 5044
! Get BurstWrite CRC
SDR 36 TDI (c10050000);
SDR 36 TDI (c10050000) TDO (000000000) MASK (FFFFFFFFF);
!==> [JTAG] teCRC = DCEF (equation = DCEF)
! Enable TE Trig
SDR 36 TDI (820020003);
! Enable Trig Output OR All readback
SDR 36 TDI (c20000000);
SDR 36 TDI (c20000000) TDO (000000000) MASK (FFFFFFFFF);
! Enable Trig Output OR All
SDR 36 TDI (820000008);
! Set Pre-Trig Sample
SDR 36 TDI (830010085);
! Set Post-Trig Sample
SDR 36 TDI (03002077a);
! setTargetHubs
! enable ER1
SIR 8 TDI (32);
! set reveal core
SDR 21 TDI (00016);
! enable ER2
SIR 8 TDI (38);
! enable ER2
SIR 8 TDI (38);
! Set LA Start cores
SDR 36 TDI (030000001);
! setTargetHubs
! enable ER1
SIR 8 TDI (32);
! set reveal core
SDR 21 TDI (00016);
! enable ER2
SIR 8 TDI (38);
! Get Force Trigger bit
SDR 36 TDI (430000000);
SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
! enable ER2
SIR 8 TDI (38);
! Get Trig Detected Cnt
SDR 36 TDI (430030000);
SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
! enable ER2
SIR 8 TDI (38);
! Get Mem Block Full Cnt
SDR 36 TDI (c30040000);
SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
!==> [JTAG] tmMemFullCnt = 0
! setTargetHubs
! enable ER1
SIR 8 TDI (32);
! set reveal core
SDR 21 TDI (00016);
! enable ER2
SIR 8 TDI (38);
! Get Force Trigger bit
SDR 36 TDI (430000000);
SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
! enable ER2
SIR 8 TDI (38);
! Get Trig Detected Cnt
SDR 36 TDI (430030000);
SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
! enable ER2
SIR 8 TDI (38);
! Get Mem Block Full Cnt
SDR 36 TDI (c30040000);
SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
!==> [JTAG] tmMemFullCnt = 0
! setTargetHubs
! enable ER1
SIR 8 TDI (32);
! set reveal core
SDR 21 TDI (00016);
! enable ER2
SIR 8 TDI (38);
! Get Force Trigger bit
SDR 36 TDI (430000000);
SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
! enable ER2
SIR 8 TDI (38);
! Get Trig Detected Cnt
SDR 36 TDI (430030000);
SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
! enable ER2
SIR 8 TDI (38);
! Get Mem Block Full Cnt
SDR 36 TDI (c30040000);
SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
!==> [JTAG] tmMemFullCnt = 0
! setTargetHubs
! enable ER1
SIR 8 TDI (32);
! set reveal core
SDR 21 TDI (00016);
! enable ER2
SIR 8 TDI (38);
! Get Force Trigger bit
SDR 36 TDI (430000000);
SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
! enable ER2
SIR 8 TDI (38);
! Get Trig Detected Cnt
SDR 36 TDI (430030000);
SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
! enable ER2
SIR 8 TDI (38);
! Get Mem Block Full Cnt
SDR 36 TDI (c30040000);
SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
!==> [JTAG] tmMemFullCnt = 1
! Is LA Armed
SDR 36 TDI (430000000);
SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
! Set LA Start/Stop readback
SDR 36 TDI (430000000);
SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
! Set LA Start/Stop
SDR 36 TDI (030000004);
! enable ER2
SIR 8 TDI (38);
! Set LA Start/Stop readback
SDR 36 TDI (430000000);
SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
! enable ER2
SIR 8 TDI (38);
! Set LA Start/Stop
SDR 36 TDI (030000004);
! enable ER2
SIR 8 TDI (38);
! Get Trig Detected Cnt
SDR 36 TDI (430030000);
SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
! Get Mem Block Full Cnt
SDR 36 TDI (c30040000);
SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
!==> [JTAG] tmMemFullCnt = 1
! Get Last Addr Written
SDR 36 TDI (430060000);
SDR 36 TDI (430060000) TDO (000000000) MASK (FFFFFFFFF);
!==> [JTAG] tmLastAddrWritten = 1681
! Get Multiple Trig Enbl
SDR 36 TDI (430050000);
SDR 36 TDI (430050000) TDO (000000000) MASK (FFFFFFFFF);
! Get BurstRead CRC
SDR 36 TDI (4300a0000);
SDR 36 TDI (4300a0000) TDO (000000000) MASK (FFFFFFFFF);
! enable ER2
SIR 8 TDI (38);
! Set Trace Mem Cnter Init
SDR 36 TDI (080000000);
! burst read
SDR 18432 TDI (00000000000000000000000000000000000000000000000000000000000000000
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FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
FFFFFFFFFFFFF);
!==> [JTAG] burst read 2304 byte = 108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108846211088440201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008040201008044221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221108844221
! Get BurstRead CRC
SDR 36 TDI (4300a0000);
SDR 36 TDI (4300a0000) TDO (000000000) MASK (FFFFFFFFF);
!==> [JTAG] dummy = B030
! Get BurstRead CRC
SDR 36 TDI (4300a0000);
SDR 36 TDI (4300a0000) TDO (000000000) MASK (FFFFFFFFF);
!==> [JTAG] tmCRC = B030 (equation = B221)
! Get Pre-Trig Sample Num
SDR 36 TDI (c30010000);
SDR 36 TDI (c30010000) TDO (000000000) MASK (FFFFFFFFF);
! Get Post-Trig Sample Num
SDR 36 TDI (c30020000);
SDR 36 TDI (c30020000) TDO (000000000) MASK (FFFFFFFFF);
!==> [TMEN] preTrig=128
! Get Pre-Trig Samples Captured
SDR 36 TDI (c31000000);
SDR 36 TDI (c31000000) TDO (000000000) MASK (FFFFFFFFF);
! Get Trig Ptr
SDR 36 TDI (c32000000);
SDR 36 TDI (c32000000) TDO (000000000) MASK (FFFFFFFFF);
!==> [JTAG] tmTrigPTr = 1815
!==> [TMEN] trigPtr=1815
!==> [TMEN] pre_cap=true (preCap=1, regNum=0, offset=0)
!==> [TMEN] trigPtr=1810 (- 5)
!==> [TMEN] (pre_cap) out:3730-2048
!==> [TMEN] (pre_cap) out:1682-1811
!==> [TMEN] (pre_cap) triggerPosition=128
CPLD3/CPLD3_Debug.trc
+2051 -2051
View File
File diff suppressed because it is too large Load Diff
CPLD3/CPLD_Con.v
+6 -6
View File
@@ -72,7 +72,7 @@ module CPLD_Con (
freq_slot_flag <= 'd0; freq_slot_flag <= 'd0;
dc_slot_flag<='d0; dc_slot_flag<='d0;
done_flag <= 'd1; done_flag <= 'd1;
PMU_RC <= 4'b1111; PMU_RC <= 4'b0000;
end end
else begin else begin
if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin
@@ -117,19 +117,19 @@ module CPLD_Con (
else if (dc_t == 1'b1) begin else if (dc_t == 1'b1) begin
case (dc_slot_flag) case (dc_slot_flag)
4'b0001: begin 4'b0001: begin
PMU_RC <= 4'b0001; PMU_RC <= 4'b1110;
end end
4'b0010: begin 4'b0010: begin
PMU_RC <= 4'b0010; PMU_RC <= 4'b1101;
end end
4'b0100: begin 4'b0100: begin
PMU_RC <= 4'b0100; PMU_RC <= 4'b1011;
end end
4'b1000: begin 4'b1000: begin
PMU_RC <= 4'b1000; PMU_RC <= 4'b0111;
end end
default:begin default:begin
PMU_RC <= 4'b0000; PMU_RC <= 4'b1111;
end end
endcase endcase
end end
CPLD3/NewExtIns_CPLD3.lpf
+1 -1
View File
@@ -13,7 +13,7 @@ IOBUF PORT "i_mosi" IO_TYPE=LVCMOS33 ;
IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 ;
IOBUF PORT "i_sclk" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_sclk" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ; IOBUF PORT "o_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ;
IOBUF PORT "o_rvaild" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_rvalid" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "i_sys_clk" DRIVE=NA IO_TYPE=LVCMOS33 SLEWRATE=NA PULLMODE=DOWN ; IOBUF PORT "i_sys_clk" DRIVE=NA IO_TYPE=LVCMOS33 SLEWRATE=NA PULLMODE=DOWN ;
IOBUF PORT "o_err" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_err" IO_TYPE=LVCMOS33 ;
CPLD3/Reg_file.v
+1 -1
View File
@@ -33,7 +33,7 @@ module Reg_file (
// --- Parameters --- // --- Parameters ---
localparam REG_COUNT = 16; localparam REG_COUNT = 16;
localparam [23:0] localparam [23:0]
IDENT = 24'h800000 | 12'b0001_0000_0000, //CPLD3==1,version=1.0.0 IDENT = 24'h800000 | 12'b0001_0001_0000, //CPLD3==1,version=1.1.0
STATE_INIT = 24'h800000; STATE_INIT = 24'h800000;
// State Machine Definition // State Machine Definition
CPLD3/RelayConTop.v
+2 -2
View File
@@ -8,7 +8,7 @@ module RelayConTop (
output o_miso, output o_miso,
output o_rvalid, output o_rvalid,
input i_rready, input i_rready,
input i_wvaild, input i_wvalid,
output [3:0]o_PMU_RC, output [3:0]o_PMU_RC,
@@ -42,7 +42,7 @@ module RelayConTop (
wire [23:0]DC_Con3 ; wire [23:0]DC_Con3 ;
wire [23:0]DC_Con4 ; wire [23:0]DC_Con4 ;
wire con_rvaild; wire con_rvalid;
wire con_done; wire con_done;
BUS_Con Bus_Con_3( BUS_Con Bus_Con_3(
CPLD3/debug.rvl
+10 -109
View File
@@ -1,7 +1,7 @@
<Project ModBy="Inserter" SigType="0" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD3/debug.rvl" Date="2026-05-26"> <Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/debug.rvl" Date="2026-05-29">
<IP Version="1_6_042617"/> <IP Version="1_6_042617"/>
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD3"/> <Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD3"/>
<Core InsertDataset="0" Insert="1" Reveal_sig="695532996" Name="RelayConTop_LA0" ID="0"> <Core InsertDataset="0" Insert="1" Reveal_sig="695936675" Name="RelayConTop_LA0" ID="0">
<Setting> <Setting>
<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/> <Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/> <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
@@ -12,122 +12,23 @@
</Setting> </Setting>
<Dataset Name="Base"> <Dataset Name="Base">
<Trace> <Trace>
<Sig Type="SIG" Name="Bus_Con_3/i_sclk"/>
<Sig Type="SIG" Name="i_rst_n"/> <Sig Type="SIG" Name="i_rst_n"/>
<Sig Type="SIG" Name="Bus_Con_3/i_cs"/>
<Sig Type="SIG" Name="Bus_Con_3/i_mosi"/>
<Sig Type="SIG" Name="Bus_Con_3/err_flag"/> <Sig Type="SIG" Name="Bus_Con_3/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_3/err_flag"/> <Sig Type="SIG" Name="CPLD_Con_3/err_flag"/>
<Sig Type="SIG" Name="CPLD_Reg_3/err_flag"/> <Sig Type="SIG" Name="CPLD_Reg_3/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_con_exec"/> <Sig Type="SIG" Name="CPLD_Con_3/i_con_exec"/>
<Bus Name="CPLD_Con_3/i_DC_Con1"> <Bus Name="o_PMU_RC">
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:0"/> <Sig Type="SIG" Name="o_PMU_RC:0"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:1"/> <Sig Type="SIG" Name="o_PMU_RC:1"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:2"/> <Sig Type="SIG" Name="o_PMU_RC:2"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:3"/> <Sig Type="SIG" Name="o_PMU_RC:3"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:4"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:5"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:6"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:7"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:8"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:9"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:10"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:11"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:12"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:13"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:14"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:15"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:16"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:17"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:18"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:19"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:20"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:21"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:22"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con2">
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:0"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:1"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:2"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:3"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:4"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:5"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:6"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:7"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:8"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:9"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:10"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:11"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:12"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:13"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:14"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:15"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:16"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:17"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:18"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:19"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:20"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:21"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:22"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con3">
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:0"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:1"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:2"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:3"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:4"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:5"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:6"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:7"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:8"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:9"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:10"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:11"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:12"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:13"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:14"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:15"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:16"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:17"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:18"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:19"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:20"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:21"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:22"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con4">
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:0"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:1"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:2"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:3"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:4"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:5"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:6"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:7"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:8"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:9"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:10"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:11"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:12"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:13"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:14"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:15"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:16"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:17"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:18"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:19"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:20"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:21"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:22"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:23"/>
</Bus> </Bus>
</Trace> </Trace>
<Trigger> <Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="con_exec,"/> <TU Serialbits="0" Type="0" ID="1" Sig="i_rst_n,"/>
<TU Serialbits="0" Type="0" ID="2" Sig="CPLD_Con_3/i_con_exec,"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/> <TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
</Trigger> </Trigger>
</Dataset> </Dataset>
</Core> </Core>
CPLD3/debug.rvs
+9 -108
View File
@@ -1,4 +1,4 @@
<Project ModBy="Inserter" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD3/debug.rvl" Date="2026-05-26"> <Project ModBy="Analyzer" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/debug.rvs" Date="2026-05-29">
<Core Name="RelayConTop_LA0"> <Core Name="RelayConTop_LA0">
<Setting> <Setting>
<Capture SamplesPerTrig="2048" NumTrigsCap="1"/> <Capture SamplesPerTrig="2048" NumTrigsCap="1"/>
@@ -7,122 +7,23 @@
</Setting> </Setting>
<Dataset Name="Base"> <Dataset Name="Base">
<Trace> <Trace>
<Sig Name="Bus_Con_3/i_sclk"/>
<Sig Name="i_rst_n"/> <Sig Name="i_rst_n"/>
<Sig Name="Bus_Con_3/i_cs"/>
<Sig Name="Bus_Con_3/i_mosi"/>
<Sig Name="Bus_Con_3/err_flag"/> <Sig Name="Bus_Con_3/err_flag"/>
<Sig Name="CPLD_Con_3/err_flag"/> <Sig Name="CPLD_Con_3/err_flag"/>
<Sig Name="CPLD_Reg_3/err_flag"/> <Sig Name="CPLD_Reg_3/err_flag"/>
<Sig Name="CPLD_Con_3/i_con_exec"/> <Sig Name="CPLD_Con_3/i_con_exec"/>
<Bus Name="CPLD_Con_3/i_DC_Con1" Radix="0"> <Bus Name="o_PMU_RC" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con1:0"/> <Sig Name="o_PMU_RC:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:1"/> <Sig Name="o_PMU_RC:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:2"/> <Sig Name="o_PMU_RC:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:3"/> <Sig Name="o_PMU_RC:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con2" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con2:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con3" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con3:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con4" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con4:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:23"/>
</Bus> </Bus>
</Trace> </Trace>
<Trigger> <Trigger>
<TU Operator="6" Name="TU1" ID="1" Value="0" Radix="0"/> <TU Operator="7" Name="TU1" ID="1" Value="0" Radix="0"/>
<TU Operator="6" Name="TU2" ID="2" Value="0" Radix="0"/>
<TE Enable="1" Expression="TU1" Name="TE1" ID="1"/> <TE Enable="1" Expression="TU1" Name="TE1" ID="1"/>
<TE Enable="1" Expression="TU2" Name="TE2" ID="2"/>
</Trigger> </Trigger>
</Dataset> </Dataset>
</Core> </Core>
CPLD3/impl1/NewExtIns_CPLD3_impl1.areasrr
-158
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@@ -1,158 +0,0 @@
----------------------------------------------------------------------
Report for cell RelayConTop.verilog
Register bits: 1206 of 6864 (18%)
PIC Latch: 0
I/O cells: 14
Cell usage:
cell count Res Usage(%)
CCU2D 41 100.0
FD1P3AX 424 100.0
FD1P3AY 2 100.0
FD1P3BX 32 100.0
FD1P3DX 437 100.0
FD1P3IX 133 100.0
FD1P3JX 1 100.0
FD1S3AX 6 100.0
FD1S3AY 1 100.0
FD1S3BX 3 100.0
FD1S3DX 140 100.0
FD1S3IX 16 100.0
FD1S3JX 1 100.0
GSR 1 100.0
IB 5 100.0
IFS1P3IX 3 100.0
IFS1P3JX 1 100.0
INV 13 100.0
L6MUX21 73 100.0
OB 8 100.0
OBZ 1 100.0
OFS1P3DX 2 100.0
OFS1P3JX 4 100.0
ORCALUT4 1035 100.0
PFUMX 102 100.0
PUR 1 100.0
VHI 13 100.0
VLO 13 100.0
jtagconn16 1 100.0
pmi_distributed_dpram_2s_1s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 1 100.0
pmi_ram_dp_Z4 1 100.0
SUB MODULES
BUS_Con_uniq_1 1 100.0
CPLD_Con_uniq_1 1 100.0
Reg_file_uniq_1 1 100.0
relaycontop_la0 1 100.0
relaycontop_la0_trig 1 100.0
reveal_coretop 1 100.0
TOTAL 2521
----------------------------------------------------------------------
Report for cell CPLD_Con_uniq_1.netlist
Instance path: CPLD_Con_3
Cell usage:
cell count Res Usage(%)
FD1P3IX 8 6.0
FD1P3JX 1 100.0
FD1S3IX 6 37.5
ORCALUT4 34 3.3
VHI 1 7.7
VLO 1 7.7
TOTAL 51
----------------------------------------------------------------------
Report for cell Reg_file_uniq_1.netlist
Instance path: CPLD_Reg_3
Cell usage:
cell count Res Usage(%)
FD1P3AX 406 95.8
FD1P3AY 2 100.0
FD1S3AX 4 66.7
FD1S3AY 1 100.0
L6MUX21 72 98.6
ORCALUT4 243 23.5
PFUMX 96 94.1
VHI 1 7.7
VLO 1 7.7
TOTAL 826
----------------------------------------------------------------------
Report for cell BUS_Con_uniq_1.netlist
Instance path: Bus_Con_3
Cell usage:
cell count Res Usage(%)
FD1P3IX 125 94.0
FD1S3AX 2 33.3
FD1S3IX 10 62.5
FD1S3JX 1 100.0
ORCALUT4 100 9.7
VHI 1 7.7
VLO 1 7.7
TOTAL 240
----------------------------------------------------------------------
Report for cell reveal_coretop.verilog
Instance path: RelayConTop_reveal_coretop_instance
Cell usage:
cell count Res Usage(%)
CCU2D 41 100.0
FD1P3AX 18 4.2
FD1P3BX 32 100.0
FD1P3DX 437 100.0
FD1S3BX 3 100.0
FD1S3DX 140 100.0
INV 12 92.3
L6MUX21 1 1.4
ORCALUT4 658 63.6
PFUMX 6 5.9
VHI 9 69.2
VLO 9 69.2
jtagconn16 1 100.0
pmi_distributed_dpram_2s_1s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 1 100.0
pmi_ram_dp_Z4 1 100.0
SUB MODULES
relaycontop_la0 1 100.0
relaycontop_la0_trig 1 100.0
TOTAL 1371
----------------------------------------------------------------------
Report for cell relaycontop_la0.netlist
Instance path: RelayConTop_reveal_coretop_instance.relaycontop_la0_inst_0
Cell usage:
cell count Res Usage(%)
CCU2D 41 100.0
FD1P3AX 18 4.2
FD1P3BX 32 100.0
FD1P3DX 437 100.0
FD1S3BX 3 100.0
FD1S3DX 140 100.0
INV 12 92.3
L6MUX21 1 1.4
ORCALUT4 658 63.6
PFUMX 6 5.9
VHI 8 61.5
VLO 8 61.5
pmi_distributed_dpram_2s_1s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 1 100.0
pmi_ram_dp_Z4 1 100.0
SUB MODULES
relaycontop_la0_trig 1 100.0
TOTAL 1367
----------------------------------------------------------------------
Report for cell relaycontop_la0_trig.netlist
Instance path: RelayConTop_reveal_coretop_instance.relaycontop_la0_inst_0.trig_u
Cell usage:
cell count Res Usage(%)
CCU2D 9 22.0
FD1P3AX 16 3.8
FD1P3DX 29 6.6
FD1S3BX 3 100.0
FD1S3DX 22 15.7
INV 5 38.5
L6MUX21 1 1.4
ORCALUT4 119 11.5
PFUMX 3 2.9
VHI 5 38.5
VLO 5 38.5
pmi_distributed_dpram_2s_1s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 1 100.0
TOTAL 218
CPLD3/impl1/NewExtIns_CPLD3_impl1.bit
BIN
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Binary file not shown.
CPLD3/impl1/NewExtIns_CPLD3_impl1.jed
+2756 -2756
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File diff suppressed because it is too large Load Diff
CPLD3/impl1/NewExtIns_CPLD3_impl1.pt
-10
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@@ -1,10 +0,0 @@
-v
10
-gt
-sethld
-sp 4
-sphld m

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