yuysh/NewInstrCalBoard_CPLD
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yuysh 8f65c6908d Change RC_RLSel logic
2026-06-01 16:19:58 +08:00
CPLD1
Change RC_RLSel logic
2026-06-01 16:19:58 +08:00
CPLD2
Change MISO logic
2026-06-01 14:44:18 +08:00
CPLD3
Change MISO logic
2026-06-01 14:44:18 +08:00
.gitignore
Update ignored items
2026-05-28 10:41:25 +08:00
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Description
新仪表校准版CPLD仓库
3.3 MiB
Releases 2
v1.1.2
Latest
2026-06-16 07:01:32 +00:00
Languages
Verilog 49.3%
SystemVerilog 38.9%
TeX 11.8%