Jeremy Shen 61076299a0 Add SPI testbench

2026-06-08 10:14:17 +08:00

CPLD1

Add SPI testbench

2026-06-08 10:14:17 +08:00

CPLD2

Add Channel Naming for CPLD2

2026-06-08 09:53:57 +08:00

CPLD3

Fix version code for CPLD3

2026-06-02 14:50:29 +08:00

.gitignore

Update ignored items

2026-05-28 10:41:25 +08:00

S

Description

新仪表校准版CPLD仓库

3.3 MiB

Releases 2

v1.1.2

Latest

2026-06-16 07:01:32 +00:00

Languages

Verilog 49.3%

SystemVerilog 38.9%

TeX 11.8%