Jeremy Shen b3eef70c28 CPLD1 fix DMM & OC shifting logic

2026-05-29 17:42:08 +08:00

CPLD1

CPLD1 fix DMM & OC shifting logic

2026-05-29 17:42:08 +08:00

CPLD2

Modify simulation files

2026-05-29 16:32:58 +08:00

CPLD3

Modify simulation files

2026-05-29 16:32:58 +08:00

.gitignore

Update ignored items

2026-05-28 10:41:25 +08:00

S

Description

新仪表校准版CPLD仓库

3.3 MiB

Releases 2

v1.1.2

Latest

2026-06-16 07:01:32 +00:00

Languages

Verilog 49.3%

SystemVerilog 38.9%

TeX 11.8%