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yuysh
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NewInstrCalBoard_CPLD
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607b43837d6ae424e8afb84888564a3bbfcc8649
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yuysh
607b43837d
Fix RC_RLSel Shifting logic(2/?)
2026-06-02 18:33:16 +08:00
CPLD1
Fix RC_RLSel Shifting logic(2/?)
2026-06-02 18:33:16 +08:00
CPLD2
Fix MISO logic for CPLD2 & CPLD3
2026-06-02 14:50:13 +08:00
CPLD3
Fix version code for CPLD3
2026-06-02 14:50:29 +08:00
.gitignore
Update ignored items
2026-05-28 10:41:25 +08:00
S
Description
新仪表校准版CPLD仓库
3.3
MiB
Releases
2
v1.1.2
Latest
2026-06-16 07:01:32 +00:00
Languages
Verilog
49.3%
SystemVerilog
38.9%
TeX
11.8%