yuysh/NewInstrCalBoard_CPLD
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32 Commits 1 Branch 2 Tags
36e6eb57684e985e67e4a57fc434a24eff5069cc
Commit Graph
21 Commits
Author SHA1 Message Date
yuysh 36e6eb5768 Unify the OC_Con logic 2026-06-05 16:49:20 +08:00
yuysh 607b43837d Fix RC_RLSel Shifting logic(2/?) 2026-06-02 18:33:16 +08:00
Jeremy Shen ff4d6a10cc Fix RC_RLSel Shifting logic 2026-06-02 17:21:32 +08:00
Jeremy Shen ed3fbd7cf5 Fix the SPI MISO logic 
Modify the tb to make it easier from all aspects
 2026-06-02 11:23:34 +08:00
Jeremy Shen 070ad1c768 Merge branch 'master' of http://mkb.local:3000/yuysh/NewInstrCalBoard_CPLD 2026-06-01 18:03:33 +08:00
Jeremy Shen 34b8bdbdd8 Add SPI_Reg testbench 2026-06-01 18:03:16 +08:00
yuysh 263eb9f16d TODO: Fix MISO logic (1/?) 2026-06-01 16:20:38 +08:00
yuysh 8f65c6908d Change RC_RLSel logic 2026-06-01 16:19:58 +08:00
Jeremy Shen e60d56dd26 Change MISO logic 2026-06-01 14:44:18 +08:00
Jeremy Shen 5b949c6b63 Fix MISO Logic 2026-06-01 12:37:02 +08:00
yuysh 54a64ec222 Bug fixes for all CPLDs 2026-05-29 18:31:27 +08:00
Jeremy Shen b3eef70c28 CPLD1 fix DMM & OC shifting logic 2026-05-29 17:42:08 +08:00
yuysh 3e722a7f15 Modify simulation files 2026-05-29 16:32:58 +08:00
yuysh 611945be04 Update CPLD1 output 2026-05-28 10:41:58 +08:00
yuysh da61ebe108 Update ignored items 2026-05-28 10:41:25 +08:00
yuysh 8de946787c CPLD1 debug logic too large, delete some signals 2026-05-28 10:29:27 +08:00
Jeremy Shen bf6769d814 gitignore fix 2026-05-28 10:25:03 +08:00
Jeremy Shen 9ae77f3dbf Add debug.rvs 2026-05-28 09:31:03 +08:00
Jeremy Shen 0d6272e7c9 Update gitignore again 2026-05-28 09:30:38 +08:00
Jeremy Shen 81e230066e Update gitignore 2026-05-27 17:40:07 +08:00
Jeremy Shen 2c6716e5eb Init Repo 2026-05-27 17:25:48 +08:00