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This commit is contained in:
Jeremy Shen
2026-05-27 17:25:48 +08:00
parent fe2e5a3fdc
commit 2c6716e5eb
46 changed files with 15406 additions and 0 deletions
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CPLD1/BUS_Con.v
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module BUS_Con (
input i_sys_clk,
input i_rst_n,
// SPI Interface
input i_sclk,
input i_mosi,
input i_cs,
output o_miso, // <-- MISO Logic added here
// Local Interface
output o_rvalid, // (Typo in original: o_rvalid)
input i_rvalid, // Valid signal from Backend (Data is ready)
input i_wvalid,
output o_wready,
input i_reg_busy,
input [23:0] i_rdata, // Data from Backend to send to Master
output o_wr,
output o_cmd_valid,
output [23:0] o_data,
output [6:0] o_addr,
output o_err
);
// --- 1. Synchronization ---
reg [1:0] cs_sync;
reg [1:0] sclk_sync;
reg [1:0] mosi_sync;
wire cs_active;
wire cs_rise;
wire sclk_rise; // For Sampling MOSI
wire sclk_fall; // For Shifting MISO
wire mosi_data;
always @(posedge i_sys_clk) begin
if (!i_rst_n) begin
cs_sync <= 2'b11;
sclk_sync <= 2'b00;
mosi_sync <= 2'b00;
end else begin
cs_sync <= {cs_sync[0], i_cs};
sclk_sync <= {sclk_sync[0], i_sclk};
mosi_sync <= {mosi_sync[0], i_mosi};
end
end
assign cs_active = ~cs_sync[1];
assign cs_rise = (!cs_sync[1] && cs_sync[0]);
// SPI Mode 0: Sample MOSI on Rising, Shift MISO on Falling
assign sclk_rise = (!sclk_sync[1] && sclk_sync[0]);
assign sclk_fall = (sclk_sync[1] && !sclk_sync[0]); // Logic for MISO
assign mosi_data = mosi_sync[1];
// --- 2. MOSI (Receive) Logic ---
reg [31:0] recv_reg;
reg [5:0] bit_cnt;
reg data_ready;
reg err_flag;
reg [1:0] state;
//
reg [31:0] tx_buffer; // Holds data waiting for the next CS Low
reg [31:0] miso_shift; // The actual shifter
// Output Registers
reg [6:0] addr_out;
reg [23:0] data_out;
reg wr_out;
reg cmd_valid_out;
//
localparam IDLE = 2'b00;
localparam CMD_SENT = 2'b01;
localparam WAIT_BUSY = 2'b10;
localparam DONE = 2'b11;
always @(posedge i_sys_clk) begin
if (!i_rst_n) begin
recv_reg <= 32'd0;
bit_cnt <= 6'd0;
data_ready <= 1'b0;
err_flag <= 1'b0;
end
else begin
data_ready <= 1'b0;
if (cs_active) begin
if (sclk_rise) begin
recv_reg <= {recv_reg[30:0], mosi_data};
bit_cnt <= bit_cnt + 1'b1;
end
else if (cs_rise) begin
if (bit_cnt == 6'd32) begin
data_ready <= 1'b1;
err_flag <= 1'b0;
bit_cnt <= 6'd0;
end
else if (bit_cnt != 0) begin
err_flag <= 1'b1;
bit_cnt <= 6'd0;
recv_reg <= 'd0;
end
end
end
if (state == DONE) begin
recv_reg <= 'd0;
end
end
end
// --- 3. MISO (Transmit) Logic ---
// Protocol: We shift out 32 bits.
// Format: [8 bit Status/Padding] + [24 bit i_rdata]
// Capture data from backend when valid
always @(posedge i_sys_clk) begin
if (!i_rst_n) begin
tx_buffer <= 32'd0;
end else begin
// If backend provides valid read data, store it.
// We pad the top 8 bits with Zeros (or you can put status flags here)
if (i_rvalid) begin
tx_buffer <= {8'h00, i_rdata};
end
end
end
// Shift data out
always @(posedge i_sys_clk) begin
if (!i_rst_n) begin
miso_shift <= 32'd0;
end else begin
if (!cs_active) begin
// Pre-load the shifter while CS is High
// This ensures Bit 31 is ready BEFORE the first clock edge
miso_shift <= tx_buffer;
end else begin
// Shift on Falling Edge (Master samples on Rising)
if (sclk_fall) begin
miso_shift <= {miso_shift[30:0], 1'b0};
end
end
end
end
// Tri-state MISO when CS is high (optional, usually good practice)
// If your board doesn't need tristate, just use: assign o_miso = miso_shift[31];
assign o_miso = (cs_active) ? miso_shift[31] : 1'bz;
// --- 4. Register Control FSM ---
always @(posedge i_sys_clk) begin
if (!i_rst_n) begin
state <= IDLE;
cmd_valid_out <= 1'b0;
addr_out <= 7'd0;
data_out <= 24'd0;
wr_out <= 1'b0;
end else begin
case (state)
IDLE: begin
if (data_ready) begin
addr_out <= recv_reg[30:24];
data_out <= recv_reg[23:0];
wr_out <= recv_reg[31];
if (!i_reg_busy) begin
cmd_valid_out <= 1'b1;
state <= CMD_SENT;
end else begin
state <= WAIT_BUSY;
end
end
end
WAIT_BUSY: begin
if (!i_reg_busy) begin
cmd_valid_out <= 1'b1;
state <= CMD_SENT;
end
end
CMD_SENT: begin
cmd_valid_out <= 1'b0;
state <= DONE;
end
DONE: begin
if (!i_reg_busy) begin
state <= IDLE;
addr_out <= 'd0;
data_out <= 'd0;
wr_out <= 'd0;
end
end
endcase
end
end
assign o_addr = addr_out;
assign o_data = data_out;
assign o_wr = wr_out;
assign o_cmd_valid = cmd_valid_out;
assign o_err = err_flag;
assign o_wready = (state == IDLE);
// Pass through unused signal or hook it up if needed
assign o_rvalid = i_rvalid;
endmodule
CPLD1/CPLD1_Debug.rva
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<!DOCTYPE ispTLA>
<ispTLA>
<CreationDate>??? 1?? 13 11:09:52 2026</CreationDate>
<XCFFileName/>
<CableSetting>
<IsTRSTConnected val="false"/>
<TRSTSetting val="0"/>
<IsBSCANConnected val="false"/>
<BSCANSetting val="0"/>
<CableType val="USB"/>
<PortAddress val="0"/>
<PortSetting val="0"/>
<TCKDelay val="1"/>
</CableSetting>
<DeviceCount>1</DeviceCount>
<Device>
<DeviceIndex>0</DeviceIndex>
<DeviceName>1. LCMXO2-7000HC</DeviceName>
<DeviceID>0x012BD043</DeviceID>
<HasIspTRACY>true</HasIspTRACY>
<HasJTAG2WB>false</HasJTAG2WB>
<SERDES/>
<IRBypassLen>8</IRBypassLen>
<RVLFileName>debug.rvl</RVLFileName>
<RVSFileName>debug.rvs</RVSFileName>
<LACoreCount>1</LACoreCount>
<WinUI CoreIndex="0">
<TraceSigTreeData>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_cs" NodeType="0" PortIndex="0"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_mosi" NodeType="0" PortIndex="1"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_sclk" NodeType="0" PortIndex="2"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/exec_flag" NodeType="0" PortIndex="3"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/i_con_exec" NodeType="0" PortIndex="4"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/slot_exec_flag" NodeType="1" PortIndex="5">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/slot_exec_flag:0" NodeType="2" PortIndex="5"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/slot_exec_flag:1" NodeType="2" PortIndex="6"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/slot_exec_flag:2" NodeType="2" PortIndex="7"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/slot_exec_flag:3" NodeType="2" PortIndex="8"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x01" NodeType="1" PortIndex="9">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x01:0" NodeType="2" PortIndex="9"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x01:1" NodeType="2" PortIndex="10"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x01:2" NodeType="2" PortIndex="11"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x01:3" NodeType="2" PortIndex="12"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x17" NodeType="1" PortIndex="13">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x17:0" NodeType="2" PortIndex="13"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x17:1" NodeType="2" PortIndex="14"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x17:2" NodeType="2" PortIndex="15"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x17:3" NodeType="2" PortIndex="16"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN" NodeType="1" PortIndex="17">
<BusRadix Radix="0"/>
<IsExpanded Expand="true"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="o_DMM_EN:0" NodeType="2" PortIndex="17"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:1" NodeType="2" PortIndex="18"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:2" NodeType="2" PortIndex="19"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:3" NodeType="2" PortIndex="20"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:4" NodeType="2" PortIndex="21"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:5" NodeType="2" PortIndex="22"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:6" NodeType="2" PortIndex="23"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:7" NodeType="2" PortIndex="24"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:8" NodeType="2" PortIndex="25"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:9" NodeType="2" PortIndex="26"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:10" NodeType="2" PortIndex="27"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:11" NodeType="2" PortIndex="28"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:12" NodeType="2" PortIndex="29"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:13" NodeType="2" PortIndex="30"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:14" NodeType="2" PortIndex="31"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:15" NodeType="2" PortIndex="32"/>
<TraceSignal IsHidden="false" Name="o_IO_RC1" NodeType="0" PortIndex="33"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx" NodeType="1" PortIndex="34">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx:0" NodeType="2" PortIndex="34"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx:1" NodeType="2" PortIndex="35"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx:2" NodeType="2" PortIndex="36"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx:3" NodeType="2" PortIndex="37"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx:4" NodeType="2" PortIndex="38"/>
</TraceSigTreeData>
<TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/>
<CoreRun Run="true"/>
<CoreWndUIData>
<ClockFrequency Unit="ns" Frequency="-1.0"/>
</CoreWndUIData>
</WinUI>
</Device>
</ispTLA>
CPLD1/CPLD1_Debug.svf
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CPLD1/CPLD1_Debug.trc
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CPLD1/CPLD1_sim.log
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#
# vlib work
# vlog -sv tb_RelayConTop.sv RelayConTop.v BUS_Con.v Reg_file.v CPLD_Con.v
# vsim tb_RelayConTop
# run -all
# quit
#
# Questa Lattice OEM Edition-64 vlog 2024.2 Compiler 2024.05 May 20 2024
# Start time: 18:32:29 on May 25,2026
# vlog -sv tb_RelayConTop.sv RelayConTop.v BUS_Con.v Reg_file.v CPLD_Con.v
# -- Compiling module tb_RelayConTop
# ** Warning: tb_RelayConTop.sv(765): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# -- Compiling module RelayConTop
# -- Compiling module BUS_Con
# -- Compiling module Reg_file
# -- Compiling module CPLD_Con
# ** Warning: CPLD_Con.v(215): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
#
# Top level modules:
# tb_RelayConTop
# End time: 18:32:29 on May 25,2026, Elapsed time: 0:00:00
# Errors: 0, Warnings: 2
# vsim tb_RelayConTop
# Start time: 18:32:29 on May 25,2026
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# // Questa Lattice OEM Edition-64
# // Version 2024.2 linux_x86_64 May 20 2024
# //
# // Unpublished work. Copyright 2024 Siemens
# //
# // This material contains trade secrets or otherwise confidential information
# // owned by Siemens Industry Software Inc. or its affiliates (collectively,
# // "SISW"), or its licensors. Access to and use of this information is strictly
# // limited as set forth in the Customer's applicable agreements with SISW.
# //
# // This material may not be copied, distributed, or otherwise disclosed outside
# // of the Customer's facilities without the express written permission of SISW,
# // and may not be used in any way not expressly authorized by SISW.
# //
# Loading sv_std.std
# Loading work.tb_RelayConTop(fast)
#
# =============================================================
# CPLD1 RelayConTop - Comprehensive Testbench
# System clock: 50 MHz | SPI clock: 2 MHz
# =============================================================
#
# -------------------------------------------------------------
# Group 1: Reset behavior & IDENT register
# -------------------------------------------------------------
# [PASS] Test 1: controller idle)
# [PASS] Test 2:  LOW after reset
# [PASS] Test 3: eset (SPI ready)
# [FAIL] Test 4: (CPLD1, v1.1.0) >>
# [PASS] Test 5:
# eros after reset
# [PASS] Test 6:
# eros after reset
# [PASS] Test 7: zero after reset
#
# -------------------------------------------------------------
# Group 2: Register read/write (ADDR 0-9)
# -------------------------------------------------------------
# [FAIL] Test 8: write/read back >>
# [FAIL] Test 9: write/read back >>
# [FAIL] Test 10: write/read back >>
# [FAIL] Test 11: write/read back >>
# [FAIL] Test 12:  back (PMU mode) >>
# [FAIL] Test 13: write/read back >>
# [FAIL] Test 14: write/read back >>
# [FAIL] Test 15: write/read back >>
# [FAIL] Test 16: default (RDY=1) >>
#
# -------------------------------------------------------------
# Group 3: Execution protocol
# -------------------------------------------------------------
# [PASS] Test 17: cution completes
# [FAIL] Test 18: essful execution >>
# [PASS] Test 19: tion (SPI ready)
# [PASS] Test 20: tes successfully
# [FAIL] Test 21: C slot execution >>
#
# -------------------------------------------------------------
# Group 4: Frequency slot decoding (all 4 slots)
# -------------------------------------------------------------
# Slot1 Ch5 (range 1-8): OC_x01=1, DMM_EN[0]=1
# [PASS] Test 22: t1 Ch5 exec done
# [FAIL] Test 23: ot1: RC_T27 idle >> RC_T27 mismatch
# [FAIL] Test 24: 5: PMU_OC_1[0]=1 >> OC_1[0] mismatch
# [FAIL] Test 25: Ch5: DMM_EN[0]=1 >>
# M_EN[0] mismatch
# [PASS] Test 26: 5: PMU_OC_2[0]=0
# Slot1 Ch50 (range 9-72): DMM_EN[1]=1
# [PASS] Test 27: 1 Ch50 exec done
# [FAIL] Test 28: h50: DMM_EN[1]=1 >>
# M_EN[1] mismatch
# [PASS] Test 29: 0: PMU_OC_1[0]=0
# Slot1 Ch100 (range 73-136): OC_x17=1, DMM_EN[2]=1
# [PASS] Test 30:  Ch100 exec done
# [FAIL] Test 31: : PMU_OC_1[16]=1 >> C_1[16] mismatch
# [FAIL] Test 32: 100: DMM_EN[2]=1 >>
# M_EN[2] mismatch
# Slot1 Ch150 (range 137-200): DMM_EN[3]=1
# [PASS] Test 33:  Ch150 exec done
# [FAIL] Test 34: 150: DMM_EN[3]=1 >>
# M_EN[3] mismatch
# Slot2 Ch5 (range 1-8): OC_x01=2, DMM_EN[4]=1
# [PASS] Test 35: t2 Ch5 exec done
# [FAIL] Test 36: 5: PMU_OC_2[0]=1 >> OC_2[0] mismatch
# [FAIL] Test 37: Ch5: DMM_EN[4]=1 >>
# M_EN[4] mismatch
# Slot3 Ch100 (range 73-136): OC_x17=4, DMM_EN[10]=1
# [PASS] Test 38:  Ch100 exec done
# [FAIL] Test 39: : PMU_OC_3[16]=1 >> C_3[16] mismatch
# [FAIL] Test 40: 00: DMM_EN[10]=1 >>
# _EN[10] mismatch
# Slot4 Ch50 (range 9-72): DMM_EN[5]=1
# [PASS] Test 41: 4 Ch50 exec done
# [FAIL] Test 42: h50: DMM_EN[5]=1 >>
# M_EN[5] mismatch
#
# -------------------------------------------------------------
# Group 5: DC slot PMU mode (DPS is stubbed, not tested)
# -------------------------------------------------------------
# DC1: V mode, Rload=3, Ch=3, PMU
# [PASS] Test 43: V-mode exec done
# [PASS] Test 44: _VSel=1 (V mode)
# [PASS] Test 45: _ISel=0 (V mode)
# [FAIL] Test 46: 8'b100 (Rload=3) >> C_RLSel mismatch
# [FAIL] Test 47: OC_1[0]=1 (Ch=3) >> OC_1[0] mismatch
# DC1: I mode, Rload=1, Ch=11, PMU
# [PASS] Test 48: I-mode exec done
# [FAIL] Test 49: _VSel=0 (I mode) >> RC_VSel mismatch
# [FAIL] Test 50: _ISel=1 (I mode) >> RC_ISel mismatch
# [FAIL] Test 51: l[0]=1 (Rload=1) >> C_RLSel mismatch
# [FAIL] Test 52: C_1[1]=1 (Ch=11) >> OC_1[1] mismatch
# DC2: V mode, Rload=5, Ch=19, PMU
# [PASS] Test 53: V-mode exec done
# [PASS] Test 54: _VSel=1 (V mode)
# [FAIL] Test 55: C_2[2]=1 (Ch=19) >> OC_2[2] mismatch
# DC3: V mode, Rload=10, Ch=27, PMU
# [PASS] Test 56: V-mode exec done
# [FAIL] Test 57: C_3[3]=1 (Ch=27) >> OC_3[3] mismatch
# DC4: V mode, Rload=18, Ch=35, PMU
# [PASS] Test 58: V-mode exec done
# [FAIL] Test 59: 17]=1 (Rload=18) >> C_RLSel mismatch
# [FAIL] Test 60: C_4[4]=1 (Ch=35) >> OC_4[4] mismatch
# [PASS] Test 61: 1 when RC_VSel=1
#
# -------------------------------------------------------------
# Group 6: RC_Tx relay output (slot 4)
# -------------------------------------------------------------
# Slot4: RC_Tx = 6'b101010
# [PASS] Test 62:  RC_Tx exec done
# [FAIL] Test 63: T27=1 (RC_Tx[5]) >> RC_T27 mismatch
# [FAIL] Test 64: T28=0 (RC_Tx[4]) >> RC_T28 mismatch
# [FAIL] Test 65: T29=1 (RC_Tx[3]) >> RC_T29 mismatch
# [FAIL] Test 66: T30=0 (RC_Tx[2]) >> RC_T30 mismatch
# [FAIL] Test 67: T31=1 (RC_Tx[1]) >> RC_T31 mismatch
# [FAIL] Test 68: T32=0 (RC_Tx[0]) >> RC_T32 mismatch
#
# -------------------------------------------------------------
# Group 7: Error conditions
# -------------------------------------------------------------
# Error 7a: Short SPI transaction (16 bits)
# [PASS] Test 69:  SPI transaction
# [PASS] Test 70: ared after reset
# Error 7b: Write to IDENT register (ADDR 0)
# [PASS] Test 71: o IDENT register
# [PASS] Test 72: ared after reset
# Error 7c: Read out-of-bounds address (ADDR 16)
# [PASS] Test 73:  reading ADDR 16
# [PASS] Test 74: ared after reset
# Error 7d: Multiple slot enable bits
# [PASS] Test 75: even with error)
# [PASS] Test 76: ple slot enables
# [PASS] Test 77: ared after reset
# Error 7e: Write to out-of-bounds address (ADDR 31)
# [PASS] Test 78:  writing ADDR 31
# [PASS] Test 79: ared after reset
#
# -------------------------------------------------------------
# Group 8: Edge cases
# -------------------------------------------------------------
# Edge 8a: Brief CS pulse
# [PASS] Test 80: d brief CS pulse
# [PASS] Test 81: ared after reset
# Edge 8b: Rapid successive SPI writes
# [FAIL] Test 82: : ADDR 2 correct >> ADDR 2 mismatch
# [FAIL] Test 83: : ADDR 3 correct >> ADDR 3 mismatch
# [FAIL] Test 84: : ADDR 4 correct >> ADDR 4 mismatch
# [FAIL] Test 85: : ADDR 5 correct >> ADDR 5 mismatch
# Edge 8c: Write to reserved registers
# [FAIL] Test 86: d ADDR 10 and 15 >> Unexpected error
#
# =============================================================
# Test Summary
# =============================================================
# Total tests: 86
# Passed: 41
# Failed: 45
# =============================================================
# *** SOME TESTS FAILED - CHECK DESIGN ***
# =============================================================
#
# ** Note: $finish : tb_RelayConTop.sv(349)
# Time: 1101600 ns Iteration: 0 Instance: /tb_RelayConTop
# End time: 18:32:29 on May 25,2026, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
CPLD1/CPLD_Con.v
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module CPLD_Con (
input i_sys_clk,
input i_rst_n,
input i_con_exec,
// Freq Relay Control
input [23:0]i_freq_relay1,
input [23:0]i_freq_relay2,
input [23:0]i_freq_relay3,
input [23:0]i_freq_relay4,
// DC related Control
input [23:0]i_DC_Con1,
input [23:0]i_DC_Con2,
input [23:0]i_DC_Con3,
input [23:0]i_DC_Con4,
//Output RELAYs
output [3:0]o_OC_x01,
output [3:0]o_OC_x17,
output [18:0]o_DMM_EN,
output o_IO_RC1,
output [5:0]o_RC_Tx,
output [31:0]o_PMU_OC_1 ,
output [31:0]o_PMU_OC_2 ,
output [31:0]o_PMU_OC_3 ,
output [31:0]o_PMU_OC_4 ,
// DMM Mode Sel
output o_RC_VSel,
output o_RC_ISel,
// Output RLoad Sel
output [17:0]o_RC_RLSel,
// FLAGs
output o_con_done,
output o_err
);
//Relay Reg
reg [3:0]OC_x01 ;
reg [3:0]OC_x17 ;
reg [18:0]DMM_en ;
reg[5:0]RC_Tx;
reg io_RC;
reg RC_VISel;
reg [17:0]RC_RLSel ;
reg [31:0]PMU_OC_1 ;
reg [31:0]PMU_OC_2 ;
reg [31:0]PMU_OC_3 ;
reg [31:0]PMU_OC_4 ;
//Condition Tester
reg [15:0]en_t ;
reg freq_t;
reg dc_t;
//Flags
reg exec_flag;
reg err_flag;
reg [3:0]freq_slot_flag;
reg [3:0]dc_slot_flag ;
reg done_flag;
//Counter
reg [15:0]delay_cnt;
always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin
delay_cnt <= 'd0;
end
else begin
if (exec_flag == 1'b1) begin
delay_cnt <= delay_cnt + 1'd1;
end
else begin
delay_cnt <= 'd0;
end
end
end
//Function Identify
always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin
en_t <= 'd0;
freq_t <= 'd0;
dc_t <= 'd0;
end
else begin
en_t <= (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) + (i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0] );
freq_t <= i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0];
dc_t <= i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0];
end
end
// Main Controller Function
always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin
exec_flag <= 1'b0;
err_flag <= 1'b0;
freq_slot_flag <= 'd0;
dc_slot_flag <= 'd0;
OC_x01 <= 'd0;
OC_x17 <= 'd0;
DMM_en <= 'd0;
RC_VISel <='d0;
RC_RLSel <='d0;
PMU_OC_1 <= 'd0 ;
PMU_OC_2 <= 'd0 ;
PMU_OC_3 <= 'd0 ;
PMU_OC_4 <= 'd0 ;
done_flag <= 'd1;
end
else begin
if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin
//To DO: More Sanity Check?
if (en_t > 'd1) begin //Only ONE Enable bit should be set!
err_flag <= 1'b1;
end
else begin
exec_flag <= 1'b1;
done_flag <= 1'b0;
err_flag <= 1'b0;
freq_slot_flag[0] <= i_freq_relay1[0];
freq_slot_flag[1] <= i_freq_relay2[0];
freq_slot_flag[2] <= i_freq_relay3[0];
freq_slot_flag[3] <= i_freq_relay4[0];
RC_Tx <= i_freq_relay4[17:12]; //Special Relay for slot4
dc_slot_flag[0] <= i_DC_Con1[0];
dc_slot_flag[1] <= i_DC_Con2[0];
dc_slot_flag[2] <= i_DC_Con3[0];
dc_slot_flag[3] <= i_DC_Con4[0];
end
end
else if (exec_flag == 1'b1) begin
if (freq_t == 1'b1) begin
io_RC <= i_freq_relay1[0] || i_freq_relay2[0] || i_freq_relay3[0] || i_freq_relay4[0];
case (freq_slot_flag)
4'b0001: begin
if (i_freq_relay1[9:1] < 9) begin
OC_x01 <= 4'b0001;
OC_x17 <= 'd0;
DMM_en <= 19'b000_0000_0000_0000_0001;
end
else if (i_freq_relay1[9:1] < 73) begin
DMM_en <= 19'b000_0000_0000_0000_0010;
OC_x01 <= 'd0;
OC_x17 <= 'd0;
end
else if (i_freq_relay1[9:1] < 137) begin
OC_x17 <= 4'b0001;
OC_x01 <= 'd0;
DMM_en <= 19'b000_0000_0000_0000_0100;
end
else begin
DMM_en <= 19'b000_0000_0000_0000_1000;
OC_x01 <= 'd0;
OC_x17 <= 'd0;
end
end
4'b0010: begin
if (i_freq_relay2[9:1] < 9) begin
OC_x01 <= 4'b0010;
OC_x17 <= 'd0;
DMM_en <= 19'b000_0000_0000_0001_0000;
end
else if (i_freq_relay2[9:1] < 73) begin
DMM_en <= 19'b000_0000_0000_0010_0000;
OC_x01 <= 'd0;
OC_x17 <= 'd0;
end
else if (i_freq_relay2[9:1] < 137) begin
OC_x17 <= 4'b0010;
OC_x01 <= 'd0;
DMM_en <= 19'b000_0000_0000_0100_0000;
end
else begin
OC_x01 <= 'd0;
OC_x17 <= 'd0;
DMM_en <= 19'b000_0000_0000_1000_0000;
end
end
4'b0100: begin
if (i_freq_relay3[9:1] < 9) begin
OC_x01 <= 'b0100;
OC_x17 <= 'd0;
DMM_en <= 19'b000_0000_0001_0000_0000;
end
else if ((i_freq_relay3[9:1] > 64)& (i_freq_relay3[9:1] < 73)) begin
OC_x01 <= 4'b0000;
OC_x17 <= 'd0;
DMM_en <= 19'b000_0000_0010_0000_0000;
end
else if (i_freq_relay3[9:1] < 137) begin
DMM_en <= 19'b000_0000_0100_0000_0000;
OC_x01 <= 'd0;
OC_x17 <= 'b0100;
end
else if (i_freq_relay3[9:1] < 201) begin
OC_x17 <= 4'd0;
OC_x01 <= 'd0;
DMM_en <= 16'b000_0000_1000_0000_0000;
end
end
4'b1000: begin
if (i_freq_relay4[9:1] < 9) begin
OC_x01 <= 4'b1000;
OC_x17 <= 'd0;
DMM_en <= 19'b000_0001_0000_0000_0000;
end
else if (i_freq_relay4[9:1] < 72) begin
DMM_en <= 19'b000_0010_0000_0000_0000;
OC_x01 <= 'd0;
OC_x17 <= 'd0;
end
else if (i_freq_relay4[9:1] < 137) begin
OC_x17 <= 4'b1000;
OC_x01 <= 'd0;
DMM_en <= 19'b000_0100_0000_0000_0000;
end
else begin
OC_x01 <= 'd0;
OC_x17 <= 'd0;
DMM_en <= 19'b000_1000_0000_0000_0000;
end
end
default: begin // You Should NOT be HERE
OC_x01 <= 4'b0000;
OC_x17 <= 4'b0000;
DMM_en <= 'd0;
end
endcase
end
else if (dc_t == 1'b1) begin
case (dc_slot_flag)
4'b0001: begin
if (i_DC_Con1[22] == 1'b1) begin
RC_VISel <= 1'b1; //Select Current
end
else begin
RC_VISel <= 1'b0; //Select Voltage
end
//Sanity Check
if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18) || (i_DC_Con1[9:1] < 1) || (i_DC_Con1[9:1] > 256)) begin
err_flag <= 1'b1;
end
else begin
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con1[21:17] - 1);
if (i_DC_Con1[23] == 1'b0) begin //Select PMU
PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con1[9:1]/8);
DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con1[9:1]/8);
end
else if (i_DC_Con1[23] == 1'b1) begin //Select DPS
end
end
end
4'b0010: begin
if (i_DC_Con2[22] == 1'b1) begin
RC_VISel <= 1'b1; //Select Current
end
else begin
RC_VISel <= 1'b0; //Select Voltage
end
//Sanity Check
if ((i_DC_Con2[21:17] < 1) || (i_DC_Con2[21:17] > 18) || (i_DC_Con2[9:1] < 1) || (i_DC_Con2[9:1] > 256)) begin
err_flag <= 1'b1;
end
else begin
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con2[21:17] - 1);
if (i_DC_Con2[23] == 1'b0) begin //Select PMU
PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con2[9:1]/8);
DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con2[9:1]/8);
end
else if (i_DC_Con2[23] == 1'b1) begin //Select DPS
end
end
end
4'b0100:begin
if (i_DC_Con3[22] == 1'b1) begin
RC_VISel <= 1'b1; //Select Current
end
else begin
RC_VISel <= 1'b0; //Select Voltage
end
//Sanity Check
if ((i_DC_Con3[21:17] < 1) || (i_DC_Con3[21:17] > 18) || (i_DC_Con3[9:1] < 1) || (i_DC_Con3[9:1] > 256)) begin
err_flag <= 1'b1;
end
else begin
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con3[21:17] - 1);
if (i_DC_Con3[23] == 1'b0) begin //Select PMU
PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con3[9:1]/8);
DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con3[9:1]/8);
end
else if (i_DC_Con3[23] == 1'b1) begin //Select DPS
end
end
end
4'b1000:begin
if (i_DC_Con4[22] == 1'b1) begin
RC_VISel <= 1'b1; //Select Current
end
else begin
RC_VISel <= 1'b0; //Select Voltage
end
//Sanity Check
if ((i_DC_Con4[21:17] < 1) || (i_DC_Con4[21:17] > 18) || (i_DC_Con4[9:1] < 1) || (i_DC_Con4[9:1] > 256)) begin
err_flag <= 1'b1;
end
else begin
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con4[21:17] - 1);
if (i_DC_Con4[23] == 1'b0) begin //Select PMU
PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con4[9:1]/8);
DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con4[9:1]/8);
end
else if (i_DC_Con4[23] == 1'b1) begin //Select DPS
end
end
end
default:begin // You Should NOT be HERE
RC_VISel <='d0;
RC_RLSel <='d0;
PMU_OC_1 <= 'd0 ;
PMU_OC_2 <= 'd0 ;
PMU_OC_3 <= 'd0 ;
PMU_OC_4 <= 'd0 ;
DMM_en <= 'd0;
end
endcase
end
done_flag <= 1'b1;
end
end
if (done_flag == 1) begin
exec_flag <= 1'b0;
end
end
assign o_con_done = done_flag;
assign o_DMM_EN = DMM_en;
assign o_OC_x01 = OC_x01;
assign o_OC_x17 = OC_x17;
assign o_IO_RC1 = io_RC;
assign o_err = err_flag;
assign o_RC_Tx = RC_Tx;
assign o_RC_ISel = (RC_VISel==1'b1)?1:0;
assign o_RC_VSel = (RC_VISel==1'b1)?0:1;
assign o_RC_RLSel = RC_RLSel;
assign o_PMU_OC_1 = PMU_OC_1;
assign o_PMU_OC_2 = PMU_OC_2;
assign o_PMU_OC_3 = PMU_OC_3;
assign o_PMU_OC_4 = PMU_OC_4;
endmodule
CPLD1/NewExtInsRelay1.sty
+206
View File
@@ -0,0 +1,206 @@
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<!DOCTYPE strategy>
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<Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
<Property name="PROP_SYN_LibPath" value="" time="0"/>
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
<Property name="PROP_SYN_UseLPF" value="True" time="0"/>
<Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
<Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
<Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
<Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
<Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
<Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
</Strategy>
CPLD1/NewExtIns_CPLD1.ccl
+1
View File
@@ -0,0 +1 @@
VERSION=20110520
CPLD1/NewExtIns_CPLD1.ldf
+41
View File
@@ -0,0 +1,41 @@
<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="NewExtIns_CPLD1" device="LCMXO2-7000HC-4FG484C" default_implementation="impl1">
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
<Options def_top="RelayConTop" top="RelayConTop"/>
<Source name="RelayConTop.v" type="Verilog" type_short="Verilog">
<Options top_module="RelayConTop"/>
</Source>
<Source name="BUS_Con.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="Reg_file.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="tb_RelayConTop.sv" type="Verilog" type_short="Verilog" syn_sim="SimOnly">
<Options VerilogStandard="System Verilog"/>
</Source>
<Source name="RelayConTop_tf.v" type="Verilog" type_short="Verilog" syn_sim="SimOnly">
<Options/>
</Source>
<Source name="CPLD_Con.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="CPLD1_Debug.rva" type="Reveal Analyzer Project File" type_short="RVA">
<Options/>
</Source>
<Source name="NewExtIns_CPLD1.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
<Source name="debug.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
<Options/>
</Source>
<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
<Source name="tb_RelayConTop/tb_RelayConTop.spf" type="Simulation Project File" type_short="SPF">
<Options/>
</Source>
</Implementation>
<Strategy name="Strategy1" file="NewExtInsRelay1.sty"/>
</BaliProject>
CPLD1/NewExtIns_CPLD1.lpf
+313
View File
@@ -0,0 +1,313 @@
RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk";
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
LOCATE COMP "i_sys_clk" SITE "B9" ;
LOCATE COMP "i_rst_n" SITE "Y14" ;
LOCATE COMP "i_sclk" SITE "AA10" ;
LOCATE COMP "i_cs" SITE "AB11" ;
LOCATE COMP "i_mosi" SITE "AB12" ;
LOCATE COMP "o_miso" SITE "AA14" ;
LOCATE COMP "o_err" SITE "AB16" ;
LOCATE COMP "o_DMM_EN[0]" SITE "F17" ;
LOCATE COMP "o_DMM_EN[1]" SITE "E17" ;
LOCATE COMP "o_DMM_EN[2]" SITE "D17" ;
IOBUF PORT "i_cs" IO_TYPE=LVCMOS33 ;
IOBUF PORT "i_mosi" IO_TYPE=LVCMOS33 ;
IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 ;
IOBUF PORT "i_sclk" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ;
IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "i_sys_clk" DRIVE=NA IO_TYPE=LVCMOS33 SLEWRATE=NA PULLMODE=DOWN ;
IOBUF PORT "o_err" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DMM_EN[0]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DMM_EN[1]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DMM_EN[2]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DMM_EN[3]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DMM_EN[4]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DMM_EN[5]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DMM_EN[6]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DMM_EN[7]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DMM_EN[8]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DMM_EN[9]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DMM_EN[10]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DMM_EN[11]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DMM_EN[12]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DMM_EN[13]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DMM_EN[14]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DMM_EN[15]" IO_TYPE=LVCMOS33 ;
LOCATE COMP "o_DMM_EN[3]" SITE "C17" ;
LOCATE COMP "o_DMM_EN[4]" SITE "AB10" ;
LOCATE COMP "o_DMM_EN[5]" SITE "AA11" ;
LOCATE COMP "o_DMM_EN[6]" SITE "AA12" ;
LOCATE COMP "o_DMM_EN[7]" SITE "AB13" ;
LOCATE COMP "o_DMM_EN[8]" SITE "D15" ;
LOCATE COMP "o_DMM_EN[9]" SITE "D14" ;
LOCATE COMP "o_DMM_EN[10]" SITE "C13" ;
LOCATE COMP "o_DMM_EN[11]" SITE "F12" ;
LOCATE COMP "o_DMM_EN[12]" SITE "W12" ;
LOCATE COMP "o_DMM_EN[13]" SITE "V12" ;
LOCATE COMP "o_DMM_EN[14]" SITE "Y12" ;
LOCATE COMP "o_DMM_EN[15]" SITE "V13" ;
LOCATE COMP "o_IO_RC1" SITE "F10" ;
IOBUF PORT "o_IO_RC1" IO_TYPE=LVCMOS33 ;
BLOCK JTAGPATHS ;
LOCATE COMP "o_PMU_OC_1[0]" SITE "M19" ;
LOCATE COMP "o_PMU_OC_1[1]" SITE "R16" ;
LOCATE COMP "o_PMU_OC_1[2]" SITE "N20" ;
LOCATE COMP "o_PMU_OC_1[3]" SITE "P20" ;
LOCATE COMP "o_PMU_OC_1[4]" SITE "G19" ;
LOCATE COMP "o_PMU_OC_1[5]" SITE "J19" ;
LOCATE COMP "o_PMU_OC_1[6]" SITE "H16" ;
LOCATE COMP "o_PMU_OC_1[7]" SITE "J17" ;
LOCATE COMP "o_PMU_OC_1[16]" SITE "W6" ;
LOCATE COMP "o_PMU_OC_1[17]" SITE "AA7" ;
LOCATE COMP "o_PMU_OC_1[18]" SITE "AB6" ;
LOCATE COMP "o_PMU_OC_1[19]" SITE "Y7" ;
LOCATE COMP "o_PMU_OC_1[20]" SITE "V4" ;
LOCATE COMP "o_PMU_OC_1[21]" SITE "R6" ;
LOCATE COMP "o_PMU_OC_1[22]" SITE "U4" ;
LOCATE COMP "o_PMU_OC_1[23]" SITE "T5" ;
LOCATE COMP "o_PMU_OC_2[0]" SITE "E16" ;
LOCATE COMP "o_PMU_OC_2[1]" SITE "F16" ;
LOCATE COMP "o_PMU_OC_2[2]" SITE "D16" ;
LOCATE COMP "o_PMU_OC_2[3]" SITE "G15" ;
LOCATE COMP "o_PMU_OC_2[4]" SITE "C22" ;
LOCATE COMP "o_PMU_OC_2[5]" SITE "D20" ;
LOCATE COMP "o_PMU_OC_2[6]" SITE "D21" ;
LOCATE COMP "o_PMU_OC_2[7]" SITE "D22" ;
LOCATE COMP "o_PMU_OC_2[16]" SITE "A17" ;
LOCATE COMP "o_PMU_OC_2[17]" SITE "A18" ;
LOCATE COMP "o_PMU_OC_2[18]" SITE "C18" ;
LOCATE COMP "o_PMU_OC_2[19]" SITE "D18" ;
LOCATE COMP "o_PMU_OC_2[20]" SITE "G13" ;
LOCATE COMP "o_PMU_OC_2[21]" SITE "F15" ;
LOCATE COMP "o_PMU_OC_2[22]" SITE "F13" ;
LOCATE COMP "o_PMU_OC_2[23]" SITE "G12" ;
LOCATE COMP "o_PMU_OC_3[0]" SITE "M3" ;
LOCATE COMP "o_PMU_OC_3[1]" SITE "R1" ;
LOCATE COMP "o_PMU_OC_3[2]" SITE "N2" ;
LOCATE COMP "o_PMU_OC_3[3]" SITE "N1" ;
LOCATE COMP "o_PMU_OC_3[4]" SITE "F19" ;
LOCATE COMP "o_PMU_OC_3[5]" SITE "E19" ;
LOCATE COMP "o_PMU_OC_3[7]" SITE "B20" ;
LOCATE COMP "o_PMU_OC_3[6]" SITE "C20" ;
LOCATE COMP "o_PMU_OC_3[16]" SITE "E8" ;
LOCATE COMP "o_PMU_OC_3[17]" SITE "E9" ;
LOCATE COMP "o_PMU_OC_3[18]" SITE "E10" ;
LOCATE COMP "o_PMU_OC_3[19]" SITE "D11" ;
LOCATE COMP "o_PMU_OC_3[20]" SITE "E7" ;
LOCATE COMP "o_PMU_OC_3[21]" SITE "D8" ;
LOCATE COMP "o_PMU_OC_3[22]" SITE "B8" ;
LOCATE COMP "o_PMU_OC_4[0]" SITE "A13" ;
LOCATE COMP "o_PMU_OC_4[1]" SITE "B13" ;
LOCATE COMP "o_PMU_OC_4[2]" SITE "B14" ;
LOCATE COMP "o_PMU_OC_4[3]" SITE "B15" ;
LOCATE COMP "o_PMU_OC_4[4]" SITE "B19" ;
LOCATE COMP "o_PMU_OC_4[5]" SITE "D12" ;
LOCATE COMP "o_PMU_OC_4[6]" SITE "E14" ;
LOCATE COMP "o_PMU_OC_4[7]" SITE "E15" ;
LOCATE COMP "o_PMU_OC_4[16]" SITE "C15" ;
LOCATE COMP "o_PMU_OC_4[17]" SITE "A16" ;
LOCATE COMP "o_PMU_OC_4[18]" SITE "B16" ;
LOCATE COMP "o_PMU_OC_4[19]" SITE "C16" ;
LOCATE COMP "o_PMU_OC_4[20]" SITE "E12" ;
LOCATE COMP "o_PMU_OC_4[21]" SITE "A21" ;
LOCATE COMP "o_PMU_OC_4[22]" SITE "B22" ;
LOCATE COMP "o_PMU_OC_4[23]" SITE "C21" ;
IOBUF PORT "o_PMU_OC_1[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ;
IOBUF PORT "o_PMU_OC_1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_2[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_4[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_1[0]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_PMU_OC_1[16]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_PMU_OC_2[0]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_PMU_OC_2[16]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_PMU_OC_3[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_PMU_OC_3[16]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_PMU_OC_4[0]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_PMU_OC_4[16]" IO_TYPE=LVCMOS33 ;
LOCATE COMP "o_RC_RLSel[1]" SITE "M4" ;
LOCATE COMP "o_RC_RLSel[2]" SITE "B10" ;
LOCATE COMP "o_RC_RLSel[3]" SITE "P3" ;
LOCATE COMP "o_RC_RLSel[4]" SITE "F5" ;
LOCATE COMP "o_RC_RLSel[5]" SITE "G10" ;
LOCATE COMP "o_RC_RLSel[6]" SITE "F6" ;
LOCATE COMP "o_RC_RLSel[7]" SITE "C8" ;
LOCATE COMP "o_RC_RLSel[8]" SITE "B7" ;
LOCATE COMP "o_RC_RLSel[9]" SITE "F8" ;
LOCATE COMP "o_RC_RLSel[10]" SITE "C5" ;
LOCATE COMP "o_RC_RLSel[11]" SITE "A3" ;
LOCATE COMP "o_RC_RLSel[12]" SITE "B11" ;
LOCATE COMP "o_RC_RLSel[13]" SITE "A5" ;
LOCATE COMP "o_RC_RLSel[14]" SITE "B4" ;
LOCATE COMP "o_RC_RLSel[15]" SITE "F11" ;
LOCATE COMP "o_RC_RLSel[16]" SITE "D9" ;
LOCATE COMP "o_RC_RLSel[17]" SITE "N5" ;
IOBUF PORT "o_RC_RLSel[0]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[1]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[2]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[3]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[4]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[5]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[6]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[7]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[8]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[9]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[10]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[11]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[12]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[13]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[14]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[15]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[16]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[17]" IO_TYPE=LVCMOS33 ;
LOCATE COMP "o_RC_LOF[0]" SITE "F3" ;
LOCATE COMP "o_RC_LOF[1]" SITE "H4" ;
LOCATE COMP "o_RC_LOS[0]" SITE "G4" ;
LOCATE COMP "o_RC_LOS[1]" SITE "L6" ;
LOCATE COMP "o_RC_RLSel[0]" SITE "M6" ;
IOBUF PORT "o_RC_LOF[0]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_LOF[1]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_LOS[0]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_LOS[1]" IO_TYPE=LVCMOS33 ;
LOCATE COMP "o_RC_ISel" SITE "P6" ;
LOCATE COMP "o_RC_VSel" SITE "L7" ;
IOBUF PORT "o_RC_VSel" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_ISel" IO_TYPE=LVCMOS33 ;
LOCATE COMP "o_DMM_EN[16]" SITE "W11" ;
IOBUF PORT "o_DMM_EN[16]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DMM_EN[17]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DMM_EN[18]" IO_TYPE=LVCMOS33 ;
LOCATE COMP "o_DMM_EN[17]" SITE "U10" ;
LOCATE COMP "o_DMM_EN[18]" SITE "T10" ;
LOCATE COMP "o_RC_T27" SITE "U13" ;
IOBUF PORT "o_RC_T27" IO_TYPE=LVCMOS33 ;
LOCATE COMP "o_RC_T28" SITE "U12" ;
LOCATE COMP "o_RC_T29" SITE "T12" ;
LOCATE COMP "o_RC_T30" SITE "T11" ;
LOCATE COMP "o_RC_T31" SITE "U11" ;
LOCATE COMP "o_RC_T32" SITE "V11" ;
IOBUF PORT "o_RC_T28" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_T29" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_T30" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_T31" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_T32" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_con_done" IO_TYPE=LVCMOS33 ;
CPLD1/NewExtIns_CPLD1.sort
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/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/RelayConTop.v
/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/BUS_Con.v
/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/Reg_file.v
/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/CPLD_Freq_Con.v
CPLD1/Reg_file.v
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module Reg_file (
input i_sys_clk,
input i_rst_n,
// Bus Interface
input i_wr_req,
input i_wr,
input [6:0] i_addr,
input [23:0] i_wdata,
output [23:0] o_rdata,
output o_rvalid,
output o_busy,
output o_err,
// Controller Interface
input i_con_done, // 1=IDLE/DONE, 0=BUSY
output o_exec,
// Direct Register Outputs
//Freq Regs
output [23:0] o_freq1,
output [23:0] o_freq2,
output [23:0] o_freq3,
output [23:0] o_freq4,
//DC Regs
output [23:0] o_DC1,
output [23:0] o_DC2,
output [23:0] o_DC3,
output [23:0] o_DC4
);
// --- Parameters ---
localparam REG_COUNT = 16;
localparam [23:0]
IDENT = 24'h200000 | 12'b0001_0001_0000, //CPLD1==1,version=1.1.0
STATE_INIT = 24'h800000;
// State Machine Definition
localparam IDLE = 4'd0;
localparam BUSY = 4'd1;
localparam EXEC_ACK = 4'd2; // Wait for controller to go BUSY (Done=0)
localparam EXEC_WAIT = 4'd3; // Wait for controller to go DONE (Done=1)
// --- Internal Signals ---
reg [3:0] state;
reg [23:0] regtable [0:REG_COUNT - 1];
reg [23:0] rdata_reg;
reg busy_flag;
reg err_flag;
reg rvalid_flag;
integer i;
// Mapping Control Bits
wire exec_bit = regtable[1][0];
always @(posedge i_sys_clk or negedge i_rst_n) begin
if (!i_rst_n) begin
for (i = 0; i < REG_COUNT; i = i + 1) begin
regtable[i] <= 24'h0;
end
regtable[0] <= IDENT;
regtable[1] <= STATE_INIT;
rvalid_flag <= 1'b0;
busy_flag <= 1'b0;
err_flag <= 1'b0;
state <= IDLE;
end
else begin
case (state)
IDLE: begin
rvalid_flag <= 1'b0;
err_flag <= 1'b0;
// Priority Check: Did we crash/reset while EXEC bit was still 1?
if (exec_bit == 1'b1) begin
state <= EXEC_ACK;
busy_flag <= 1'b1;
end
else if (i_wr_req == 1'b1) begin
busy_flag <= 1'b1;
state <= BUSY;
// Addr Sanity Check
if ((i_wr && (i_addr == 'd0 || i_addr >= REG_COUNT)) ||
(!i_wr && (i_addr >= REG_COUNT)))
begin
err_flag <= 1'b1;
end
end
else begin
busy_flag <= 1'b0;
end
end
BUSY: begin
if (err_flag) begin
state <= IDLE;
end
else begin
if (i_wr == 1'b1) begin // --- WRITE ---
if (exec_bit == 1'b1) begin
// Cannot write if Controller is already running
err_flag <= 1'b1;
state <= IDLE;
end
else begin
regtable[i_addr] <= i_wdata;
// Check if this write is a "Start Command"
if (i_addr == 7'd1 && i_wdata[0] == 1'b1) begin
// Go to Handshake Start
state <= EXEC_ACK;
end else begin
state <= IDLE;
end
end
end
else begin // --- READ ---
rdata_reg <= regtable[i_addr];
rvalid_flag <= 1'b1;
state <= IDLE;
end
end
end
// --- EXEC PHASE 1: ACK ---
// Wait for Controller to register the command and pull 'done' LOW (Busy)
EXEC_ACK: begin
busy_flag <= 1'b1;
if (i_con_done == 1'b0) begin
state <= EXEC_WAIT;
end
// Optional: Timeout counter here to prevent hanging if Controller is dead
end
// --- EXEC PHASE 2: WAIT ---
// Now wait for Controller to finish and pull 'done' HIGH (Idle/Ready)
EXEC_WAIT: begin
busy_flag <= 1'b1;
if (i_con_done == 1'b1) begin
// 1. Clear the Exec bit (Auto-Clear)
// 2. Set the Ready bit (Bit 23) if you wish
regtable[1] <= {1'b1, regtable[1][22:1], 1'b0};
busy_flag <= 1'b0;
state <= IDLE;
end
end
default: state <= IDLE;
endcase
end
end
assign o_rvalid = rvalid_flag;
assign o_rdata = rdata_reg;
assign o_busy = busy_flag;
assign o_err = err_flag;
// Output the control bit to the controller
// This stays HIGH during both EXEC_ACK and EXEC_WAIT
assign o_exec = exec_bit;
assign o_freq1 = regtable[2];
assign o_freq2 = regtable[3];
assign o_freq3 = regtable[4];
assign o_freq4 = regtable[5];
assign o_DC1 = regtable[6];
assign o_DC2 = regtable[7];
assign o_DC3 = regtable[8];
assign o_DC4 = regtable[9];
endmodule
CPLD1/RelayConTop.sort
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/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/RelayConTop.v
/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/BUS_Con.v
/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/Reg_file.v
/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/CPLD_Freq_Con.v
CPLD1/RelayConTop.sym
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Binary file not shown.
CPLD1/RelayConTop.tfi
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// TOOL: vlog2tf
// DATE: Fri May 15 17:23:34 2026
// TITLE: Lattice Semiconductor Corporation
// MODULE: RelayConTop
// DESIGN: RelayConTop
// FILENAME: RelayConTop.tfi
// PROJECT: NewExtIns_CPLD1
// VERSION: 2.0
// NOTE: DO NOT EDIT THIS FILE
//
// This file is generated by the Verilog Test Fixture Declarations process and
// contains an I/O and instance declarations of the Verilog source file
// you selected from the Sources in Project list.
// Notes:
// 1) This include file (.tfi) should be referenced by your text fixture using
// the `include compile directive using the syntax: `include "<file_name>.tfi"
// 2) If your design I/O changes, rerun the process to obtain new I/O and
// instance declarations.
// 3) Verilog simulations will produce errors if there are Lattice FPGA library
// elements in your design that require the instantiation of GSR, PUR, and TSALL
// and they are not present in the test fixture. For more information see the
// How To section of online help.
// Inputs
reg i_sys_clk;
reg i_rst_n;
reg i_sclk;
reg i_mosi;
reg i_cs;
reg i_rready;
reg i_wvalid;
// Outputs
wire o_miso;
wire o_rvalid;
wire o_wready;
wire o_err;
wire o_con_done;
wire [18:0] o_DMM_EN;
wire o_IO_RC1;
wire o_RC_T27;
wire o_RC_T28;
wire o_RC_T29;
wire o_RC_T30;
wire o_RC_T31;
wire [31:0] o_OC_1;
wire [31:0] o_OC_2;
wire [31:0] o_OC_3;
wire [31:0] o_OC_4;
// Bidirs
// Instantiate the UUT
RelayConTop UUT (
.i_sys_clk(i_sys_clk),
.i_rst_n(i_rst_n),
.i_sclk(i_sclk),
.i_mosi(i_mosi),
.i_cs(i_cs),
.o_miso(o_miso),
.o_rvalid(o_rvalid),
.i_rready(i_rready),
.i_wvalid(i_wvalid),
.o_wready(o_wready),
.o_err(o_err),
.o_con_done(o_con_done),
.o_DMM_EN(o_DMM_EN),
.o_IO_RC1(o_IO_RC1),
.o_RC_T27(o_RC_T27),
.o_RC_T28(o_RC_T28),
.o_RC_T29(o_RC_T29),
.o_RC_T30(o_RC_T30),
.o_RC_T31(o_RC_T31),
.o_OC_1(o_OC_1),
.o_OC_2(o_OC_2),
.o_OC_3(o_OC_3),
.o_OC_4(o_OC_4)
);
// Initialize Inputs
`ifdef auto_init
initial begin
i_sys_clk = 0;
i_rst_n = 0;
i_sclk = 0;
i_mosi = 0;
i_cs = 0;
i_rready = 0;
i_wvalid = 0;
end
`endif
CPLD1/RelayConTop.v
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module RelayConTop (
input i_sys_clk,
input i_rst_n,
input i_sclk,
input i_mosi,
input i_cs,
output o_miso,
//output o_rvalid,
input i_rready,
input i_wvalid,
output o_wready,
output o_err,
output o_con_done,
output [18:0]o_DMM_EN,
output o_IO_RC1,
output o_RC_T27,
output o_RC_T28,
output o_RC_T29,
output o_RC_T30,
output o_RC_T31,
output o_RC_T32,
output [17:0]o_RC_RLSel,
output o_RC_VSel,
output o_RC_ISel,
output [1:0]o_RC_LOF, //Strange DMM_N port relay
output [1:0]o_RC_LOS,
output [31:0]o_PMU_OC_1,
output [31:0]o_PMU_OC_2,
output [31:0]o_PMU_OC_3,
output [31:0]o_PMU_OC_4
);
wire [3:0]OC_x01;
wire [3:0]OC_x17;
wire [5:0]RC_Tx;
wire [18:0]DMM_EN;
wire IO_RC1;
wire [23:0]r_data ;
wire [23:0]w_data ;
wire [6:0]reg_addr ;
wire cmd_valid;
wire reg_busy;
wire wr_flag; //1=write,0=read
wire bus_err_flag;
wire reg_err_flag;
wire cpld_err_flag;
wire con_exec;
wire [23:0]freq1_relay ;
wire [23:0]freq2_relay ;
wire [23:0]freq3_relay ;
wire [23:0]freq4_relay ;
//DC Control Reg output
wire [23:0]DC_Con1 ;
wire [23:0]DC_Con2 ;
wire [23:0]DC_Con3 ;
wire [23:0]DC_Con4 ;
//PMU OC Control
wire [31:0]PMU_OC_1 ;
wire [31:0]PMU_OC_2 ;
wire [31:0]PMU_OC_3 ;
wire [31:0]PMU_OC_4 ;
//RL Control
wire [17:0]RC_RLSel ;
//DMM V Select
wire RC_VSel;
//DMM I Select
wire RC_ISel;
wire con_rvalid;
wire con_done;
BUS_Con BUS_Con_1(
.i_sys_clk(i_sys_clk),
.i_rst_n(i_rst_n),
.i_sclk(i_sclk),
.i_mosi(i_mosi),
.i_cs(i_cs),
.i_rvalid(con_rvalid),
.i_wvalid(i_wvalid),
.i_reg_busy(reg_busy),
.i_rdata(r_data),
.o_cmd_valid(cmd_valid),
.o_wr(wr_flag),
.o_miso(o_miso),
.o_rvalid(o_rvalid),
.o_wready(o_wready),
.o_data(w_data),
.o_addr(reg_addr),
.o_err(bus_err_flag)
);
Reg_file CPLD_Reg_1(
.i_sys_clk(i_sys_clk),
.i_rst_n(i_rst_n),
.i_wr_req(cmd_valid),
.i_wr(wr_flag),
.i_addr(reg_addr),
.i_wdata(w_data),
.i_con_done(con_done), //Controller Exec Done
.o_freq1(freq1_relay), //Freq_Slot1
.o_freq2(freq2_relay), //Freq_Slot2
.o_freq3(freq3_relay), //Freq_Slot3
.o_freq4(freq4_relay), //Freq_Slot4
.o_DC1(DC_Con1),
.o_DC2(DC_Con2),
.o_DC3(DC_Con3),
.o_DC4(DC_Con4),
.o_rvalid(con_rvalid),
.o_rdata(r_data),
.o_exec(con_exec), //Exec cmd
.o_busy(reg_busy),
.o_err(reg_err_flag)
);
CPLD_Con CPLD_Con_1(
.i_sys_clk(i_sys_clk),
.i_rst_n(i_rst_n),
.i_con_exec(con_exec),
.i_freq_relay1(freq1_relay),
.i_freq_relay2(freq2_relay),
.i_freq_relay3(freq3_relay),
.i_freq_relay4(freq4_relay),
.i_DC_Con1(DC_Con1),
.i_DC_Con2(DC_Con2),
.i_DC_Con3(DC_Con3),
.i_DC_Con4(DC_Con4),
.o_con_done(con_done),
.o_OC_x01(OC_x01),
.o_OC_x17(OC_x17),
.o_RC_Tx(RC_Tx),
.o_DMM_EN(DMM_EN),
.o_PMU_OC_1(PMU_OC_1),
.o_PMU_OC_2(PMU_OC_2),
.o_PMU_OC_3(PMU_OC_3),
.o_PMU_OC_4(PMU_OC_4),
.o_RC_VSel(RC_VSel),
.o_RC_ISel(RC_ISel),
.o_RC_RLSel(RC_RLSel),
.o_IO_RC1(IO_RC1),
.o_err(cpld_err_flag)
);
assign o_con_done = con_done;
//assign o_OC_x01 = OC_x01;
assign o_PMU_OC_1[0] = OC_x01[0];
assign o_PMU_OC_2[0] = OC_x01[1];
assign o_PMU_OC_3[0] = OC_x01[2];
assign o_PMU_OC_4[0] = OC_x01[3];
//assign o_OC_x17 = OC_x17;
assign o_PMU_OC_1[16] = OC_x17[0];
assign o_PMU_OC_2[16] = OC_x17[1];
assign o_PMU_OC_3[16] = OC_x17[2];
assign o_PMU_OC_4[16] = OC_x17[3];
assign o_PMU_OC_1[15:1] = PMU_OC_1[15:1];
assign o_PMU_OC_1[31:17] = PMU_OC_1[31:17];
assign o_PMU_OC_2[15:1] = PMU_OC_2[15:1];
assign o_PMU_OC_2[31:17] = PMU_OC_2[31:17];
assign o_PMU_OC_3[15:1] = PMU_OC_3[15:1];
assign o_PMU_OC_3[31:17] = PMU_OC_3[31:17];
assign o_PMU_OC_4[15:1] = PMU_OC_4[15:1];
assign o_PMU_OC_4[31:17] = PMU_OC_4[31:17];
assign o_DMM_EN = DMM_EN;
assign o_IO_RC1 = IO_RC1;
assign o_RC_T27 = RC_Tx[5];
assign o_RC_T28 = RC_Tx[4];
assign o_RC_T29 = RC_Tx[3];
assign o_RC_T30 = RC_Tx[2];
assign o_RC_T31 = RC_Tx[1];
assign o_RC_T32 = RC_Tx[0];
assign o_RC_RLSel = RC_RLSel;
assign o_RC_VSel = RC_VSel;
assign o_RC_ISel = RC_ISel;
assign o_RC_LOF = (RC_VSel == 1'b1)?2'b01:2'b10; //if Measure V then close RC_LOF[0]
assign o_RC_LOS = (RC_VSel == 1'b1)?2'b01:2'b10;
assign o_err = bus_err_flag || reg_err_flag ||cpld_err_flag;
endmodule
CPLD1/RelayConTop_tf.v
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// TOOL: vlog2tf
// DATE: Fri May 15 17:23:27 2026
// TITLE: Lattice Semiconductor Corporation
// MODULE: RelayConTop
// DESIGN: RelayConTop
// FILENAME: RelayConTop_tf.v
// PROJECT: NewExtIns_CPLD1
// VERSION: 2.0
// This file is auto generated by Diamond
`timescale 1 ns / 1 ps
// Define Module for Test Fixture
module RelayConTop_tf();
// Inputs
reg i_sys_clk;
reg i_rst_n;
reg i_sclk;
reg i_mosi;
reg i_cs;
reg i_rready;
reg i_wvalid;
// Outputs
wire o_miso;
wire o_rvalid;
wire o_wready;
wire o_err;
wire o_con_done;
wire [18:0] o_DMM_EN;
wire o_IO_RC1;
wire o_RC_T27;
wire o_RC_T28;
wire o_RC_T29;
wire o_RC_T30;
wire o_RC_T31;
wire [31:0] o_OC_1;
wire [31:0] o_OC_2;
wire [31:0] o_OC_3;
wire [31:0] o_OC_4;
// Bidirs
// Instantiate the UUT
// Please check and add your parameters manually
RelayConTop UUT (
.i_sys_clk(i_sys_clk),
.i_rst_n(i_rst_n),
.i_sclk(i_sclk),
.i_mosi(i_mosi),
.i_cs(i_cs),
.o_miso(o_miso),
.o_rvalid(o_rvalid),
.i_rready(i_rready),
.i_wvalid(i_wvalid),
.o_wready(o_wready),
.o_err(o_err),
.o_con_done(o_con_done),
.o_DMM_EN(o_DMM_EN),
.o_IO_RC1(o_IO_RC1),
.o_RC_T27(o_RC_T27),
.o_RC_T28(o_RC_T28),
.o_RC_T29(o_RC_T29),
.o_RC_T30(o_RC_T30),
.o_RC_T31(o_RC_T31),
.o_OC_1(o_OC_1),
.o_OC_2(o_OC_2),
.o_OC_3(o_OC_3),
.o_OC_4(o_OC_4)
);
// Initialize Inputs
// You can add your stimulus here
initial begin
i_sys_clk = 0;
i_rst_n = 0;
i_sclk = 0;
i_mosi = 0;
i_cs = 0;
i_rready = 0;
i_wvalid = 0;
end
endmodule // RelayConTop_tf
CPLD1/debug.rvl
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<Project ModBy="Inserter" SigType="0" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/debug.rvl" Date="2026-05-26">
<IP Version="1_6_042617"/>
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD1"/>
<Core InsertDataset="0" Insert="1" Reveal_sig="695532518" Name="RelayConTop_LA0" ID="0">
<Setting>
<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
<Capture Mode="0" MinSamplesPerTrig="8"/>
<Event CntEnable="0" MaxEventCnt="8"/>
<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_RelayConTop_LA0_net"/>
<DistRAM Disable="0"/>
</Setting>
<Dataset Name="Base">
<Trace>
<Sig Type="SIG" Name="BUS_Con_1/i_cs"/>
<Sig Type="SIG" Name="BUS_Con_1/i_mosi"/>
<Sig Type="SIG" Name="BUS_Con_1/i_sclk"/>
<Bus Name="o_DMM_EN">
<Sig Type="SIG" Name="o_DMM_EN:0"/>
<Sig Type="SIG" Name="o_DMM_EN:1"/>
<Sig Type="SIG" Name="o_DMM_EN:2"/>
<Sig Type="SIG" Name="o_DMM_EN:3"/>
<Sig Type="SIG" Name="o_DMM_EN:4"/>
<Sig Type="SIG" Name="o_DMM_EN:5"/>
<Sig Type="SIG" Name="o_DMM_EN:6"/>
<Sig Type="SIG" Name="o_DMM_EN:7"/>
<Sig Type="SIG" Name="o_DMM_EN:8"/>
<Sig Type="SIG" Name="o_DMM_EN:9"/>
<Sig Type="SIG" Name="o_DMM_EN:10"/>
<Sig Type="SIG" Name="o_DMM_EN:11"/>
<Sig Type="SIG" Name="o_DMM_EN:12"/>
<Sig Type="SIG" Name="o_DMM_EN:13"/>
<Sig Type="SIG" Name="o_DMM_EN:14"/>
<Sig Type="SIG" Name="o_DMM_EN:15"/>
</Bus>
<Sig Type="SIG" Name="o_IO_RC1"/>
<Sig Type="SIG" Name="BUS_Con_1/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_1/err_flag"/>
<Sig Type="SIG" Name="CPLD_Reg_1/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_con_exec"/>
<Bus Name="CPLD_Con_1/i_DC_Con1">
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:0"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:1"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:2"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:3"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:4"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:5"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:6"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:7"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:8"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:9"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:10"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:11"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:12"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:13"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:14"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:15"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:16"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:17"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:18"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:19"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:20"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:21"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:22"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:23"/>
</Bus>
<Bus Name="CPLD_Con_1/i_DC_Con2">
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:0"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:1"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:2"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:3"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:4"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:5"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:6"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:7"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:8"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:9"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:10"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:11"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:12"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:13"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:14"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:15"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:16"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:17"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:18"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:19"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:20"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:21"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:22"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:23"/>
</Bus>
<Bus Name="CPLD_Con_1/i_DC_Con3">
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:0"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:1"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:2"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:3"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:4"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:5"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:6"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:7"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:8"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:9"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:10"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:11"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:12"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:13"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:14"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:15"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:16"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:17"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:18"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:19"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:20"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:21"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:22"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:23"/>
</Bus>
<Bus Name="CPLD_Con_1/i_DC_Con4">
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:0"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:1"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:2"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:3"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:4"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:5"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:6"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:7"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:8"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:9"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:10"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:11"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:12"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:13"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:14"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:15"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:16"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:17"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:18"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:19"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:20"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:21"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:22"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:23"/>
</Bus>
</Trace>
<Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="i_cs,"/>
<TU Serialbits="0" Type="0" ID="2" Sig="i_sclk,"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
</Trigger>
</Dataset>
</Core>
</Project>
CPLD1/tb_RelayConTop.sv
+914
View File
@@ -0,0 +1,914 @@
//------------------------------------------------------------------------------
//
// Testbench: CPLD1 - RelayConTop
// Project: NewCalBoard DIG
// Tool: Lattice Diamond Verilog-2001 simulator
// Purpose: Verify SPI interface, register file, and relay control logic
// for CPLD1 (main relay controller + PMU output + DMM enable).
//
// Architecture (3 sub-modules):
// RelayConTop
// - BUS_Con - SPI Mode 0 master interface (32-bit transactions)
// - Reg_file - 16-register file + execution FSM
// - CPLD_Con - Relay control logic (freq + DC/PMU decoding)
//
// SPI Protocol:
// Frame: [WR:1][Addr:7][Data:24] (MSB first, CPOL=0 CPHA=0)
// Read response: [8'h00][24-bit rdata]
//
// DPS path is NOT implemented (stubbed out) - all DC tests use PMU mode.
//
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
`define SYS_CLK_PERIOD 20 // 50 MHz system clock
`define SPI_CLK_PERIOD 400 // 1 MHz SPI clock (200x slower than sys clk)
module tb_RelayConTop;
////==========================================================================
// Signal declarations - mirrors RelayConTop pinout exactly
////==========================================================================
// Clock & reset
reg i_sys_clk;
reg i_rst_n;
// SPI interface (Zynq PS drives these)
reg i_sclk;
reg i_mosi;
reg i_cs;
// Flow control (from Zynq PS / SPI_Con IP)
reg i_rready;
reg i_wvalid;
// Status outputs (monitored by testbench)
wire o_miso;
wire o_rvalid;
wire o_wready;
wire o_err;
wire o_con_done;
// Relay control outputs
wire o_IO_RC1;
wire o_RC_VSel;
wire o_RC_ISel;
wire [17:0] o_RC_RLSel;
wire [1:0] o_RC_LOF;
wire [1:0] o_RC_LOS;
wire o_RC_T27;
wire o_RC_T28;
wire o_RC_T29;
wire o_RC_T30;
wire o_RC_T31;
wire o_RC_T32;
// PMU output channels (4 x 32-bit)
wire [31:0] o_PMU_OC_1;
wire [31:0] o_PMU_OC_2;
wire [31:0] o_PMU_OC_3;
wire [31:0] o_PMU_OC_4;
// DMM enable bus (19 bits)
wire [18:0] o_DMM_EN;
////==========================================================================
// DUT instantiation - connect every pin
////==========================================================================
RelayConTop DUT (
.i_sys_clk (i_sys_clk),
.i_rst_n (i_rst_n),
.i_sclk (i_sclk),
.i_mosi (i_mosi),
.i_cs (i_cs),
.o_miso (o_miso),
.i_rready (i_rready),
.i_wvalid (i_wvalid),
.o_wready (o_wready),
.o_err (o_err),
.o_con_done (o_con_done),
.o_DMM_EN (o_DMM_EN),
.o_IO_RC1 (o_IO_RC1),
.o_RC_T27 (o_RC_T27),
.o_RC_T28 (o_RC_T28),
.o_RC_T29 (o_RC_T29),
.o_RC_T30 (o_RC_T30),
.o_RC_T31 (o_RC_T31),
.o_RC_T32 (o_RC_T32),
.o_RC_RLSel (o_RC_RLSel),
.o_RC_VSel (o_RC_VSel),
.o_RC_ISel (o_RC_ISel),
.o_RC_LOF (o_RC_LOF),
.o_RC_LOS (o_RC_LOS),
.o_PMU_OC_1 (o_PMU_OC_1),
.o_PMU_OC_2 (o_PMU_OC_2),
.o_PMU_OC_3 (o_PMU_OC_3),
.o_PMU_OC_4 (o_PMU_OC_4)
);
////==========================================================================
// Clock generation
////==========================================================================
// System clock: 50 MHz (period = 20 ns)
initial begin
i_sys_clk = 0;
forever #(`SYS_CLK_PERIOD / 2) i_sys_clk = ~i_sys_clk;
end
// SPI clock: 1 MHz (period = 400 ns)
initial begin
i_sclk = 0;
forever #(`SPI_CLK_PERIOD / 2) i_sclk = ~i_sclk;
end
////==========================================================================
// Test statistics
////==========================================================================
integer test_pass;
integer test_fail;
integer test_num;
initial begin
test_pass = 0;
test_fail = 0;
test_num = 0;
end
// Helper: log a pass (Verilog-2001 compatible)
task tb_pass;
input [132:1] msg;
begin
test_pass = test_pass + 1;
$display("[PASS] Test %0d: %s", test_num, msg);
end
endtask
// Helper: log a fail with optional detail
task tb_fail;
input [132:1] msg;
input [132:1] detail;
begin
test_fail = test_fail + 1;
$display("[FAIL] Test %0d: %s >> %s", test_num, msg, detail);
end
endtask
// Helper: assert a condition (Verilog-2001 compatible)
task tb_assert;
input condition;
input [132:1] msg;
input [132:1] detail;
begin
test_num = test_num + 1;
if (condition) begin
tb_pass(msg);
end else begin
tb_fail(msg, detail);
end
end
endtask
////==========================================================================
// SPI helper tasks
//
// SPI Mode 0 timing:
// - CPOL = 0: SCLK idle LOW
// - CPHA = 0: data sampled on RISING edge, shifted on FALLING edge
// - MSB first, 32 bits per transaction
//
// Frame layout: [bit31: WR] [bit30:24: Addr(7b)] [bit23:0: Data(24b)]
// Read response: [8'h00][24-bit rdata] shifted out on falling SCLK edges
//
// MISO is tri-stated (high-Z) when CS is HIGH.
////==========================================================================
// --- spi_send: Drive a 32-bit word out through MOSI ---
task spi_send;
input [31:0] data;
integer i;
begin
@(negedge i_sclk);
i_cs = 1'b0;
@(negedge i_sclk);
for (i = 31; i >= 0; i = i - 1) begin
i_mosi = data[i];
@(posedge i_sclk);
end
@(negedge i_sclk);
i_cs = 1'b1;
i_mosi = 1'b0;
@(negedge i_sclk);
end
endtask
// --- spi_read: Send command, capture 32-bit response on MISO ---
task spi_read;
input [31:0] cmd;
output [31:0] rdata;
integer i;
begin
@(negedge i_sclk);
i_cs = 1'b0;
@(negedge i_sclk);
// CPLD uses sys_clk domain for internal logic. Add #1ns delay
// after falling edge to let CPLD update o_miso before we sample.
rdata = 32'b0;
for (i = 31; i >= 0; i = i - 1) begin
i_mosi = cmd[i];
@(posedge i_sclk);
@(negedge i_sclk);
#1;
rdata[i] = o_miso;
end
@(negedge i_sclk);
i_cs = 1'b1;
i_mosi = 1'b0;
@(negedge i_sclk);
end
endtask
// --- spi_write: Send a write command (no response capture needed) ---
task spi_write;
input [31:0] data;
begin
spi_send(data);
end
endtask
// --- wait_con_done: Poll con_done for LOW->HIGH cycle ---
task wait_con_done;
input [15:0] max_cycles;
output [1:0] result;
integer i;
begin
result = 2'b0;
// Phase 1: Wait for con_done to go LOW (exec started)
for (i = 0; i < max_cycles; i = i + 1) begin
#(`SYS_CLK_PERIOD);
if (!o_con_done) break;
end
// Phase 2: Wait for con_done to go HIGH (exec finished)
for (i = 0; i < max_cycles; i = i + 1) begin
#(`SYS_CLK_PERIOD);
if (o_con_done) begin
result = 2'b1;
return;
end
end
end
endtask
// --- wait_wready: Poll o_wready until HIGH ---
task wait_wready;
input [15:0] max_cycles;
output [1:0] result;
integer i;
begin
result = 2'b0;
for (i = 0; i < max_cycles; i = i + 1) begin
#(`SYS_CLK_PERIOD);
if (o_wready) begin
result = 2'b1;
return;
end
end
end
endtask
////==========================================================================
// Convenience: build SPI frame fields
////==========================================================================
function [31:0] mk_write;
input [6:0] addr;
input [23:0] data;
begin
mk_write = {1'b1, addr, data};
end
endfunction
function [31:0] mk_read;
input [6:0] addr;
begin
mk_read = {1'b0, addr, 24'b0};
end
endfunction
////==========================================================================
// Main test sequence
////==========================================================================
initial begin
// Initialize all signals to safe defaults
i_rst_n = 1'b0;
i_cs = 1'b1;
i_mosi = 1'b0;
i_rready = 1'b0;
i_wvalid = 1'b0;
// Hold reset for 4 system clock cycles (80 ns)
#(`SYS_CLK_PERIOD * 4);
i_rst_n = 1'b1;
// Allow CPLD internal state machines to settle
#(`SYS_CLK_PERIOD * 10);
$display("");
$display("=============================================================");
$display(" CPLD1 RelayConTop - Comprehensive Testbench");
$display(" System clock: %d MHz | SPI clock: %d MHz",
1000 / `SYS_CLK_PERIOD, 1000 / `SPI_CLK_PERIOD);
$display("=============================================================");
$display("");
test_reset_behavior();
test_register_rw();
test_exec_protocol();
test_freq_slots();
test_dc_slots_pmu();
test_rc_tx_output();
test_error_conditions();
test_edge_cases();
print_summary();
#(`SYS_CLK_PERIOD * 20);
$finish;
end
////==========================================================================
// Test Group 1: Reset behavior & IDENT register (ADDR 0)
////==========================================================================
task test_reset_behavior;
reg [31:0] r_ident;
begin
$display("-------------------------------------------------------------");
$display(" Group 1: Reset behavior & IDENT register");
$display("-------------------------------------------------------------");
tb_assert(o_con_done === 1'b1,
"o_con_done is HIGH after reset (controller idle)", "");
tb_assert(o_err === 1'b0,
"o_err is LOW after reset", "");
tb_assert(o_wready === 1'b1,
"o_wready is HIGH after reset (SPI ready)", "");
// IDENT register: CPLD1=bit21, version=1.1.0 = 24'h200010
spi_read(mk_read(7'd0), r_ident);
r_ident = r_ident[23:0];
tb_assert(r_ident === 24'h200010,
"IDENT register returns 24'h200010 (CPLD1, v1.1.0)", "");
tb_assert(o_DMM_EN === 19'b0,
"o_DMM_EN is all zeros after reset", "");
tb_assert(o_RC_RLSel === 18'b0,
"o_RC_RLSel is all zeros after reset", "");
tb_assert(o_PMU_OC_1 === 32'b0 && o_PMU_OC_2 === 32'b0 &&
o_PMU_OC_3 === 32'b0 && o_PMU_OC_4 === 32'b0,
"All PMU_OC outputs are zero after reset", "");
#(`SPI_CLK_PERIOD * 2);
end
endtask
////==========================================================================
// Test Group 2: Register read/write (ADDR 0-9)
////==========================================================================
task test_register_rw;
reg [31:0] rdata;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Group 2: Register read/write (ADDR 0-9)");
$display("-------------------------------------------------------------");
spi_write(mk_write(7'd2, 24'h000005));
@(negedge i_sclk);
spi_read(mk_read(7'd2), rdata);
tb_assert(rdata === 24'h000005,
"Freq_Slot1 (ADDR 2) write/read back", "");
spi_write(mk_write(7'd3, 24'h003001));
@(negedge i_sclk);
spi_read(mk_read(7'd3), rdata);
tb_assert(rdata === 24'h003001,
"Freq_Slot2 (ADDR 3) write/read back", "");
spi_write(mk_write(7'd4, 24'h001040));
@(negedge i_sclk);
spi_read(mk_read(7'd4), rdata);
tb_assert(rdata === 24'h001040,
"Freq_Slot3 (ADDR 4) write/read back", "");
spi_write(mk_write(7'd5, 24'h000802));
@(negedge i_sclk);
spi_read(mk_read(7'd5), rdata);
tb_assert(rdata === 24'h000802,
"Freq_Slot4 (ADDR 5) write/read back", "");
spi_write(mk_write(7'd6, 24'h002003));
@(negedge i_sclk);
spi_read(mk_read(7'd6), rdata);
tb_assert(rdata === 24'h002003,
"DC_Slot1 (ADDR 6) write/read back (PMU mode)", "");
spi_write(mk_write(7'd7, 24'h004005));
@(negedge i_sclk);
spi_read(mk_read(7'd7), rdata);
tb_assert(rdata === 24'h004005,
"DC_Slot2 (ADDR 7) write/read back", "");
spi_write(mk_write(7'd8, 24'h006007));
@(negedge i_sclk);
spi_read(mk_read(7'd8), rdata);
tb_assert(rdata === 24'h006007,
"DC_Slot3 (ADDR 8) write/read back", "");
spi_write(mk_write(7'd9, 24'h008009));
@(negedge i_sclk);
spi_read(mk_read(7'd9), rdata);
tb_assert(rdata === 24'h008009,
"DC_Slot4 (ADDR 9) write/read back", "");
spi_read(mk_read(7'd1), rdata);
tb_assert(rdata === 24'h800000,
"STATE register (ADDR 1) default (RDY=1)", "");
#(`SPI_CLK_PERIOD * 2);
end
endtask
////==========================================================================
// Test Group 3: Execution protocol
////==========================================================================
task test_exec_protocol;
reg [1:0] done_result;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Group 3: Execution protocol");
$display("-------------------------------------------------------------");
// Configure and trigger execution
spi_write(mk_write(7'd2, 24'h000005));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001)); // EXEC=1
@(negedge i_sclk);
wait_con_done(500, done_result);
tb_assert(done_result === 1'b1,
"con_done goes HIGH after execution completes", "");
tb_assert(o_err === 1'b0,
"No error flag set after successful execution", "");
wait_wready(100, done_result);
tb_assert(done_result === 1'b1,
"o_wready is HIGH after execution (SPI ready)", "");
// Execute with DC_Slot1
spi_write(mk_write(7'd6, 24'h002003));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_result);
tb_assert(done_result === 1'b1,
"DC slot execution completes successfully", "");
tb_assert(o_err === 1'b0,
"No error after DC slot execution", "");
#(`SPI_CLK_PERIOD * 2);
end
endtask
////==========================================================================
// Test Group 4: Frequency slot decoding (all 4 slots)
////==========================================================================
task test_freq_slots;
reg [1:0] done_r;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Group 4: Frequency slot decoding (all 4 slots)");
$display("-------------------------------------------------------------");
// Slot1 Ch5 (range 1-8): OC_x01=1, DMM_EN[0]=1
$display(" Slot1 Ch5 (range 1-8): OC_x01=1, DMM_EN[0]=1");
spi_write(mk_write(7'd2, 24'h000005));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "Slot1 Ch5 exec done", "timeout");
tb_assert(o_RC_T27 === 1'b0, "Slot1: RC_T27 idle", "RC_T27 mismatch");
tb_assert(o_PMU_OC_1[0] === 1'b1, "Slot1 Ch5: PMU_OC_1[0]=1", "PMU_OC_1[0] mismatch");
tb_assert(o_DMM_EN[0] === 1'b1, "Slot1 Ch5: DMM_EN[0]=1", "DMM_EN[0] mismatch");
tb_assert(o_PMU_OC_2[0] === 1'b0, "Slot1 Ch5: PMU_OC_2[0]=0", "PMU_OC_2[0] mismatch");
#(`SPI_CLK_PERIOD);
// Slot1 Ch50 (range 9-72): DMM_EN[1]=1
// = (0<<10) | (50<<1) | 1 = 24'h000065
$display(" Slot1 Ch50 (range 9-72): DMM_EN[1]=1");
spi_write(mk_write(7'd2, 24'h000065));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "Slot1 Ch50 exec done", "timeout");
tb_assert(o_DMM_EN[1] === 1'b1, "Slot1 Ch50: DMM_EN[1]=1", "DMM_EN[1] mismatch");
tb_assert(o_PMU_OC_1[0] === 1'b0, "Slot1 Ch50: PMU_OC_1[0]=0", "PMU_OC_1[0] mismatch");
#(`SPI_CLK_PERIOD);
// Slot1 Ch100 (range 73-136): OC_x17=1, DMM_EN[2]=1
// = (0<<10) | (100<<1) | 1 = 24'h0000C9
$display(" Slot1 Ch100 (range 73-136): OC_x17=1, DMM_EN[2]=1");
spi_write(mk_write(7'd2, 24'h0000C9));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "Slot1 Ch100 exec done", "timeout");
tb_assert(o_PMU_OC_1[16] === 1'b1, "Slot1 Ch100: PMU_OC_1[16]=1", "PMU_OC_1[16] mismatch");
tb_assert(o_DMM_EN[2] === 1'b1, "Slot1 Ch100: DMM_EN[2]=1", "DMM_EN[2] mismatch");
#(`SPI_CLK_PERIOD);
// Slot1 Ch150 (range 137-200): DMM_EN[3]=1
// = (0<<10) | (150<<1) | 1 = 24'h00012D
$display(" Slot1 Ch150 (range 137-200): DMM_EN[3]=1");
spi_write(mk_write(7'd2, 24'h00012D));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "Slot1 Ch150 exec done", "timeout");
tb_assert(o_DMM_EN[3] === 1'b1, "Slot1 Ch150: DMM_EN[3]=1", "DMM_EN[3] mismatch");
#(`SPI_CLK_PERIOD);
// Slot2 Ch5 (range 1-8): OC_x01=2, DMM_EN[4]=1
// = (0<<10) | (5<<1) | 1 = 24'h000006
$display(" Slot2 Ch5 (range 1-8): OC_x01=2, DMM_EN[4]=1");
spi_write(mk_write(7'd3, 24'h000006));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "Slot2 Ch5 exec done", "timeout");
tb_assert(o_PMU_OC_2[0] === 1'b1, "Slot2 Ch5: PMU_OC_2[0]=1", "PMU_OC_2[0] mismatch");
tb_assert(o_DMM_EN[4] === 1'b1, "Slot2 Ch5: DMM_EN[4]=1", "DMM_EN[4] mismatch");
#(`SPI_CLK_PERIOD);
// Slot3 Ch100 (range 73-136): OC_x17=4, DMM_EN[10]=1
// = (0<<10) | (100<<1) | 1 = 24'h0000C9
$display(" Slot3 Ch100 (range 73-136): OC_x17=4, DMM_EN[10]=1");
spi_write(mk_write(7'd4, 24'h0000C9));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "Slot3 Ch100 exec done", "timeout");
tb_assert(o_PMU_OC_3[16] === 1'b1, "Slot3 Ch100: PMU_OC_3[16]=1", "PMU_OC_3[16] mismatch");
tb_assert(o_DMM_EN[10] === 1'b1, "Slot3 Ch100: DMM_EN[10]=1", "DMM_EN[10] mismatch");
#(`SPI_CLK_PERIOD);
// Slot4 Ch50 (range 9-72): DMM_EN[5]=1
// = (0<<10) | (50<<1) | 1 = 24'h000065
$display(" Slot4 Ch50 (range 9-72): DMM_EN[5]=1");
spi_write(mk_write(7'd5, 24'h000065));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "Slot4 Ch50 exec done", "timeout");
tb_assert(o_DMM_EN[5] === 1'b1, "Slot4 Ch50: DMM_EN[5]=1", "DMM_EN[5] mismatch");
#(`SPI_CLK_PERIOD * 2);
end
endtask
////==========================================================================
// Test Group 5: DC slot PMU mode
////==========================================================================
task test_dc_slots_pmu;
reg [1:0] done_r;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Group 5: DC slot PMU mode (DPS is stubbed, not tested)");
$display("-------------------------------------------------------------");
// 5a. DC_Slot1: V mode, Rload=3, Ch=3, PMU
// = (3<<17) | (3<<1) | 1 = 24'h060007
$display(" DC1: V mode, Rload=3, Ch=3, PMU");
spi_write(mk_write(7'd6, 24'h060007));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "DC1 V-mode exec done", "timeout");
tb_assert(o_RC_VSel === 1'b1, "DC1: RC_VSel=1 (V mode)", "RC_VSel mismatch");
tb_assert(o_RC_ISel === 1'b0, "DC1: RC_ISel=0 (V mode)", "RC_ISel mismatch");
tb_assert(o_RC_RLSel === 18'b100, "DC1: RC_RLSel=18'b100 (Rload=3)", "RC_RLSel mismatch");
tb_assert(o_PMU_OC_1[0] === 1'b1, "DC1: PMU_OC_1[0]=1 (Ch=3)", "PMU_OC_1[0] mismatch");
#(`SPI_CLK_PERIOD);
// 5b. DC_Slot1: I mode, Rload=1, Ch=11, PMU
// = (1<<22) | (1<<17) | (11<<1) | 1 = 24'h420017
$display(" DC1: I mode, Rload=1, Ch=11, PMU");
spi_write(mk_write(7'd6, 24'h420017));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "DC1 I-mode exec done", "timeout");
tb_assert(o_RC_VSel === 1'b0, "DC1: RC_VSel=0 (I mode)", "RC_VSel mismatch");
tb_assert(o_RC_ISel === 1'b1, "DC1: RC_ISel=1 (I mode)", "RC_ISel mismatch");
tb_assert(o_RC_RLSel[0] === 1'b1, "DC1: RC_RLSel[0]=1 (Rload=1)", "RC_RLSel mismatch");
tb_assert(o_PMU_OC_1[1] === 1'b1, "DC1: PMU_OC_1[1]=1 (Ch=11)", "PMU_OC_1[1] mismatch");
#(`SPI_CLK_PERIOD);
// 5c. DC_Slot2: V mode, Rload=5, Ch=19, PMU
// = (5<<17) | (19<<1) | 1 = 24'h0A0027
$display(" DC2: V mode, Rload=5, Ch=19, PMU");
spi_write(mk_write(7'd7, 24'h0A0027));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "DC2 V-mode exec done", "timeout");
tb_assert(o_RC_VSel === 1'b1, "DC2: RC_VSel=1 (V mode)", "RC_VSel mismatch");
tb_assert(o_PMU_OC_2[2] === 1'b1, "DC2: PMU_OC_2[2]=1 (Ch=19)", "PMU_OC_2[2] mismatch");
#(`SPI_CLK_PERIOD);
// 5d. DC_Slot3: V mode, Rload=10, Ch=27, PMU
// = (10<<17) | (27<<1) | 1 = 24'h140037
$display(" DC3: V mode, Rload=10, Ch=27, PMU");
spi_write(mk_write(7'd8, 24'h140037));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "DC3 V-mode exec done", "timeout");
tb_assert(o_PMU_OC_3[3] === 1'b1, "DC3: PMU_OC_3[3]=1 (Ch=27)", "PMU_OC_3[3] mismatch");
#(`SPI_CLK_PERIOD);
// 5e. DC_Slot4: V mode, Rload=18, Ch=35, PMU
// = (18<<17) | (35<<1) | 1 = 24'h240047
$display(" DC4: V mode, Rload=18, Ch=35, PMU");
spi_write(mk_write(7'd9, 24'h240047));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "DC4 V-mode exec done", "timeout");
tb_assert(o_RC_RLSel[17] === 1'b1, "DC4: RC_RLSel[17]=1 (Rload=18)", "RC_RLSel mismatch");
tb_assert(o_PMU_OC_4[4] === 1'b1, "DC4: PMU_OC_4[4]=1 (Ch=35)", "PMU_OC_4[4] mismatch");
#(`SPI_CLK_PERIOD);
// 5f. RC_LOF/LOS when RC_VSel=1 (V mode)
tb_assert(o_RC_LOF === 2'b01 && o_RC_LOS === 2'b01,
"RC_LOF/LOS=01 when RC_VSel=1", "");
#(`SPI_CLK_PERIOD * 2);
end
endtask
////==========================================================================
// Test Group 6: RC_Tx relay output (slot 4)
////==========================================================================
task test_rc_tx_output;
reg [1:0] done_r;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Group 6: RC_Tx relay output (slot 4)");
$display("-------------------------------------------------------------");
// 6a. RC_Tx pattern: bits 17:12 = 6'b101010 (42)
// = (42<<12) | (5<<1) | 1 = 24'h02A00B
$display(" Slot4: RC_Tx = 6'b101010");
spi_write(mk_write(7'd5, 24'h02A00B));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "Slot4 RC_Tx exec done", "timeout");
tb_assert(o_RC_T27 === 1'b1, "RC_T27=1 (RC_Tx[5])", "RC_T27 mismatch");
tb_assert(o_RC_T28 === 1'b0, "RC_T28=0 (RC_Tx[4])", "RC_T28 mismatch");
tb_assert(o_RC_T29 === 1'b1, "RC_T29=1 (RC_Tx[3])", "RC_T29 mismatch");
tb_assert(o_RC_T30 === 1'b0, "RC_T30=0 (RC_Tx[2])", "RC_T30 mismatch");
tb_assert(o_RC_T31 === 1'b1, "RC_T31=1 (RC_Tx[1])", "RC_T31 mismatch");
tb_assert(o_RC_T32 === 1'b0, "RC_T32=0 (RC_Tx[0])", "RC_T32 mismatch");
#(`SPI_CLK_PERIOD * 2);
end
endtask
////==========================================================================
// Test Group 7: Error conditions
////==========================================================================
task test_error_conditions;
reg [1:0] done_r;
reg [31:0] rdata;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Group 7: Error conditions");
$display("-------------------------------------------------------------");
// 7a. Short SPI transaction (16 bits)
$display(" Error 7a: Short SPI transaction (16 bits)");
i_cs = 1'b0;
@(negedge i_sclk);
@(negedge i_sclk);
for (integer bi = 0; bi < 16; bi = bi + 1) begin
i_mosi = 1'b0;
@(posedge i_sclk);
@(negedge i_sclk);
end
i_cs = 1'b1;
@(negedge i_sclk);
#(`SYS_CLK_PERIOD * 5);
tb_assert(o_err === 1'b1,
"o_err HIGH after short SPI transaction", "");
i_rst_n = 1'b0;
#(`SYS_CLK_PERIOD * 4);
i_rst_n = 1'b1;
#(`SYS_CLK_PERIOD * 4);
tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
// 7b. Write to IDENT register (ADDR 0, read-only)
$display(" Error 7b: Write to IDENT register (ADDR 0)");
spi_write(mk_write(7'd0, 24'hDEADBEE >> 8));
@(negedge i_sclk);
tb_assert(o_err === 1'b1,
"o_err HIGH after write to IDENT register", "");
i_rst_n = 1'b0;
#(`SYS_CLK_PERIOD * 4);
i_rst_n = 1'b1;
#(`SYS_CLK_PERIOD * 4);
tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
#(`SPI_CLK_PERIOD);
// 7c. Read out-of-bounds address (ADDR 16)
$display(" Error 7c: Read out-of-bounds address (ADDR 16)");
spi_read(mk_read(7'd16), rdata);
@(negedge i_sclk);
#(`SYS_CLK_PERIOD * 5);
tb_assert(o_err === 1'b1,
"o_err HIGH after reading ADDR 16", "");
i_rst_n = 1'b0;
#(`SYS_CLK_PERIOD * 4);
i_rst_n = 1'b1;
#(`SYS_CLK_PERIOD * 4);
tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
#(`SPI_CLK_PERIOD);
// 7d. Multiple slot enables (en_t > 1)
$display(" Error 7d: Multiple slot enable bits");
spi_write(mk_write(7'd2, 24'h000005));
@(negedge i_sclk);
spi_write(mk_write(7'd3, 24'h000006));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "Execution completes (even with error)", "");
tb_assert(o_err === 1'b1,
"o_err HIGH with multiple slot enables", "");
i_rst_n = 1'b0;
#(`SYS_CLK_PERIOD * 4);
i_rst_n = 1'b1;
#(`SYS_CLK_PERIOD * 4);
tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
#(`SPI_CLK_PERIOD);
// 7e. Write to out-of-bounds address (ADDR 31)
$display(" Error 7e: Write to out-of-bounds address (ADDR 31)");
spi_write(mk_write(7'd31, 24'h123456));
@(negedge i_sclk);
#(`SYS_CLK_PERIOD * 5);
tb_assert(o_err === 1'b1,
"o_err HIGH after writing ADDR 31", "");
i_rst_n = 1'b0;
#(`SYS_CLK_PERIOD * 4);
i_rst_n = 1'b1;
#(`SYS_CLK_PERIOD * 4);
tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
#(`SPI_CLK_PERIOD * 2);
end
endtask
////==========================================================================
// Test Group 8: Edge cases
////==========================================================================
task test_edge_cases;
reg [31:0] rdata;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Group 8: Edge cases");
$display("-------------------------------------------------------------");
// 8a. Brief CS pulse (too short for 32-bit)
$display(" Edge 8a: Brief CS pulse");
i_cs = 1'b0;
@(negedge i_sclk);
@(negedge i_sclk);
i_cs = 1'b1;
@(negedge i_sclk);
#(`SYS_CLK_PERIOD * 5);
tb_assert(o_err === 1'b1,
"o_err detected brief CS pulse", "");
i_rst_n = 1'b0;
#(`SYS_CLK_PERIOD * 4);
i_rst_n = 1'b1;
#(`SYS_CLK_PERIOD * 4);
tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
#(`SPI_CLK_PERIOD);
// 8b. Rapid successive SPI writes
$display(" Edge 8b: Rapid successive SPI writes");
spi_write(mk_write(7'd2, 24'h000001));
spi_write(mk_write(7'd3, 24'h000002));
spi_write(mk_write(7'd4, 24'h000003));
spi_write(mk_write(7'd5, 24'h000004));
@(negedge i_sclk);
spi_read(mk_read(7'd2), rdata);
tb_assert(rdata === 24'h000001, "Rapid write: ADDR 2 correct", "ADDR 2 mismatch");
spi_read(mk_read(7'd3), rdata);
tb_assert(rdata === 24'h000002, "Rapid write: ADDR 3 correct", "ADDR 3 mismatch");
spi_read(mk_read(7'd4), rdata);
tb_assert(rdata === 24'h000003, "Rapid write: ADDR 4 correct", "ADDR 4 mismatch");
spi_read(mk_read(7'd5), rdata);
tb_assert(rdata === 24'h000004, "Rapid write: ADDR 5 correct", "ADDR 5 mismatch");
#(`SPI_CLK_PERIOD);
// 8c. Write to reserved registers (ADDR 10-15) - no error
$display(" Edge 8c: Write to reserved registers");
spi_write(mk_write(7'd10, 24'hABCDEF));
@(negedge i_sclk);
spi_write(mk_write(7'd15, 24'h123456));
@(negedge i_sclk);
tb_assert(o_err === 1'b0, "No error writing to reserved ADDR 10 and 15",
"Unexpected error");
#(`SPI_CLK_PERIOD * 2);
end
endtask
////==========================================================================
// Summary
////==========================================================================
task print_summary;
begin
$display("");
$display("=============================================================");
$display(" Test Summary");
$display("=============================================================");
$display(" Total tests: %0d", test_pass + test_fail);
$display(" Passed: %0d", test_pass);
$display(" Failed: %0d", test_fail);
$display("=============================================================");
if (test_fail == 0) begin
$display(" *** ALL TESTS PASSED ***");
end else begin
$display(" *** SOME TESTS FAILED - CHECK DESIGN ***");
end
$display("=============================================================");
$display("");
end
endtask
endmodule