diff --git a/CPLD1/BUS_Con.v b/CPLD1/BUS_Con.v
new file mode 100644
index 0000000..c28774e
--- /dev/null
+++ b/CPLD1/BUS_Con.v
@@ -0,0 +1,213 @@
+module BUS_Con (
+    input i_sys_clk,
+    input i_rst_n,
+    
+    // SPI Interface
+    input i_sclk,
+    input i_mosi,
+    input i_cs,
+    output o_miso,          // <-- MISO Logic added here
+    
+    // Local Interface
+    output o_rvalid,        // (Typo in original: o_rvalid)
+    input i_rvalid,         // Valid signal from Backend (Data is ready)
+    input i_wvalid,
+    output o_wready,
+    input i_reg_busy,
+    input [23:0] i_rdata,   // Data from Backend to send to Master
+    output o_wr,
+    output o_cmd_valid,
+    output [23:0] o_data,
+    output [6:0] o_addr,
+    output o_err
+);
+
+    // --- 1. Synchronization ---
+    reg [1:0] cs_sync;
+    reg [1:0] sclk_sync;
+    reg [1:0] mosi_sync;
+    
+    wire cs_active;
+    wire cs_rise;
+    wire sclk_rise; // For Sampling MOSI
+    wire sclk_fall; // For Shifting MISO
+    wire mosi_data;
+	
+
+    always @(posedge i_sys_clk) begin
+        if (!i_rst_n) begin
+            cs_sync   <= 2'b11;
+            sclk_sync <= 2'b00;
+            mosi_sync <= 2'b00;
+        end else begin
+            cs_sync   <= {cs_sync[0], i_cs};
+            sclk_sync <= {sclk_sync[0], i_sclk};
+            mosi_sync <= {mosi_sync[0], i_mosi};
+        end
+    end
+
+    assign cs_active = ~cs_sync[1]; 
+    assign cs_rise   = (!cs_sync[1] && cs_sync[0]); 
+    
+    // SPI Mode 0: Sample MOSI on Rising, Shift MISO on Falling
+    assign sclk_rise = (!sclk_sync[1] && sclk_sync[0]); 
+    assign sclk_fall = (sclk_sync[1] && !sclk_sync[0]); // Logic for MISO
+    assign mosi_data = mosi_sync[1];
+
+    // --- 2. MOSI (Receive) Logic ---
+    reg [31:0] recv_reg;
+    reg [5:0]  bit_cnt;
+    reg        data_ready;
+    reg        err_flag;
+	reg [1:0] state;
+	//
+	reg [31:0] tx_buffer;  // Holds data waiting for the next CS Low
+    reg [31:0] miso_shift; // The actual shifter
+    // Output Registers
+    reg [6:0]  addr_out;
+    reg [23:0] data_out;
+    reg        wr_out;
+    reg        cmd_valid_out;
+	
+	//
+	localparam IDLE      = 2'b00;
+    localparam CMD_SENT  = 2'b01;
+    localparam WAIT_BUSY = 2'b10;
+    localparam DONE      = 2'b11;
+    
+
+    always @(posedge i_sys_clk) begin
+        if (!i_rst_n) begin
+            recv_reg      <= 32'd0;
+            bit_cnt       <= 6'd0;
+            data_ready    <= 1'b0;
+            err_flag      <= 1'b0;
+        end 
+		else begin
+            data_ready <= 1'b0; 
+
+            if (cs_active) begin
+                if (sclk_rise) begin
+                    recv_reg <= {recv_reg[30:0], mosi_data}; 
+                    bit_cnt  <= bit_cnt + 1'b1;
+                end
+				else if (cs_rise) begin
+					if (bit_cnt == 6'd32) begin
+						data_ready <= 1'b1;
+						err_flag   <= 1'b0;
+						bit_cnt <= 6'd0;
+					end 
+					else if (bit_cnt != 0) begin
+						err_flag   <= 1'b1;
+						bit_cnt <= 6'd0;
+                        recv_reg <= 'd0;
+					end
+				end
+            end
+            if (state == DONE) begin
+                recv_reg <= 'd0;
+            end
+        end
+    end
+
+    // --- 3. MISO (Transmit) Logic ---
+    // Protocol: We shift out 32 bits. 
+    // Format: [8 bit Status/Padding] + [24 bit i_rdata]
+    
+
+    // Capture data from backend when valid
+    always @(posedge i_sys_clk) begin
+        if (!i_rst_n) begin
+            tx_buffer <= 32'd0;
+        end else begin
+            // If backend provides valid read data, store it.
+            // We pad the top 8 bits with Zeros (or you can put status flags here)
+            if (i_rvalid) begin
+                tx_buffer <= {8'h00, i_rdata}; 
+            end
+        end
+    end
+
+    // Shift data out
+    always @(posedge i_sys_clk) begin
+        if (!i_rst_n) begin
+            miso_shift <= 32'd0;
+        end else begin
+            if (!cs_active) begin
+                // Pre-load the shifter while CS is High
+                // This ensures Bit 31 is ready BEFORE the first clock edge
+                miso_shift <= tx_buffer;
+            end else begin
+                // Shift on Falling Edge (Master samples on Rising)
+                if (sclk_fall) begin
+                    miso_shift <= {miso_shift[30:0], 1'b0};
+                end
+            end
+        end
+    end
+
+    // Tri-state MISO when CS is high (optional, usually good practice)
+    // If your board doesn't need tristate, just use: assign o_miso = miso_shift[31];
+    assign o_miso = (cs_active) ? miso_shift[31] : 1'bz;
+
+    // --- 4. Register Control FSM ---
+
+    always @(posedge i_sys_clk) begin
+        if (!i_rst_n) begin
+            state         <= IDLE;
+            cmd_valid_out <= 1'b0;
+            addr_out      <= 7'd0;
+            data_out      <= 24'd0;
+            wr_out        <= 1'b0;
+        end else begin
+            case (state)
+                IDLE: begin
+                    if (data_ready) begin
+                        addr_out      <= recv_reg[30:24];
+                        data_out      <= recv_reg[23:0];
+                        wr_out        <= recv_reg[31];
+                        
+                        if (!i_reg_busy) begin
+                            cmd_valid_out <= 1'b1;
+                            state         <= CMD_SENT;
+                        end else begin
+                            state         <= WAIT_BUSY;
+                        end
+                    end
+                end
+
+                WAIT_BUSY: begin
+                    if (!i_reg_busy) begin
+                        cmd_valid_out <= 1'b1;
+                        state         <= CMD_SENT;
+                    end
+                end
+
+                CMD_SENT: begin
+                    cmd_valid_out <= 1'b0;
+                    state         <= DONE;
+                end
+
+                DONE: begin
+                    if (!i_reg_busy) begin
+                        state <= IDLE;
+                        addr_out <= 'd0;
+                        data_out <= 'd0;
+                        wr_out <= 'd0;
+                    end
+                end
+            endcase
+        end
+    end
+
+    assign o_addr      = addr_out;
+    assign o_data      = data_out;
+    assign o_wr        = wr_out;
+    assign o_cmd_valid = cmd_valid_out;
+    assign o_err       = err_flag;
+    assign o_wready    = (state == IDLE); 
+    
+    // Pass through unused signal or hook it up if needed
+    assign o_rvalid    = i_rvalid; 
+
+endmodule
\ No newline at end of file
diff --git a/CPLD1/CPLD1_Debug.rva b/CPLD1/CPLD1_Debug.rva
new file mode 100644
index 0000000..377f9a5
--- /dev/null
+++ b/CPLD1/CPLD1_Debug.rva
@@ -0,0 +1,96 @@
+<!DOCTYPE ispTLA>
+<ispTLA>
+ <CreationDate>??? 1?? 13 11:09:52 2026</CreationDate>
+ <XCFFileName/>
+ <CableSetting>
+  <IsTRSTConnected val="false"/>
+  <TRSTSetting val="0"/>
+  <IsBSCANConnected val="false"/>
+  <BSCANSetting val="0"/>
+  <CableType val="USB"/>
+  <PortAddress val="0"/>
+  <PortSetting val="0"/>
+  <TCKDelay val="1"/>
+ </CableSetting>
+ <DeviceCount>1</DeviceCount>
+ <Device>
+  <DeviceIndex>0</DeviceIndex>
+  <DeviceName>1. LCMXO2-7000HC</DeviceName>
+  <DeviceID>0x012BD043</DeviceID>
+  <HasIspTRACY>true</HasIspTRACY>
+  <HasJTAG2WB>false</HasJTAG2WB>
+  <SERDES/>
+  <IRBypassLen>8</IRBypassLen>
+  <RVLFileName>debug.rvl</RVLFileName>
+  <RVSFileName>debug.rvs</RVSFileName>
+  <LACoreCount>1</LACoreCount>
+  <WinUI CoreIndex="0">
+   <TraceSigTreeData>
+    <TraceSignal IsHidden="false" Name="BUS_Con_1/i_cs" NodeType="0" PortIndex="0"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_1/i_mosi" NodeType="0" PortIndex="1"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_1/i_sclk" NodeType="0" PortIndex="2"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/exec_flag" NodeType="0" PortIndex="3"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/i_con_exec" NodeType="0" PortIndex="4"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/slot_exec_flag" NodeType="1" PortIndex="5">
+     <BusRadix Radix="0"/>
+     <IsExpanded Expand="false"/>
+    </TraceSignal>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/slot_exec_flag:0" NodeType="2" PortIndex="5"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/slot_exec_flag:1" NodeType="2" PortIndex="6"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/slot_exec_flag:2" NodeType="2" PortIndex="7"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/slot_exec_flag:3" NodeType="2" PortIndex="8"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x01" NodeType="1" PortIndex="9">
+     <BusRadix Radix="0"/>
+     <IsExpanded Expand="false"/>
+    </TraceSignal>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x01:0" NodeType="2" PortIndex="9"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x01:1" NodeType="2" PortIndex="10"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x01:2" NodeType="2" PortIndex="11"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x01:3" NodeType="2" PortIndex="12"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x17" NodeType="1" PortIndex="13">
+     <BusRadix Radix="0"/>
+     <IsExpanded Expand="false"/>
+    </TraceSignal>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x17:0" NodeType="2" PortIndex="13"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x17:1" NodeType="2" PortIndex="14"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x17:2" NodeType="2" PortIndex="15"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x17:3" NodeType="2" PortIndex="16"/>
+    <TraceSignal IsHidden="false" Name="o_DMM_EN" NodeType="1" PortIndex="17">
+     <BusRadix Radix="0"/>
+     <IsExpanded Expand="true"/>
+    </TraceSignal>
+    <TraceSignal IsHidden="false" Name="o_DMM_EN:0" NodeType="2" PortIndex="17"/>
+    <TraceSignal IsHidden="false" Name="o_DMM_EN:1" NodeType="2" PortIndex="18"/>
+    <TraceSignal IsHidden="false" Name="o_DMM_EN:2" NodeType="2" PortIndex="19"/>
+    <TraceSignal IsHidden="false" Name="o_DMM_EN:3" NodeType="2" PortIndex="20"/>
+    <TraceSignal IsHidden="false" Name="o_DMM_EN:4" NodeType="2" PortIndex="21"/>
+    <TraceSignal IsHidden="false" Name="o_DMM_EN:5" NodeType="2" PortIndex="22"/>
+    <TraceSignal IsHidden="false" Name="o_DMM_EN:6" NodeType="2" PortIndex="23"/>
+    <TraceSignal IsHidden="false" Name="o_DMM_EN:7" NodeType="2" PortIndex="24"/>
+    <TraceSignal IsHidden="false" Name="o_DMM_EN:8" NodeType="2" PortIndex="25"/>
+    <TraceSignal IsHidden="false" Name="o_DMM_EN:9" NodeType="2" PortIndex="26"/>
+    <TraceSignal IsHidden="false" Name="o_DMM_EN:10" NodeType="2" PortIndex="27"/>
+    <TraceSignal IsHidden="false" Name="o_DMM_EN:11" NodeType="2" PortIndex="28"/>
+    <TraceSignal IsHidden="false" Name="o_DMM_EN:12" NodeType="2" PortIndex="29"/>
+    <TraceSignal IsHidden="false" Name="o_DMM_EN:13" NodeType="2" PortIndex="30"/>
+    <TraceSignal IsHidden="false" Name="o_DMM_EN:14" NodeType="2" PortIndex="31"/>
+    <TraceSignal IsHidden="false" Name="o_DMM_EN:15" NodeType="2" PortIndex="32"/>
+    <TraceSignal IsHidden="false" Name="o_IO_RC1" NodeType="0" PortIndex="33"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx" NodeType="1" PortIndex="34">
+     <BusRadix Radix="0"/>
+     <IsExpanded Expand="false"/>
+    </TraceSignal>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx:0" NodeType="2" PortIndex="34"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx:1" NodeType="2" PortIndex="35"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx:2" NodeType="2" PortIndex="36"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx:3" NodeType="2" PortIndex="37"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx:4" NodeType="2" PortIndex="38"/>
+   </TraceSigTreeData>
+   <TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/>
+   <CoreRun Run="true"/>
+   <CoreWndUIData>
+    <ClockFrequency Unit="ns" Frequency="-1.0"/>
+   </CoreWndUIData>
+  </WinUI>
+ </Device>
+</ispTLA>
diff --git a/CPLD1/CPLD1_Debug.svf b/CPLD1/CPLD1_Debug.svf
new file mode 100644
index 0000000..34e0b62
--- /dev/null
+++ b/CPLD1/CPLD1_Debug.svf
@@ -0,0 +1,1125 @@
+!
+! Diamond Reveal Analyzer SVF
+!
+! initialize SDR and SIR end state
+ENDDR IDLE;
+ENDIR IDLE;
+! initialize Header and Trailer
+HDR 0;
+HIR 0;
+TDR 0;
+TIR 0;
+
+! setTargetHubs
+! enable ER1
+SIR 8 TDI (32);
+! set reveal core
+SDR 21 TDI (00016);
+! enable ER2
+SIR 8 TDI (38);
+
+! enable ER2
+SIR 8 TDI (38);
+! enable ER2
+SIR 8 TDI (38);
+! Set Odd Parity readback
+SDR 36 TDI (c20000000);
+SDR 36 TDI (c20000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Set Odd Parity
+SDR 36 TDI (020000000);
+
+! Set LA Start/Stop readback
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Set LA Start/Stop 
+SDR 36 TDI (830000000);
+
+! Get Pattern
+SDR 36 TDI (430090000);
+SDR 36 TDI (430090000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Get Tracy Signature
+SDR 36 TDI (c30070000);
+SDR 36 TDI (c30070000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Get Tracy Signature
+SDR 36 TDI (c30080000);
+SDR 36 TDI (c30080000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Set Opcode Value
+SDR 36 TDI (000000007);
+
+! Set Mask Value
+SDR 36 TDI (000200000);
+
+! Set Opcode Value
+SDR 36 TDI (001000006);
+
+! Set Mask Value
+SDR 36 TDI (801200000);
+
+! Set Then Num
+SDR 36 TDI (010000000);
+
+! Set NEXT THEN
+SDR 36 TDI (810040000);
+
+! Set Cnt Cntg
+SDR 36 TDI (010030000);
+
+! Set Event Count
+SDR 36 TDI (810100000);
+
+! Set Event Count
+SDR 36 TDI (010110000);
+
+! Set Then Num
+SDR 36 TDI (811000000);
+
+! Set NEXT THEN
+SDR 36 TDI (011040000);
+
+! Set Cnt Cntg
+SDR 36 TDI (811030000);
+
+! Set Event Count
+SDR 36 TDI (011100000);
+
+! Set Event Count
+SDR 36 TDI (811110000);
+
+! Get BurstWrite CRC
+SDR 36 TDI (c10050000);
+SDR 36 TDI (c10050000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Set Truth Tbl Addr Cnter Init
+SDR 36 TDI (810020000);
+
+! Set Truth Table Prog
+SDR 36 TDI (810010000);
+
+! burst write
+SDR 16 TDI (5044);
+
+!==> [JTAG] burst write 2 byte = 5044
+
+! Get BurstWrite CRC
+SDR 36 TDI (c10050000);
+SDR 36 TDI (c10050000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] teCRC = DCEF (equation = DCEF)
+
+! Enable TE Trig
+SDR 36 TDI (820020003);
+
+! Enable Trig Output OR All readback
+SDR 36 TDI (c20000000);
+SDR 36 TDI (c20000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Enable Trig Output OR All
+SDR 36 TDI (820000008);
+
+! Set Pre-Trig Sample
+SDR 36 TDI (830010085);
+
+! Set Post-Trig Sample
+SDR 36 TDI (03002077a);
+
+! setTargetHubs
+! enable ER1
+SIR 8 TDI (32);
+! set reveal core
+SDR 21 TDI (00016);
+! enable ER2
+SIR 8 TDI (38);
+
+! enable ER2
+SIR 8 TDI (38);
+! Set LA Start cores
+SDR 36 TDI (030000001);
+
+! setTargetHubs
+! enable ER1
+SIR 8 TDI (32);
+! set reveal core
+SDR 21 TDI (00016);
+! enable ER2
+SIR 8 TDI (38);
+
+! Get Force Trigger bit
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Trig Detected Cnt
+SDR 36 TDI (430030000);
+SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Mem Block Full Cnt
+SDR 36 TDI (c30040000);
+SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmMemFullCnt = 0
+
+! setTargetHubs
+! enable ER1
+SIR 8 TDI (32);
+! set reveal core
+SDR 21 TDI (00016);
+! enable ER2
+SIR 8 TDI (38);
+
+! Get Force Trigger bit
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Trig Detected Cnt
+SDR 36 TDI (430030000);
+SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Mem Block Full Cnt
+SDR 36 TDI (c30040000);
+SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmMemFullCnt = 0
+
+! setTargetHubs
+! enable ER1
+SIR 8 TDI (32);
+! set reveal core
+SDR 21 TDI (00016);
+! enable ER2
+SIR 8 TDI (38);
+
+! Get Force Trigger bit
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Trig Detected Cnt
+SDR 36 TDI (430030000);
+SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Mem Block Full Cnt
+SDR 36 TDI (c30040000);
+SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmMemFullCnt = 0
+
+! setTargetHubs
+! enable ER1
+SIR 8 TDI (32);
+! set reveal core
+SDR 21 TDI (00016);
+! enable ER2
+SIR 8 TDI (38);
+
+! Get Force Trigger bit
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Trig Detected Cnt
+SDR 36 TDI (430030000);
+SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Mem Block Full Cnt
+SDR 36 TDI (c30040000);
+SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmMemFullCnt = 0
+
+! setTargetHubs
+! enable ER1
+SIR 8 TDI (32);
+! set reveal core
+SDR 21 TDI (00016);
+! enable ER2
+SIR 8 TDI (38);
+
+! Get Force Trigger bit
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Trig Detected Cnt
+SDR 36 TDI (430030000);
+SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Mem Block Full Cnt
+SDR 36 TDI (c30040000);
+SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmMemFullCnt = 1
+
+! Is LA Armed
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Set LA Start/Stop readback
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Set LA Start/Stop 
+SDR 36 TDI (030000004);
+
+! enable ER2
+SIR 8 TDI (38);
+! Set LA Start/Stop readback
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Set LA Start/Stop 
+SDR 36 TDI (030000004);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Trig Detected Cnt
+SDR 36 TDI (430030000);
+SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Get Mem Block Full Cnt
+SDR 36 TDI (c30040000);
+SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmMemFullCnt = 1
+
+! Get Last Addr Written
+SDR 36 TDI (430060000);
+SDR 36 TDI (430060000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmLastAddrWritten = 1330
+
+! Get Multiple Trig Enbl
+SDR 36 TDI (430050000);
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+! Get BurstRead CRC
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+! enable ER2
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+! burst read
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+
+!==> [JTAG] burst read 9984 byte = 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+
+! Get BurstRead CRC
+SDR 36 TDI (4300a0000);
+SDR 36 TDI (4300a0000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] dummy = 5BEC
+
+! Get BurstRead CRC
+SDR 36 TDI (4300a0000);
+SDR 36 TDI (4300a0000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmCRC = 5BEC (equation = B9CB)
+
+! Get Pre-Trig Sample Num
+SDR 36 TDI (c30010000);
+SDR 36 TDI (c30010000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Get Post-Trig Sample Num
+SDR 36 TDI (c30020000);
+SDR 36 TDI (c30020000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [TMEN] preTrig=128
+
+! Get Pre-Trig Samples Captured
+SDR 36 TDI (c31000000);
+SDR 36 TDI (c31000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Get Trig Ptr
+SDR 36 TDI (c32000000);
+SDR 36 TDI (c32000000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmTrigPTr = 1464
+
+!==> [TMEN] trigPtr=1464
+
+!==> [TMEN] pre_cap=true (preCap=1, regNum=0, offset=0)
+
+!==> [TMEN] trigPtr=1459 (- 5)
+
+!==> [TMEN] (pre_cap) out:3379-2048
+
+!==> [TMEN] (pre_cap) out:1331-1460
+
+!==> [TMEN] (pre_cap) triggerPosition=128
+
diff --git a/CPLD1/CPLD1_Debug.trc b/CPLD1/CPLD1_Debug.trc
new file mode 100644
index 0000000..01631ef
--- /dev/null
+++ b/CPLD1/CPLD1_Debug.trc
@@ -0,0 +1,2056 @@
+Device=0 LA=0
+TriggerFrameCount=1
+0 
+TriggerPosCount=1
+128 
+DataPos=1709
+Signature=677825265
+TraceWidth=39 TraceDepth=2048 TimeStampWidth=0
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diff --git a/CPLD1/CPLD1_sim.log b/CPLD1/CPLD1_sim.log
new file mode 100644
index 0000000..6869d75
--- /dev/null
+++ b/CPLD1/CPLD1_sim.log
@@ -0,0 +1,209 @@
+# 
+#   vlib work
+#   vlog -sv tb_RelayConTop.sv RelayConTop.v BUS_Con.v Reg_file.v CPLD_Con.v
+#   vsim tb_RelayConTop
+#   run -all
+#   quit
+# 
+# Questa Lattice OEM Edition-64 vlog 2024.2 Compiler 2024.05 May 20 2024
+# Start time: 18:32:29 on May 25,2026
+# vlog -sv tb_RelayConTop.sv RelayConTop.v BUS_Con.v Reg_file.v CPLD_Con.v 
+# -- Compiling module tb_RelayConTop
+# ** Warning: tb_RelayConTop.sv(765): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
+# -- Compiling module RelayConTop
+# -- Compiling module BUS_Con
+# -- Compiling module Reg_file
+# -- Compiling module CPLD_Con
+# ** Warning: CPLD_Con.v(215): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
+# 
+# Top level modules:
+# 	tb_RelayConTop
+# End time: 18:32:29 on May 25,2026, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 2
+# vsim tb_RelayConTop 
+# Start time: 18:32:29 on May 25,2026
+# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
+# //  Questa Lattice OEM Edition-64
+# //  Version 2024.2 linux_x86_64 May 20 2024
+# //
+# // Unpublished work. Copyright 2024 Siemens
+# //
+# // This material contains trade secrets or otherwise confidential information
+# // owned by Siemens Industry Software Inc. or its affiliates (collectively,
+# // "SISW"), or its licensors. Access to and use of this information is strictly
+# // limited as set forth in the Customer's applicable agreements with SISW.
+# //
+# // This material may not be copied, distributed, or otherwise disclosed outside
+# // of the Customer's facilities without the express written permission of SISW,
+# // and may not be used in any way not expressly authorized by SISW.
+# //
+# Loading sv_std.std
+# Loading work.tb_RelayConTop(fast)
+# 
+# =============================================================
+#   CPLD1 RelayConTop - Comprehensive Testbench
+#   System clock:          50 MHz | SPI clock:           2 MHz
+# =============================================================
+# 
+# -------------------------------------------------------------
+#   Group 1: Reset behavior & IDENT register
+# -------------------------------------------------------------
+# [PASS] Test 1: controller idle)
+# [PASS] Test 2:  LOW after reset
+# [PASS] Test 3: eset (SPI ready)
+# [FAIL] Test 4:   (CPLD1, v1.1.0)  >>                  
+# [PASS] Test 5: 
+# eros after reset
+# [PASS] Test 6: 
+# eros after reset
+# [PASS] Test 7:  zero after reset
+# 
+# -------------------------------------------------------------
+#   Group 2: Register read/write (ADDR 0-9)
+# -------------------------------------------------------------
+# [FAIL] Test 8: 	 write/read back  >>                  
+# [FAIL] Test 9: 	 write/read back  >>                  
+# [FAIL] Test 10: 	 write/read back  >>                  
+# [FAIL] Test 11: 	 write/read back  >>                  
+# [FAIL] Test 12:  back (PMU mode)  >>                  
+# [FAIL] Test 13: 	 write/read back  >>                  
+# [FAIL] Test 14: 	 write/read back  >>                  
+# [FAIL] Test 15: 	 write/read back  >>                  
+# [FAIL] Test 16: 	 default (RDY=1)  >>                  
+# 
+# -------------------------------------------------------------
+#   Group 3: Execution protocol
+# -------------------------------------------------------------
+# [PASS] Test 17: cution completes
+# [FAIL] Test 18: essful execution  >>                  
+# [PASS] Test 19: tion (SPI ready)
+# [PASS] Test 20: tes successfully
+# [FAIL] Test 21: C slot execution  >>                  
+# 
+# -------------------------------------------------------------
+#   Group 4: Frequency slot decoding (all 4 slots)
+# -------------------------------------------------------------
+#   Slot1 Ch5 (range 1-8): OC_x01=1, DMM_EN[0]=1
+# [PASS] Test 22: t1 Ch5 exec done
+# [FAIL] Test 23: ot1: RC_T27 idle  >>   RC_T27 mismatch
+# [FAIL] Test 24: 5: PMU_OC_1[0]=1  >> OC_1[0] mismatch
+# [FAIL] Test 25:  Ch5: DMM_EN[0]=1  >> 
+# M_EN[0] mismatch
+# [PASS] Test 26: 5: PMU_OC_2[0]=0
+#   Slot1 Ch50 (range 9-72): DMM_EN[1]=1
+# [PASS] Test 27: 1 Ch50 exec done
+# [FAIL] Test 28: h50: DMM_EN[1]=1  >> 
+# M_EN[1] mismatch
+# [PASS] Test 29: 0: PMU_OC_1[0]=0
+#   Slot1 Ch100 (range 73-136): OC_x17=1, DMM_EN[2]=1
+# [PASS] Test 30: 
 Ch100 exec done
+# [FAIL] Test 31:  : PMU_OC_1[16]=1  >> C_1[16] mismatch
+# [FAIL] Test 32: 100: DMM_EN[2]=1  >> 
+# M_EN[2] mismatch
+#   Slot1 Ch150 (range 137-200): DMM_EN[3]=1
+# [PASS] Test 33: 
 Ch150 exec done
+# [FAIL] Test 34: 150: DMM_EN[3]=1  >> 
+# M_EN[3] mismatch
+#   Slot2 Ch5 (range 1-8): OC_x01=2, DMM_EN[4]=1
+# [PASS] Test 35: t2 Ch5 exec done
+# [FAIL] Test 36: 5: PMU_OC_2[0]=1  >> OC_2[0] mismatch
+# [FAIL] Test 37:  Ch5: DMM_EN[4]=1  >> 
+# M_EN[4] mismatch
+#   Slot3 Ch100 (range 73-136): OC_x17=4, DMM_EN[10]=1
+# [PASS] Test 38:  Ch100 exec done
+# [FAIL] Test 39:  : PMU_OC_3[16]=1  >> C_3[16] mismatch
+# [FAIL] Test 40: 
00: DMM_EN[10]=1  >> 
+# _EN[10] mismatch
+#   Slot4 Ch50 (range 9-72): DMM_EN[5]=1
+# [PASS] Test 41: 4 Ch50 exec done
+# [FAIL] Test 42: h50: DMM_EN[5]=1  >> 
+# M_EN[5] mismatch
+# 
+# -------------------------------------------------------------
+#   Group 5: DC slot PMU mode (DPS is stubbed, not tested)
+# -------------------------------------------------------------
+#   DC1: V mode, Rload=3, Ch=3, PMU
+# [PASS] Test 43:  V-mode exec done
+# [PASS] Test 44: _VSel=1 (V mode)
+# [PASS] Test 45: _ISel=0 (V mode)
+# [FAIL] Test 46: 
8'b100 (Rload=3)  >> C_RLSel mismatch
+# [FAIL] Test 47: OC_1[0]=1 (Ch=3)  >> OC_1[0] mismatch
+#   DC1: I mode, Rload=1, Ch=11, PMU
+# [PASS] Test 48:  I-mode exec done
+# [FAIL] Test 49: _VSel=0 (I mode)  >>  RC_VSel mismatch
+# [FAIL] Test 50: _ISel=1 (I mode)  >>  RC_ISel mismatch
+# [FAIL] Test 51: l[0]=1 (Rload=1)  >> C_RLSel mismatch
+# [FAIL] Test 52: C_1[1]=1 (Ch=11)  >> OC_1[1] mismatch
+#   DC2: V mode, Rload=5, Ch=19, PMU
+# [PASS] Test 53:  V-mode exec done
+# [PASS] Test 54: _VSel=1 (V mode)
+# [FAIL] Test 55: C_2[2]=1 (Ch=19)  >> OC_2[2] mismatch
+#   DC3: V mode, Rload=10, Ch=27, PMU
+# [PASS] Test 56:  V-mode exec done
+# [FAIL] Test 57: C_3[3]=1 (Ch=27)  >> OC_3[3] mismatch
+#   DC4: V mode, Rload=18, Ch=35, PMU
+# [PASS] Test 58:  V-mode exec done
+# [FAIL] Test 59: 17]=1 (Rload=18)  >> C_RLSel mismatch
+# [FAIL] Test 60: C_4[4]=1 (Ch=35)  >> OC_4[4] mismatch
+# [PASS] Test 61:  1 when RC_VSel=1
+# 
+# -------------------------------------------------------------
+#   Group 6: RC_Tx relay output (slot 4)
+# -------------------------------------------------------------
+#   Slot4: RC_Tx = 6'b101010
+# [PASS] Test 62:  RC_Tx exec done
+# [FAIL] Test 63: T27=1 (RC_Tx[5])  >>   RC_T27 mismatch
+# [FAIL] Test 64: T28=0 (RC_Tx[4])  >>   RC_T28 mismatch
+# [FAIL] Test 65: T29=1 (RC_Tx[3])  >>   RC_T29 mismatch
+# [FAIL] Test 66: T30=0 (RC_Tx[2])  >>   RC_T30 mismatch
+# [FAIL] Test 67: T31=1 (RC_Tx[1])  >>   RC_T31 mismatch
+# [FAIL] Test 68: T32=0 (RC_Tx[0])  >>   RC_T32 mismatch
+# 
+# -------------------------------------------------------------
+#   Group 7: Error conditions
+# -------------------------------------------------------------
+#   Error 7a: Short SPI transaction (16 bits)
+# [PASS] Test 69:  SPI transaction
+# [PASS] Test 70: ared after reset
+#   Error 7b: Write to IDENT register (ADDR 0)
+# [PASS] Test 71: o IDENT register
+# [PASS] Test 72: ared after reset
+#   Error 7c: Read out-of-bounds address (ADDR 16)
+# [PASS] Test 73:  reading ADDR 16
+# [PASS] Test 74: ared after reset
+#   Error 7d: Multiple slot enable bits
+# [PASS] Test 75: even with error)
+# [PASS] Test 76: 	ple slot enables
+# [PASS] Test 77: ared after reset
+#   Error 7e: Write to out-of-bounds address (ADDR 31)
+# [PASS] Test 78:  writing ADDR 31
+# [PASS] Test 79: ared after reset
+# 
+# -------------------------------------------------------------
+#   Group 8: Edge cases
+# -------------------------------------------------------------
+#   Edge 8a: Brief CS pulse
+# [PASS] Test 80: d brief CS pulse
+# [PASS] Test 81: ared after reset
+#   Edge 8b: Rapid successive SPI writes
+# [FAIL] Test 82: : ADDR 2 correct  >>   ADDR 2 mismatch
+# [FAIL] Test 83: : ADDR 3 correct  >>   ADDR 3 mismatch
+# [FAIL] Test 84: : ADDR 4 correct  >>   ADDR 4 mismatch
+# [FAIL] Test 85: : ADDR 5 correct  >>   ADDR 5 mismatch
+#   Edge 8c: Write to reserved registers
+# [FAIL] Test 86: d ADDR 10 and 15  >>  Unexpected error
+# 
+# =============================================================
+#   Test Summary
+# =============================================================
+#   Total tests: 86
+#   Passed:      41
+#   Failed:      45
+# =============================================================
+#   *** SOME TESTS FAILED - CHECK DESIGN ***
+# =============================================================
+# 
+# ** Note: $finish    : tb_RelayConTop.sv(349)
+#    Time: 1101600 ns  Iteration: 0  Instance: /tb_RelayConTop
+# End time: 18:32:29 on May 25,2026, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
diff --git a/CPLD1/CPLD_Con.v b/CPLD1/CPLD_Con.v
new file mode 100644
index 0000000..67f30d6
--- /dev/null
+++ b/CPLD1/CPLD_Con.v
@@ -0,0 +1,376 @@
+module CPLD_Con (
+    input i_sys_clk,
+    input i_rst_n,
+    input i_con_exec,
+
+// Freq Relay Control
+    input [23:0]i_freq_relay1,
+    input [23:0]i_freq_relay2,
+    input [23:0]i_freq_relay3,
+    input [23:0]i_freq_relay4,
+
+// DC related Control
+    input [23:0]i_DC_Con1,
+    input [23:0]i_DC_Con2,
+    input [23:0]i_DC_Con3,
+    input [23:0]i_DC_Con4,
+
+    //Output RELAYs
+    output [3:0]o_OC_x01,
+    output [3:0]o_OC_x17,
+    output [18:0]o_DMM_EN,
+    output o_IO_RC1,
+    output [5:0]o_RC_Tx,
+
+    output [31:0]o_PMU_OC_1 ,
+    output [31:0]o_PMU_OC_2 ,
+    output [31:0]o_PMU_OC_3 ,
+    output [31:0]o_PMU_OC_4 ,
+
+//  DMM Mode Sel
+    output o_RC_VSel,           
+    output o_RC_ISel,
+
+// Output RLoad Sel
+    output [17:0]o_RC_RLSel,
+
+//  FLAGs
+    output o_con_done,
+    output o_err
+);
+
+    //Relay Reg
+    reg [3:0]OC_x01 ;
+    reg [3:0]OC_x17 ;
+    reg [18:0]DMM_en ;
+	
+	reg[5:0]RC_Tx;
+    reg io_RC;
+
+    reg RC_VISel;
+    reg [17:0]RC_RLSel ;
+    reg [31:0]PMU_OC_1 ;
+    reg [31:0]PMU_OC_2 ;
+    reg [31:0]PMU_OC_3 ;
+    reg [31:0]PMU_OC_4 ;
+
+    //Condition Tester
+    reg [15:0]en_t ;
+    reg freq_t;
+    reg dc_t;
+
+    //Flags
+    reg exec_flag;
+    reg err_flag;
+    reg [3:0]freq_slot_flag;
+    reg [3:0]dc_slot_flag ;
+    reg done_flag;
+
+    //Counter
+    reg [15:0]delay_cnt;
+
+    always @(posedge i_sys_clk) begin
+        if (i_rst_n == 1'b0) begin
+            delay_cnt <= 'd0;
+        end
+        else begin
+            if (exec_flag == 1'b1) begin
+                delay_cnt <= delay_cnt + 1'd1;
+            end
+            else begin
+                delay_cnt <= 'd0;
+            end
+        end
+    end
+
+//Function Identify
+    always @(posedge i_sys_clk) begin
+        if (i_rst_n == 1'b0) begin
+            en_t <= 'd0;
+            freq_t <= 'd0;
+            dc_t <= 'd0;
+        end
+        else begin
+            en_t <= (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) + (i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0] );
+            freq_t <= i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0];
+            dc_t <= i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0];
+        end
+    end
+
+//  Main Controller Function
+    always @(posedge i_sys_clk) begin
+        if (i_rst_n == 1'b0) begin
+            exec_flag <= 1'b0;
+            err_flag <= 1'b0;
+
+            freq_slot_flag <= 'd0;
+            dc_slot_flag <= 'd0;
+
+            OC_x01              <= 'd0;
+            OC_x17              <= 'd0;
+
+            DMM_en            <= 'd0;
+            
+            RC_VISel            <='d0;
+            RC_RLSel           <='d0;
+
+            PMU_OC_1       <= 'd0 ;
+            PMU_OC_2       <= 'd0 ;
+            PMU_OC_3       <= 'd0 ;
+            PMU_OC_4       <= 'd0 ;
+
+            done_flag <= 'd1;
+        end
+        else begin
+            if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin
+                //To DO: More Sanity Check?
+                if (en_t > 'd1) begin                                                   //Only ONE Enable bit should be set!
+                    err_flag <= 1'b1;
+                end
+                else begin
+                    exec_flag <= 1'b1;
+                    done_flag <= 1'b0;
+                    err_flag <= 1'b0;
+                    freq_slot_flag[0] <= i_freq_relay1[0];
+                    freq_slot_flag[1] <= i_freq_relay2[0];
+                    freq_slot_flag[2] <= i_freq_relay3[0];
+                    freq_slot_flag[3] <= i_freq_relay4[0];
+                    
+                    RC_Tx <= i_freq_relay4[17:12];                      //Special Relay for slot4
+
+                    dc_slot_flag[0] <= i_DC_Con1[0];
+                    dc_slot_flag[1] <= i_DC_Con2[0];
+                    dc_slot_flag[2] <= i_DC_Con3[0];
+                    dc_slot_flag[3] <= i_DC_Con4[0];
+
+                end
+            end
+            else if (exec_flag == 1'b1) begin
+                if (freq_t == 1'b1) begin
+                    io_RC <= i_freq_relay1[0] || i_freq_relay2[0] || i_freq_relay3[0] || i_freq_relay4[0];
+                    case (freq_slot_flag)
+                        4'b0001: begin
+                            if (i_freq_relay1[9:1] < 9) begin
+                                OC_x01 <= 4'b0001;
+                                OC_x17 <= 'd0;
+                                DMM_en <= 19'b000_0000_0000_0000_0001;
+                            end
+                            else if (i_freq_relay1[9:1] < 73) begin
+                                DMM_en <= 19'b000_0000_0000_0000_0010;
+                                OC_x01 <= 'd0;
+                                OC_x17 <= 'd0;
+                            end
+                            else if (i_freq_relay1[9:1] < 137) begin
+                                OC_x17 <= 4'b0001;
+                                OC_x01 <= 'd0;
+                                DMM_en <= 19'b000_0000_0000_0000_0100;
+                            end
+                            else begin
+                                DMM_en <= 19'b000_0000_0000_0000_1000;
+                                OC_x01 <= 'd0;
+                                OC_x17 <= 'd0;
+                            end
+                        end
+                        4'b0010: begin
+                            if (i_freq_relay2[9:1] < 9) begin
+                                OC_x01 <= 4'b0010;
+                                OC_x17 <= 'd0;
+                                DMM_en <= 19'b000_0000_0000_0001_0000;
+                            end
+                            else if (i_freq_relay2[9:1] < 73) begin
+                                DMM_en <= 19'b000_0000_0000_0010_0000;
+                                OC_x01 <= 'd0;
+                                OC_x17 <= 'd0;
+                            end
+                            else if (i_freq_relay2[9:1] < 137) begin
+                                OC_x17 <= 4'b0010;
+                                OC_x01 <= 'd0;
+                                DMM_en <= 19'b000_0000_0000_0100_0000;
+                            end
+                            else begin
+                                OC_x01 <= 'd0;
+                                OC_x17 <= 'd0;
+                                DMM_en <= 19'b000_0000_0000_1000_0000;
+                            end
+                        end
+                        4'b0100: begin
+                            if (i_freq_relay3[9:1] < 9) begin
+                                OC_x01 <= 'b0100;
+                                OC_x17 <= 'd0;
+                                DMM_en <= 19'b000_0000_0001_0000_0000;
+                            end
+                            else if ((i_freq_relay3[9:1] > 64)& (i_freq_relay3[9:1] < 73)) begin
+                                OC_x01 <= 4'b0000;
+                                OC_x17 <= 'd0;
+                                DMM_en <= 19'b000_0000_0010_0000_0000;
+                            end
+                            else if (i_freq_relay3[9:1] < 137) begin
+                                DMM_en <= 19'b000_0000_0100_0000_0000;
+                                OC_x01 <= 'd0;
+                                OC_x17 <= 'b0100;
+                            end
+                            else if (i_freq_relay3[9:1] < 201) begin
+                                OC_x17 <= 4'd0;
+                                OC_x01 <= 'd0;
+                                DMM_en <= 16'b000_0000_1000_0000_0000; 
+                            end
+                        end
+                        4'b1000: begin
+                            if (i_freq_relay4[9:1] < 9) begin
+                                OC_x01 <= 4'b1000;
+                                OC_x17 <= 'd0;
+                                DMM_en <= 19'b000_0001_0000_0000_0000;
+                            end
+                            else if (i_freq_relay4[9:1] < 72) begin
+                                DMM_en <= 19'b000_0010_0000_0000_0000;
+                                OC_x01 <= 'd0;
+                                OC_x17 <= 'd0;
+                            end
+                            else if (i_freq_relay4[9:1] < 137) begin
+                                OC_x17 <= 4'b1000;
+                                OC_x01 <= 'd0;
+                                DMM_en <= 19'b000_0100_0000_0000_0000;
+                            end
+                            else begin
+                                OC_x01 <= 'd0;
+                                OC_x17 <= 'd0;
+                                DMM_en <= 19'b000_1000_0000_0000_0000;
+                            end
+                        end
+                        default: begin                                                                                  // You Should NOT be HERE
+                            OC_x01 <= 4'b0000;
+                            OC_x17 <= 4'b0000;
+                            DMM_en <= 'd0;
+                        end
+                    endcase
+                end
+                else if (dc_t == 1'b1) begin
+                    case (dc_slot_flag)
+                        4'b0001: begin
+                            if (i_DC_Con1[22] == 1'b1) begin
+                                RC_VISel <= 1'b1;                                   //Select Current
+                            end
+                            else begin
+                                RC_VISel <= 1'b0;                                   //Select Voltage
+                            end
+                            //Sanity Check
+                            if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18) || (i_DC_Con1[9:1] < 1) || (i_DC_Con1[9:1]  > 256)) begin
+                                err_flag <= 1'b1;
+                            end
+                            else begin
+                                RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con1[21:17] - 1);
+                                if (i_DC_Con1[23] == 1'b0) begin                //Select PMU
+                                    PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con1[9:1]/8);
+                                    DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con1[9:1]/8);
+                                end
+                                else if (i_DC_Con1[23] == 1'b1) begin       //Select DPS
+                                    
+                                end
+                            end
+                        end
+                        4'b0010: begin
+                            if (i_DC_Con2[22] == 1'b1) begin
+                                RC_VISel <= 1'b1;                                   //Select Current
+                            end
+                            else begin
+                                RC_VISel <= 1'b0;                                   //Select Voltage
+                            end
+                             //Sanity Check
+                            if ((i_DC_Con2[21:17] < 1) || (i_DC_Con2[21:17] > 18) || (i_DC_Con2[9:1] < 1) || (i_DC_Con2[9:1]  > 256)) begin
+                                err_flag <= 1'b1;
+                            end
+                            else begin
+                                RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con2[21:17] - 1);
+                                if (i_DC_Con2[23] == 1'b0) begin                //Select PMU
+                                    PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con2[9:1]/8);
+                                    DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con2[9:1]/8);
+                                end
+                                else if (i_DC_Con2[23] == 1'b1) begin       //Select DPS
+                                    
+                                end
+                            end
+                        end
+                        4'b0100:begin
+                            if (i_DC_Con3[22] == 1'b1) begin
+                                RC_VISel <= 1'b1;                                   //Select Current
+                            end
+                            else begin
+                                RC_VISel <= 1'b0;                                   //Select Voltage
+                            end
+                             //Sanity Check
+                            if ((i_DC_Con3[21:17] < 1) || (i_DC_Con3[21:17] > 18) || (i_DC_Con3[9:1] < 1) || (i_DC_Con3[9:1]  > 256)) begin
+                                err_flag <= 1'b1;
+                            end
+                            else begin
+                                RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con3[21:17] - 1);
+                                if (i_DC_Con3[23] == 1'b0) begin                //Select PMU
+                                    PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con3[9:1]/8);
+                                    DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con3[9:1]/8);
+                                end
+                                else if (i_DC_Con3[23] == 1'b1) begin       //Select DPS
+                                    
+                                end
+                            end
+                        end
+                        4'b1000:begin
+                            if (i_DC_Con4[22] == 1'b1) begin
+                                RC_VISel <= 1'b1;                                   //Select Current
+                            end
+                            else begin
+                                RC_VISel <= 1'b0;                                   //Select Voltage
+                            end
+                             //Sanity Check
+                            if ((i_DC_Con4[21:17] < 1) || (i_DC_Con4[21:17] > 18) || (i_DC_Con4[9:1] < 1) || (i_DC_Con4[9:1]  > 256)) begin
+                                err_flag <= 1'b1;
+                            end
+                            else begin
+                                RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con4[21:17] - 1);
+                                if (i_DC_Con4[23] == 1'b0) begin                //Select PMU
+                                    PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con4[9:1]/8);
+                                    DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con4[9:1]/8);
+                                end
+                                else if (i_DC_Con4[23] == 1'b1) begin       //Select DPS
+                                    
+                                end
+                            end
+                        end
+                        default:begin                           // You Should NOT be HERE
+                            RC_VISel            <='d0;
+                            RC_RLSel           <='d0;
+
+                            PMU_OC_1       <= 'd0 ;
+                            PMU_OC_2       <= 'd0 ;
+                            PMU_OC_3       <= 'd0 ;
+                            PMU_OC_4       <= 'd0 ;
+                            DMM_en            <= 'd0;
+                        end
+                    endcase
+                end
+                done_flag <= 1'b1;
+            end
+        end
+        if (done_flag == 1) begin
+            exec_flag <= 1'b0; 
+        end
+    end 
+
+    assign o_con_done = done_flag;
+    assign o_DMM_EN = DMM_en;
+    assign o_OC_x01 = OC_x01;
+    assign o_OC_x17 = OC_x17;
+    assign o_IO_RC1 = io_RC;
+    assign o_err = err_flag;
+    assign o_RC_Tx = RC_Tx;
+
+    assign o_RC_ISel = (RC_VISel==1'b1)?1:0;
+    assign o_RC_VSel = (RC_VISel==1'b1)?0:1;
+
+    assign o_RC_RLSel = RC_RLSel;
+
+    assign o_PMU_OC_1   = PMU_OC_1;
+    assign o_PMU_OC_2   = PMU_OC_2;
+    assign o_PMU_OC_3   = PMU_OC_3;
+    assign o_PMU_OC_4   = PMU_OC_4;
+
+
+endmodule
\ No newline at end of file
diff --git a/CPLD1/NewExtInsRelay1.sty b/CPLD1/NewExtInsRelay1.sty
new file mode 100644
index 0000000..11299b1
--- /dev/null
+++ b/CPLD1/NewExtInsRelay1.sty
@@ -0,0 +1,206 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE strategy>
+<Strategy version="1.0" predefined="0" description="" label="Strategy1">
+    <Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
+    <Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
+    <Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
+    <Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
+    <Property name="PROP_BD_EdfMemPath" value="" time="0"/>
+    <Property name="PROP_BD_ParSearchPath" value="" time="0"/>
+    <Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
+    <Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
+    <Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
+    <Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
+    <Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
+    <Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
+    <Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
+    <Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
+    <Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
+    <Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
+    <Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
+    <Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
+    <Property name="PROP_BIT_NoHeader" value="False" time="0"/>
+    <Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
+    <Property name="PROP_BIT_OutFormatBitGen_REF" value="Bit File (Binary)" time="0"/>
+    <Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
+    <Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
+    <Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
+    <Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
+    <Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
+    <Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
+    <Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
+    <Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
+    <Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
+    <Property name="PROP_LST_CarryChain" value="True" time="0"/>
+    <Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
+    <Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
+    <Property name="PROP_LST_DSPUtil" value="100" time="0"/>
+    <Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
+    <Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
+    <Property name="PROP_LST_EBRUtil" value="100" time="0"/>
+    <Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
+    <Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
+    <Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
+    <Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
+    <Property name="PROP_LST_EdfMemPath" value="" time="0"/>
+    <Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
+    <Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
+    <Property name="PROP_LST_IOInsertion" value="True" time="0"/>
+    <Property name="PROP_LST_InterFileDump" value="False" time="0"/>
+    <Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
+    <Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
+    <Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
+    <Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
+    <Property name="PROP_LST_PropagatConst" value="True" time="0"/>
+    <Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
+    <Property name="PROP_LST_ReportTrimmedUserNets" value="False" time="0"/>
+    <Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
+    <Property name="PROP_LST_ResourceShare" value="True" time="0"/>
+    <Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
+    <Property name="PROP_LST_UseLPF" value="True" time="0"/>
+    <Property name="PROP_LST_VHDL2008" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
+    <Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
+    <Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
+    <Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
+    <Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
+    <Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
+    <Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
+    <Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
+    <Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
+    <Property name="PROP_MAP_MapModArgs" value="" time="0"/>
+    <Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
+    <Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
+    <Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
+    <Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
+    <Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
+    <Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
+    <Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
+    <Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
+    <Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
+    <Property name="PROP_PARSTA_FullName" value="False" time="0"/>
+    <Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
+    <Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
+    <Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
+    <Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
+    <Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
+    <Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
+    <Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
+    <Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
+    <Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
+    <Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
+    <Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
+    <Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
+    <Property name="PROP_PAR_PARModArgs" value="" time="0"/>
+    <Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
+    <Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
+    <Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
+    <Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
+    <Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
+    <Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
+    <Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
+    <Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
+    <Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_StopZero" value="False" time="0"/>
+    <Property name="PROP_PAR_parHold" value="On" time="0"/>
+    <Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
+    <Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
+    <Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
+    <Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
+    <Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
+    <Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
+    <Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
+    <Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
+    <Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
+    <Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
+    <Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfArea" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
+    <Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
+    <Property name="PROP_SYN_EdfFrequency" value="200" time="0"/>
+    <Property name="PROP_SYN_EdfGSR" value="Auto" time="0"/>
+    <Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfNumCritPath" value="3" time="0"/>
+    <Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
+    <Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
+    <Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
+    <Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
+    <Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
+    <Property name="PROP_SYN_LibPath" value="" time="0"/>
+    <Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
+    <Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
+    <Property name="PROP_SYN_UseLPF" value="True" time="0"/>
+    <Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
+    <Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
+    <Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
+    <Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
+    <Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
+    <Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
+    <Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
+    <Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
+    <Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
+    <Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
+    <Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
+    <Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
+    <Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
+</Strategy>
diff --git a/CPLD1/NewExtIns_CPLD1.ccl b/CPLD1/NewExtIns_CPLD1.ccl
new file mode 100644
index 0000000..dcf391b
--- /dev/null
+++ b/CPLD1/NewExtIns_CPLD1.ccl
@@ -0,0 +1 @@
+VERSION=20110520
diff --git a/CPLD1/NewExtIns_CPLD1.ldf b/CPLD1/NewExtIns_CPLD1.ldf
new file mode 100644
index 0000000..9f8a17b
--- /dev/null
+++ b/CPLD1/NewExtIns_CPLD1.ldf
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.2" title="NewExtIns_CPLD1" device="LCMXO2-7000HC-4FG484C" default_implementation="impl1">
+    <Options/>
+    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
+        <Options def_top="RelayConTop" top="RelayConTop"/>
+        <Source name="RelayConTop.v" type="Verilog" type_short="Verilog">
+            <Options top_module="RelayConTop"/>
+        </Source>
+        <Source name="BUS_Con.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="Reg_file.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="tb_RelayConTop.sv" type="Verilog" type_short="Verilog" syn_sim="SimOnly">
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
+        <Source name="RelayConTop_tf.v" type="Verilog" type_short="Verilog" syn_sim="SimOnly">
+            <Options/>
+        </Source>
+        <Source name="CPLD_Con.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="CPLD1_Debug.rva" type="Reveal Analyzer Project File" type_short="RVA">
+            <Options/>
+        </Source>
+        <Source name="NewExtIns_CPLD1.lpf" type="Logic Preference" type_short="LPF">
+            <Options/>
+        </Source>
+        <Source name="debug.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
+            <Options/>
+        </Source>
+        <Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
+            <Options/>
+        </Source>
+        <Source name="tb_RelayConTop/tb_RelayConTop.spf" type="Simulation Project File" type_short="SPF">
+            <Options/>
+        </Source>
+    </Implementation>
+    <Strategy name="Strategy1" file="NewExtInsRelay1.sty"/>
+</BaliProject>
diff --git a/CPLD1/NewExtIns_CPLD1.lpf b/CPLD1/NewExtIns_CPLD1.lpf
new file mode 100644
index 0000000..4b8a16c
--- /dev/null
+++ b/CPLD1/NewExtIns_CPLD1.lpf
@@ -0,0 +1,313 @@
+RVL_ALIAS "i_sys_clk" "i_sys_clk"; 
+RVL_ALIAS "i_sys_clk" "i_sys_clk"; 
+RVL_ALIAS "i_sys_clk" "i_sys_clk"; 
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+LOCATE COMP "i_sys_clk" SITE "B9" ;
+LOCATE COMP "i_rst_n" SITE "Y14" ;
+LOCATE COMP "i_sclk" SITE "AA10" ;
+LOCATE COMP "i_cs" SITE "AB11" ;
+LOCATE COMP "i_mosi" SITE "AB12" ;
+LOCATE COMP "o_miso" SITE "AA14" ;
+LOCATE COMP "o_err" SITE "AB16" ;
+LOCATE COMP "o_DMM_EN[0]" SITE "F17" ;
+LOCATE COMP "o_DMM_EN[1]" SITE "E17" ;
+LOCATE COMP "o_DMM_EN[2]" SITE "D17" ;
+IOBUF PORT "i_cs" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "i_mosi" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "i_sclk" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ;
+IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "i_sys_clk" DRIVE=NA IO_TYPE=LVCMOS33 SLEWRATE=NA PULLMODE=DOWN ;
+IOBUF PORT "o_err" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_DMM_EN[0]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_DMM_EN[1]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_DMM_EN[2]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_DMM_EN[3]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_DMM_EN[4]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_DMM_EN[5]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_DMM_EN[6]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_DMM_EN[7]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_DMM_EN[8]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_DMM_EN[9]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_DMM_EN[10]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_DMM_EN[11]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_DMM_EN[12]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_DMM_EN[13]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_DMM_EN[14]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_DMM_EN[15]" IO_TYPE=LVCMOS33 ;
+LOCATE COMP "o_DMM_EN[3]" SITE "C17" ;
+LOCATE COMP "o_DMM_EN[4]" SITE "AB10" ;
+LOCATE COMP "o_DMM_EN[5]" SITE "AA11" ;
+LOCATE COMP "o_DMM_EN[6]" SITE "AA12" ;
+LOCATE COMP "o_DMM_EN[7]" SITE "AB13" ;
+LOCATE COMP "o_DMM_EN[8]" SITE "D15" ;
+LOCATE COMP "o_DMM_EN[9]" SITE "D14" ;
+LOCATE COMP "o_DMM_EN[10]" SITE "C13" ;
+LOCATE COMP "o_DMM_EN[11]" SITE "F12" ;
+LOCATE COMP "o_DMM_EN[12]" SITE "W12" ;
+LOCATE COMP "o_DMM_EN[13]" SITE "V12" ;
+LOCATE COMP "o_DMM_EN[14]" SITE "Y12" ;
+LOCATE COMP "o_DMM_EN[15]" SITE "V13" ;
+LOCATE COMP "o_IO_RC1" SITE "F10" ;
+IOBUF PORT "o_IO_RC1" IO_TYPE=LVCMOS33 ;
+BLOCK JTAGPATHS ;
+LOCATE COMP "o_PMU_OC_1[0]" SITE "M19" ;
+LOCATE COMP "o_PMU_OC_1[1]" SITE "R16" ;
+LOCATE COMP "o_PMU_OC_1[2]" SITE "N20" ;
+LOCATE COMP "o_PMU_OC_1[3]" SITE "P20" ;
+LOCATE COMP "o_PMU_OC_1[4]" SITE "G19" ;
+LOCATE COMP "o_PMU_OC_1[5]" SITE "J19" ;
+LOCATE COMP "o_PMU_OC_1[6]" SITE "H16" ;
+LOCATE COMP "o_PMU_OC_1[7]" SITE "J17" ;
+LOCATE COMP "o_PMU_OC_1[16]" SITE "W6" ;
+LOCATE COMP "o_PMU_OC_1[17]" SITE "AA7" ;
+LOCATE COMP "o_PMU_OC_1[18]" SITE "AB6" ;
+LOCATE COMP "o_PMU_OC_1[19]" SITE "Y7" ;
+LOCATE COMP "o_PMU_OC_1[20]" SITE "V4" ;
+LOCATE COMP "o_PMU_OC_1[21]" SITE "R6" ;
+LOCATE COMP "o_PMU_OC_1[22]" SITE "U4" ;
+LOCATE COMP "o_PMU_OC_1[23]" SITE "T5" ;
+LOCATE COMP "o_PMU_OC_2[0]" SITE "E16" ;
+LOCATE COMP "o_PMU_OC_2[1]" SITE "F16" ;
+LOCATE COMP "o_PMU_OC_2[2]" SITE "D16" ;
+LOCATE COMP "o_PMU_OC_2[3]" SITE "G15" ;
+LOCATE COMP "o_PMU_OC_2[4]" SITE "C22" ;
+LOCATE COMP "o_PMU_OC_2[5]" SITE "D20" ;
+LOCATE COMP "o_PMU_OC_2[6]" SITE "D21" ;
+LOCATE COMP "o_PMU_OC_2[7]" SITE "D22" ;
+LOCATE COMP "o_PMU_OC_2[16]" SITE "A17" ;
+LOCATE COMP "o_PMU_OC_2[17]" SITE "A18" ;
+LOCATE COMP "o_PMU_OC_2[18]" SITE "C18" ;
+LOCATE COMP "o_PMU_OC_2[19]" SITE "D18" ;
+LOCATE COMP "o_PMU_OC_2[20]" SITE "G13" ;
+LOCATE COMP "o_PMU_OC_2[21]" SITE "F15" ;
+LOCATE COMP "o_PMU_OC_2[22]" SITE "F13" ;
+LOCATE COMP "o_PMU_OC_2[23]" SITE "G12" ;
+LOCATE COMP "o_PMU_OC_3[0]" SITE "M3" ;
+LOCATE COMP "o_PMU_OC_3[1]" SITE "R1" ;
+LOCATE COMP "o_PMU_OC_3[2]" SITE "N2" ;
+LOCATE COMP "o_PMU_OC_3[3]" SITE "N1" ;
+LOCATE COMP "o_PMU_OC_3[4]" SITE "F19" ;
+LOCATE COMP "o_PMU_OC_3[5]" SITE "E19" ;
+LOCATE COMP "o_PMU_OC_3[7]" SITE "B20" ;
+LOCATE COMP "o_PMU_OC_3[6]" SITE "C20" ;
+LOCATE COMP "o_PMU_OC_3[16]" SITE "E8" ;
+LOCATE COMP "o_PMU_OC_3[17]" SITE "E9" ;
+LOCATE COMP "o_PMU_OC_3[18]" SITE "E10" ;
+LOCATE COMP "o_PMU_OC_3[19]" SITE "D11" ;
+LOCATE COMP "o_PMU_OC_3[20]" SITE "E7" ;
+LOCATE COMP "o_PMU_OC_3[21]" SITE "D8" ;
+LOCATE COMP "o_PMU_OC_3[22]" SITE "B8" ;
+LOCATE COMP "o_PMU_OC_4[0]" SITE "A13" ;
+LOCATE COMP "o_PMU_OC_4[1]" SITE "B13" ;
+LOCATE COMP "o_PMU_OC_4[2]" SITE "B14" ;
+LOCATE COMP "o_PMU_OC_4[3]" SITE "B15" ;
+LOCATE COMP "o_PMU_OC_4[4]" SITE "B19" ;
+LOCATE COMP "o_PMU_OC_4[5]" SITE "D12" ;
+LOCATE COMP "o_PMU_OC_4[6]" SITE "E14" ;
+LOCATE COMP "o_PMU_OC_4[7]" SITE "E15" ;
+LOCATE COMP "o_PMU_OC_4[16]" SITE "C15" ;
+LOCATE COMP "o_PMU_OC_4[17]" SITE "A16" ;
+LOCATE COMP "o_PMU_OC_4[18]" SITE "B16" ;
+LOCATE COMP "o_PMU_OC_4[19]" SITE "C16" ;
+LOCATE COMP "o_PMU_OC_4[20]" SITE "E12" ;
+LOCATE COMP "o_PMU_OC_4[21]" SITE "A21" ;
+LOCATE COMP "o_PMU_OC_4[22]" SITE "B22" ;
+LOCATE COMP "o_PMU_OC_4[23]" SITE "C21" ;
+IOBUF PORT "o_PMU_OC_1[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ;
+IOBUF PORT "o_PMU_OC_1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[0]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_PMU_OC_1[16]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_PMU_OC_2[0]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_PMU_OC_2[16]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_PMU_OC_3[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[16]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_PMU_OC_4[0]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_PMU_OC_4[16]" IO_TYPE=LVCMOS33 ;
+LOCATE COMP "o_RC_RLSel[1]" SITE "M4" ;
+LOCATE COMP "o_RC_RLSel[2]" SITE "B10" ;
+LOCATE COMP "o_RC_RLSel[3]" SITE "P3" ;
+LOCATE COMP "o_RC_RLSel[4]" SITE "F5" ;
+LOCATE COMP "o_RC_RLSel[5]" SITE "G10" ;
+LOCATE COMP "o_RC_RLSel[6]" SITE "F6" ;
+LOCATE COMP "o_RC_RLSel[7]" SITE "C8" ;
+LOCATE COMP "o_RC_RLSel[8]" SITE "B7" ;
+LOCATE COMP "o_RC_RLSel[9]" SITE "F8" ;
+LOCATE COMP "o_RC_RLSel[10]" SITE "C5" ;
+LOCATE COMP "o_RC_RLSel[11]" SITE "A3" ;
+LOCATE COMP "o_RC_RLSel[12]" SITE "B11" ;
+LOCATE COMP "o_RC_RLSel[13]" SITE "A5" ;
+LOCATE COMP "o_RC_RLSel[14]" SITE "B4" ;
+LOCATE COMP "o_RC_RLSel[15]" SITE "F11" ;
+LOCATE COMP "o_RC_RLSel[16]" SITE "D9" ;
+LOCATE COMP "o_RC_RLSel[17]" SITE "N5" ;
+IOBUF PORT "o_RC_RLSel[0]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_RLSel[1]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_RLSel[2]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_RLSel[3]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_RLSel[4]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_RLSel[5]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_RLSel[6]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_RLSel[7]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_RLSel[8]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_RLSel[9]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_RLSel[10]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_RLSel[11]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_RLSel[12]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_RLSel[13]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_RLSel[14]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_RLSel[15]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_RLSel[16]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_RLSel[17]" IO_TYPE=LVCMOS33 ;
+LOCATE COMP "o_RC_LOF[0]" SITE "F3" ;
+LOCATE COMP "o_RC_LOF[1]" SITE "H4" ;
+LOCATE COMP "o_RC_LOS[0]" SITE "G4" ;
+LOCATE COMP "o_RC_LOS[1]" SITE "L6" ;
+LOCATE COMP "o_RC_RLSel[0]" SITE "M6" ;
+IOBUF PORT "o_RC_LOF[0]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_LOF[1]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_LOS[0]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_LOS[1]" IO_TYPE=LVCMOS33 ;
+LOCATE COMP "o_RC_ISel" SITE "P6" ;
+LOCATE COMP "o_RC_VSel" SITE "L7" ;
+IOBUF PORT "o_RC_VSel" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_ISel" IO_TYPE=LVCMOS33 ;
+LOCATE COMP "o_DMM_EN[16]" SITE "W11" ;
+IOBUF PORT "o_DMM_EN[16]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_DMM_EN[17]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_DMM_EN[18]" IO_TYPE=LVCMOS33 ;
+LOCATE COMP "o_DMM_EN[17]" SITE "U10" ;
+LOCATE COMP "o_DMM_EN[18]" SITE "T10" ;
+LOCATE COMP "o_RC_T27" SITE "U13" ;
+IOBUF PORT "o_RC_T27" IO_TYPE=LVCMOS33 ;
+LOCATE COMP "o_RC_T28" SITE "U12" ;
+LOCATE COMP "o_RC_T29" SITE "T12" ;
+LOCATE COMP "o_RC_T30" SITE "T11" ;
+LOCATE COMP "o_RC_T31" SITE "U11" ;
+LOCATE COMP "o_RC_T32" SITE "V11" ;
+IOBUF PORT "o_RC_T28" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T29" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T30" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T31" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T32" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_con_done" IO_TYPE=LVCMOS33 ;
diff --git a/CPLD1/NewExtIns_CPLD1.sort b/CPLD1/NewExtIns_CPLD1.sort
new file mode 100644
index 0000000..e4df8fe
--- /dev/null
+++ b/CPLD1/NewExtIns_CPLD1.sort
@@ -0,0 +1,4 @@
+/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/RelayConTop.v
+/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/BUS_Con.v
+/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/Reg_file.v
+/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/CPLD_Freq_Con.v
diff --git a/CPLD1/Reg_file.v b/CPLD1/Reg_file.v
new file mode 100644
index 0000000..f09baea
--- /dev/null
+++ b/CPLD1/Reg_file.v
@@ -0,0 +1,179 @@
+module Reg_file (
+    input i_sys_clk,
+    input i_rst_n,
+    
+    // Bus Interface
+    input i_wr_req,
+    input i_wr,
+    input [6:0] i_addr,
+    input [23:0] i_wdata,
+    
+    output [23:0] o_rdata,
+    output o_rvalid,
+    output o_busy,
+    output o_err,
+
+    // Controller Interface
+    input i_con_done,       // 1=IDLE/DONE, 0=BUSY
+    output o_exec,
+    
+    // Direct Register Outputs
+    //Freq Regs
+    output [23:0] o_freq1,
+    output [23:0] o_freq2,
+    output [23:0] o_freq3,
+    output [23:0] o_freq4,
+
+    //DC Regs
+    output [23:0] o_DC1,
+    output [23:0] o_DC2,
+    output [23:0] o_DC3,
+    output [23:0] o_DC4
+
+);
+
+    // --- Parameters ---
+    localparam REG_COUNT = 16;
+    localparam [23:0]
+        IDENT      = 24'h200000 | 12'b0001_0001_0000,            //CPLD1==1,version=1.1.0
+        STATE_INIT = 24'h800000;
+    
+    // State Machine Definition
+    localparam IDLE       = 4'd0;
+    localparam BUSY       = 4'd1;
+    localparam EXEC_ACK   = 4'd2; // Wait for controller to go BUSY (Done=0)
+    localparam EXEC_WAIT  = 4'd3; // Wait for controller to go DONE (Done=1)
+
+    // --- Internal Signals ---
+    reg [3:0] state;
+    reg [23:0] regtable [0:REG_COUNT - 1];
+    reg [23:0] rdata_reg;
+
+    reg busy_flag;
+    reg err_flag;
+    reg rvalid_flag;
+
+    integer i;
+
+    // Mapping Control Bits
+    wire exec_bit = regtable[1][0];
+    
+    always @(posedge i_sys_clk or negedge i_rst_n) begin
+        if (!i_rst_n) begin
+            for (i = 0; i < REG_COUNT; i = i + 1) begin
+                regtable[i] <= 24'h0;
+            end
+            regtable[0] <= IDENT;
+            regtable[1] <= STATE_INIT;
+            
+            rvalid_flag <= 1'b0;
+            busy_flag   <= 1'b0;
+            err_flag    <= 1'b0;
+            state       <= IDLE;
+        end
+        else begin
+            case (state)
+                IDLE: begin
+                    rvalid_flag <= 1'b0;
+                    err_flag    <= 1'b0;
+                    
+                    // Priority Check: Did we crash/reset while EXEC bit was still 1?
+                    if (exec_bit == 1'b1) begin
+                        state     <= EXEC_ACK;
+                        busy_flag <= 1'b1;
+                    end
+                    else if (i_wr_req == 1'b1) begin
+                        busy_flag <= 1'b1;
+                        state     <= BUSY;
+
+                        // Addr Sanity Check
+                        if ((i_wr && (i_addr == 'd0 || i_addr >= REG_COUNT)) || 
+                            (!i_wr && (i_addr >= REG_COUNT))) 
+                        begin
+                            err_flag <= 1'b1;
+                        end
+                    end
+                    else begin
+                        busy_flag <= 1'b0;
+                    end
+                end  
+
+                BUSY: begin
+                    if (err_flag) begin
+                        state <= IDLE;
+                    end
+                    else begin
+                        if (i_wr == 1'b1) begin // --- WRITE ---
+                            if (exec_bit == 1'b1) begin     
+                                // Cannot write if Controller is already running
+                                err_flag <= 1'b1;
+                                state    <= IDLE;
+                            end
+                            else begin
+                                regtable[i_addr] <= i_wdata;
+
+                                // Check if this write is a "Start Command"
+                                if (i_addr == 7'd1 && i_wdata[0] == 1'b1) begin
+                                    // Go to Handshake Start
+                                    state <= EXEC_ACK; 
+                                end else begin
+                                    state <= IDLE; 
+                                end
+                            end
+                        end
+                        else begin // --- READ ---
+                            rdata_reg   <= regtable[i_addr];
+                            rvalid_flag <= 1'b1;
+                            state       <= IDLE;
+                        end
+                    end
+                end
+
+                // --- EXEC PHASE 1: ACK ---
+                // Wait for Controller to register the command and pull 'done' LOW (Busy)
+                EXEC_ACK: begin
+                    busy_flag <= 1'b1;
+                    if (i_con_done == 1'b0) begin
+                        state <= EXEC_WAIT;
+                    end
+                    // Optional: Timeout counter here to prevent hanging if Controller is dead
+                end
+
+                // --- EXEC PHASE 2: WAIT ---
+                // Now wait for Controller to finish and pull 'done' HIGH (Idle/Ready)
+                EXEC_WAIT: begin
+                    busy_flag <= 1'b1;
+                    if (i_con_done == 1'b1) begin
+                        // 1. Clear the Exec bit (Auto-Clear)
+                        // 2. Set the Ready bit (Bit 23) if you wish
+                        regtable[1] <= {1'b1, regtable[1][22:1], 1'b0};
+                        
+                        busy_flag   <= 1'b0;
+                        state       <= IDLE;
+                    end
+                end
+
+                default: state <= IDLE;
+            endcase
+        end
+    end
+    
+    assign o_rvalid = rvalid_flag;
+    assign o_rdata  = rdata_reg;
+    assign o_busy   = busy_flag; 
+    assign o_err    = err_flag;
+    
+    // Output the control bit to the controller
+    // This stays HIGH during both EXEC_ACK and EXEC_WAIT
+    assign o_exec   = exec_bit;
+    
+    assign o_freq1  = regtable[2];
+    assign o_freq2  = regtable[3];
+    assign o_freq3  = regtable[4];
+    assign o_freq4  = regtable[5];
+    assign o_DC1    = regtable[6];
+    assign o_DC2    = regtable[7];
+    assign o_DC3    = regtable[8];
+    assign o_DC4    = regtable[9];
+
+endmodule
\ No newline at end of file
diff --git a/CPLD1/RelayConTop.sort b/CPLD1/RelayConTop.sort
new file mode 100644
index 0000000..e4df8fe
--- /dev/null
+++ b/CPLD1/RelayConTop.sort
@@ -0,0 +1,4 @@
+/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/RelayConTop.v
+/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/BUS_Con.v
+/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/Reg_file.v
+/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/CPLD_Freq_Con.v
diff --git a/CPLD1/RelayConTop.sym b/CPLD1/RelayConTop.sym
new file mode 100644
index 0000000..07bc9d0
Binary files /dev/null and b/CPLD1/RelayConTop.sym differ
diff --git a/CPLD1/RelayConTop.tfi b/CPLD1/RelayConTop.tfi
new file mode 100644
index 0000000..e7a4823
--- /dev/null
+++ b/CPLD1/RelayConTop.tfi
@@ -0,0 +1,103 @@
+
+
+// TOOL:     vlog2tf
+// DATE:     Fri May 15 17:23:34 2026
+ 
+// TITLE:    Lattice Semiconductor Corporation
+// MODULE:   RelayConTop
+// DESIGN:   RelayConTop
+// FILENAME: RelayConTop.tfi
+// PROJECT:  NewExtIns_CPLD1
+// VERSION:  2.0
+// NOTE: DO NOT EDIT THIS FILE
+//
+// This file is generated by the Verilog Test Fixture Declarations process and 
+// contains an I/O and instance declarations of the Verilog source file
+// you selected from the Sources in Project list.
+// Notes:
+// 1) This include file (.tfi) should be referenced by your text fixture using
+// the `include compile directive using the syntax:  `include "<file_name>.tfi"
+// 2) If your design I/O changes, rerun the process to obtain new I/O and 
+// instance declarations.
+// 3) Verilog simulations will produce errors if there are Lattice FPGA library 
+// elements in your design that require the instantiation of GSR, PUR, and TSALL
+// and they are not present in the test fixture. For more information see the 
+// How To section of online help. 
+
+
+
+// Inputs
+	reg i_sys_clk;
+	reg i_rst_n;
+	reg i_sclk;
+	reg i_mosi;
+	reg i_cs;
+	reg i_rready;
+	reg i_wvalid;
+
+
+// Outputs
+	wire o_miso;
+	wire o_rvalid;
+	wire o_wready;
+	wire o_err;
+	wire o_con_done;
+	wire [18:0] o_DMM_EN;
+	wire o_IO_RC1;
+	wire o_RC_T27;
+	wire o_RC_T28;
+	wire o_RC_T29;
+	wire o_RC_T30;
+	wire o_RC_T31;
+	wire [31:0] o_OC_1;
+	wire [31:0] o_OC_2;
+	wire [31:0] o_OC_3;
+	wire [31:0] o_OC_4;
+
+
+// Bidirs
+
+
+// Instantiate the UUT
+	RelayConTop UUT (
+		.i_sys_clk(i_sys_clk), 
+		.i_rst_n(i_rst_n), 
+		.i_sclk(i_sclk), 
+		.i_mosi(i_mosi), 
+		.i_cs(i_cs), 
+		.o_miso(o_miso), 
+		.o_rvalid(o_rvalid), 
+		.i_rready(i_rready), 
+		.i_wvalid(i_wvalid), 
+		.o_wready(o_wready), 
+		.o_err(o_err), 
+		.o_con_done(o_con_done), 
+		.o_DMM_EN(o_DMM_EN), 
+		.o_IO_RC1(o_IO_RC1), 
+		.o_RC_T27(o_RC_T27), 
+		.o_RC_T28(o_RC_T28), 
+		.o_RC_T29(o_RC_T29), 
+		.o_RC_T30(o_RC_T30), 
+		.o_RC_T31(o_RC_T31), 
+		.o_OC_1(o_OC_1), 
+		.o_OC_2(o_OC_2), 
+		.o_OC_3(o_OC_3), 
+		.o_OC_4(o_OC_4)
+	);
+
+
+// Initialize Inputs
+`ifdef auto_init
+
+	initial begin
+		i_sys_clk = 0;
+		i_rst_n = 0;
+		i_sclk = 0;
+		i_mosi = 0;
+		i_cs = 0;
+		i_rready = 0;
+		i_wvalid = 0;
+	end
+
+`endif
+
diff --git a/CPLD1/RelayConTop.v b/CPLD1/RelayConTop.v
new file mode 100644
index 0000000..1fe1182
--- /dev/null
+++ b/CPLD1/RelayConTop.v
@@ -0,0 +1,201 @@
+module RelayConTop (
+	input i_sys_clk,
+	input i_rst_n,
+	
+	input i_sclk,
+	input i_mosi,
+	input i_cs,
+	output o_miso,
+	//output o_rvalid,
+	input i_rready,
+	input i_wvalid,
+	output o_wready,
+	output o_err,
+	output o_con_done,
+    output [18:0]o_DMM_EN,
+    output o_IO_RC1,
+	output o_RC_T27,
+	output o_RC_T28,
+	output o_RC_T29,
+	output o_RC_T30,
+	output o_RC_T31,
+	output o_RC_T32,
+
+	output [17:0]o_RC_RLSel,
+	output o_RC_VSel,
+	output o_RC_ISel,
+
+	output [1:0]o_RC_LOF,					//Strange DMM_N port relay
+	output [1:0]o_RC_LOS,
+
+	output [31:0]o_PMU_OC_1,
+	output [31:0]o_PMU_OC_2,
+	output [31:0]o_PMU_OC_3,
+	output [31:0]o_PMU_OC_4
+	
+);
+	wire [3:0]OC_x01;
+	wire [3:0]OC_x17;
+	wire [5:0]RC_Tx;
+
+	wire [18:0]DMM_EN;
+	wire IO_RC1;
+
+
+	wire [23:0]r_data ;
+	wire [23:0]w_data ;
+	wire [6:0]reg_addr ;
+
+	wire cmd_valid;
+	wire reg_busy;
+	wire wr_flag;						//1=write,0=read
+	wire bus_err_flag;
+	wire reg_err_flag;
+	wire cpld_err_flag;
+
+	wire con_exec;
+	wire [23:0]freq1_relay ;
+	wire [23:0]freq2_relay ;
+	wire [23:0]freq3_relay ;
+	wire [23:0]freq4_relay ;
+
+	//DC Control Reg output
+	wire [23:0]DC_Con1 ;
+	wire [23:0]DC_Con2 ;
+	wire [23:0]DC_Con3 ;
+	wire [23:0]DC_Con4 ;
+
+	//PMU OC Control
+	wire [31:0]PMU_OC_1 ;
+	wire [31:0]PMU_OC_2 ;
+	wire [31:0]PMU_OC_3 ;
+	wire [31:0]PMU_OC_4 ;
+
+	//RL Control
+	wire [17:0]RC_RLSel ;
+
+	//DMM V Select
+	wire RC_VSel;
+	//DMM I Select
+	wire RC_ISel;
+
+	wire con_rvalid;
+
+	wire con_done;
+
+	BUS_Con BUS_Con_1(
+		.i_sys_clk(i_sys_clk),
+		.i_rst_n(i_rst_n),
+		.i_sclk(i_sclk),
+		.i_mosi(i_mosi),
+		.i_cs(i_cs),
+		.i_rvalid(con_rvalid),
+		.i_wvalid(i_wvalid),
+		.i_reg_busy(reg_busy),
+		.i_rdata(r_data),
+		.o_cmd_valid(cmd_valid),
+		.o_wr(wr_flag),
+ 		.o_miso(o_miso),
+		.o_rvalid(o_rvalid),
+		.o_wready(o_wready),
+		.o_data(w_data),
+		.o_addr(reg_addr),
+		.o_err(bus_err_flag)
+	);
+
+	Reg_file CPLD_Reg_1(
+		.i_sys_clk(i_sys_clk),
+		.i_rst_n(i_rst_n),
+		.i_wr_req(cmd_valid),
+		.i_wr(wr_flag),
+		.i_addr(reg_addr),
+		.i_wdata(w_data),
+		.i_con_done(con_done),                               	//Controller Exec Done
+		.o_freq1(freq1_relay),                            		//Freq_Slot1
+		.o_freq2(freq2_relay),                            		//Freq_Slot2
+		.o_freq3(freq3_relay),                            		//Freq_Slot3 
+		.o_freq4(freq4_relay),									//Freq_Slot4
+		.o_DC1(DC_Con1),
+		.o_DC2(DC_Con2),
+		.o_DC3(DC_Con3),
+		.o_DC4(DC_Con4),
+		.o_rvalid(con_rvalid),
+		.o_rdata(r_data),
+		.o_exec(con_exec),                                  	//Exec cmd
+		.o_busy(reg_busy),
+		.o_err(reg_err_flag)
+	);
+	
+	CPLD_Con CPLD_Con_1(
+		.i_sys_clk(i_sys_clk),
+		.i_rst_n(i_rst_n),
+		.i_con_exec(con_exec),
+		.i_freq_relay1(freq1_relay),
+		.i_freq_relay2(freq2_relay),
+		.i_freq_relay3(freq3_relay),
+		.i_freq_relay4(freq4_relay),
+		.i_DC_Con1(DC_Con1),
+		.i_DC_Con2(DC_Con2),
+		.i_DC_Con3(DC_Con3),
+		.i_DC_Con4(DC_Con4),
+		.o_con_done(con_done),
+		.o_OC_x01(OC_x01),
+  		.o_OC_x17(OC_x17),
+		.o_RC_Tx(RC_Tx),
+  		.o_DMM_EN(DMM_EN),
+		.o_PMU_OC_1(PMU_OC_1),
+		.o_PMU_OC_2(PMU_OC_2),
+		.o_PMU_OC_3(PMU_OC_3),
+		.o_PMU_OC_4(PMU_OC_4),
+    	.o_RC_VSel(RC_VSel),
+    	.o_RC_ISel(RC_ISel),
+		.o_RC_RLSel(RC_RLSel),
+  		.o_IO_RC1(IO_RC1),
+  		.o_err(cpld_err_flag)
+	);
+
+	assign o_con_done = con_done;
+	//assign o_OC_x01 = OC_x01;
+	assign o_PMU_OC_1[0] = OC_x01[0];
+	assign o_PMU_OC_2[0] = OC_x01[1];
+	assign o_PMU_OC_3[0] = OC_x01[2];
+	assign o_PMU_OC_4[0] = OC_x01[3];
+	
+	//assign o_OC_x17 = OC_x17;
+	assign o_PMU_OC_1[16] = OC_x17[0];
+	assign o_PMU_OC_2[16] = OC_x17[1];
+	assign o_PMU_OC_3[16] = OC_x17[2];
+	assign o_PMU_OC_4[16] = OC_x17[3];
+
+	assign o_PMU_OC_1[15:1] = PMU_OC_1[15:1];
+	assign o_PMU_OC_1[31:17] = PMU_OC_1[31:17];
+	
+	assign o_PMU_OC_2[15:1] = PMU_OC_2[15:1];
+	assign o_PMU_OC_2[31:17] = PMU_OC_2[31:17];
+	
+	assign o_PMU_OC_3[15:1] = PMU_OC_3[15:1];
+	assign o_PMU_OC_3[31:17] = PMU_OC_3[31:17];
+
+	assign o_PMU_OC_4[15:1] = PMU_OC_4[15:1];
+	assign o_PMU_OC_4[31:17] = PMU_OC_4[31:17];
+
+	assign o_DMM_EN = DMM_EN;
+	assign o_IO_RC1 = IO_RC1;
+
+	assign o_RC_T27 = RC_Tx[5];
+	assign o_RC_T28 = RC_Tx[4];
+	assign o_RC_T29 = RC_Tx[3];
+	assign o_RC_T30 = RC_Tx[2];
+	assign o_RC_T31 = RC_Tx[1];
+	assign o_RC_T32 = RC_Tx[0];
+
+	assign o_RC_RLSel = RC_RLSel;
+	assign o_RC_VSel = RC_VSel;
+	assign o_RC_ISel = RC_ISel;
+	
+	assign  o_RC_LOF = (RC_VSel == 1'b1)?2'b01:2'b10;						//if Measure V then close RC_LOF[0]
+	assign  o_RC_LOS = (RC_VSel == 1'b1)?2'b01:2'b10;
+	
+	assign o_err = bus_err_flag || reg_err_flag ||cpld_err_flag;
+	
+endmodule
diff --git a/CPLD1/RelayConTop_tf.v b/CPLD1/RelayConTop_tf.v
new file mode 100644
index 0000000..de3022a
--- /dev/null
+++ b/CPLD1/RelayConTop_tf.v
@@ -0,0 +1,93 @@
+
+
+// TOOL:     vlog2tf
+// DATE:     Fri May 15 17:23:27 2026
+ 
+// TITLE:    Lattice Semiconductor Corporation
+// MODULE:   RelayConTop
+// DESIGN:   RelayConTop
+// FILENAME: RelayConTop_tf.v
+// PROJECT:  NewExtIns_CPLD1
+// VERSION:  2.0
+// This file is auto generated by Diamond
+
+
+`timescale 1 ns / 1 ps
+
+// Define Module for Test Fixture
+module RelayConTop_tf();
+
+// Inputs
+    reg i_sys_clk;
+    reg i_rst_n;
+    reg i_sclk;
+    reg i_mosi;
+    reg i_cs;
+    reg i_rready;
+    reg i_wvalid;
+
+
+// Outputs
+    wire o_miso;
+    wire o_rvalid;
+    wire o_wready;
+    wire o_err;
+    wire o_con_done;
+    wire [18:0] o_DMM_EN;
+    wire o_IO_RC1;
+    wire o_RC_T27;
+    wire o_RC_T28;
+    wire o_RC_T29;
+    wire o_RC_T30;
+    wire o_RC_T31;
+    wire [31:0] o_OC_1;
+    wire [31:0] o_OC_2;
+    wire [31:0] o_OC_3;
+    wire [31:0] o_OC_4;
+
+
+// Bidirs
+
+
+// Instantiate the UUT
+// Please check and add your parameters manually
+    RelayConTop UUT (
+        .i_sys_clk(i_sys_clk), 
+        .i_rst_n(i_rst_n), 
+        .i_sclk(i_sclk), 
+        .i_mosi(i_mosi), 
+        .i_cs(i_cs), 
+        .o_miso(o_miso), 
+        .o_rvalid(o_rvalid), 
+        .i_rready(i_rready), 
+        .i_wvalid(i_wvalid), 
+        .o_wready(o_wready), 
+        .o_err(o_err), 
+        .o_con_done(o_con_done), 
+        .o_DMM_EN(o_DMM_EN), 
+        .o_IO_RC1(o_IO_RC1), 
+        .o_RC_T27(o_RC_T27), 
+        .o_RC_T28(o_RC_T28), 
+        .o_RC_T29(o_RC_T29), 
+        .o_RC_T30(o_RC_T30), 
+        .o_RC_T31(o_RC_T31), 
+        .o_OC_1(o_OC_1), 
+        .o_OC_2(o_OC_2), 
+        .o_OC_3(o_OC_3), 
+        .o_OC_4(o_OC_4)
+        );
+
+
+// Initialize Inputs
+// You can add your stimulus here
+    initial begin
+            i_sys_clk = 0;
+            i_rst_n = 0;
+            i_sclk = 0;
+            i_mosi = 0;
+            i_cs = 0;
+            i_rready = 0;
+            i_wvalid = 0;
+    end
+
+endmodule // RelayConTop_tf
\ No newline at end of file
diff --git a/CPLD1/debug.rvl b/CPLD1/debug.rvl
new file mode 100644
index 0000000..28c5395
--- /dev/null
+++ b/CPLD1/debug.rvl
@@ -0,0 +1,154 @@
+<Project ModBy="Inserter" SigType="0" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/debug.rvl" Date="2026-05-26">
+    <IP Version="1_6_042617"/>
+    <Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD1"/>
+    <Core InsertDataset="0" Insert="1" Reveal_sig="695532518" Name="RelayConTop_LA0" ID="0">
+        <Setting>
+            <Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
+            <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
+            <Capture Mode="0" MinSamplesPerTrig="8"/>
+            <Event CntEnable="0" MaxEventCnt="8"/>
+            <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_RelayConTop_LA0_net"/>
+            <DistRAM Disable="0"/>
+        </Setting>
+        <Dataset Name="Base">
+            <Trace>
+                <Sig Type="SIG" Name="BUS_Con_1/i_cs"/>
+                <Sig Type="SIG" Name="BUS_Con_1/i_mosi"/>
+                <Sig Type="SIG" Name="BUS_Con_1/i_sclk"/>
+                <Bus Name="o_DMM_EN">
+                    <Sig Type="SIG" Name="o_DMM_EN:0"/>
+                    <Sig Type="SIG" Name="o_DMM_EN:1"/>
+                    <Sig Type="SIG" Name="o_DMM_EN:2"/>
+                    <Sig Type="SIG" Name="o_DMM_EN:3"/>
+                    <Sig Type="SIG" Name="o_DMM_EN:4"/>
+                    <Sig Type="SIG" Name="o_DMM_EN:5"/>
+                    <Sig Type="SIG" Name="o_DMM_EN:6"/>
+                    <Sig Type="SIG" Name="o_DMM_EN:7"/>
+                    <Sig Type="SIG" Name="o_DMM_EN:8"/>
+                    <Sig Type="SIG" Name="o_DMM_EN:9"/>
+                    <Sig Type="SIG" Name="o_DMM_EN:10"/>
+                    <Sig Type="SIG" Name="o_DMM_EN:11"/>
+                    <Sig Type="SIG" Name="o_DMM_EN:12"/>
+                    <Sig Type="SIG" Name="o_DMM_EN:13"/>
+                    <Sig Type="SIG" Name="o_DMM_EN:14"/>
+                    <Sig Type="SIG" Name="o_DMM_EN:15"/>
+                </Bus>
+                <Sig Type="SIG" Name="o_IO_RC1"/>
+                <Sig Type="SIG" Name="BUS_Con_1/err_flag"/>
+                <Sig Type="SIG" Name="CPLD_Con_1/err_flag"/>
+                <Sig Type="SIG" Name="CPLD_Reg_1/err_flag"/>
+                <Sig Type="SIG" Name="CPLD_Con_1/i_con_exec"/>
+                <Bus Name="CPLD_Con_1/i_DC_Con1">
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:0"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:1"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:2"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:3"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:4"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:5"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:6"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:7"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:8"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:9"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:10"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:11"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:12"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:13"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:14"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:15"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:16"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:17"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:18"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:19"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:20"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:21"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:22"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:23"/>
+                </Bus>
+                <Bus Name="CPLD_Con_1/i_DC_Con2">
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:0"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:1"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:2"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:3"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:4"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:5"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:6"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:7"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:8"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:9"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:10"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:11"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:12"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:13"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:14"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:15"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:16"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:17"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:18"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:19"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:20"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:21"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:22"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:23"/>
+                </Bus>
+                <Bus Name="CPLD_Con_1/i_DC_Con3">
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:0"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:1"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:2"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:3"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:4"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:5"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:6"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:7"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:8"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:9"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:10"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:11"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:12"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:13"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:14"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:15"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:16"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:17"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:18"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:19"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:20"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:21"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:22"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:23"/>
+                </Bus>
+                <Bus Name="CPLD_Con_1/i_DC_Con4">
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:0"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:1"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:2"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:3"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:4"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:5"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:6"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:7"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:8"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:9"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:10"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:11"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:12"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:13"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:14"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:15"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:16"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:17"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:18"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:19"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:20"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:21"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:22"/>
+                    <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:23"/>
+                </Bus>
+            </Trace>
+            <Trigger>
+                <TU Serialbits="0" Type="0" ID="1" Sig="i_cs,"/>
+                <TU Serialbits="0" Type="0" ID="2" Sig="i_sclk,"/>
+                <TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
+                <TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
+            </Trigger>
+        </Dataset>
+    </Core>
+</Project>
diff --git a/CPLD1/tb_RelayConTop.sv b/CPLD1/tb_RelayConTop.sv
new file mode 100644
index 0000000..604c8f2
--- /dev/null
+++ b/CPLD1/tb_RelayConTop.sv
@@ -0,0 +1,914 @@
+//------------------------------------------------------------------------------
+//
+//  Testbench: CPLD1 - RelayConTop
+//  Project:  NewCalBoard DIG
+//  Tool:     Lattice Diamond Verilog-2001 simulator
+//  Purpose:  Verify SPI interface, register file, and relay control logic
+//            for CPLD1 (main relay controller + PMU output + DMM enable).
+//
+//  Architecture (3 sub-modules):
+//    RelayConTop
+//    - BUS_Con - SPI Mode 0 master interface (32-bit transactions)
+//    - Reg_file - 16-register file + execution FSM
+//    - CPLD_Con - Relay control logic (freq + DC/PMU decoding)
+//
+//  SPI Protocol:
+//    Frame: [WR:1][Addr:7][Data:24]  (MSB first, CPOL=0 CPHA=0)
+//    Read response: [8'h00][24-bit rdata]
+//
+//  DPS path is NOT implemented (stubbed out) - all DC tests use PMU mode.
+//
+//------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+
+`define SYS_CLK_PERIOD  20     // 50 MHz system clock
+`define SPI_CLK_PERIOD  400    // 1 MHz SPI clock (200x slower than sys clk)
+
+module tb_RelayConTop;
+
+    ////==========================================================================
+    // Signal declarations - mirrors RelayConTop pinout exactly
+    ////==========================================================================
+
+    // Clock & reset
+    reg             i_sys_clk;
+    reg             i_rst_n;
+
+    // SPI interface (Zynq PS drives these)
+    reg             i_sclk;
+    reg             i_mosi;
+    reg             i_cs;
+
+    // Flow control (from Zynq PS / SPI_Con IP)
+    reg             i_rready;
+    reg             i_wvalid;
+
+    // Status outputs (monitored by testbench)
+    wire            o_miso;
+    wire            o_rvalid;
+    wire            o_wready;
+    wire            o_err;
+    wire            o_con_done;
+
+    // Relay control outputs
+    wire            o_IO_RC1;
+    wire            o_RC_VSel;
+    wire            o_RC_ISel;
+    wire            [17:0]  o_RC_RLSel;
+    wire            [1:0]   o_RC_LOF;
+    wire            [1:0]   o_RC_LOS;
+    wire            o_RC_T27;
+    wire            o_RC_T28;
+    wire            o_RC_T29;
+    wire            o_RC_T30;
+    wire            o_RC_T31;
+    wire            o_RC_T32;
+
+    // PMU output channels (4 x 32-bit)
+    wire    [31:0]  o_PMU_OC_1;
+    wire    [31:0]  o_PMU_OC_2;
+    wire    [31:0]  o_PMU_OC_3;
+    wire    [31:0]  o_PMU_OC_4;
+
+    // DMM enable bus (19 bits)
+    wire    [18:0]  o_DMM_EN;
+
+
+    ////==========================================================================
+    // DUT instantiation - connect every pin
+    ////==========================================================================
+    RelayConTop DUT (
+        .i_sys_clk   (i_sys_clk),
+        .i_rst_n     (i_rst_n),
+        .i_sclk      (i_sclk),
+        .i_mosi      (i_mosi),
+        .i_cs        (i_cs),
+        .o_miso      (o_miso),
+        .i_rready    (i_rready),
+        .i_wvalid    (i_wvalid),
+        .o_wready    (o_wready),
+        .o_err       (o_err),
+        .o_con_done  (o_con_done),
+        .o_DMM_EN    (o_DMM_EN),
+        .o_IO_RC1    (o_IO_RC1),
+        .o_RC_T27    (o_RC_T27),
+        .o_RC_T28    (o_RC_T28),
+        .o_RC_T29    (o_RC_T29),
+        .o_RC_T30    (o_RC_T30),
+        .o_RC_T31    (o_RC_T31),
+        .o_RC_T32    (o_RC_T32),
+        .o_RC_RLSel  (o_RC_RLSel),
+        .o_RC_VSel   (o_RC_VSel),
+        .o_RC_ISel   (o_RC_ISel),
+        .o_RC_LOF    (o_RC_LOF),
+        .o_RC_LOS    (o_RC_LOS),
+        .o_PMU_OC_1  (o_PMU_OC_1),
+        .o_PMU_OC_2  (o_PMU_OC_2),
+        .o_PMU_OC_3  (o_PMU_OC_3),
+        .o_PMU_OC_4  (o_PMU_OC_4)
+    );
+
+
+    ////==========================================================================
+    // Clock generation
+    ////==========================================================================
+
+    // System clock: 50 MHz (period = 20 ns)
+    initial begin
+        i_sys_clk = 0;
+        forever #(`SYS_CLK_PERIOD / 2) i_sys_clk = ~i_sys_clk;
+    end
+
+    // SPI clock: 1 MHz (period = 400 ns)
+    initial begin
+        i_sclk = 0;
+        forever #(`SPI_CLK_PERIOD / 2) i_sclk = ~i_sclk;
+    end
+
+
+    ////==========================================================================
+    // Test statistics
+    ////==========================================================================
+    integer test_pass;
+    integer test_fail;
+    integer test_num;
+
+    initial begin
+        test_pass = 0;
+        test_fail = 0;
+        test_num  = 0;
+    end
+
+    // Helper: log a pass (Verilog-2001 compatible)
+    task tb_pass;
+        input [132:1] msg;
+        begin
+            test_pass = test_pass + 1;
+            $display("[PASS] Test %0d: %s", test_num, msg);
+        end
+    endtask
+
+    // Helper: log a fail with optional detail
+    task tb_fail;
+        input [132:1] msg;
+        input [132:1] detail;
+        begin
+            test_fail = test_fail + 1;
+            $display("[FAIL] Test %0d: %s  >> %s", test_num, msg, detail);
+        end
+    endtask
+
+    // Helper: assert a condition (Verilog-2001 compatible)
+    task tb_assert;
+        input              condition;
+        input [132:1]      msg;
+        input [132:1]      detail;
+        begin
+            test_num = test_num + 1;
+            if (condition) begin
+                tb_pass(msg);
+            end else begin
+                tb_fail(msg, detail);
+            end
+        end
+    endtask
+
+
+    ////==========================================================================
+    // SPI helper tasks
+    //
+    // SPI Mode 0 timing:
+    //   - CPOL = 0: SCLK idle LOW
+    //   - CPHA = 0: data sampled on RISING edge, shifted on FALLING edge
+    //   - MSB first, 32 bits per transaction
+    //
+    // Frame layout:  [bit31: WR] [bit30:24: Addr(7b)] [bit23:0: Data(24b)]
+    // Read response: [8'h00][24-bit rdata] shifted out on falling SCLK edges
+    //
+    // MISO is tri-stated (high-Z) when CS is HIGH.
+    ////==========================================================================
+
+    // --- spi_send: Drive a 32-bit word out through MOSI ---
+    task spi_send;
+        input [31:0] data;
+        integer      i;
+        begin
+            @(negedge i_sclk);
+            i_cs   = 1'b0;
+            @(negedge i_sclk);
+
+            for (i = 31; i >= 0; i = i - 1) begin
+                i_mosi = data[i];
+                @(posedge i_sclk);
+            end
+
+            @(negedge i_sclk);
+            i_cs   = 1'b1;
+            i_mosi = 1'b0;
+            @(negedge i_sclk);
+        end
+    endtask
+
+    // --- spi_read: Send command, capture 32-bit response on MISO ---
+    task spi_read;
+        input  [31:0]  cmd;
+        output [31:0]  rdata;
+        integer        i;
+        begin
+            @(negedge i_sclk);
+            i_cs   = 1'b0;
+            @(negedge i_sclk);
+
+            // CPLD uses sys_clk domain for internal logic. Add #1ns delay
+            // after falling edge to let CPLD update o_miso before we sample.
+            rdata = 32'b0;
+            for (i = 31; i >= 0; i = i - 1) begin
+                i_mosi = cmd[i];
+                @(posedge i_sclk);
+                @(negedge i_sclk);
+                #1;
+                rdata[i] = o_miso;
+            end
+
+            @(negedge i_sclk);
+            i_cs   = 1'b1;
+            i_mosi = 1'b0;
+            @(negedge i_sclk);
+        end
+    endtask
+
+    // --- spi_write: Send a write command (no response capture needed) ---
+    task spi_write;
+        input [31:0] data;
+        begin
+            spi_send(data);
+        end
+    endtask
+
+    // --- wait_con_done: Poll con_done for LOW->HIGH cycle ---
+    task wait_con_done;
+        input  [15:0] max_cycles;
+        output [1:0]  result;
+        integer       i;
+        begin
+            result = 2'b0;
+
+            // Phase 1: Wait for con_done to go LOW (exec started)
+            for (i = 0; i < max_cycles; i = i + 1) begin
+                #(`SYS_CLK_PERIOD);
+                if (!o_con_done) break;
+            end
+
+            // Phase 2: Wait for con_done to go HIGH (exec finished)
+            for (i = 0; i < max_cycles; i = i + 1) begin
+                #(`SYS_CLK_PERIOD);
+                if (o_con_done) begin
+                    result = 2'b1;
+                    return;
+                end
+            end
+        end
+    endtask
+
+    // --- wait_wready: Poll o_wready until HIGH ---
+    task wait_wready;
+        input  [15:0] max_cycles;
+        output [1:0]  result;
+        integer       i;
+        begin
+            result = 2'b0;
+            for (i = 0; i < max_cycles; i = i + 1) begin
+                #(`SYS_CLK_PERIOD);
+                if (o_wready) begin
+                    result = 2'b1;
+                    return;
+                end
+            end
+        end
+    endtask
+
+
+    ////==========================================================================
+    // Convenience: build SPI frame fields
+    ////==========================================================================
+    function [31:0] mk_write;
+        input [6:0] addr;
+        input [23:0] data;
+        begin
+            mk_write = {1'b1, addr, data};
+        end
+    endfunction
+
+    function [31:0] mk_read;
+        input [6:0] addr;
+        begin
+            mk_read = {1'b0, addr, 24'b0};
+        end
+    endfunction
+
+
+    ////==========================================================================
+    // Main test sequence
+    ////==========================================================================
+    initial begin
+        // Initialize all signals to safe defaults
+        i_rst_n     = 1'b0;
+        i_cs        = 1'b1;
+        i_mosi      = 1'b0;
+        i_rready    = 1'b0;
+        i_wvalid    = 1'b0;
+
+        // Hold reset for 4 system clock cycles (80 ns)
+        #(`SYS_CLK_PERIOD * 4);
+        i_rst_n = 1'b1;
+
+        // Allow CPLD internal state machines to settle
+        #(`SYS_CLK_PERIOD * 10);
+
+        $display("");
+        $display("=============================================================");
+        $display("  CPLD1 RelayConTop - Comprehensive Testbench");
+        $display("  System clock: %d MHz | SPI clock: %d MHz",
+                 1000 / `SYS_CLK_PERIOD, 1000 / `SPI_CLK_PERIOD);
+        $display("=============================================================");
+        $display("");
+
+        test_reset_behavior();
+        test_register_rw();
+        test_exec_protocol();
+        test_freq_slots();
+        test_dc_slots_pmu();
+        test_rc_tx_output();
+        test_error_conditions();
+        test_edge_cases();
+
+        print_summary();
+
+        #(`SYS_CLK_PERIOD * 20);
+        $finish;
+    end
+
+
+    ////==========================================================================
+    // Test Group 1: Reset behavior & IDENT register (ADDR 0)
+    ////==========================================================================
+    task test_reset_behavior;
+        reg [31:0] r_ident;
+        begin
+            $display("-------------------------------------------------------------");
+            $display("  Group 1: Reset behavior & IDENT register");
+            $display("-------------------------------------------------------------");
+
+            tb_assert(o_con_done === 1'b1,
+                "o_con_done is HIGH after reset (controller idle)", "");
+
+            tb_assert(o_err === 1'b0,
+                "o_err is LOW after reset", "");
+
+            tb_assert(o_wready === 1'b1,
+                "o_wready is HIGH after reset (SPI ready)", "");
+
+            // IDENT register: CPLD1=bit21, version=1.1.0 = 24'h200010
+            spi_read(mk_read(7'd0), r_ident);
+            r_ident = r_ident[23:0];
+            tb_assert(r_ident === 24'h200010,
+                "IDENT register returns 24'h200010 (CPLD1, v1.1.0)", "");
+
+            tb_assert(o_DMM_EN === 19'b0,
+                "o_DMM_EN is all zeros after reset", "");
+
+            tb_assert(o_RC_RLSel === 18'b0,
+                "o_RC_RLSel is all zeros after reset", "");
+
+            tb_assert(o_PMU_OC_1 === 32'b0 && o_PMU_OC_2 === 32'b0 &&
+                      o_PMU_OC_3 === 32'b0 && o_PMU_OC_4 === 32'b0,
+                "All PMU_OC outputs are zero after reset", "");
+
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    ////==========================================================================
+    // Test Group 2: Register read/write (ADDR 0-9)
+    ////==========================================================================
+    task test_register_rw;
+        reg [31:0] rdata;
+        begin
+            $display("");
+            $display("-------------------------------------------------------------");
+            $display("  Group 2: Register read/write (ADDR 0-9)");
+            $display("-------------------------------------------------------------");
+
+            spi_write(mk_write(7'd2, 24'h000005));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd2), rdata);
+            tb_assert(rdata === 24'h000005,
+                "Freq_Slot1 (ADDR 2) write/read back", "");
+
+            spi_write(mk_write(7'd3, 24'h003001));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd3), rdata);
+            tb_assert(rdata === 24'h003001,
+                "Freq_Slot2 (ADDR 3) write/read back", "");
+
+            spi_write(mk_write(7'd4, 24'h001040));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd4), rdata);
+            tb_assert(rdata === 24'h001040,
+                "Freq_Slot3 (ADDR 4) write/read back", "");
+
+            spi_write(mk_write(7'd5, 24'h000802));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd5), rdata);
+            tb_assert(rdata === 24'h000802,
+                "Freq_Slot4 (ADDR 5) write/read back", "");
+
+            spi_write(mk_write(7'd6, 24'h002003));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd6), rdata);
+            tb_assert(rdata === 24'h002003,
+                "DC_Slot1 (ADDR 6) write/read back (PMU mode)", "");
+
+            spi_write(mk_write(7'd7, 24'h004005));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd7), rdata);
+            tb_assert(rdata === 24'h004005,
+                "DC_Slot2 (ADDR 7) write/read back", "");
+
+            spi_write(mk_write(7'd8, 24'h006007));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd8), rdata);
+            tb_assert(rdata === 24'h006007,
+                "DC_Slot3 (ADDR 8) write/read back", "");
+
+            spi_write(mk_write(7'd9, 24'h008009));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd9), rdata);
+            tb_assert(rdata === 24'h008009,
+                "DC_Slot4 (ADDR 9) write/read back", "");
+
+            spi_read(mk_read(7'd1), rdata);
+            tb_assert(rdata === 24'h800000,
+                "STATE register (ADDR 1) default (RDY=1)", "");
+
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    ////==========================================================================
+    // Test Group 3: Execution protocol
+    ////==========================================================================
+    task test_exec_protocol;
+        reg [1:0] done_result;
+        begin
+            $display("");
+            $display("-------------------------------------------------------------");
+            $display("  Group 3: Execution protocol");
+            $display("-------------------------------------------------------------");
+
+            // Configure and trigger execution
+            spi_write(mk_write(7'd2, 24'h000005));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));  // EXEC=1
+            @(negedge i_sclk);
+
+            wait_con_done(500, done_result);
+            tb_assert(done_result === 1'b1,
+                "con_done goes HIGH after execution completes", "");
+
+            tb_assert(o_err === 1'b0,
+                "No error flag set after successful execution", "");
+
+            wait_wready(100, done_result);
+            tb_assert(done_result === 1'b1,
+                "o_wready is HIGH after execution (SPI ready)", "");
+
+            // Execute with DC_Slot1
+            spi_write(mk_write(7'd6, 24'h002003));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_result);
+            tb_assert(done_result === 1'b1,
+                "DC slot execution completes successfully", "");
+            tb_assert(o_err === 1'b0,
+                "No error after DC slot execution", "");
+
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    ////==========================================================================
+    // Test Group 4: Frequency slot decoding (all 4 slots)
+    ////==========================================================================
+    task test_freq_slots;
+        reg [1:0] done_r;
+        begin
+            $display("");
+            $display("-------------------------------------------------------------");
+            $display("  Group 4: Frequency slot decoding (all 4 slots)");
+            $display("-------------------------------------------------------------");
+
+            // Slot1 Ch5 (range 1-8): OC_x01=1, DMM_EN[0]=1
+            $display("  Slot1 Ch5 (range 1-8): OC_x01=1, DMM_EN[0]=1");
+            spi_write(mk_write(7'd2, 24'h000005));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Slot1 Ch5 exec done", "timeout");
+            tb_assert(o_RC_T27 === 1'b0, "Slot1: RC_T27 idle", "RC_T27 mismatch");
+            tb_assert(o_PMU_OC_1[0] === 1'b1, "Slot1 Ch5: PMU_OC_1[0]=1", "PMU_OC_1[0] mismatch");
+            tb_assert(o_DMM_EN[0] === 1'b1, "Slot1 Ch5: DMM_EN[0]=1", "DMM_EN[0] mismatch");
+            tb_assert(o_PMU_OC_2[0] === 1'b0, "Slot1 Ch5: PMU_OC_2[0]=0", "PMU_OC_2[0] mismatch");
+            #(`SPI_CLK_PERIOD);
+
+            // Slot1 Ch50 (range 9-72): DMM_EN[1]=1
+            // = (0<<10) | (50<<1) | 1 = 24'h000065
+            $display("  Slot1 Ch50 (range 9-72): DMM_EN[1]=1");
+            spi_write(mk_write(7'd2, 24'h000065));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Slot1 Ch50 exec done", "timeout");
+            tb_assert(o_DMM_EN[1] === 1'b1, "Slot1 Ch50: DMM_EN[1]=1", "DMM_EN[1] mismatch");
+            tb_assert(o_PMU_OC_1[0] === 1'b0, "Slot1 Ch50: PMU_OC_1[0]=0", "PMU_OC_1[0] mismatch");
+            #(`SPI_CLK_PERIOD);
+
+            // Slot1 Ch100 (range 73-136): OC_x17=1, DMM_EN[2]=1
+            // = (0<<10) | (100<<1) | 1 = 24'h0000C9
+            $display("  Slot1 Ch100 (range 73-136): OC_x17=1, DMM_EN[2]=1");
+            spi_write(mk_write(7'd2, 24'h0000C9));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Slot1 Ch100 exec done", "timeout");
+            tb_assert(o_PMU_OC_1[16] === 1'b1, "Slot1 Ch100: PMU_OC_1[16]=1", "PMU_OC_1[16] mismatch");
+            tb_assert(o_DMM_EN[2] === 1'b1, "Slot1 Ch100: DMM_EN[2]=1", "DMM_EN[2] mismatch");
+            #(`SPI_CLK_PERIOD);
+
+            // Slot1 Ch150 (range 137-200): DMM_EN[3]=1
+            // = (0<<10) | (150<<1) | 1 = 24'h00012D
+            $display("  Slot1 Ch150 (range 137-200): DMM_EN[3]=1");
+            spi_write(mk_write(7'd2, 24'h00012D));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Slot1 Ch150 exec done", "timeout");
+            tb_assert(o_DMM_EN[3] === 1'b1, "Slot1 Ch150: DMM_EN[3]=1", "DMM_EN[3] mismatch");
+            #(`SPI_CLK_PERIOD);
+
+            // Slot2 Ch5 (range 1-8): OC_x01=2, DMM_EN[4]=1
+            // = (0<<10) | (5<<1) | 1 = 24'h000006
+            $display("  Slot2 Ch5 (range 1-8): OC_x01=2, DMM_EN[4]=1");
+            spi_write(mk_write(7'd3, 24'h000006));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Slot2 Ch5 exec done", "timeout");
+            tb_assert(o_PMU_OC_2[0] === 1'b1, "Slot2 Ch5: PMU_OC_2[0]=1", "PMU_OC_2[0] mismatch");
+            tb_assert(o_DMM_EN[4] === 1'b1, "Slot2 Ch5: DMM_EN[4]=1", "DMM_EN[4] mismatch");
+            #(`SPI_CLK_PERIOD);
+
+            // Slot3 Ch100 (range 73-136): OC_x17=4, DMM_EN[10]=1
+            // = (0<<10) | (100<<1) | 1 = 24'h0000C9
+            $display("  Slot3 Ch100 (range 73-136): OC_x17=4, DMM_EN[10]=1");
+            spi_write(mk_write(7'd4, 24'h0000C9));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Slot3 Ch100 exec done", "timeout");
+            tb_assert(o_PMU_OC_3[16] === 1'b1, "Slot3 Ch100: PMU_OC_3[16]=1", "PMU_OC_3[16] mismatch");
+            tb_assert(o_DMM_EN[10] === 1'b1, "Slot3 Ch100: DMM_EN[10]=1", "DMM_EN[10] mismatch");
+            #(`SPI_CLK_PERIOD);
+
+            // Slot4 Ch50 (range 9-72): DMM_EN[5]=1
+            // = (0<<10) | (50<<1) | 1 = 24'h000065
+            $display("  Slot4 Ch50 (range 9-72): DMM_EN[5]=1");
+            spi_write(mk_write(7'd5, 24'h000065));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Slot4 Ch50 exec done", "timeout");
+            tb_assert(o_DMM_EN[5] === 1'b1, "Slot4 Ch50: DMM_EN[5]=1", "DMM_EN[5] mismatch");
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    ////==========================================================================
+    // Test Group 5: DC slot PMU mode
+    ////==========================================================================
+    task test_dc_slots_pmu;
+        reg [1:0] done_r;
+        begin
+            $display("");
+            $display("-------------------------------------------------------------");
+            $display("  Group 5: DC slot PMU mode (DPS is stubbed, not tested)");
+            $display("-------------------------------------------------------------");
+
+            // 5a. DC_Slot1: V mode, Rload=3, Ch=3, PMU
+            //     = (3<<17) | (3<<1) | 1 = 24'h060007
+            $display("  DC1: V mode, Rload=3, Ch=3, PMU");
+            spi_write(mk_write(7'd6, 24'h060007));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "DC1 V-mode exec done", "timeout");
+            tb_assert(o_RC_VSel === 1'b1, "DC1: RC_VSel=1 (V mode)", "RC_VSel mismatch");
+            tb_assert(o_RC_ISel === 1'b0, "DC1: RC_ISel=0 (V mode)", "RC_ISel mismatch");
+            tb_assert(o_RC_RLSel === 18'b100, "DC1: RC_RLSel=18'b100 (Rload=3)", "RC_RLSel mismatch");
+            tb_assert(o_PMU_OC_1[0] === 1'b1, "DC1: PMU_OC_1[0]=1 (Ch=3)", "PMU_OC_1[0] mismatch");
+            #(`SPI_CLK_PERIOD);
+
+            // 5b. DC_Slot1: I mode, Rload=1, Ch=11, PMU
+            //     = (1<<22) | (1<<17) | (11<<1) | 1 = 24'h420017
+            $display("  DC1: I mode, Rload=1, Ch=11, PMU");
+            spi_write(mk_write(7'd6, 24'h420017));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "DC1 I-mode exec done", "timeout");
+            tb_assert(o_RC_VSel === 1'b0, "DC1: RC_VSel=0 (I mode)", "RC_VSel mismatch");
+            tb_assert(o_RC_ISel === 1'b1, "DC1: RC_ISel=1 (I mode)", "RC_ISel mismatch");
+            tb_assert(o_RC_RLSel[0] === 1'b1, "DC1: RC_RLSel[0]=1 (Rload=1)", "RC_RLSel mismatch");
+            tb_assert(o_PMU_OC_1[1] === 1'b1, "DC1: PMU_OC_1[1]=1 (Ch=11)", "PMU_OC_1[1] mismatch");
+            #(`SPI_CLK_PERIOD);
+
+            // 5c. DC_Slot2: V mode, Rload=5, Ch=19, PMU
+            //     = (5<<17) | (19<<1) | 1 = 24'h0A0027
+            $display("  DC2: V mode, Rload=5, Ch=19, PMU");
+            spi_write(mk_write(7'd7, 24'h0A0027));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "DC2 V-mode exec done", "timeout");
+            tb_assert(o_RC_VSel === 1'b1, "DC2: RC_VSel=1 (V mode)", "RC_VSel mismatch");
+            tb_assert(o_PMU_OC_2[2] === 1'b1, "DC2: PMU_OC_2[2]=1 (Ch=19)", "PMU_OC_2[2] mismatch");
+            #(`SPI_CLK_PERIOD);
+
+            // 5d. DC_Slot3: V mode, Rload=10, Ch=27, PMU
+            //     = (10<<17) | (27<<1) | 1 = 24'h140037
+            $display("  DC3: V mode, Rload=10, Ch=27, PMU");
+            spi_write(mk_write(7'd8, 24'h140037));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "DC3 V-mode exec done", "timeout");
+            tb_assert(o_PMU_OC_3[3] === 1'b1, "DC3: PMU_OC_3[3]=1 (Ch=27)", "PMU_OC_3[3] mismatch");
+            #(`SPI_CLK_PERIOD);
+
+            // 5e. DC_Slot4: V mode, Rload=18, Ch=35, PMU
+            //     = (18<<17) | (35<<1) | 1 = 24'h240047
+            $display("  DC4: V mode, Rload=18, Ch=35, PMU");
+            spi_write(mk_write(7'd9, 24'h240047));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "DC4 V-mode exec done", "timeout");
+            tb_assert(o_RC_RLSel[17] === 1'b1, "DC4: RC_RLSel[17]=1 (Rload=18)", "RC_RLSel mismatch");
+            tb_assert(o_PMU_OC_4[4] === 1'b1, "DC4: PMU_OC_4[4]=1 (Ch=35)", "PMU_OC_4[4] mismatch");
+            #(`SPI_CLK_PERIOD);
+
+            // 5f. RC_LOF/LOS when RC_VSel=1 (V mode)
+            tb_assert(o_RC_LOF === 2'b01 && o_RC_LOS === 2'b01,
+                "RC_LOF/LOS=01 when RC_VSel=1", "");
+
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    ////==========================================================================
+    // Test Group 6: RC_Tx relay output (slot 4)
+    ////==========================================================================
+    task test_rc_tx_output;
+        reg [1:0] done_r;
+        begin
+            $display("");
+            $display("-------------------------------------------------------------");
+            $display("  Group 6: RC_Tx relay output (slot 4)");
+            $display("-------------------------------------------------------------");
+
+            // 6a. RC_Tx pattern: bits 17:12 = 6'b101010 (42)
+            //     = (42<<12) | (5<<1) | 1 = 24'h02A00B
+            $display("  Slot4: RC_Tx = 6'b101010");
+            spi_write(mk_write(7'd5, 24'h02A00B));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Slot4 RC_Tx exec done", "timeout");
+
+            tb_assert(o_RC_T27 === 1'b1, "RC_T27=1 (RC_Tx[5])", "RC_T27 mismatch");
+            tb_assert(o_RC_T28 === 1'b0, "RC_T28=0 (RC_Tx[4])", "RC_T28 mismatch");
+            tb_assert(o_RC_T29 === 1'b1, "RC_T29=1 (RC_Tx[3])", "RC_T29 mismatch");
+            tb_assert(o_RC_T30 === 1'b0, "RC_T30=0 (RC_Tx[2])", "RC_T30 mismatch");
+            tb_assert(o_RC_T31 === 1'b1, "RC_T31=1 (RC_Tx[1])", "RC_T31 mismatch");
+            tb_assert(o_RC_T32 === 1'b0, "RC_T32=0 (RC_Tx[0])", "RC_T32 mismatch");
+
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    ////==========================================================================
+    // Test Group 7: Error conditions
+    ////==========================================================================
+    task test_error_conditions;
+        reg [1:0] done_r;
+        reg [31:0] rdata;
+        begin
+            $display("");
+            $display("-------------------------------------------------------------");
+            $display("  Group 7: Error conditions");
+            $display("-------------------------------------------------------------");
+
+            // 7a. Short SPI transaction (16 bits)
+            $display("  Error 7a: Short SPI transaction (16 bits)");
+            i_cs = 1'b0;
+            @(negedge i_sclk);
+            @(negedge i_sclk);
+            for (integer bi = 0; bi < 16; bi = bi + 1) begin
+                i_mosi = 1'b0;
+                @(posedge i_sclk);
+                @(negedge i_sclk);
+            end
+            i_cs = 1'b1;
+            @(negedge i_sclk);
+            #(`SYS_CLK_PERIOD * 5);
+            tb_assert(o_err === 1'b1,
+                "o_err HIGH after short SPI transaction", "");
+            i_rst_n = 1'b0;
+            #(`SYS_CLK_PERIOD * 4);
+            i_rst_n = 1'b1;
+            #(`SYS_CLK_PERIOD * 4);
+            tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
+
+            // 7b. Write to IDENT register (ADDR 0, read-only)
+            $display("  Error 7b: Write to IDENT register (ADDR 0)");
+            spi_write(mk_write(7'd0, 24'hDEADBEE >> 8));
+            @(negedge i_sclk);
+            tb_assert(o_err === 1'b1,
+                "o_err HIGH after write to IDENT register", "");
+            i_rst_n = 1'b0;
+            #(`SYS_CLK_PERIOD * 4);
+            i_rst_n = 1'b1;
+            #(`SYS_CLK_PERIOD * 4);
+            tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
+
+            #(`SPI_CLK_PERIOD);
+
+            // 7c. Read out-of-bounds address (ADDR 16)
+            $display("  Error 7c: Read out-of-bounds address (ADDR 16)");
+            spi_read(mk_read(7'd16), rdata);
+            @(negedge i_sclk);
+            #(`SYS_CLK_PERIOD * 5);
+            tb_assert(o_err === 1'b1,
+                "o_err HIGH after reading ADDR 16", "");
+            i_rst_n = 1'b0;
+            #(`SYS_CLK_PERIOD * 4);
+            i_rst_n = 1'b1;
+            #(`SYS_CLK_PERIOD * 4);
+            tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
+
+            #(`SPI_CLK_PERIOD);
+
+            // 7d. Multiple slot enables (en_t > 1)
+            $display("  Error 7d: Multiple slot enable bits");
+            spi_write(mk_write(7'd2, 24'h000005));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd3, 24'h000006));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Execution completes (even with error)", "");
+            tb_assert(o_err === 1'b1,
+                "o_err HIGH with multiple slot enables", "");
+            i_rst_n = 1'b0;
+            #(`SYS_CLK_PERIOD * 4);
+            i_rst_n = 1'b1;
+            #(`SYS_CLK_PERIOD * 4);
+            tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
+
+            #(`SPI_CLK_PERIOD);
+
+            // 7e. Write to out-of-bounds address (ADDR 31)
+            $display("  Error 7e: Write to out-of-bounds address (ADDR 31)");
+            spi_write(mk_write(7'd31, 24'h123456));
+            @(negedge i_sclk);
+            #(`SYS_CLK_PERIOD * 5);
+            tb_assert(o_err === 1'b1,
+                "o_err HIGH after writing ADDR 31", "");
+            i_rst_n = 1'b0;
+            #(`SYS_CLK_PERIOD * 4);
+            i_rst_n = 1'b1;
+            #(`SYS_CLK_PERIOD * 4);
+            tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
+
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    ////==========================================================================
+    // Test Group 8: Edge cases
+    ////==========================================================================
+    task test_edge_cases;
+        reg [31:0] rdata;
+        begin
+            $display("");
+            $display("-------------------------------------------------------------");
+            $display("  Group 8: Edge cases");
+            $display("-------------------------------------------------------------");
+
+            // 8a. Brief CS pulse (too short for 32-bit)
+            $display("  Edge 8a: Brief CS pulse");
+            i_cs = 1'b0;
+            @(negedge i_sclk);
+            @(negedge i_sclk);
+            i_cs = 1'b1;
+            @(negedge i_sclk);
+            #(`SYS_CLK_PERIOD * 5);
+            tb_assert(o_err === 1'b1,
+                "o_err detected brief CS pulse", "");
+            i_rst_n = 1'b0;
+            #(`SYS_CLK_PERIOD * 4);
+            i_rst_n = 1'b1;
+            #(`SYS_CLK_PERIOD * 4);
+            tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
+
+            #(`SPI_CLK_PERIOD);
+
+            // 8b. Rapid successive SPI writes
+            $display("  Edge 8b: Rapid successive SPI writes");
+            spi_write(mk_write(7'd2, 24'h000001));
+            spi_write(mk_write(7'd3, 24'h000002));
+            spi_write(mk_write(7'd4, 24'h000003));
+            spi_write(mk_write(7'd5, 24'h000004));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd2), rdata);
+            tb_assert(rdata === 24'h000001, "Rapid write: ADDR 2 correct", "ADDR 2 mismatch");
+            spi_read(mk_read(7'd3), rdata);
+            tb_assert(rdata === 24'h000002, "Rapid write: ADDR 3 correct", "ADDR 3 mismatch");
+            spi_read(mk_read(7'd4), rdata);
+            tb_assert(rdata === 24'h000003, "Rapid write: ADDR 4 correct", "ADDR 4 mismatch");
+            spi_read(mk_read(7'd5), rdata);
+            tb_assert(rdata === 24'h000004, "Rapid write: ADDR 5 correct", "ADDR 5 mismatch");
+
+            #(`SPI_CLK_PERIOD);
+
+            // 8c. Write to reserved registers (ADDR 10-15) - no error
+            $display("  Edge 8c: Write to reserved registers");
+            spi_write(mk_write(7'd10, 24'hABCDEF));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd15, 24'h123456));
+            @(negedge i_sclk);
+            tb_assert(o_err === 1'b0, "No error writing to reserved ADDR 10 and 15",
+                "Unexpected error");
+
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    ////==========================================================================
+    // Summary
+    ////==========================================================================
+    task print_summary;
+        begin
+            $display("");
+            $display("=============================================================");
+            $display("  Test Summary");
+            $display("=============================================================");
+            $display("  Total tests: %0d", test_pass + test_fail);
+            $display("  Passed:      %0d", test_pass);
+            $display("  Failed:      %0d", test_fail);
+            $display("=============================================================");
+            if (test_fail == 0) begin
+                $display("  *** ALL TESTS PASSED ***");
+            end else begin
+                $display("  *** SOME TESTS FAILED - CHECK DESIGN ***");
+            end
+            $display("=============================================================");
+            $display("");
+        end
+    endtask
+
+endmodule
diff --git a/CPLD2/.vscode/settings.json b/CPLD2/.vscode/settings.json
new file mode 100644
index 0000000..12f91d4
--- /dev/null
+++ b/CPLD2/.vscode/settings.json
@@ -0,0 +1,3 @@
+{
+    "iis.configDir": ""
+}
\ No newline at end of file
diff --git a/CPLD2/BUS_Con.v b/CPLD2/BUS_Con.v
new file mode 100644
index 0000000..82c450f
--- /dev/null
+++ b/CPLD2/BUS_Con.v
@@ -0,0 +1,215 @@
+module BUS_Con (
+    input i_sys_clk,
+    input i_rst_n,
+    
+    // SPI Interface
+    input i_sclk,
+    input i_mosi,
+    input i_cs,
+    output o_miso,          // <-- MISO Logic added here
+    
+    // Local Interface
+    output o_rvalid,        // (Typo in original: o_rvalid)
+    input i_rvalid,         // Valid signal from Backend (Data is ready)
+    input i_wvalid,
+    output o_wready,
+    input i_reg_busy,
+    input [23:0] i_rdata,   // Data from Backend to send to Master
+    output o_wr,
+    output o_cmd_valid,
+    output [23:0] o_data,
+    output [6:0] o_addr,
+    output o_err
+);
+
+    // --- 1. Synchronization ---
+    reg [1:0] cs_sync;
+    reg [1:0] sclk_sync;
+    reg [1:0] mosi_sync;
+    
+    wire cs_active;
+    wire cs_rise;
+    wire sclk_rise; // For Sampling MOSI
+    wire sclk_fall; // For Shifting MISO
+    wire mosi_data;
+	
+
+    always @(posedge i_sys_clk) begin
+        if (!i_rst_n) begin
+            cs_sync   <= 2'b11;
+            sclk_sync <= 2'b00;
+            mosi_sync <= 2'b00;
+        end else begin
+            cs_sync   <= {cs_sync[0], i_cs};
+            sclk_sync <= {sclk_sync[0], i_sclk};
+            mosi_sync <= {mosi_sync[0], i_mosi};
+        end
+    end
+
+    assign cs_active = ~cs_sync[1]; 
+    assign cs_rise   = (!cs_sync[1] && cs_sync[0]); 
+    
+    // SPI Mode 0: Sample MOSI on Rising, Shift MISO on Falling
+    assign sclk_rise = (!sclk_sync[1] && sclk_sync[0]); 
+    assign sclk_fall = (sclk_sync[1] && !sclk_sync[0]); // Logic for MISO
+    assign mosi_data = mosi_sync[1];
+
+    // --- 2. MOSI (Receive) Logic ---
+    reg [31:0] recv_reg;
+    reg [5:0]  bit_cnt;
+    reg        data_ready;
+    reg        err_flag;
+	reg [1:0] state;
+	//
+	reg [31:0] tx_buffer;  // Holds data waiting for the next CS Low
+    reg [31:0] miso_shift; // The actual shifter
+    // Output Registers
+    reg [6:0]  addr_out;
+    reg [23:0] data_out;
+    reg        wr_out;
+    reg        cmd_valid_out;
+	
+	//
+	localparam IDLE      = 2'b00;
+    localparam CMD_SENT  = 2'b01;
+    localparam WAIT_BUSY = 2'b10;
+    localparam DONE      = 2'b11;
+    
+
+    always @(posedge i_sys_clk) begin
+        if (!i_rst_n) begin
+            recv_reg      <= 32'd0;
+            bit_cnt       <= 6'd0;
+            data_ready    <= 1'b0;
+            err_flag      <= 1'b0;
+        end 
+		else begin
+            data_ready <= 1'b0; 
+
+            if (cs_active) begin
+                if (sclk_rise) begin
+                    recv_reg <= {recv_reg[30:0], mosi_data}; 
+                    bit_cnt  <= bit_cnt + 1'b1;
+                end
+				else if (cs_rise) begin
+					if (bit_cnt == 6'd32) begin
+						data_ready <= 1'b1;
+						err_flag   <= 1'b0;
+						bit_cnt <= 6'd0;
+					end 
+					else if (bit_cnt != 0) begin
+						err_flag   <= 1'b1;
+						bit_cnt <= 6'd0;
+                        recv_reg <= 'd0;
+					end
+				end
+            end
+            if (state == DONE) begin
+                recv_reg <= 'd0;
+            end
+        end
+    end
+
+    // --- 3. MISO (Transmit) Logic ---
+    // Protocol: We shift out 32 bits. 
+    // Format: [8 bit Status/Padding] + [24 bit i_rdata]
+    
+
+    // Capture data from backend when valid
+    always @(posedge i_sys_clk) begin
+        if (!i_rst_n) begin
+            tx_buffer <= 32'd0;
+        end else begin
+            // If backend provides valid read data, store it.
+            // We pad the top 8 bits with Zeros (or you can put status flags here)
+            if (i_rvalid) begin
+                tx_buffer <= {8'h00, i_rdata}; 
+            end
+        end
+    end
+
+    // Shift data out
+    always @(posedge i_sys_clk) begin
+        if (!i_rst_n) begin
+            miso_shift <= 32'd0;
+        end else begin
+            if (!cs_active) begin
+                // Pre-load the shifter while CS is High
+                // This ensures Bit 31 is ready BEFORE the first clock edge
+                miso_shift <= tx_buffer;
+            end else begin
+                // Shift on Falling Edge (Master samples on Rising)
+                if (sclk_fall) begin
+                    miso_shift <= {miso_shift[30:0], 1'b0};
+                end
+            end
+        end
+    end
+
+    // Tri-state MISO when CS is high (optional, usually good practice)
+    // If your board doesn't need tristate, just use: assign o_miso = miso_shift[31];
+    assign o_miso = (cs_active) ? miso_shift[31] : 1'bz;
+
+    // --- 4. Register Control FSM ---
+
+    
+
+    always @(posedge i_sys_clk) begin
+        if (!i_rst_n) begin
+            state         <= IDLE;
+            cmd_valid_out <= 1'b0;
+            addr_out      <= 7'd0;
+            data_out      <= 24'd0;
+            wr_out        <= 1'b0;
+        end else begin
+            case (state)
+                IDLE: begin
+                    if (data_ready) begin
+                        addr_out      <= recv_reg[30:24];
+                        data_out      <= recv_reg[23:0];
+                        wr_out        <= recv_reg[31];
+                        
+                        if (!i_reg_busy) begin
+                            cmd_valid_out <= 1'b1;
+                            state         <= CMD_SENT;
+                        end else begin
+                            state         <= WAIT_BUSY;
+                        end
+                    end
+                end
+
+                WAIT_BUSY: begin
+                    if (!i_reg_busy) begin
+                        cmd_valid_out <= 1'b1;
+                        state         <= CMD_SENT;
+                    end
+                end
+
+                CMD_SENT: begin
+                    cmd_valid_out <= 1'b0;
+                    state         <= DONE;
+                end
+
+                DONE: begin
+                    if (!i_reg_busy) begin
+                        state <= IDLE;
+                        addr_out <= 'd0;
+                        data_out <= 'd0;
+                        wr_out <= 'd0;
+                    end
+                end
+            endcase
+        end
+    end
+
+    assign o_addr      = addr_out;
+    assign o_data      = data_out;
+    assign o_wr        = wr_out;
+    assign o_cmd_valid = cmd_valid_out;
+    assign o_err       = err_flag;
+    assign o_wready    = (state == IDLE); 
+    
+    // Pass through unused signal or hook it up if needed
+    assign o_rvalid    = i_rvalid; 
+
+endmodule
\ No newline at end of file
diff --git a/CPLD2/CPLD_Con.v b/CPLD2/CPLD_Con.v
new file mode 100644
index 0000000..1ff77a2
--- /dev/null
+++ b/CPLD2/CPLD_Con.v
@@ -0,0 +1,329 @@
+module CPLD_Con (
+    input i_sys_clk,
+    input i_rst_n,
+    input i_con_exec,
+
+// Freq Relay Control
+    input [23:0]i_freq_relay1,
+    input [23:0]i_freq_relay2,
+    input [23:0]i_freq_relay3,
+    input [23:0]i_freq_relay4,
+
+// DC related Control
+    input [23:0]i_DC_Con1,
+    input [23:0]i_DC_Con2,
+    input [23:0]i_DC_Con3,
+    input [23:0]i_DC_Con4,
+
+//Output RELAYs    
+    output [7:0]o_RC_F,           //Ref: Schematic
+    output [15:0]o_RC_S,
+    output [31:0]o_RC_T,
+    output [3:0] o_OC_x09,
+    output [3:0] o_OC_x25,
+
+    output [31:0]o_PMU_OC_1 ,
+    output [31:0]o_PMU_OC_2 ,
+    output [31:0]o_PMU_OC_3 ,
+    output [31:0]o_PMU_OC_4,
+
+//Output FLAGs
+	output o_err,
+    output o_con_done
+);
+
+    //Output Relay Reg
+    reg [3:0] OC_x09; 
+    reg [3:0] OC_x25;
+
+    //Condition Tester
+    reg [15:0]en_t ;
+    reg freq_t;
+    reg dc_t;
+
+    //Relay Reg
+    reg [7:0]relay_l1;
+    reg [15:0]relay_l2 ;
+    reg [31:0]relay_l3 ;
+
+    reg [31:0]PMU_OC_1 ;
+    reg [31:0]PMU_OC_2 ;
+    reg [31:0]PMU_OC_3 ;
+    reg [31:0]PMU_OC_4 ;
+
+    //Flags
+    reg exec_done_flag;
+    reg exec_flag;
+	
+	reg [3:0]freq_slot_flag;
+    reg [3:0]dc_slot_flag ;
+	reg err_flag;
+
+    //Counter
+    reg [15:0]delay_cnt;
+
+    wire [8:0] freq_relay1 = i_freq_relay1[9:1];
+    wire [8:0] freq_relay2 = i_freq_relay2[9:1];
+    wire [8:0] freq_relay3 = i_freq_relay3[9:1];
+    wire [8:0] freq_relay4 = i_freq_relay4[9:1];
+
+    always @(posedge i_sys_clk) begin
+        if (i_rst_n == 1'b0) begin
+            delay_cnt <= 'd0;
+        end
+        else begin
+            if (exec_flag == 1'b1) begin
+                delay_cnt <= delay_cnt + 1'd1;
+            end
+            else begin
+                delay_cnt <= 'd0;
+            end
+        end
+    end
+
+    //Function Identify
+    always @(posedge i_sys_clk) begin
+        if (i_rst_n == 1'b0) begin
+            en_t <= 'd0;
+            freq_t <= 'd0;
+            dc_t <= 'd0;
+        end
+        else begin
+            en_t <= (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) + (i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0] );
+            freq_t <= i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0];
+            dc_t <= i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0];
+        end
+    end
+    
+//  Main Controller Function
+    always @(posedge i_sys_clk) begin
+        if (i_rst_n == 1'b0) begin
+            relay_l1 <= 'd0;
+            relay_l2 <= 'd0;
+            relay_l3 <= 'd0;
+            exec_flag <= 1'b0;
+            exec_done_flag <= 1'b1;
+			freq_slot_flag <= 'd0;
+            PMU_OC_1 <= 'd0;
+            PMU_OC_2 <= 'd0;
+            PMU_OC_3 <= 'd0;
+            PMU_OC_4 <= 'd0;
+            dc_slot_flag<='d0;
+			err_flag <= 'd0;
+        end
+        else begin
+            if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin
+                //To DO: More Sanity Check?
+                if (en_t > 'd1) begin                                                   //Only ONE Enable bit should be set!
+                    err_flag <= 1'b1;
+                end
+                else begin
+                    exec_done_flag <= 'd0;
+                    exec_flag <= 1'b1;
+
+                    freq_slot_flag[0] <= i_freq_relay1[0];
+                    freq_slot_flag[1] <= i_freq_relay2[0];
+                    freq_slot_flag[2] <= i_freq_relay3[0];
+                    freq_slot_flag[3] <= i_freq_relay4[0];
+
+                    dc_slot_flag[0] <= i_DC_Con1[0];
+                    dc_slot_flag[1] <= i_DC_Con2[0];
+                    dc_slot_flag[2] <= i_DC_Con3[0];
+                    dc_slot_flag[3] <= i_DC_Con4[0];
+                end
+            end
+            else if (exec_flag == 1'b1) begin
+                //Output Relay
+                if (freq_t == 1'b1) begin
+                    case (freq_slot_flag)
+                        4'b0001: begin
+                            relay_l1 <= {'d0,i_freq_relay1[22],i_freq_relay1[23]};
+                            if (delay_cnt == 'd500) begin
+                                relay_l2 <= {'d0,i_freq_relay1[18],i_freq_relay1[19],i_freq_relay1[20],i_freq_relay1[21]};
+                            end
+                            else if (delay_cnt == 'd1000) begin
+                                relay_l3 <= {'d0,i_freq_relay1[10],i_freq_relay1[11],i_freq_relay1[12],i_freq_relay1[13],i_freq_relay1[14],i_freq_relay1[15],i_freq_relay1[16],i_freq_relay1[17]};
+                            end
+                            else if (delay_cnt == 'd1080) begin
+                                exec_flag <= 'd0;
+                                exec_done_flag <= 1'b1;
+                            end
+                            if ((freq_relay1 > 64) & (freq_relay1 < 73)) begin
+                                OC_x09 <= 4'b0001;
+                            end
+                            else if ((freq_relay1 > 192) & (freq_relay1 < 201)) begin
+                                OC_x25 <= 4'b0001;
+                            end
+                            else begin
+                                OC_x09 <= 'd0;
+                                OC_x25 <= 'd0;
+                            end
+                        end
+                        4'b0010: begin
+                            relay_l1 <= {4'd0,i_freq_relay2[22],i_freq_relay2[23],2'd0};
+                            if (delay_cnt == 'd500) begin
+                                relay_l2 <= {8'd0,i_freq_relay2[18],i_freq_relay2[19],i_freq_relay2[20],i_freq_relay2[21],4'd0};
+                            end
+                            else if (delay_cnt == 'd1000) begin
+                                relay_l3 <= {16'd0,i_freq_relay2[10],i_freq_relay2[11],i_freq_relay2[12],i_freq_relay2[13],i_freq_relay2[14],i_freq_relay2[15],i_freq_relay2[16],i_freq_relay2[17],8'd0};
+                            end
+                            else if (delay_cnt == 'd1080) begin
+                                exec_flag <= 'd0;
+                                exec_done_flag <= 1'b1;
+                            end
+                            if ((freq_relay2 > 64) & (freq_relay2 < 73)) begin
+                                OC_x09 <= 4'b0010;
+                            end
+                            else if ((freq_relay2 > 192) & (freq_relay2 < 201)) begin
+                                OC_x25 <= 4'b0010;
+                            end
+                            else begin
+                                OC_x09 <= 'd0;
+                                OC_x25 <= 'd0;
+                            end
+                        end
+                        4'b0100: begin
+                            relay_l1 <= {2'd0,i_freq_relay3[22],i_freq_relay3[23],4'd0};
+                            if (delay_cnt == 'd500) begin
+                                relay_l2 <= {4'd0,i_freq_relay3[18],i_freq_relay3[19],i_freq_relay3[20],i_freq_relay3[21],8'd0};
+                            end
+                            else if (delay_cnt == 'd1000) begin
+                                relay_l3 <= {8'd0,i_freq_relay3[12],i_freq_relay3[13],i_freq_relay3[10],i_freq_relay3[11],i_freq_relay3[16],i_freq_relay3[17],i_freq_relay3[14],i_freq_relay3[15],16'd0};
+                            end
+                            else if (delay_cnt == 'd1080) begin
+                                exec_flag <= 'd0;
+                                exec_done_flag <= 1'b1;
+                            end
+                            if ((freq_relay3 > 64) &(freq_relay3 <73)) begin
+                                OC_x09 <= 4'b0100;
+                            end
+                            else if ((freq_relay3 > 192) & (freq_relay3 < 201)) begin
+                                OC_x25 <= 4'b0100;
+                            end
+                            else begin
+                                OC_x09 <= 'd0;
+                                OC_x25 <= 'd0;
+                            end
+                        end
+                        4'b1000: begin
+                            relay_l1 <= {i_freq_relay4[22],i_freq_relay4[23],6'd0};
+                            if (delay_cnt == 'd500) begin
+                                relay_l2 <= {i_freq_relay4[18],i_freq_relay4[19],i_freq_relay4[20],i_freq_relay4[21],12'd0};
+                            end
+                            else if (delay_cnt == 'd1000) begin
+                                relay_l3 <= {i_freq_relay4[10],i_freq_relay4[11],i_freq_relay4[12],i_freq_relay4[13],i_freq_relay4[14],i_freq_relay4[15],i_freq_relay4[16],i_freq_relay4[17],24'd0};
+                            end
+                            else if (delay_cnt == 'd1080) begin
+                                exec_flag <= 'd0;
+                                exec_done_flag <= 1'b1;
+                            end
+                            if ((freq_relay4 > 64) & (freq_relay4 < 73)) begin
+                                OC_x09 <= 4'b1000;
+                            end
+                            else if ((freq_relay4 > 192) & (freq_relay4 < 201)) begin
+                                OC_x25 <= 4'b1000;
+                            end
+                            else begin
+                                OC_x09 <= 'd0;
+                                OC_x25 <= 'd0;
+                            end
+                        end
+                        default: begin 
+                            OC_x09 <= 4'b0000;
+                            OC_x25 <= 4'b0000;
+                        end
+                    endcase
+                end
+                else if (dc_t == 1'b1) begin
+                    case (dc_slot_flag)
+                        4'b0001: begin
+                            //Sanity Check
+                            if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18) || (i_DC_Con1[9:1] < 1) || (i_DC_Con1[9:1]  > 256)) begin
+                                err_flag <= 1'b1;
+                            end
+                            else begin
+                                if (i_DC_Con1[23] == 1'b0) begin                //Select PMU
+                                    PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con1[9:1]/8);
+                                end
+                                else if (i_DC_Con1[23] == 1'b1) begin       //Select DPS
+                                    
+                                end
+                            end
+                            exec_flag <= 'd0;
+                            exec_done_flag <= 1'b1;
+                        end
+                        4'b0010: begin
+                             //Sanity Check
+                            if ((i_DC_Con2[21:17] < 1) || (i_DC_Con2[21:17] > 18) || (i_DC_Con2[9:1] < 1) || (i_DC_Con2[9:1]  > 256)) begin
+                                err_flag <= 1'b1;
+                            end
+                            else begin
+                                if (i_DC_Con2[23] == 1'b0) begin                //Select PMU
+                                    PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con2[9:1]/8);
+                                end
+                                else if (i_DC_Con2[23] == 1'b1) begin       //Select DPS
+                                    
+                                end
+                            end
+                            exec_flag <= 'd0;
+                            exec_done_flag <= 1'b1;
+                        end
+                        4'b0100:begin
+                             //Sanity Check
+                            if ((i_DC_Con3[21:17] < 1) || (i_DC_Con3[21:17] > 18) || (i_DC_Con3[9:1] < 1) || (i_DC_Con3[9:1]  > 256)) begin
+                                err_flag <= 1'b1;
+                            end
+                            else begin
+                                if (i_DC_Con3[23] == 1'b0) begin                //Select PMU
+                                    PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con3[9:1]/8);
+                                end
+                                else if (i_DC_Con3[23] == 1'b1) begin       //Select DPS
+                                    
+                                end
+                            end
+                            exec_flag <= 'd0;
+                            exec_done_flag <= 1'b1;
+                        end
+                        4'b1000:begin
+                             //Sanity Check
+                            if ((i_DC_Con4[21:17] < 1) || (i_DC_Con4[21:17] > 18) || (i_DC_Con4[9:1] < 1) || (i_DC_Con4[9:1]  > 256)) begin
+                                err_flag <= 1'b1;
+                            end
+                            else begin
+                                if (i_DC_Con4[23] == 1'b0) begin                //Select PMU
+                                    PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con4[9:1]/8);
+                                end
+                                else if (i_DC_Con4[23] == 1'b1) begin       //Select DPS
+                                    
+                                end
+                            end
+                            exec_flag <= 'd0;
+                            exec_done_flag <= 1'b1;
+                        end
+                        default:begin                           // You Should NOT be HERE
+                            PMU_OC_1       <= 'd0 ;
+                            PMU_OC_2       <= 'd0 ;
+                            PMU_OC_3       <= 'd0 ;
+                            PMU_OC_4       <= 'd0 ;
+                        end
+                    endcase
+                end
+            end
+        end
+    end 
+
+    assign o_RC_F = relay_l1;
+    assign o_RC_S = relay_l2;
+    assign o_RC_T = relay_l3;
+    assign o_con_done = exec_done_flag;
+    assign o_OC_x09 = OC_x09;
+    assign o_OC_x25 = OC_x25;
+
+    assign o_PMU_OC_1 = PMU_OC_1;
+    assign o_PMU_OC_2 = PMU_OC_2;
+    assign o_PMU_OC_3 = PMU_OC_3;
+    assign o_PMU_OC_4 = PMU_OC_4;
+    
+    assign o_err = err_flag;
+
+endmodule
\ No newline at end of file
diff --git a/CPLD2/NewExtInsRelay1.sty b/CPLD2/NewExtInsRelay1.sty
new file mode 100644
index 0000000..11299b1
--- /dev/null
+++ b/CPLD2/NewExtInsRelay1.sty
@@ -0,0 +1,206 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE strategy>
+<Strategy version="1.0" predefined="0" description="" label="Strategy1">
+    <Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
+    <Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
+    <Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
+    <Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
+    <Property name="PROP_BD_EdfMemPath" value="" time="0"/>
+    <Property name="PROP_BD_ParSearchPath" value="" time="0"/>
+    <Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
+    <Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
+    <Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
+    <Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
+    <Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
+    <Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
+    <Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
+    <Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
+    <Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
+    <Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
+    <Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
+    <Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
+    <Property name="PROP_BIT_NoHeader" value="False" time="0"/>
+    <Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
+    <Property name="PROP_BIT_OutFormatBitGen_REF" value="Bit File (Binary)" time="0"/>
+    <Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
+    <Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
+    <Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
+    <Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
+    <Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
+    <Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
+    <Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
+    <Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
+    <Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
+    <Property name="PROP_LST_CarryChain" value="True" time="0"/>
+    <Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
+    <Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
+    <Property name="PROP_LST_DSPUtil" value="100" time="0"/>
+    <Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
+    <Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
+    <Property name="PROP_LST_EBRUtil" value="100" time="0"/>
+    <Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
+    <Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
+    <Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
+    <Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
+    <Property name="PROP_LST_EdfMemPath" value="" time="0"/>
+    <Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
+    <Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
+    <Property name="PROP_LST_IOInsertion" value="True" time="0"/>
+    <Property name="PROP_LST_InterFileDump" value="False" time="0"/>
+    <Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
+    <Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
+    <Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
+    <Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
+    <Property name="PROP_LST_PropagatConst" value="True" time="0"/>
+    <Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
+    <Property name="PROP_LST_ReportTrimmedUserNets" value="False" time="0"/>
+    <Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
+    <Property name="PROP_LST_ResourceShare" value="True" time="0"/>
+    <Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
+    <Property name="PROP_LST_UseLPF" value="True" time="0"/>
+    <Property name="PROP_LST_VHDL2008" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
+    <Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
+    <Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
+    <Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
+    <Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
+    <Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
+    <Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
+    <Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
+    <Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
+    <Property name="PROP_MAP_MapModArgs" value="" time="0"/>
+    <Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
+    <Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
+    <Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
+    <Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
+    <Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
+    <Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
+    <Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
+    <Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
+    <Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
+    <Property name="PROP_PARSTA_FullName" value="False" time="0"/>
+    <Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
+    <Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
+    <Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
+    <Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
+    <Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
+    <Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
+    <Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
+    <Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
+    <Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
+    <Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
+    <Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
+    <Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
+    <Property name="PROP_PAR_PARModArgs" value="" time="0"/>
+    <Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
+    <Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
+    <Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
+    <Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
+    <Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
+    <Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
+    <Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
+    <Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
+    <Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_StopZero" value="False" time="0"/>
+    <Property name="PROP_PAR_parHold" value="On" time="0"/>
+    <Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
+    <Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
+    <Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
+    <Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
+    <Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
+    <Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
+    <Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
+    <Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
+    <Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
+    <Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
+    <Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfArea" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
+    <Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
+    <Property name="PROP_SYN_EdfFrequency" value="200" time="0"/>
+    <Property name="PROP_SYN_EdfGSR" value="Auto" time="0"/>
+    <Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfNumCritPath" value="3" time="0"/>
+    <Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
+    <Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
+    <Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
+    <Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
+    <Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
+    <Property name="PROP_SYN_LibPath" value="" time="0"/>
+    <Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
+    <Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
+    <Property name="PROP_SYN_UseLPF" value="True" time="0"/>
+    <Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
+    <Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
+    <Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
+    <Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
+    <Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
+    <Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
+    <Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
+    <Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
+    <Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
+    <Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
+    <Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
+    <Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
+    <Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
+</Strategy>
diff --git a/CPLD2/NewExtIns_CPLD2.ccl b/CPLD2/NewExtIns_CPLD2.ccl
new file mode 100644
index 0000000..dcf391b
--- /dev/null
+++ b/CPLD2/NewExtIns_CPLD2.ccl
@@ -0,0 +1 @@
+VERSION=20110520
diff --git a/CPLD2/NewExtIns_CPLD2.ldf b/CPLD2/NewExtIns_CPLD2.ldf
new file mode 100644
index 0000000..f5d011c
--- /dev/null
+++ b/CPLD2/NewExtIns_CPLD2.ldf
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.2" title="NewExtIns_CPLD2" device="LCMXO2-7000HC-4FG484C" default_implementation="impl1">
+    <Options/>
+    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
+        <Options def_top="RelayConTop" top="RelayConTop"/>
+        <Source name="RelayConTop.v" type="Verilog" type_short="Verilog">
+            <Options top_module="RelayConTop"/>
+        </Source>
+        <Source name="BUS_Con.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="Reg_file.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="tb_RelayConTop.sv" type="Verilog" type_short="Verilog" syn_sim="SimOnly">
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
+        <Source name="CPLD_Con.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="NewExtIns_CPLD2.lpf" type="Logic Preference" type_short="LPF">
+            <Options/>
+        </Source>
+        <Source name="debug.rvl" type="Reveal" type_short="Reveal">
+            <Options/>
+        </Source>
+        <Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
+            <Options/>
+        </Source>
+        <Source name="tb_RelayConTop/tb_RelayConTop.spf" type="Simulation Project File" type_short="SPF">
+            <Options/>
+        </Source>
+        <Source name="untitled.rva" type="Reveal Analyzer Project File" type_short="RVA">
+            <Options/>
+        </Source>
+    </Implementation>
+    <Strategy name="Strategy1" file="NewExtInsRelay1.sty"/>
+</BaliProject>
diff --git a/CPLD2/NewExtIns_CPLD2.lpf b/CPLD2/NewExtIns_CPLD2.lpf
new file mode 100644
index 0000000..134bbe9
--- /dev/null
+++ b/CPLD2/NewExtIns_CPLD2.lpf
@@ -0,0 +1,324 @@
+rvl_alias "i_sys_clk" "i_sys_clk";
+RVL_ALIAS "i_sys_clk" "i_sys_clk"; 
+RVL_ALIAS "i_sys_clk" "i_sys_clk"; 
+RVL_ALIAS "i_sys_clk" "i_sys_clk"; 
+RVL_ALIAS "i_sys_clk" "i_sys_clk"; 
+RVL_ALIAS "i_sys_clk" "i_sys_clk"; 
+RVL_ALIAS "i_sys_clk" "i_sys_clk"; 
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+LOCATE COMP "i_sys_clk" SITE "B9" ;
+LOCATE COMP "i_rst_n" SITE "Y14" ;
+LOCATE COMP "i_sclk" SITE "AA16" ;
+LOCATE COMP "i_cs" SITE "Y15" ;
+LOCATE COMP "i_mosi" SITE "AB12" ;
+//LOCATE COMP "o_RC_T[26]" SITE "U13" ;
+//LOCATE COMP "o_RC_T[27]" SITE "U12" ;
+//LOCATE COMP "o_RC_T[28]" SITE "T12" ;
+//LOCATE COMP "o_RC_T[29]" SITE "T11" ;
+//LOCATE COMP "o_RC_T[30]" SITE "U11" ;
+//LOCATE COMP "o_RC_T[31]" SITE "V11" ;
+IOBUF PORT "i_cs" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "i_mosi" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "i_sclk" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ;
+IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_RC_F[0]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_F[1]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "i_sys_clk" DRIVE=NA IO_TYPE=LVCMOS33 SLEWRATE=NA PULLMODE=DOWN ;
+IOBUF PORT "o_RC_F[2]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_F[3]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_F[4]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_F[5]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_F[6]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_F[7]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_S[0]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_S[1]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_S[2]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_S[3]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_S[4]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_S[5]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_S[6]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_S[7]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_S[8]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_S[9]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_S[10]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_S[11]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_S[12]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_S[13]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_S[14]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_S[15]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[0]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[1]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[2]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[3]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[4]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[5]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[6]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[7]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[8]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[9]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[10]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[11]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[12]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[13]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[14]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[15]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[16]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[17]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[18]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[19]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[20]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[21]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[22]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[23]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[24]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_RC_T[25]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_err" IO_TYPE=LVCMOS33 ;
+BLOCK JTAGPATHS ;
+LOCATE COMP "o_RC_F[0]" SITE "U13" ;
+LOCATE COMP "o_RC_F[1]" SITE "U12" ;
+LOCATE COMP "o_RC_F[2]" SITE "T12" ;
+LOCATE COMP "o_RC_F[3]" SITE "T11" ;
+LOCATE COMP "o_RC_F[4]" SITE "U11" ;
+LOCATE COMP "o_RC_F[5]" SITE "V11" ;
+LOCATE COMP "o_RC_F[6]" SITE "W11" ;
+LOCATE COMP "o_RC_F[7]" SITE "U10" ;
+LOCATE COMP "o_RC_S[0]" SITE "T10" ;
+LOCATE COMP "o_RC_S[1]" SITE "W9" ;
+LOCATE COMP "o_RC_S[2]" SITE "AB2" ;
+LOCATE COMP "o_RC_S[3]" SITE "Y3" ;
+LOCATE COMP "o_RC_S[4]" SITE "AA3" ;
+LOCATE COMP "o_RC_S[5]" SITE "AB3" ;
+LOCATE COMP "o_RC_S[6]" SITE "Y4" ;
+LOCATE COMP "o_RC_S[7]" SITE "AA4" ;
+LOCATE COMP "o_RC_S[8]" SITE "Y5" ;
+LOCATE COMP "o_RC_S[9]" SITE "W6" ;
+LOCATE COMP "o_RC_S[10]" SITE "AB5" ;
+LOCATE COMP "o_RC_S[11]" SITE "AB6" ;
+LOCATE COMP "o_RC_S[12]" SITE "Y6" ;
+LOCATE COMP "o_RC_S[13]" SITE "Y7" ;
+LOCATE COMP "o_RC_S[14]" SITE "AB7" ;
+LOCATE COMP "o_RC_S[15]" SITE "AA7" ;
+LOCATE COMP "o_RC_T[0]" SITE "AA8" ;
+LOCATE COMP "o_RC_T[1]" SITE "Y10" ;
+LOCATE COMP "o_RC_T[2]" SITE "AB10" ;
+LOCATE COMP "o_RC_T[3]" SITE "AA10" ;
+LOCATE COMP "o_RC_T[4]" SITE "AA11" ;
+LOCATE COMP "o_RC_T[5]" SITE "AB11" ;
+LOCATE COMP "o_RC_T[6]" SITE "AA12" ;
+LOCATE COMP "o_RC_T[7]" SITE "AB13" ;
+LOCATE COMP "o_RC_T[8]" SITE "V8" ;
+LOCATE COMP "o_RC_T[9]" SITE "V12" ;
+LOCATE COMP "o_RC_T[10]" SITE "W12" ;
+LOCATE COMP "o_RC_T[11]" SITE "Y12" ;
+LOCATE COMP "o_RC_T[12]" SITE "V13" ;
+LOCATE COMP "o_RC_T[13]" SITE "V14" ;
+LOCATE COMP "o_RC_T[14]" SITE "V16" ;
+LOCATE COMP "o_RC_T[15]" SITE "AB17" ;
+LOCATE COMP "o_RC_T[16]" SITE "Y18" ;
+LOCATE COMP "o_RC_T[17]" SITE "AA19" ;
+LOCATE COMP "o_RC_T[18]" SITE "AB20" ;
+LOCATE COMP "o_RC_T[19]" SITE "W19" ;
+LOCATE COMP "o_RC_T[20]" SITE "W17" ;
+LOCATE COMP "o_RC_T[21]" SITE "Y17" ;
+LOCATE COMP "o_RC_T[22]" SITE "T15" ;
+LOCATE COMP "o_RC_T[23]" SITE "U15" ;
+LOCATE COMP "o_RC_T[24]" SITE "T13" ;
+LOCATE COMP "o_RC_T[25]" SITE "AA13" ;
+LOCATE COMP "o_err" SITE "AB16" ;
+IOBUF PORT "o_PMU_OC_1[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_2[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_3[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_4[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_PMU_OC_1[8]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_PMU_OC_2[8]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_PMU_OC_3[8]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_PMU_OC_4[8]" IO_TYPE=LVCMOS33 ;
+LOCATE COMP "o_PMU_OC_1[8]" SITE "D14" ;
+LOCATE COMP "o_PMU_OC_1[9]" SITE "G13" ;
+LOCATE COMP "o_PMU_OC_1[10]" SITE "C13" ;
+LOCATE COMP "o_PMU_OC_1[11]" SITE "F13" ;
+LOCATE COMP "o_PMU_OC_1[12]" SITE "C17" ;
+LOCATE COMP "o_PMU_OC_1[13]" SITE "F17" ;
+LOCATE COMP "o_PMU_OC_1[14]" SITE "D17" ;
+LOCATE COMP "o_PMU_OC_1[15]" SITE "E17" ;
+LOCATE COMP "o_PMU_OC_1[24]" SITE "N5" ;
+LOCATE COMP "o_PMU_OC_1[25]" SITE "D15" ;
+LOCATE COMP "o_PMU_OC_1[26]" SITE "P3" ;
+LOCATE COMP "o_PMU_OC_1[27]" SITE "M4" ;
+LOCATE COMP "o_PMU_OC_1[28]" SITE "R6" ;
+LOCATE COMP "o_PMU_OC_1[29]" SITE "T5" ;
+LOCATE COMP "o_PMU_OC_1[30]" SITE "P6" ;
+LOCATE COMP "o_PMU_OC_1[31]" SITE "U4" ;
+LOCATE COMP "o_PMU_OC_2[8]" SITE "C1" ;
+LOCATE COMP "o_PMU_OC_2[9]" SITE "C2" ;
+LOCATE COMP "o_PMU_OC_2[10]" SITE "C3" ;
+LOCATE COMP "o_PMU_OC_2[11]" SITE "B1" ;
+LOCATE COMP "o_PMU_OC_2[12]" SITE "H5" ;
+LOCATE COMP "o_PMU_OC_2[13]" SITE "H6" ;
+LOCATE COMP "o_PMU_OC_2[14]" SITE "H2" ;
+LOCATE COMP "o_PMU_OC_2[15]" SITE "H3" ;
+LOCATE COMP "o_PMU_OC_2[24]" SITE "T7" ;
+LOCATE COMP "o_PMU_OC_2[25]" SITE "U5" ;
+LOCATE COMP "o_PMU_OC_2[26]" SITE "W5" ;
+LOCATE COMP "o_PMU_OC_2[27]" SITE "T6" ;
+LOCATE COMP "o_PMU_OC_2[28]" SITE "E8" ;
+LOCATE COMP "o_PMU_OC_2[29]" SITE "E9" ;
+LOCATE COMP "o_PMU_OC_2[30]" SITE "E10" ;
+LOCATE COMP "o_PMU_OC_2[31]" SITE "D11" ;
+LOCATE COMP "o_PMU_OC_3[8]" SITE "A11" ;
+LOCATE COMP "o_PMU_OC_3[9]" SITE "A12" ;
+LOCATE COMP "o_PMU_OC_3[10]" SITE "B12" ;
+LOCATE COMP "o_PMU_OC_3[11]" SITE "A13" ;
+LOCATE COMP "o_PMU_OC_3[12]" SITE "B19" ;
+LOCATE COMP "o_PMU_OC_3[13]" SITE "C18" ;
+LOCATE COMP "o_PMU_OC_3[14]" SITE "A17" ;
+LOCATE COMP "o_PMU_OC_3[15]" SITE "B16" ;
+LOCATE COMP "o_PMU_OC_3[24]" SITE "B13" ;
+LOCATE COMP "o_PMU_OC_3[25]" SITE "B14" ;
+LOCATE COMP "o_PMU_OC_3[26]" SITE "B15" ;
+LOCATE COMP "o_PMU_OC_3[27]" SITE "C15" ;
+LOCATE COMP "o_PMU_OC_3[28]" SITE "G21" ;
+LOCATE COMP "o_PMU_OC_3[29]" SITE "E22" ;
+LOCATE COMP "o_PMU_OC_3[30]" SITE "E20" ;
+LOCATE COMP "o_PMU_OC_3[31]" SITE "D21" ;
+LOCATE COMP "o_PMU_OC_4[8]" SITE "G1" ;
+LOCATE COMP "o_PMU_OC_4[9]" SITE "G2" ;
+LOCATE COMP "o_PMU_OC_4[10]" SITE "G3" ;
+LOCATE COMP "o_PMU_OC_4[11]" SITE "F1" ;
+LOCATE COMP "o_PMU_OC_4[12]" SITE "C4" ;
+LOCATE COMP "o_PMU_OC_4[13]" SITE "C5" ;
+LOCATE COMP "o_PMU_OC_4[14]" SITE "G11" ;
+LOCATE COMP "o_PMU_OC_4[15]" SITE "E11" ;
+LOCATE COMP "o_PMU_OC_4[24]" SITE "E1" ;
+LOCATE COMP "o_PMU_OC_4[25]" SITE "D1" ;
+LOCATE COMP "o_PMU_OC_4[26]" SITE "E2" ;
+LOCATE COMP "o_PMU_OC_4[27]" SITE "D3" ;
+LOCATE COMP "o_PMU_OC_4[28]" SITE "C11" ;
+LOCATE COMP "o_PMU_OC_4[29]" SITE "A2" ;
+LOCATE COMP "o_PMU_OC_4[30]" SITE "B3" ;
+LOCATE COMP "o_PMU_OC_4[31]" SITE "A3" ;
+USE PRIMARY NET "i_sys_clk_c" ;
+IOBUF PORT "o_rvalid" IO_TYPE=LVCMOS33 ;
diff --git a/CPLD2/Reg_file.v b/CPLD2/Reg_file.v
new file mode 100644
index 0000000..6679d43
--- /dev/null
+++ b/CPLD2/Reg_file.v
@@ -0,0 +1,178 @@
+module Reg_file (
+    input i_sys_clk,
+    input i_rst_n,
+    
+    // Bus Interface
+    input i_wr_req,
+    input i_wr,
+    input [6:0] i_addr,
+    input [23:0] i_wdata,
+    
+    output [23:0] o_rdata,
+    output o_rvalid,
+    output o_busy,
+    output o_err,
+
+    // Controller Interface
+    input i_con_done,       // 1=IDLE/DONE, 0=BUSY
+    output o_exec,
+    
+    // Direct Register Outputs
+    output [23:0] o_freq1,
+    output [23:0] o_freq2,
+    output [23:0] o_freq3,
+    output [23:0] o_freq4,
+
+    //DC Regs
+    output [23:0] o_DC1,
+    output [23:0] o_DC2,
+    output [23:0] o_DC3,
+    output [23:0] o_DC4
+);
+
+    // --- Parameters ---
+    localparam REG_COUNT = 16;
+    localparam [23:0]
+        IDENT      = 24'h400000 | 12'b0001_0001_0000,            //CPLD2==1,version=1.1.0
+        STATE_INIT = 24'h800000;
+    
+    // State Machine Definition
+    localparam IDLE       = 4'd0;
+    localparam BUSY       = 4'd1;
+    localparam EXEC_ACK   = 4'd2; // Wait for controller to go BUSY (Done=0)
+    localparam EXEC_WAIT  = 4'd3; // Wait for controller to go DONE (Done=1)
+
+    // --- Internal Signals ---
+    reg [3:0] state;
+    reg [23:0] regtable [0:REG_COUNT - 1];
+    reg [23:0] rdata_reg;
+
+    reg busy_flag;
+    reg err_flag;
+    reg rvalid_flag;
+
+    integer i;
+
+    // Mapping Control Bits
+    wire exec_bit = regtable[1][0];
+    
+    always @(posedge i_sys_clk or negedge i_rst_n) begin
+        if (!i_rst_n) begin
+            for (i = 0; i < REG_COUNT; i = i + 1) begin
+                regtable[i] <= 24'h0;
+            end
+            regtable[0] <= IDENT;
+            regtable[1] <= STATE_INIT;
+            
+            rvalid_flag <= 1'b0;
+            busy_flag   <= 1'b0;
+            err_flag    <= 1'b0;
+            state       <= IDLE;
+        end
+        else begin
+            case (state)
+                IDLE: begin
+                    rvalid_flag <= 1'b0;
+                    err_flag    <= 1'b0;
+                    
+                    // Priority Check: Did we crash/reset while EXEC bit was still 1?
+                    if (exec_bit == 1'b1) begin
+                        state     <= EXEC_ACK;
+                        busy_flag <= 1'b1;
+                    end
+                    else if (i_wr_req == 1'b1) begin
+                        busy_flag <= 1'b1;
+                        state     <= BUSY;
+
+                        // Addr Sanity Check
+                        if ((i_wr && (i_addr == 'd0 || i_addr >= REG_COUNT)) || 
+                            (!i_wr && (i_addr >= REG_COUNT))) 
+                        begin
+                            err_flag <= 1'b1;
+                        end
+                    end
+                    else begin
+                        busy_flag <= 1'b0;
+                    end
+                end  
+
+                BUSY: begin
+                    if (err_flag) begin
+                        state <= IDLE;
+                    end
+                    else begin
+                        if (i_wr == 1'b1) begin // --- WRITE ---
+                            if (exec_bit == 1'b1) begin     
+                                // Cannot write if Controller is already running
+                                err_flag <= 1'b1;
+                                state    <= IDLE;
+                            end
+                            else begin
+                                regtable[i_addr] <= i_wdata;
+
+                                // Check if this write is a "Start Command"
+                                if (i_addr == 7'd1 && i_wdata[0] == 1'b1) begin
+                                    // Go to Handshake Start
+                                    state <= EXEC_ACK; 
+                                end else begin
+                                    state <= IDLE; 
+                                end
+                            end
+                        end
+                        else begin // --- READ ---
+                            rdata_reg   <= regtable[i_addr];
+                            rvalid_flag <= 1'b1;
+                            state       <= IDLE;
+                        end
+                    end
+                end
+
+                // --- EXEC PHASE 1: ACK ---
+                // Wait for Controller to register the command and pull 'done' LOW (Busy)
+                EXEC_ACK: begin
+                    busy_flag <= 1'b1;
+                    if (i_con_done == 1'b0) begin
+                        state <= EXEC_WAIT;
+                    end
+                    // Optional: Timeout counter here to prevent hanging if Controller is dead
+                end
+
+                // --- EXEC PHASE 2: WAIT ---
+                // Now wait for Controller to finish and pull 'done' HIGH (Idle/Ready)
+                EXEC_WAIT: begin
+                    busy_flag <= 1'b1;
+                    if (i_con_done == 1'b1) begin
+                        // 1. Clear the Exec bit (Auto-Clear)
+                        // 2. Set the Ready bit (Bit 23) if you wish
+                        regtable[1] <= {1'b1, regtable[1][22:1], 1'b0};
+                        
+                        busy_flag   <= 1'b0;
+                        state       <= IDLE;
+                    end
+                end
+
+                default: state <= IDLE;
+            endcase
+        end
+    end
+    
+    assign o_rvalid = rvalid_flag;
+    assign o_rdata  = rdata_reg;
+    assign o_busy   = busy_flag; 
+    assign o_err    = err_flag;
+    
+    // Output the control bit to the controller
+    // This stays HIGH during both EXEC_ACK and EXEC_WAIT
+    assign o_exec   = exec_bit;
+    
+    assign o_freq1  = regtable[2];
+    assign o_freq2  = regtable[3];
+    assign o_freq3  = regtable[4];
+    assign o_freq4  = regtable[5];
+    
+    assign o_DC1    = regtable[6];
+    assign o_DC2    = regtable[7];
+    assign o_DC3    = regtable[8];
+    assign o_DC4    = regtable[9];
+
+endmodule
\ No newline at end of file
diff --git a/CPLD2/RelayConTop.v b/CPLD2/RelayConTop.v
new file mode 100644
index 0000000..a20acac
--- /dev/null
+++ b/CPLD2/RelayConTop.v
@@ -0,0 +1,167 @@
+module RelayConTop (
+	input i_sys_clk,
+	input i_rst_n,
+	
+	input i_sclk,
+	input i_mosi,
+	input i_cs,
+	output o_miso,
+	output o_rvalid,
+	input i_rready,
+	input i_wvalid,
+	output o_wready,
+	output o_err,
+	output [7:0]o_RC_F,           //Ref: Schematic
+    output [15:0]o_RC_S,
+    output [25:0]o_RC_T,		  //Actually ONLY 25 pin(rest is on CPLD1)
+	//output [3:0] o_OC_x09,
+	//output [3:0] o_OC_x25,
+	output [31:0]o_PMU_OC_1 ,
+    output [31:0]o_PMU_OC_2 ,
+    output [31:0]o_PMU_OC_3 ,
+    output [31:0]o_PMU_OC_4
+);
+
+	wire [7:0] RC_F;
+	wire [15:0] RC_S;
+	wire [31:0] RC_T;
+	wire [3:0]OC_x09 ;
+	wire [3:0]OC_x25 ;
+
+	wire [23:0]r_data ;
+	wire [23:0]w_data ;
+	wire [6:0]reg_addr ;
+
+	wire cmd_valid;
+	wire reg_busy;
+	wire wr_flag;						//1=write,0=read
+	wire bus_err_flag;
+	wire reg_err_flag;
+	wire cpld_err_flag;
+
+	wire con_exec;
+	wire [23:0]freq1_relay ;
+	wire [23:0]freq2_relay ;
+	wire [23:0]freq3_relay ;
+	wire [23:0]freq4_relay ;
+
+	//DC Control Reg output
+	wire [23:0]DC_Con1 ;
+	wire [23:0]DC_Con2 ;
+	wire [23:0]DC_Con3 ;
+	wire [23:0]DC_Con4 ;
+
+	//PMU OC Control
+	wire [31:0]PMU_OC_1 ;
+	wire [31:0]PMU_OC_2 ;
+	wire [31:0]PMU_OC_3 ;
+	wire [31:0]PMU_OC_4 ;
+
+	wire con_rvalid;
+
+	wire con_done;
+
+BUS_Con BUS_Con_2(
+		.i_sys_clk(i_sys_clk),
+		.i_rst_n(i_rst_n),
+		.i_sclk(i_sclk),
+		.i_mosi(i_mosi),
+		.i_cs(i_cs),
+		.i_rvalid(con_rvalid),
+		.i_wvalid(i_wvalid),
+		.i_reg_busy(reg_busy),
+		.i_rdata(r_data),
+		.o_cmd_valid(cmd_valid),
+		.o_wr(wr_flag),
+  		.o_miso(o_miso),
+		.o_rvalid(o_rvalid),
+		.o_wready(o_wready),
+		.o_data(w_data),
+		.o_addr(reg_addr),
+		.o_err(bus_err_flag)
+	);
+
+	Reg_file CPLD_Reg_2(
+		.i_sys_clk(i_sys_clk),
+		.i_rst_n(i_rst_n),
+		.i_wr_req(cmd_valid),
+		.i_wr(wr_flag),
+		.i_addr(reg_addr),
+		.i_wdata(w_data),
+		.i_con_done(con_done),                               	//Controller Exec Done
+		.o_freq1(freq1_relay),                            		//Freq_Slot1
+		.o_freq2(freq2_relay),                            		//Freq_Slot2
+		.o_freq3(freq3_relay),                            		//Freq_Slot3 
+		.o_freq4(freq4_relay),									//Freq_Slot4
+		.o_DC1(DC_Con1),
+		.o_DC2(DC_Con2),
+		.o_DC3(DC_Con3),
+		.o_DC4(DC_Con4),
+		.o_rvalid(con_rvalid),
+		.o_rdata(r_data),
+		.o_exec(con_exec),                                  	//Exec cmd
+		.o_busy(reg_busy),
+		.o_err(reg_err_flag)
+	);
+	
+	CPLD_Con CPLD_Con_2(
+		.i_sys_clk(i_sys_clk),
+		.i_rst_n(i_rst_n),
+		.i_con_exec(con_exec),
+		.i_freq_relay1(freq1_relay),
+		.i_freq_relay2(freq2_relay),
+		.i_freq_relay3(freq3_relay),
+		.i_freq_relay4(freq4_relay),
+		.i_DC_Con1(DC_Con1),
+		.i_DC_Con2(DC_Con2),
+		.i_DC_Con3(DC_Con3),
+		.i_DC_Con4(DC_Con4),
+		.o_PMU_OC_1(PMU_OC_1),
+		.o_PMU_OC_2(PMU_OC_2),
+		.o_PMU_OC_3(PMU_OC_3),
+		.o_PMU_OC_4(PMU_OC_4),
+		.o_con_done(con_done),
+		.o_RC_F(RC_F),
+		.o_RC_S(RC_S),
+		.o_RC_T(RC_T),
+		.o_OC_x09(OC_x09),
+		.o_OC_x25(OC_x25),
+		.o_err(cpld_err_flag)
+	);
+
+
+	assign o_RC_F = RC_F;
+    assign o_RC_S = RC_S;
+    assign o_RC_T = RC_T[25:0];
+	
+	assign o_PMU_OC_1[8] = OC_x09[0];
+	assign o_PMU_OC_2[8] = OC_x09[1];
+	assign o_PMU_OC_3[8] = OC_x09[2];
+	assign o_PMU_OC_4[8] = OC_x09[3];
+
+	assign o_PMU_OC_1[24] = OC_x25[0];
+	assign o_PMU_OC_2[24] = OC_x25[1];
+	assign o_PMU_OC_3[24] = OC_x25[2];
+	assign o_PMU_OC_4[24] = OC_x25[3];
+
+	assign o_PMU_OC_1[7:0] = PMU_OC_1[7:0];
+	assign o_PMU_OC_1[23:9] = PMU_OC_1[23:8];
+	assign o_PMU_OC_1[31:25] = PMU_OC_1[31:25];
+	
+	assign o_PMU_OC_2[7:0] = PMU_OC_2[7:0];
+	assign o_PMU_OC_2[23:9] = PMU_OC_2[23:9];
+	assign o_PMU_OC_2[31:25] = PMU_OC_2[31:25];
+	
+	assign o_PMU_OC_3[7:0] = PMU_OC_3[7:0];
+	assign o_PMU_OC_3[23:9] = PMU_OC_3[23:9];
+	assign o_PMU_OC_3[31:25]= PMU_OC_3[31:25];
+
+	assign o_PMU_OC_4[7:0] = PMU_OC_4[7:0];
+	assign o_PMU_OC_4[23:9] = PMU_OC_4[23:9];
+	assign o_PMU_OC_4[31:25] = PMU_OC_4[31:25];
+
+
+	assign o_err = bus_err_flag || reg_err_flag ||  cpld_err_flag;
+	
+	
+endmodule
diff --git a/CPLD2/debug.rvl b/CPLD2/debug.rvl
new file mode 100644
index 0000000..68a0c4b
--- /dev/null
+++ b/CPLD2/debug.rvl
@@ -0,0 +1,68 @@
+<Project ModBy="Inserter" SigType="0" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD2/debug.rvl" Date="2026-05-26">
+    <IP Version="1_6_042617"/>
+    <Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD2"/>
+    <Core InsertDataset="0" Insert="1" Reveal_sig="695532641" Name="RelayConTop_LA0" ID="0">
+        <Setting>
+            <Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
+            <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
+            <Capture Mode="0" MinSamplesPerTrig="8"/>
+            <Event CntEnable="0" MaxEventCnt="8"/>
+            <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_RelayConTop_LA0_net"/>
+            <DistRAM Disable="0"/>
+        </Setting>
+        <Dataset Name="Base">
+            <Trace>
+                <Sig Type="SIG" Name="i_rst_n"/>
+                <Sig Type="SIG" Name="BUS_Con_2/i_cs"/>
+                <Sig Type="SIG" Name="BUS_Con_2/i_sclk"/>
+                <Sig Type="SIG" Name="BUS_Con_2/i_mosi"/>
+                <Sig Type="SIG" Name="BUS_Con_2/i_reg_busy"/>
+                <Sig Type="SIG" Name="CPLD_Reg_2/o_exec"/>
+                <Bus Name="RC_T">
+                    <Sig Type="SIG" Name="RC_T:0"/>
+                    <Sig Type="SIG" Name="RC_T:1"/>
+                    <Sig Type="SIG" Name="RC_T:2"/>
+                    <Sig Type="SIG" Name="RC_T:3"/>
+                    <Sig Type="SIG" Name="RC_T:4"/>
+                    <Sig Type="SIG" Name="RC_T:5"/>
+                    <Sig Type="SIG" Name="RC_T:6"/>
+                    <Sig Type="SIG" Name="RC_T:7"/>
+                    <Sig Type="SIG" Name="RC_T:8"/>
+                    <Sig Type="SIG" Name="RC_T:9"/>
+                    <Sig Type="SIG" Name="RC_T:10"/>
+                    <Sig Type="SIG" Name="RC_T:11"/>
+                    <Sig Type="SIG" Name="RC_T:12"/>
+                    <Sig Type="SIG" Name="RC_T:13"/>
+                    <Sig Type="SIG" Name="RC_T:14"/>
+                    <Sig Type="SIG" Name="RC_T:15"/>
+                    <Sig Type="SIG" Name="RC_T:16"/>
+                    <Sig Type="SIG" Name="RC_T:17"/>
+                    <Sig Type="SIG" Name="RC_T:18"/>
+                    <Sig Type="SIG" Name="RC_T:19"/>
+                    <Sig Type="SIG" Name="RC_T:20"/>
+                    <Sig Type="SIG" Name="RC_T:21"/>
+                    <Sig Type="SIG" Name="RC_T:22"/>
+                    <Sig Type="SIG" Name="RC_T:23"/>
+                    <Sig Type="SIG" Name="RC_T:24"/>
+                    <Sig Type="SIG" Name="RC_T:25"/>
+                    <Sig Type="SIG" Name="RC_T:26"/>
+                    <Sig Type="SIG" Name="RC_T:27"/>
+                    <Sig Type="SIG" Name="RC_T:28"/>
+                    <Sig Type="SIG" Name="RC_T:29"/>
+                    <Sig Type="SIG" Name="RC_T:30"/>
+                    <Sig Type="SIG" Name="RC_T:31"/>
+                </Bus>
+                <Sig Type="SIG" Name="BUS_Con_2/err_flag"/>
+                <Sig Type="SIG" Name="CPLD_Con_2/err_flag"/>
+                <Sig Type="SIG" Name="CPLD_Reg_2/err_flag"/>
+                <Sig Type="SIG" Name="CPLD_Con_2/i_con_exec"/>
+            </Trace>
+            <Trigger>
+                <TU Serialbits="0" Type="0" ID="1" Sig="i_cs,"/>
+                <TU Serialbits="0" Type="0" ID="2" Sig="i_rst_n,"/>
+                <TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
+                <TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
+            </Trigger>
+        </Dataset>
+    </Core>
+</Project>
diff --git a/CPLD2/tb_RelayConTop.sv b/CPLD2/tb_RelayConTop.sv
new file mode 100644
index 0000000..6bb8c21
--- /dev/null
+++ b/CPLD2/tb_RelayConTop.sv
@@ -0,0 +1,964 @@
+//------------------------------------------------------------------------------
+//
+//  Testbench: CPLD2 - RelayConTop
+//  Project:  NewCalBoard DIG
+//  Tool:     Lattice Diamond Verilog-2001 simulator
+//  Purpose:  Verify SPI interface, register file, and relay control logic
+//            for CPLD2 (RC_F/RC_S/RC_T relay control + OC channels + PMU_OC).
+//
+//  CPLD2-specific:
+//    - Outputs: RC_F[7:0], RC_S[15:0], RC_T[25:0], OC_x09[3:0], OC_x25[3:0]
+//    - PMU_OC_1-4[31:0] (from OC_x09/OC_x25 mapping)
+//    - CPLD_Con handles freq relays only (DC slots are stubs)
+//    - Signal names: i_wvaild (typo), i_rvaild (typo)
+//
+//  Architecture (3 sub-modules):
+//    RelayConTop
+//    - BUS_Con - SPI Mode 0 master interface (32-bit transactions)
+//    - Reg_file - 16-register file + execution FSM
+//    - CPLD_Con - Freq relay control logic (no DC handling)
+//
+//  SPI Protocol:
+//    Frame: [WR:1][Addr:7][Data:24]  (MSB first, CPOL=0 CPHA=0)
+//    Read response: [8'h00][24-bit rdata]
+//
+//------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+
+`define SYS_CLK_PERIOD  20     // 50 MHz system clock
+`define SPI_CLK_PERIOD  400    // 1 MHz SPI clock (200x slower than sys clk)
+
+module tb_RelayConTop;
+
+    //==========================================================================
+    // Signal declarations - mirrors CPLD2 RelayConTop pinout
+    //==========================================================================
+
+    // Clock & reset
+    reg             i_sys_clk;
+    reg             i_rst_n;
+
+    // SPI interface (Zynq PS drives these)
+    reg             i_sclk;
+    reg             i_mosi;
+    reg             i_cs;
+
+    // Flow control (CPLD2 uses typo names: i_wvaild, i_rvaild)
+    reg             i_rready;
+    reg             i_wvaild;
+
+    // Status outputs (monitored by testbench)
+    // Note: CPLD2 does NOT expose o_con_done as a top-level output
+    wire            o_miso;
+    wire            o_rvalid;
+    wire            o_wready;
+    wire            o_err;
+
+    // Relay control outputs (CPLD2 specific)
+    wire    [7:0]   o_RC_F;       // RC_F relays (2 bits used per slot)
+    wire    [15:0]  o_RC_S;       // RC_S relays (4 bits used per slot)
+    wire    [25:0]  o_RC_T;       // RC_T relays (8 bits used per slot, only 26 bits)
+
+    // OC channel selectors
+    wire    [3:0]   o_OC_x09;     // OC channel selector (range 65-72)
+    wire    [3:0]   o_OC_x25;     // OC channel selector (range 193-200)
+
+    // PMU output channels (4 x 32-bit, mapped from OC_x09/OC_x25)
+    wire    [31:0]  o_PMU_OC_1;
+    wire    [31:0]  o_PMU_OC_2;
+    wire    [31:0]  o_PMU_OC_3;
+    wire    [31:0]  o_PMU_OC_4;
+
+
+    //==========================================================================
+    // DUT instantiation - CPLD2 specific pin names
+    // Note: CPLD2 does NOT expose o_con_done as a top-level output
+    //==========================================================================
+    RelayConTop DUT (
+        .i_sys_clk  (i_sys_clk),
+        .i_rst_n    (i_rst_n),
+        .i_sclk     (i_sclk),
+        .i_mosi     (i_mosi),
+        .i_cs       (i_cs),
+        .o_miso     (o_miso),
+        .o_rvalid   (o_rvalid),
+        .i_rready   (i_rready),
+        .i_wvaild   (i_wvaild),       // CPLD2 typo: wvaild
+        .o_wready   (o_wready),
+        .o_err      (o_err),
+        .o_RC_F     (o_RC_F),
+        .o_RC_S     (o_RC_S),
+        .o_RC_T     (o_RC_T),
+        .o_PMU_OC_1 (o_PMU_OC_1),
+        .o_PMU_OC_2 (o_PMU_OC_2),
+        .o_PMU_OC_3 (o_PMU_OC_3),
+        .o_PMU_OC_4 (o_PMU_OC_4)
+    );
+
+
+    //==========================================================================
+    // Clock generation
+    //==========================================================================
+
+    // System clock: 50 MHz (period = 20 ns)
+    initial begin
+        i_sys_clk = 0;
+        forever #(`SYS_CLK_PERIOD / 2) i_sys_clk = ~i_sys_clk;
+    end
+
+    // SPI clock: 1 MHz (period = 400 ns)
+    initial begin
+        i_sclk = 0;
+        forever #(`SPI_CLK_PERIOD / 2) i_sclk = ~i_sclk;
+    end
+
+
+    //==========================================================================
+    // Test statistics
+    //==========================================================================
+    integer test_pass;
+    integer test_fail;
+    integer test_num;
+
+    initial begin
+        test_pass = 0;
+        test_fail = 0;
+        test_num  = 0;
+    end
+
+    // Helper: log a pass
+    task tb_pass;
+        input string msg;
+        begin
+            test_pass = test_pass + 1;
+            $display("[PASS] Test %0d: %s", test_num, msg);
+        end
+    endtask
+
+    // Helper: log a fail with optional detail
+    task tb_fail;
+        input string msg;
+        input string detail;
+        begin
+            test_fail = test_fail + 1;
+            $display("[FAIL] Test %0d: %s  >> %s", test_num, msg, detail);
+        end
+    endtask
+
+    // Helper: assert a condition
+    task tb_assert;
+        input              condition;
+        input string       msg;
+        input string       detail;
+        begin
+            test_num = test_num + 1;
+            if (condition) begin
+                tb_pass(msg);
+            end else begin
+                tb_fail(msg, detail);
+            end
+        end
+    endtask
+
+
+    //==========================================================================
+    // SPI helper tasks
+    //
+    // SPI Mode 0 timing:
+    //   - CPOL = 0: SCLK idle LOW
+    //   - CPHA = 0: data sampled on RISING edge, shifted on FALLING edge
+    //   - MSB first, 32 bits per transaction
+    //
+    // Frame layout:  [bit31: WR] [bit30:24: Addr(7b)] [bit23:0: Data(24b)]
+    // Read response: [8'h00][24-bit rdata] shifted out on falling SCLK edges
+    //
+    // MISO is tri-stated (high-Z) when CS is HIGH.
+    //==========================================================================
+
+    // --- spi_send: Drive a 32-bit word out through MOSI ---
+    task spi_send;
+        input [31:0] data;
+        integer      i;
+        begin
+            @(negedge i_sclk);
+            i_cs   = 1'b0;
+            @(negedge i_sclk);
+
+            for (i = 31; i >= 0; i = i - 1) begin
+                i_mosi = data[i];
+                @(posedge i_sclk);
+            end
+
+            @(negedge i_sclk);
+            i_cs   = 1'b1;
+            i_mosi = 1'b0;
+            @(negedge i_sclk);
+        end
+    endtask
+
+    // --- spi_read: Send command, capture 32-bit response on MISO ---
+    task spi_read;
+        input  [31:0]  cmd;
+        output [31:0]  rdata;
+        integer        i;
+        begin
+            @(negedge i_sclk);
+            i_cs   = 1'b0;
+            @(negedge i_sclk);
+
+            rdata = 32'b0;
+            for (i = 31; i >= 0; i = i - 1) begin
+                i_mosi = cmd[i];
+                @(posedge i_sclk);
+                @(negedge i_sclk);
+                #1;
+                rdata[i] = o_miso;
+            end
+
+            @(negedge i_sclk);
+            i_cs   = 1'b1;
+            i_mosi = 1'b0;
+            @(negedge i_sclk);
+        end
+    endtask
+
+    // --- spi_write: Send a write command (no response capture needed) ---
+    task spi_write;
+        input [31:0] data;
+        begin
+            spi_send(data);
+        end
+    endtask
+
+    // --- wait_con_done: Poll o_wready for HIGH (CPLD2 doesn't expose con_done)
+    // When execution completes, the SPI interface becomes ready again (o_wready=1)
+    task wait_con_done;
+        input  [15:0] max_cycles;
+        output [1:0]  result;
+        integer       i;
+        begin
+            result = 2'b0;
+
+            // Wait for o_wready to go HIGH (SPI interface ready after execution)
+            for (i = 0; i < max_cycles; i = i + 1) begin
+                #(`SYS_CLK_PERIOD);
+                if (o_wready) begin
+                    result = 2'b1;
+                    return;
+                end
+            end
+        end
+    endtask
+
+    // --- wait_wready: Poll o_wready until HIGH ---
+    task wait_wready;
+        input  [15:0] max_cycles;
+        output [1:0]  result;
+        integer       i;
+        begin
+            result = 2'b0;
+            for (i = 0; i < max_cycles; i = i + 1) begin
+                #(`SYS_CLK_PERIOD);
+                if (o_wready) begin
+                    result = 2'b1;
+                    return;
+                end
+            end
+        end
+    endtask
+
+
+    //==========================================================================
+    // Convenience: build SPI frame fields
+    //==========================================================================
+    function [31:0] mk_write;
+        input [6:0] addr;
+        input [23:0] data;
+        begin
+            mk_write = {1'b1, addr, data};
+        end
+    endfunction
+
+    function [31:0] mk_read;
+        input [6:0] addr;
+        begin
+            mk_read = {1'b0, addr, 24'b0};
+        end
+    endfunction
+
+
+    //==========================================================================
+    // Main test sequence
+    //==========================================================================
+    initial begin
+        // Initialize all signals to safe defaults
+        i_rst_n     = 1'b0;
+        i_cs        = 1'b1;
+        i_mosi      = 1'b0;
+        i_rready    = 1'b0;
+        i_wvaild    = 1'b0;
+
+        // Hold reset for 4 system clock cycles (80 ns)
+        #(`SYS_CLK_PERIOD * 4);
+        i_rst_n = 1'b1;
+
+        // Allow CPLD internal state machines to settle
+        #(`SYS_CLK_PERIOD * 10);
+
+        $display("");
+        $display("=============================================================");
+        $display("  CPLD2 RelayConTop - Comprehensive Testbench");
+        $display("  System clock: %d MHz | SPI clock: %d MHz",
+                 1000 / `SYS_CLK_PERIOD, 1000 / `SPI_CLK_PERIOD);
+        $display("  Outputs: RC_F[7:0], RC_S[15:0], RC_T[25:0], OC_x09/25, PMU_OC[4x32]");
+        $display("=============================================================");
+        $display("");
+
+        test_reset_behavior();
+        test_register_rw();
+        test_exec_protocol();
+        test_freq_slots();
+        test_rc_relay_outputs();
+        test_dc_stub_behavior();
+        test_error_conditions();
+        test_edge_cases();
+
+        print_summary();
+
+        #(`SYS_CLK_PERIOD * 20);
+        $finish;
+    end
+
+
+    //==========================================================================
+    // Test Group 1: Reset behavior & IDENT register (ADDR 0)
+    //==========================================================================
+    task test_reset_behavior;
+        reg [31:0] r_ident;
+        begin
+            $display("-------------------------------------------------------------");
+            $display("  Group 1: Reset behavior & IDENT register");
+            $display("-------------------------------------------------------------");
+
+            tb_assert(o_wready === 1'b1,
+                "o_wready is HIGH after reset (SPI ready, controller idle)", "");
+
+            tb_assert(o_err === 1'b0,
+                "o_err is LOW after reset", "");
+
+            tb_assert(o_wready === 1'b1,
+                "o_wready is HIGH after reset (SPI ready)", "");
+
+            // IDENT register: CPLD2=bit22, version=1.1.0 = 24'h400010
+            spi_read(mk_read(7'd0), r_ident);
+            r_ident = r_ident[23:0];
+            tb_assert(r_ident === 24'h400010,
+                "IDENT register returns 24'h400010 (CPLD2, v1.1.0)", "");
+
+            // All relay outputs should be zero after reset
+            tb_assert(o_RC_F === 8'b0,
+                "o_RC_F is all zeros after reset", "");
+
+            tb_assert(o_RC_S === 16'b0,
+                "o_RC_S is all zeros after reset", "");
+
+            tb_assert(o_RC_T[25:0] === 26'b0,
+                "o_RC_T[25:0] is all zeros after reset", "");
+
+            tb_assert(o_OC_x09 === 4'b0,
+                "o_OC_x09 is all zeros after reset", "");
+
+            tb_assert(o_OC_x25 === 4'b0,
+                "o_OC_x25 is all zeros after reset", "");
+
+            tb_assert(o_PMU_OC_1 === 32'b0 && o_PMU_OC_2 === 32'b0 &&
+                      o_PMU_OC_3 === 32'b0 && o_PMU_OC_4 === 32'b0,
+                "All PMU_OC outputs are zero after reset", "");
+
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    //==========================================================================
+    // Test Group 2: Register read/write (ADDR 0-9)
+    //==========================================================================
+    task test_register_rw;
+        reg [31:0] rdata;
+        begin
+            $display("");
+            $display("-------------------------------------------------------------");
+            $display("  Group 2: Register read/write (ADDR 0-9)");
+            $display("-------------------------------------------------------------");
+
+            spi_write(mk_write(7'd2, 24'h000005));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd2), rdata);
+            tb_assert(rdata === 24'h000005,
+                "Freq_Slot1 (ADDR 2) write/read back", "");
+
+            spi_write(mk_write(7'd3, 24'h003001));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd3), rdata);
+            tb_assert(rdata === 24'h003001,
+                "Freq_Slot2 (ADDR 3) write/read back", "");
+
+            spi_write(mk_write(7'd4, 24'h001040));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd4), rdata);
+            tb_assert(rdata === 24'h001040,
+                "Freq_Slot3 (ADDR 4) write/read back", "");
+
+            spi_write(mk_write(7'd5, 24'h000802));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd5), rdata);
+            tb_assert(rdata === 24'h000802,
+                "Freq_Slot4 (ADDR 5) write/read back", "");
+
+            spi_write(mk_write(7'd6, 24'h002003));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd6), rdata);
+            tb_assert(rdata === 24'h002003,
+                "DC_Slot1 (ADDR 6) write/read back", "");
+
+            spi_write(mk_write(7'd7, 24'h004005));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd7), rdata);
+            tb_assert(rdata === 24'h004005,
+                "DC_Slot2 (ADDR 7) write/read back", "");
+
+            spi_write(mk_write(7'd8, 24'h006007));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd8), rdata);
+            tb_assert(rdata === 24'h006007,
+                "DC_Slot3 (ADDR 8) write/read back", "");
+
+            spi_write(mk_write(7'd9, 24'h008009));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd9), rdata);
+            tb_assert(rdata === 24'h008009,
+                "DC_Slot4 (ADDR 9) write/read back", "");
+
+            spi_read(mk_read(7'd1), rdata);
+            tb_assert(rdata === 24'h800000,
+                "STATE register (ADDR 1) default (RDY=1)", "");
+
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    //==========================================================================
+    // Test Group 3: Execution protocol
+    //==========================================================================
+    task test_exec_protocol;
+        reg [1:0] done_result;
+        begin
+            $display("");
+            $display("-------------------------------------------------------------");
+            $display("  Group 3: Execution protocol");
+            $display("-------------------------------------------------------------");
+
+            // Configure and trigger execution with Freq_Slot1
+            spi_write(mk_write(7'd2, 24'h000005));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));  // EXEC=1
+            @(negedge i_sclk);
+
+            wait_con_done(500, done_result);
+            tb_assert(done_result === 1'b1,
+                "con_done goes HIGH after execution completes", "");
+
+            tb_assert(o_err === 1'b0,
+                "No error flag set after successful execution", "");
+
+            wait_wready(100, done_result);
+            tb_assert(done_result === 1'b1,
+                "o_wready is HIGH after execution (SPI ready)", "");
+
+            // Execute with DC_Slot1 (should complete but produce no output)
+            spi_write(mk_write(7'd6, 24'h002003));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_result);
+            tb_assert(done_result === 1'b1,
+                "DC slot execution completes (stub behavior)", "");
+            tb_assert(o_err === 1'b0,
+                "No error after DC slot execution (stub)", "");
+
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    //==========================================================================
+    // Test Group 4: Frequency slot decoding (all 4 slots)
+    //
+    // Freq_Slot N bit layout:
+    //   Bit 23:10: Per Relay_Control (14 bits)
+    //   Bit 9:1:   Channel_Number (9 bits)
+    //   Bit 0:     Slot_EN (1=Enable)
+    //
+    // Channel ranges:
+    //   1-8:     OC_x09 = slot_bit, PMU_OC[0] bit 0
+    //   9-72:    (no OC_x09/OC_x25), PMU_OC[0] from channel
+    //   73-136:  OC_x25 = slot_bit, PMU_OC[0] bit 16+
+    //   137-200: (no OC_x09/OC_x25), PMU_OC[0] bit 24+
+    //==========================================================================
+    task test_freq_slots;
+        reg [1:0] done_r;
+        begin
+            $display("");
+            $display("-------------------------------------------------------------");
+            $display("  Group 4: Frequency slot decoding (all 4 slots)");
+            $display("-------------------------------------------------------------");
+
+            // Slot1 Ch5 (range 1-8): OC_x09 = 4'b0001
+            // = (1<<23) | (0<<22) | (5<<1) | 1 = 24'h08000B (sets RC_F[1:0]=01)
+            $display("  Slot1 Ch5 (range 1-8): OC_x09=0001");
+            spi_write(mk_write(7'd2, 24'h08000B));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Slot1 Ch5 exec done", "timeout");
+            tb_assert(o_OC_x09[0] === 1'b1, "Slot1 Ch5: OC_x09[0]=1", "OC_x09[0] mismatch");
+            tb_assert(o_OC_x25 === 4'b0, "Slot1 Ch5: OC_x25=0", "OC_x25 mismatch");
+            tb_assert(o_RC_F[1:0] == 2'b01, "Slot1 Ch5: RC_F[1:0] has relay bits", "RC_F mismatch");
+            #(`SPI_CLK_PERIOD);
+
+            // Slot1 Ch50 (range 9-72): no OC_x09/OC_x25
+            // = (0<<10) | (50<<1) | 1 = 24'h000065
+            $display("  Slot1 Ch50 (range 9-72): OC_x09=0, OC_x25=0");
+            spi_write(mk_write(7'd2, 24'h000065));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Slot1 Ch50 exec done", "timeout");
+            tb_assert(o_OC_x09 === 4'b0, "Slot1 Ch50: OC_x09=0", "OC_x09 mismatch");
+            tb_assert(o_OC_x25 === 4'b0, "Slot1 Ch50: OC_x25=0", "OC_x25 mismatch");
+            #(`SPI_CLK_PERIOD);
+
+            // Slot1 Ch100 (range 73-136): OC_x25 = 4'b0001
+            // = (0<<10) | (100<<1) | 1 = 24'h0000C9
+            $display("  Slot1 Ch100 (range 73-136): OC_x25=0001");
+            spi_write(mk_write(7'd2, 24'h0000C9));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Slot1 Ch100 exec done", "timeout");
+            tb_assert(o_OC_x09 === 4'b0, "Slot1 Ch100: OC_x09=0", "OC_x09 mismatch");
+            tb_assert(o_OC_x25[0] === 1'b1, "Slot1 Ch100: OC_x25[0]=1", "OC_x25[0] mismatch");
+            tb_assert(o_RC_T[15:8] != 8'b0, "Slot1 Ch100: RC_T has relay bits", "RC_T mismatch");
+            #(`SPI_CLK_PERIOD);
+
+            // Slot1 Ch150 (range 137-200): no OC_x09/OC_x25
+            // = (0<<10) | (150<<1) | 1 = 24'h00012D
+            $display("  Slot1 Ch150 (range 137-200): OC_x09=0, OC_x25=0");
+            spi_write(mk_write(7'd2, 24'h00012D));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Slot1 Ch150 exec done", "timeout");
+            tb_assert(o_OC_x09 === 4'b0, "Slot1 Ch150: OC_x09=0", "OC_x09 mismatch");
+            tb_assert(o_OC_x25 === 4'b0, "Slot1 Ch150: OC_x25=0", "OC_x25 mismatch");
+            #(`SPI_CLK_PERIOD);
+
+            // Slot2 Ch5 (range 1-8): OC_x09 = 4'b0010
+            // = (1<<23) | (0<<22) | (5<<1) | 1 = 24'h08000B (sets RC_F[3:2]=01)
+            $display("  Slot2 Ch5 (range 1-8): OC_x09=0010");
+            spi_write(mk_write(7'd3, 24'h08000B));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Slot2 Ch5 exec done", "timeout");
+            tb_assert(o_OC_x09[1] === 1'b1, "Slot2 Ch5: OC_x09[1]=1", "OC_x09[1] mismatch");
+            tb_assert(o_RC_F[5:4] == 2'b01, "Slot2 Ch5: RC_F[5:4] has relay bits", "RC_F mismatch");
+            #(`SPI_CLK_PERIOD);
+
+            // Slot3 Ch100 (range 73-136): OC_x25 = 4'b0100
+            // = (0xAA<<10) | (100<<1) | 1 = 24'h02A8C9 (sets RC_T bits)
+            $display("  Slot3 Ch100 (range 73-136): OC_x25=0100");
+            spi_write(mk_write(7'd4, 24'h02A8C9));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Slot3 Ch100 exec done", "timeout");
+            tb_assert(o_OC_x25[2] === 1'b1, "Slot3 Ch100: OC_x25[2]=1", "OC_x25[2] mismatch");
+            #(`SPI_CLK_PERIOD);
+
+            // Slot4 Ch50 (range 9-72): no OC_x09/OC_x25
+            // = (0<<10) | (50<<1) | 1 = 24'h000065
+            $display("  Slot4 Ch50 (range 9-72): OC_x09=0, OC_x25=0");
+            spi_write(mk_write(7'd5, 24'h000065));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Slot4 Ch50 exec done", "timeout");
+            tb_assert(o_OC_x09 === 4'b0, "Slot4 Ch50: OC_x09=0", "OC_x09 mismatch");
+            tb_assert(o_OC_x25 === 4'b0, "Slot4 Ch50: OC_x25=0", "OC_x25 mismatch");
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    //==========================================================================
+    // Test Group 5: RC relay output patterns (RC_F, RC_S, RC_T)
+    //
+    // CPLD2 CPLD_Con relay mapping (frequency mode):
+    //   Slot1: RC_F[1:0], RC_S[3:0], RC_T[7:0]
+    //   Slot2: RC_F[5:4], RC_S[11:8], RC_T[23:16]
+    //   Slot3: RC_F[7:6], RC_S[15:12], RC_T[15:8] (bit-reordered)
+    //   Slot4: RC_F[1:0], RC_S[3:0], RC_T[7:0]
+    //
+    // Timing: relay_l1 at t=0, relay_l2 at t=500, relay_l3 at t=1000
+    //         exec_done at t=1080
+    //==========================================================================
+    task test_rc_relay_outputs;
+        reg [1:0] done_r;
+        begin
+            $display("");
+            $display("-------------------------------------------------------------");
+            $display("  Group 5: RC relay output patterns (RC_F/RC_S/RC_T)");
+            $display("-------------------------------------------------------------");
+
+            // 5a. Slot4 Ch5: Verify RC_F, RC_S, RC_T relay bit extraction
+            // Freq_Slot4 with RC_F[1:0]={1,0}, RC_S[3:0]={1,0,1,0}, Ch=5
+            // = (1<<23) | (0xA<<18) | (5<<1) | 1 = 24'hA8000B
+            $display("  Slot4: RC_F/RC_S/RC_T relay extraction");
+            spi_write(mk_write(7'd5, 24'hA8000B));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Slot4 relay exec done", "timeout");
+
+            // RC_F[1:0] should have relay bits from freq4[23:22]
+            tb_assert(o_RC_F[1:0] != 2'b00,
+                "Slot4: RC_F[1:0] has relay bits from freq4[23:22]",
+                $sformatf("RC_F[1:0]=%b", o_RC_F[1:0]));
+
+            // RC_S[3:0] should have relay bits from freq4[21:18]
+            tb_assert(o_RC_S[3:0] != 4'b0000,
+                "Slot4: RC_S[3:0] has relay bits from freq4[21:18]",
+                $sformatf("RC_S[3:0]=%b", o_RC_S[3:0]));
+
+            // RC_T[7:0] should have relay bits from freq4[17:10]
+            tb_assert(o_RC_T[7:0] != 8'b00000000,
+                "Slot4: RC_T[7:0] has relay bits from freq4[17:10]",
+                $sformatf("RC_T[7:0]=%b", o_RC_T[7:0]));
+
+            // 5b. Slot4 with specific relay pattern: bits 23=1, 22=0, 21=1, 20=0, 19=1, 18=0, Ch=5
+            // = (1<<23) | (0<<22) | (1<<21) | (0<<20) | (1<<19) | (0<<18) | (5<<1) | 1
+            // = 24'hA8000B
+            $display("  Slot4: RC_F/RC_S/RC_T specific relay pattern");
+            spi_write(mk_write(7'd5, 24'hA8000B));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Slot4 pattern exec done", "timeout");
+
+            // Verify RC_F[1:0] = {freq4[22], freq4[23]} = {0, 1} = 2'b01
+            tb_assert(o_RC_F[1:0] === 2'b01,
+                "Slot4: RC_F[1:0] = {freq4[22], freq4[23]} = 01",
+                $sformatf("RC_F[1:0]=%b", o_RC_F[1:0]));
+
+            // Verify RC_S[3:0] = {freq4[21], freq4[20], freq4[19], freq4[18]} = {1, 0, 1, 0} = 4'b1010
+            tb_assert(o_RC_S[3:0] === 4'b1010,
+                "Slot4: RC_S[3:0] = freq4[21:18] = 1010",
+                $sformatf("RC_S[3:0]=%b", o_RC_S[3:0]));
+
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    //==========================================================================
+    // Test Group 6: DC stub behavior
+    //
+    // CPLD2 CPLD_Con has DC slot cases but they are stubs:
+    //   - No relay output changes
+    //   - No PMU_OC output changes
+    //   - Just sets exec_flag=0, exec_done_flag=1
+    //
+    // The top module maps OC_x09/OC_x25 to PMU_OC via:
+    //   PMU_OC_N[8] = OC_x09[N-1]
+    //   PMU_OC_N[24] = OC_x25[N-1]
+    //   PMU_OC_N[7:0] = PMU_OC_internal[7:0] (always zero for DC stubs)
+    //   PMU_OC_N[23:9] = PMU_OC_internal[23:8] (always zero for DC stubs)
+    //   PMU_OC_N[31:25] = PMU_OC_internal[31:25] (always zero for DC stubs)
+    //==========================================================================
+    task test_dc_stub_behavior;
+        reg [1:0] done_r;
+        begin
+            $display("");
+            $display("-------------------------------------------------------------");
+            $display("  Group 6: DC stub behavior (no output changes)");
+            $display("-------------------------------------------------------------");
+
+            // 6a. DC_Slot1: Should complete but produce no relay/PMU output
+            $display("  DC1: Stub behavior - no relay or PMU output");
+            spi_write(mk_write(7'd6, 24'h002003));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "DC1 exec done (stub)", "timeout");
+
+            // RC outputs should remain at their previous state or be zero
+            // (DC stub doesn't change relay outputs)
+            tb_assert(o_err === 1'b0,
+                "DC1 stub: no error flag", "");
+
+            // 6b. DC_Slot2: Same stub behavior
+            $display("  DC2: Stub behavior - no relay or PMU output");
+            spi_write(mk_write(7'd7, 24'h004005));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "DC2 exec done (stub)", "timeout");
+            tb_assert(o_err === 1'b0,
+                "DC2 stub: no error flag", "");
+
+            // 6c. DC_Slot3: Same stub behavior
+            $display("  DC3: Stub behavior - no relay or PMU output");
+            spi_write(mk_write(7'd8, 24'h006007));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "DC3 exec done (stub)", "timeout");
+            tb_assert(o_err === 1'b0,
+                "DC3 stub: no error flag", "");
+
+            // 6d. DC_Slot4: Same stub behavior
+            $display("  DC4: Stub behavior - no relay or PMU output");
+            spi_write(mk_write(7'd9, 24'h008009));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "DC4 exec done (stub)", "timeout");
+            tb_assert(o_err === 1'b0,
+                "DC4 stub: no error flag", "");
+
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    //==========================================================================
+    // Test Group 7: Error conditions
+    //==========================================================================
+    task test_error_conditions;
+        reg [1:0] done_r;
+        reg [31:0] rdata;
+        begin
+            $display("");
+            $display("-------------------------------------------------------------");
+            $display("  Group 7: Error conditions");
+            $display("-------------------------------------------------------------");
+
+            // 7a. Short SPI transaction (16 bits)
+            $display("  Error 7a: Short SPI transaction (16 bits)");
+            i_cs = 1'b0;
+            @(negedge i_sclk);
+            @(negedge i_sclk);
+            for (integer bi = 0; bi < 16; bi = bi + 1) begin
+                i_mosi = 1'b0;
+                @(posedge i_sclk);
+                @(negedge i_sclk);
+            end
+            i_cs = 1'b1;
+            @(negedge i_sclk);
+            #(`SYS_CLK_PERIOD * 5);
+            tb_assert(o_err === 1'b1,
+                "o_err HIGH after short SPI transaction", "");
+            i_rst_n = 1'b0;
+            #(`SYS_CLK_PERIOD * 4);
+            i_rst_n = 1'b1;
+            #(`SYS_CLK_PERIOD * 4);
+            tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
+
+            #(`SPI_CLK_PERIOD);
+
+            // 7b. Write to IDENT register (ADDR 0, read-only)
+            $display("  Error 7b: Write to IDENT register (ADDR 0)");
+            spi_write(mk_write(7'd0, 24'hDEADBEE >> 8));
+            @(negedge i_sclk);
+            tb_assert(o_err === 1'b1,
+                "o_err HIGH after write to IDENT register", "");
+            i_rst_n = 1'b0;
+            #(`SYS_CLK_PERIOD * 4);
+            i_rst_n = 1'b1;
+            #(`SYS_CLK_PERIOD * 4);
+            tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
+
+            #(`SPI_CLK_PERIOD);
+
+            // 7c. Read out-of-bounds address (ADDR 16)
+            $display("  Error 7c: Read out-of-bounds address (ADDR 16)");
+            spi_read(mk_read(7'd16), rdata);
+            @(negedge i_sclk);
+            #(`SYS_CLK_PERIOD * 5);
+            tb_assert(o_err === 1'b1,
+                "o_err HIGH after reading ADDR 16", "");
+            i_rst_n = 1'b0;
+            #(`SYS_CLK_PERIOD * 4);
+            i_rst_n = 1'b1;
+            #(`SYS_CLK_PERIOD * 4);
+            tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
+
+            #(`SPI_CLK_PERIOD);
+
+            // 7d. Multiple slot enable bits (en_t > 1)
+            $display("  Error 7d: Multiple slot enable bits");
+            spi_write(mk_write(7'd2, 24'h000005));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd3, 24'h000006));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Execution completes (even with error)", "");
+            tb_assert(o_err === 1'b1,
+                "o_err HIGH with multiple slot enables", "");
+            i_rst_n = 1'b0;
+            #(`SYS_CLK_PERIOD * 4);
+            i_rst_n = 1'b1;
+            #(`SYS_CLK_PERIOD * 4);
+            tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
+
+            #(`SPI_CLK_PERIOD);
+
+            // 7e. Write to out-of-bounds address (ADDR 31)
+            $display("  Error 7e: Write to out-of-bounds address (ADDR 31)");
+            spi_write(mk_write(7'd31, 24'h123456));
+            @(negedge i_sclk);
+            #(`SYS_CLK_PERIOD * 5);
+            tb_assert(o_err === 1'b1,
+                "o_err HIGH after writing ADDR 31", "");
+            i_rst_n = 1'b0;
+            #(`SYS_CLK_PERIOD * 4);
+            i_rst_n = 1'b1;
+            #(`SYS_CLK_PERIOD * 4);
+            tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
+
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    //==========================================================================
+    // Test Group 8: Edge cases
+    //==========================================================================
+    task test_edge_cases;
+        reg [31:0] rdata;
+        begin
+            $display("");
+            $display("-------------------------------------------------------------");
+            $display("  Group 8: Edge cases");
+            $display("-------------------------------------------------------------");
+
+            // 8a. Brief CS pulse (too short for 32-bit)
+            $display("  Edge 8a: Brief CS pulse");
+            i_cs = 1'b0;
+            @(negedge i_sclk);
+            @(negedge i_sclk);
+            i_cs = 1'b1;
+            @(negedge i_sclk);
+            #(`SYS_CLK_PERIOD * 5);
+            tb_assert(o_err === 1'b1,
+                "o_err detected brief CS pulse", "");
+            i_rst_n = 1'b0;
+            #(`SYS_CLK_PERIOD * 4);
+            i_rst_n = 1'b1;
+            #(`SYS_CLK_PERIOD * 4);
+            tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
+
+            #(`SPI_CLK_PERIOD);
+
+            // 8b. Rapid successive SPI writes
+            $display("  Edge 8b: Rapid successive SPI writes");
+            spi_write(mk_write(7'd2, 24'h000001));
+            spi_write(mk_write(7'd3, 24'h000002));
+            spi_write(mk_write(7'd4, 24'h000003));
+            spi_write(mk_write(7'd5, 24'h000004));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd2), rdata);
+            tb_assert(rdata === 24'h000001, "Rapid write: ADDR 2 correct", "ADDR 2 mismatch");
+            spi_read(mk_read(7'd3), rdata);
+            tb_assert(rdata === 24'h000002, "Rapid write: ADDR 3 correct", "ADDR 3 mismatch");
+            spi_read(mk_read(7'd4), rdata);
+            tb_assert(rdata === 24'h000003, "Rapid write: ADDR 4 correct", "ADDR 4 mismatch");
+            spi_read(mk_read(7'd5), rdata);
+            tb_assert(rdata === 24'h000004, "Rapid write: ADDR 5 correct", "ADDR 5 mismatch");
+
+            #(`SPI_CLK_PERIOD);
+
+            // 8c. Write to reserved registers (ADDR 10-15) - no error
+            $display("  Edge 8c: Write to reserved registers");
+            spi_write(mk_write(7'd10, 24'hABCDEF));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd15, 24'h123456));
+            @(negedge i_sclk);
+            tb_assert(o_err === 1'b0, "No error writing to reserved ADDR 10 and 15",
+                "Unexpected error");
+
+            // 8d. Write STATE with EXEC=1 while already executing (should error)
+            $display("  Edge 8d: Write STATE while already executing");
+            spi_write(mk_write(7'd2, 24'h000005));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));  // EXEC=1
+            @(negedge i_sclk);
+            // Try to write another register while EXEC is still active
+            spi_write(mk_write(7'd3, 24'h000006));
+            @(negedge i_sclk);
+            #(`SYS_CLK_PERIOD * 5);
+            tb_assert(o_err === 1'b1,
+                "o_err HIGH when writing during execution", "");
+            i_rst_n = 1'b0;
+            #(`SYS_CLK_PERIOD * 4);
+            i_rst_n = 1'b1;
+            #(`SYS_CLK_PERIOD * 4);
+            tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
+
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    //==========================================================================
+    // Summary
+    //==========================================================================
+    task print_summary;
+        begin
+            $display("");
+            $display("=============================================================");
+            $display("  Test Summary");
+            $display("=============================================================");
+            $display("  Total tests: %0d", test_pass + test_fail);
+            $display("  Passed:      %0d", test_pass);
+            $display("  Failed:      %0d", test_fail);
+            $display("=============================================================");
+            if (test_fail == 0) begin
+                $display("  *** ALL TESTS PASSED ***");
+            end else begin
+                $display("  *** SOME TESTS FAILED - CHECK DESIGN ***");
+            end
+            $display("=============================================================");
+            $display("");
+        end
+    endtask
+
+endmodule
diff --git a/CPLD2/untitled.rva b/CPLD2/untitled.rva
new file mode 100644
index 0000000..5b52b57
--- /dev/null
+++ b/CPLD2/untitled.rva
@@ -0,0 +1,79 @@
+<!DOCTYPE ispTLA>
+<ispTLA>
+ <CreationDate>??? 1?? 13 14:14:20 2026</CreationDate>
+ <XCFFileName/>
+ <CableSetting>
+  <IsTRSTConnected val="false"/>
+  <TRSTSetting val="0"/>
+  <IsBSCANConnected val="false"/>
+  <BSCANSetting val="0"/>
+  <CableType val="USB"/>
+  <PortAddress val="0"/>
+  <PortSetting val="0"/>
+  <TCKDelay val="1"/>
+ </CableSetting>
+ <DeviceCount>1</DeviceCount>
+ <Device>
+  <DeviceIndex>0</DeviceIndex>
+  <DeviceName>1. LCMXO2-7000HC</DeviceName>
+  <DeviceID>0x012BD043</DeviceID>
+  <HasIspTRACY>true</HasIspTRACY>
+  <HasJTAG2WB>false</HasJTAG2WB>
+  <SERDES/>
+  <IRBypassLen>8</IRBypassLen>
+  <RVLFileName>debug.rvl</RVLFileName>
+  <RVSFileName>debug.rvs</RVSFileName>
+  <LACoreCount>1</LACoreCount>
+  <WinUI CoreIndex="0">
+   <TraceSigTreeData>
+    <TraceSignal IsHidden="false" Name="i_rst_n" NodeType="0" PortIndex="0"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_2/i_cs" NodeType="0" PortIndex="1"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_2/i_sclk" NodeType="0" PortIndex="2"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_2/i_mosi" NodeType="0" PortIndex="3"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_2/i_reg_busy" NodeType="0" PortIndex="4"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Reg_2/o_exec" NodeType="0" PortIndex="5"/>
+    <TraceSignal IsHidden="false" Name="RC_T" NodeType="1" PortIndex="6">
+     <BusRadix Radix="0"/>
+     <IsExpanded Expand="false"/>
+    </TraceSignal>
+    <TraceSignal IsHidden="false" Name="RC_T:0" NodeType="2" PortIndex="6"/>
+    <TraceSignal IsHidden="false" Name="RC_T:1" NodeType="2" PortIndex="7"/>
+    <TraceSignal IsHidden="false" Name="RC_T:2" NodeType="2" PortIndex="8"/>
+    <TraceSignal IsHidden="false" Name="RC_T:3" NodeType="2" PortIndex="9"/>
+    <TraceSignal IsHidden="false" Name="RC_T:4" NodeType="2" PortIndex="10"/>
+    <TraceSignal IsHidden="false" Name="RC_T:5" NodeType="2" PortIndex="11"/>
+    <TraceSignal IsHidden="false" Name="RC_T:6" NodeType="2" PortIndex="12"/>
+    <TraceSignal IsHidden="false" Name="RC_T:7" NodeType="2" PortIndex="13"/>
+    <TraceSignal IsHidden="false" Name="RC_T:8" NodeType="2" PortIndex="14"/>
+    <TraceSignal IsHidden="false" Name="RC_T:9" NodeType="2" PortIndex="15"/>
+    <TraceSignal IsHidden="false" Name="RC_T:10" NodeType="2" PortIndex="16"/>
+    <TraceSignal IsHidden="false" Name="RC_T:11" NodeType="2" PortIndex="17"/>
+    <TraceSignal IsHidden="false" Name="RC_T:12" NodeType="2" PortIndex="18"/>
+    <TraceSignal IsHidden="false" Name="RC_T:13" NodeType="2" PortIndex="19"/>
+    <TraceSignal IsHidden="false" Name="RC_T:14" NodeType="2" PortIndex="20"/>
+    <TraceSignal IsHidden="false" Name="RC_T:15" NodeType="2" PortIndex="21"/>
+    <TraceSignal IsHidden="false" Name="RC_T:16" NodeType="2" PortIndex="22"/>
+    <TraceSignal IsHidden="false" Name="RC_T:17" NodeType="2" PortIndex="23"/>
+    <TraceSignal IsHidden="false" Name="RC_T:18" NodeType="2" PortIndex="24"/>
+    <TraceSignal IsHidden="false" Name="RC_T:19" NodeType="2" PortIndex="25"/>
+    <TraceSignal IsHidden="false" Name="RC_T:20" NodeType="2" PortIndex="26"/>
+    <TraceSignal IsHidden="false" Name="RC_T:21" NodeType="2" PortIndex="27"/>
+    <TraceSignal IsHidden="false" Name="RC_T:22" NodeType="2" PortIndex="28"/>
+    <TraceSignal IsHidden="false" Name="RC_T:23" NodeType="2" PortIndex="29"/>
+    <TraceSignal IsHidden="false" Name="RC_T:24" NodeType="2" PortIndex="30"/>
+    <TraceSignal IsHidden="false" Name="RC_T:25" NodeType="2" PortIndex="31"/>
+    <TraceSignal IsHidden="false" Name="RC_T:26" NodeType="2" PortIndex="32"/>
+    <TraceSignal IsHidden="false" Name="RC_T:27" NodeType="2" PortIndex="33"/>
+    <TraceSignal IsHidden="false" Name="RC_T:28" NodeType="2" PortIndex="34"/>
+    <TraceSignal IsHidden="false" Name="RC_T:29" NodeType="2" PortIndex="35"/>
+    <TraceSignal IsHidden="false" Name="RC_T:30" NodeType="2" PortIndex="36"/>
+    <TraceSignal IsHidden="false" Name="RC_T:31" NodeType="2" PortIndex="37"/>
+   </TraceSigTreeData>
+   <TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/>
+   <CoreRun Run="true"/>
+   <CoreWndUIData>
+    <ClockFrequency Unit="ns" Frequency="-1.0"/>
+   </CoreWndUIData>
+  </WinUI>
+ </Device>
+</ispTLA>
diff --git a/CPLD2/untitled.svf b/CPLD2/untitled.svf
new file mode 100644
index 0000000..91017da
--- /dev/null
+++ b/CPLD2/untitled.svf
@@ -0,0 +1,2469 @@
+!
+! Diamond Reveal Analyzer SVF
+!
+! initialize SDR and SIR end state
+ENDDR IDLE;
+ENDIR IDLE;
+! initialize Header and Trailer
+HDR 0;
+HIR 0;
+TDR 0;
+TIR 0;
+
+! setTargetHubs
+! enable ER1
+SIR 8 TDI (32);
+! set reveal core
+SDR 21 TDI (00016);
+! enable ER2
+SIR 8 TDI (38);
+
+! enable ER2
+SIR 8 TDI (38);
+! enable ER2
+SIR 8 TDI (38);
+! Set Odd Parity readback
+SDR 36 TDI (c20000000);
+SDR 36 TDI (c20000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Set Odd Parity
+SDR 36 TDI (020000000);
+
+! Set LA Start/Stop readback
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Set LA Start/Stop 
+SDR 36 TDI (830000000);
+
+! Get Pattern
+SDR 36 TDI (430090000);
+SDR 36 TDI (430090000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Get Tracy Signature
+SDR 36 TDI (c30070000);
+SDR 36 TDI (c30070000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Get Tracy Signature
+SDR 36 TDI (c30080000);
+SDR 36 TDI (c30080000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Set Opcode Value
+SDR 36 TDI (000000007);
+
+! Set Mask Value
+SDR 36 TDI (000200000);
+
+! Set Opcode Value
+SDR 36 TDI (001000006);
+
+! Set Mask Value
+SDR 36 TDI (801200000);
+
+! Set Opcode Value
+SDR 36 TDI (002000000);
+
+! Set Comp Value
+SDR 36 TDI (802100000);
+
+! Set Mask Value
+SDR 36 TDI (802200000);
+
+! Set Then Num
+SDR 36 TDI (010000000);
+
+! Set NEXT THEN
+SDR 36 TDI (810040000);
+
+! Set Cnt Cntg
+SDR 36 TDI (010030000);
+
+! Set Event Count
+SDR 36 TDI (810100000);
+
+! Set Event Count
+SDR 36 TDI (010110000);
+
+! Set Then Num
+SDR 36 TDI (811000000);
+
+! Set NEXT THEN
+SDR 36 TDI (011040000);
+
+! Set Cnt Cntg
+SDR 36 TDI (811030000);
+
+! Set Event Count
+SDR 36 TDI (011100000);
+
+! Set Event Count
+SDR 36 TDI (811110000);
+
+! Set Then Num
+SDR 36 TDI (812000000);
+
+! Set NEXT THEN
+SDR 36 TDI (012040000);
+
+! Set Cnt Cntg
+SDR 36 TDI (812030000);
+
+! Set Event Count
+SDR 36 TDI (012100000);
+
+! Set Event Count
+SDR 36 TDI (812110000);
+
+! Get BurstWrite CRC
+SDR 36 TDI (c10050000);
+SDR 36 TDI (c10050000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Set Truth Tbl Addr Cnter Init
+SDR 36 TDI (810020000);
+
+! Set Truth Table Prog
+SDR 36 TDI (810010000);
+
+! burst write
+SDR 48 TDI (550050504444);
+
+!==> [JTAG] burst write 6 byte = 550050504444
+
+! Get BurstWrite CRC
+SDR 36 TDI (c10050000);
+SDR 36 TDI (c10050000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] teCRC = FFFF (equation = 1CAF)
+
+! Enable TE Trig
+SDR 36 TDI (020020007);
+
+! Enable Trig Output OR All readback
+SDR 36 TDI (c20000000);
+SDR 36 TDI (c20000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Enable Trig Output OR All
+SDR 36 TDI (820000008);
+
+! Set Pre-Trig Sample
+SDR 36 TDI (830010085);
+
+! Set Post-Trig Sample
+SDR 36 TDI (03002077a);
+
+! setTargetHubs
+! enable ER1
+SIR 8 TDI (32);
+! set reveal core
+SDR 21 TDI (00016);
+! enable ER2
+SIR 8 TDI (38);
+
+! enable ER2
+SIR 8 TDI (38);
+! Set LA Start cores
+SDR 36 TDI (030000001);
+
+! setTargetHubs
+! enable ER1
+SIR 8 TDI (32);
+! set reveal core
+SDR 21 TDI (00016);
+! enable ER2
+SIR 8 TDI (38);
+
+! Get Force Trigger bit
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Trig Detected Cnt
+SDR 36 TDI (430030000);
+SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Mem Block Full Cnt
+SDR 36 TDI (c30040000);
+SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmMemFullCnt = 0
+
+! setTargetHubs
+! enable ER1
+SIR 8 TDI (32);
+! set reveal core
+SDR 21 TDI (00016);
+! enable ER2
+SIR 8 TDI (38);
+
+! Get Force Trigger bit
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Trig Detected Cnt
+SDR 36 TDI (430030000);
+SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Mem Block Full Cnt
+SDR 36 TDI (c30040000);
+SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmMemFullCnt = 0
+
+! setTargetHubs
+! enable ER1
+SIR 8 TDI (32);
+! set reveal core
+SDR 21 TDI (00016);
+! enable ER2
+SIR 8 TDI (38);
+
+! Get Force Trigger bit
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Trig Detected Cnt
+SDR 36 TDI (430030000);
+SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Mem Block Full Cnt
+SDR 36 TDI (c30040000);
+SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmMemFullCnt = 0
+
+! setTargetHubs
+! enable ER1
+SIR 8 TDI (32);
+! set reveal core
+SDR 21 TDI (00016);
+! enable ER2
+SIR 8 TDI (38);
+
+! Get Force Trigger bit
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Trig Detected Cnt
+SDR 36 TDI (430030000);
+SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Mem Block Full Cnt
+SDR 36 TDI (c30040000);
+SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmMemFullCnt = 0
+
+! setTargetHubs
+! enable ER1
+SIR 8 TDI (32);
+! set reveal core
+SDR 21 TDI (00016);
+! enable ER2
+SIR 8 TDI (38);
+
+! Get Force Trigger bit
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Trig Detected Cnt
+SDR 36 TDI (430030000);
+SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Mem Block Full Cnt
+SDR 36 TDI (c30040000);
+SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmMemFullCnt = 0
+
+! setTargetHubs
+! enable ER1
+SIR 8 TDI (32);
+! set reveal core
+SDR 21 TDI (00016);
+! enable ER2
+SIR 8 TDI (38);
+
+! Get Force Trigger bit
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Trig Detected Cnt
+SDR 36 TDI (430030000);
+SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Mem Block Full Cnt
+SDR 36 TDI (c30040000);
+SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmMemFullCnt = 0
+
+! setTargetHubs
+! enable ER1
+SIR 8 TDI (32);
+! set reveal core
+SDR 21 TDI (00016);
+! enable ER2
+SIR 8 TDI (38);
+
+! Get Force Trigger bit
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Trig Detected Cnt
+SDR 36 TDI (430030000);
+SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Mem Block Full Cnt
+SDR 36 TDI (c30040000);
+SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmMemFullCnt = 0
+
+! setTargetHubs
+! enable ER1
+SIR 8 TDI (32);
+! set reveal core
+SDR 21 TDI (00016);
+! enable ER2
+SIR 8 TDI (38);
+
+! Get Force Trigger bit
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Trig Detected Cnt
+SDR 36 TDI (430030000);
+SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Mem Block Full Cnt
+SDR 36 TDI (c30040000);
+SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmMemFullCnt = 0
+
+! setTargetHubs
+! enable ER1
+SIR 8 TDI (32);
+! set reveal core
+SDR 21 TDI (00016);
+! enable ER2
+SIR 8 TDI (38);
+
+! Get Force Trigger bit
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Trig Detected Cnt
+SDR 36 TDI (430030000);
+SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Mem Block Full Cnt
+SDR 36 TDI (c30040000);
+SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmMemFullCnt = 0
+
+! setTargetHubs
+! enable ER1
+SIR 8 TDI (32);
+! set reveal core
+SDR 21 TDI (00016);
+! enable ER2
+SIR 8 TDI (38);
+
+! Get Force Trigger bit
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Trig Detected Cnt
+SDR 36 TDI (430030000);
+SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Mem Block Full Cnt
+SDR 36 TDI (c30040000);
+SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmMemFullCnt = 1
+
+! Is LA Armed
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Set LA Start/Stop readback
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Set LA Start/Stop 
+SDR 36 TDI (030000004);
+
+! enable ER2
+SIR 8 TDI (38);
+! Set LA Start/Stop readback
+SDR 36 TDI (430000000);
+SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Set LA Start/Stop 
+SDR 36 TDI (030000004);
+
+! enable ER2
+SIR 8 TDI (38);
+! Get Trig Detected Cnt
+SDR 36 TDI (430030000);
+SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Get Mem Block Full Cnt
+SDR 36 TDI (c30040000);
+SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmMemFullCnt = 1
+
+! Get Last Addr Written
+SDR 36 TDI (430060000);
+SDR 36 TDI (430060000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmLastAddrWritten = 865
+
+! Get Multiple Trig Enbl
+SDR 36 TDI (430050000);
+SDR 36 TDI (430050000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Get BurstRead CRC
+SDR 36 TDI (4300a0000);
+SDR 36 TDI (4300a0000) TDO (000000000) MASK (FFFFFFFFF);
+
+! enable ER2
+SIR 8 TDI (38);
+! Set Trace Mem Cnter Init
+SDR 36 TDI (080000000);
+
+! burst read
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+
+! Get BurstRead CRC
+SDR 36 TDI (4300a0000);
+SDR 36 TDI (4300a0000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] dummy = 2D8F
+
+! Get BurstRead CRC
+SDR 36 TDI (4300a0000);
+SDR 36 TDI (4300a0000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmCRC = 2D8F (equation = 47F8)
+
+! Get Pre-Trig Sample Num
+SDR 36 TDI (c30010000);
+SDR 36 TDI (c30010000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Get Post-Trig Sample Num
+SDR 36 TDI (c30020000);
+SDR 36 TDI (c30020000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [TMEN] preTrig=128
+
+! Get Pre-Trig Samples Captured
+SDR 36 TDI (c31000000);
+SDR 36 TDI (c31000000) TDO (000000000) MASK (FFFFFFFFF);
+
+! Get Trig Ptr
+SDR 36 TDI (c32000000);
+SDR 36 TDI (c32000000) TDO (000000000) MASK (FFFFFFFFF);
+
+!==> [JTAG] tmTrigPTr = 999
+
+!==> [TMEN] trigPtr=999
+
+!==> [TMEN] pre_cap=true (preCap=1, regNum=0, offset=0)
+
+!==> [TMEN] trigPtr=994 (- 5)
+
+!==> [TMEN] (pre_cap) out:2914-2048
+
+!==> [TMEN] (pre_cap) out:866-995
+
+!==> [TMEN] (pre_cap) triggerPosition=128
+
diff --git a/CPLD2/untitled.trc b/CPLD2/untitled.trc
new file mode 100644
index 0000000..e69de29
diff --git a/CPLD3/BUS_Con.v b/CPLD3/BUS_Con.v
new file mode 100644
index 0000000..cc61c73
--- /dev/null
+++ b/CPLD3/BUS_Con.v
@@ -0,0 +1,215 @@
+module BUS_Con (
+    input i_sys_clk,
+    input i_rst_n,
+    
+    // SPI Interface
+    input i_sclk,
+    input i_mosi,
+    input i_cs,
+    output o_miso,          // <-- MISO Logic added here
+    
+    // Local Interface
+    output o_rvalid,        // (Typo in original: o_rvalid)
+    input i_rvalid,         // Valid signal from Backend (Data is ready)
+    input i_wvalid,
+    output o_wready,
+    input i_reg_busy,
+    input [23:0] i_rdata,   // Data from Backend to send to Master
+    output o_wr,
+    output o_cmd_valid,
+    output [23:0] o_data,
+    output [6:0] o_addr,
+    output o_err
+);
+
+    // --- 1. Synchronization ---
+    reg [1:0] cs_sync;
+    reg [1:0] sclk_sync;
+    reg [1:0] mosi_sync;
+    
+    wire cs_active;
+    wire cs_rise;
+    wire sclk_rise; // For Sampling MOSI
+    wire sclk_fall; // For Shifting MISO
+    wire mosi_data;
+	
+
+    always @(posedge i_sys_clk) begin
+        if (!i_rst_n) begin
+            cs_sync   <= 2'b11;
+            sclk_sync <= 2'b00;
+            mosi_sync <= 2'b00;
+        end else begin
+            cs_sync   <= {cs_sync[0], i_cs};
+            sclk_sync <= {sclk_sync[0], i_sclk};
+            mosi_sync <= {mosi_sync[0], i_mosi};
+        end
+    end
+
+    assign cs_active = ~cs_sync[1]; 
+    assign cs_rise   = (!cs_sync[1] && cs_sync[0]); 
+    
+    // SPI Mode 0: Sample MOSI on Rising, Shift MISO on Falling
+    assign sclk_rise = (!sclk_sync[1] && sclk_sync[0]); 
+    assign sclk_fall = (sclk_sync[1] && !sclk_sync[0]); // Logic for MISO
+    assign mosi_data = mosi_sync[1];
+
+    // --- 2. MOSI (Receive) Logic ---
+    reg [31:0] recv_reg;
+    reg [5:0]  bit_cnt;
+    reg        data_ready;
+    reg        err_flag;
+	reg [1:0] state;
+	//
+	reg [31:0] tx_buffer;  // Holds data waiting for the next CS Low
+    reg [31:0] miso_shift; // The actual shifter
+    // Output Registers
+    reg [6:0]  addr_out;
+    reg [23:0] data_out;
+    reg        wr_out;
+    reg        cmd_valid_out;
+	
+	//
+	localparam IDLE      = 2'b00;
+    localparam CMD_SENT  = 2'b01;
+    localparam WAIT_BUSY = 2'b10;
+    localparam DONE      = 2'b11;
+    
+
+    always @(posedge i_sys_clk) begin
+        if (!i_rst_n) begin
+            recv_reg      <= 32'd0;
+            bit_cnt       <= 6'd0;
+            data_ready    <= 1'b0;
+            err_flag      <= 1'b0;
+        end 
+		else begin
+            data_ready <= 1'b0; 
+
+            if (cs_active) begin
+                if (sclk_rise) begin
+                    recv_reg <= {recv_reg[30:0], mosi_data}; 
+                    bit_cnt  <= bit_cnt + 1'b1;
+                end
+				else if (cs_rise) begin
+					if (bit_cnt == 6'd32) begin
+						data_ready <= 1'b1;
+						err_flag   <= 1'b0;
+						bit_cnt <= 6'd0;
+					end 
+					else if (bit_cnt != 0) begin
+						err_flag   <= 1'b1;
+						bit_cnt <= 6'd0;
+                        recv_reg <= 'd0;
+					end
+				end
+            end
+            if (state == DONE) begin
+                recv_reg <= 'd0;
+            end
+        end
+    end
+
+    // --- 3. MISO (Transmit) Logic ---
+    // Protocol: We shift out 32 bits. 
+    // Format: [8 bit Status/Padding] + [24 bit i_rdata]
+    
+
+    // Capture data from backend when valid
+    always @(posedge i_sys_clk) begin
+        if (!i_rst_n) begin
+            tx_buffer <= 32'd0;
+        end else begin
+            // If backend provides valid read data, store it.
+            // We pad the top 8 bits with Zeros (or you can put status flags here)
+            if (i_rvalid) begin
+                tx_buffer <= {8'h00, i_rdata}; 
+            end
+        end
+    end
+
+    // Shift data out
+    always @(posedge i_sys_clk) begin
+        if (!i_rst_n) begin
+            miso_shift <= 32'd0;
+        end else begin
+            if (!cs_active) begin
+                // Pre-load the shifter while CS is High
+                // This ensures Bit 31 is ready BEFORE the first clock edge
+                miso_shift <= tx_buffer;
+            end else begin
+                // Shift on Falling Edge (Master samples on Rising)
+                if (sclk_fall) begin
+                    miso_shift <= {miso_shift[30:0], 1'b0};
+                end
+            end
+        end
+    end
+
+    // Tri-state MISO when CS is high (optional, usually good practice)
+    // If your board doesn't need tristate, just use: assign o_miso = miso_shift[31];
+    assign o_miso = (cs_active) ? miso_shift[31] : 1'bz;
+
+    // --- 4. Register Control FSM ---
+
+    
+
+    always @(posedge i_sys_clk) begin
+        if (!i_rst_n) begin
+            state         <= IDLE;
+            cmd_valid_out <= 1'b0;
+            addr_out      <= 7'd0;
+            data_out      <= 24'd0;
+            wr_out        <= 1'b0;
+        end else begin
+            case (state)
+                IDLE: begin
+                    if (data_ready) begin
+                        addr_out      <= recv_reg[30:24];
+                        data_out      <= recv_reg[23:0];
+                        wr_out        <= recv_reg[31];
+                        
+                        if (!i_reg_busy) begin
+                            cmd_valid_out <= 1'b1;
+                            state         <= CMD_SENT;
+                        end else begin
+                            state         <= WAIT_BUSY;
+                        end
+                    end
+                end
+
+                WAIT_BUSY: begin
+                    if (!i_reg_busy) begin
+                        cmd_valid_out <= 1'b1;
+                        state         <= CMD_SENT;
+                    end
+                end
+
+                CMD_SENT: begin
+                    cmd_valid_out <= 1'b0;
+                    state         <= DONE;
+                end
+
+                DONE: begin
+                    if (!i_reg_busy) begin
+                        state <= IDLE;
+                        addr_out <= 'd0;
+                        data_out <= 'd0;
+                        wr_out <= 'd0;
+                    end
+                end
+            endcase
+        end
+    end
+
+    assign o_addr      = addr_out;
+    assign o_data      = data_out;
+    assign o_wr        = wr_out;
+    assign o_cmd_valid = cmd_valid_out;
+    assign o_err       = err_flag;
+    assign o_wready    = (state == IDLE); 
+    
+    // Pass through unused signal or hook it up if needed
+    assign o_rvalid    = 1'b0; 
+
+endmodule
\ No newline at end of file
diff --git a/CPLD3/CPLD3_Debug.rva b/CPLD3/CPLD3_Debug.rva
new file mode 100644
index 0000000..f1b216b
--- /dev/null
+++ b/CPLD3/CPLD3_Debug.rva
@@ -0,0 +1,107 @@
+<!DOCTYPE ispTLA>
+<ispTLA>
+ <CreationDate>??? 1?? 13 14:07:51 2026</CreationDate>
+ <XCFFileName/>
+ <CableSetting>
+  <IsTRSTConnected val="false"/>
+  <TRSTSetting val="0"/>
+  <IsBSCANConnected val="false"/>
+  <BSCANSetting val="0"/>
+  <CableType val="USB"/>
+  <PortAddress val="0"/>
+  <PortSetting val="0"/>
+  <TCKDelay val="1"/>
+ </CableSetting>
+ <DeviceCount>1</DeviceCount>
+ <Device>
+  <DeviceIndex>0</DeviceIndex>
+  <DeviceName>1. LCMXO2-7000HC</DeviceName>
+  <DeviceID>0x012BD043</DeviceID>
+  <HasIspTRACY>true</HasIspTRACY>
+  <HasJTAG2WB>false</HasJTAG2WB>
+  <SERDES/>
+  <IRBypassLen>8</IRBypassLen>
+  <RVLFileName>debug.rvl</RVLFileName>
+  <RVSFileName>debug.rvs</RVSFileName>
+  <LACoreCount>1</LACoreCount>
+  <WinUI CoreIndex="0">
+   <TraceSigTreeData>
+    <TraceSignal IsHidden="false" Name="i_rst_n" NodeType="0" PortIndex="0"/>
+    <TraceSignal IsHidden="false" Name="i_cs" NodeType="0" PortIndex="1"/>
+    <TraceSignal IsHidden="false" Name="i_mosi" NodeType="0" PortIndex="2"/>
+    <TraceSignal IsHidden="false" Name="i_sclk" NodeType="0" PortIndex="3"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Con_3/slot_exec_flag" NodeType="1" PortIndex="4">
+     <BusRadix Radix="0"/>
+     <IsExpanded Expand="false"/>
+    </TraceSignal>
+    <TraceSignal IsHidden="false" Name="CPLD_Con_3/slot_exec_flag:0" NodeType="2" PortIndex="4"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Con_3/slot_exec_flag:1" NodeType="2" PortIndex="5"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Con_3/slot_exec_flag:2" NodeType="2" PortIndex="6"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Con_3/slot_exec_flag:3" NodeType="2" PortIndex="7"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Con_3/o_PMU_RC" NodeType="1" PortIndex="8">
+     <BusRadix Radix="0"/>
+     <IsExpanded Expand="false"/>
+    </TraceSignal>
+    <TraceSignal IsHidden="false" Name="CPLD_Con_3/o_PMU_RC:0" NodeType="2" PortIndex="8"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Con_3/o_PMU_RC:1" NodeType="2" PortIndex="9"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Con_3/o_PMU_RC:2" NodeType="2" PortIndex="10"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Con_3/o_PMU_RC:3" NodeType="2" PortIndex="11"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out" NodeType="1" PortIndex="12">
+     <BusRadix Radix="0"/>
+     <IsExpanded Expand="false"/>
+    </TraceSignal>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:0" NodeType="2" PortIndex="12"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:1" NodeType="2" PortIndex="13"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:2" NodeType="2" PortIndex="14"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:3" NodeType="2" PortIndex="15"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:4" NodeType="2" PortIndex="16"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:5" NodeType="2" PortIndex="17"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:6" NodeType="2" PortIndex="18"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out" NodeType="1" PortIndex="19">
+     <BusRadix Radix="0"/>
+     <IsExpanded Expand="false"/>
+    </TraceSignal>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:0" NodeType="2" PortIndex="19"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:1" NodeType="2" PortIndex="20"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:2" NodeType="2" PortIndex="21"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:3" NodeType="2" PortIndex="22"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:4" NodeType="2" PortIndex="23"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:5" NodeType="2" PortIndex="24"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:6" NodeType="2" PortIndex="25"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:7" NodeType="2" PortIndex="26"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:8" NodeType="2" PortIndex="27"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:9" NodeType="2" PortIndex="28"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:10" NodeType="2" PortIndex="29"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:11" NodeType="2" PortIndex="30"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:12" NodeType="2" PortIndex="31"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:13" NodeType="2" PortIndex="32"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:14" NodeType="2" PortIndex="33"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:15" NodeType="2" PortIndex="34"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:16" NodeType="2" PortIndex="35"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:17" NodeType="2" PortIndex="36"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:18" NodeType="2" PortIndex="37"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:19" NodeType="2" PortIndex="38"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:20" NodeType="2" PortIndex="39"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:21" NodeType="2" PortIndex="40"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:22" NodeType="2" PortIndex="41"/>
+    <TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:23" NodeType="2" PortIndex="42"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Reg_3/state" NodeType="1" PortIndex="43">
+     <BusRadix Radix="0"/>
+     <IsExpanded Expand="false"/>
+    </TraceSignal>
+    <TraceSignal IsHidden="false" Name="CPLD_Reg_3/state:0" NodeType="2" PortIndex="43"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Reg_3/state:1" NodeType="2" PortIndex="44"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Reg_3/state:2" NodeType="2" PortIndex="45"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Reg_3/state:3" NodeType="2" PortIndex="46"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Reg_3/i_con_done" NodeType="0" PortIndex="47"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Reg_3/busy_flag" NodeType="0" PortIndex="48"/>
+    <TraceSignal IsHidden="false" Name="CPLD_Reg_3/exec_bit" NodeType="0" PortIndex="49"/>
+   </TraceSigTreeData>
+   <TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/>
+   <CoreRun Run="true"/>
+   <CoreWndUIData>
+    <ClockFrequency Unit="ns" Frequency="-1.0"/>
+   </CoreWndUIData>
+  </WinUI>
+ </Device>
+</ispTLA>
diff --git a/CPLD3/CPLD3_Debug.svf b/CPLD3/CPLD3_Debug.svf
new file mode 100644
index 0000000..d3fbbb6
--- /dev/null
+++ b/CPLD3/CPLD3_Debug.svf
@@ -0,0 +1,12 @@
+!
+! Diamond Reveal Analyzer SVF
+!
+! initialize SDR and SIR end state
+ENDDR IDLE;
+ENDIR IDLE;
+! initialize Header and Trailer
+HDR 0;
+HIR 0;
+TDR 0;
+TIR 0;
+
diff --git a/CPLD3/CPLD3_Debug.trc b/CPLD3/CPLD3_Debug.trc
new file mode 100644
index 0000000..bd1397c
--- /dev/null
+++ b/CPLD3/CPLD3_Debug.trc
@@ -0,0 +1,2056 @@
+Device=0 LA=0
+TriggerFrameCount=1
+0 
+TriggerPosCount=1
+128 
+DataPos=128
+Signature=677845409
+TraceWidth=50 TraceDepth=2048 TimeStampWidth=0
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+2034 -1 1 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
+2035 -1 1 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
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+2037 -1 1 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
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+2041 -1 1 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
+2042 -1 1 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
+2043 -1 1 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
+2044 -1 1 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
+2045 -1 1 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
+2046 -1 1 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
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diff --git a/CPLD3/CPLD_Con.v b/CPLD3/CPLD_Con.v
new file mode 100644
index 0000000..2a6bb73
--- /dev/null
+++ b/CPLD3/CPLD_Con.v
@@ -0,0 +1,149 @@
+module CPLD_Con (
+    input i_sys_clk,
+    input i_rst_n,
+    input i_con_exec,
+    input [23:0]i_freq_relay1,
+    input [23:0]i_freq_relay2,
+    input [23:0]i_freq_relay3,
+    input [23:0]i_freq_relay4,
+
+// DC related Control
+    input [23:0]i_DC_Con1,
+    input [23:0]i_DC_Con2,
+    input [23:0]i_DC_Con3,
+    input [23:0]i_DC_Con4,
+
+    output o_con_done,
+    output [3:0]o_PMU_RC,
+    output o_err
+);
+
+    //Relay Reg
+    reg [3:0] PMU_RC;
+
+    //Condition Tester
+    reg [15:0]en_t ;
+    reg freq_t;
+    reg dc_t;
+
+    //Flags
+    reg exec_flag;
+    reg err_flag;
+    reg [3:0]freq_slot_flag;
+	reg [3:0]dc_slot_flag;
+    reg done_flag;
+
+    //Counter
+    reg [15:0]delay_cnt;
+
+    always @(posedge i_sys_clk) begin
+        if (i_rst_n == 1'b0) begin
+            delay_cnt <= 'd0;
+        end
+        else begin
+            if (exec_flag == 1'b1) begin
+                delay_cnt <= delay_cnt + 1'd1;
+            end
+            else begin
+                delay_cnt <= 'd0;
+            end
+        end
+    end
+
+    //Function Identify
+    always @(posedge i_sys_clk) begin
+        if (i_rst_n == 1'b0) begin
+            en_t <= 'd0;
+            freq_t <= 'd0;
+            dc_t <= 'd0;
+        end
+        else begin
+            en_t <= (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) + (i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0] );
+            freq_t <= i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0];
+            dc_t <= i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0];
+        end
+    end
+
+    //  Main Controller Function
+    always @(posedge i_sys_clk) begin
+        if (i_rst_n == 1'b0) begin
+            exec_flag <= 1'b0;
+            err_flag <= 1'b0;
+            freq_slot_flag <= 'd0;
+            dc_slot_flag<='d0;
+            done_flag <= 'd1;
+            PMU_RC <= 4'b1111;
+        end
+        else begin
+            if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin
+                exec_flag <= 1'b1;
+                done_flag <= 1'b0;
+                //To DO: More Sanity Check?
+                if (en_t > 'd1) begin                                                   //Only ONE Enable bit should be set!
+                    err_flag <= 1'b1;
+                end
+                else begin
+                    freq_slot_flag[0] <= i_freq_relay1[0];
+                    freq_slot_flag[1] <= i_freq_relay2[0];
+                    freq_slot_flag[2] <= i_freq_relay3[0];
+                    freq_slot_flag[3] <= i_freq_relay4[0];
+
+                    dc_slot_flag[0] <= i_DC_Con1[0];
+                    dc_slot_flag[1] <= i_DC_Con2[0];
+                    dc_slot_flag[2] <= i_DC_Con3[0];
+                    dc_slot_flag[3] <= i_DC_Con4[0];
+                end
+            end
+            else if (exec_flag == 1'b1) begin
+                if (freq_t == 1'b1) begin
+                    case (freq_slot_flag)
+                        4'b0001: begin
+                            PMU_RC <= 4'b1111;
+                        end
+                        4'b0010: begin
+                            PMU_RC <= 4'b1100;
+                        end
+                        4'b0100: begin
+                            PMU_RC <= 4'b1010;
+                        end
+                        4'b1000: begin
+                            PMU_RC <= 4'b0110;
+                        end
+                        default:begin
+                            PMU_RC <= 4'b0000;
+                        end
+                    endcase
+                end
+                else if (dc_t == 1'b1)  begin
+                    case (dc_slot_flag)
+                        4'b0001: begin
+                            PMU_RC <= 4'b0001;
+                        end
+                        4'b0010: begin
+                            PMU_RC <= 4'b0010;
+                        end
+                        4'b0100: begin
+                            PMU_RC <= 4'b0100;
+                        end
+                        4'b1000: begin
+                            PMU_RC <= 4'b1000;
+                        end
+                        default:begin
+                            PMU_RC <= 4'b0000;
+                        end
+                    endcase
+                end
+                done_flag <= 1'b1;
+            end
+        end
+        if (done_flag == 1) begin
+            exec_flag <= 1'b0; 
+        end
+    end 
+
+    assign o_con_done = done_flag;
+    assign o_PMU_RC = PMU_RC;
+    assign o_err = err_flag;
+
+
+endmodule
\ No newline at end of file
diff --git a/CPLD3/NewExtInsRelay1.sty b/CPLD3/NewExtInsRelay1.sty
new file mode 100644
index 0000000..11299b1
--- /dev/null
+++ b/CPLD3/NewExtInsRelay1.sty
@@ -0,0 +1,206 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE strategy>
+<Strategy version="1.0" predefined="0" description="" label="Strategy1">
+    <Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
+    <Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
+    <Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
+    <Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
+    <Property name="PROP_BD_EdfMemPath" value="" time="0"/>
+    <Property name="PROP_BD_ParSearchPath" value="" time="0"/>
+    <Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
+    <Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
+    <Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
+    <Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
+    <Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
+    <Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
+    <Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
+    <Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
+    <Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
+    <Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
+    <Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
+    <Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
+    <Property name="PROP_BIT_NoHeader" value="False" time="0"/>
+    <Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
+    <Property name="PROP_BIT_OutFormatBitGen_REF" value="Bit File (Binary)" time="0"/>
+    <Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
+    <Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
+    <Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
+    <Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
+    <Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
+    <Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
+    <Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
+    <Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
+    <Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
+    <Property name="PROP_LST_CarryChain" value="True" time="0"/>
+    <Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
+    <Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
+    <Property name="PROP_LST_DSPUtil" value="100" time="0"/>
+    <Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
+    <Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
+    <Property name="PROP_LST_EBRUtil" value="100" time="0"/>
+    <Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
+    <Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
+    <Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
+    <Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
+    <Property name="PROP_LST_EdfMemPath" value="" time="0"/>
+    <Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
+    <Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
+    <Property name="PROP_LST_IOInsertion" value="True" time="0"/>
+    <Property name="PROP_LST_InterFileDump" value="False" time="0"/>
+    <Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
+    <Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
+    <Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
+    <Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
+    <Property name="PROP_LST_PropagatConst" value="True" time="0"/>
+    <Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
+    <Property name="PROP_LST_ReportTrimmedUserNets" value="False" time="0"/>
+    <Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
+    <Property name="PROP_LST_ResourceShare" value="True" time="0"/>
+    <Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
+    <Property name="PROP_LST_UseLPF" value="True" time="0"/>
+    <Property name="PROP_LST_VHDL2008" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
+    <Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
+    <Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
+    <Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
+    <Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
+    <Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
+    <Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
+    <Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
+    <Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
+    <Property name="PROP_MAP_MapModArgs" value="" time="0"/>
+    <Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
+    <Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
+    <Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
+    <Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
+    <Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
+    <Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
+    <Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
+    <Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
+    <Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
+    <Property name="PROP_PARSTA_FullName" value="False" time="0"/>
+    <Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
+    <Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
+    <Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
+    <Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
+    <Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
+    <Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
+    <Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
+    <Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
+    <Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
+    <Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
+    <Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
+    <Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
+    <Property name="PROP_PAR_PARModArgs" value="" time="0"/>
+    <Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
+    <Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
+    <Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
+    <Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
+    <Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
+    <Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
+    <Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
+    <Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
+    <Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_StopZero" value="False" time="0"/>
+    <Property name="PROP_PAR_parHold" value="On" time="0"/>
+    <Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
+    <Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
+    <Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
+    <Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
+    <Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
+    <Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
+    <Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
+    <Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
+    <Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
+    <Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
+    <Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfArea" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
+    <Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
+    <Property name="PROP_SYN_EdfFrequency" value="200" time="0"/>
+    <Property name="PROP_SYN_EdfGSR" value="Auto" time="0"/>
+    <Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfNumCritPath" value="3" time="0"/>
+    <Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
+    <Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
+    <Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
+    <Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
+    <Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
+    <Property name="PROP_SYN_LibPath" value="" time="0"/>
+    <Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
+    <Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
+    <Property name="PROP_SYN_UseLPF" value="True" time="0"/>
+    <Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
+    <Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
+    <Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
+    <Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
+    <Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
+    <Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
+    <Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
+    <Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
+    <Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
+    <Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
+    <Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
+    <Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
+    <Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
+</Strategy>
diff --git a/CPLD3/NewExtIns_CPLD3.ccl b/CPLD3/NewExtIns_CPLD3.ccl
new file mode 100644
index 0000000..dcf391b
--- /dev/null
+++ b/CPLD3/NewExtIns_CPLD3.ccl
@@ -0,0 +1 @@
+VERSION=20110520
diff --git a/CPLD3/NewExtIns_CPLD3.ldf b/CPLD3/NewExtIns_CPLD3.ldf
new file mode 100644
index 0000000..7da2797
--- /dev/null
+++ b/CPLD3/NewExtIns_CPLD3.ldf
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.2" title="NewExtIns_CPLD3" device="LCMXO2-7000HC-4FG484C" default_implementation="impl1">
+    <Options/>
+    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
+        <Options def_top="RelayConTop" top="RelayConTop"/>
+        <Source name="RelayConTop.v" type="Verilog" type_short="Verilog">
+            <Options top_module="RelayConTop"/>
+        </Source>
+        <Source name="BUS_Con.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="Reg_file.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="tb_RelayConTop.sv" type="Verilog" type_short="Verilog" syn_sim="SimOnly">
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
+        <Source name="CPLD_Con.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="CPLD3_Debug.rva" type="Reveal Analyzer Project File" type_short="RVA">
+            <Options/>
+        </Source>
+        <Source name="NewExtIns_CPLD3.lpf" type="Logic Preference" type_short="LPF">
+            <Options/>
+        </Source>
+        <Source name="debug.rvl" type="Reveal" type_short="Reveal">
+            <Options/>
+        </Source>
+        <Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
+            <Options/>
+        </Source>
+        <Source name="tb_RelayConTop/tb_RelayConTop.spf" type="Simulation Project File" type_short="SPF">
+            <Options/>
+        </Source>
+    </Implementation>
+    <Strategy name="Strategy1" file="NewExtInsRelay1.sty"/>
+</BaliProject>
diff --git a/CPLD3/NewExtIns_CPLD3.lpf b/CPLD3/NewExtIns_CPLD3.lpf
new file mode 100644
index 0000000..ef512d7
--- /dev/null
+++ b/CPLD3/NewExtIns_CPLD3.lpf
@@ -0,0 +1,29 @@
+rvl_alias "i_sys_clk" "i_sys_clk";
+RVL_ALIAS "i_sys_clk" "i_sys_clk"; 
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+LOCATE COMP "i_sys_clk" SITE "B9" ;
+LOCATE COMP "i_rst_n" SITE "Y14" ;
+LOCATE COMP "i_sclk" SITE "AA10" ;
+LOCATE COMP "i_cs" SITE "AB11" ;
+LOCATE COMP "i_mosi" SITE "AB12" ;
+LOCATE COMP "o_miso" SITE "AA14" ;
+IOBUF PORT "i_cs" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "i_mosi" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "i_sclk" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ;
+IOBUF PORT "o_rvaild" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "i_sys_clk" DRIVE=NA IO_TYPE=LVCMOS33 SLEWRATE=NA PULLMODE=DOWN ;
+IOBUF PORT "o_err" IO_TYPE=LVCMOS33 ;
+LOCATE COMP "o_err" SITE "AB16" ;
+LOCATE COMP "o_PMU_RC[0]" SITE "V2" ;
+LOCATE COMP "o_PMU_RC[1]" SITE "N18" ;
+LOCATE COMP "o_PMU_RC[2]" SITE "P19" ;
+LOCATE COMP "o_PMU_RC[3]" SITE "P18" ;
+IOBUF PORT "o_PMU_RC[0]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_PMU_RC[1]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_PMU_RC[2]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_PMU_RC[3]" IO_TYPE=LVCMOS33 ;
+BLOCK JTAGPATHS ;
diff --git a/CPLD3/Reg_file.v b/CPLD3/Reg_file.v
new file mode 100644
index 0000000..8f00652
--- /dev/null
+++ b/CPLD3/Reg_file.v
@@ -0,0 +1,178 @@
+module Reg_file (
+    input i_sys_clk,
+    input i_rst_n,
+    
+    // Bus Interface
+    input i_wr_req,
+    input i_wr,
+    input [6:0] i_addr,
+    input [23:0] i_wdata,
+    
+    output [23:0] o_rdata,
+    output o_rvalid,
+    output o_busy,
+    output o_err,
+
+    // Controller Interface
+    input i_con_done,       // 1=IDLE/DONE, 0=BUSY
+    output o_exec,
+    
+    // Direct Register Outputs
+    output [23:0] o_freq1,
+    output [23:0] o_freq2,
+    output [23:0] o_freq3,
+    output [23:0] o_freq4,
+
+    //DC Regs
+    output [23:0] o_DC1,
+    output [23:0] o_DC2,
+    output [23:0] o_DC3,
+    output [23:0] o_DC4
+);
+
+    // --- Parameters ---
+    localparam REG_COUNT = 16;
+    localparam [23:0]
+        IDENT      = 24'h800000 | 12'b0001_0000_0000,            //CPLD3==1,version=1.0.0
+        STATE_INIT = 24'h800000;
+    
+    // State Machine Definition
+    localparam IDLE       = 4'd0;
+    localparam BUSY       = 4'd1;
+    localparam EXEC_ACK   = 4'd2; // Wait for controller to go BUSY (Done=0)
+    localparam EXEC_WAIT  = 4'd3; // Wait for controller to go DONE (Done=1)
+
+    // --- Internal Signals ---
+    reg [3:0] state;
+    reg [23:0] regtable [0:REG_COUNT - 1];
+    reg [23:0] rdata_reg;
+
+    reg busy_flag;
+    reg err_flag;
+    reg rvalid_flag;
+
+    integer i;
+
+    // Mapping Control Bits
+    wire exec_bit = regtable[1][0];
+    
+    always @(posedge i_sys_clk or negedge i_rst_n) begin
+        if (!i_rst_n) begin
+            for (i = 0; i < REG_COUNT; i = i + 1) begin
+                regtable[i] <= 24'h0;
+            end
+            regtable[0] <= IDENT;
+            regtable[1] <= STATE_INIT;
+            
+            rvalid_flag <= 1'b0;
+            busy_flag   <= 1'b0;
+            err_flag    <= 1'b0;
+            state       <= IDLE;
+        end
+        else begin
+            case (state)
+                IDLE: begin
+                    rvalid_flag <= 1'b0;
+                    err_flag    <= 1'b0;
+                    
+                    // Priority Check: Did we crash/reset while EXEC bit was still 1?
+                    if (exec_bit == 1'b1) begin
+                        state     <= EXEC_ACK;
+                        busy_flag <= 1'b1;
+                    end
+                    else if (i_wr_req == 1'b1) begin
+                        busy_flag <= 1'b1;
+                        state     <= BUSY;
+
+                        // Addr Sanity Check
+                        if ((i_wr && (i_addr == 'd0 || i_addr >= REG_COUNT)) || 
+                            (!i_wr && (i_addr >= REG_COUNT))) 
+                        begin
+                            err_flag <= 1'b1;
+                        end
+                    end
+                    else begin
+                        busy_flag <= 1'b0;
+                    end
+                end  
+
+                BUSY: begin
+                    if (err_flag) begin
+                        state <= IDLE;
+                    end
+                    else begin
+                        if (i_wr == 1'b1) begin // --- WRITE ---
+                            if (exec_bit == 1'b1) begin     
+                                // Cannot write if Controller is already running
+                                err_flag <= 1'b1;
+                                state    <= IDLE;
+                            end
+                            else begin
+                                regtable[i_addr] <= i_wdata;
+
+                                // Check if this write is a "Start Command"
+                                if (i_addr == 7'd1 && i_wdata[0] == 1'b1) begin
+                                    // Go to Handshake Start
+                                    state <= EXEC_ACK; 
+                                end else begin
+                                    state <= IDLE; 
+                                end
+                            end
+                        end
+                        else begin // --- READ ---
+                            rdata_reg   <= regtable[i_addr];
+                            rvalid_flag <= 1'b1;
+                            state       <= IDLE;
+                        end
+                    end
+                end
+
+                // --- EXEC PHASE 1: ACK ---
+                // Wait for Controller to register the command and pull 'done' LOW (Busy)
+                EXEC_ACK: begin
+                    busy_flag <= 1'b1;
+                    if (i_con_done == 1'b0) begin
+                        state <= EXEC_WAIT;
+                    end
+                    // Optional: Timeout counter here to prevent hanging if Controller is dead
+                end
+
+                // --- EXEC PHASE 2: WAIT ---
+                // Now wait for Controller to finish and pull 'done' HIGH (Idle/Ready)
+                EXEC_WAIT: begin
+                    busy_flag <= 1'b1;
+                    if (i_con_done == 1'b1) begin
+                        // 1. Clear the Exec bit (Auto-Clear)
+                        // 2. Set the Ready bit (Bit 23) if you wish
+                        regtable[1] <= {1'b1, regtable[1][22:1], 1'b0};
+                        
+                        busy_flag   <= 1'b0;
+                        state       <= IDLE;
+                    end
+                end
+
+                default: state <= IDLE;
+            endcase
+        end
+    end
+    
+    assign o_rvalid = rvalid_flag;
+    assign o_rdata  = rdata_reg;
+    assign o_busy   = busy_flag; 
+    assign o_err    = err_flag;
+    
+    // Output the control bit to the controller
+    // This stays HIGH during both EXEC_ACK and EXEC_WAIT
+    assign o_exec   = exec_bit;
+    
+    assign o_freq1  = regtable[2];
+    assign o_freq2  = regtable[3];
+    assign o_freq3  = regtable[4];
+    assign o_freq4  = regtable[5];
+
+    assign o_DC1    = regtable[6];
+    assign o_DC2    = regtable[7];
+    assign o_DC3    = regtable[8];
+    assign o_DC4    = regtable[9];
+
+endmodule
\ No newline at end of file
diff --git a/CPLD3/RelayConTop.v b/CPLD3/RelayConTop.v
new file mode 100644
index 0000000..9c7aeb6
--- /dev/null
+++ b/CPLD3/RelayConTop.v
@@ -0,0 +1,113 @@
+module RelayConTop (
+	input i_sys_clk,
+	input i_rst_n,
+	
+	input i_sclk,
+	input i_mosi,
+	input i_cs,
+	output o_miso,
+	output o_rvalid,
+	input i_rready,
+	input i_wvaild,
+
+	output [3:0]o_PMU_RC,
+
+	output o_wready,
+	output o_err,
+	output o_con_done
+);
+
+	wire [3:0]PMU_RC ;
+
+	wire [23:0]r_data ;
+	wire [23:0]w_data ;
+	wire [6:0]reg_addr ;
+
+	wire cmd_valid;
+	wire reg_busy;
+	wire wr_flag;						//1=write,0=read
+	wire bus_err_flag;
+	wire reg_err_flag;
+	wire cpld_err_flag;
+
+	wire con_exec;
+	wire [23:0]freq1_relay ;
+	wire [23:0]freq2_relay ;
+	wire [23:0]freq3_relay ;
+	wire [23:0]freq4_relay ;
+
+	//DC Control Reg output
+	wire [23:0]DC_Con1 ;
+	wire [23:0]DC_Con2 ;
+	wire [23:0]DC_Con3 ;
+	wire [23:0]DC_Con4 ;
+
+	wire con_rvaild;
+	wire con_done;
+
+	BUS_Con Bus_Con_3(
+		.i_sys_clk(i_sys_clk),
+		.i_rst_n(i_rst_n),
+		.i_sclk(i_sclk),
+		.i_mosi(i_mosi),
+		.i_cs(i_cs),
+		.i_rvalid(con_rvalid),
+		.i_wvalid(i_wvalid),
+		.i_reg_busy(reg_busy),
+		.i_rdata(r_data),
+		.o_cmd_valid(cmd_valid),
+		.o_wr(wr_flag),
+ 		.o_miso(o_miso),
+		.o_rvalid(o_rvalid),
+		.o_wready(o_wready),
+		.o_data(w_data),
+		.o_addr(reg_addr),
+		.o_err(bus_err_flag)
+	);
+
+	Reg_file CPLD_Reg_3(
+		.i_sys_clk(i_sys_clk),
+		.i_rst_n(i_rst_n),
+		.i_wr_req(cmd_valid),
+		.i_wr(wr_flag),
+		.i_addr(reg_addr),
+		.i_wdata(w_data),
+		.i_con_done(con_done),                               	//Controller Exec Done
+		.o_freq1(freq1_relay),                            		//Freq_Slot1
+		.o_freq2(freq2_relay),                            		//Freq_Slot2
+		.o_freq3(freq3_relay),                            		//Freq_Slot3 
+		.o_freq4(freq4_relay),									//Freq_Slot4
+		.o_DC1(DC_Con1),
+		.o_DC2(DC_Con2),
+		.o_DC3(DC_Con3),
+		.o_DC4(DC_Con4),
+		.o_rvalid(con_rvalid),
+		.o_rdata(r_data),
+		.o_exec(con_exec),                                  	//Exec cmd
+		.o_busy(reg_busy),
+		.o_err(reg_err_flag)
+	);
+	
+	CPLD_Con CPLD_Con_3(
+		.i_sys_clk(i_sys_clk),
+		.i_rst_n(i_rst_n),
+		.i_con_exec(con_exec),
+		.i_DC_Con1(DC_Con1),
+		.i_DC_Con2(DC_Con2),
+		.i_DC_Con3(DC_Con3),
+		.i_DC_Con4(DC_Con4),
+		.i_freq_relay1(freq1_relay),
+		.i_freq_relay2(freq2_relay),
+		.i_freq_relay3(freq3_relay),
+		.i_freq_relay4(freq4_relay),
+		.o_con_done(con_done),
+		.o_PMU_RC(PMU_RC),
+  		.o_err(cpld_err_flag)
+	);
+
+	assign o_con_done = con_done;
+	assign o_PMU_RC = PMU_RC;
+	
+	assign o_err = bus_err_flag || reg_err_flag ||cpld_err_flag;
+	
+endmodule
diff --git a/CPLD3/debug.rvl b/CPLD3/debug.rvl
new file mode 100644
index 0000000..9864e18
--- /dev/null
+++ b/CPLD3/debug.rvl
@@ -0,0 +1,134 @@
+<Project ModBy="Inserter" SigType="0" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD3/debug.rvl" Date="2026-05-26">
+    <IP Version="1_6_042617"/>
+    <Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD3"/>
+    <Core InsertDataset="0" Insert="1" Reveal_sig="695532996" Name="RelayConTop_LA0" ID="0">
+        <Setting>
+            <Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
+            <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
+            <Capture Mode="0" MinSamplesPerTrig="8"/>
+            <Event CntEnable="0" MaxEventCnt="8"/>
+            <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_RelayConTop_LA0_net"/>
+            <DistRAM Disable="0"/>
+        </Setting>
+        <Dataset Name="Base">
+            <Trace>
+                <Sig Type="SIG" Name="Bus_Con_3/i_sclk"/>
+                <Sig Type="SIG" Name="i_rst_n"/>
+                <Sig Type="SIG" Name="Bus_Con_3/i_cs"/>
+                <Sig Type="SIG" Name="Bus_Con_3/i_mosi"/>
+                <Sig Type="SIG" Name="Bus_Con_3/err_flag"/>
+                <Sig Type="SIG" Name="CPLD_Con_3/err_flag"/>
+                <Sig Type="SIG" Name="CPLD_Reg_3/err_flag"/>
+                <Sig Type="SIG" Name="CPLD_Con_3/i_con_exec"/>
+                <Bus Name="CPLD_Con_3/i_DC_Con1">
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:0"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:1"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:2"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:3"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:4"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:5"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:6"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:7"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:8"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:9"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:10"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:11"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:12"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:13"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:14"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:15"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:16"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:17"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:18"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:19"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:20"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:21"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:22"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:23"/>
+                </Bus>
+                <Bus Name="CPLD_Con_3/i_DC_Con2">
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:0"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:1"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:2"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:3"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:4"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:5"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:6"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:7"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:8"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:9"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:10"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:11"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:12"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:13"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:14"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:15"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:16"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:17"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:18"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:19"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:20"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:21"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:22"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:23"/>
+                </Bus>
+                <Bus Name="CPLD_Con_3/i_DC_Con3">
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:0"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:1"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:2"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:3"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:4"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:5"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:6"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:7"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:8"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:9"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:10"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:11"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:12"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:13"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:14"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:15"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:16"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:17"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:18"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:19"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:20"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:21"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:22"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:23"/>
+                </Bus>
+                <Bus Name="CPLD_Con_3/i_DC_Con4">
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:0"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:1"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:2"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:3"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:4"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:5"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:6"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:7"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:8"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:9"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:10"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:11"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:12"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:13"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:14"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:15"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:16"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:17"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:18"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:19"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:20"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:21"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:22"/>
+                    <Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:23"/>
+                </Bus>
+            </Trace>
+            <Trigger>
+                <TU Serialbits="0" Type="0" ID="1" Sig="con_exec,"/>
+                <TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
+            </Trigger>
+        </Dataset>
+    </Core>
+</Project>
diff --git a/CPLD3/tb_RelayConTop.sv b/CPLD3/tb_RelayConTop.sv
new file mode 100644
index 0000000..89ec2c6
--- /dev/null
+++ b/CPLD3/tb_RelayConTop.sv
@@ -0,0 +1,839 @@
+//------------------------------------------------------------------------------
+//
+//  Testbench: CPLD3 - RelayConTop
+//  Project:  NewCalBoard DIG
+//  Tool:     Lattice Diamond Verilog-2001 simulator
+//  Purpose:  Verify SPI interface, register file, and PMU relay control logic
+//            for CPLD3 (PMU_RC[3:0] only).
+//
+//  CPLD3-specific:
+//    - Outputs: PMU_RC[3:0] only (PMU relay control)
+//    - CPLD_Con handles PMU_RC only (no relay outputs, no DC handling)
+//    - Minimal CPLD_Con: freq slot masks 2 PMU channels, DC slot selects 1
+//
+//  Architecture (3 sub-modules):
+//    RelayConTop
+//    - BUS_Con - SPI Mode 0 master interface (32-bit transactions)
+//    - Reg_file - 16-register file + execution FSM
+//    - CPLD_Con - PMU_RC relay control logic
+//
+//  SPI Protocol:
+//    Frame: [WR:1][Addr:7][Data:24]  (MSB first, CPOL=0 CPHA=0)
+//    Read response: [8'h00][24-bit rdata]
+//
+//------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+
+`define SYS_CLK_PERIOD  20     // 50 MHz system clock
+`define SPI_CLK_PERIOD  400    // 1 MHz SPI clock (200x slower than sys clk)
+
+module tb_RelayConTop;
+
+    //==========================================================================
+    // Signal declarations - mirrors CPLD3 RelayConTop pinout
+    //==========================================================================
+
+    // Clock & reset
+    reg             i_sys_clk;
+    reg             i_rst_n;
+
+    // SPI interface (Zynq PS drives these)
+    reg             i_sclk;
+    reg             i_mosi;
+    reg             i_cs;
+
+    // Flow control (CPLD3 top module uses typo: i_wvaild)
+    reg             i_rready;
+    reg             i_wvaild;
+
+    // Status outputs (monitored by testbench)
+    wire            o_miso;
+    wire            o_rvalid;
+    wire            o_wready;
+    wire            o_err;
+    wire            o_con_done;
+
+    // PMU relay control (CPLD3 specific)
+    wire    [3:0]   o_PMU_RC;     // PMU relay control (4-bit)
+
+
+    //==========================================================================
+    // DUT instantiation - CPLD3 specific pin names
+    // Note: CPLD3 top module port: i_wvaild (typo), o_rvalid (correct)
+    //==========================================================================
+    RelayConTop DUT (
+        .i_sys_clk  (i_sys_clk),
+        .i_rst_n    (i_rst_n),
+        .i_sclk     (i_sclk),
+        .i_mosi     (i_mosi),
+        .i_cs       (i_cs),
+        .o_miso     (o_miso),
+        .o_rvalid   (o_rvalid),
+        .i_rready   (i_rready),
+        .i_wvaild   (i_wvaild),
+        .o_wready   (o_wready),
+        .o_err      (o_err),
+        .o_con_done (o_con_done),
+        .o_PMU_RC   (o_PMU_RC)
+    );
+
+
+    //==========================================================================
+    // Clock generation
+    //==========================================================================
+
+    // System clock: 50 MHz (period = 20 ns)
+    initial begin
+        i_sys_clk = 0;
+        forever #(`SYS_CLK_PERIOD / 2) i_sys_clk = ~i_sys_clk;
+    end
+
+    // SPI clock: 1 MHz (period = 400 ns)
+    initial begin
+        i_sclk = 0;
+        forever #(`SPI_CLK_PERIOD / 2) i_sclk = ~i_sclk;
+    end
+
+
+    //==========================================================================
+    // Test statistics
+    //==========================================================================
+    integer test_pass;
+    integer test_fail;
+    integer test_num;
+
+    initial begin
+        test_pass = 0;
+        test_fail = 0;
+        test_num  = 0;
+    end
+
+    // Helper: log a pass
+    task tb_pass;
+        input string msg;
+        begin
+            test_pass = test_pass + 1;
+            $display("[PASS] Test %0d: %s", test_num, msg);
+        end
+    endtask
+
+    // Helper: log a fail with optional detail
+    task tb_fail;
+        input string msg;
+        input string detail;
+        begin
+            test_fail = test_fail + 1;
+            $display("[FAIL] Test %0d: %s  >> %s", test_num, msg, detail);
+        end
+    endtask
+
+    // Helper: assert a condition
+    task tb_assert;
+        input              condition;
+        input string       msg;
+        input string       detail;
+        begin
+            test_num = test_num + 1;
+            if (condition) begin
+                tb_pass(msg);
+            end else begin
+                tb_fail(msg, detail);
+            end
+        end
+    endtask
+
+
+    //==========================================================================
+    // SPI helper tasks
+    //
+    // SPI Mode 0 timing:
+    //   - CPOL = 0: SCLK idle LOW
+    //   - CPHA = 0: data sampled on RISING edge, shifted on FALLING edge
+    //   - MSB first, 32 bits per transaction
+    //
+    // Frame layout:  [bit31: WR] [bit30:24: Addr(7b)] [bit23:0: Data(24b)]
+    // Read response: [8'h00][24-bit rdata] shifted out on falling SCLK edges
+    //
+    // MISO is tri-stated (high-Z) when CS is HIGH.
+    //==========================================================================
+
+    // --- spi_send: Drive a 32-bit word out through MOSI ---
+    task spi_send;
+        input [31:0] data;
+        integer      i;
+        begin
+            @(negedge i_sclk);
+            i_cs   = 1'b0;
+            @(negedge i_sclk);
+
+            for (i = 31; i >= 0; i = i - 1) begin
+                i_mosi = data[i];
+                @(posedge i_sclk);
+            end
+
+            @(negedge i_sclk);
+            i_cs   = 1'b1;
+            i_mosi = 1'b0;
+            @(negedge i_sclk);
+        end
+    endtask
+
+    // --- spi_read: Send command, capture 32-bit response on MISO ---
+    task spi_read;
+        input  [31:0]  cmd;
+        output [31:0]  rdata;
+        integer        i;
+        begin
+            @(negedge i_sclk);
+            i_cs   = 1'b0;
+            @(negedge i_sclk);
+
+            rdata = 32'b0;
+            for (i = 31; i >= 0; i = i - 1) begin
+                i_mosi = cmd[i];
+                @(posedge i_sclk);
+                @(negedge i_sclk);
+                #1;
+                rdata[i] = o_miso;
+            end
+
+            @(negedge i_sclk);
+            i_cs   = 1'b1;
+            i_mosi = 1'b0;
+            @(negedge i_sclk);
+        end
+    endtask
+
+    // --- spi_write: Send a write command (no response capture needed) ---
+    task spi_write;
+        input [31:0] data;
+        begin
+            spi_send(data);
+        end
+    endtask
+
+    // --- wait_con_done: Poll con_done for LOW->HIGH cycle ---
+    task wait_con_done;
+        input  [15:0] max_cycles;
+        output [1:0]  result;
+        integer       i;
+        begin
+            result = 2'b0;
+
+            // Phase 1: Wait for con_done to go LOW (exec started)
+            for (i = 0; i < max_cycles; i = i + 1) begin
+                #(`SYS_CLK_PERIOD);
+                if (!o_con_done) break;
+            end
+
+            // Phase 2: Wait for con_done to go HIGH (exec finished)
+            for (i = 0; i < max_cycles; i = i + 1) begin
+                #(`SYS_CLK_PERIOD);
+                if (o_con_done) begin
+                    result = 2'b1;
+                    return;
+                end
+            end
+        end
+    endtask
+
+    // --- wait_wready: Poll o_wready until HIGH ---
+    task wait_wready;
+        input  [15:0] max_cycles;
+        output [1:0]  result;
+        integer       i;
+        begin
+            result = 2'b0;
+            for (i = 0; i < max_cycles; i = i + 1) begin
+                #(`SYS_CLK_PERIOD);
+                if (o_wready) begin
+                    result = 2'b1;
+                    return;
+                end
+            end
+        end
+    endtask
+
+
+    //==========================================================================
+    // Convenience: build SPI frame fields
+    //==========================================================================
+    function [31:0] mk_write;
+        input [6:0] addr;
+        input [23:0] data;
+        begin
+            mk_write = {1'b1, addr, data};
+        end
+    endfunction
+
+    function [31:0] mk_read;
+        input [6:0] addr;
+        begin
+            mk_read = {1'b0, addr, 24'b0};
+        end
+    endfunction
+
+
+    //==========================================================================
+    // Main test sequence
+    //==========================================================================
+    initial begin
+        // Initialize all signals to safe defaults
+        i_rst_n     = 1'b0;
+        i_cs        = 1'b1;
+        i_mosi      = 1'b0;
+        i_rready    = 1'b0;
+        i_wvaild    = 1'b0;
+
+        // Hold reset for 4 system clock cycles (80 ns)
+        #(`SYS_CLK_PERIOD * 4);
+        i_rst_n = 1'b1;
+
+        // Allow CPLD internal state machines to settle
+        #(`SYS_CLK_PERIOD * 10);
+
+        $display("");
+        $display("=============================================================");
+        $display("  CPLD3 RelayConTop - Comprehensive Testbench");
+        $display("  System clock: %d MHz | SPI clock: %d MHz",
+                 1000 / `SYS_CLK_PERIOD, 1000 / `SPI_CLK_PERIOD);
+        $display("  Outputs: PMU_RC[3:0] (PMU relay control)");
+        $display("=============================================================");
+        $display("");
+
+        test_reset_behavior();
+        test_register_rw();
+        test_exec_protocol();
+        test_pmu_rc_freq_slots();
+        test_pmu_rc_dc_slots();
+        test_error_conditions();
+        test_edge_cases();
+
+        print_summary();
+
+        #(`SYS_CLK_PERIOD * 20);
+        $finish;
+    end
+
+
+    //==========================================================================
+    // Test Group 1: Reset behavior & IDENT register (ADDR 0)
+    //==========================================================================
+    task test_reset_behavior;
+        reg [31:0] r_ident;
+        begin
+            $display("-------------------------------------------------------------");
+            $display("  Group 1: Reset behavior & IDENT register");
+            $display("-------------------------------------------------------------");
+
+            tb_assert(o_con_done === 1'b1,
+                "o_con_done is HIGH after reset (controller idle)", "");
+
+            tb_assert(o_err === 1'b0,
+                "o_err is LOW after reset", "");
+
+            tb_assert(o_wready === 1'b1,
+                "o_wready is HIGH after reset (SPI ready)", "");
+
+            // IDENT register: CPLD3=bit23, version=1.0.0 = 24'h800100
+            spi_read(mk_read(7'd0), r_ident);
+            r_ident = r_ident[23:0];
+            tb_assert(r_ident === 24'h800100,
+                "IDENT register returns 24'h800100 (CPLD3, v1.0.0)", "");
+
+            // PMU_RC should be 4'b1111 after reset (CPLD_Con initializes to 1111)
+            tb_assert(o_PMU_RC === 4'b1111,
+                "o_PMU_RC is 4'b1111 after reset (initial state)", "");
+
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    //==========================================================================
+    // Test Group 2: Register read/write (ADDR 0-9)
+    //==========================================================================
+    task test_register_rw;
+        reg [31:0] rdata;
+        begin
+            $display("");
+            $display("-------------------------------------------------------------");
+            $display("  Group 2: Register read/write (ADDR 0-9)");
+            $display("-------------------------------------------------------------");
+
+            spi_write(mk_write(7'd2, 24'h000005));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd2), rdata);
+            tb_assert(rdata === 24'h000005,
+                "Freq_Slot1 (ADDR 2) write/read back", "");
+
+            spi_write(mk_write(7'd3, 24'h003001));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd3), rdata);
+            tb_assert(rdata === 24'h003001,
+                "Freq_Slot2 (ADDR 3) write/read back", "");
+
+            spi_write(mk_write(7'd4, 24'h001040));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd4), rdata);
+            tb_assert(rdata === 24'h001040,
+                "Freq_Slot3 (ADDR 4) write/read back", "");
+
+            spi_write(mk_write(7'd5, 24'h000802));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd5), rdata);
+            tb_assert(rdata === 24'h000802,
+                "Freq_Slot4 (ADDR 5) write/read back", "");
+
+            spi_write(mk_write(7'd6, 24'h002003));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd6), rdata);
+            tb_assert(rdata === 24'h002003,
+                "DC_Slot1 (ADDR 6) write/read back", "");
+
+            spi_write(mk_write(7'd7, 24'h004005));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd7), rdata);
+            tb_assert(rdata === 24'h004005,
+                "DC_Slot2 (ADDR 7) write/read back", "");
+
+            spi_write(mk_write(7'd8, 24'h006007));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd8), rdata);
+            tb_assert(rdata === 24'h006007,
+                "DC_Slot3 (ADDR 8) write/read back", "");
+
+            spi_write(mk_write(7'd9, 24'h008009));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd9), rdata);
+            tb_assert(rdata === 24'h008009,
+                "DC_Slot4 (ADDR 9) write/read back", "");
+
+            spi_read(mk_read(7'd1), rdata);
+            tb_assert(rdata === 24'h800000,
+                "STATE register (ADDR 1) default (RDY=1)", "");
+
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    //==========================================================================
+    // Test Group 3: Execution protocol
+    //==========================================================================
+    task test_exec_protocol;
+        reg [1:0] done_result;
+        begin
+            $display("");
+            $display("-------------------------------------------------------------");
+            $display("  Group 3: Execution protocol");
+            $display("-------------------------------------------------------------");
+
+            // Configure and trigger execution with Freq_Slot1
+            spi_write(mk_write(7'd2, 24'h000005));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));  // EXEC=1
+            @(negedge i_sclk);
+
+            wait_con_done(500, done_result);
+            tb_assert(done_result === 1'b1,
+                "con_done goes HIGH after execution completes", "");
+
+            tb_assert(o_err === 1'b0,
+                "No error flag set after successful execution", "");
+
+            wait_wready(100, done_result);
+            tb_assert(done_result === 1'b1,
+                "o_wready is HIGH after execution (SPI ready)", "");
+
+            // Execute with DC_Slot1
+            spi_write(mk_write(7'd6, 24'h002003));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_result);
+            tb_assert(done_result === 1'b1,
+                "DC slot execution completes successfully", "");
+            tb_assert(o_err === 1'b0,
+                "No error after DC slot execution", "");
+
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    //==========================================================================
+    // Test Group 4: PMU_RC freq slot decoding
+    //
+    // CPLD3 CPLD_Con PMU_RC logic (frequency mode):
+    //   Slot1 (freq_slot_flag=0001): PMU_RC = 4'b1111  (mask all 4 PMU)
+    //   Slot2 (freq_slot_flag=0010): PMU_RC = 4'b1100  (mask PMU 3,4)
+    //   Slot3 (freq_slot_flag=0100): PMU_RC = 4'b1010  (mask PMU 1,3)
+    //   Slot4 (freq_slot_flag=1000): PMU_RC = 4'b0110  (mask PMU 2,4)
+    //
+    // CPLD3 CPLD_Con PMU_RC logic (DC mode):
+    //   Slot1 (dc_slot_flag=0001): PMU_RC = 4'b0001  (select PMU 1)
+    //   Slot2 (dc_slot_flag=0010): PMU_RC = 4'b0010  (select PMU 2)
+    //   Slot3 (dc_slot_flag=0100): PMU_RC = 4'b0100  (select PMU 3)
+    //   Slot4 (dc_slot_flag=1000): PMU_RC = 4'b1000  (select PMU 4)
+    //
+    // Note: PMU_RC is 4-bit where each bit represents a PMU channel.
+    //   Freq mode: bits are MASK bits (1 = disabled/masked)
+    //   DC mode: bits are SELECT bits (1 = selected channel)
+    //==========================================================================
+    task test_pmu_rc_freq_slots;
+        reg [1:0] done_r;
+        begin
+            $display("");
+            $display("-------------------------------------------------------------");
+            $display("  Group 4: PMU_RC freq slot decoding");
+            $display("-------------------------------------------------------------");
+
+            // 4a. Freq_Slot1: PMU_RC = 4'b1111 (all masked)
+            // Freq_Slot1 = (0<<10) | (5<<1) | 1 = 24'h000005
+            $display("  Freq Slot1: PMU_RC = 1111 (all masked)");
+            spi_write(mk_write(7'd2, 24'h000005));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Freq Slot1 exec done", "timeout");
+            tb_assert(o_PMU_RC === 4'b1111,
+                "Freq Slot1: PMU_RC = 4'b1111",
+                $sformatf("PMU_RC=%b", o_PMU_RC));
+
+            // 4b. Freq_Slot2: PMU_RC = 4'b1100 (mask PMU 3,4)
+            // Freq_Slot2 = (0<<10) | (5<<1) | 1 = 24'h000006
+            $display("  Freq Slot2: PMU_RC = 1100 (mask PMU3,4)");
+            spi_write(mk_write(7'd3, 24'h000006));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Freq Slot2 exec done", "timeout");
+            tb_assert(o_PMU_RC === 4'b1100,
+                "Freq Slot2: PMU_RC = 4'b1100",
+                $sformatf("PMU_RC=%b", o_PMU_RC));
+
+            // 4c. Freq_Slot3: PMU_RC = 4'b1010 (mask PMU 1,3)
+            // Freq_Slot3 = (0<<10) | (5<<1) | 1 = 24'h000007
+            $display("  Freq Slot3: PMU_RC = 1010 (mask PMU1,3)");
+            spi_write(mk_write(7'd4, 24'h000007));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Freq Slot3 exec done", "timeout");
+            tb_assert(o_PMU_RC === 4'b1010,
+                "Freq Slot3: PMU_RC = 4'b1010",
+                $sformatf("PMU_RC=%b", o_PMU_RC));
+
+            // 4d. Freq_Slot4: PMU_RC = 4'b0110 (mask PMU 2,4)
+            // Freq_Slot4 = (0<<10) | (5<<1) | 1 = 24'h000008
+            $display("  Freq Slot4: PMU_RC = 0110 (mask PMU2,4)");
+            spi_write(mk_write(7'd5, 24'h000008));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Freq Slot4 exec done", "timeout");
+            tb_assert(o_PMU_RC === 4'b0110,
+                "Freq Slot4: PMU_RC = 4'b0110",
+                $sformatf("PMU_RC=%b", o_PMU_RC));
+
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    //==========================================================================
+    // Test Group 5: PMU_RC DC slot decoding
+    //
+    // CPLD3 CPLD_Con PMU_RC logic (DC mode):
+    //   Slot1: PMU_RC = 4'b0001 (select PMU 1)
+    //   Slot2: PMU_RC = 4'b0010 (select PMU 2)
+    //   Slot3: PMU_RC = 4'b0100 (select PMU 3)
+    //   Slot4: PMU_RC = 4'b1000 (select PMU 4)
+    //
+    // DC_Slot N bit layout:
+    //   Bit 23: PMU(0)/DPS(1)
+    //   Bit 22: V(0)/I(1)
+    //   Bit 21:17: Rload_Sel (0-31)
+    //   Bit 9:1: Channel_Number (1-256)
+    //   Bit 0: Slot_EN (1=Enable)
+    //==========================================================================
+    task test_pmu_rc_dc_slots;
+        reg [1:0] done_r;
+        begin
+            $display("");
+            $display("-------------------------------------------------------------");
+            $display("  Group 5: PMU_RC DC slot decoding");
+            $display("-------------------------------------------------------------");
+
+            // 5a. DC_Slot1: PMU_RC = 4'b0001 (select PMU 1)
+            // DC_Slot1 = PMU mode, V mode, Rload=3, Ch=3
+            // = (0<<23) | (0<<22) | (3<<17) | (3<<1) | 1 = 24'h060007
+            $display("  DC Slot1: PMU_RC = 0001 (select PMU1)");
+            spi_write(mk_write(7'd6, 24'h060007));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "DC Slot1 exec done", "timeout");
+            tb_assert(o_PMU_RC === 4'b0001,
+                "DC Slot1: PMU_RC = 4'b0001",
+                $sformatf("PMU_RC=%b", o_PMU_RC));
+
+            // 5b. DC_Slot2: PMU_RC = 4'b0010 (select PMU 2)
+            // DC_Slot2 = PMU mode, V mode, Rload=5, Ch=19
+            // = (0<<23) | (0<<22) | (5<<17) | (19<<1) | 1 = 24'h0A0027
+            $display("  DC Slot2: PMU_RC = 0010 (select PMU2)");
+            spi_write(mk_write(7'd7, 24'h0A0027));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "DC Slot2 exec done", "timeout");
+            tb_assert(o_PMU_RC === 4'b0010,
+                "DC Slot2: PMU_RC = 4'b0010",
+                $sformatf("PMU_RC=%b", o_PMU_RC));
+
+            // 5c. DC_Slot3: PMU_RC = 4'b0100 (select PMU 3)
+            // DC_Slot3 = PMU mode, V mode, Rload=10, Ch=27
+            // = (0<<23) | (0<<22) | (10<<17) | (27<<1) | 1 = 24'h140037
+            $display("  DC Slot3: PMU_RC = 0100 (select PMU3)");
+            spi_write(mk_write(7'd8, 24'h140037));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "DC Slot3 exec done", "timeout");
+            tb_assert(o_PMU_RC === 4'b0100,
+                "DC Slot3: PMU_RC = 4'b0100",
+                $sformatf("PMU_RC=%b", o_PMU_RC));
+
+            // 5d. DC_Slot4: PMU_RC = 4'b1000 (select PMU 4)
+            // DC_Slot4 = PMU mode, V mode, Rload=18, Ch=35
+            // = (0<<23) | (0<<22) | (18<<17) | (35<<1) | 1 = 24'h240047
+            $display("  DC Slot4: PMU_RC = 1000 (select PMU4)");
+            spi_write(mk_write(7'd9, 24'h240047));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "DC Slot4 exec done", "timeout");
+            tb_assert(o_PMU_RC === 4'b1000,
+                "DC Slot4: PMU_RC = 4'b1000",
+                $sformatf("PMU_RC=%b", o_PMU_RC));
+
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    //==========================================================================
+    // Test Group 6: Error conditions
+    //==========================================================================
+    task test_error_conditions;
+        reg [1:0] done_r;
+        reg [31:0] rdata;
+        begin
+            $display("");
+            $display("-------------------------------------------------------------");
+            $display("  Group 6: Error conditions");
+            $display("-------------------------------------------------------------");
+
+            // 6a. Short SPI transaction (16 bits)
+            $display("  Error 6a: Short SPI transaction (16 bits)");
+            i_cs = 1'b0;
+            @(negedge i_sclk);
+            @(negedge i_sclk);
+            for (integer bi = 0; bi < 16; bi = bi + 1) begin
+                i_mosi = 1'b0;
+                @(posedge i_sclk);
+                @(negedge i_sclk);
+            end
+            i_cs = 1'b1;
+            @(negedge i_sclk);
+            #(`SYS_CLK_PERIOD * 5);
+            tb_assert(o_err === 1'b1,
+                "o_err HIGH after short SPI transaction", "");
+            i_rst_n = 1'b0;
+            #(`SYS_CLK_PERIOD * 4);
+            i_rst_n = 1'b1;
+            #(`SYS_CLK_PERIOD * 4);
+            tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
+
+            #(`SPI_CLK_PERIOD);
+
+            // 6b. Write to IDENT register (ADDR 0, read-only)
+            $display("  Error 6b: Write to IDENT register (ADDR 0)");
+            spi_write(mk_write(7'd0, 24'hDEADBEE >> 8));
+            @(negedge i_sclk);
+            tb_assert(o_err === 1'b1,
+                "o_err HIGH after write to IDENT register", "");
+            i_rst_n = 1'b0;
+            #(`SYS_CLK_PERIOD * 4);
+            i_rst_n = 1'b1;
+            #(`SYS_CLK_PERIOD * 4);
+            tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
+
+            #(`SPI_CLK_PERIOD);
+
+            // 6c. Read out-of-bounds address (ADDR 16)
+            $display("  Error 6c: Read out-of-bounds address (ADDR 16)");
+            spi_read(mk_read(7'd16), rdata);
+            @(negedge i_sclk);
+            #(`SYS_CLK_PERIOD * 5);
+            tb_assert(o_err === 1'b1,
+                "o_err HIGH after reading ADDR 16", "");
+            i_rst_n = 1'b0;
+            #(`SYS_CLK_PERIOD * 4);
+            i_rst_n = 1'b1;
+            #(`SYS_CLK_PERIOD * 4);
+            tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
+
+            #(`SPI_CLK_PERIOD);
+
+            // 6d. Multiple slot enable bits (en_t > 1)
+            $display("  Error 6d: Multiple slot enable bits");
+            spi_write(mk_write(7'd2, 24'h000005));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd3, 24'h000006));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));
+            @(negedge i_sclk);
+            wait_con_done(500, done_r);
+            tb_assert(done_r === 1'b1, "Execution completes (even with error)", "");
+            tb_assert(o_err === 1'b1,
+                "o_err HIGH with multiple slot enables", "");
+            i_rst_n = 1'b0;
+            #(`SYS_CLK_PERIOD * 4);
+            i_rst_n = 1'b1;
+            #(`SYS_CLK_PERIOD * 4);
+            tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
+
+            #(`SPI_CLK_PERIOD);
+
+            // 6e. Write to out-of-bounds address (ADDR 31)
+            $display("  Error 6e: Write to out-of-bounds address (ADDR 31)");
+            spi_write(mk_write(7'd31, 24'h123456));
+            @(negedge i_sclk);
+            #(`SYS_CLK_PERIOD * 5);
+            tb_assert(o_err === 1'b1,
+                "o_err HIGH after writing ADDR 31", "");
+            i_rst_n = 1'b0;
+            #(`SYS_CLK_PERIOD * 4);
+            i_rst_n = 1'b1;
+            #(`SYS_CLK_PERIOD * 4);
+            tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
+
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    //==========================================================================
+    // Test Group 7: Edge cases
+    //==========================================================================
+    task test_edge_cases;
+        reg [31:0] rdata;
+        begin
+            $display("");
+            $display("-------------------------------------------------------------");
+            $display("  Group 7: Edge cases");
+            $display("-------------------------------------------------------------");
+
+            // 7a. Brief CS pulse (too short for 32-bit)
+            $display("  Edge 7a: Brief CS pulse");
+            i_cs = 1'b0;
+            @(negedge i_sclk);
+            @(negedge i_sclk);
+            i_cs = 1'b1;
+            @(negedge i_sclk);
+            #(`SYS_CLK_PERIOD * 5);
+            tb_assert(o_err === 1'b1,
+                "o_err detected brief CS pulse", "");
+            i_rst_n = 1'b0;
+            #(`SYS_CLK_PERIOD * 4);
+            i_rst_n = 1'b1;
+            #(`SYS_CLK_PERIOD * 4);
+            tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
+
+            #(`SPI_CLK_PERIOD);
+
+            // 7b. Rapid successive SPI writes
+            $display("  Edge 7b: Rapid successive SPI writes");
+            spi_write(mk_write(7'd2, 24'h000001));
+            spi_write(mk_write(7'd3, 24'h000002));
+            spi_write(mk_write(7'd4, 24'h000003));
+            spi_write(mk_write(7'd5, 24'h000004));
+            @(negedge i_sclk);
+            spi_read(mk_read(7'd2), rdata);
+            tb_assert(rdata === 24'h000001, "Rapid write: ADDR 2 correct", "ADDR 2 mismatch");
+            spi_read(mk_read(7'd3), rdata);
+            tb_assert(rdata === 24'h000002, "Rapid write: ADDR 3 correct", "ADDR 3 mismatch");
+            spi_read(mk_read(7'd4), rdata);
+            tb_assert(rdata === 24'h000003, "Rapid write: ADDR 4 correct", "ADDR 4 mismatch");
+            spi_read(mk_read(7'd5), rdata);
+            tb_assert(rdata === 24'h000004, "Rapid write: ADDR 5 correct", "ADDR 5 mismatch");
+
+            #(`SPI_CLK_PERIOD);
+
+            // 7c. Write to reserved registers (ADDR 10-15) - no error
+            $display("  Edge 7c: Write to reserved registers");
+            spi_write(mk_write(7'd10, 24'hABCDEF));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd15, 24'h123456));
+            @(negedge i_sclk);
+            tb_assert(o_err === 1'b0, "No error writing to reserved ADDR 10 and 15",
+                "Unexpected error");
+
+            // 7d. Write STATE with EXEC=1 while already executing (should error)
+            $display("  Edge 7d: Write STATE while already executing");
+            spi_write(mk_write(7'd2, 24'h000005));
+            @(negedge i_sclk);
+            spi_write(mk_write(7'd1, 24'h000001));  // EXEC=1
+            @(negedge i_sclk);
+            // Try to write another register while EXEC is still active
+            spi_write(mk_write(7'd3, 24'h000006));
+            @(negedge i_sclk);
+            #(`SYS_CLK_PERIOD * 5);
+            tb_assert(o_err === 1'b1,
+                "o_err HIGH when writing during execution", "");
+            i_rst_n = 1'b0;
+            #(`SYS_CLK_PERIOD * 4);
+            i_rst_n = 1'b1;
+            #(`SYS_CLK_PERIOD * 4);
+            tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
+
+            #(`SPI_CLK_PERIOD * 2);
+        end
+    endtask
+
+
+    //==========================================================================
+    // Summary
+    //==========================================================================
+    task print_summary;
+        begin
+            $display("");
+            $display("=============================================================");
+            $display("  Test Summary");
+            $display("=============================================================");
+            $display("  Total tests: %0d", test_pass + test_fail);
+            $display("  Passed:      %0d", test_pass);
+            $display("  Failed:      %0d", test_fail);
+            $display("=============================================================");
+            if (test_fail == 0) begin
+                $display("  *** ALL TESTS PASSED ***");
+            end else begin
+                $display("  *** SOME TESTS FAILED - CHECK DESIGN ***");
+            end
+            $display("=============================================================");
+            $display("");
+        end
+    endtask
+
+endmodule