202 lines
4.5 KiB
Verilog
202 lines
4.5 KiB
Verilog
module RelayConTop (
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input i_sys_clk,
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input i_rst_n,
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input i_sclk,
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input i_mosi,
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input i_cs,
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output o_miso,
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//output o_rvalid,
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input i_rready,
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input i_wvalid,
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output o_wready,
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output o_err,
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output o_con_done,
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output [18:0]o_DMM_EN,
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output o_IO_RC1,
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output o_RC_T27,
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output o_RC_T28,
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output o_RC_T29,
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output o_RC_T30,
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output o_RC_T31,
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output o_RC_T32,
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output [17:0]o_RC_RLSel,
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output o_RC_VSel,
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output o_RC_ISel,
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output [1:0]o_RC_LOF, //Strange DMM_N port relay
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output [1:0]o_RC_LOS,
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output [31:0]o_PMU_OC_1,
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output [31:0]o_PMU_OC_2,
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output [31:0]o_PMU_OC_3,
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output [31:0]o_PMU_OC_4
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);
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wire [3:0]OC_x01;
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wire [3:0]OC_x17;
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wire [5:0]RC_Tx;
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wire [18:0]DMM_EN;
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wire IO_RC1;
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wire [23:0]r_data ;
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wire [23:0]w_data ;
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wire [6:0]reg_addr ;
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wire cmd_valid;
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wire reg_busy;
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wire wr_flag; //1=write,0=read
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wire bus_err_flag;
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wire reg_err_flag;
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wire cpld_err_flag;
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wire con_exec;
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wire [23:0]freq1_relay ;
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wire [23:0]freq2_relay ;
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wire [23:0]freq3_relay ;
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wire [23:0]freq4_relay ;
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//DC Control Reg output
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wire [23:0]DC_Con1 ;
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wire [23:0]DC_Con2 ;
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wire [23:0]DC_Con3 ;
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wire [23:0]DC_Con4 ;
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//PMU OC Control
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wire [31:0]PMU_OC_1 ;
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wire [31:0]PMU_OC_2 ;
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wire [31:0]PMU_OC_3 ;
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wire [31:0]PMU_OC_4 ;
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//RL Control
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wire [17:0]RC_RLSel ;
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//DMM V Select
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wire RC_VSel;
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//DMM I Select
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wire RC_ISel;
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wire con_rvalid;
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wire con_done;
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BUS_Con BUS_Con_1(
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.i_sys_clk(i_sys_clk),
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.i_rst_n(i_rst_n),
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.i_sclk(i_sclk),
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.i_mosi(i_mosi),
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.i_cs(i_cs),
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.i_rvalid(con_rvalid),
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.i_wvalid(i_wvalid),
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.i_reg_busy(reg_busy),
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.i_rdata(r_data),
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.o_cmd_valid(cmd_valid),
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.o_wr(wr_flag),
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.o_miso(o_miso),
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.o_rvalid(o_rvalid),
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.o_wready(o_wready),
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.o_data(w_data),
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.o_addr(reg_addr),
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.o_err(bus_err_flag)
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);
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Reg_file CPLD_Reg_1(
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.i_sys_clk(i_sys_clk),
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.i_rst_n(i_rst_n),
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.i_wr_req(cmd_valid),
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.i_wr(wr_flag),
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.i_addr(reg_addr),
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.i_wdata(w_data),
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.i_con_done(con_done), //Controller Exec Done
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.o_freq1(freq1_relay), //Freq_Slot1
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.o_freq2(freq2_relay), //Freq_Slot2
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.o_freq3(freq3_relay), //Freq_Slot3
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.o_freq4(freq4_relay), //Freq_Slot4
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.o_DC1(DC_Con1),
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.o_DC2(DC_Con2),
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.o_DC3(DC_Con3),
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.o_DC4(DC_Con4),
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.o_rvalid(con_rvalid),
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.o_rdata(r_data),
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.o_exec(con_exec), //Exec cmd
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.o_busy(reg_busy),
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.o_err(reg_err_flag)
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);
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CPLD_Con CPLD_Con_1(
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.i_sys_clk(i_sys_clk),
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.i_rst_n(i_rst_n),
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.i_con_exec(con_exec),
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.i_freq_relay1(freq1_relay),
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.i_freq_relay2(freq2_relay),
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.i_freq_relay3(freq3_relay),
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.i_freq_relay4(freq4_relay),
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.i_DC_Con1(DC_Con1),
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.i_DC_Con2(DC_Con2),
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.i_DC_Con3(DC_Con3),
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.i_DC_Con4(DC_Con4),
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.o_con_done(con_done),
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.o_OC_x01(OC_x01),
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.o_OC_x17(OC_x17),
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.o_RC_Tx(RC_Tx),
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.o_DMM_EN(DMM_EN),
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.o_PMU_OC_1(PMU_OC_1),
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.o_PMU_OC_2(PMU_OC_2),
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.o_PMU_OC_3(PMU_OC_3),
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.o_PMU_OC_4(PMU_OC_4),
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.o_RC_VSel(RC_VSel),
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.o_RC_ISel(RC_ISel),
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.o_RC_RLSel(RC_RLSel),
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.o_IO_RC1(IO_RC1),
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.o_err(cpld_err_flag)
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);
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assign o_con_done = con_done;
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//assign o_OC_x01 = OC_x01;
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assign o_PMU_OC_1[0] = OC_x01[0];
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assign o_PMU_OC_2[0] = OC_x01[1];
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assign o_PMU_OC_3[0] = OC_x01[2];
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assign o_PMU_OC_4[0] = OC_x01[3];
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//assign o_OC_x17 = OC_x17;
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assign o_PMU_OC_1[16] = OC_x17[0];
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assign o_PMU_OC_2[16] = OC_x17[1];
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assign o_PMU_OC_3[16] = OC_x17[2];
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assign o_PMU_OC_4[16] = OC_x17[3];
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assign o_PMU_OC_1[15:1] = PMU_OC_1[15:1];
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assign o_PMU_OC_1[31:17] = PMU_OC_1[31:17];
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assign o_PMU_OC_2[15:1] = PMU_OC_2[15:1];
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assign o_PMU_OC_2[31:17] = PMU_OC_2[31:17];
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assign o_PMU_OC_3[15:1] = PMU_OC_3[15:1];
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assign o_PMU_OC_3[31:17] = PMU_OC_3[31:17];
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assign o_PMU_OC_4[15:1] = PMU_OC_4[15:1];
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assign o_PMU_OC_4[31:17] = PMU_OC_4[31:17];
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assign o_DMM_EN = DMM_EN;
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assign o_IO_RC1 = IO_RC1;
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assign o_RC_T27 = RC_Tx[5];
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assign o_RC_T28 = RC_Tx[4];
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assign o_RC_T29 = RC_Tx[3];
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assign o_RC_T30 = RC_Tx[2];
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assign o_RC_T31 = RC_Tx[1];
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assign o_RC_T32 = RC_Tx[0];
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assign o_RC_RLSel = RC_RLSel;
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assign o_RC_VSel = RC_VSel;
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assign o_RC_ISel = RC_ISel;
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assign o_RC_LOF = (RC_VSel == 1'b1)?2'b01:2'b10; //if Measure V then close RC_LOF[0]
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assign o_RC_LOS = (RC_VSel == 1'b1)?2'b01:2'b10;
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assign o_err = bus_err_flag || reg_err_flag ||cpld_err_flag;
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endmodule
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