Jeremy Shen 070ad1c768 Merge branch 'master' of http://mkb.local:3000/yuysh/NewInstrCalBoard_CPLD

2026-06-01 18:03:33 +08:00

..

impl1

TODO: Fix MISO logic (1/?)

2026-06-01 16:20:38 +08:00

tb_RelayConTop

Update gitignore

2026-05-27 17:40:07 +08:00

tb_SPI_RegRW

Add SPI_Reg testbench

2026-06-01 18:03:16 +08:00

BUS_Con.v

TODO: Fix MISO logic (1/?)

2026-06-01 16:20:38 +08:00

CPLD1_Debug.rva

TODO: Fix MISO logic (1/?)

2026-06-01 16:20:38 +08:00

CPLD1_Debug.svf

TODO: Fix MISO logic (1/?)

2026-06-01 16:20:38 +08:00

CPLD1_Debug.trc

TODO: Fix MISO logic (1/?)

2026-06-01 16:20:38 +08:00

CPLD1_sim.log

Init Repo

2026-05-27 17:25:48 +08:00

CPLD_Con.v

Change RC_RLSel logic

2026-06-01 16:19:58 +08:00

debug.rvl

TODO: Fix MISO logic (1/?)

2026-06-01 16:20:38 +08:00

debug.rvs

TODO: Fix MISO logic (1/?)

2026-06-01 16:20:38 +08:00

NewExtIns_CPLD1.ccl

Init Repo

2026-05-27 17:25:48 +08:00

NewExtIns_CPLD1.ldf

Modify simulation files

2026-05-29 16:32:58 +08:00

NewExtIns_CPLD1.lpf

TODO: Fix MISO logic (1/?)

2026-06-01 16:20:38 +08:00

NewExtIns_CPLD1.sort

Init Repo

2026-05-27 17:25:48 +08:00

NewExtInsRelay1.sty

Init Repo

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Reg_file.v

Init Repo

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RelayConTop_tf.v

Init Repo

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RelayConTop.sort

Init Repo

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RelayConTop.sym

Init Repo

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RelayConTop.tfi

Init Repo

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RelayConTop.v

Init Repo

2026-05-27 17:25:48 +08:00

tb_RelayConTop.sv

Init Repo

2026-05-27 17:25:48 +08:00

tb_SPI_RegRW.sv

Add SPI_Reg testbench

2026-06-01 18:03:16 +08:00