847 lines
32 KiB
Systemverilog
847 lines
32 KiB
Systemverilog
//------------------------------------------------------------------------------
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//
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// Testbench: CPLD1 - SPI Communication & Register R/W
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// Project: NewCalBoard DIG
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// Tool: Lattice Diamond Verilog-2001 simulator
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// Purpose: Verify SPI protocol (MISO/MOSI timing) and register read/write
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// on the full RelayConTop design.
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//
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// Protocol:
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// Write: [WR=1][Addr:7b][Data:24b] = 32 bits
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// Read: [WR=0][Addr:7b][Don'tCare:24b] -> MISO returns [8'h00][24-bit rdata]
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//
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`define SYS_CLK_PERIOD 20 // 50 MHz system clock
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`define SPI_CLK_PERIOD 400 // 1 MHz SPI clock
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module tb_SPI_RegRW;
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////==========================================================================
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// Signal declarations - mirrors RelayConTop pinout exactly
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////==========================================================================
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// Clock & reset
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reg i_sys_clk;
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reg i_rst_n;
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// SPI interface (Zynq PS drives these)
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reg i_sclk;
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reg i_mosi;
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reg i_cs;
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// Flow control (from Zynq PS / SPI_Con IP)
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reg i_rready;
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reg i_wvalid;
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// Status outputs (monitored by testbench)
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wire o_miso;
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wire o_wready;
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wire o_err;
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wire o_con_done;
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// Relay control outputs
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wire o_IO_RC1;
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wire o_RC_VSel;
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wire o_RC_ISel;
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wire [17:0] o_RC_RLSel;
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wire [1:0] o_RC_LOF;
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wire [1:0] o_RC_LOS;
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wire o_RC_T27;
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wire o_RC_T28;
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wire o_RC_T29;
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wire o_RC_T30;
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wire o_RC_T31;
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wire o_RC_T32;
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// PMU output channels (4 x 32-bit)
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wire [31:0] o_PMU_OC_1;
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wire [31:0] o_PMU_OC_2;
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wire [31:0] o_PMU_OC_3;
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wire [31:0] o_PMU_OC_4;
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// DMM enable bus (19 bits)
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wire [18:0] o_DMM_EN;
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////==========================================================================
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// DUT instantiation - connect every pin
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////==========================================================================
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RelayConTop DUT (
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.i_sys_clk (i_sys_clk),
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.i_rst_n (i_rst_n),
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.i_sclk (i_sclk),
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.i_mosi (i_mosi),
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.i_cs (i_cs),
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.o_miso (o_miso),
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.i_rready (i_rready),
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.i_wvalid (i_wvalid),
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.o_wready (o_wready),
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.o_err (o_err),
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.o_con_done (o_con_done),
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.o_DMM_EN (o_DMM_EN),
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.o_IO_RC1 (o_IO_RC1),
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.o_RC_T27 (o_RC_T27),
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.o_RC_T28 (o_RC_T28),
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.o_RC_T29 (o_RC_T29),
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.o_RC_T30 (o_RC_T30),
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.o_RC_T31 (o_RC_T31),
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.o_RC_T32 (o_RC_T32),
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.o_RC_RLSel (o_RC_RLSel),
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.o_RC_VSel (o_RC_VSel),
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.o_RC_ISel (o_RC_ISel),
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.o_RC_LOF (o_RC_LOF),
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.o_RC_LOS (o_RC_LOS),
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.o_PMU_OC_1 (o_PMU_OC_1),
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.o_PMU_OC_2 (o_PMU_OC_2),
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.o_PMU_OC_3 (o_PMU_OC_3),
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.o_PMU_OC_4 (o_PMU_OC_4)
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);
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//==========================================================================
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// Clock Generation
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//==========================================================================
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initial begin
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i_sys_clk = 0;
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forever #(`SYS_CLK_PERIOD / 2) i_sys_clk = ~i_sys_clk;
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end
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initial begin
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i_sclk = 0;
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forever #(`SPI_CLK_PERIOD / 2) i_sclk = ~i_sclk;
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end
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//==========================================================================
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// Test Statistics
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//==========================================================================
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integer test_pass;
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integer test_fail;
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integer test_num; // assertion count
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integer test_case_num; // test case count (7 main tests + optional)
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initial begin
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test_pass = 0;
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test_fail = 0;
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test_num = 0;
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test_case_num = 0;
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end
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task tb_pass;
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input string msg;
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begin
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test_pass = test_pass + 1;
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$display("[PASS] Assertion %0d: %s", test_num, msg);
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end
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endtask
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task tb_fail;
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input string msg;
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input string detail;
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begin
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test_fail = test_fail + 1;
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$display("[FAIL] Assertion %0d: %s >> %s", test_num, msg, detail);
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end
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endtask
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task tb_assert;
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input condition;
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input string msg;
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input string detail;
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begin
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test_num = test_num + 1;
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if (condition) begin
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tb_pass(msg);
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end else begin
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tb_fail(msg, detail);
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end
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end
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endtask
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//==========================================================================
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// SPI Helper Tasks
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//
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// SPI Mode 0: CPOL=0, CPHA=0
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// - SCLK idle LOW
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// - MOSI sampled on RISING edge
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// - MISO shifted on FALLING edge
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// - MSB first, 32 bits per transaction
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//
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// MISO is tri-stated (high-Z) when CS is HIGH.
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//==========================================================================
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// --- spi_send: Drive a 32-bit word out through MOSI ---
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task spi_send;
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input [31:0] data;
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integer i;
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begin
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@(negedge i_sclk);
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i_cs = 1'b0;
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@(negedge i_sclk);
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for (i = 31; i >= 0; i = i - 1) begin
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i_mosi = data[i];
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@(posedge i_sclk);
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end
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@(negedge i_sclk);
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i_cs = 1'b1;
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i_mosi = 1'b0;
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@(negedge i_sclk);
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end
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endtask
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// --- spi_read: Send command, capture response on MISO ---
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// C1 Fix: Added @(posedge i_sys_clk) after CS low to allow BUS_Con
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// 2-stage sync chain (cs_sync/sclk_sync) to settle before MISO sampling.
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// W2 Fix: #1 delay = 1ps (min time step) for clock-to-Q timing margin.
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task spi_read;
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input [31:0] cmd;
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output [31:0] rdata;
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integer i;
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begin
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@(negedge i_sclk);
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i_cs = 1'b0;
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@(posedge i_sys_clk); // C1: System clock sync for BUS_Con cross-domain settle
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rdata = 32'b0;
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for (i = 31; i >= 0; i = i - 1) begin
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i_mosi = cmd[i];
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@(posedge i_sclk);
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@(negedge i_sclk);
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#1; // W2: 1ps clock-to-Q timing margin for MISO sampling
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rdata[i] = o_miso;
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end
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@(negedge i_sclk);
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i_cs = 1'b1;
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i_mosi = 1'b0;
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@(negedge i_sclk);
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end
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endtask
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// --- spi_write: Send a write command ---
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task spi_write;
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input [31:0] data;
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begin
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spi_send(data);
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end
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endtask
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//--- wait_wready: Wait for SPI to be ready ---
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task wait_wready;
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input [15:0] max_cycles;
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output [1:0] result;
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integer i;
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begin
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result = 2'b0;
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for (i = 0; i < max_cycles; i = i + 1) begin
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#(`SYS_CLK_PERIOD);
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if (o_wready) begin
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result = 2'b1;
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return;
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end
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end
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end
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endtask
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//==========================================================================
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// Convenience: Build SPI frames
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//==========================================================================
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function [31:0] mk_write;
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input [6:0] addr;
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input [23:0] data;
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begin
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mk_write = {1'b1, addr, data};
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end
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endfunction
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function [31:0] mk_read;
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input [6:0] addr;
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begin
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mk_read = {1'b0, addr, 24'b0};
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end
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endfunction
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//==========================================================================
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// Main Test Sequence
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//==========================================================================
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initial begin
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// Initialize
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i_rst_n = 1'b0;
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i_cs = 1'b1;
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i_mosi = 1'b0;
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#(`SYS_CLK_PERIOD * 4);
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i_rst_n = 1'b1;
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#(`SYS_CLK_PERIOD * 10);
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$display("");
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$display("=============================================================");
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$display(" CPLD1 SPI Communication & Register R/W Testbench");
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$display(" System clock: %d MHz | SPI clock: %d MHz",
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1000 / `SYS_CLK_PERIOD, 1000 / `SPI_CLK_PERIOD);
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$display("=============================================================");
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$display("");
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test_spi_miso_mosi_timing();
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test_ident_register();
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test_register_rw_cycle();
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test_write_then_read();
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test_rapid_spi_transactions();
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test_error_conditions();
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test_miso_tri_state();
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test_con_done_flow(); // S3: execution flow test
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print_summary();
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#(`SYS_CLK_PERIOD * 20);
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$finish;
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end
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//==========================================================================
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// Test 1: MISO/MOSI SPI Timing
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//==========================================================================
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task test_spi_miso_mosi_timing;
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reg [31:0] rdata;
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reg [1:0] wait_result;
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begin
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test_case_num = test_case_num + 1;
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$display("");
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$display("-------------------------------------------------------------");
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$display(" Test 1: MISO/MOSI SPI Timing");
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$display("-------------------------------------------------------------");
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// 1a. MISO is high-Z when CS is HIGH
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$display(" 1a. MISO tri-state when CS=HIGH");
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i_cs = 1'b1;
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@(negedge i_sclk);
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tb_assert(o_miso === 1'bz,
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"MISO is high-Z when CS=HIGH",
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$sformatf("o_miso = %b (expected z)", o_miso));
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// 1b. MISO responds after CS goes LOW
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$display(" 1b. MISO active after CS=LOW");
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spi_read(mk_read(7'd0), rdata);
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tb_assert(o_miso !== 1'bz,
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"MISO is active (not high-Z) when CS=LOW",
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"");
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// 1c. Verify data alignment: first 8 bits are 0, then 24-bit data
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$display(" 1c. Verify read response alignment");
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spi_read(mk_read(7'd0), rdata);
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tb_assert(rdata[7:0] === 8'h00,
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"First 8 bits of read response are 0 padding",
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$sformatf("rdata[7:0] = 0x%02h (expected 0x00)", rdata[7:0]));
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tb_assert(rdata[23:0] === 24'h200010,
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"Last 24 bits are IDENT register value",
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$sformatf("rdata[23:0] = 0x%06h (expected 0x200010)", rdata[23:0]));
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// 1d. Write command: verify MOSI is sampled correctly
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$display(" 1d. Write command sent correctly");
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spi_write(mk_write(7'd2, (24'h0DEADBEE >> 8))); // W3: parentheses for clarity
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wait_wready(100, wait_result); // C2: explicit wready check
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tb_assert(wait_result[1] === 1'b1,
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"wready asserted after write",
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$sformatf("wait_result = %b", wait_result));
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#(`SPI_CLK_PERIOD);
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end
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endtask
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//==========================================================================
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// Test 2: IDENT Register (ADDR 0)
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//==========================================================================
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task test_ident_register;
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reg [31:0] rdata;
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begin
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test_case_num = test_case_num + 1;
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$display("");
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$display("-------------------------------------------------------------");
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$display(" Test 2: IDENT Register (ADDR 0)");
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$display("-------------------------------------------------------------");
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// 2a. Read IDENT register
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$display(" 2a. Read IDENT register");
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spi_read(mk_read(7'd0), rdata);
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tb_assert(rdata[23:0] === 24'h200010,
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"IDENT register returns 24'h200010 (CPLD1, v1.1.0)",
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$sformatf("rdata[23:0] = 0x%06h", rdata[23:0]));
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// 2b. Read IDENT multiple times (should always return same value)
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$display(" 2b. Read IDENT multiple times");
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spi_read(mk_read(7'd0), rdata);
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tb_assert(rdata[23:0] === 24'h200010,
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"IDENT register returns same value on repeat read",
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"");
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spi_read(mk_read(7'd0), rdata);
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tb_assert(rdata[23:0] === 24'h200010,
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"IDENT register returns same value on 3rd read",
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"");
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#(`SPI_CLK_PERIOD);
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end
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endtask
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//==========================================================================
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// Test 3: Register Read/Write Cycle
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//==========================================================================
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task test_register_rw_cycle;
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reg [31:0] rdata;
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reg [1:0] wait_result;
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begin
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test_case_num = test_case_num + 1;
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$display("");
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$display("-------------------------------------------------------------");
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$display(" Test 3: Register Read/Write Cycle");
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$display("-------------------------------------------------------------");
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// 3a. Write to ADDR 2 (Freq_Slot1), then read back
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$display(" 3a. Write ADDR 2 = 0x000005, read back");
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spi_write(mk_write(7'd2, 24'h000005));
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wait_wready(100, wait_result); // C2: explicit wready check
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tb_assert(wait_result[1] === 1'b1,
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"wready asserted after write to ADDR 2",
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$sformatf("wait_result = %b", wait_result));
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spi_read(mk_read(7'd2), rdata);
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tb_assert(rdata[23:0] === 24'h000005,
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"ADDR 2: write 0x000005, read back 0x000005",
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$sformatf("rdata[23:0] = 0x%06h", rdata[23:0]));
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// 3b. Write to ADDR 3, read back
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$display(" 3b. Write ADDR 3 = 0x003001, read back");
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spi_write(mk_write(7'd3, 24'h003001));
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wait_wready(100, wait_result); // C2: explicit wready check
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tb_assert(wait_result[1] === 1'b1,
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"wready asserted after write to ADDR 3",
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$sformatf("wait_result = %b", wait_result));
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spi_read(mk_read(7'd3), rdata);
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tb_assert(rdata[23:0] === 24'h003001,
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"ADDR 3: write 0x003001, read back 0x003001",
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$sformatf("rdata[23:0] = 0x%06h", rdata[23:0]));
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// 3c. Write to ADDR 4, read back
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$display(" 3c. Write ADDR 4 = 0x001040, read back");
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spi_write(mk_write(7'd4, 24'h001040));
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wait_wready(100, wait_result); // C2: explicit wready check
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tb_assert(wait_result[1] === 1'b1,
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"wready asserted after write to ADDR 4",
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$sformatf("wait_result = %b", wait_result));
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spi_read(mk_read(7'd4), rdata);
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tb_assert(rdata[23:0] === 24'h001040,
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"ADDR 4: write 0x001040, read back 0x001040",
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$sformatf("rdata[23:0] = 0x%06h", rdata[23:0]));
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// 3d. Write to ADDR 5, read back
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$display(" 3d. Write ADDR 5 = 0x000802, read back");
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spi_write(mk_write(7'd5, 24'h000802));
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wait_wready(100, wait_result); // C2: explicit wready check
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tb_assert(wait_result[1] === 1'b1,
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"wready asserted after write to ADDR 5",
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$sformatf("wait_result = %b", wait_result));
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spi_read(mk_read(7'd5), rdata);
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tb_assert(rdata[23:0] === 24'h000802,
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"ADDR 5: write 0x000802, read back 0x000802",
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$sformatf("rdata[23:0] = 0x%06h", rdata[23:0]));
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// 3e. Write to ADDR 6 (DC_Slot1), read back
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$display(" 3e. Write ADDR 6 = 0x002003, read back");
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spi_write(mk_write(7'd6, 24'h002003));
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wait_wready(100, wait_result); // C2: explicit wready check
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tb_assert(wait_result[1] === 1'b1,
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"wready asserted after write to ADDR 6",
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$sformatf("wait_result = %b", wait_result));
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spi_read(mk_read(7'd6), rdata);
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tb_assert(rdata[23:0] === 24'h002003,
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"ADDR 6: write 0x002003, read back 0x002003",
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$sformatf("rdata[23:0] = 0x%06h", rdata[23:0]));
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// 3f. Write all DC registers
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$display(" 3f. Write ADDR 7-9, read back");
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spi_write(mk_write(7'd7, 24'h004005));
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wait_wready(100, wait_result); // C2: explicit wready check
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tb_assert(wait_result[1] === 1'b1,
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"wready asserted after write to ADDR 7",
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$sformatf("wait_result = %b", wait_result));
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spi_read(mk_read(7'd7), rdata);
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tb_assert(rdata[23:0] === 24'h004005,
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"ADDR 7: write 0x004005, read back 0x004005",
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"");
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spi_write(mk_write(7'd8, 24'h006007));
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wait_wready(100, wait_result); // C2: explicit wready check
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tb_assert(wait_result[1] === 1'b1,
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"wready asserted after write to ADDR 8",
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$sformatf("wait_result = %b", wait_result));
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spi_read(mk_read(7'd8), rdata);
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tb_assert(rdata[23:0] === 24'h006007,
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"ADDR 8: write 0x006007, read back 0x006007",
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"");
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|
|
|
spi_write(mk_write(7'd9, 24'h008009));
|
|
wait_wready(100, wait_result); // C2: explicit wready check
|
|
tb_assert(wait_result[1] === 1'b1,
|
|
"wready asserted after write to ADDR 9",
|
|
$sformatf("wait_result = %b", wait_result));
|
|
spi_read(mk_read(7'd9), rdata);
|
|
tb_assert(rdata[23:0] === 24'h008009,
|
|
"ADDR 9: write 0x008009, read back 0x008009",
|
|
"");
|
|
|
|
#(`SPI_CLK_PERIOD);
|
|
end
|
|
endtask
|
|
|
|
//==========================================================================
|
|
// Test 4: Write Then Read (separate transactions)
|
|
//==========================================================================
|
|
task test_write_then_read;
|
|
reg [31:0] rdata;
|
|
reg [1:0] wait_result;
|
|
begin
|
|
test_case_num = test_case_num + 1;
|
|
$display("");
|
|
$display("-------------------------------------------------------------");
|
|
$display(" Test 4: Write Then Read (separate transactions)");
|
|
$display("-------------------------------------------------------------");
|
|
|
|
// 4a. Write value, wait, then read (verify persistence)
|
|
$display(" 4a. Write 0xABCDEF to ADDR 2, read after delay");
|
|
spi_write(mk_write(7'd2, 24'hABCDEF));
|
|
wait_wready(100, wait_result); // C2: explicit wready check
|
|
tb_assert(wait_result[1] === 1'b1,
|
|
"wready asserted after write to ADDR 2",
|
|
$sformatf("wait_result = %b", wait_result));
|
|
|
|
// Simulate some delay (multiple SPI clock cycles)
|
|
#(`SPI_CLK_PERIOD * 3);
|
|
|
|
spi_read(mk_read(7'd2), rdata);
|
|
tb_assert(rdata[23:0] === 24'hABCDEF,
|
|
"ADDR 2: value persists after delay",
|
|
$sformatf("rdata[23:0] = 0x%06h (expected 0xABCDEF)", rdata[23:0]));
|
|
|
|
// 4b. Write another value, read immediately
|
|
$display(" 4b. Write 0x112233 to ADDR 3, read immediately");
|
|
spi_write(mk_write(7'd3, 24'h112233));
|
|
wait_wready(100, wait_result); // C2: explicit wready check
|
|
tb_assert(wait_result[1] === 1'b1,
|
|
"wready asserted after write to ADDR 3",
|
|
$sformatf("wait_result = %b", wait_result));
|
|
spi_read(mk_read(7'd3), rdata);
|
|
tb_assert(rdata[23:0] === 24'h112233,
|
|
"ADDR 3: value reads back immediately",
|
|
$sformatf("rdata[23:0] = 0x%06h", rdata[23:0]));
|
|
|
|
// 4c. Write 0 to register, read back
|
|
$display(" 4c. Write 0x000000 to ADDR 4, read back");
|
|
spi_write(mk_write(7'd4, 24'h000000));
|
|
wait_wready(100, wait_result); // C2: explicit wready check
|
|
tb_assert(wait_result[1] === 1'b1,
|
|
"wready asserted after write to ADDR 4",
|
|
$sformatf("wait_result = %b", wait_result));
|
|
spi_read(mk_read(7'd4), rdata);
|
|
tb_assert(rdata[23:0] === 24'h000000,
|
|
"ADDR 4: write 0x000000, read back 0x000000",
|
|
"");
|
|
|
|
#(`SPI_CLK_PERIOD);
|
|
end
|
|
endtask
|
|
|
|
//==========================================================================
|
|
// Test 5: Rapid SPI Transactions
|
|
//==========================================================================
|
|
task test_rapid_spi_transactions;
|
|
reg [31:0] rdata;
|
|
reg [1:0] wait_result;
|
|
begin
|
|
test_case_num = test_case_num + 1;
|
|
$display("");
|
|
$display("-------------------------------------------------------------");
|
|
$display(" Test 5: Rapid SPI Transactions");
|
|
$display("-------------------------------------------------------------");
|
|
|
|
// 5a. Multiple rapid writes
|
|
$display(" 5a. Rapid successive writes");
|
|
spi_write(mk_write(7'd2, 24'h000001));
|
|
spi_write(mk_write(7'd3, 24'h000002));
|
|
spi_write(mk_write(7'd4, 24'h000003));
|
|
spi_write(mk_write(7'd5, 24'h000004));
|
|
wait_wready(100, wait_result); // C2: explicit wready check
|
|
tb_assert(wait_result[1] === 1'b1,
|
|
"wready asserted after rapid writes",
|
|
$sformatf("wait_result = %b", wait_result));
|
|
|
|
// Verify all values
|
|
spi_read(mk_read(7'd2), rdata);
|
|
tb_assert(rdata[23:0] === 24'h000001,
|
|
"Rapid write: ADDR 2 = 0x000001",
|
|
$sformatf("rdata[23:0] = 0x%06h", rdata[23:0]));
|
|
|
|
spi_read(mk_read(7'd3), rdata);
|
|
tb_assert(rdata[23:0] === 24'h000002,
|
|
"Rapid write: ADDR 3 = 0x000002",
|
|
"");
|
|
|
|
spi_read(mk_read(7'd4), rdata);
|
|
tb_assert(rdata[23:0] === 24'h000003,
|
|
"Rapid write: ADDR 4 = 0x000003",
|
|
"");
|
|
|
|
spi_read(mk_read(7'd5), rdata);
|
|
tb_assert(rdata[23:0] === 24'h000004,
|
|
"Rapid write: ADDR 5 = 0x000004",
|
|
"");
|
|
|
|
// 5b. Interleaved write/read
|
|
$display(" 5b. Interleaved write/read");
|
|
spi_write(mk_write(7'd6, (24'h0DEADBEE >> 8))); // W3: parentheses for clarity
|
|
wait_wready(100, wait_result); // C2: explicit wready check
|
|
tb_assert(wait_result[1] === 1'b1,
|
|
"wready asserted after write to ADDR 6",
|
|
$sformatf("wait_result = %b", wait_result));
|
|
spi_read(mk_read(7'd6), rdata);
|
|
tb_assert(rdata[23:0] === (24'h0DEADBEE >> 8),
|
|
"Interleaved: ADDR 6 correct",
|
|
"");
|
|
|
|
spi_write(mk_write(7'd7, (24'hCAFEBE >> 8))); // W3: parentheses for clarity
|
|
wait_wready(100, wait_result); // C2: explicit wready check
|
|
tb_assert(wait_result[1] === 1'b1,
|
|
"wready asserted after write to ADDR 7",
|
|
$sformatf("wait_result = %b", wait_result));
|
|
spi_read(mk_read(7'd7), rdata);
|
|
tb_assert(rdata[23:0] === (24'hCAFEBE >> 8),
|
|
"Interleaved: ADDR 7 correct",
|
|
"");
|
|
|
|
#(`SPI_CLK_PERIOD);
|
|
end
|
|
endtask
|
|
|
|
//==========================================================================
|
|
// Test 6: Error Conditions
|
|
//==========================================================================
|
|
task test_error_conditions;
|
|
reg [31:0] rdata;
|
|
reg [1:0] wait_result;
|
|
begin
|
|
test_case_num = test_case_num + 1;
|
|
$display("");
|
|
$display("-------------------------------------------------------------");
|
|
$display(" Test 6: Error Conditions");
|
|
$display("-------------------------------------------------------------");
|
|
|
|
// 6a. Read out-of-bounds address (ADDR 16)
|
|
$display(" 6a. Read ADDR 16 (out of bounds)");
|
|
tb_assert(o_err === 1'b0, // W1: pre-check o_err is cleared before test
|
|
"o_err should be low before Test 6a",
|
|
$sformatf("o_err = %b", o_err));
|
|
spi_read(mk_read(7'd16), rdata);
|
|
@(negedge i_sclk);
|
|
#(`SYS_CLK_PERIOD * 5);
|
|
tb_assert(o_err === 1'b1,
|
|
"o_err HIGH after reading ADDR 16",
|
|
"");
|
|
i_rst_n = 1'b0;
|
|
#(`SYS_CLK_PERIOD * 4);
|
|
i_rst_n = 1'b1;
|
|
#(`SYS_CLK_PERIOD * 4);
|
|
tb_assert(o_err === 1'b0,
|
|
"o_err cleared after reset",
|
|
"");
|
|
|
|
// 6b. Write to out-of-bounds address (ADDR 31)
|
|
$display(" 6b. Write ADDR 31 (out of bounds)");
|
|
tb_assert(o_err === 1'b0, // W1: pre-check o_err is cleared before test
|
|
"o_err should be low before Test 6b",
|
|
$sformatf("o_err = %b", o_err));
|
|
spi_write(mk_write(7'd31, 24'h123456));
|
|
wait_wready(100, wait_result); // C2: explicit wready check
|
|
#(`SYS_CLK_PERIOD * 5);
|
|
tb_assert(o_err === 1'b1,
|
|
"o_err HIGH after writing ADDR 31",
|
|
"");
|
|
i_rst_n = 1'b0;
|
|
#(`SYS_CLK_PERIOD * 4);
|
|
i_rst_n = 1'b1;
|
|
#(`SYS_CLK_PERIOD * 4);
|
|
tb_assert(o_err === 1'b0,
|
|
"o_err cleared after reset",
|
|
"");
|
|
|
|
// 6c. Short SPI transaction (16 bits)
|
|
$display(" 6c. Short SPI transaction (16 bits)");
|
|
tb_assert(o_err === 1'b0, // W1: pre-check o_err is cleared before test
|
|
"o_err should be low before Test 6c",
|
|
$sformatf("o_err = %b", o_err));
|
|
i_cs = 1'b0;
|
|
#(`SYS_CLK_PERIOD * 2); // W4: allow BUS_Con sync chain to settle
|
|
@(negedge i_sclk);
|
|
@(negedge i_sclk);
|
|
for (integer bi = 0; bi < 16; bi = bi + 1) begin
|
|
i_mosi = 1'b0;
|
|
@(posedge i_sclk);
|
|
@(negedge i_sclk);
|
|
end
|
|
i_cs = 1'b1;
|
|
@(negedge i_sclk);
|
|
#(`SYS_CLK_PERIOD * 5);
|
|
tb_assert(o_err === 1'b1,
|
|
"o_err HIGH after short SPI transaction",
|
|
"");
|
|
i_rst_n = 1'b0;
|
|
#(`SYS_CLK_PERIOD * 4);
|
|
i_rst_n = 1'b1;
|
|
#(`SYS_CLK_PERIOD * 4);
|
|
tb_assert(o_err === 1'b0,
|
|
"o_err cleared after reset",
|
|
"");
|
|
|
|
// 6d. Brief CS pulse (too short)
|
|
$display(" 6d. Brief CS pulse");
|
|
tb_assert(o_err === 1'b0, // W1: pre-check o_err is cleared before test
|
|
"o_err should be low before Test 6d",
|
|
$sformatf("o_err = %b", o_err));
|
|
i_cs = 1'b0;
|
|
#(`SYS_CLK_PERIOD * 2); // W4: allow BUS_Con sync chain to settle
|
|
@(negedge i_sclk);
|
|
@(negedge i_sclk);
|
|
i_cs = 1'b1;
|
|
@(negedge i_sclk);
|
|
#(`SYS_CLK_PERIOD * 5);
|
|
tb_assert(o_err === 1'b1,
|
|
"o_err detected brief CS pulse",
|
|
"");
|
|
i_rst_n = 1'b0;
|
|
#(`SYS_CLK_PERIOD * 4);
|
|
i_rst_n = 1'b1;
|
|
#(`SYS_CLK_PERIOD * 4);
|
|
tb_assert(o_err === 1'b0,
|
|
"o_err cleared after reset",
|
|
"");
|
|
|
|
#(`SPI_CLK_PERIOD * 2);
|
|
end
|
|
endtask
|
|
|
|
//==========================================================================
|
|
// Test 7: MISO Tri-State Behavior
|
|
//==========================================================================
|
|
task test_miso_tri_state;
|
|
begin
|
|
test_case_num = test_case_num + 1;
|
|
$display("");
|
|
$display("-------------------------------------------------------------");
|
|
$display(" Test 7: MISO Tri-State Behavior");
|
|
$display("-------------------------------------------------------------");
|
|
|
|
// 7a. MISO is high-Z when CS is HIGH
|
|
$display(" 7a. MISO high-Z when CS=HIGH");
|
|
i_cs = 1'b1;
|
|
@(negedge i_sclk);
|
|
tb_assert(o_miso === 1'bz,
|
|
"MISO is high-Z when CS=HIGH",
|
|
$sformatf("o_miso = %b (expected z)", o_miso));
|
|
|
|
// 7b. MISO is active when CS is LOW
|
|
$display(" 7b. MISO active when CS=LOW");
|
|
i_cs = 1'b0;
|
|
@(negedge i_sclk);
|
|
tb_assert(o_miso !== 1'bz,
|
|
"MISO is active (not high-Z) when CS=LOW",
|
|
"");
|
|
|
|
// 7c. MISO returns to high-Z when CS goes HIGH again
|
|
$display(" 7c. MISO returns to high-Z when CS=HIGH");
|
|
i_cs = 1'b1;
|
|
@(negedge i_sclk);
|
|
tb_assert(o_miso === 1'bz,
|
|
"MISO returns to high-Z when CS=HIGH",
|
|
$sformatf("o_miso = %b (expected z)", o_miso));
|
|
|
|
#(`SPI_CLK_PERIOD);
|
|
end
|
|
endtask
|
|
|
|
//==========================================================================
|
|
// Test 8: o_con_done Execution Flow (S3)
|
|
//==========================================================================
|
|
task test_con_done_flow;
|
|
reg [31:0] rdata;
|
|
reg [1:0] wait_result;
|
|
begin
|
|
test_case_num = test_case_num + 1;
|
|
$display("");
|
|
$display("-------------------------------------------------------------");
|
|
$display(" Test 8: o_con_done Execution Flow");
|
|
$display("-------------------------------------------------------------");
|
|
|
|
// 8a. Write EXEC bit to ADDR 1 (STATE_REG), then verify o_con_done
|
|
$display(" 8a. Write EXEC bit, wait for o_con_done");
|
|
spi_write(mk_write(7'd1, 24'h800001)); // Set EXEC bit
|
|
wait_wready(100, wait_result);
|
|
tb_assert(wait_result[1] === 1'b1,
|
|
"wready asserted after EXEC write",
|
|
$sformatf("wait_result = %b", wait_result));
|
|
|
|
// Wait for o_con_done to go high (controller execution complete)
|
|
// Poll o_con_done for up to 500 system clock cycles
|
|
begin
|
|
integer j;
|
|
reg found;
|
|
found = 1'b0;
|
|
for (j = 0; j < 500; j = j + 1) begin
|
|
#(`SYS_CLK_PERIOD);
|
|
if (o_con_done === 1'b1 && found === 1'b0) begin
|
|
tb_assert(1'b1,
|
|
"o_con_done asserted within 500 sys clock cycles",
|
|
"");
|
|
found = 1'b1;
|
|
end
|
|
end
|
|
tb_assert(found === 1'b1,
|
|
"o_con_done not asserted within 500 sys clock cycles",
|
|
"");
|
|
end
|
|
|
|
// 8b. Read back ADDR 1 to verify STATE bit changed
|
|
$display(" 8b. Read ADDR 1 to verify state change");
|
|
spi_read(mk_read(7'd1), rdata);
|
|
// After execution, bit 23 (ready bit) should be set
|
|
// and EXEC bit (bit 0) should be cleared
|
|
$display(" 8b. ADDR 1 read value = 0x%06h", rdata[23:0]);
|
|
|
|
#(`SPI_CLK_PERIOD);
|
|
end
|
|
endtask
|
|
|
|
//==========================================================================
|
|
// Summary
|
|
//==========================================================================
|
|
task print_summary;
|
|
begin
|
|
$display("");
|
|
$display("=============================================================");
|
|
$display(" Test Summary");
|
|
$display("=============================================================");
|
|
$display(" Test cases run: %0d", test_case_num);
|
|
$display(" Total assertions: %0d", test_pass + test_fail);
|
|
$display(" Passed: %0d", test_pass);
|
|
$display(" Failed: %0d", test_fail);
|
|
$display("=============================================================");
|
|
if (test_fail == 0) begin
|
|
$display(" *** ALL TESTS PASSED ***");
|
|
end else begin
|
|
$display(" *** SOME TESTS FAILED - CHECK DESIGN ***");
|
|
end
|
|
$display("=============================================================");
|
|
$display("");
|
|
end
|
|
endtask
|
|
|
|
endmodule
|