14 Commits

Include renames

Author	SHA1	Message	Date
Jeremy Shen	34b8bdbdd8	Add SPI_Reg testbench	2026-06-01 18:03:16 +08:00
Jeremy Shen	e60d56dd26	Change MISO logic	2026-06-01 14:44:18 +08:00
Jeremy Shen	5b949c6b63	Fix MISO Logic	2026-06-01 12:37:02 +08:00
yuysh	54a64ec222	Bug fixes for all CPLDs	2026-05-29 18:31:27 +08:00
Jeremy Shen	b3eef70c28	CPLD1 fix DMM & OC shifting logic	2026-05-29 17:42:08 +08:00
yuysh	3e722a7f15	Modify simulation files	2026-05-29 16:32:58 +08:00
yuysh	611945be04	Update CPLD1 output	2026-05-28 10:41:58 +08:00
yuysh	da61ebe108	Update ignored items	2026-05-28 10:41:25 +08:00
yuysh	8de946787c	CPLD1 debug logic too large, delete some signals	2026-05-28 10:29:27 +08:00
Jeremy Shen	bf6769d814	gitignore fix	2026-05-28 10:25:03 +08:00
Jeremy Shen	9ae77f3dbf	Add debug.rvs	2026-05-28 09:31:03 +08:00
Jeremy Shen	0d6272e7c9	Update gitignore again	2026-05-28 09:30:38 +08:00
Jeremy Shen	81e230066e	Update gitignore	2026-05-27 17:40:07 +08:00
Jeremy Shen	2c6716e5eb	Init Repo	2026-05-27 17:25:48 +08:00