Add LWIP CMD Server Stack

Add lwip cmd server
Add CPLD_Con.c/h: Move CPLD Control Code to seperate file.
2026-06-18 09:59:22 +08:00 · 2026-06-17 15:47:27 +08:00 · 2026-06-01 10:50:36 +08:00 · 2026-05-29 18:18:49 +08:00 · 2026-05-29 14:11:26 +08:00 · 2026-05-28 18:39:13 +08:00
569 changed files with 1735 additions and 1049183 deletions
@@ -0,0 +1,142 @@
 # ===========================================================================
 # General .gitignore for Xilinx Vivado / Vitis / SDK Projects
 # Works for ANY project folder following standard Xilinx directory structure
 #
 # Directory naming convention: <ProjectName>.<suffix>/
 #   e.g., Debug_FW.cache/, Debug_FW.gen/, Debug_FW.hw/, Debug_FW.runs/,
 #         Debug_FW.sim/, Debug_FW.srcs/, Debug_FW.ip_user_files/
 #   e.g., Debug_FW.sdk/ (SDK workspace, different structure)
 # ===========================================================================
 #
 # PRESERVED (committed):
 #   - Source files (.v, .vhdl, .bd, .xdc, .c, .h, .ld)
 #   - Project/workspace config files (.xpr, .project, .cproject)
 #   - IP configuration (.xci)
 #   - Generated HDL sources (in .gen/ but NOT sim/)
 #   - BSP files (system.mss, platform.tcl, etc.)
 #   - Output files (.xsa, .bit, .elf)
 #   - Hardware platform files (.hdf, ps7_init.*)
 #
 # IGNORED (build artifacts, workspace state, caches):
 # ===========================================================================
 # ----- Vivado Cache -----
 # Directory: <ProjectName>.cache/ - regenerated by Vivado
 *.cache/
 # ----- Logs -----
 *.log
 # ----- Vivado Generated Sources -----
 # Directory: <ProjectName>.gen/ - keep HDL, ignore sim files
 *.gen/*/ip/*/sim/
 *.gen/*/ip/*/sim_tlm/
 # ----- Vivado IP User Files -----
 # Directory: <ProjectName>.ip_user_files/ - keep mem_init, ignore sim scripts and bd
 *.ip_user_files/sim_scripts/
 *.ip_user_files/bd/
 # ----- Vivado Simulation -----
 # Directory: <ProjectName>.sim/
 *.sim/
 # ----- Vivado Runs (synthesis & implementation outputs) -----
 # Directory: <ProjectName>.runs/ - keep run control scripts, ignore outputs
 *.runs/synth_1/*.log
 *.runs/synth_1/*.jou
 *.runs/synth_1/*.vds
 *.runs/synth_1/*.rpt
 *.runs/synth_1/*.pb
 *.runs/synth_1/*.dcp
 *.runs/synth_1/*.bin
 *.runs/synth_1/*.bit
 *.runs/synth_1/.Xil/
 *.runs/synth_1/__synthesis_is_complete__
 *.runs/impl_1/*.log
 *.runs/impl_1/*.jou
 *.runs/impl_1/*.vdi
 *.runs/impl_1/*.rpt
 *.runs/impl_1/*.rpx
 *.runs/impl_1/*.pb
 *.runs/impl_1/*.dcp
 *.runs/impl_1/*.bin
 *.runs/impl_1/*.bit
 *.runs/impl_1/*.ltx
 *.runs/impl_1/*.wdf
 *.runs/impl_1/.Xil/
 *.runs/impl_1/*.tmp
 *.runs/impl_1/*.hwdef
 *.runs/impl_1/*.json
 *.runs/impl_1/*.hw
 *.runs/impl_1/*.bd
 *.runs/impl_1/*.dat
 *.runs/impl_1/*.csv
 *.runs/impl_1/*.xml
 *.runs/impl_1/*.h5
 *.runs/impl_1/*.lpx
 *.runs/impl_1/*.spn
 *.runs/impl_1/*.spnx
 *.runs/impl_1/*.xdci
 *.runs/impl_1/*.lck
 *.runs/impl_1/*.dmp
 *.runs/impl_1/*.mcs
 *.runs/impl_1/*.bit.bif
 *.runs/impl_1/*.bin.bif
 *.runs/impl_1/*.mcs.bif
 # Keep run control files
 !*.runs/impl_1/gen_run.xml
 !*.runs/impl_1/rundef.js
 !*.runs/impl_1/runme.sh
 !*.runs/impl_1/runme.bat
 !*.runs/synth_1/gen_run.xml
 !*.runs/synth_1/rundef.js
 !*.runs/synth_1/runme.sh
 !*.runs/synth_1/runme.bat
 !*.runs/.jobs/
 !*.runs/.jobs/vrs_config_*.xml
 # ----- SDK Workspace (Vivado SDK) -----
 # Directory: <ProjectName>.sdk/ - different structure (no dot before "sdk")
 # Keep: .project, .cproject, sources, BSP, hw_platform configs
 # Ignore: workspace metadata, build outputs, logs
 *.sdk/.metadata/
 *.sdk/.sdk/
 *.sdk/RemoteSystemsTempFiles/
 *.sdk/SDK.log
 *.sdk/webtalk/
 *.sdk/*/Debug/
 *.sdk/*/Release/
 *.sdk/*/bootimage/
 *.sdk/*_hw_platform_*/system_wrapper.bit
 *.sdk/*_hw_platform_*/system_*.bit
 # ----- General Build Artifacts -----
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 *.pyc
 __pycache__/
 *.o
 *.a
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 # ----- OS Files -----
 .DS_Store
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 # ----- Eclipse / Vitis workspace metadata (regenerated on open) -----
 .metadata/
 # ----- Vitis workspace build artifacts (regenerated) -----
 **/export/
 **/tempdsa/
 **/RemoteSystemsTempFiles/
 # ----- IDE / Editor temporary files -----
 *.swo
 *.orig
 *.rej
@@ -1,106 +0,0 @@
 // Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
 // Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
 // Date        : Wed May 27 16:39:27 2026
 // Host        : mkb running 64-bit unknown
 // Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
 //               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.v
 // Design      : u_ila_0
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7z035ffg676-2
 // --------------------------------------------------------------------------------
 // This empty module with port declaration file causes synthesis tools to infer a black box for IP.
 // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
 // Please paste the declaration into a Verilog source file or add the file as an additional source.
 (* X_CORE_INFO = "ila,Vivado 2023.2" *)
 module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5, 
  probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17, 
  probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28, 
  probe29, probe30, probe31, probe32, probe33, probe34, probe35, probe36, probe37, probe38, probe39, 
  probe40, probe41, probe42, probe43, probe44, probe45, probe46, probe47, probe48, probe49, probe50, 
  probe51, probe52, probe53, probe54, probe55, probe56, probe57, probe58, probe59, probe60, probe61, 
  probe62, probe63, probe64, probe65, probe66, probe67, probe68, probe69, probe70, probe71, probe72, 
  probe73, probe74, probe75, probe76)
 /* synthesis syn_black_box black_box_pad_pin="probe0[0:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[0:0],probe20[0:0],probe21[0:0],probe22[0:0],probe23[0:0],probe24[0:0],probe25[0:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0],probe56[0:0],probe57[0:0],probe58[0:0],probe59[0:0],probe60[0:0],probe61[0:0],probe62[0:0],probe63[0:0],probe64[0:0],probe65[0:0],probe66[0:0],probe67[0:0],probe68[0:0],probe69[0:0],probe70[0:0],probe71[0:0],probe72[0:0],probe73[0:0],probe74[0:0],probe75[0:0],probe76[0:0]" */
 /* synthesis syn_force_seq_prim="clk" */;
  input clk /* synthesis syn_isclock = 1 */;
  input [0:0]probe0;
  input [0:0]probe1;
  input [0:0]probe2;
  input [0:0]probe3;
  input [0:0]probe4;
  input [0:0]probe5;
  input [0:0]probe6;
  input [0:0]probe7;
  input [0:0]probe8;
  input [0:0]probe9;
  input [0:0]probe10;
  input [0:0]probe11;
  input [0:0]probe12;
  input [0:0]probe13;
  input [0:0]probe14;
  input [0:0]probe15;
  input [0:0]probe16;
  input [0:0]probe17;
  input [0:0]probe18;
  input [0:0]probe19;
  input [0:0]probe20;
  input [0:0]probe21;
  input [0:0]probe22;
  input [0:0]probe23;
  input [0:0]probe24;
  input [0:0]probe25;
  input [0:0]probe26;
  input [0:0]probe27;
  input [0:0]probe28;
  input [0:0]probe29;
  input [0:0]probe30;
  input [0:0]probe31;
  input [0:0]probe32;
  input [0:0]probe33;
  input [0:0]probe34;
  input [0:0]probe35;
  input [0:0]probe36;
  input [0:0]probe37;
  input [0:0]probe38;
  input [0:0]probe39;
  input [0:0]probe40;
  input [0:0]probe41;
  input [0:0]probe42;
  input [0:0]probe43;
  input [0:0]probe44;
  input [0:0]probe45;
  input [0:0]probe46;
  input [0:0]probe47;
  input [0:0]probe48;
  input [0:0]probe49;
  input [0:0]probe50;
  input [0:0]probe51;
  input [0:0]probe52;
  input [0:0]probe53;
  input [0:0]probe54;
  input [0:0]probe55;
  input [0:0]probe56;
  input [0:0]probe57;
  input [0:0]probe58;
  input [0:0]probe59;
  input [0:0]probe60;
  input [0:0]probe61;
  input [0:0]probe62;
  input [0:0]probe63;
  input [0:0]probe64;
  input [0:0]probe65;
  input [0:0]probe66;
  input [0:0]probe67;
  input [0:0]probe68;
  input [0:0]probe69;
  input [0:0]probe70;
  input [0:0]probe71;
  input [0:0]probe72;
  input [0:0]probe73;
  input [0:0]probe74;
  input [0:0]probe75;
  input [0:0]probe76;
 endmodule
@@ -1,108 +0,0 @@
 -- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
 -- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
 -- Date        : Wed May 27 16:39:27 2026
 -- Host        : mkb running 64-bit unknown
 -- Command     : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
 --               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.vhdl
 -- Design      : u_ila_0
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7z035ffg676-2
 -- --------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
  Port ( 
    clk : in STD_LOGIC;
    probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe7 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe9 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe11 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe12 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe13 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe14 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe15 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe16 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe17 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe18 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe19 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe20 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe21 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe22 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe23 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe25 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe26 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe27 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe28 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe29 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe30 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe31 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe32 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe33 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe34 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe35 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe36 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe37 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe38 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe39 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe40 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe41 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe42 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe43 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe44 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe45 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe46 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe47 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe48 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe49 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe50 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe51 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe52 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe53 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe54 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe55 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe56 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe57 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe58 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe59 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe60 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe61 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe62 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe63 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe64 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe65 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe66 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe67 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe68 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe69 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe70 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe71 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe72 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe73 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe74 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe75 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe76 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
 end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
 architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
 attribute syn_black_box : boolean;
 attribute black_box_pad_pin : string;
 attribute syn_black_box of stub : architecture is true;
 attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[0:0],probe20[0:0],probe21[0:0],probe22[0:0],probe23[0:0],probe24[0:0],probe25[0:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[0:0],probe40[0:0],probe41[0:0],probe42[0:0],probe43[0:0],probe44[0:0],probe45[0:0],probe46[0:0],probe47[0:0],probe48[0:0],probe49[0:0],probe50[0:0],probe51[0:0],probe52[0:0],probe53[0:0],probe54[0:0],probe55[0:0],probe56[0:0],probe57[0:0],probe58[0:0],probe59[0:0],probe60[0:0],probe61[0:0],probe62[0:0],probe63[0:0],probe64[0:0],probe65[0:0],probe66[0:0],probe67[0:0],probe68[0:0],probe69[0:0],probe70[0:0],probe71[0:0],probe72[0:0],probe73[0:0],probe74[0:0],probe75[0:0],probe76[0:0]";
 attribute X_CORE_INFO : string;
 attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2023.2";
 begin
 end;
@@ -1,24 +0,0 @@
 // Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
 // Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
 // Date        : Wed May 27 16:37:32 2026
 // Host        : mkb running 64-bit unknown
 // Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
 //               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_hub_stub.v
 // Design      : dbg_hub
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7z035ffg676-2
 // --------------------------------------------------------------------------------
 // This empty module with port declaration file causes synthesis tools to infer a black box for IP.
 // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
 // Please paste the declaration into a Verilog source file or add the file as an additional source.
 (* X_CORE_INFO = "xsdbm_v3_0_0_xsdbm,Vivado 2023.2" *)
 module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(sl_iport0_o, sl_oport0_i, clk)
 /* synthesis syn_black_box black_box_pad_pin="sl_iport0_o[36:0],sl_oport0_i[16:0]" */
 /* synthesis syn_force_seq_prim="clk" */;
  output [36:0]sl_iport0_o;
  input [16:0]sl_oport0_i;
  input clk /* synthesis syn_isclock = 1 */;
 endmodule
@@ -1,33 +0,0 @@
 -- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
 -- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
 -- Date        : Wed May 27 16:37:32 2026
 -- Host        : mkb running 64-bit unknown
 -- Command     : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
 --               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_hub_stub.vhdl
 -- Design      : dbg_hub
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7z035ffg676-2
 -- --------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
  Port ( 
    sl_iport0_o : out STD_LOGIC_VECTOR ( 36 downto 0 );
    sl_oport0_i : in STD_LOGIC_VECTOR ( 16 downto 0 );
    clk : in STD_LOGIC
  );
 end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
 architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
 attribute syn_black_box : boolean;
 attribute black_box_pad_pin : string;
 attribute syn_black_box of stub : architecture is true;
 attribute black_box_pad_pin of stub : architecture is "sl_iport0_o[36:0],sl_oport0_i[16:0],clk";
 attribute X_CORE_INFO : string;
 attribute X_CORE_INFO of stub : architecture is "xsdbm_v3_0_0_xsdbm,Vivado 2023.2";
 begin
 end;
@@ -1,66 +0,0 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
  <spirit:vendor>xilinx.com</spirit:vendor>
  <spirit:library>ipcache</spirit:library>
  <spirit:name>eed9b44902dc411e</spirit:name>
  <spirit:version>0</spirit:version>
  <spirit:componentInstances>
    <spirit:componentInstance>
      <spirit:instanceName>dbg_hub</spirit:instanceName>
      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xsdbm" spirit:version="3.0"/>
      <spirit:configurableElementValues>
        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BSCANID">76546592</spirit:configurableElementValue>
        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BSCAN_MODE">false</spirit:configurableElementValue>
        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BSCAN_MODE_WITH_CORE">false</spirit:configurableElementValue>
        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BUILD_REVISION">0</spirit:configurableElementValue>
        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CLKFBOUT_MULT_F">10.000</spirit:configurableElementValue>
        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CLKOUT0_DIVIDE_F">10.000</spirit:configurableElementValue>
        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CLK_INPUT_FREQ_HZ">300000000</spirit:configurableElementValue>
        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CORE_MAJOR_VER">1</spirit:configurableElementValue>
        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CORE_MINOR_ALPHA_VER">97</spirit:configurableElementValue>
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 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313873:00:00
 73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323531382e3930324d42:00:00
 73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313230382e3534334d42:00:00
 eof:2441486396
@@ -1,3 +0,0 @@
 version:1
 73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
 eof:2511430288
@@ -1,182 +0,0 @@
 <?xml version="1.0" encoding="UTF-8" ?>
 <document>
 <!--The data in this file is primarily intended for consumption by Xilinx tools.
 The structure and the elements are likely to change over the next few releases.
 This means code written to parse this file will need to be revisited each subsequent release.-->
 <application name="pa" timeStamp="Wed May 27 16:36:05 2026">
 <section name="Project Information" visible="false">
 <property name="ProjectID" value="84d0ce4348d446c883fb079fc9cadc0a" type="ProjectID"/>
 <property name="ProjectIteration" value="25" type="ProjectIteration"/>
 </section>
 <section name="PlanAhead Usage" visible="true">
 <item name="Project Data">
 <property name="SrcSetCount" value="1" type="SrcSetCount"/>
 <property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
 <property name="DesignMode" value="RTL" type="DesignMode"/>
 <property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
 <property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
 </item>
 <item name="Java Command Handlers">
 <property name="AddCfgMem" value="8" type="JavaHandler"/>
 <property name="AddSources" value="5" type="JavaHandler"/>
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 <property name="BootDevice" value="11" type="JavaHandler"/>
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 <property name="CustomizeRSBBlock" value="11" type="JavaHandler"/>
 <property name="DebugWizardCmdHandler" value="5" type="JavaHandler"/>
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 <property name="EditUndo" value="4" type="JavaHandler"/>
 <property name="LaunchOpenTarget" value="1" type="JavaHandler"/>
 <property name="LaunchProgramFpga" value="11" type="JavaHandler"/>
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 <property name="MarkDebug" value="41" type="JavaHandler"/>
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 <property name="NewHardwareDashboard" value="1" type="JavaHandler"/>
 <property name="NewLaunchHardware" value="42" type="JavaHandler"/>
 <property name="NewProject" value="1" type="JavaHandler"/>
 <property name="OpenBlockDesign" value="18" type="JavaHandler"/>
 <property name="OpenHardwareManager" value="20" type="JavaHandler"/>
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 <property name="ProgramCfgMem" value="6" type="JavaHandler"/>
 <property name="ProgramDevice" value="5" type="JavaHandler"/>
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 <property name="RunImplementation" value="11" type="JavaHandler"/>
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 <property name="RunTrigger" value="5" type="JavaHandler"/>
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 <property name="SaveRSBDesign" value="4" type="JavaHandler"/>
 <property name="ShowSource" value="1" type="JavaHandler"/>
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 <property name="ToolsSettings" value="2" type="JavaHandler"/>
 <property name="UnmarkDebug" value="1" type="JavaHandler"/>
 <property name="ViewLayoutCmd" value="2" type="JavaHandler"/>
 <property name="ViewTaskSynthesis" value="4" type="JavaHandler"/>
 </item>
 <item name="Gui Handlers">
 <property name="AddedConstraintsWithoutTargetDialog_CREATE_NEW_FILE" value="1" type="GuiHandlerData"/>
 <property name="ApplyRSBMultiAutomationDialog_CHECKBOX_TREE" value="3" type="GuiHandlerData"/>
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 <property name="CmdMsgDialog_OK" value="21" type="GuiHandlerData"/>
 <property name="ConstraintsChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
 <property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="3" type="GuiHandlerData"/>
 <property name="CreateConstraintsFilePanel_FILE_NAME" value="2" type="GuiHandlerData"/>
 <property name="CreateNewDiagramDialog_DESIGN_NAME" value="1" type="GuiHandlerData"/>
 <property name="DDRConfigTreeTablePanel_DDR_CONFIG_TREE_TABLE" value="18" type="GuiHandlerData"/>
 <property name="DebugWizard_ADVANCED_TRIGGER" value="3" type="GuiHandlerData"/>
 <property name="DebugWizard_CAPTURE_CONTROL" value="3" type="GuiHandlerData"/>
 <property name="DebugWizard_FIND_NETS_TO_ADD" value="1" type="GuiHandlerData"/>
 <property name="FPGAChooser_FAMILY" value="1" type="GuiHandlerData"/>
 <property name="FPGAChooser_FPGA_TABLE" value="1" type="GuiHandlerData"/>
 <property name="FPGAChooser_SPEED" value="1" type="GuiHandlerData"/>
 <property name="FileSetPanel_FILE_SET_PANEL_TREE" value="216" type="GuiHandlerData"/>
 <property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="128" type="GuiHandlerData"/>
 <property name="HardwareIlaWaveformView_RUN_TRIGGER_FOR_THIS_ILA_CORE" value="5" type="GuiHandlerData"/>
 <property name="HardwareTreePanel_HARDWARE_TREE_TABLE" value="77" type="GuiHandlerData"/>
 <property name="MIOConfigTreeTablePanel_MIO_CONFIG_TREE_TABLE" value="137" type="GuiHandlerData"/>
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 <property name="MainMenuMgr_CONSTRAINTS" value="4" type="GuiHandlerData"/>
 <property name="MainMenuMgr_EDIT" value="14" type="GuiHandlerData"/>
 <property name="MainMenuMgr_EXPORT" value="76" type="GuiHandlerData"/>
 <property name="MainMenuMgr_FILE" value="146" type="GuiHandlerData"/>
 <property name="MainMenuMgr_FLOW" value="14" type="GuiHandlerData"/>
 <property name="MainMenuMgr_HELP" value="2" type="GuiHandlerData"/>
 <property name="MainMenuMgr_IMPORT" value="24" type="GuiHandlerData"/>
 <property name="MainMenuMgr_IP" value="63" type="GuiHandlerData"/>
 <property name="MainMenuMgr_PROJECT" value="69" type="GuiHandlerData"/>
 <property name="MainMenuMgr_REPORTS" value="14" type="GuiHandlerData"/>
 <property name="MainMenuMgr_TEXT_EDITOR" value="46" type="GuiHandlerData"/>
 <property name="MainMenuMgr_TOOLS" value="32" type="GuiHandlerData"/>
 <property name="MainMenuMgr_VIEW" value="14" type="GuiHandlerData"/>
 <property name="MainMenuMgr_WINDOW" value="14" type="GuiHandlerData"/>
 <property name="MainToolbarMgr_RUN" value="4" type="GuiHandlerData"/>
 <property name="MainWinMenuMgr_LAYOUT" value="20" type="GuiHandlerData"/>
 <property name="MainWinMenuMgr_LOAD" value="1" type="GuiHandlerData"/>
 <property name="NetlistTreeView_NETLIST_TREE" value="126" type="GuiHandlerData"/>
 <property name="NewExportHardwareDialog_INCLUDE_BITSTREAM" value="18" type="GuiHandlerData"/>
 <property name="PACommandNames_ADD_SOURCES" value="4" type="GuiHandlerData"/>
 <property name="PACommandNames_AUTO_CONNECT_PORTS" value="1" type="GuiHandlerData"/>
 <property name="PACommandNames_AUTO_CONNECT_TARGET" value="12" type="GuiHandlerData"/>
 <property name="PACommandNames_AUTO_UPDATE_HIER" value="35" type="GuiHandlerData"/>
 <property name="PACommandNames_BOOT_DEVICE" value="11" type="GuiHandlerData"/>
 <property name="PACommandNames_CLOSE_HARDWARE_DESIGN" value="1" type="GuiHandlerData"/>
 <property name="PACommandNames_CREATE_TOP_HDL" value="4" type="GuiHandlerData"/>
 <property name="PACommandNames_EXPORT_HARDWARE" value="24" type="GuiHandlerData"/>
 <property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="6" type="GuiHandlerData"/>
 <property name="PACommandNames_GOTO_NETLIST_DESIGN" value="3" type="GuiHandlerData"/>
 <property name="PACommandNames_GOTO_SOURCE" value="1" type="GuiHandlerData"/>
 <property name="PACommandNames_LAUNCH_HARDWARE" value="42" type="GuiHandlerData"/>
 <property name="PACommandNames_MARK_DEBUG_NET" value="41" type="GuiHandlerData"/>
 <property name="PACommandNames_NEW_PROJECT" value="1" type="GuiHandlerData"/>
 <property name="PACommandNames_OPEN_TARGET_WIZARD" value="1" type="GuiHandlerData"/>
 <property name="PACommandNames_PROGRAM_CONFIG_MEMORY" value="2" type="GuiHandlerData"/>
 <property name="PACommandNames_PROGRAM_FPGA" value="9" type="GuiHandlerData"/>
 <property name="PACommandNames_REFRESH_DEVICE" value="13" type="GuiHandlerData"/>
 <property name="PACommandNames_RUN_BITGEN" value="10" type="GuiHandlerData"/>
 <property name="PACommandNames_RUN_SYNTHESIS" value="4" type="GuiHandlerData"/>
 <property name="PACommandNames_STOP_TRIGGER" value="1" type="GuiHandlerData"/>
 <property name="PACommandNames_UNMARK_DEBUG_NET" value="1" type="GuiHandlerData"/>
 <property name="PAViews_ADDRESS_EDITOR" value="3" type="GuiHandlerData"/>
 <property name="PAViews_CODE" value="14" type="GuiHandlerData"/>
 <property name="PAViews_DASHBOARD" value="15" type="GuiHandlerData"/>
 <property name="PAViews_DEVICE" value="2" type="GuiHandlerData"/>
 <property name="PAViews_IP_CATALOG" value="4" type="GuiHandlerData"/>
 <property name="PAViews_PACKAGE" value="1" type="GuiHandlerData"/>
 <property name="PAViews_PROJECT_SUMMARY" value="25" type="GuiHandlerData"/>
 <property name="PAViews_SYSTEM" value="1" type="GuiHandlerData"/>
 <property name="PackageTreePanel_PACKAGE_TREE_PANEL" value="1" type="GuiHandlerData"/>
 <property name="PlanAheadTab_REFRESH_CHANGED_MODULES" value="1" type="GuiHandlerData"/>
 <property name="ProgramCfgMemDialog_CONTENTS_OF_CONFIGURATION_FILE" value="4" type="GuiHandlerData"/>
 <property name="ProgramCfgMemDialog_SPECIFY_ELF_FILE" value="4" type="GuiHandlerData"/>
 <property name="ProgramDebugTab_AVAILABLE_TARGETS_ON_SERVER" value="2" type="GuiHandlerData"/>
 <property name="ProgramDebugTab_OPEN_TARGET" value="9" type="GuiHandlerData"/>
 <property name="ProgramDebugTab_PROGRAM_DEVICE" value="4" type="GuiHandlerData"/>
 <property name="ProgramDebugTab_REFRESH_DEVICE" value="15" type="GuiHandlerData"/>
 <property name="ProgramFpgaDialog_PROGRAM" value="9" type="GuiHandlerData"/>
 <property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/>
 <property name="ProjectTab_CLOSE_DESIGN" value="2" type="GuiHandlerData"/>
 <property name="ProjectTab_RELOAD" value="1" type="GuiHandlerData"/>
 <property name="RDICommands_CUSTOM_COMMANDS" value="8" type="GuiHandlerData"/>
 <property name="RDICommands_DELETE" value="2" type="GuiHandlerData"/>
 <property name="RDICommands_PROPERTIES" value="4" type="GuiHandlerData"/>
 <property name="RDICommands_SETTINGS" value="1" type="GuiHandlerData"/>
 <property name="RDIViews_WAVEFORM_VIEWER" value="4" type="GuiHandlerData"/>
 <property name="RSBAddModuleDialog_MODULE_LIST" value="1" type="GuiHandlerData"/>
 <property name="RSBApplyAutomationBar_RUN_BLOCK_AUTOMATION" value="1" type="GuiHandlerData"/>
 <property name="RSBApplyAutomationBar_RUN_CONNECTION_AUTOMATION" value="2" type="GuiHandlerData"/>
 <property name="RSBExternalInterfacePropPanels_NAME" value="1" type="GuiHandlerData"/>
 <property name="SaveProjectUtils_SAVE" value="1" type="GuiHandlerData"/>
 <property name="SelectMenu_HIGHLIGHT" value="12" type="GuiHandlerData"/>
 <property name="SelectMenu_MARK" value="2" type="GuiHandlerData"/>
 <property name="SignalTreePanel_SIGNAL_TREE_TABLE" value="17" type="GuiHandlerData"/>
 <property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="6" type="GuiHandlerData"/>
 <property name="SimpleOutputProductDialog_SYNTHESIZE_DESIGN_GLOBALLY" value="1" type="GuiHandlerData"/>
 <property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="2" type="GuiHandlerData"/>
 <property name="SrcMenu_IP_HIERARCHY" value="23" type="GuiHandlerData"/>
 <property name="SrcMenu_REFRESH_HIERARCHY" value="23" type="GuiHandlerData"/>
 <property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="7" type="GuiHandlerData"/>
 <property name="SystemBuilderMenu_ADD_IP" value="1" type="GuiHandlerData"/>
 <property name="SystemBuilderMenu_ADD_MODULE" value="3" type="GuiHandlerData"/>
 <property name="SystemBuilderView_EXPAND_COLLAPSE" value="7" type="GuiHandlerData"/>
 <property name="SystemBuilderView_ORIENTATION" value="5" type="GuiHandlerData"/>
 <property name="SystemBuilderView_PINNING" value="10" type="GuiHandlerData"/>
 <property name="TaskBanner_CLOSE" value="5" type="GuiHandlerData"/>
 <property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiHandlerData"/>
 <property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="8" type="GuiHandlerData"/>
 </item>
 </section>
 </application>
 </document>
@@ -1,845 +0,0 @@
 *** Running vivado
    with args -log system_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace
 ****** Vivado v2023.2 (64-bit)
  **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
  **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
  **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
 source system_wrapper.tcl -notrace
 INFO: [IP_Flow 19-234] Refreshing IP repositories
 INFO: [IP_Flow 19-1704] No user IP repositories specified
 INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'.
 Command: link_design -top system_wrapper -part xc7z035ffg676-2
 Design is defaulting to srcset: sources_1
 Design is defaulting to constrset: constrs_1
 INFO: [Device 21-403] Loading part xc7z035ffg676-2
 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1722.395 ; gain = 0.000 ; free physical = 1995 ; free virtual = 71203
 INFO: [Netlist 29-17] Analyzing 39 Unisim elements for replacement
 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
 INFO: [Project 1-479] Netlist was created with Vivado 2023.2
 INFO: [Project 1-570] Preparing netlist for logic optimization
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
 WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-11' -to list should not be empty. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc:50]
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
 INFO: [Project 1-1687] 1 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design.
 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2307.883 ; gain = 0.000 ; free physical = 1722 ; free virtual = 70993
 INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 33 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 33 instances
 11 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
 link_design completed successfully
 link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2307.883 ; gain = 962.004 ; free physical = 1730 ; free virtual = 71000
 Command: opt_design
 Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
 Running DRC as a precondition to command opt_design
 Starting DRC Task
 INFO: [DRC 23-27] Running DRC with 8 threads
 INFO: [Project 1-461] DRC finished with 0 Errors
 INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
 Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2307.883 ; gain = 0.000 ; free physical = 1727 ; free virtual = 71012
 Starting Cache Timing Information Task
 INFO: [Timing 38-35] Done setting XDC timing constraints.
 Ending Cache Timing Information Task | Checksum: 2382775f8
 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2762.520 ; gain = 454.637 ; free physical = 1293 ; free virtual = 70618
 Starting Logic Optimization Task
 Phase 1 Initialization
 Phase 1.1 Core Generation And Design Setup
 Phase 1.1.1 Generate And Synthesize Debug Cores
 INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub 
 INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV.
 INFO: [Chipscope 16-329] Generating Script for core instance : u_ila_0 
 INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:ila:6.2 for cell u_ila_0_CV.
 Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3095.020 ; gain = 0.000 ; free physical = 9128 ; free virtual = 68708
 Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3201.777 ; gain = 0.000 ; free physical = 8923 ; free virtual = 68563
 Netlist sorting complete. Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.24 . Memory (MB): peak = 3378.160 ; gain = 0.000 ; free physical = 8306 ; free virtual = 68085
 Phase 1.1.1 Generate And Synthesize Debug Cores | Checksum: 1a85f7bbe
 Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8306 ; free virtual = 68085
 Phase 1.1 Core Generation And Design Setup | Checksum: 1a85f7bbe
 Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8306 ; free virtual = 68085
 Phase 1.2 Setup Constraints And Sort Netlist
 Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1a85f7bbe
 Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8306 ; free virtual = 68086
 Phase 1 Initialization | Checksum: 1a85f7bbe
 Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8300 ; free virtual = 68083
 Phase 2 Timer Update And Timing Data Collection
 Phase 2.1 Timer Update
 Phase 2.1 Timer Update | Checksum: 1a85f7bbe
 Time (s): cpu = 00:03:06 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8296 ; free virtual = 68078
 Phase 2.2 Timing Data Collection
 Phase 2.2 Timing Data Collection | Checksum: 1a85f7bbe
 Time (s): cpu = 00:03:06 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8279 ; free virtual = 68065
 Phase 2 Timer Update And Timing Data Collection | Checksum: 1a85f7bbe
 Time (s): cpu = 00:03:06 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8279 ; free virtual = 68065
 Phase 3 Retarget
 INFO: [Opt 31-138] Pushed 1 inverter(s) to 1 load pin(s).
 INFO: [Opt 31-49] Retargeted 0 cell(s).
 Phase 3 Retarget | Checksum: 20e292eaa
 Time (s): cpu = 00:03:07 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8270 ; free virtual = 68062
 Retarget | Checksum: 20e292eaa
 INFO: [Opt 31-389] Phase Retarget created 4 cells and removed 35 cells
 INFO: [Opt 31-1021] In phase Retarget, 99 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
 Phase 4 Constant propagation
 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
 Phase 4 Constant propagation | Checksum: 1fb9c5663
 Time (s): cpu = 00:03:07 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8271 ; free virtual = 68063
 Constant propagation | Checksum: 1fb9c5663
 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 16 cells
 INFO: [Opt 31-1021] In phase Constant propagation, 49 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
 Phase 5 Sweep
 Phase 5 Sweep | Checksum: 1dd19d44b
 Time (s): cpu = 00:03:08 ; elapsed = 00:03:18 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8274 ; free virtual = 68074
 Sweep | Checksum: 1dd19d44b
 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 46 cells
 INFO: [Opt 31-1021] In phase Sweep, 956 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
 Phase 6 BUFG optimization
 INFO: [Opt 31-194] Inserted BUFG system_i/dna_port_read_0/inst/read_vld_BUFG_inst to drive 57 load(s) on clock net system_i/dna_port_read_0/inst/read_vld_BUFG
 INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
 Phase 6 BUFG optimization | Checksum: 202feca59
 Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8266 ; free virtual = 68070
 BUFG optimization | Checksum: 202feca59
 INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 0 cells.
 Phase 7 Shift Register Optimization
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_A due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_B due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/I_YESLUT6.U_SRLC16E due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_A due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_B due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 due to none static srl address bits
 INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
 Phase 7 Shift Register Optimization | Checksum: 202feca59
 Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8263 ; free virtual = 68069
 Shift Register Optimization | Checksum: 202feca59
 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
 Phase 8 Post Processing Netlist
 Phase 8 Post Processing Netlist | Checksum: 202feca59
 Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8260 ; free virtual = 68067
 Post Processing Netlist | Checksum: 202feca59
 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
 INFO: [Opt 31-1021] In phase Post Processing Netlist, 57 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
 Phase 9 Finalization
 Phase 9.1 Finalizing Design Cores and Updating Shapes
 Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2572a104c
 Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8258 ; free virtual = 68070
 Phase 9.2 Verifying Netlist Connectivity
 Starting Connectivity Check Task
 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3442.176 ; gain = 0.000 ; free physical = 8255 ; free virtual = 68068
 Phase 9.2 Verifying Netlist Connectivity | Checksum: 2572a104c
 Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8255 ; free virtual = 68068
 Phase 9 Finalization | Checksum: 2572a104c
 Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8255 ; free virtual = 68068
 Opt_design Change Summary
 =========================
 -------------------------------------------------------------------------------------------------------------------------
 |  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
 -------------------------------------------------------------------------------------------------------------------------
 |  Retarget                     |               4  |              35  |                                             99  |
 |  Constant propagation         |               0  |              16  |                                             49  |
 |  Sweep                        |               0  |              46  |                                            956  |
 |  BUFG optimization            |               1  |               0  |                                              0  |
 |  Shift Register Optimization  |               0  |               0  |                                              0  |
 |  Post Processing Netlist      |               0  |               0  |                                             57  |
 -------------------------------------------------------------------------------------------------------------------------
 Ending Logic Optimization Task | Checksum: 2572a104c
 Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8254 ; free virtual = 68068
 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
 Done building netlist checker database: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3442.176 ; gain = 0.000 ; free physical = 8253 ; free virtual = 68067
 Starting Power Optimization Task
 INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
 INFO: [Power 33-23] Power model is not available for DNA_PORT_inst
 INFO: [Pwropt 34-9] Applying IDT optimizations ...
 INFO: [Pwropt 34-10] Applying ODC optimizations ...
 INFO: [Timing 38-35] Done setting XDC timing constraints.
 Running Vector-less Activity Propagation...
 Finished Running Vector-less Activity Propagation
 Starting PowerOpt Patch Enables Task
 INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 3 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
 INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
 Number of BRAM Ports augmented: 3 newly gated: 0 Total Ports: 6
 Ending PowerOpt Patch Enables Task | Checksum: 1c6a995af
 Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.24 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7922 ; free virtual = 67775
 Ending Power Optimization Task | Checksum: 1c6a995af
 Time (s): cpu = 00:00:11 ; elapsed = 00:00:04 . Memory (MB): peak = 3998.043 ; gain = 555.867 ; free physical = 7922 ; free virtual = 67775
 Starting Final Cleanup Task
 Ending Final Cleanup Task | Checksum: 1c6a995af
 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7922 ; free virtual = 67774
 Starting Netlist Obfuscation Task
 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7921 ; free virtual = 67776
 Ending Netlist Obfuscation Task | Checksum: 1b06a1b26
 Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7921 ; free virtual = 67776
 INFO: [Common 17-83] Releasing license: Implementation
 54 Infos, 82 Warnings, 0 Critical Warnings and 0 Errors encountered.
 opt_design completed successfully
 opt_design: Time (s): cpu = 00:03:26 ; elapsed = 00:03:28 . Memory (MB): peak = 3998.043 ; gain = 1690.160 ; free physical = 7921 ; free virtual = 67776
 INFO: [runtcl-4] Executing : report_drc -file system_wrapper_drc_opted.rpt -pb system_wrapper_drc_opted.pb -rpx system_wrapper_drc_opted.rpx
 Command: report_drc -file system_wrapper_drc_opted.rpt -pb system_wrapper_drc_opted.pb -rpx system_wrapper_drc_opted.rpx
 INFO: [IP_Flow 19-1839] IP Catalog is up to date.
 INFO: [DRC 23-27] Running DRC with 8 threads
 INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_drc_opted.rpt.
 report_drc completed successfully
 INFO: [Timing 38-35] Done setting XDC timing constraints.
 INFO: [Timing 38-480] Writing timing data to binary archive.
 Wrote PlaceDB: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7766 ; free virtual = 67648
 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7766 ; free virtual = 67648
 Writing XDEF routing.
 Writing XDEF routing logical nets.
 Write ShapeDB Complete: Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67652
 Writing XDEF routing special nets.
 Wrote RouteStorage: Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67653
 Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67653
 Wrote Device Cache: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67654
 Write Physdb Complete: Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67654
 INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_opt.dcp' has been generated.
 INFO: [Chipscope 16-240] Debug cores have already been implemented
 Command: place_design
 Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
 INFO: [Common 17-83] Releasing license: Implementation
 INFO: [DRC 23-27] Running DRC with 8 threads
 INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
 INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
 Running DRC as a precondition to command place_design
 INFO: [DRC 23-27] Running DRC with 8 threads
 INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
 INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
 Starting Placer Task
 Phase 1 Placer Initialization
 Phase 1.1 Placer Initialization Netlist Sorting
 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7612 ; free virtual = 67560
 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 19758bd7a
 Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7612 ; free virtual = 67559
 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7611 ; free virtual = 67559
 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 8751fbf6
 Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7587 ; free virtual = 67558
 Phase 1.3 Build Placer Netlist Model
 Phase 1.3 Build Placer Netlist Model | Checksum: dd0b0e99
 Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7431 ; free virtual = 67481
 Phase 1.4 Constrain Clocks/Macros
 Phase 1.4 Constrain Clocks/Macros | Checksum: dd0b0e99
 Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7428 ; free virtual = 67479
 Phase 1 Placer Initialization | Checksum: dd0b0e99
 Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7428 ; free virtual = 67479
 Phase 2 Global Placement
 Phase 2.1 Floorplanning
 Phase 2.1 Floorplanning | Checksum: eecb6848
 Time (s): cpu = 00:00:20 ; elapsed = 00:00:11 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7404 ; free virtual = 67474
 Phase 2.2 Update Timing before SLR Path Opt
 Phase 2.2 Update Timing before SLR Path Opt | Checksum: db55687b
 Time (s): cpu = 00:00:23 ; elapsed = 00:00:12 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7407 ; free virtual = 67493
 Phase 2.3 Post-Processing in Floorplanning
 Phase 2.3 Post-Processing in Floorplanning | Checksum: db55687b
 Time (s): cpu = 00:00:24 ; elapsed = 00:00:12 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7401 ; free virtual = 67488
 Phase 2.4 Global Placement Core
 Phase 2.4.1 UpdateTiming Before Physical Synthesis
 Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1e9ca9de9
 Time (s): cpu = 00:00:54 ; elapsed = 00:00:25 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7017 ; free virtual = 67264
 Phase 2.4.2 Physical Synthesis In Placer
 INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 1172 LUT instances to create LUTNM shape
 INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
 INFO: [Physopt 32-1138] End 1 Pass. Optimized 565 nets or LUTs. Breaked 0 LUT, combined 565 existing LUTs and moved 0 existing LUT
 INFO: [Physopt 32-65] No nets found for high-fanout optimization.
 INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
 INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
 INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
 INFO: [Physopt 32-670] No setup violation found.  Shift Register to Pipeline Optimization was not performed.
 INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
 INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
 INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
 INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
 INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7022 ; free virtual = 67279
 Summary of Physical Synthesis Optimizations
 ============================================
 -----------------------------------------------------------------------------------------------------------------------------------------------------------
 |  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
 -----------------------------------------------------------------------------------------------------------------------------------------------------------
 |  LUT Combining                                    |            0  |            565  |                   565  |           0  |           1  |  00:00:00  |
 |  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
 |  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
 |  DSP Register                                     |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
 |  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
 |  Shift Register                                   |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
 |  BRAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
 |  URAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
 |  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
 |  Total                                            |            0  |            565  |                   565  |           0  |           4  |  00:00:01  |
 -----------------------------------------------------------------------------------------------------------------------------------------------------------
 Phase 2.4.2 Physical Synthesis In Placer | Checksum: 2be40b2db
 Time (s): cpu = 00:00:59 ; elapsed = 00:00:28 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7014 ; free virtual = 67290
 Phase 2.4 Global Placement Core | Checksum: 2859c5ffd
 Time (s): cpu = 00:01:01 ; elapsed = 00:00:29 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7011 ; free virtual = 67293
 Phase 2 Global Placement | Checksum: 2859c5ffd
 Time (s): cpu = 00:01:01 ; elapsed = 00:00:29 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7011 ; free virtual = 67293
 Phase 3 Detail Placement
 Phase 3.1 Commit Multi Column Macros
 Phase 3.1 Commit Multi Column Macros | Checksum: 1ea091a8d
 Time (s): cpu = 00:01:05 ; elapsed = 00:00:30 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7007 ; free virtual = 67305
 Phase 3.2 Commit Most Macros & LUTRAMs
 Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 29969cf51
 Time (s): cpu = 00:01:13 ; elapsed = 00:00:35 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6986 ; free virtual = 67345
 Phase 3.3 Area Swap Optimization
 Phase 3.3 Area Swap Optimization | Checksum: 2b62d77e5
 Time (s): cpu = 00:01:14 ; elapsed = 00:00:35 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6984 ; free virtual = 67343
 Phase 3.4 Pipeline Register Optimization
 Phase 3.4 Pipeline Register Optimization | Checksum: 1ed299be3
 Time (s): cpu = 00:01:14 ; elapsed = 00:00:35 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6982 ; free virtual = 67342
 Phase 3.5 Small Shape Detail Placement
 Phase 3.5.1 Place Remaining
 Phase 3.5.1 Place Remaining | Checksum: 21b5bb37c
 Time (s): cpu = 00:01:20 ; elapsed = 00:00:41 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6918 ; free virtual = 67346
 Phase 3.5 Small Shape Detail Placement | Checksum: 21b5bb37c
 Time (s): cpu = 00:01:20 ; elapsed = 00:00:41 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6849 ; free virtual = 67281
 Phase 3.6 Re-assign LUT pins
 Phase 3.6 Re-assign LUT pins | Checksum: 1a6b845f5
 Time (s): cpu = 00:01:21 ; elapsed = 00:00:42 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6838 ; free virtual = 67277
 Phase 3.7 Pipeline Register Optimization
 Phase 3.7 Pipeline Register Optimization | Checksum: 1a81ce610
 Time (s): cpu = 00:01:21 ; elapsed = 00:00:42 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6834 ; free virtual = 67277
 Phase 3 Detail Placement | Checksum: 1a81ce610
 Time (s): cpu = 00:01:21 ; elapsed = 00:00:42 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6828 ; free virtual = 67276
 Phase 4 Post Placement Optimization and Clean-Up
 Phase 4.1 Post Commit Optimization
 INFO: [Timing 38-35] Done setting XDC timing constraints.
 Phase 4.1.1 Post Placement Optimization
 Post Placement Optimization Initialization | Checksum: 1472dfedc
 Phase 4.1.1.1 BUFG Insertion
 Starting Physical Synthesis Task
 Phase 1 Physical Synthesis Initialization
 INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.626 | TNS=0.000 |
 Phase 1 Physical Synthesis Initialization | Checksum: a925bbef
 Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6782 ; free virtual = 67315
 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
 Ending Physical Synthesis Task | Checksum: a925bbef
 Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6769 ; free virtual = 67309
 Phase 4.1.1.1 BUFG Insertion | Checksum: 1472dfedc
 Time (s): cpu = 00:01:38 ; elapsed = 00:00:50 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6768 ; free virtual = 67314
 Phase 4.1.1.2 Post Placement Timing Optimization
 INFO: [Place 30-746] Post Placement Timing Summary WNS=2.626. For the most accurate timing information please run report_timing.
 Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 14f55351a
 Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6755 ; free virtual = 67307
 Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6755 ; free virtual = 67307
 Phase 4.1 Post Commit Optimization | Checksum: 14f55351a
 Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6755 ; free virtual = 67307
 Phase 4.2 Post Placement Cleanup
 Phase 4.2 Post Placement Cleanup | Checksum: 14f55351a
 Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6750 ; free virtual = 67308
 Phase 4.3 Placer Reporting
 Phase 4.3.1 Print Estimated Congestion
 INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
 |           | Global Congestion | Short Congestion  |
 | Direction | Region Size       | Region Size       |
 |___________|___________________|___________________|
 |      North|                2x2|                2x2|
 |___________|___________________|___________________|
 |      South|                1x1|                1x1|
 |___________|___________________|___________________|
 |       East|                1x1|                1x1|
 |___________|___________________|___________________|
 |       West|                1x1|                1x1|
 |___________|___________________|___________________|
 Phase 4.3.1 Print Estimated Congestion | Checksum: 14f55351a
 Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6748 ; free virtual = 67312
 Phase 4.3 Placer Reporting | Checksum: 14f55351a
 Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6751 ; free virtual = 67321
 Phase 4.4 Final Placement Cleanup
 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6751 ; free virtual = 67321
 Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6751 ; free virtual = 67321
 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 19c30fa75
 Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6741 ; free virtual = 67314
 Ending Placer Task | Checksum: dcf0239e
 Time (s): cpu = 00:01:41 ; elapsed = 00:00:53 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6725 ; free virtual = 67298
 90 Infos, 82 Warnings, 0 Critical Warnings and 0 Errors encountered.
 place_design completed successfully
 place_design: Time (s): cpu = 00:01:44 ; elapsed = 00:00:54 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6725 ; free virtual = 67298
 INFO: [runtcl-4] Executing : report_io -file system_wrapper_io_placed.rpt
 report_io: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6722 ; free virtual = 67295
 INFO: [runtcl-4] Executing : report_utilization -file system_wrapper_utilization_placed.rpt -pb system_wrapper_utilization_placed.pb
 INFO: [runtcl-4] Executing : report_control_sets -verbose -file system_wrapper_control_sets_placed.rpt
 report_control_sets: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6708 ; free virtual = 67293
 INFO: [Timing 38-480] Writing timing data to binary archive.
 Write ShapeDB Complete: Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6731 ; free virtual = 67329
 Wrote PlaceDB: Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6584 ; free virtual = 67235
 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6584 ; free virtual = 67235
 Writing XDEF routing.
 Writing XDEF routing logical nets.
 Writing XDEF routing special nets.
 Wrote RouteStorage: Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6584 ; free virtual = 67236
 Wrote Netlist Cache: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6582 ; free virtual = 67237
 Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6582 ; free virtual = 67238
 Write Physdb Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6581 ; free virtual = 67237
 INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_placed.dcp' has been generated.
 Command: route_design
 Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
 Running DRC as a precondition to command route_design
 INFO: [DRC 23-27] Running DRC with 8 threads
 INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
 INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
 Starting Routing Task
 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
 Phase 1 Build RT Design
 Checksum: PlaceDB: 76da8209 ConstDB: 0 ShapeSum: 6615a195 RouteDB: 0
 Post Restoration Checksum: NetGraph: 4a144a14 | NumContArr: af14b29e | Constraints: c2a8fa9d | Timing: c2a8fa9d
 Phase 1 Build RT Design | Checksum: 27e7af1ec
 Time (s): cpu = 00:00:49 ; elapsed = 00:00:32 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 5905 ; free virtual = 66985
 Phase 2 Router Initialization
 Phase 2.1 Fix Topology Constraints
 Phase 2.1 Fix Topology Constraints | Checksum: 27e7af1ec
 Time (s): cpu = 00:00:50 ; elapsed = 00:00:32 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 5899 ; free virtual = 66984
 Phase 2.2 Pre Route Cleanup
 Phase 2.2 Pre Route Cleanup | Checksum: 27e7af1ec
 Time (s): cpu = 00:00:50 ; elapsed = 00:00:32 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 5899 ; free virtual = 66984
 Number of Nodes with overlaps = 0
 Phase 2.3 Update Timing
 Phase 2.3 Update Timing | Checksum: 32928bcd2
 Time (s): cpu = 00:01:06 ; elapsed = 00:00:40 . Memory (MB): peak = 4046.500 ; gain = 48.457 ; free physical = 5635 ; free virtual = 66801
 INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.632  | TNS=0.000  | WHS=-0.263 | THS=-1616.164|
 Phase 2.4 Update Timing for Bus Skew
 Phase 2.4.1 Update Timing
 Phase 2.4.1 Update Timing | Checksum: 2864114c5
 Time (s): cpu = 00:01:19 ; elapsed = 00:00:43 . Memory (MB): peak = 4046.500 ; gain = 48.457 ; free physical = 5449 ; free virtual = 66672
 INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.632  | TNS=0.000  | WHS=N/A    | THS=N/A    |
 Phase 2.4 Update Timing for Bus Skew | Checksum: 291576a87
 Time (s): cpu = 00:01:19 ; elapsed = 00:00:44 . Memory (MB): peak = 4046.500 ; gain = 48.457 ; free physical = 5447 ; free virtual = 66671
 Router Utilization Summary
  Global Vertical Routing Utilization    = 0.0211705 %
  Global Horizontal Routing Utilization  = 0.00488761 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 38492
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 38484
  Number of Partially Routed Nets     = 8
  Number of Node Overlaps             = 6
 Phase 2 Router Initialization | Checksum: 2a426d310
 Time (s): cpu = 00:01:20 ; elapsed = 00:00:44 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5405 ; free virtual = 66633
 Phase 3 Initial Routing
 Phase 3.1 Global Routing
 Phase 3.1 Global Routing | Checksum: 2a426d310
 Time (s): cpu = 00:01:20 ; elapsed = 00:00:44 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5405 ; free virtual = 66633
 Phase 3.2 Initial Net Routing
 Phase 3.2 Initial Net Routing | Checksum: 22defbe6f
 Time (s): cpu = 00:01:27 ; elapsed = 00:00:46 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5394 ; free virtual = 66641
 Phase 3 Initial Routing | Checksum: 22defbe6f
 Time (s): cpu = 00:01:27 ; elapsed = 00:00:46 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5394 ; free virtual = 66641
 Phase 4 Rip-up And Reroute
 Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 2836
 Number of Nodes with overlaps = 86
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 0
 INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.177  | TNS=0.000  | WHS=N/A    | THS=N/A    |
 Phase 4.1 Global Iteration 0 | Checksum: 23a222cd5
 Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5385 ; free virtual = 66739
 Phase 4 Rip-up And Reroute | Checksum: 23a222cd5
 Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5385 ; free virtual = 66739
 Phase 5 Delay and Skew Optimization
 Phase 5.1 Delay CleanUp
 Phase 5.1 Delay CleanUp | Checksum: 23a222cd5
 Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5384 ; free virtual = 66738
 Phase 5.2 Clock Skew Optimization
 Phase 5.2 Clock Skew Optimization | Checksum: 23a222cd5
 Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5384 ; free virtual = 66738
 Phase 5 Delay and Skew Optimization | Checksum: 23a222cd5
 Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5384 ; free virtual = 66738
 Phase 6 Post Hold Fix
 Phase 6.1 Hold Fix Iter
 Phase 6.1.1 Update Timing
 Phase 6.1.1 Update Timing | Checksum: 2a8514d39
 Time (s): cpu = 00:01:47 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5382 ; free virtual = 66749
 INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.189  | TNS=0.000  | WHS=0.028  | THS=0.000  |
 Phase 6.1 Hold Fix Iter | Checksum: 253fa4620
 Time (s): cpu = 00:01:47 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748
 Phase 6 Post Hold Fix | Checksum: 253fa4620
 Time (s): cpu = 00:01:47 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748
 Phase 7 Route finalize
 Router Utilization Summary
  Global Vertical Routing Utilization    = 2.42898 %
  Global Horizontal Routing Utilization  = 2.87613 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0
 Phase 7 Route finalize | Checksum: 253fa4620
 Time (s): cpu = 00:01:48 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748
 Phase 8 Verifying routed nets
 Verification completed successfully
 Phase 8 Verifying routed nets | Checksum: 253fa4620
 Time (s): cpu = 00:01:48 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748
 Phase 9 Depositing Routes
 Phase 9 Depositing Routes | Checksum: 24ae08112
 Time (s): cpu = 00:01:50 ; elapsed = 00:00:57 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5378 ; free virtual = 66754
 Phase 10 Post Router Timing
 INFO: [Route 35-57] Estimated Timing Summary | WNS=1.189  | TNS=0.000  | WHS=0.028  | THS=0.000  |
 INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
 Phase 10 Post Router Timing | Checksum: 24ae08112
 Time (s): cpu = 00:01:53 ; elapsed = 00:00:58 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5367 ; free virtual = 66762
 INFO: [Route 35-16] Router Completed Successfully
 Phase 11 Post-Route Event Processing
 Phase 11 Post-Route Event Processing | Checksum: 10a817867
 Time (s): cpu = 00:01:54 ; elapsed = 00:00:59 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5358 ; free virtual = 66761
 Ending Routing Task | Checksum: 10a817867
 Time (s): cpu = 00:01:55 ; elapsed = 00:01:00 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5334 ; free virtual = 66752
 Routing Is Done.
 INFO: [Common 17-83] Releasing license: Implementation
 108 Infos, 82 Warnings, 0 Critical Warnings and 0 Errors encountered.
 route_design completed successfully
 route_design: Time (s): cpu = 00:01:59 ; elapsed = 00:01:02 . Memory (MB): peak = 4083.043 ; gain = 85.000 ; free physical = 5335 ; free virtual = 66757
 INFO: [runtcl-4] Executing : report_drc -file system_wrapper_drc_routed.rpt -pb system_wrapper_drc_routed.pb -rpx system_wrapper_drc_routed.rpx
 Command: report_drc -file system_wrapper_drc_routed.rpt -pb system_wrapper_drc_routed.pb -rpx system_wrapper_drc_routed.rpx
 INFO: [IP_Flow 19-1839] IP Catalog is up to date.
 INFO: [DRC 23-27] Running DRC with 8 threads
 INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_drc_routed.rpt.
 report_drc completed successfully
 INFO: [runtcl-4] Executing : report_methodology -file system_wrapper_methodology_drc_routed.rpt -pb system_wrapper_methodology_drc_routed.pb -rpx system_wrapper_methodology_drc_routed.rpx
 Command: report_methodology -file system_wrapper_methodology_drc_routed.rpt -pb system_wrapper_methodology_drc_routed.pb -rpx system_wrapper_methodology_drc_routed.rpx
 INFO: [Timing 38-35] Done setting XDC timing constraints.
 INFO: [DRC 23-133] Running Methodology with 8 threads
 INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_methodology_drc_routed.rpt.
 report_methodology completed successfully
 report_methodology: Time (s): cpu = 00:00:18 ; elapsed = 00:00:06 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5233 ; free virtual = 66738
 INFO: [runtcl-4] Executing : report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx
 Command: report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx
 INFO: [Power 33-23] Power model is not available for DNA_PORT_inst
 INFO: [Timing 38-35] Done setting XDC timing constraints.
 Running Vector-less Activity Propagation...
 Finished Running Vector-less Activity Propagation
 WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
 Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
 119 Infos, 83 Warnings, 0 Critical Warnings and 0 Errors encountered.
 report_power completed successfully
 report_power: Time (s): cpu = 00:00:16 ; elapsed = 00:00:06 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5140 ; free virtual = 66731
 INFO: [runtcl-4] Executing : report_route_status -file system_wrapper_route_status.rpt -pb system_wrapper_route_status.pb
 INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file system_wrapper_timing_summary_routed.rpt -pb system_wrapper_timing_summary_routed.pb -rpx system_wrapper_timing_summary_routed.rpx -warn_on_violation 
 INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
 INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
 WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
 INFO: [runtcl-4] Executing : report_incremental_reuse -file system_wrapper_incremental_reuse_routed.rpt
 INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
 INFO: [runtcl-4] Executing : report_clock_utilization -file system_wrapper_clock_utilization_routed.rpt
 INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file system_wrapper_bus_skew_routed.rpt -pb system_wrapper_bus_skew_routed.pb -rpx system_wrapper_bus_skew_routed.rpx
 INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
 INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
 INFO: [Timing 38-480] Writing timing data to binary archive.
 Write ShapeDB Complete: Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5090 ; free virtual = 66740
 Wrote PlaceDB: Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5008 ; free virtual = 66718
 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5008 ; free virtual = 66718
 Writing XDEF routing.
 Writing XDEF routing logical nets.
 Writing XDEF routing special nets.
 Wrote RouteStorage: Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.29 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66717
 Wrote Netlist Cache: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66719
 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66720
 Write Physdb Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66721
 INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_routed.dcp' has been generated.
 Command: write_bitstream -force system_wrapper.bit
 Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
 Running DRC as a precondition to command write_bitstream
 INFO: [IP_Flow 19-1839] IP Catalog is up to date.
 INFO: [DRC 23-27] Running DRC with 8 threads
 WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A3' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1/I0) is not included in the LUT equation: 'O5=(A1*A2)+(A1*(~A2)*(~A4))+((~A1))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
 WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A3' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[0]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[0]_i_1/I0) is not included in the LUT equation: 'O6=(A6+~A6)*((A5))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
 WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A5' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1/I1) is not included in the LUT equation: 'O5=(A1*A2)+(A1*(~A2)*(~A4))+((~A1))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
 WARNING: [DRC RTSTAT-10] No routable loads: 21 net(s) have no routable loads. The problem bus(es) and/or net(s) are dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TMS, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg[2:0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_capture[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_runtest[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i... and (the first 15 of 19 listed).
 INFO: [Vivado 12-3199] DRC finished with 0 Errors, 4 Warnings
 INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
 Loading data files...
 Loading site data...
 Loading route data...
 Processing options...
 Creating bitmap...
 Creating bitstream...
 Writing bitstream ./system_wrapper.bit...
 INFO: [Vivado 12-1842] Bitgen Completed Successfully.
 INFO: [Common 17-83] Releasing license: Implementation
 13 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
 write_bitstream completed successfully
 write_bitstream: Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 4599.906 ; gain = 300.855 ; free physical = 4256 ; free virtual = 66217
 INFO: [Common 17-206] Exiting Vivado at Wed May 27 16:43:10 2026...
@@ -1,696 +0,0 @@
 *** Running vivado
    with args -log system_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl
 ****** Vivado v2023.2 (64-bit)
  **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
  **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
  **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
 source system_wrapper.tcl -notrace
 INFO: [IP_Flow 19-234] Refreshing IP repositories
 INFO: [IP_Flow 19-1704] No user IP repositories specified
 INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'.
 Command: synth_design -top system_wrapper -part xc7z035ffg676-2
 Starting synth_design
 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035'
 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035'
 INFO: [Device 21-403] Loading part xc7z035ffg676-2
 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
 INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
 INFO: [Synth 8-7075] Helper process launched with PID 958941
 ---------------------------------------------------------------------------------
 Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2149.453 ; gain = 411.629 ; free physical = 845 ; free virtual = 70077
 ---------------------------------------------------------------------------------
 WARNING: [Synth 8-11121] redeclaration of ANSI port 'read_vld' is not allowed [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:33]
 WARNING: [Synth 8-11121] redeclaration of ANSI port 'dna_port' is not allowed [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:34]
 INFO: [Synth 8-6157] synthesizing module 'system_wrapper' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:13]
 INFO: [Synth 8-6157] synthesizing module 'IOBUF' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:78197]
 INFO: [Synth 8-6155] done synthesizing module 'IOBUF' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:78197]
 INFO: [Synth 8-6157] synthesizing module 'system' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:318]
 INFO: [Synth 8-6157] synthesizing module 'system_dna_port_read_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_dna_port_read_0_0/synth/system_dna_port_read_0_0.v:53]
 INFO: [Synth 8-6157] synthesizing module 'dna_port_read' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:23]
 INFO: [Synth 8-6157] synthesizing module 'DNA_PORT' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:39264]
 	Parameter SIM_DNA_VALUE bound to: 57'b000000000000000000000000000000000000000000000000000000000 
 INFO: [Synth 8-6155] done synthesizing module 'DNA_PORT' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:39264]
 INFO: [Synth 8-6155] done synthesizing module 'dna_port_read' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:23]
 INFO: [Synth 8-6155] done synthesizing module 'system_dna_port_read_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_dna_port_read_0_0/synth/system_dna_port_read_0_0.v:53]
 INFO: [Synth 8-6157] synthesizing module 'system_mydna_read_v1_0_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_mydna_read_v1_0_0_0/synth/system_mydna_read_v1_0_0_0.v:53]
 INFO: [Synth 8-6157] synthesizing module 'mydna_read_v1_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0.v:4]
 	Parameter C_S00_AXI_DATA_WIDTH bound to: 32 - type: integer 
 	Parameter C_S00_AXI_ADDR_WIDTH bound to: 4 - type: integer 
 INFO: [Synth 8-6157] synthesizing module 'mydna_read_v1_0_S00_AXI' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:4]
 	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
 	Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer 
 INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:235]
 INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:379]
 INFO: [Synth 8-6155] done synthesizing module 'mydna_read_v1_0_S00_AXI' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:4]
 INFO: [Synth 8-6155] done synthesizing module 'mydna_read_v1_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0.v:4]
 INFO: [Synth 8-6155] done synthesizing module 'system_mydna_read_v1_0_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_mydna_read_v1_0_0_0/synth/system_mydna_read_v1_0_0_0.v:53]
 INFO: [Synth 8-6157] synthesizing module 'system_processing_system7_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:53]
 INFO: [Synth 8-6157] synthesizing module 'processing_system7_v5_5_processing_system7' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152]
 INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
 INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
 INFO: [Synth 8-6157] synthesizing module 'BIBUF' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1598]
 INFO: [Synth 8-6155] done synthesizing module 'BIBUF' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1598]
 INFO: [Synth 8-6157] synthesizing module 'PS7' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111859]
 INFO: [Synth 8-6155] done synthesizing module 'PS7' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111859]
 INFO: [Synth 8-6155] done synthesizing module 'processing_system7_v5_5_processing_system7' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152]
 WARNING: [Synth 8-7071] port 'M_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'M_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'S_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'S_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'S_AXI_ACP_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'S_AXI_HP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'S_AXI_HP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'S_AXI_HP2_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'S_AXI_HP3_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'DMA0_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'DMA1_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'DMA2_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'DMA3_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7023] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 INFO: [Synth 8-6155] done synthesizing module 'system_processing_system7_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:53]
 INFO: [Synth 8-6157] synthesizing module 'system_ps7_0_axi_periph_1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:632]
 INFO: [Synth 8-6157] synthesizing module 's00_couplers_imp_11SE3QO' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:13]
 INFO: [Synth 8-6157] synthesizing module 'system_auto_pc_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v:53]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_axi_protocol_converter' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5285]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4704]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_aw_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4360]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_cmd_translator' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3720]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_incr_cmd' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3216]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_incr_cmd' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3216]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wrap_cmd' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2982]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wrap_cmd' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2982]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_cmd_translator' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3720]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3392]
 INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3446]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3392]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_aw_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4360]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_b_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3906]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_b_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3906]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_ar_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4516]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3546]
 INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3608]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3546]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_ar_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4516]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_r_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4155]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_r_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4155]
 INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
 INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
 INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
 INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
 INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
 INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized2' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
 WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'SI_REG' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4871]
 WARNING: [Synth 8-7023] instance 'SI_REG' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4871]
 INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
 INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
 INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
 INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
 INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
 INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized3' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized3' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized4' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized4' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized5' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized5' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized6' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized6' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
 WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'MI_REG' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5126]
 WARNING: [Synth 8-7023] instance 'MI_REG' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5126]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4704]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_axi_protocol_converter' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5285]
 INFO: [Synth 8-6155] done synthesizing module 'system_auto_pc_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v:53]
 INFO: [Synth 8-6155] done synthesizing module 's00_couplers_imp_11SE3QO' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:13]
 INFO: [Synth 8-6155] done synthesizing module 'system_ps7_0_axi_periph_1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:632]
 INFO: [Synth 8-638] synthesizing module 'system_rst_ps7_0_100M_1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:74]
 	Parameter C_FAMILY bound to: zynq - type: string 
 	Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer 
 	Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer 
 	Parameter C_EXT_RESET_HIGH bound to: 1'b0 
 	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
 	Parameter C_NUM_BUS_RST bound to: 1 - type: integer 
 	Parameter C_NUM_PERP_RST bound to: 1 - type: integer 
 	Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer 
 	Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer 
 INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1271' bound to instance 'U0' of component 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:129]
 INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330]
 	Parameter INIT bound to: 1'b1 
 INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1399]
 	Parameter INIT bound to: 1'b1 
 INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1415]
 	Parameter INIT bound to: 1'b0 
 INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1441]
 	Parameter INIT bound to: 1'b1 
 INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1464]
 	Parameter INIT bound to: 1'b0 
 INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1488]
 INFO: [Synth 8-638] synthesizing module 'lpf' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821]
 INFO: [Synth 8-3491] module 'SRL16' declared at '/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721' bound to instance 'POR_SRL_I' of component 'SRL16' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:873]
 INFO: [Synth 8-6157] synthesizing module 'SRL16' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721]
 INFO: [Synth 8-6155] done synthesizing module 'SRL16' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721]
 INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
 	Parameter INIT bound to: 1'b0 
 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:514]
 	Parameter INIT bound to: 1'b0 
 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:545]
 	Parameter INIT bound to: 1'b0 
 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:554]
 	Parameter INIT bound to: 1'b0 
 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:564]
 	Parameter INIT bound to: 1'b0 
 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:574]
 	Parameter INIT bound to: 1'b0 
 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:584]
 INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
 INFO: [Synth 8-256] done synthesizing module 'lpf' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821]
 INFO: [Synth 8-638] synthesizing module 'sequence_psr' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304]
 INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126]
 INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126]
 INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304]
 INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330]
 INFO: [Synth 8-256] done synthesizing module 'system_rst_ps7_0_100M_1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:74]
 WARNING: [Synth 8-7071] port 'mb_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
 WARNING: [Synth 8-7071] port 'bus_struct_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
 WARNING: [Synth 8-7071] port 'peripheral_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
 WARNING: [Synth 8-7023] instance 'rst_ps7_0_100M' of module 'system_rst_ps7_0_100M_1' has 10 connections declared, but only 7 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
 INFO: [Synth 8-6155] done synthesizing module 'system' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:318]
 INFO: [Synth 8-6155] done synthesizing module 'system_wrapper' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:13]
 WARNING: [Synth 8-6014] Unused sequential element slv_reg1_reg was removed.  [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:228]
 WARNING: [Synth 8-6014] Unused sequential element slv_reg2_reg was removed.  [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:229]
 WARNING: [Synth 8-6014] Unused sequential element state_r1_reg was removed.  [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3596]
 WARNING: [Synth 8-6014] Unused sequential element s_arlen_r_reg was removed.  [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3597]
 WARNING: [Synth 8-7129] Port prmry_aclk in module cdc_sync is either unconnected or has no load
 WARNING: [Synth 8-7129] Port prmry_resetn in module cdc_sync is either unconnected or has no load
 WARNING: [Synth 8-7129] Port prmry_vect_in[1] in module cdc_sync is either unconnected or has no load
 WARNING: [Synth 8-7129] Port prmry_vect_in[0] in module cdc_sync is either unconnected or has no load
 WARNING: [Synth 8-7129] Port scndry_resetn in module cdc_sync is either unconnected or has no load
 WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized6 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized6 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized3 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized3 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized5 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized5 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized4 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized4 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port m_axi_bid[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port m_axi_buser[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port m_axi_rid[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port m_axi_rlast in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port m_axi_ruser[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awlen[7] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awlen[6] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awlen[5] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awlen[4] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awlen[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awlen[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awlen[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awlen[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awsize[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awsize[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awsize[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awburst[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awburst[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awlock[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awcache[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awcache[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awcache[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awcache[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awregion[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awregion[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awregion[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awregion[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awqos[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awqos[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awqos[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awqos[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awuser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_wid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_wlast in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_wuser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arlen[7] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arlen[6] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arlen[5] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arlen[4] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arlen[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arlen[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arlen[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arlen[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arsize[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arsize[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arsize[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arburst[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arburst[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arlock[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arcache[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arcache[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arcache[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arcache[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arregion[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arregion[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arregion[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arregion[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arqos[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arqos[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arqos[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arqos[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_aruser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port aclk2x in module axi_register_slice_v2_1_29_axi_register_slice__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port m_axi_buser[0] in module axi_infrastructure_v1_1_0_vector2axi is either unconnected or has no load
 WARNING: [Synth 8-7129] Port m_axi_ruser[0] in module axi_infrastructure_v1_1_0_vector2axi is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awregion[3] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awregion[2] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awregion[1] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awregion[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awuser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_wuser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arregion[3] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arregion[2] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arregion[1] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arregion[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_aruser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port aclk2x in module axi_register_slice_v2_1_29_axi_register_slice is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_arlen[7] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_arlen[6] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_arlen[5] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_arlen[4] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_arlen[3] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_arlen[2] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
 INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
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 Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 767 ; free virtual = 69885
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Handling Custom Attributes
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 768 ; free virtual = 69891
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 768 ; free virtual = 69891
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 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2359.391 ; gain = 0.000 ; free physical = 749 ; free virtual = 69874
 INFO: [Netlist 29-17] Analyzing 46 Unisim elements for replacement
 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
 INFO: [Project 1-570] Preparing netlist for logic optimization
 Processing XDC Constraints
 Initializing timing engine
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
 INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
 Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
 INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
 Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
 INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
 Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
 INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
 Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc]
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc]
 INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
 Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
 Completed Processing XDC Constraints
 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2518.867 ; gain = 0.000 ; free physical = 714 ; free virtual = 69858
 INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 46 instances were transformed.
  FDR => FDRE: 12 instances
  IOBUF => IOBUF (IBUF, OBUFT): 33 instances
  SRL16 => SRL16E: 1 instance 
 Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2518.902 ; gain = 0.000 ; free physical = 872 ; free virtual = 69870
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 Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 946 ; free virtual = 69833
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Loading Part and Timing Information
 ---------------------------------------------------------------------------------
 Loading part: xc7z035ffg676-2
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 Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 945 ; free virtual = 69833
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Applying 'set_property' XDC Constraints
 ---------------------------------------------------------------------------------
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_0. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 1).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_1. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 2).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_2. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 3).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_3. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 4).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_4. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 5).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_5. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 6).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_6. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 7).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_7. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 8).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_8. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 9).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_9. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 10).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_10. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 11).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_11. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 12).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_12. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 13).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_13. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 14).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_14. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 15).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_15. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 16).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_16. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 17).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_17. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 18).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_18. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 19).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_19. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 20).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_20. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 21).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_21. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 22).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_22. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 23).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_23. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 24).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_24. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 25).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_25. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 26).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_28. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 27).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_29. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 28).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_30. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 29).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_26. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 30).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_27. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 31).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_31. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 32).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_32. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 33).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_o_0. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 34).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_t_0. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 67).
 Applied set_property KEEP_HIERARCHY = SOFT for system_i/processing_system7_0/inst. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc, line 30).
 Applied set_property KEEP_HIERARCHY = SOFT for system_i/rst_ps7_0_100M/U0. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc, line 35).
 Applied set_property KEEP_HIERARCHY = SOFT for system_i. (constraint file  auto generated constraint).
 Applied set_property KEEP_HIERARCHY = SOFT for system_i/processing_system7_0. (constraint file  auto generated constraint).
 Applied set_property KEEP_HIERARCHY = SOFT for system_i/dna_port_read_0. (constraint file  auto generated constraint).
 Applied set_property KEEP_HIERARCHY = SOFT for system_i/mydna_read_v1_0_0. (constraint file  auto generated constraint).
 Applied set_property KEEP_HIERARCHY = SOFT for system_i/ps7_0_axi_periph/s00_couplers/auto_pc. (constraint file  auto generated constraint).
 Applied set_property KEEP_HIERARCHY = SOFT for system_i/ps7_0_axi_periph. (constraint file  auto generated constraint).
 Applied set_property KEEP_HIERARCHY = SOFT for system_i/rst_ps7_0_100M. (constraint file  auto generated constraint).
 ---------------------------------------------------------------------------------
 Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 940 ; free virtual = 69830
 ---------------------------------------------------------------------------------
 INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm'
 INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm'
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_0'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:213]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_1'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:218]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_2'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:273]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_3'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:328]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_4'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:348]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_5'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:353]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_6'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:358]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_7'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:363]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_8'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:368]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_9'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:373]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_10'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:223]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_11'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:228]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_12'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:233]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_13'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:238]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_14'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:243]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_15'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:248]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_16'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:253]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_17'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:258]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_18'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:263]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_19'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:268]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_20'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:278]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_21'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:283]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_22'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:288]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_23'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:293]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_24'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:298]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_25'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:303]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_28'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:318]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_29'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:323]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_30'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:333]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_26'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:308]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_27'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:313]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_31'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:338]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_32'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:343]
 WARNING: [Synth 8-327] inferring latch for variable 'dna_port_reg_reg' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:413]
 ---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
 ---------------------------------------------------------------------------------------------------
                 SM_IDLE |                               01 |                               00
               SM_CMD_EN |                               11 |                               01
         SM_CMD_ACCEPTED |                               10 |                               10
            SM_DONE_WAIT |                               00 |                               11
 ---------------------------------------------------------------------------------------------------
 INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm'
 ---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
 ---------------------------------------------------------------------------------------------------
                 SM_IDLE |                               01 |                               00
               SM_CMD_EN |                               11 |                               01
         SM_CMD_ACCEPTED |                               10 |                               10
                 SM_DONE |                               00 |                               11
 ---------------------------------------------------------------------------------------------------
 INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm'
 ---------------------------------------------------------------------------------
 Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 929 ; free virtual = 69825
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start RTL Component Statistics 
 ---------------------------------------------------------------------------------
 Detailed RTL Component Info : 
 +---Adders : 
 	   2 Input   12 Bit       Adders := 8     
 	   2 Input    9 Bit       Adders := 2     
 	   2 Input    8 Bit       Adders := 2     
 	   2 Input    6 Bit       Adders := 1     
 	   2 Input    5 Bit       Adders := 4     
 	   2 Input    4 Bit       Adders := 4     
 	   2 Input    2 Bit       Adders := 2     
 +---Registers : 
 	               66 Bit    Registers := 4     
 	               57 Bit    Registers := 1     
 	               47 Bit    Registers := 2     
 	               32 Bit    Registers := 3     
 	               14 Bit    Registers := 2     
 	               12 Bit    Registers := 9     
 	                9 Bit    Registers := 2     
 	                8 Bit    Registers := 3     
 	                6 Bit    Registers := 1     
 	                5 Bit    Registers := 4     
 	                4 Bit    Registers := 8     
 	                3 Bit    Registers := 3     
 	                2 Bit    Registers := 9     
 	                1 Bit    Registers := 43    
 +---Muxes : 
 	   2 Input   66 Bit        Muxes := 4     
 	   2 Input   47 Bit        Muxes := 2     
 	   4 Input   32 Bit        Muxes := 3     
 	   2 Input   32 Bit        Muxes := 9     
 	   2 Input   14 Bit        Muxes := 2     
 	   2 Input   12 Bit        Muxes := 6     
 	   2 Input    9 Bit        Muxes := 4     
 	   2 Input    8 Bit        Muxes := 1     
 	   2 Input    6 Bit        Muxes := 1     
 	   2 Input    5 Bit        Muxes := 4     
 	   2 Input    4 Bit        Muxes := 18    
 	   2 Input    2 Bit        Muxes := 17    
 	   4 Input    2 Bit        Muxes := 4     
 	   2 Input    1 Bit        Muxes := 37    
 ---------------------------------------------------------------------------------
 Finished RTL Component Statistics 
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Part Resource Summary
 ---------------------------------------------------------------------------------
 Part Resources:
 DSPs: 900 (col length:140)
 BRAMs: 1000 (col length: RAMB18 140 RAMB36 70)
 ---------------------------------------------------------------------------------
 Finished Part Resource Summary
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Cross Boundary and Area Optimization
 ---------------------------------------------------------------------------------
 WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
 INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '66' to '62' bits. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726]
 INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '66' to '62' bits. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726]
 WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (FDRE_inst) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (BSR_OUT_DFF[0].FDRE_BSR) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (PR_OUT_DFF[0].FDRE_PER) is unused and will be removed from module proc_sys_reset.
 ---------------------------------------------------------------------------------
 Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1838 ; free virtual = 70743
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Applying XDC Timing Constraints
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1815 ; free virtual = 70747
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Timing Optimization
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1781 ; free virtual = 70713
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Technology Mapping
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1765 ; free virtual = 70711
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start IO Insertion
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Flattening Before IO Insertion
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Flattening Before IO Insertion
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Final Netlist Cleanup
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Final Netlist Cleanup
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70517
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Renaming Generated Instances
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70517
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Rebuilding User Hierarchy
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Renaming Generated Ports
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Handling Custom Attributes
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Renaming Generated Nets
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start ROM, RAM, DSP, Shift Register and Retiming Reporting
 ---------------------------------------------------------------------------------
 Dynamic Shift Register Report:
 +------------+----------------+--------+------------+--------+---------+--------+--------+--------+
 |Module Name | RTL Name       | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 | 
 +------------+----------------+--------+------------+--------+---------+--------+--------+--------+
 |dsrl        | memory_reg[3]  | 20     | 20         | 20     | 0       | 0      | 0      | 0      | 
 |dsrl__1     | memory_reg[3]  | 2      | 2          | 2      | 0       | 0      | 0      | 0      | 
 |dsrl__2     | memory_reg[31] | 34     | 34         | 0      | 34      | 0      | 0      | 0      | 
 |dsrl__3     | memory_reg[31] | 13     | 13         | 0      | 13      | 0      | 0      | 0      | 
 +------------+----------------+--------+------------+--------+---------+--------+--------+--------+
 ---------------------------------------------------------------------------------
 Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Writing Synthesis Report
 ---------------------------------------------------------------------------------
 Report BlackBoxes: 
 +-+--------------+----------+
 | |BlackBox name |Instances |
 +-+--------------+----------+
 +-+--------------+----------+
 Report Cell Usage: 
 +------+---------+------+
 |      |Cell     |Count |
 +------+---------+------+
 |1     |BIBUF    |   130|
 |2     |BUFG     |     1|
 |3     |CARRY4   |     6|
 |4     |DNA_PORT |     1|
 |5     |LUT1     |    69|
 |6     |LUT2     |    24|
 |7     |LUT3     |   169|
 |8     |LUT4     |    52|
 |9     |LUT5     |    71|
 |10    |LUT6     |   118|
 |11    |PS7      |     1|
 |12    |SRL16    |     1|
 |13    |SRL16E   |    16|
 |14    |SRLC32E  |    45|
 |15    |FDCE     |    66|
 |16    |FDR      |     4|
 |17    |FDRE     |   501|
 |18    |FDSE     |    20|
 |19    |LD       |    57|
 |20    |IOBUF    |    33|
 +------+---------+------+
 ---------------------------------------------------------------------------------
 Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
 ---------------------------------------------------------------------------------
 Synthesis finished with 0 errors, 0 critical warnings and 136 warnings.
 Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 618.598 ; free physical = 1531 ; free virtual = 70510
 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1531 ; free virtual = 70509
 INFO: [Project 1-571] Translating synthesized netlist
 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2518.902 ; gain = 0.000 ; free physical = 1748 ; free virtual = 70732
 INFO: [Netlist 29-17] Analyzing 101 Unisim elements for replacement
 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
 INFO: [Project 1-570] Preparing netlist for logic optimization
 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2563.766 ; gain = 0.000 ; free physical = 1757 ; free virtual = 70743
 INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 95 instances were transformed.
  FDR => FDRE: 4 instances
  IOBUF => IOBUF (IBUF, OBUFT): 33 instances
  LD => LDCE: 57 instances
  SRL16 => SRL16E: 1 instance 
 Synth Design complete | Checksum: 8993d7c
 INFO: [Common 17-83] Releasing license: Synthesis
 187 Infos, 142 Warnings, 0 Critical Warnings and 0 Errors encountered.
 synth_design completed successfully
 synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 2563.801 ; gain = 1259.379 ; free physical = 1759 ; free virtual = 70746
 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1991.605; main = 1727.861; forked = 379.983
 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3465.613; main = 2563.770; forked = 1042.766
 Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2611.777 ; gain = 0.000 ; free physical = 1758 ; free virtual = 70746
 INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/system_wrapper.dcp' has been generated.
 INFO: [runtcl-4] Executing : report_utilization -file system_wrapper_utilization_synth.rpt -pb system_wrapper_utilization_synth.pb
 INFO: [Common 17-206] Exiting Vivado at Wed May 27 16:36:31 2026...
@@ -1,4 +0,0 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <section name="Workbench">
 	<item value="system_wrapper_hw_platform_0" key="applicationwizard.hw_platform_key"/>
 </section>
@@ -1,12 +0,0 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <section name="Workbench">
 	<item value="system_wrapper_hw_platform_0" key="programflash.hwplatform"/>
 	<item value="Local" key="system_wrapper_hw_platform_0-target"/>
 	<item value="G:\CALBOARD\z035_mars1k\debug_bin\bin_8.1\BOOT.bin" key="system_wrapper_hw_platform_0-imgFile"/>
 	<item value="G:\CALBOARD\z035_mars1k\debug_bin\bin_8.1\FSBL.elf" key="system_wrapper_hw_platform_0-fsblFile"/>
 	<item value="false" key="system_wrapper_hw_platform_0-verifyFlash"/>
 	<item value="false" key="system_wrapper_hw_platform_0-blankCheck"/>
 	<item value="" key="system_wrapper_hw_platform_0-offSet"/>
 	<item value="qspi-x4-single" key="system_wrapper_hw_platform_0-flashType"/>
 	<item value="Auto Detect" key="system_wrapper_hw_platform_0-device"/>
 </section>
@@ -1,6 +0,0 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <section name="Workbench">
 	<item value="E:\CALBOARD\z035_mars1k_a1_sc1\bin\bin_1.14.2" key="bootgen_files_selection"/>
 	<item value="G:\CALBOARD\z035_mars1k\debug_bin\bin_8.1" key="zynq_flash_files_selection"/>
 	<item value="E:\CALBOARD\z035_mars1k_a1_sc1\bin\bin_1.14.2" key="last_stored_selection"/>
 </section>
@@ -1,42 +0,0 @@
 *** SESSION 7月 20, 2023 10:59:21.88 --------------------------------------------
 *** SESSION 7月 21, 2023 09:54:56.41 --------------------------------------------
 *** SESSION 7月 24, 2023 10:09:44.70 --------------------------------------------
 *** SESSION 7月 24, 2023 11:27:55.22 --------------------------------------------
 *** SESSION 7月 31, 2023 11:22:21.62 --------------------------------------------
 *** SESSION 7月 31, 2023 13:59:53.10 --------------------------------------------
 *** SESSION 7月 31, 2023 14:30:21.17 --------------------------------------------
 *** SESSION 7月 31, 2023 17:14:19.33 --------------------------------------------
 *** SESSION 8月 01, 2023 10:16:04.23 --------------------------------------------
 *** SESSION 8月 01, 2023 10:23:48.19 --------------------------------------------
 *** SESSION 8月 01, 2023 10:39:16.67 --------------------------------------------
 *** SESSION 8月 01, 2023 15:03:13.23 --------------------------------------------
 *** SESSION 8月 01, 2023 15:21:29.39 --------------------------------------------
 *** SESSION 8月 01, 2023 15:30:09.04 --------------------------------------------
 *** SESSION 8月 01, 2023 17:30:44.26 --------------------------------------------
 *** SESSION 8月 02, 2023 14:01:49.61 --------------------------------------------
 *** SESSION 8月 02, 2023 17:43:36.54 --------------------------------------------
 *** SESSION 8月 03, 2023 09:50:30.02 --------------------------------------------
 *** SESSION 8月 03, 2023 10:00:25.50 --------------------------------------------
 *** SESSION 8月 11, 2023 16:02:32.49 --------------------------------------------
 *** SESSION 10月 18, 2023 15:58:26.50 -------------------------------------------
 *** SESSION 10月 18, 2023 16:46:46.04 -------------------------------------------
 *** SESSION 12月 06, 2023 15:24:59.20 -------------------------------------------
 *** SESSION 12月 07, 2023 11:03:56.42 -------------------------------------------
 *** SESSION 3月 21, 2024 10:55:38.18 --------------------------------------------
 *** SESSION 4月 17, 2024 18:05:13.72 --------------------------------------------
 *** SESSION 11月 22, 2024 13:43:07.68 -------------------------------------------
 *** SESSION 11月 22, 2024 14:56:54.59 -------------------------------------------
 *** SESSION 12月 26, 2024 15:50:42.16 -------------------------------------------
 *** SESSION 11月 13, 2025 12:44:24.10 -------------------------------------------
 *** SESSION 11月 13, 2025 12:56:34.12 -------------------------------------------
 *** SESSION 11月 13, 2025 13:57:56.63 -------------------------------------------
 *** SESSION 1月 12, 2026 17:48:47.43 --------------------------------------------
 *** SESSION 1月 12, 2026 18:09:32.44 --------------------------------------------
 *** SESSION 1月 13, 2026 09:55:02.84 --------------------------------------------
 *** SESSION 1月 14, 2026 14:00:24.31 --------------------------------------------
 *** SESSION 1月 14, 2026 14:37:51.43 --------------------------------------------
 *** SESSION 1月 14, 2026 15:02:21.84 --------------------------------------------
 *** SESSION 1月 14, 2026 16:03:07.13 --------------------------------------------
 *** SESSION 1月 14, 2026 17:47:06.30 --------------------------------------------
 *** SESSION 1月 15, 2026 15:03:55.78 --------------------------------------------
 *** SESSION 1月 19, 2026 10:54:39.60 --------------------------------------------
@@ -1 +0,0 @@
@@ -1 +0,0 @@
@@ -1,76 +0,0 @@
 15:10:04 **** Build of configuration Debug for project FSBL ****
 make pre-build main-build 
 a9-linaro-pre-build-step
 ' '
 'Building file: ../src/fsbl_hooks.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/fsbl_hooks.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/fsbl_hooks.d" -MT"src/fsbl_hooks.o" -o "src/fsbl_hooks.o" "../src/fsbl_hooks.c"
 'Finished building: ../src/fsbl_hooks.c'
 ' '
 'Building file: ../src/image_mover.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/image_mover.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/image_mover.d" -MT"src/image_mover.o" -o "src/image_mover.o" "../src/image_mover.c"
 'Finished building: ../src/image_mover.c'
 ' '
 'Building file: ../src/main.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/main.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/main.d" -MT"src/main.o" -o "src/main.o" "../src/main.c"
 In file included from ../src/main.c:137:0:
 ../../FSBL_bsp/ps7_cortexa9_0/include/xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
 #pragma message ("For the sleep routines, Global timer is being used")
         ^~~~~~~
 'Finished building: ../src/main.c'
 ' '
 'Building file: ../src/md5.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/md5.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/md5.d" -MT"src/md5.o" -o "src/md5.o" "../src/md5.c"
 'Finished building: ../src/md5.c'
 ' '
 'Building file: ../src/nand.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/nand.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/nand.d" -MT"src/nand.o" -o "src/nand.o" "../src/nand.c"
 'Finished building: ../src/nand.c'
 ' '
 'Building file: ../src/nor.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/nor.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/nor.d" -MT"src/nor.o" -o "src/nor.o" "../src/nor.c"
 'Finished building: ../src/nor.c'
 ' '
 'Building file: ../src/pcap.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/pcap.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/pcap.d" -MT"src/pcap.o" -o "src/pcap.o" "../src/pcap.c"
 In file included from ../src/pcap.c:100:0:
 ../../FSBL_bsp/ps7_cortexa9_0/include/xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
 #pragma message ("For the sleep routines, Global timer is being used")
         ^~~~~~~
 'Finished building: ../src/pcap.c'
 ' '
 'Building file: E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/ps7_init.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/ps7_init.d" -MT"src/ps7_init.o" -o "src/ps7_init.o" "E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.c"
 'Finished building: E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.c'
 ' '
 'Building file: ../src/qspi.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/qspi.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/qspi.d" -MT"src/qspi.o" -o "src/qspi.o" "../src/qspi.c"
 'Finished building: ../src/qspi.c'
 ' '
 'Building file: ../src/sd.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/sd.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/sd.d" -MT"src/sd.o" -o "src/sd.o" "../src/sd.c"
 'Finished building: ../src/sd.c'
 ' '
 'Building target: FSBL.elf'
 'Invoking: ARM v7 gcc linker'
 arm-none-eabi-gcc -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec -Wl,-T -Wl,../src/lscript.ld -L../../FSBL_bsp/ps7_cortexa9_0/lib -o "FSBL.elf"  ./src/fsbl_handoff.o ./src/fsbl_hooks.o ./src/image_mover.o ./src/main.o ./src/md5.o ./src/nand.o ./src/nor.o ./src/pcap.o ./src/ps7_init.o ./src/qspi.o ./src/rsa.o ./src/sd.o   -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilffs,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lrsa,-lxil,-lgcc,-lc,--end-group
 'Finished building target: FSBL.elf'
 ' '
 'Invoking: ARM v7 Print Size'
 arm-none-eabi-size FSBL.elf  |tee "FSBL.elf.size"
   text	   data	    bss	    dec	    hex	filename
  81496	  10160	  74712	 166368	  289e0	FSBL.elf
 'Finished building: FSBL.elf.size'
 ' '
 15:10:09 Build Finished (took 4s.365ms)
@@ -1,106 +0,0 @@
 15:09:36 **** Build of project FSBL_bsp ****
 make -k all 
 "Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src"
 make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src"
 make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_0/src"
 make -C ps7_cortexa9_0/libsrc/ddrps_v1_0/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_5/src"
 make -C ps7_cortexa9_0/libsrc/devcfg_v3_5/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_4/src"
 make -C ps7_cortexa9_0/libsrc/dmaps_v2_4/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_8/src"
 make -C ps7_cortexa9_0/libsrc/emacps_v3_8/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_4/src"
 make -C ps7_cortexa9_0/libsrc/gpiops_v3_4/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_5/src"
 make -C ps7_cortexa9_0/libsrc/qspips_v3_5/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/scugic_v3_10/src"
 make -C ps7_cortexa9_0/libsrc/scugic_v3_10/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_1/src"
 make -C ps7_cortexa9_0/libsrc/scutimer_v2_1/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_1/src"
 make -C ps7_cortexa9_0/libsrc/scuwdt_v2_1/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/sdps_v3_6/src"
 make -C ps7_cortexa9_0/libsrc/sdps_v3_6/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/standalone_v6_8/src"
 make -C ps7_cortexa9_0/libsrc/standalone_v6_8/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_7/src"
 make -C ps7_cortexa9_0/libsrc/uartps_v3_7/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_3/src"
 make -C ps7_cortexa9_0/libsrc/xadcps_v2_3/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/xilffs_v4_0/src"
 make -C ps7_cortexa9_0/libsrc/xilffs_v4_0/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/xilrsa_v1_5/src"
 make -C ps7_cortexa9_0/libsrc/xilrsa_v1_5/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make libs in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src"
 make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling coresightps_dcc"
 "Running Make libs in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src"
 make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling cpu_cortexa9"
 "Running Make libs in ps7_cortexa9_0/libsrc/ddrps_v1_0/src"
 make -C ps7_cortexa9_0/libsrc/ddrps_v1_0/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling ddrps"
 "Running Make libs in ps7_cortexa9_0/libsrc/devcfg_v3_5/src"
 make -C ps7_cortexa9_0/libsrc/devcfg_v3_5/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling devcfg"
 "Running Make libs in ps7_cortexa9_0/libsrc/dmaps_v2_4/src"
 make -C ps7_cortexa9_0/libsrc/dmaps_v2_4/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling dmaps"
 "Running Make libs in ps7_cortexa9_0/libsrc/emacps_v3_8/src"
 make -C ps7_cortexa9_0/libsrc/emacps_v3_8/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling emacps"
 "Running Make libs in ps7_cortexa9_0/libsrc/gpiops_v3_4/src"
 make -C ps7_cortexa9_0/libsrc/gpiops_v3_4/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling gpiops"
 "Running Make libs in ps7_cortexa9_0/libsrc/qspips_v3_5/src"
 make -C ps7_cortexa9_0/libsrc/qspips_v3_5/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling qspips"
 "Running Make libs in ps7_cortexa9_0/libsrc/scugic_v3_10/src"
 make -C ps7_cortexa9_0/libsrc/scugic_v3_10/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling scugic"
 "Running Make libs in ps7_cortexa9_0/libsrc/scutimer_v2_1/src"
 make -C ps7_cortexa9_0/libsrc/scutimer_v2_1/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling scutimer"
 "Running Make libs in ps7_cortexa9_0/libsrc/scuwdt_v2_1/src"
 make -C ps7_cortexa9_0/libsrc/scuwdt_v2_1/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling scuwdt"
 "Running Make libs in ps7_cortexa9_0/libsrc/sdps_v3_6/src"
 make -C ps7_cortexa9_0/libsrc/sdps_v3_6/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling sdps"
 "Running Make libs in ps7_cortexa9_0/libsrc/standalone_v6_8/src"
 make -C ps7_cortexa9_0/libsrc/standalone_v6_8/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling standalone"
 In file included from usleep.c:56:0:
 xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
 #pragma message ("For the sleep routines, Global timer is being used")
         ^~~~~~~
 In file included from sleep.c:53:0:
 xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
 #pragma message ("For the sleep routines, Global timer is being used")
         ^~~~~~~
 In file included from xil_sleeptimer.c:51:0:
 xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
 #pragma message ("For the sleep routines, Global timer is being used")
         ^~~~~~~
 In file included from xtime_l.c:49:0:
 xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
 #pragma message ("For the sleep routines, Global timer is being used")
         ^~~~~~~
 "Running Make libs in ps7_cortexa9_0/libsrc/uartps_v3_7/src"
 make -C ps7_cortexa9_0/libsrc/uartps_v3_7/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling uartps"
 "Running Make libs in ps7_cortexa9_0/libsrc/xadcps_v2_3/src"
 make -C ps7_cortexa9_0/libsrc/xadcps_v2_3/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling xadcps"
 "Running Make libs in ps7_cortexa9_0/libsrc/xilffs_v4_0/src"
 make -C ps7_cortexa9_0/libsrc/xilffs_v4_0/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling XilFFs Library"
 "Running Make libs in ps7_cortexa9_0/libsrc/xilrsa_v1_5/src"
 make -C ps7_cortexa9_0/libsrc/xilrsa_v1_5/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 'Finished building libraries'
 15:10:04 Build Finished (took 27s.930ms)
@@ -1,36 +0,0 @@
 10:56:55 **** Auto Build of configuration Debug for project calboard ****
 make pre-build main-build 
 a9-linaro-pre-build-step
 ' '
 'Building file: ../src/cal_meas.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/cal_meas.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/cal_meas.d" -MT"src/cal_meas.o" -o "src/cal_meas.o" "../src/cal_meas.c"
 ../src/cal_meas.c: In function 'sw_config':
 ../src/cal_meas.c:20:10: warning: unused variable 'memt_areal' [-Wunused-variable]
    char  memt_areal = *(slot_start+6);
          ^~~~~~~~~~
 ../src/cal_meas.c:19:10: warning: unused variable 'load' [-Wunused-variable]
    char  load       = *(slot_start+5);
          ^~~~
 ../src/cal_meas.c:18:10: warning: unused variable 'volt_cur' [-Wunused-variable]
    char  volt_cur   = *(slot_start+4);
          ^~~~~~~~
 ../src/cal_meas.c:15:10: warning: unused variable 'm_fun' [-Wunused-variable]
    char  m_fun      = *(slot_start+1);
          ^~~~~
 'Finished building: ../src/cal_meas.c'
 ' '
 'Building target: calboard.elf'
 'Invoking: ARM v7 gcc linker'
 arm-none-eabi-gcc -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec -Wl,-T -Wl,../src/lscript.ld -L../../calboard_bsp/ps7_cortexa9_0/lib -o "calboard.elf"  ./src/GPIO_Driv.o ./src/SPI_Driv.o ./src/cal_meas.o ./src/crc16.o ./src/dna_read.o ./src/echo.o ./src/i2c_access.o ./src/iic_phyreset.o ./src/main.o ./src/platform.o ./src/platform_mb.o ./src/platform_ppc.o ./src/platform_zynq.o ./src/platform_zynqmp.o ./src/sfp.o ./src/si5324.o   -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxil,-llwip4,-lgcc,-lc,--end-group
 'Finished building target: calboard.elf'
 ' '
 'Invoking: ARM v7 Print Size'
 arm-none-eabi-size calboard.elf  |tee "calboard.elf.size"
   text	   data	    bss	    dec	    hex	filename
 132680	   3184	5363760	5499624	 53eae8	calboard.elf
 'Finished building: calboard.elf.size'
 ' '
 10:56:56 Build Finished (took 1s.11ms)
@@ -1,102 +0,0 @@
 15:10:09 **** Build of project calboard_bsp ****
 make -k all 
 "Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src"
 make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src"
 make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_0/src"
 make -C ps7_cortexa9_0/libsrc/ddrps_v1_0/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_5/src"
 make -C ps7_cortexa9_0/libsrc/devcfg_v3_5/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_4/src"
 make -C ps7_cortexa9_0/libsrc/dmaps_v2_4/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_8/src"
 make -C ps7_cortexa9_0/libsrc/emacps_v3_8/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_4/src"
 make -C ps7_cortexa9_0/libsrc/gpiops_v3_4/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/lwip211_v1_7/src"
 make -C ps7_cortexa9_0/libsrc/lwip211_v1_7/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_5/src"
 make -C ps7_cortexa9_0/libsrc/qspips_v3_5/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/scugic_v3_10/src"
 make -C ps7_cortexa9_0/libsrc/scugic_v3_10/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_1/src"
 make -C ps7_cortexa9_0/libsrc/scutimer_v2_1/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_1/src"
 make -C ps7_cortexa9_0/libsrc/scuwdt_v2_1/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/sdps_v3_6/src"
 make -C ps7_cortexa9_0/libsrc/sdps_v3_6/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/standalone_v6_8/src"
 make -C ps7_cortexa9_0/libsrc/standalone_v6_8/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_7/src"
 make -C ps7_cortexa9_0/libsrc/uartps_v3_7/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_3/src"
 make -C ps7_cortexa9_0/libsrc/xadcps_v2_3/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make libs in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src"
 make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling coresightps_dcc"
 "Running Make libs in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src"
 make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling cpu_cortexa9"
 "Running Make libs in ps7_cortexa9_0/libsrc/ddrps_v1_0/src"
 make -C ps7_cortexa9_0/libsrc/ddrps_v1_0/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling ddrps"
 "Running Make libs in ps7_cortexa9_0/libsrc/devcfg_v3_5/src"
 make -C ps7_cortexa9_0/libsrc/devcfg_v3_5/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling devcfg"
 "Running Make libs in ps7_cortexa9_0/libsrc/dmaps_v2_4/src"
 make -C ps7_cortexa9_0/libsrc/dmaps_v2_4/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling dmaps"
 "Running Make libs in ps7_cortexa9_0/libsrc/emacps_v3_8/src"
 make -C ps7_cortexa9_0/libsrc/emacps_v3_8/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling emacps"
 "Running Make libs in ps7_cortexa9_0/libsrc/gpiops_v3_4/src"
 make -C ps7_cortexa9_0/libsrc/gpiops_v3_4/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling gpiops"
 "Running Make libs in ps7_cortexa9_0/libsrc/lwip211_v1_7/src"
 make -C ps7_cortexa9_0/libsrc/lwip211_v1_7/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling lwip src and adapter files"
 "Running Make libs in ps7_cortexa9_0/libsrc/qspips_v3_5/src"
 make -C ps7_cortexa9_0/libsrc/qspips_v3_5/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling qspips"
 "Running Make libs in ps7_cortexa9_0/libsrc/scugic_v3_10/src"
 make -C ps7_cortexa9_0/libsrc/scugic_v3_10/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling scugic"
 "Running Make libs in ps7_cortexa9_0/libsrc/scutimer_v2_1/src"
 make -C ps7_cortexa9_0/libsrc/scutimer_v2_1/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling scutimer"
 "Running Make libs in ps7_cortexa9_0/libsrc/scuwdt_v2_1/src"
 make -C ps7_cortexa9_0/libsrc/scuwdt_v2_1/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling scuwdt"
 "Running Make libs in ps7_cortexa9_0/libsrc/sdps_v3_6/src"
 make -C ps7_cortexa9_0/libsrc/sdps_v3_6/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling sdps"
 "Running Make libs in ps7_cortexa9_0/libsrc/standalone_v6_8/src"
 make -C ps7_cortexa9_0/libsrc/standalone_v6_8/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling standalone"
 In file included from usleep.c:56:0:
 xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
 #pragma message ("For the sleep routines, Global timer is being used")
         ^~~~~~~
 In file included from sleep.c:53:0:
 xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
 #pragma message ("For the sleep routines, Global timer is being used")
         ^~~~~~~
 In file included from xil_sleeptimer.c:51:0:
 xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
 #pragma message ("For the sleep routines, Global timer is being used")
         ^~~~~~~
 In file included from xtime_l.c:49:0:
 xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
 #pragma message ("For the sleep routines, Global timer is being used")
         ^~~~~~~
 "Running Make libs in ps7_cortexa9_0/libsrc/uartps_v3_7/src"
 make -C ps7_cortexa9_0/libsrc/uartps_v3_7/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling uartps"
 "Running Make libs in ps7_cortexa9_0/libsrc/xadcps_v2_3/src"
 make -C ps7_cortexa9_0/libsrc/xadcps_v2_3/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling xadcps"
 'Finished building libraries'
 15:10:35 Build Finished (took 26s.875ms)
@@ -1,7 +0,0 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <section name="Workbench">
 	<section name="org.eclipse.cdt.ui.text.hover.CMacroExpansionExploration">
 	</section>
 	<section name="completion_proposal_size">
 	</section>
 </section>
@@ -1,459 +0,0 @@
 16:43:51 **** Incremental Build of configuration Debug for project calboard ****
 make pre-build main-build 
 a9-linaro-pre-build-step
 ' '
 make: Nothing to be done for 'main-build'.
 15:09:36 **** Build of project FSBL_bsp ****
 make -k all 
 "Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src"
 make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src"
 make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_0/src"
 make -C ps7_cortexa9_0/libsrc/ddrps_v1_0/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_5/src"
 make -C ps7_cortexa9_0/libsrc/devcfg_v3_5/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_4/src"
 make -C ps7_cortexa9_0/libsrc/dmaps_v2_4/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_8/src"
 make -C ps7_cortexa9_0/libsrc/emacps_v3_8/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_4/src"
 make -C ps7_cortexa9_0/libsrc/gpiops_v3_4/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_5/src"
 make -C ps7_cortexa9_0/libsrc/qspips_v3_5/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/scugic_v3_10/src"
 make -C ps7_cortexa9_0/libsrc/scugic_v3_10/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_1/src"
 make -C ps7_cortexa9_0/libsrc/scutimer_v2_1/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_1/src"
 make -C ps7_cortexa9_0/libsrc/scuwdt_v2_1/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/sdps_v3_6/src"
 make -C ps7_cortexa9_0/libsrc/sdps_v3_6/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/standalone_v6_8/src"
 make -C ps7_cortexa9_0/libsrc/standalone_v6_8/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_7/src"
 make -C ps7_cortexa9_0/libsrc/uartps_v3_7/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_3/src"
 make -C ps7_cortexa9_0/libsrc/xadcps_v2_3/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/xilffs_v4_0/src"
 make -C ps7_cortexa9_0/libsrc/xilffs_v4_0/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/xilrsa_v1_5/src"
 make -C ps7_cortexa9_0/libsrc/xilrsa_v1_5/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make libs in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src"
 make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling coresightps_dcc"
 "Running Make libs in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src"
 make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling cpu_cortexa9"
 "Running Make libs in ps7_cortexa9_0/libsrc/ddrps_v1_0/src"
 make -C ps7_cortexa9_0/libsrc/ddrps_v1_0/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling ddrps"
 "Running Make libs in ps7_cortexa9_0/libsrc/devcfg_v3_5/src"
 make -C ps7_cortexa9_0/libsrc/devcfg_v3_5/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling devcfg"
 "Running Make libs in ps7_cortexa9_0/libsrc/dmaps_v2_4/src"
 make -C ps7_cortexa9_0/libsrc/dmaps_v2_4/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling dmaps"
 "Running Make libs in ps7_cortexa9_0/libsrc/emacps_v3_8/src"
 make -C ps7_cortexa9_0/libsrc/emacps_v3_8/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling emacps"
 "Running Make libs in ps7_cortexa9_0/libsrc/gpiops_v3_4/src"
 make -C ps7_cortexa9_0/libsrc/gpiops_v3_4/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling gpiops"
 "Running Make libs in ps7_cortexa9_0/libsrc/qspips_v3_5/src"
 make -C ps7_cortexa9_0/libsrc/qspips_v3_5/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling qspips"
 "Running Make libs in ps7_cortexa9_0/libsrc/scugic_v3_10/src"
 make -C ps7_cortexa9_0/libsrc/scugic_v3_10/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling scugic"
 "Running Make libs in ps7_cortexa9_0/libsrc/scutimer_v2_1/src"
 make -C ps7_cortexa9_0/libsrc/scutimer_v2_1/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling scutimer"
 "Running Make libs in ps7_cortexa9_0/libsrc/scuwdt_v2_1/src"
 make -C ps7_cortexa9_0/libsrc/scuwdt_v2_1/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling scuwdt"
 "Running Make libs in ps7_cortexa9_0/libsrc/sdps_v3_6/src"
 make -C ps7_cortexa9_0/libsrc/sdps_v3_6/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling sdps"
 "Running Make libs in ps7_cortexa9_0/libsrc/standalone_v6_8/src"
 make -C ps7_cortexa9_0/libsrc/standalone_v6_8/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling standalone"
 In file included from usleep.c:56:0:
 xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
 #pragma message ("For the sleep routines, Global timer is being used")
         ^~~~~~~
 In file included from sleep.c:53:0:
 xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
 #pragma message ("For the sleep routines, Global timer is being used")
         ^~~~~~~
 In file included from xil_sleeptimer.c:51:0:
 xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
 #pragma message ("For the sleep routines, Global timer is being used")
         ^~~~~~~
 In file included from xtime_l.c:49:0:
 xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
 #pragma message ("For the sleep routines, Global timer is being used")
         ^~~~~~~
 "Running Make libs in ps7_cortexa9_0/libsrc/uartps_v3_7/src"
 make -C ps7_cortexa9_0/libsrc/uartps_v3_7/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling uartps"
 "Running Make libs in ps7_cortexa9_0/libsrc/xadcps_v2_3/src"
 make -C ps7_cortexa9_0/libsrc/xadcps_v2_3/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling xadcps"
 "Running Make libs in ps7_cortexa9_0/libsrc/xilffs_v4_0/src"
 make -C ps7_cortexa9_0/libsrc/xilffs_v4_0/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling XilFFs Library"
 "Running Make libs in ps7_cortexa9_0/libsrc/xilrsa_v1_5/src"
 make -C ps7_cortexa9_0/libsrc/xilrsa_v1_5/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 'Finished building libraries'
 15:10:04 **** Build of configuration Debug for project FSBL ****
 make pre-build main-build 
 a9-linaro-pre-build-step
 ' '
 'Building file: ../src/fsbl_hooks.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/fsbl_hooks.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/fsbl_hooks.d" -MT"src/fsbl_hooks.o" -o "src/fsbl_hooks.o" "../src/fsbl_hooks.c"
 'Finished building: ../src/fsbl_hooks.c'
 ' '
 'Building file: ../src/image_mover.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/image_mover.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/image_mover.d" -MT"src/image_mover.o" -o "src/image_mover.o" "../src/image_mover.c"
 'Finished building: ../src/image_mover.c'
 ' '
 'Building file: ../src/main.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/main.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/main.d" -MT"src/main.o" -o "src/main.o" "../src/main.c"
 In file included from ../src/main.c:137:0:
 ../../FSBL_bsp/ps7_cortexa9_0/include/xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
 #pragma message ("For the sleep routines, Global timer is being used")
         ^~~~~~~
 'Finished building: ../src/main.c'
 ' '
 'Building file: ../src/md5.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/md5.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/md5.d" -MT"src/md5.o" -o "src/md5.o" "../src/md5.c"
 'Finished building: ../src/md5.c'
 ' '
 'Building file: ../src/nand.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/nand.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/nand.d" -MT"src/nand.o" -o "src/nand.o" "../src/nand.c"
 'Finished building: ../src/nand.c'
 ' '
 'Building file: ../src/nor.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/nor.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/nor.d" -MT"src/nor.o" -o "src/nor.o" "../src/nor.c"
 'Finished building: ../src/nor.c'
 ' '
 'Building file: ../src/pcap.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/pcap.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/pcap.d" -MT"src/pcap.o" -o "src/pcap.o" "../src/pcap.c"
 In file included from ../src/pcap.c:100:0:
 ../../FSBL_bsp/ps7_cortexa9_0/include/xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
 #pragma message ("For the sleep routines, Global timer is being used")
         ^~~~~~~
 'Finished building: ../src/pcap.c'
 ' '
 'Building file: E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/ps7_init.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/ps7_init.d" -MT"src/ps7_init.o" -o "src/ps7_init.o" "E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.c"
 'Finished building: E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.c'
 ' '
 'Building file: ../src/qspi.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/qspi.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/qspi.d" -MT"src/qspi.o" -o "src/qspi.o" "../src/qspi.c"
 'Finished building: ../src/qspi.c'
 ' '
 'Building file: ../src/sd.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/sd.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/sd.d" -MT"src/sd.o" -o "src/sd.o" "../src/sd.c"
 'Finished building: ../src/sd.c'
 ' '
 'Building target: FSBL.elf'
 'Invoking: ARM v7 gcc linker'
 arm-none-eabi-gcc -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec -Wl,-T -Wl,../src/lscript.ld -L../../FSBL_bsp/ps7_cortexa9_0/lib -o "FSBL.elf"  ./src/fsbl_handoff.o ./src/fsbl_hooks.o ./src/image_mover.o ./src/main.o ./src/md5.o ./src/nand.o ./src/nor.o ./src/pcap.o ./src/ps7_init.o ./src/qspi.o ./src/rsa.o ./src/sd.o   -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilffs,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lrsa,-lxil,-lgcc,-lc,--end-group
 'Finished building target: FSBL.elf'
 ' '
 'Invoking: ARM v7 Print Size'
 arm-none-eabi-size FSBL.elf  |tee "FSBL.elf.size"
   text	   data	    bss	    dec	    hex	filename
  81496	  10160	  74712	 166368	  289e0	FSBL.elf
 'Finished building: FSBL.elf.size'
 ' '
 15:10:09 **** Build of project calboard_bsp ****
 make -k all 
 "Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src"
 make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src"
 make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_0/src"
 make -C ps7_cortexa9_0/libsrc/ddrps_v1_0/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_5/src"
 make -C ps7_cortexa9_0/libsrc/devcfg_v3_5/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_4/src"
 make -C ps7_cortexa9_0/libsrc/dmaps_v2_4/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_8/src"
 make -C ps7_cortexa9_0/libsrc/emacps_v3_8/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_4/src"
 make -C ps7_cortexa9_0/libsrc/gpiops_v3_4/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/lwip211_v1_7/src"
 make -C ps7_cortexa9_0/libsrc/lwip211_v1_7/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_5/src"
 make -C ps7_cortexa9_0/libsrc/qspips_v3_5/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/scugic_v3_10/src"
 make -C ps7_cortexa9_0/libsrc/scugic_v3_10/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_1/src"
 make -C ps7_cortexa9_0/libsrc/scutimer_v2_1/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_1/src"
 make -C ps7_cortexa9_0/libsrc/scuwdt_v2_1/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/sdps_v3_6/src"
 make -C ps7_cortexa9_0/libsrc/sdps_v3_6/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/standalone_v6_8/src"
 make -C ps7_cortexa9_0/libsrc/standalone_v6_8/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_7/src"
 make -C ps7_cortexa9_0/libsrc/uartps_v3_7/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_3/src"
 make -C ps7_cortexa9_0/libsrc/xadcps_v2_3/src -s include  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Running Make libs in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src"
 make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling coresightps_dcc"
 "Running Make libs in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src"
 make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling cpu_cortexa9"
 "Running Make libs in ps7_cortexa9_0/libsrc/ddrps_v1_0/src"
 make -C ps7_cortexa9_0/libsrc/ddrps_v1_0/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling ddrps"
 "Running Make libs in ps7_cortexa9_0/libsrc/devcfg_v3_5/src"
 make -C ps7_cortexa9_0/libsrc/devcfg_v3_5/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling devcfg"
 "Running Make libs in ps7_cortexa9_0/libsrc/dmaps_v2_4/src"
 make -C ps7_cortexa9_0/libsrc/dmaps_v2_4/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling dmaps"
 "Running Make libs in ps7_cortexa9_0/libsrc/emacps_v3_8/src"
 make -C ps7_cortexa9_0/libsrc/emacps_v3_8/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling emacps"
 "Running Make libs in ps7_cortexa9_0/libsrc/gpiops_v3_4/src"
 make -C ps7_cortexa9_0/libsrc/gpiops_v3_4/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling gpiops"
 "Running Make libs in ps7_cortexa9_0/libsrc/lwip211_v1_7/src"
 make -C ps7_cortexa9_0/libsrc/lwip211_v1_7/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling lwip src and adapter files"
 "Running Make libs in ps7_cortexa9_0/libsrc/qspips_v3_5/src"
 make -C ps7_cortexa9_0/libsrc/qspips_v3_5/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling qspips"
 "Running Make libs in ps7_cortexa9_0/libsrc/scugic_v3_10/src"
 make -C ps7_cortexa9_0/libsrc/scugic_v3_10/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling scugic"
 "Running Make libs in ps7_cortexa9_0/libsrc/scutimer_v2_1/src"
 make -C ps7_cortexa9_0/libsrc/scutimer_v2_1/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling scutimer"
 "Running Make libs in ps7_cortexa9_0/libsrc/scuwdt_v2_1/src"
 make -C ps7_cortexa9_0/libsrc/scuwdt_v2_1/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling scuwdt"
 "Running Make libs in ps7_cortexa9_0/libsrc/sdps_v3_6/src"
 make -C ps7_cortexa9_0/libsrc/sdps_v3_6/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling sdps"
 "Running Make libs in ps7_cortexa9_0/libsrc/standalone_v6_8/src"
 make -C ps7_cortexa9_0/libsrc/standalone_v6_8/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling standalone"
 In file included from usleep.c:56:0:
 xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
 #pragma message ("For the sleep routines, Global timer is being used")
         ^~~~~~~
 In file included from sleep.c:53:0:
 xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
 #pragma message ("For the sleep routines, Global timer is being used")
         ^~~~~~~
 In file included from xil_sleeptimer.c:51:0:
 xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
 #pragma message ("For the sleep routines, Global timer is being used")
         ^~~~~~~
 In file included from xtime_l.c:49:0:
 xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
 #pragma message ("For the sleep routines, Global timer is being used")
         ^~~~~~~
 "Running Make libs in ps7_cortexa9_0/libsrc/uartps_v3_7/src"
 make -C ps7_cortexa9_0/libsrc/uartps_v3_7/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling uartps"
 "Running Make libs in ps7_cortexa9_0/libsrc/xadcps_v2_3/src"
 make -C ps7_cortexa9_0/libsrc/xadcps_v2_3/src -s libs  "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
 "Compiling xadcps"
 'Finished building libraries'
 15:10:36 **** Build of configuration Debug for project calboard ****
 make pre-build main-build 
 a9-linaro-pre-build-step
 ' '
 'Building file: ../src/GPIO_Driv.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/GPIO_Driv.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/GPIO_Driv.d" -MT"src/GPIO_Driv.o" -o "src/GPIO_Driv.o" "../src/GPIO_Driv.c"
 In file included from ../../calboard_bsp/ps7_cortexa9_0/include/xgpiops.h:119:0,
                 from ../src/GPIO_Driv.h:12,
                 from ../src/GPIO_Driv.c:7:
 ../src/GPIO_Driv.c: In function 'EMIO_config':
 ../../calboard_bsp/ps7_cortexa9_0/include/xstatus.h:61:41: warning: 'return' with a value, in function returning void
 #define XST_FAILURE                     1L
                                         ^
 ../src/GPIO_Driv.c:21:11: note: in expansion of macro 'XST_FAILURE'
    return XST_FAILURE;
           ^~~~~~~~~~~
 ../src/GPIO_Driv.c:16:6: note: declared here
 void EMIO_config(void)
      ^~~~~~~~~~~
 'Finished building: ../src/GPIO_Driv.c'
 ' '
 'Building file: ../src/SPI_Driv.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/SPI_Driv.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/SPI_Driv.d" -MT"src/SPI_Driv.o" -o "src/SPI_Driv.o" "../src/SPI_Driv.c"
 'Finished building: ../src/SPI_Driv.c'
 ' '
 'Building file: ../src/cal_meas.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/cal_meas.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/cal_meas.d" -MT"src/cal_meas.o" -o "src/cal_meas.o" "../src/cal_meas.c"
 ../src/cal_meas.c: In function 'sw_config':
 ../src/cal_meas.c:20:10: warning: unused variable 'memt_areal' [-Wunused-variable]
    char  memt_areal = *(slot_start+6);
          ^~~~~~~~~~
 ../src/cal_meas.c:19:10: warning: unused variable 'load' [-Wunused-variable]
    char  load       = *(slot_start+5);
          ^~~~
 ../src/cal_meas.c:18:10: warning: unused variable 'volt_cur' [-Wunused-variable]
    char  volt_cur   = *(slot_start+4);
          ^~~~~~~~
 ../src/cal_meas.c:15:10: warning: unused variable 'm_fun' [-Wunused-variable]
    char  m_fun      = *(slot_start+1);
          ^~~~~
 'Finished building: ../src/cal_meas.c'
 ' '
 'Building file: ../src/dna_read.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/dna_read.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/dna_read.d" -MT"src/dna_read.o" -o "src/dna_read.o" "../src/dna_read.c"
 ../src/dna_read.c: In function 'dna_port_read':
 ../src/dna_read.c:19:2: warning: implicit declaration of function 'usleep' [-Wimplicit-function-declaration]
  usleep(20);
  ^~~~~~
 'Finished building: ../src/dna_read.c'
 ' '
 'Building file: ../src/echo.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/echo.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/echo.d" -MT"src/echo.o" -o "src/echo.o" "../src/echo.c"
 ../src/echo.c: In function 'recv_callback':
 ../src/echo.c:92:35: warning: pointer targets in passing argument 1 of 'do_crc_table' differ in signedness [-Wpointer-sign]
       crc_read_dat = do_crc_table(recv_data+6, recv_len-8);
                                   ^~~~~~~~~
 In file included from ../src/echo.c:32:0:
 ../src/crc16.h:11:16: note: expected 'unsigned char *' but argument is of type 'char *'
 unsigned short do_crc_table(unsigned char* ptr, int len);
                ^~~~~~~~~~~~
 'Finished building: ../src/echo.c'
 ' '
 'Building file: ../src/i2c_access.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/i2c_access.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/i2c_access.d" -MT"src/i2c_access.o" -o "src/i2c_access.o" "../src/i2c_access.c"
 'Finished building: ../src/i2c_access.c'
 ' '
 'Building file: ../src/iic_phyreset.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/iic_phyreset.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/iic_phyreset.d" -MT"src/iic_phyreset.o" -o "src/iic_phyreset.o" "../src/iic_phyreset.c"
 'Finished building: ../src/iic_phyreset.c'
 ' '
 'Building file: ../src/main.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/main.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/main.d" -MT"src/main.o" -o "src/main.o" "../src/main.c"
 'Finished building: ../src/main.c'
 ' '
 'Building file: ../src/platform_zynq.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/platform_zynq.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/platform_zynq.d" -MT"src/platform_zynq.o" -o "src/platform_zynq.o" "../src/platform_zynq.c"
 'Finished building: ../src/platform_zynq.c'
 ' '
 'Building file: ../src/platform_zynqmp.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/platform_zynqmp.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/platform_zynqmp.d" -MT"src/platform_zynqmp.o" -o "src/platform_zynqmp.o" "../src/platform_zynqmp.c"
 'Finished building: ../src/platform_zynqmp.c'
 ' '
 'Building file: ../src/sfp.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/sfp.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/sfp.d" -MT"src/sfp.o" -o "src/sfp.o" "../src/sfp.c"
 'Finished building: ../src/sfp.c'
 ' '
 'Building file: ../src/si5324.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/si5324.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/si5324.d" -MT"src/si5324.o" -o "src/si5324.o" "../src/si5324.c"
 'Finished building: ../src/si5324.c'
 ' '
 'Building target: calboard.elf'
 'Invoking: ARM v7 gcc linker'
 arm-none-eabi-gcc -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec -Wl,-T -Wl,../src/lscript.ld -L../../calboard_bsp/ps7_cortexa9_0/lib -o "calboard.elf"  ./src/GPIO_Driv.o ./src/SPI_Driv.o ./src/cal_meas.o ./src/crc16.o ./src/dna_read.o ./src/echo.o ./src/i2c_access.o ./src/iic_phyreset.o ./src/main.o ./src/platform.o ./src/platform_mb.o ./src/platform_ppc.o ./src/platform_zynq.o ./src/platform_zynqmp.o ./src/sfp.o ./src/si5324.o   -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxil,-llwip4,-lgcc,-lc,--end-group
 'Finished building target: calboard.elf'
 ' '
 'Invoking: ARM v7 Print Size'
 arm-none-eabi-size calboard.elf  |tee "calboard.elf.size"
   text	   data	    bss	    dec	    hex	filename
 132488	   3184	5363760	5499432	 53ea28	calboard.elf
 'Finished building: calboard.elf.size'
 ' '
 10:56:14 **** Auto Build of configuration Debug for project calboard ****
 make pre-build main-build 
 a9-linaro-pre-build-step
 ' '
 'Building file: ../src/cal_meas.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/cal_meas.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/cal_meas.d" -MT"src/cal_meas.o" -o "src/cal_meas.o" "../src/cal_meas.c"
 ../src/cal_meas.c: In function 'sw_config':
 ../src/cal_meas.c:20:10: warning: unused variable 'memt_areal' [-Wunused-variable]
    char  memt_areal = *(slot_start+6);
          ^~~~~~~~~~
 ../src/cal_meas.c:19:10: warning: unused variable 'load' [-Wunused-variable]
    char  load       = *(slot_start+5);
          ^~~~
 ../src/cal_meas.c:18:10: warning: unused variable 'volt_cur' [-Wunused-variable]
    char  volt_cur   = *(slot_start+4);
          ^~~~~~~~
 ../src/cal_meas.c:15:10: warning: unused variable 'm_fun' [-Wunused-variable]
    char  m_fun      = *(slot_start+1);
          ^~~~~
 'Finished building: ../src/cal_meas.c'
 ' '
 'Building target: calboard.elf'
 'Invoking: ARM v7 gcc linker'
 arm-none-eabi-gcc -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec -Wl,-T -Wl,../src/lscript.ld -L../../calboard_bsp/ps7_cortexa9_0/lib -o "calboard.elf"  ./src/GPIO_Driv.o ./src/SPI_Driv.o ./src/cal_meas.o ./src/crc16.o ./src/dna_read.o ./src/echo.o ./src/i2c_access.o ./src/iic_phyreset.o ./src/main.o ./src/platform.o ./src/platform_mb.o ./src/platform_ppc.o ./src/platform_zynq.o ./src/platform_zynqmp.o ./src/sfp.o ./src/si5324.o   -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxil,-llwip4,-lgcc,-lc,--end-group
 'Finished building target: calboard.elf'
 ' '
 'Invoking: ARM v7 Print Size'
 arm-none-eabi-size calboard.elf  |tee "calboard.elf.size"
   text	   data	    bss	    dec	    hex	filename
 132552	   3184	5363760	5499496	 53ea68	calboard.elf
 'Finished building: calboard.elf.size'
 ' '
 10:56:55 **** Auto Build of configuration Debug for project calboard ****
 make pre-build main-build 
 a9-linaro-pre-build-step
 ' '
 'Building file: ../src/cal_meas.c'
 'Invoking: ARM v7 gcc compiler'
 arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/cal_meas.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/cal_meas.d" -MT"src/cal_meas.o" -o "src/cal_meas.o" "../src/cal_meas.c"
 ../src/cal_meas.c: In function 'sw_config':
 ../src/cal_meas.c:20:10: warning: unused variable 'memt_areal' [-Wunused-variable]
    char  memt_areal = *(slot_start+6);
          ^~~~~~~~~~
 ../src/cal_meas.c:19:10: warning: unused variable 'load' [-Wunused-variable]
    char  load       = *(slot_start+5);
          ^~~~
 ../src/cal_meas.c:18:10: warning: unused variable 'volt_cur' [-Wunused-variable]
    char  volt_cur   = *(slot_start+4);
          ^~~~~~~~
 ../src/cal_meas.c:15:10: warning: unused variable 'm_fun' [-Wunused-variable]
    char  m_fun      = *(slot_start+1);
          ^~~~~
 'Finished building: ../src/cal_meas.c'
 ' '
 'Building target: calboard.elf'
 'Invoking: ARM v7 gcc linker'
 arm-none-eabi-gcc -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec -Wl,-T -Wl,../src/lscript.ld -L../../calboard_bsp/ps7_cortexa9_0/lib -o "calboard.elf"  ./src/GPIO_Driv.o ./src/SPI_Driv.o ./src/cal_meas.o ./src/crc16.o ./src/dna_read.o ./src/echo.o ./src/i2c_access.o ./src/iic_phyreset.o ./src/main.o ./src/platform.o ./src/platform_mb.o ./src/platform_ppc.o ./src/platform_zynq.o ./src/platform_zynqmp.o ./src/sfp.o ./src/si5324.o   -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxil,-llwip4,-lgcc,-lc,--end-group
 'Finished building target: calboard.elf'
 ' '
 'Invoking: ARM v7 Print Size'
 arm-none-eabi-size calboard.elf  |tee "calboard.elf.size"
   text	   data	    bss	    dec	    hex	filename
 132680	   3184	5363760	5499624	 53eae8	calboard.elf
 'Finished building: calboard.elf.size'
 ' '
@@ -1,227 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start, u32 CPLD_UU[11])
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 u8      cpld_addr = 0;
 		 u32     cpld_dat  = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(slot==1)
 		 {
 			 cpld_addr = 0x82;
 		 }
 		 else if(slot==2)
 		 {
 			 cpld_addr = 0x83;
 		 }
 		 else if(slot==3)
 		 {
 			 cpld_addr = 0x84;
 		 }
 		 else
 		 {
 			 cpld_addr = 0x85;
 		 }
 		 switch(ch_num)
 		 {
 		   case 0x0001:
 		 	   {
 		 		   relay_ctrl = 0x00000000;
 		 		   break;
 		 	   }
 		   case 0x0002:
 		   	   {
 		   		   relay_ctrl = 0x00020000;
 		   		   break;
 		   	   }
 		   case 0x0003:
 		   	   {
 		   		   relay_ctrl = 0x00200000;
 		   		   break;
 		   	   }
 		   case 0x0004:
 		   	   {
 		   		   relay_ctrl = 0x00022000;
 		   		   break;
 		   	   }
 		   case 0x0005:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0006:
 		   	   {
 		   		   relay_ctrl = 0x00810000;
 		   		   break;
 		   	   }
 		   case 0x0007:
 		   	   {
 		   		   relay_ctrl = 0x00A00000;
 		   		   break;
 		   	   }
 		   case 0x0008:
 		   	   {
 		   		   relay_ctrl = 0x00A10000;
 		   		   break;
 		   	   }
 		   case 0x0041:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0042:
 		   	   {
 		   		   relay_ctrl = 0x00008000;
 		   		   break;
 		   	   }
 		   case 0x0043:
 		   	   {
 		   		   relay_ctrl = 0x00100000;
 		   		   break;
 		   	   }
 		   case 0x0044:
 		   	   {
 		   		   relay_ctrl = 0x00108000;
 		   		   break;
 		   	   }
 		   case 0x0045:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0046:
 		   	   {
 		   		   relay_ctrl = 0x00804000;
 		   		   break;
 		   	   }
 		   case 0x0047:
 		   	   {
 		   		   relay_ctrl = 0x00900000;
 		   		   break;
 		   	   }
 		   case 0x0048:
 		   	   {
 		   		   relay_ctrl = 0x00904000;
 		   		   break;
 		   	   }
 		   case 0x0081:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0082:
 		   	   {
 		   		   relay_ctrl = 0x00002000;
 		   		   break;
 		   	   }
 		   case 0x0083:
 		   	   {
 		   		   relay_ctrl = 0x00080000;
 		   		   break;
 		   	   }
 		   case 0x0084:
 		   	   {
 		   		   relay_ctrl = 0x00082000;
 		   		   break;
 		   	   }
 		   case 0x0085:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x0086:
 		   	   {
 		   		   relay_ctrl = 0x00401000;
 		   		   break;
 		   	   }
 		   case 0x0087:
 		   	   {
 		   		   relay_ctrl = 0x00480000;
 		   		   break;
 		   	   }
 		   case 0x0088:
 		   	   {
 		   		   relay_ctrl = 0x00481000;
 		   		   break;
 		   	   }
 		   case 0x00C1:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x00C2:
 		   	   {
 		   		   relay_ctrl = 0x00000800;
 		   		   break;
 		   	   }
 		   case 0x00C3:
 		   	   {
 		   		   relay_ctrl = 0x00040000;
 		   		   break;
 		   	   }
 		   case 0x00C4:
 		   	   {
 		   		   relay_ctrl = 0x00040800;
 		   		   break;
 		   	   }
 		   case 0x00C5:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x00C6:
 		   	   {
 		   		   relay_ctrl = 0x00400400;
 		   		   break;
 		   	   }
 		   case 0x00C7:
 		   	   {
 		   		   relay_ctrl = 0x00440000;
 		   		   break;
 		   	   }
 		   case 0x00C8:
 		   	   {
 		   		   relay_ctrl = 0x00440400;
 		   		   break;
 		   	   }
 		 }
 		 ch_num_dat = ((u32)ch_num)<<1;
 		 cpld_dat   = relay_ctrl|ch_num_dat|slot_en;
 		 sw_config_data[0] = (u8)(cpld_dat>>16);
 		 sw_config_data[1] = (u8)(cpld_dat>>8);
 		 sw_config_data[2] = (u8)cpld_dat;
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
 }
@@ -1,217 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 u8      cpld_addr = 0;
 		 u32     cpld_dat  = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(slot==1)
 		 {
 			 cpld_addr = 0x82;
 		 }
 		 else if(slot==2)
 		 {
 			 cpld_addr = 0x83;
 		 }
 		 else if(slot==3)
 		 {
 			 cpld_addr = 0x84;
 		 }
 		 else
 		 {
 			 cpld_addr = 0x85;
 		 }
 		 switch(ch_num)
 		 {
 		   case 0x0001:
 		 	   {
 		 		   relay_ctrl = 0x00000000;
 		 		   break;
 		 	   }
 		   case 0x0002:
 		   	   {
 		   		   relay_ctrl = 0x00020000;
 		   		   break;
 		   	   }
 		   case 0x0003:
 		   	   {
 		   		   relay_ctrl = 0x00200000;
 		   		   break;
 		   	   }
 		   case 0x0004:
 		   	   {
 		   		   relay_ctrl = 0x00022000;
 		   		   break;
 		   	   }
 		   case 0x0005:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0006:
 		   	   {
 		   		   relay_ctrl = 0x00810000;
 		   		   break;
 		   	   }
 		   case 0x0007:
 		   	   {
 		   		   relay_ctrl = 0x00A00000;
 		   		   break;
 		   	   }
 		   case 0x0008:
 		   	   {
 		   		   relay_ctrl = 0x00A10000;
 		   		   break;
 		   	   }
 		   case 0x0041:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0042:
 		   	   {
 		   		   relay_ctrl = 0x00008000;
 		   		   break;
 		   	   }
 		   case 0x0043:
 		   	   {
 		   		   relay_ctrl = 0x00100000;
 		   		   break;
 		   	   }
 		   case 0x0044:
 		   	   {
 		   		   relay_ctrl = 0x00108000;
 		   		   break;
 		   	   }
 		   case 0x0045:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0046:
 		   	   {
 		   		   relay_ctrl = 0x00804000;
 		   		   break;
 		   	   }
 		   case 0x0047:
 		   	   {
 		   		   relay_ctrl = 0x00900000;
 		   		   break;
 		   	   }
 		   case 0x0048:
 		   	   {
 		   		   relay_ctrl = 0x00904000;
 		   		   break;
 		   	   }
 		   case 0x0081:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0082:
 		   	   {
 		   		   relay_ctrl = 0x00002000;
 		   		   break;
 		   	   }
 		   case 0x0083:
 		   	   {
 		   		   relay_ctrl = 0x00080000;
 		   		   break;
 		   	   }
 		   case 0x0084:
 		   	   {
 		   		   relay_ctrl = 0x00082000;
 		   		   break;
 		   	   }
 		   case 0x0085:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x0086:
 		   	   {
 		   		   relay_ctrl = 0x00401000;
 		   		   break;
 		   	   }
 		   case 0x0087:
 		   	   {
 		   		   relay_ctrl = 0x00480000;
 		   		   break;
 		   	   }
 		   case 0x0088:
 		   	   {
 		   		   relay_ctrl = 0x00481000;
 		   		   break;
 		   	   }
 		   case 0x00C1:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x00C2:
 		   	   {
 		   		   relay_ctrl = 0x00000800;
 		   		   break;
 		   	   }
 		   case 0x00C3:
 		   	   {
 		   		   relay_ctrl = 0x00040000;
 		   		   break;
 		   	   }
 		   case 0x00C4:
 		   	   {
 		   		   relay_ctrl = 0x00040800;
 		   		   break;
 		   	   }
 		   case 0x00C5:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x00C6:
 		   	   {
 		   		   relay_ctrl = 0x00400400;
 		   		   break;
 		   	   }
 		   case 0x00C7:
 		   	   {
 		   		   relay_ctrl = 0x00440000;
 		   		   break;
 		   	   }
 		   case 0x00C8:
 		   	   {
 		   		   relay_ctrl = 0x00440400;
 		   		   break;
 		   	   }
 		 }
 }
@@ -1,79 +0,0 @@
 /*
 * GPIO_Driv.c
 *
 *  Created on: 2021年5月7日
 *      Author: Administrator
 */
 #include "GPIO_Driv.h"
 XGpioPs psGpioInstancePtr;     //端口
 XGpioPs_Config* GpioConfigPtr; //设备ID
 					//sck,cs,sdi,sdo,rst
 u32 CPLD_U1  [11] = {54,55,56,57,58,59,60,61,62,63,64};
 u32 CPLD_U2  [11] = {65,66,67,68,69,70,71,72,73,74,75};
 u32 CPLD_U3  [11] = {76,77,78,79,80,81,82,83,84,85,86};
 void EMIO_config(void)
 {
 	    int xStatus;
 		GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
 		if(GpioConfigPtr == NULL)
 			return XST_FAILURE;
 		xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
 		if(XST_SUCCESS != xStatus)
 			print(" PS GPIO INIT FAILED \n\r");
 		/*-------------------------------------CPLD_U1------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 1);//57---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 0);//58---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59---sdio3
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60---sdio4
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61---sdio5
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62---sdio6
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63---sdio7
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 1);//57---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 0);//58---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//---sdio3
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//---sdio4
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//---sdio5
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//---sdio6
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//---sdio7
 		/*-------------------------------------CPLD_U2------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//61---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//62---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//63---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//64---sdo
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//65---rst
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66---sdio3
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67---sdio4
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67---sdio5
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67---sdio6
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67---sdio7
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
 }
@@ -1,237 +0,0 @@
 /*
 * Copyright (C) 2009 - 2019 Xilinx, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
 * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
 * OF SUCH DAMAGE.
 *
 */
 #include <stdio.h>
 #include <string.h>
 #include "dna_read.h"
 #include "crc16.h"
 #include "GPIO_Driv.h"
 #include "SPI_Driv.h"
 #include "cal_meas.h"
 #include "lwip/err.h"
 #include "lwip/tcp.h"
 #if defined (__arm__) || defined (__aarch64__)
 #include "xil_printf.h"
 #endif
 char *recv_data;
 char dna_data[10];
 unsigned short recv_len;
 unsigned  read_dat = 0;
 char 	  dat_0[20] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
 unsigned  crc_read_dat = 0;
 char     crc_alg_dat[2] = {0,0};
 char     send_data_cpld1[2] = {0xAA,0x56};
 int transfer_data() {
 	return 0;
 }
 void print_app_header()
 {
 #if (LWIP_IPV6==0)
 	xil_printf("\n\r\n\r-----lwIP TCP echo server ------\n\r");
 #else
 	xil_printf("\n\r\n\r-----lwIPv6 TCP echo server ------\n\r");
 #endif
 	xil_printf("TCP packets sent to port 6001 will be echoed back\n\r");
 }
 err_t recv_callback(void *arg, struct tcp_pcb *tpcb,
                               struct pbuf *p, err_t err)
 {
 	/* do not read the packet if we are not in ESTABLISHED state */
 	if (!p) {
 		tcp_close(tpcb);
 		tcp_recv(tpcb, NULL);
 		return ERR_OK;
 	}
 	/* indicate that the packet has been received */
 	tcp_recved(tpcb, p->len);
 	/* echo back the payload */
 	/* in this case, we assume that the payload is < TCP_SND_BUF */
 	if (tcp_sndbuf(tpcb) > p->len) {
 		recv_len = p->len;
 		recv_data = (char*)malloc(sizeof(char)*recv_len);
 	    memcpy(recv_data,p->payload,recv_len);
 	    if(recv_data[6] == 0x0E)
 	    {
 	    	crc_read_dat = do_crc_table(recv_data+6, recv_len-8);
 	    	crc_alg_dat[0] = (u8)crc_read_dat;
 	    	crc_alg_dat[1] = (u8)(crc_read_dat>>8);
 	    	dat_0[0]= 0x00;
 	    	switch(recv_data[7])
 	    	{
 	    	  case 0xA2://SLOT
 	    	          {
 						  dat_0[1]= 0x06;
 						  dat_0[2]= recv_data[2];
 						  dat_0[3]= recv_data[3];
 						  dat_0[4]= recv_data[4];
 						  dat_0[5]= recv_data[5];
 						  dat_0[6]= recv_data[6];
 						  dat_0[7]= recv_data[7];
 	    	        	  if(recv_data[15]==crc_alg_dat[1]&&recv_data[16]==crc_alg_dat[0])
 	    	        	  {
 	    	        		  dat_0[8]= 0x01;
 	    	        		  dat_0[9]= 0x01;
 	    	        	  }
 	    	        	  else
 						  {
 							  dat_0[8]= 0xff;
 							  dat_0[9]= 0xff;
 						  }
 	    	        	  dat_0[10]= recv_data[15];
 	    	        	  dat_0[11]= recv_data[16];
 	    	        	  char slot_start[7] = {recv_data[8],recv_data[9],recv_data[10],recv_data[11],recv_data[12],recv_data[13],recv_data[14]};
 	    	        	  //xil_printf("slot_start[0]:%x, slot_start[1]:%x,slot_start[2]:%x,slot_start[3]:%x,slot_start[4]:%x,slot_start[5]:%x,slot_start[6]:%x\n\r", slot_start[0],slot_start[1],slot_start[2],slot_start[3],slot_start[4],slot_start[5],slot_start[6]);
 	    	        	  rst_CPLD(CPLD_U1,4);
 	    	        	  rst_CPLD(CPLD_U2,4);
 	    	        	  rst_CPLD(CPLD_U3,4);
 	    	        	  sw_config(slot_start);
 	    	        	  tcp_write(tpcb, dat_0, 12, 1);
 	    	        	  break;
 	    	          }
 	    	  case 0xA3://dna_port_read
 					  {
 						  dna_port_read(dna_data);
 						  dat_0[1]=0x0e;
 						  dat_0[2]=recv_data[2];
 						  dat_0[3]=recv_data[3];
 						  dat_0[4]=recv_data[4];
 						  dat_0[5]=recv_data[5];
 						  dat_0[6]=recv_data[6];
 						  dat_0[7]=recv_data[7];
 						  if(recv_data[8]==crc_alg_dat[1]&&recv_data[9]==crc_alg_dat[0])
 						  {
 							  dat_0[8]= 0x01;
 							  dat_0[9]= 0x01;
 						  }
 						  else
 						  {
 							  dat_0[8]= 0xff;
 							  dat_0[9]= 0xff;
 						  }
 						  dat_0[10]= dna_data[0];
 						  dat_0[11]= dna_data[1];
 						  dat_0[12]= dna_data[2];
 						  dat_0[13]= dna_data[3];
 						  dat_0[14]= dna_data[4];
 						  dat_0[15]= dna_data[5];
 						  dat_0[16]= dna_data[6];
 						  dat_0[17]= dna_data[7];
 						  dat_0[18]= recv_data[8];
 						  dat_0[19]= recv_data[9];
 						  tcp_write(tpcb, dat_0, 20, 1);
 						  break;
 					  }
 	    	}
 	    }
 	} else
 		xil_printf("no space in tcp_sndbuf\n\r");
 	/* free the received pbuf */
 	pbuf_free(p);
 	return ERR_OK;
 }
 err_t accept_callback(void *arg, struct tcp_pcb *newpcb, err_t err)
 {
 	static int connection = 1;
 	/* set the receive callback for this connection */
 	tcp_recv(newpcb, recv_callback);
 	/* just use an integer number indicating the connection id as the
 	   callback argument */
 	tcp_arg(newpcb, (void*)(UINTPTR)connection);
 	/* increment for subsequent accepted connections */
 	connection++;
 	return ERR_OK;
 }
 int start_application()
 {
 	struct tcp_pcb *pcb;
 	err_t err;
 	unsigned port = 200;
 	/* create new TCP PCB structure */
 	pcb = tcp_new_ip_type(IPADDR_TYPE_ANY);
 	if (!pcb) {
 		xil_printf("Error creating PCB. Out of Memory\n\r");
 		return -1;
 	}
 	/* bind to specified @port */
 	err = tcp_bind(pcb, IP_ANY_TYPE, port);
 	if (err != ERR_OK) {
 		xil_printf("Unable to bind to port %d: err = %d\n\r", port, err);
 		return -2;
 	}
 	/* we do not need any arguments to callback functions */
 	tcp_arg(pcb, NULL);
 	/* listen for connections */
 	pcb = tcp_listen(pcb);
 	if (!pcb) {
 		xil_printf("Out of memory while tcp_listen\n\r");
 		return -3;
 	}
 	/* specify callback to use for incoming connections */
 	tcp_accept(pcb, accept_callback);
 	xil_printf("TCP echo server started @ port %d\n\r", port);
 	return 0;
 }
@@ -1,242 +0,0 @@
 /*
 * Copyright (C) 2009 - 2019 Xilinx, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
 * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
 * OF SUCH DAMAGE.
 *
 */
 #include <stdio.h>
 #include <string.h>
 #include "dna_read.h"
 #include "crc16.h"
 #include "GPIO_Driv.h"
 #include "SPI_Driv.h"
 #include "cal_meas.h"
 #include "lwip/err.h"
 #include "lwip/tcp.h"
 #if defined (__arm__) || defined (__aarch64__)
 #include "xil_printf.h"
 #endif
 char *recv_data;
 char dna_data[10];
 unsigned short recv_len;
 unsigned  read_dat = 0;
 char 	  dat_0[20] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
 unsigned  crc_read_dat = 0;
 char     crc_alg_dat[2] = {0,0};
 char     send_data_cpld1[2] = {0xAA,0x56};
 int transfer_data() {
 	return 0;
 }
 void print_app_header()
 {
 #if (LWIP_IPV6==0)
 	xil_printf("\n\r\n\r-----lwIP TCP echo server ------\n\r");
 #else
 	xil_printf("\n\r\n\r-----lwIPv6 TCP echo server ------\n\r");
 #endif
 	xil_printf("TCP packets sent to port 6001 will be echoed back\n\r");
 }
 err_t recv_callback(void *arg, struct tcp_pcb *tpcb,
                               struct pbuf *p, err_t err)
 {
 	/* do not read the packet if we are not in ESTABLISHED state */
 	if (!p) {
 		tcp_close(tpcb);
 		tcp_recv(tpcb, NULL);
 		return ERR_OK;
 	}
 	/* indicate that the packet has been received */
 	tcp_recved(tpcb, p->len);
 	/* echo back the payload */
 	/* in this case, we assume that the payload is < TCP_SND_BUF */
 	if (tcp_sndbuf(tpcb) > p->len) {
 		recv_len = p->len;
 		recv_data = (char*)malloc(sizeof(char)*recv_len);
 	    memcpy(recv_data,p->payload,recv_len);
 	    if(recv_data[6] == 0x0E)
 	    {
 	    	crc_read_dat = do_crc_table(recv_data+6, recv_len-8);
 	    	crc_alg_dat[0] = (u8)crc_read_dat;
 	    	crc_alg_dat[1] = (u8)(crc_read_dat>>8);
 	    	dat_0[0]= 0x00;
 	    	switch(recv_data[7])
 	    	{
 	    	  case 0xA2://SLOT
 	    	          {
 						  dat_0[1]= 0x06;
 						  dat_0[2]= recv_data[2];
 						  dat_0[3]= recv_data[3];
 						  dat_0[4]= recv_data[4];
 						  dat_0[5]= recv_data[5];
 						  dat_0[6]= recv_data[6];
 						  dat_0[7]= recv_data[7];
 	    	        	  if(recv_data[15]==crc_alg_dat[1]&&recv_data[16]==crc_alg_dat[0])
 	    	        	  {
 	    	        		  dat_0[8]= 0x01;
 	    	        		  dat_0[9]= 0x01;
 	    	        	  }
 	    	        	  else
 						  {
 							  dat_0[8]= 0xff;
 							  dat_0[9]= 0xff;
 						  }
 	    	        	  dat_0[10]= recv_data[15];
 	    	        	  dat_0[11]= recv_data[16];
 	    	        	  char slot_start[7] = {recv_data[8],recv_data[9],recv_data[10],recv_data[11],recv_data[12],recv_data[13],recv_data[14]};
 	    	        	  //xil_printf("slot_start[0]:%x, slot_start[1]:%x,slot_start[2]:%x,slot_start[3]:%x,slot_start[4]:%x,slot_start[5]:%x,slot_start[6]:%x\n\r", slot_start[0],slot_start[1],slot_start[2],slot_start[3],slot_start[4],slot_start[5],slot_start[6]);
 	    	        	  rst_CPLD(CPLD_U1,4);
 	    	        	  rst_CPLD(CPLD_U2,4);
 	    	        	  rst_CPLD(CPLD_U3,4);
 	    	        	  sw_config(slot_start);
 	    	        	  tcp_write(tpcb, dat_0, 12, 1);
 	    	        	  break;
 	    	          }
 	    	  case 0xA3://dna_port_read
 					  {
 						  dna_port_read(dna_data);
 						  dat_0[1]=0x0e;
 						  dat_0[2]=recv_data[2];
 						  dat_0[3]=recv_data[3];
 						  dat_0[4]=recv_data[4];
 						  dat_0[5]=recv_data[5];
 						  dat_0[6]=recv_data[6];
 						  dat_0[7]=recv_data[7];
 						  if(recv_data[8]==crc_alg_dat[1]&&recv_data[9]==crc_alg_dat[0])
 						  {
 							  dat_0[8]= 0x01;
 							  dat_0[9]= 0x01;
 						  }
 						  else
 						  {
 							  dat_0[8]= 0xff;
 							  dat_0[9]= 0xff;
 						  }
 						  dat_0[10]= dna_data[0];
 						  dat_0[11]= dna_data[1];
 						  dat_0[12]= dna_data[2];
 						  dat_0[13]= dna_data[3];
 						  dat_0[14]= dna_data[4];
 						  dat_0[15]= dna_data[5];
 						  dat_0[16]= dna_data[6];
 						  dat_0[17]= dna_data[7];
 						  dat_0[18]= recv_data[8];
 						  dat_0[19]= recv_data[9];
 						  tcp_write(tpcb, dat_0, 20, 1);
 						  break;
 					  }
 	    	}
 	    }
 	} else
 		xil_printf("no space in tcp_sndbuf\n\r");
 	/* free the received pbuf */
 	pbuf_free(p);
 	return ERR_OK;
 }
 err_t accept_callback(void *arg, struct tcp_pcb *newpcb, err_t err)
 {
 	static int connection = 1;
 	/* set the receive callback for this connection */
 	tcp_recv(newpcb, recv_callback);
 	/* just use an integer number indicating the connection id as the
 	   callback argument */
 	tcp_arg(newpcb, (void*)(UINTPTR)connection);
 	/* increment for subsequent accepted connections */
 	connection++;
 	return ERR_OK;
 }
 int start_application()
 {
 	struct tcp_pcb *pcb;
 	err_t err;
 	unsigned port = 200;
 	/* create new TCP PCB structure */
 	pcb = tcp_new_ip_type(IPADDR_TYPE_ANY);
 	if (!pcb) {
 		xil_printf("Error creating PCB. Out of Memory\n\r");
 		return -1;
 	}
 	/* bind to specified @port */
 	err = tcp_bind(pcb, IP_ANY_TYPE, port);
 	if (err != ERR_OK) {
 		xil_printf("Unable to bind to port %d: err = %d\n\r", port, err);
 		return -2;
 	}
 	/* we do not need any arguments to callback functions */
 	tcp_arg(pcb, NULL);
 	/* listen for connections */
 	pcb = tcp_listen(pcb);
 	if (!pcb) {
 		xil_printf("Out of memory while tcp_listen\n\r");
 		return -3;
 	}
 	/* specify callback to use for incoming connections */
 	tcp_accept(pcb, accept_callback);
 	xil_printf("TCP echo server started @ port %d\n\r", port);
 	return 0;
 }
@@ -1,29 +0,0 @@
 /*
 * cal_meas.h
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #ifndef SRC_CAL_MEAS_H_
 #define SRC_CAL_MEAS_H_
 #include "sleep.h"
 #include "stdio.h"
 #include "xgpiops.h"
 #include "SPI_Driv.h"
 #include "GPIO_Driv.h"
 #define     U1_SW_FC_DV0  1
 #define     dat_width     3
 void  sw_init( void );
 void  sw_config(char *slot_start);
 void  fsmc_mmc_config(char slot,char m_fun);
 void  dmm_config(char slot, u16 ch_num);
 void  rc_config(char m_fun);
 void  fsc_oc_config(char slot,char m_fun, u16 ch_num);
 void  rl_config(char load);
 #endif /* SRC_CAL_MEAS_H_ */
@@ -1,81 +0,0 @@
 /*
 * GPIO_Driv.c
 *
 *  Created on: 2021年5月7日
 *      Author: Administrator
 */
 #include "GPIO_Driv.h"
 XGpioPs psGpioInstancePtr;     //端口
 XGpioPs_Config* GpioConfigPtr; //设备ID
 					//sck,cs,sdi,sdo,rst
 u32 CPLD_U1  [11] = {54,55,56,57,58,59,60,61,62,63,64};
 u32 CPLD_U2  [11] = {65,66,67,68,69,70,71,72,73,74,75};
 u32 CPLD_U3  [11] = {76,77,78,79,80,81,82,83,84,85,86};
 void EMIO_config(void)
 {
 	    int xStatus;
 		GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
 		if(GpioConfigPtr == NULL)
 			return XST_FAILURE;
 		xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
 		if(XST_SUCCESS != xStatus)
 			print(" PS GPIO INIT FAILED \n\r");
 		/*-------------------------------------CPLD_U1------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 1);//57---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 0);//58---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59---sdio3
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60---sdio4
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61---sdio5
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62---sdio6
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63---sdio7
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 1);//57---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 0);//58---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//---sdio3
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//---sdio4
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//---sdio5
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//---sdio6
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//---sdio7
 		/*-------------------------------------CPLD_U2------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 1);//68---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 0);//69---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66---sdio3
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67---sdio4
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67---sdio5
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67---sdio6
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67---sdio7
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 1);//68---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 0);//69---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
 }
@@ -1,157 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 u8      cpld_addr = 0;
 		 u32     cpld_dat  = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(slot==1)
 		 {
 			 cpld_addr = 0x82;
 		 }
 		 else if(slot==2)
 		 {
 			 cpld_addr = 0x83;
 		 }
 		 else if(slot==3)
 		 {
 			 cpld_addr = 0x84;
 		 }
 		 else
 		 {
 			 cpld_addr = 0x85;
 		 }
 		 switch(ch_num)
 		 {
 		   case 0x0001:
 		 	   {
 		 		   relay_ctrl = 0x00000000;
 		 		   break;
 		 	   }
 		   case 0x0002:
 		   	   {
 		   		   relay_ctrl = 0x00020000;
 		   		   break;
 		   	   }
 		   case 0x0003:
 		   	   {
 		   		   relay_ctrl = 0x00200000;
 		   		   break;
 		   	   }
 		   case 0x0004:
 		   	   {
 		   		   relay_ctrl = 0x00022000;
 		   		   break;
 		   	   }
 		   case 0x0005:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0006:
 		   	   {
 		   		   relay_ctrl = 0x00810000;
 		   		   break;
 		   	   }
 		   case 0x0007:
 		   	   {
 		   		   relay_ctrl = 0x00A00000;
 		   		   break;
 		   	   }
 		   case 0x0008:
 		   	   {
 		   		   relay_ctrl = 0x00A10000;
 		   		   break;
 		   	   }
 		   case 0x0041:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0042:
 		   	   {
 		   		   relay_ctrl = 0x00008000;
 		   		   break;
 		   	   }
 		   case 0x0043:
 		   	   {
 		   		   relay_ctrl = 0x00100000;
 		   		   break;
 		   	   }
 		   case 0x0044:
 		   	   {
 		   		   relay_ctrl = 0x00108000;
 		   		   break;
 		   	   }
 		   case 0x0045:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0046:
 		   	   {
 		   		   relay_ctrl = 0x00804000;
 		   		   break;
 		   	   }
 		   case 0x0047:
 		   	   {
 		   		   relay_ctrl = 0x00900000;
 		   		   break;
 		   	   }
 		   case 0x0048:
 		   	   {
 		   		   relay_ctrl = 0x00904000;
 		   		   break;
 		   	   }
 		 }
 		 if(ch_num==1|ch_num==65|ch_num==129|ch_num==193)
 		 {
 			 relay_ctrl = 0x00000000;
 		 }
 		 if(ch_num>=1&&ch_num<=16)
 		  {
 		 	//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
 		 	fc_dv0_dat = (0x0001<<(ch_num-1));
 		 	fc_dv0_dat = ~fc_dv0_dat;
 		 	sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 		 	sw_config_data[1] = (u8)(fc_dv0_dat);
 		 	spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	//xil_printf("CPLD_U1:\n\r");
 		 	//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 		 	//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 		 }
 }
@@ -1,285 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0xFF,0xFF,0xFF};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16     u1_io_rc_dat = 0;
 		 u16     u1_rc_dat = 0;
 		 u16     u1_lofs_vpk_dat = 0;
 		 u16     u1_lofs_apk_dat = 0;
 		 u16     u1_lofs_vpk_apk_dat = 0;
 		 u16 	 ch_num = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 //xil_printf("slot: %d\n\r", slot);
 		 //xil_printf("m_fun: %d\n\r", m_fun);
 		 //xil_printf("ch_num: %d\n\r", ch_num);
 		 fsc_oc_config(slot,m_fun,ch_num);
 		 if(m_fun==0x04)
 		 {
 			 dmm_config(slot,ch_num);
 			 //xil_printf("memt_areal: %d\n\r", memt_areal);
 			 if(memt_areal==0x01)
 			 {
 				 u1_io_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_io_rc_dat);
 				 spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
 				 //xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
 			 }
 			 else
 			 {
 				 u1_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_rc_dat);
 				 spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
 				// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
 			 }
 		 }
 }
 void  dmm_config(char slot, u16 ch_num)
 {
 	u16   sw_oc_dmm_dat = 0;
 	if(ch_num>=1&&ch_num<=64)
 	{
 		sw_oc_dmm_dat = (0x0001<<((slot-1)*4));
 		sw_oc_dmm_dat = ~sw_oc_dmm_dat;
 	}
 	else if(ch_num>=65&&ch_num<=128)
 	{
 		sw_oc_dmm_dat = (0x0001<<((slot-1)*4+1));
 		sw_oc_dmm_dat = ~sw_oc_dmm_dat;
 	}
 	else if(ch_num>=129&&ch_num<=192)
 	{
 		sw_oc_dmm_dat = (0x0001<<((slot-1)*4+2));
 		sw_oc_dmm_dat = ~sw_oc_dmm_dat;
 	}
 	else
 	{
 		sw_oc_dmm_dat = (0x0001<<((slot-1)*4+3));
 		sw_oc_dmm_dat = ~sw_oc_dmm_dat;
 	}
 	//xil_printf("oc_dmm_dat: %x\n\r", sw_oc_dmm_dat);
 	sw_config_data[0] = (u8)(sw_oc_dmm_dat>>8);
 	sw_config_data[1] = (u8)(sw_oc_dmm_dat);
 	spi_write_onewire(U1_SW_OC_DMM, sw_config_data, dat_width, CPLD_U1);
 }
 void  rc_config(char m_fun)
 {
 	u16     rc_dat = 0;
 	switch(m_fun)
 	{
 	   case 0x01:
 	   {
 		   rc_dat = 0xFFFD;
 		   break;
 	   }
 	   case 0x02:
 	   {
 		   rc_dat = 0xFFFB;
 		   break;
 	   }
 	   case 0x03:
 	   {
 		   rc_dat = 0xFFF9;
 		   break;
 	   }
 	}
 	//xil_printf("rc_dat: %x\n\r", rc_dat);
 	sw_config_data[0] = (u8)(rc_dat>>8);
 	sw_config_data[1] = (u8)(rc_dat);
 	spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
 }
 void  rl_config(char load)
 {
 	u16 rl_dat = 0;
 	if(load>=1&&load<=9)
 	{
 		rl_dat = (0x0001<<(load-1));
 		rl_dat = ~rl_dat;
 		//xil_printf("load: %x\n\r", load);
 		//xil_printf("rl_01_dat: %x\n\r", rl_dat);
 		sw_config_data[0] = (u8)(rl_dat>>8);
 		sw_config_data[1] = (u8)(rl_dat);
 		spi_write_onewire(U1_SW_RL1, sw_config_data, dat_width, CPLD_U1);
 	}
 	else
 	{
 		rl_dat = (0x0001<<(load-10));
 		rl_dat = ~rl_dat;
 		//xil_printf("load: %x\n\r", load);
 		//xil_printf("rl_02_dat: %x\n\r", rl_dat);
 		sw_config_data[0] = (u8)(rl_dat>>8);
 		sw_config_data[1] = (u8)(rl_dat);
 		spi_write_onewire(U1_SW_RL2, sw_config_data, dat_width, CPLD_U1);
 	}
 }
 void  fsc_oc_config(char slot,char m_fun, u16 ch_num)
 {
        u16	    fc_dv0_dat = 0;
 		switch(m_fun)
 		{
 		  case 0x01:
 		  {
 			  if(ch_num>=1&&ch_num<=16)
 			  {
 				  //xil_printf("m_fun=0x01,ch_num=1~16 \n\r");
 				  fc_dv0_dat = (0x0001<<(ch_num-1));
 				  fc_dv0_dat = ~fc_dv0_dat;
 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 				  spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 				  //xil_printf("CPLD_U1:\n\r");
 				  //xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 			  }
 			  else
 			  {
 				  //xil_printf("m_fun=0x01,ch_num=17~32 \n\r");
 				  fc_dv0_dat = (0x0001<<(ch_num-17));
 				  fc_dv0_dat = ~fc_dv0_dat;
 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 				  spi_write_onewire(U2_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
 				  //xil_printf("CPLD_U2:\n\r");
 				  //xil_printf("fc_reg_addr: %d\n\r", U2_SW_FC_DV0+slot-1);
 			  }
 			  //xil_printf("reg_data: %x\n\r", fc_dv0_dat);
 			  break;
 		  }
 		  case 0x02:
 		  {
 			  if(ch_num>=1&&ch_num<=16)
 			  {
 				  //xil_printf("m_fun=0x02,ch_num=1~16 \n\r");
 				  fc_dv0_dat = (0x0001<<(ch_num-1));
 				  fc_dv0_dat = ~fc_dv0_dat;
 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 				  spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 				  //xil_printf("CPLD_U1:\n\r");
 				  //xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 			  }
 			  else
 			  {
 				  //xil_printf("m_fun=0x02,ch_num=17~32 \n\r");
 				  fc_dv0_dat = (0x0001<<(ch_num-17));
 				  fc_dv0_dat = ~fc_dv0_dat;
 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 				  spi_write_onewire(U2_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
 				  //xil_printf("CPLD_U2:\n\r");
 				  //xil_printf("sc_reg_addr: %d\n\r", U2_SW_SC_DV0+slot-1);
 			  }
 			  //xil_printf("reg_data: %x\n\r", fc_dv0_dat);
 			  break;
 		  }
 		  case 0x03:
 		  {
 			  if(ch_num>=1&&ch_num<=16)
 			  {
 				  //xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
 				  fc_dv0_dat = (0x0001<<(ch_num-1));
 				  fc_dv0_dat = ~fc_dv0_dat;
 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 				  spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 				  spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 				  //xil_printf("CPLD_U1:\n\r");
 				  //xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 				  //xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 			  }
 			  else
 			  {
 				  //xil_printf("m_fun=0x03,ch_num=17~32 \n\r");
 				  fc_dv0_dat = (0x0001<<(ch_num-17));
 				  fc_dv0_dat = ~fc_dv0_dat;
 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 				  spi_write_onewire(U2_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
 				  spi_write_onewire(U2_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
 				  //xil_printf("CPLD_U2:\n\r");
 				  //xil_printf("fc_reg_addr: %d\n\r", U2_SW_FC_DV0+slot-1);
 				  //xil_printf("sc_reg_addr: %d\n\r", U2_SW_SC_DV0+slot-1);
 			  }
 			  //xil_printf("reg_data: %x\n\r", fc_dv0_dat);
 			  break;
 		  }
 		  case 0x04:
 		  {
 			  if(ch_num>=1&&ch_num<=64)
 			  {
 				  //xil_printf("m_fun=0x04,ch_num=1~64 \n\r");
 				  fc_dv0_dat = (0x0001<<((ch_num-1)/8));
 				  fc_dv0_dat = ~fc_dv0_dat;
 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 				  spi_write_onewire(U1_SW_OC_DV0+(slot-1)*2, sw_config_data, dat_width, CPLD_U1);
 				  //xil_printf("CPLD_U1:\n\r");
 				  //xil_printf("oc_reg_addr: %d\n\r", U1_SW_OC_DV0+(slot-1)*2);
 			  }
 			  else if(ch_num>=65&&ch_num<=128)
 			  {
 				  //xil_printf("m_fun=0x04,ch_num=65~128 \n\r");
 				  fc_dv0_dat = (0x0001<<((ch_num-65)/8));
 				  fc_dv0_dat = ~fc_dv0_dat;
 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 				  spi_write_onewire(U2_SW_OC_DV0+(slot-1)*2, sw_config_data, dat_width, CPLD_U2);
 				  //xil_printf("CPLD_U2:\n\r");
 				  //xil_printf("oc_reg_addr: %d\n\r", U2_SW_OC_DV0+(slot-1)*2);
 			  }
 			  else if(ch_num>=129&&ch_num<=192)
 			  {
 				  //xil_printf("m_fun=0x04,ch_num=129~192 \n\r");
 				  fc_dv0_dat = (0x0001<<((ch_num-129)/8));
 				  fc_dv0_dat = ~fc_dv0_dat;
 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 				  spi_write_onewire(U1_SW_OC_DV1+(slot-1)*2, sw_config_data, dat_width, CPLD_U1);
 				  //xil_printf("CPLD_U1:\n\r");
 				  //xil_printf("oc_reg_addr: %d\n\r", U1_SW_OC_DV1+(slot-1)*2);
 			  }
 			  else if(ch_num>=193&&ch_num<=256)
 			  {
 				  //xil_printf("m_fun=0x04,ch_num=193~256 \n\r");
 				  fc_dv0_dat = (0x0001<<((ch_num-193)/8));
 				  fc_dv0_dat = ~fc_dv0_dat;
 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 				  spi_write_onewire(U2_SW_OC_DV1+(slot-1)*2, sw_config_data, dat_width, CPLD_U2);
 				  //xil_printf("CPLD_U2:\n\r");
 				  //xil_printf("oc_reg_addr: %d\n\r", U2_SW_OC_DV1+(slot-1)*2);
 			  }
 			  //xil_printf("reg_data: %x\n\r", fc_dv0_dat);
 			  break;
 		  }
       }
 }
@@ -1,237 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 u8      cpld_addr = 0;
 		 u32     cpld_dat  = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(slot==1)
 		 {
 			 cpld_addr = 0x82;
 		 }
 		 else if(slot==2)
 		 {
 			 cpld_addr = 0x83;
 		 }
 		 else if(slot==3)
 		 {
 			 cpld_addr = 0x84;
 		 }
 		 else
 		 {
 			 cpld_addr = 0x85;
 		 }
 		 switch(ch_num)
 		 {
 		   case 0x0001:
 		 	   {
 		 		   relay_ctrl = 0x00000000;
 		 		   break;
 		 	   }
 		   case 0x0002:
 		   	   {
 		   		   relay_ctrl = 0x00020000;
 		   		   break;
 		   	   }
 		   case 0x0003:
 		   	   {
 		   		   relay_ctrl = 0x00200000;
 		   		   break;
 		   	   }
 		   case 0x0004:
 		   	   {
 		   		   relay_ctrl = 0x00022000;
 		   		   break;
 		   	   }
 		   case 0x0005:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0006:
 		   	   {
 		   		   relay_ctrl = 0x00810000;
 		   		   break;
 		   	   }
 		   case 0x0007:
 		   	   {
 		   		   relay_ctrl = 0x00A00000;
 		   		   break;
 		   	   }
 		   case 0x0008:
 		   	   {
 		   		   relay_ctrl = 0x00A10000;
 		   		   break;
 		   	   }
 		   case 0x0041:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0042:
 		   	   {
 		   		   relay_ctrl = 0x00008000;
 		   		   break;
 		   	   }
 		   case 0x0043:
 		   	   {
 		   		   relay_ctrl = 0x00100000;
 		   		   break;
 		   	   }
 		   case 0x0044:
 		   	   {
 		   		   relay_ctrl = 0x00108000;
 		   		   break;
 		   	   }
 		   case 0x0045:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0046:
 		   	   {
 		   		   relay_ctrl = 0x00804000;
 		   		   break;
 		   	   }
 		   case 0x0047:
 		   	   {
 		   		   relay_ctrl = 0x00900000;
 		   		   break;
 		   	   }
 		   case 0x0048:
 		   	   {
 		   		   relay_ctrl = 0x00904000;
 		   		   break;
 		   	   }
 		   case 0x0081:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0082:
 		   	   {
 		   		   relay_ctrl = 0x00002000;
 		   		   break;
 		   	   }
 		   case 0x0083:
 		   	   {
 		   		   relay_ctrl = 0x00080000;
 		   		   break;
 		   	   }
 		   case 0x0084:
 		   	   {
 		   		   relay_ctrl = 0x00082000;
 		   		   break;
 		   	   }
 		   case 0x0085:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x0086:
 		   	   {
 		   		   relay_ctrl = 0x00401000;
 		   		   break;
 		   	   }
 		   case 0x0087:
 		   	   {
 		   		   relay_ctrl = 0x00480000;
 		   		   break;
 		   	   }
 		   case 0x0088:
 		   	   {
 		   		   relay_ctrl = 0x00481000;
 		   		   break;
 		   	   }
 		   case 0x00C1:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x00C2:
 		   	   {
 		   		   relay_ctrl = 0x00000800;
 		   		   break;
 		   	   }
 		   case 0x00C3:
 		   	   {
 		   		   relay_ctrl = 0x00040000;
 		   		   break;
 		   	   }
 		   case 0x00C4:
 		   	   {
 		   		   relay_ctrl = 0x00040800;
 		   		   break;
 		   	   }
 		   case 0x00C5:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x00C6:
 		   	   {
 		   		   relay_ctrl = 0x00400400;
 		   		   break;
 		   	   }
 		   case 0x00C7:
 		   	   {
 		   		   relay_ctrl = 0x00440000;
 		   		   break;
 		   	   }
 		   case 0x00C8:
 		   	   {
 		   		   relay_ctrl = 0x00440400;
 		   		   break;
 		   	   }
 		 }
 		 if(ch_num==1|ch_num==65|ch_num==129|ch_num==193)
 		 {
 			 relay_ctrl = 0x00000000;
 		 }
 		 if(ch_num>=1&&ch_num<=16)
 		  {
 		 	//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
 		 	fc_dv0_dat = (0x0001<<(ch_num-1));
 		 	fc_dv0_dat = ~fc_dv0_dat;
 		 	sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 		 	sw_config_data[1] = (u8)(fc_dv0_dat);
 		 	spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	//xil_printf("CPLD_U1:\n\r");
 		 	//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 		 	//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 		 }
 }
@@ -1,80 +0,0 @@
 /*
 * GPIO_Driv.c
 *
 *  Created on: 2021年5月7日
 *      Author: Administrator
 */
 #include "GPIO_Driv.h"
 XGpioPs psGpioInstancePtr;     //端口
 XGpioPs_Config* GpioConfigPtr; //设备ID
 					//sck,cs,sdi,sdo,rst
 u32 CPLD_U1  [11] = {54,55,56,57,58,59,60,61,62,63,64};
 u32 CPLD_U2  [11] = {65,66,67,68,69,70,71,72,73,74,75};
 u32 CPLD_U3  [11] = {76,77,78,79,80,81,82,83,84,85,86};
 void EMIO_config(void)
 {
 	    int xStatus;
 		GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
 		if(GpioConfigPtr == NULL)
 			return XST_FAILURE;
 		xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
 		if(XST_SUCCESS != xStatus)
 			print(" PS GPIO INIT FAILED \n\r");
 		/*-------------------------------------CPLD_U1------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 1);//57---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 0);//58---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59---sdio3
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60---sdio4
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61---sdio5
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62---sdio6
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63---sdio7
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 1);//57---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 0);//58---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//---sdio3
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//---sdio4
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//---sdio5
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//---sdio6
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//---sdio7
 		/*-------------------------------------CPLD_U2------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//61---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//65---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//62---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 1);//63---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 0);//64---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66---sdio3
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67---sdio4
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67---sdio5
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67---sdio6
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67---sdio7
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
 }
@@ -1,108 +0,0 @@
 /*
 * GPIO_Driv.c
 *
 *  Created on: 2021年5月7日
 *      Author: Administrator
 */
 #include "GPIO_Driv.h"
 XGpioPs psGpioInstancePtr;     //端口
 XGpioPs_Config* GpioConfigPtr; //设备ID
 					//sck,cs,sdi,sdo,rst
 u32 CPLD_U1  [11] = {54,55,56,57,58,59,60,61,62,63,64};
 u32 CPLD_U2  [11] = {65,66,67,68,69,70,71,72,73,74,75};
 u32 CPLD_U3  [11] = {76,77,78,79,80,81,82,83,84,85,86};
 void EMIO_config(void)
 {
 	    int xStatus;
 		GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
 		if(GpioConfigPtr == NULL)
 			return XST_FAILURE;
 		xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
 		if(XST_SUCCESS != xStatus)
 			print(" PS GPIO INIT FAILED \n\r");
 		/*-------------------------------------CPLD_U1------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 1);//57---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 0);//58---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 1);//57---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 0);//58---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//
 		/*-------------------------------------CPLD_U2------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 1);//68---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 0);//69---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 1);//68---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 0);//69---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
 		/*-------------------------------------CPLD_U3------------------------------------*/
 				//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//65---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//66---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//67---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 1);//68---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 0);//69---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//66
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//67
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//67
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//67
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//67
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//65---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//66---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//67---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 1);//68---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 0);//69---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);
 }
@@ -1,68 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(m_fun==0x04)
 		 {
 			 //xil_printf("memt_areal: %d\n\r", memt_areal);
 			 if(memt_areal==0x01)
 			 {
 				 u1_io_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_io_rc_dat);
 				 spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
 				 //xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
 			 }
 			 else
 			 {
 				 u1_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_rc_dat);
 				 spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
 				// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
 			 }
 		 }
 		 if(ch_num>=1&&ch_num<=16)
 		  {
 		 	//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
 		 	fc_dv0_dat = (0x0001<<(ch_num-1));
 		 	fc_dv0_dat = ~fc_dv0_dat;
 		 	sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 		 	sw_config_data[1] = (u8)(fc_dv0_dat);
 		 	spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	//xil_printf("CPLD_U1:\n\r");
 		 	//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 		 	//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 		 }
 }
@@ -1,67 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(m_fun==0x04)
 		 {
 			 //xil_printf("memt_areal: %d\n\r", memt_areal);
 			 if(memt_areal==0x01)
 			 {
 				 u1_io_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_io_rc_dat);
 				 spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
 				 //xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
 			 }
 			 else
 			 {
 				 u1_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_rc_dat);
 				 spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
 				// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
 			 }
 		 }
 		 if(ch_num>=1&&ch_num<=16)
 		  {
 		 	//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
 		 	fc_dv0_dat = (0x0001<<(ch_num-1));
 		 	fc_dv0_dat = ~fc_dv0_dat;
 		 	sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 		 	sw_config_data[1] = (u8)(fc_dv0_dat);
 		 	spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	//xil_printf("CPLD_U1:\n\r");
 		 	//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 		 	//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 		 }
 }
@@ -1,87 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 u8      cpld_addr = 0;
 		 u32     cpld_dat  = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(slot==1)
 		 {
 			 cpld_addr = 0x82;
 		 }
 		 else if(slot==2)
 		 {
 			 cpld_addr = 0x83;
 		 }
 		 else if(slot==3)
 		 {
 			 cpld_addr = 0x84;
 		 }
 		 else
 		 {
 			 cpld_addr = 0x85;
 		 }
 		 if(ch_num==1|ch_num==65|ch_num==129|ch_num==193)
 		 {
 			 //xil_printf("memt_areal: %d\n\r", memt_areal);
 			 if(memt_areal==0x01)
 			 {
 				 u1_io_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_io_rc_dat);
 				 spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
 				 //xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
 			 }
 			 else
 			 {
 				 u1_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_rc_dat);
 				 spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
 				// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
 			 }
 		 }
 		 if(ch_num>=1&&ch_num<=16)
 		  {
 		 	//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
 		 	fc_dv0_dat = (0x0001<<(ch_num-1));
 		 	fc_dv0_dat = ~fc_dv0_dat;
 		 	sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 		 	sw_config_data[1] = (u8)(fc_dv0_dat);
 		 	spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	//xil_printf("CPLD_U1:\n\r");
 		 	//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 		 	//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 		 }
 }
@@ -1,65 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0xFF,0xFF,0xFF};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(m_fun==0x04)
 		 {
 			 //xil_printf("memt_areal: %d\n\r", memt_areal);
 			 if(memt_areal==0x01)
 			 {
 				 u1_io_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_io_rc_dat);
 				 spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
 				 //xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
 			 }
 			 else
 			 {
 				 u1_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_rc_dat);
 				 spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
 				// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
 			 }
 		 }
 		 if(ch_num>=1&&ch_num<=16)
 		  {
 		 				  //xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
 		 				  fc_dv0_dat = (0x0001<<(ch_num-1));
 		 				  fc_dv0_dat = ~fc_dv0_dat;
 		 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 		 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 		 				  spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 				  spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 				  //xil_printf("CPLD_U1:\n\r");
 		 				  //xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 		 				  //xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 		 }
 }
@@ -1,247 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 u8      cpld_addr = 0;
 		 u32     cpld_dat  = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(slot==1)
 		 {
 			 cpld_addr = 0x82;
 		 }
 		 else if(slot==2)
 		 {
 			 cpld_addr = 0x83;
 		 }
 		 else if(slot==3)
 		 {
 			 cpld_addr = 0x84;
 		 }
 		 else
 		 {
 			 cpld_addr = 0x85;
 		 }
 		 switch(ch_num)
 		 {
 		   case 0x0001:
 		 	   {
 		 		   relay_ctrl = 0x00000000;
 		 		   break;
 		 	   }
 		   case 0x0002:
 		   	   {
 		   		   relay_ctrl = 0x00020000;
 		   		   break;
 		   	   }
 		   case 0x0003:
 		   	   {
 		   		   relay_ctrl = 0x00200000;
 		   		   break;
 		   	   }
 		   case 0x0004:
 		   	   {
 		   		   relay_ctrl = 0x00220000;
 		   		   break;
 		   	   }
 		   case 0x0005:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0006:
 		   	   {
 		   		   relay_ctrl = 0x00810000;
 		   		   break;
 		   	   }
 		   case 0x0007:
 		   	   {
 		   		   relay_ctrl = 0x00A00000;
 		   		   break;
 		   	   }
 		   case 0x0008:
 		   	   {
 		   		   relay_ctrl = 0x00A10000;
 		   		   break;
 		   	   }
 		   case 0x0041:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0042:
 		   	   {
 		   		   relay_ctrl = 0x00008000;
 		   		   break;
 		   	   }
 		   case 0x0043:
 		   	   {
 		   		   relay_ctrl = 0x00100000;
 		   		   break;
 		   	   }
 		   case 0x0044:
 		   	   {
 		   		   relay_ctrl = 0x00108000;
 		   		   break;
 		   	   }
 		   case 0x0045:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0046:
 		   	   {
 		   		   relay_ctrl = 0x00804000;
 		   		   break;
 		   	   }
 		   case 0x0047:
 		   	   {
 		   		   relay_ctrl = 0x00900000;
 		   		   break;
 		   	   }
 		   case 0x0048:
 		   	   {
 		   		   relay_ctrl = 0x00904000;
 		   		   break;
 		   	   }
 		   case 0x0081:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0082:
 		   	   {
 		   		   relay_ctrl = 0x00002000;
 		   		   break;
 		   	   }
 		   case 0x0083:
 		   	   {
 		   		   relay_ctrl = 0x00080000;
 		   		   break;
 		   	   }
 		   case 0x0084:
 		   	   {
 		   		   relay_ctrl = 0x00082000;
 		   		   break;
 		   	   }
 		   case 0x0085:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x0086:
 		   	   {
 		   		   relay_ctrl = 0x00401000;
 		   		   break;
 		   	   }
 		   case 0x0087:
 		   	   {
 		   		   relay_ctrl = 0x00480000;
 		   		   break;
 		   	   }
 		   case 0x0088:
 		   	   {
 		   		   relay_ctrl = 0x00481000;
 		   		   break;
 		   	   }
 		   case 0x00C1:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x00C2:
 		   	   {
 		   		   relay_ctrl = 0x00000800;
 		   		   break;
 		   	   }
 		   case 0x00C3:
 		   	   {
 		   		   relay_ctrl = 0x00040000;
 		   		   break;
 		   	   }
 		   case 0x00C4:
 		   	   {
 		   		   relay_ctrl = 0x00040800;
 		   		   break;
 		   	   }
 		   case 0x00C5:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x00C6:
 		   	   {
 		   		   relay_ctrl = 0x00400400;
 		   		   break;
 		   	   }
 		   case 0x00C7:
 		   	   {
 		   		   relay_ctrl = 0x00440000;
 		   		   break;
 		   	   }
 		   case 0x00C8:
 		   	   {
 		   		   relay_ctrl = 0x00440400;
 		   		   break;
 		   	   }
 		 }
 		 ch_num_dat = ((u32)ch_num)<<1;
 		 cpld_dat   = relay_ctrl|ch_num_dat|slot_en;
 		 sw_config_data[0] = (u8)(cpld_dat>>16);
 		 sw_config_data[1] = (u8)(cpld_dat>>8);
 		 sw_config_data[2] = (u8)(cpld_dat);
 		 xil_printf("relay_ctrl: %d\n\r", relay_ctrl);
 		 xil_printf("ch_num_dat: %d\n\r", ch_num_dat);
 		 xil_printf("cpld_addr: %d\n\r",  cpld_addr);
 		 xil_printf("cpld_dat: %d\n\r",   cpld_dat);
 		 xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[0]);
 		 xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[1]);
 		 xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[2]);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
 		 sw_config_data[0] = 0x00;
 		 sw_config_data[1] = 0x00;
 		 sw_config_data[2] = 0x01;
 		 spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U1);
 		 spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U2);
 		 spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U3);
 		 slot_en   = 0x00000000;
 		 cpld_dat   = relay_ctrl|ch_num_dat|slot_en;
 }
@@ -1,87 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 u8      cpld_addr = 0;
 		 u32     cpld_dat  = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(slot==1)
 		 {
 			 cpld_addr = 0x82;
 		 }
 		 else if(slot==2)
 		 {
 			 cpld_addr = 0x83;
 		 }
 		 else if(slot==3)
 		 {
 			 cpld_addr = 0x84;
 		 }
 		 else
 		 {
 			 cpld_addr = 0x85;
 		 }
 		 switch(ch_num)
 		 {
 		   case 0x0001:
 		 	   {
 		 		   relay_ctrl = 0x00000000;
 		 		   break;
 		 	   }
 		   case 0x0002:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		 }
 		 if(ch_num==1|ch_num==65|ch_num==129|ch_num==193)
 		 {
 			 relay_ctrl = 0x00000000;
 		 }
 		 if(ch_num>=1&&ch_num<=16)
 		  {
 		 	//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
 		 	fc_dv0_dat = (0x0001<<(ch_num-1));
 		 	fc_dv0_dat = ~fc_dv0_dat;
 		 	sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 		 	sw_config_data[1] = (u8)(fc_dv0_dat);
 		 	spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	//xil_printf("CPLD_U1:\n\r");
 		 	//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 		 	//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 		 }
 }
@@ -1,108 +0,0 @@
 /*
 * GPIO_Driv.c
 *
 *  Created on: 2021年5月7日
 *      Author: Administrator
 */
 #include "GPIO_Driv.h"
 XGpioPs psGpioInstancePtr;     //端口
 XGpioPs_Config* GpioConfigPtr; //设备ID
 					//sck,cs,sdi,sdo,rst
 u32 CPLD_U1  [11] = {54,55,56,57,58,59,60,61,62,63,64};
 u32 CPLD_U2  [11] = {65,66,67,68,69,70,71,72,73,74,75};
 u32 CPLD_U3  [11] = {76,77,78,79,80,81,82,83,84,85,86};
 void EMIO_config(void)
 {
 	    int xStatus;
 		GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
 		if(GpioConfigPtr == NULL)
 			return XST_FAILURE;
 		xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
 		if(XST_SUCCESS != xStatus)
 			print(" PS GPIO INIT FAILED \n\r");
 		/*-------------------------------------CPLD_U1------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 0);//57---sdo
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 1);//58---rst_n
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);//57---sdo
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);//58---rst_n
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//59
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//60
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//61
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//62
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//63
 		/*-------------------------------------CPLD_U2------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//68---sdo
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//69---rst_n
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//70
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//71
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//72
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//73
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//74
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);//68---sdo
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);//69---rst_n
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);//70
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);//71
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);//72
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);//73
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);//74
 		/*-------------------------------------CPLD_U3------------------------------------*/
 				//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//76---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//77---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//78---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 0);//79---sdo
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 1);//80---rst_n
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//81
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//82
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//83
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//84
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//85
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//76---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//77---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//78---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 1);//79---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 0);//80---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);//81
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);//82
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);//83
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);//84
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);//85
 }
@@ -1,63 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0xFF,0xFF,0xFF};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(m_fun==0x04)
 		 {
 			 //xil_printf("memt_areal: %d\n\r", memt_areal);
 			 if(memt_areal==0x01)
 			 {
 				 u1_io_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_io_rc_dat);
 				 spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
 				 //xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
 			 }
 			 else
 			 {
 				 u1_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_rc_dat);
 				 spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
 				// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
 			 }
 		 }
 		 if(ch_num>=1&&ch_num<=16)
 		  {
 		 	//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
 		 	fc_dv0_dat = (0x0001<<(ch_num-1));
 		 	fc_dv0_dat = ~fc_dv0_dat;
 		 	sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 		 	sw_config_data[1] = (u8)(fc_dv0_dat);
 		 	spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	//xil_printf("CPLD_U1:\n\r");
 		 	//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 		 	//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 		 }
 }
@@ -1,238 +0,0 @@
 /*
 * Copyright (C) 2009 - 2019 Xilinx, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
 * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
 * OF SUCH DAMAGE.
 *
 */
 #include <stdio.h>
 #include <string.h>
 #include "dna_read.h"
 #include "crc16.h"
 #include "GPIO_Driv.h"
 #include "SPI_Driv.h"
 #include "cal_meas.h"
 #include "lwip/err.h"
 #include "lwip/tcp.h"
 #if defined (__arm__) || defined (__aarch64__)
 #include "xil_printf.h"
 #endif
 char *recv_data;
 char dna_data[10];
 unsigned short recv_len;
 unsigned  read_dat = 0;
 char 	  dat_0[20] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
 unsigned  crc_read_dat = 0;
 char     crc_alg_dat[2] = {0,0};
 char     send_data_cpld1[2] = {0xAA,0x56};
 int transfer_data() {
 	return 0;
 }
 void print_app_header()
 {
 #if (LWIP_IPV6==0)
 	xil_printf("\n\r\n\r-----lwIP TCP echo server ------\n\r");
 #else
 	xil_printf("\n\r\n\r-----lwIPv6 TCP echo server ------\n\r");
 #endif
 	xil_printf("TCP packets sent to port 6001 will be echoed back\n\r");
 }
 err_t recv_callback(void *arg, struct tcp_pcb *tpcb,
                               struct pbuf *p, err_t err)
 {
 	/* do not read the packet if we are not in ESTABLISHED state */
 	if (!p) {
 		tcp_close(tpcb);
 		tcp_recv(tpcb, NULL);
 		return ERR_OK;
 	}
 	/* indicate that the packet has been received */
 	tcp_recved(tpcb, p->len);
 	/* echo back the payload */
 	/* in this case, we assume that the payload is < TCP_SND_BUF */
 	if (tcp_sndbuf(tpcb) > p->len) {
 		recv_len = p->len;
 		recv_data = (char*)malloc(sizeof(char)*recv_len);
 	    memcpy(recv_data,p->payload,recv_len);
 	    if(recv_data[6] == 0x0E)
 	    {
 	    	crc_read_dat = do_crc_table(recv_data+6, recv_len-8);
 	    	crc_alg_dat[0] = (u8)crc_read_dat;
 	    	crc_alg_dat[1] = (u8)(crc_read_dat>>8);
 	    	dat_0[0]= 0x00;
 	    	switch(recv_data[7])
 	    	{
 	    	  case 0xA2://SLOT
 	    	          {
 						  dat_0[1]= 0x06;
 						  dat_0[2]= recv_data[2];
 						  dat_0[3]= recv_data[3];
 						  dat_0[4]= recv_data[4];
 						  dat_0[5]= recv_data[5];
 						  dat_0[6]= recv_data[6];
 						  dat_0[7]= recv_data[7];
 	    	        	  if(recv_data[15]==crc_alg_dat[1]&&recv_data[16]==crc_alg_dat[0])
 	    	        	  {
 	    	        		  dat_0[8]= 0x01;
 	    	        		  dat_0[9]= 0x01;
 	    	        	  }
 	    	        	  else
 						  {
 							  dat_0[8]= 0xff;
 							  dat_0[9]= 0xff;
 						  }
 	    	        	  dat_0[10]= recv_data[15];
 	    	        	  dat_0[11]= recv_data[16];
 	    	        	  char slot_start[7] = {recv_data[8],recv_data[9],recv_data[10],recv_data[11],recv_data[12],recv_data[13],recv_data[14]};
 	    	        	  //xil_printf("slot_start[0]:%x, slot_start[1]:%x,slot_start[2]:%x,slot_start[3]:%x,slot_start[4]:%x,slot_start[5]:%x,slot_start[6]:%x\n\r", slot_start[0],slot_start[1],slot_start[2],slot_start[3],slot_start[4],slot_start[5],slot_start[6]);
 	    	        	  rst_CPLD(CPLD_U1,4);
 	    	        	  rst_CPLD(CPLD_U2,4);
 	    	        	  rst_CPLD(CPLD_U3,4);
 	    	        	  sw_config(slot_start);
 	    	        	  tcp_write(tpcb, dat_0, 12, 1);
 	    	        	  break;
 	    	          }
 	    	  case 0xA3://dna_port_read
 					  {
 						  dna_port_read(dna_data);
 						  dat_0[1]=0x0e;
 						  dat_0[2]=recv_data[2];
 						  dat_0[3]=recv_data[3];
 						  dat_0[4]=recv_data[4];
 						  dat_0[5]=recv_data[5];
 						  dat_0[6]=recv_data[6];
 						  dat_0[7]=recv_data[7];
 						  if(recv_data[8]==crc_alg_dat[1]&&recv_data[9]==crc_alg_dat[0])
 						  {
 							  dat_0[8]= 0x01;
 							  dat_0[9]= 0x01;
 						  }
 						  else
 						  {
 							  dat_0[8]= 0xff;
 							  dat_0[9]= 0xff;
 						  }
 						  dat_0[10]= dna_data[0];
 						  dat_0[11]= dna_data[1];
 						  dat_0[12]= dna_data[2];
 						  dat_0[13]= dna_data[3];
 						  dat_0[14]= dna_data[4];
 						  dat_0[15]= dna_data[5];
 						  dat_0[16]= dna_data[6];
 						  dat_0[17]= dna_data[7];
 						  dat_0[18]= recv_data[8];
 						  dat_0[19]= recv_data[9];
 						  tcp_write(tpcb, dat_0, 20, 1);
 						  break;
 					  }
 	    	}
 	    }
 	} else
 		xil_printf("no space in tcp_sndbuf\n\r");
 	/* free the received pbuf */
 	pbuf_free(p);
 	return ERR_OK;
 }
 err_t accept_callback(void *arg, struct tcp_pcb *newpcb, err_t err)
 {
 	static int connection = 1;
 	/* set the receive callback for this connection */
 	tcp_recv(newpcb, recv_callback);
 	/* just use an integer number indicating the connection id as the
 	   callback argument */
 	tcp_arg(newpcb, (void*)(UINTPTR)connection);
 	/* increment for subsequent accepted connections */
 	connection++;
 	return ERR_OK;
 }
 int start_application()
 {
 	struct tcp_pcb *pcb;
 	err_t err;
 	unsigned port = 200;
 	/* create new TCP PCB structure */
 	pcb = tcp_new_ip_type(IPADDR_TYPE_ANY);
 	if (!pcb) {
 		xil_printf("Error creating PCB. Out of Memory\n\r");
 		return -1;
 	}
 	/* bind to specified @port */
 	err = tcp_bind(pcb, IP_ANY_TYPE, port);
 	if (err != ERR_OK) {
 		xil_printf("Unable to bind to port %d: err = %d\n\r", port, err);
 		return -2;
 	}
 	/* we do not need any arguments to callback functions */
 	tcp_arg(pcb, NULL);
 	/* listen for connections */
 	pcb = tcp_listen(pcb);
 	if (!pcb) {
 		xil_printf("Out of memory while tcp_listen\n\r");
 		return -3;
 	}
 	/* specify callback to use for incoming connections */
 	tcp_accept(pcb, accept_callback);
 	xil_printf("TCP echo server started @ port %d\n\r", port);
 	return 0;
 }
@@ -1,79 +0,0 @@
 /*
 * GPIO_Driv.c
 *
 *  Created on: 2021年5月7日
 *      Author: Administrator
 */
 #include "GPIO_Driv.h"
 XGpioPs psGpioInstancePtr;     //端口
 XGpioPs_Config* GpioConfigPtr; //设备ID
 					//sck,cs,sdi,sdo,rst
 u32 CPLD_U1  [11] = {54,55,56,57,58,59,60,61,62,63,64};
 u32 CPLD_U2  [11] = {65,66,67,68,69,70,71,72,73,74,75};
 u32 CPLD_U3  [11] = {76,77,78,79,80,81,82,83,84,85,86};
 void EMIO_config(void)
 {
 	    int xStatus;
 		GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
 		if(GpioConfigPtr == NULL)
 			return XST_FAILURE;
 		xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
 		if(XST_SUCCESS != xStatus)
 			print(" PS GPIO INIT FAILED \n\r");
 		/*-------------------------------------CPLD_U1------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 1);//57---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 0);//58---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59---sdio3
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60---sdio4
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61---sdio5
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62---sdio6
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63---sdio7
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 1);//57---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 0);//58---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);
 		/*-------------------------------------CPLD_U2------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//61---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//62---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//63---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//64---sdo
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//65---rst
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66---sdio3
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67---sdio4
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67---sdio5
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67---sdio6
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67---sdio7
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
 }
@@ -1,558 +0,0 @@
 /*
 * SPI_Driv.c
 *
 *  Created on: 2021年4月2日
 *      Author: dell
 */
 #include "SPI_Driv.h"
 XGpioPs psGpioInstancePtr;     //端口
 XGpioPs_Config* GpioConfigPtr; //设备ID
 extern u32 K7_U0[16];
 extern u32 molex_4_bank_3[4];
 extern u32 cs_en_bank_3[4];
 /******************************************************************************
 * Function    : void interface_initial(u32* device,u32 num_wire)
 * Description : interface initial
 * Parameter   : device   -- CPLD
 * 				num_wire -- 复位线编号
 * Return      : void
 ******************************************************************************/
 void interface_initial(u32* device)  //wire_num = cs sck sdi/o
 {
 	u32   sck   = *(device+0);
 	u32	  cs    = *(device+1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
 }
 /******************************************************************************
 * Function    : void rst_CPLD(u32* device,u32 num_wire)
 * Description : CPLD reset
 * Parameter   : device   -- CPLD
 * 				num_wire -- 复位线编号
 * Return      : void
 ******************************************************************************/
 void rst_CPLD(u32* device,u32 num_wire) //wire_num = cs sck sdi/o
 {
 	u32	rst_n = *(device+num_wire);
 	XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
 	usleep(2);
 	XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
 }
 /******************************************************************************
 * Function    : void spi_write_onewire(char addr, u32 data, char width, u32* device)
 * Description : spi onewire write
 * Parameter   : addr   -- 地址
 * 				data   -- 数据
 * 				width  -- 数据长度
 * 				device -- CPLD
 * Return      : void
 ******************************************************************************/
 void spi_write_onewire(char addr, char *data, char width, u32* device)
 {
 	char  temp_addr = 0;
 	//u32   temp_data = 0;
 	u32   temp_data = 0;
 	char  i = 0,j=0;
 	u32   sck = *(device+0);
 	u32	  cs= *(device+1);
 	u32   sdi= *(device+2);
 	temp_addr = addr;
 	///temp_data = data;
 	//XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs,  0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs,  0);
 	//XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1);			// w/r标志位    1=w 0=r
 	//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	for(i = 0; i < 8; i++)								// 8bit地址
 	{
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	    if(temp_addr&0x80)
 	    	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据     数据从中间变量到通信线上
 	    else
 	    	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    temp_addr = temp_addr<<1;                       //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
 	}
 	for(j=0;j<width;j++)
 	{
 		temp_data = *(data+j);
 		for(i = 0; i < 8; i++)                             //nbit数据
 		{
 			XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 			XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 			if(temp_data&0x80)							//注意数据位nbit，要从[n-1]取位
 				XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1);
 			else
 				XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 			XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 			XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 			temp_data <<=  1;
 		}
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	}
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs , 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 }
 /******************************************************************************
 * Function    : u32	spi_read_onewire(char addr, char width, u32* device)
 * Description : spi onewire read
 * Parameter   : addr   -- 地址
 * 				data   -- 数据
 * 				width  -- 数据长度
 * 				device -- CPLD
 * Return      : void
 ******************************************************************************/
 u32	spi_read_onewire(char addr, char width, u32* device,char* read_data)
 {
 	char  temp_addr=0;
 	u32	  temp_data=0;
 	char  i=0,j=0;
 	u32   sck = *(device+0);
 	u32	  cs= *(device+1);
 	u32   sdi= *(device+2);
 	u32   sdo= *(device+3);
 	temp_addr = addr;
 	//XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	//XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);		// w/r标志位    1=w 0=r
 	//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	for(i = 0; i < 8; i++)								// 8bit地址
 	{
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	    if(temp_addr&0x80)
 	    	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据     数据从中间变量到通信线上
 	    else
 	    	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    temp_addr = temp_addr<<1;                       //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
 	}
 	for(j=0; j<width; j++)
 	{
 			for(i = 0; i < 8; i++)                             //nbit数据
 			{
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 				temp_data = temp_data << 1;                     //sck低电平准备数据    准备好数位，此时的数据相当于从右边的FPGA移进MCU(先准备好中间变量)
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 				if(XGpioPs_ReadPin(&psGpioInstancePtr,sdo))    //sck高电平接收数据     数据匹配到准备好的数位，等待一起传递到MCU
 					temp_data = temp_data| 0x00000001;
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 			    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 			}
 	}
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 	read_data[0] = (u8)(temp_data>>16);
 	read_data[1] = (u8)(temp_data>>8);
 	read_data[0] = (u8)(temp_data);
 	return temp_data;
 }
 /******************************************************************************
 * Function    : void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
 * Description : forwire write to reg
 * Parameter   : txdata--数据
 * 				sdi0,sdi1,sdi2,sdi3--IO
 * Return      : void
 ******************************************************************************/
 void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
 {
 	switch(txdata & 0x0F)
 	{
 	   case 0x00:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x01:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x02:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x03:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x04:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x05:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x06:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x07:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x08:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x09:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0A:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0B:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0C:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0D:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0E:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0F:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	}
 }
 /******************************************************************************
 * Function    : void spi_write_fourwire(char addr, u16 data, u32* device)
 * Description : spi fourwire write
 * Parameter   : addr   -- 地址
 * 				data   -- 数据
 * 				width  -- 数据长度
 *  				device -- CPLD
 * Return      : void
 ******************************************************************************/
 void spi_write_fourwire(char addr, u16 data, u32* device)
 {
 	u8    temp_addr = 0;
 	u16   temp_data = 0;
 	u8	  split_addr[2] = {0};	//将8bit地址拆分，分别给4线传输，
 	u8	  split_data[4] = {0};	//16bit数据拆成4个4bit
 	u8    i;
 	u32   sck   = *(device+0);
 	u32	  cs    = *(device+1);
 	u32	  sdi0 = *(device+2);
 	u32	  sdi1 = *(device+3);
 	u32	  sdi2 = *(device+4);
 	u32	  sdi3 = *(device+5);
 	temp_addr = addr;
 	temp_data = data;
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	fourwire_write(0x01,sdi0,sdi1,sdi2,sdi3);     			// w/r标志位    1=w 0=r
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	for(i = 0; i < 2;i++)									// 8bit地址 四根线分两次传输
 	{
 		split_addr[i] = (temp_addr>>(4*(1-i)))&0x0F;		//sck高电平准备数据		数据从MCU到中间变量上
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		fourwire_write(split_addr[i],sdi0,sdi1,sdi2,sdi3);	//sck低电平传输数据     数据从中间变量到通信线上
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	}
 	for(i = 0; i < 4;i++)									//16bit数据  4根线分四次传输
 	{
 		split_data[i] = (temp_data>>(4*(3-i)))&0x0F;
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		fourwire_write(split_data[i],sdi0,sdi1,sdi2,sdi3);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	}
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
    fourwire_write(0x00,sdi0,sdi1,sdi2,sdi3);
    //usleep(20);
 }
 /******************************************************************************
 * Function    : u16	fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
 * Description : forwire read from reg
 * Parameter   : sdo0,sdo1,sdo2,sdo3--IO
 * Return      : rxdata--数据
 ******************************************************************************/
 u16	fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
 {
 	u32 GPIO_PIN[4];
 	u16	rdata[4];
 	u16 rxdata = 0;
 	GPIO_PIN[0] = sdo0;
 	GPIO_PIN[1] = sdo1;
 	GPIO_PIN[2] = sdo2;
 	GPIO_PIN[3] = sdo3;
 	for(u8 i = 0; i < 4 ; i++)
 	{
 		rdata[i] = XGpioPs_ReadPin(&psGpioInstancePtr,GPIO_PIN[i]);
 		//xil_printf("rdata[i] = %x\r\n",rdata[i]);
 		rxdata   = ((rdata[i])<<i) + rxdata ;
 	}
 	return	rxdata;
 }
 /******************************************************************************
 * Function    : void spi_read_fourwire(char addr, u16* rxdata, u32* device)
 * Description : spi fourwire read
 * Parameter   : addr   -- 地址
 * 				rxdata -- 数据
 * 				device -- CPLD
 * Return      : void
 ******************************************************************************/
 void spi_read_fourwire(char addr, u16* rxdata, u32* device)   //接收数据使用指针传递，方便接收多个
 {
 	u8    temp_addr = 0;
 	u16   temp_data = 0;
 	u8	  split_addr[2] = {0};	//将8bit地址拆分，分别给4线传输，
 	u16	  split_data[4] = {0};	//16bit数据拆成4个4bit
 	u8    i = 0;
 	u32   sck   = *(device+0);
 	u32	  cs    = *(device+1);
 	u32	  sdio0 = *(device+2);
 	u32	  sdio1 = *(device+3);
 	u32	  sdio2 = *(device+4);
 	u32	  sdio3 = *(device+5);
 	temp_addr = addr;
 	split_addr[0] = (temp_addr >> 4)&0x0F;
 	split_addr[1] = (temp_addr)&0x0F;
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3);     			// w/r标志位    1=w 0=r
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	for(i = 0; i < 2; i++)									// 8bit地址 四根线分两次传输
 	{
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		fourwire_write(split_addr[i],sdio0,sdio1,sdio2,sdio3);	//sck低电平传输数据     数据从中间变量到通信线上
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	}
 	for(i = 0; i < 4; i++)
 	{
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),0);  //input
 	}
 	for(i = 0; i < 4; i++)									//16bit数据  4根线分四次接收
 	{
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		split_data[i] = fourwire_read(sdio0,sdio1,sdio2,sdio3);	//sck低电平准备数据     数据从通信线到中间变量上
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    temp_data = temp_data<<4;
 	    temp_data = temp_data + split_data[i];
 		//temp_data = (split_data[i]<<(4*(3-i))) + temp_data;		//sck高电平接收数据     数据从中间变量到MCU上
 //	    xil_printf("split_data[i],temp_data = %x,%x\r\n",split_data[i],temp_data);
 	}
 	for(i = 0; i < 4; i++)
 	{
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),1);  //output
 	}
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3);
 	*rxdata = temp_data;
    XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
    XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
    XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);//add 2 lines
    //usleep(20);
 }
 /******************************************************************************
 * Function    : void GPIO_dir_set(u32* device,char dir)
 * Description : change GPIO direction
 * Parameter   : device -- CPLD
 * 				dir    -- GPIO_OUT/GPIO_IN
 * Return      : void
 ******************************************************************************/
 void GPIO_dir_set_16(u32* device,char dir)
 {
 	u32   sdio[16] = {0};
 	u8    i;
 	for(i = 0; i < 16;i++)
 	{
 		sdio[i] = *(device+i);
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, sdio[i],1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir);
 	}
 }
 void GPIO_dir_set_cs_enable(u32* device,u8 dir)
 {
 	u32   sdio[4] = {0};
 	u8    i;
 	u8    dir_temp = 0;
 	for(i = 0; i < 4;i++)
 	{
 		sdio[i]  = *(device+i);
 		dir_temp =  (((dir >> (3-i))) & 0x01);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir_temp);
 	}
 }
 void  rst(char *d)
 {
 	XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, *d, 1);
 	usleep(20);
 	XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
 }
 void func_test(void)
 {
 	XGpioPs_Write(&psGpioInstancePtr, 0x03, 0x12345678);
 }
@@ -1,68 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 u32     cpld_dat = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(m_fun==0x04)
 		 {
 			 //xil_printf("memt_areal: %d\n\r", memt_areal);
 			 if(memt_areal==0x01)
 			 {
 				 u1_io_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_io_rc_dat);
 				 spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
 				 //xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
 			 }
 			 else
 			 {
 				 u1_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_rc_dat);
 				 spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
 				// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
 			 }
 		 }
 		 if(ch_num>=1&&ch_num<=16)
 		  {
 		 	//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
 		 	fc_dv0_dat = (0x0001<<(ch_num-1));
 		 	fc_dv0_dat = ~fc_dv0_dat;
 		 	sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 		 	sw_config_data[1] = (u8)(fc_dv0_dat);
 		 	spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	//xil_printf("CPLD_U1:\n\r");
 		 	//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 		 	//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 		 }
 }
@@ -1,87 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 u8      cpld_addr = 0;
 		 u32     cpld_dat  = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(slot==1)
 		 {
 			 cpld_addr = 0x82;
 		 }
 		 else if(slot==2)
 		 {
 			 cpld_addr = 0x83;
 		 }
 		 else if(slot==3)
 		 {
 			 cpld_addr = 0x84;
 		 }
 		 else
 		 {
 			 cpld_addr = 0x85;
 		 }
 		 if(m_fun==0x04)
 		 {
 			 //xil_printf("memt_areal: %d\n\r", memt_areal);
 			 if(memt_areal==0x01)
 			 {
 				 u1_io_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_io_rc_dat);
 				 spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
 				 //xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
 			 }
 			 else
 			 {
 				 u1_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_rc_dat);
 				 spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
 				// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
 			 }
 		 }
 		 if(ch_num>=1&&ch_num<=16)
 		  {
 		 	//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
 		 	fc_dv0_dat = (0x0001<<(ch_num-1));
 		 	fc_dv0_dat = ~fc_dv0_dat;
 		 	sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 		 	sw_config_data[1] = (u8)(fc_dv0_dat);
 		 	spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	//xil_printf("CPLD_U1:\n\r");
 		 	//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 		 	//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 		 }
 }
@@ -1,244 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 u8      cpld_addr = 0;
 		 u32     cpld_dat  = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(slot==1)
 		 {
 			 cpld_addr = 0x82;
 		 }
 		 else if(slot==2)
 		 {
 			 cpld_addr = 0x83;
 		 }
 		 else if(slot==3)
 		 {
 			 cpld_addr = 0x84;
 		 }
 		 else
 		 {
 			 cpld_addr = 0x85;
 		 }
 		 switch(ch_num)
 		 {
 		   case 0x0001:
 		 	   {
 		 		   relay_ctrl = 0x00000000;
 		 		   break;
 		 	   }
 		   case 0x0002:
 		   	   {
 		   		   relay_ctrl = 0x00020000;
 		   		   break;
 		   	   }
 		   case 0x0003:
 		   	   {
 		   		   relay_ctrl = 0x00200000;
 		   		   break;
 		   	   }
 		   case 0x0004:
 		   	   {
 		   		   relay_ctrl = 0x00220000;
 		   		   break;
 		   	   }
 		   case 0x0005:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0006:
 		   	   {
 		   		   relay_ctrl = 0x00810000;
 		   		   break;
 		   	   }
 		   case 0x0007:
 		   	   {
 		   		   relay_ctrl = 0x00A00000;
 		   		   break;
 		   	   }
 		   case 0x0008:
 		   	   {
 		   		   relay_ctrl = 0x00A10000;
 		   		   break;
 		   	   }
 		   case 0x0041:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0042:
 		   	   {
 		   		   relay_ctrl = 0x00008000;
 		   		   break;
 		   	   }
 		   case 0x0043:
 		   	   {
 		   		   relay_ctrl = 0x00100000;
 		   		   break;
 		   	   }
 		   case 0x0044:
 		   	   {
 		   		   relay_ctrl = 0x00108000;
 		   		   break;
 		   	   }
 		   case 0x0045:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0046:
 		   	   {
 		   		   relay_ctrl = 0x00804000;
 		   		   break;
 		   	   }
 		   case 0x0047:
 		   	   {
 		   		   relay_ctrl = 0x00900000;
 		   		   break;
 		   	   }
 		   case 0x0048:
 		   	   {
 		   		   relay_ctrl = 0x00904000;
 		   		   break;
 		   	   }
 		   case 0x0081:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0082:
 		   	   {
 		   		   relay_ctrl = 0x00002000;
 		   		   break;
 		   	   }
 		   case 0x0083:
 		   	   {
 		   		   relay_ctrl = 0x00080000;
 		   		   break;
 		   	   }
 		   case 0x0084:
 		   	   {
 		   		   relay_ctrl = 0x00082000;
 		   		   break;
 		   	   }
 		   case 0x0085:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x0086:
 		   	   {
 		   		   relay_ctrl = 0x00401000;
 		   		   break;
 		   	   }
 		   case 0x0087:
 		   	   {
 		   		   relay_ctrl = 0x00480000;
 		   		   break;
 		   	   }
 		   case 0x0088:
 		   	   {
 		   		   relay_ctrl = 0x00481000;
 		   		   break;
 		   	   }
 		   case 0x00C1:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x00C2:
 		   	   {
 		   		   relay_ctrl = 0x00000800;
 		   		   break;
 		   	   }
 		   case 0x00C3:
 		   	   {
 		   		   relay_ctrl = 0x00040000;
 		   		   break;
 		   	   }
 		   case 0x00C4:
 		   	   {
 		   		   relay_ctrl = 0x00040800;
 		   		   break;
 		   	   }
 		   case 0x00C5:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x00C6:
 		   	   {
 		   		   relay_ctrl = 0x00400400;
 		   		   break;
 		   	   }
 		   case 0x00C7:
 		   	   {
 		   		   relay_ctrl = 0x00440000;
 		   		   break;
 		   	   }
 		   case 0x00C8:
 		   	   {
 		   		   relay_ctrl = 0x00440400;
 		   		   break;
 		   	   }
 		 }
 		 ch_num_dat = ((u32)ch_num)<<1;
 		 cpld_dat   = relay_ctrl|ch_num_dat|slot_en;
 		 sw_config_data[0] = (u8)(cpld_dat>>16);
 		 sw_config_data[1] = (u8)(cpld_dat>>8);
 		 sw_config_data[2] = (u8)(cpld_dat);
 		 xil_printf("relay_ctrl: %d\n\r", relay_ctrl);
 		 xil_printf("ch_num_dat: %d\n\r", ch_num_dat);
 		 xil_printf("cpld_addr: %d\n\r",  cpld_addr);
 		 xil_printf("cpld_dat: %d\n\r",   cpld_dat);
 		 xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[0]);
 		 xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[1]);
 		 xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[2]);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
 		 sw_config_data[0] = 0x00;
 		 sw_config_data[1] = 0x00;
 		 sw_config_data[2] = 0x01;
 		 spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U1);
 		 spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U2);
 		 spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U3);
 }
@@ -1,241 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 u8      cpld_addr = 0;
 		 u32     cpld_dat  = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(slot==1)
 		 {
 			 cpld_addr = 0x82;
 		 }
 		 else if(slot==2)
 		 {
 			 cpld_addr = 0x83;
 		 }
 		 else if(slot==3)
 		 {
 			 cpld_addr = 0x84;
 		 }
 		 else
 		 {
 			 cpld_addr = 0x85;
 		 }
 		 switch(ch_num)
 		 {
 		   case 0x0001:
 		 	   {
 		 		   relay_ctrl = 0x00000000;
 		 		   break;
 		 	   }
 		   case 0x0002:
 		   	   {
 		   		   relay_ctrl = 0x00020000;
 		   		   break;
 		   	   }
 		   case 0x0003:
 		   	   {
 		   		   relay_ctrl = 0x00200000;
 		   		   break;
 		   	   }
 		   case 0x0004:
 		   	   {
 		   		   relay_ctrl = 0x00220000;
 		   		   break;
 		   	   }
 		   case 0x0005:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0006:
 		   	   {
 		   		   relay_ctrl = 0x00810000;
 		   		   break;
 		   	   }
 		   case 0x0007:
 		   	   {
 		   		   relay_ctrl = 0x00A00000;
 		   		   break;
 		   	   }
 		   case 0x0008:
 		   	   {
 		   		   relay_ctrl = 0x00A10000;
 		   		   break;
 		   	   }
 		   case 0x0041:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0042:
 		   	   {
 		   		   relay_ctrl = 0x00008000;
 		   		   break;
 		   	   }
 		   case 0x0043:
 		   	   {
 		   		   relay_ctrl = 0x00100000;
 		   		   break;
 		   	   }
 		   case 0x0044:
 		   	   {
 		   		   relay_ctrl = 0x00108000;
 		   		   break;
 		   	   }
 		   case 0x0045:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0046:
 		   	   {
 		   		   relay_ctrl = 0x00804000;
 		   		   break;
 		   	   }
 		   case 0x0047:
 		   	   {
 		   		   relay_ctrl = 0x00900000;
 		   		   break;
 		   	   }
 		   case 0x0048:
 		   	   {
 		   		   relay_ctrl = 0x00904000;
 		   		   break;
 		   	   }
 		   case 0x0081:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0082:
 		   	   {
 		   		   relay_ctrl = 0x00002000;
 		   		   break;
 		   	   }
 		   case 0x0083:
 		   	   {
 		   		   relay_ctrl = 0x00080000;
 		   		   break;
 		   	   }
 		   case 0x0084:
 		   	   {
 		   		   relay_ctrl = 0x00082000;
 		   		   break;
 		   	   }
 		   case 0x0085:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x0086:
 		   	   {
 		   		   relay_ctrl = 0x00401000;
 		   		   break;
 		   	   }
 		   case 0x0087:
 		   	   {
 		   		   relay_ctrl = 0x00480000;
 		   		   break;
 		   	   }
 		   case 0x0088:
 		   	   {
 		   		   relay_ctrl = 0x00481000;
 		   		   break;
 		   	   }
 		   case 0x00C1:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x00C2:
 		   	   {
 		   		   relay_ctrl = 0x00000800;
 		   		   break;
 		   	   }
 		   case 0x00C3:
 		   	   {
 		   		   relay_ctrl = 0x00040000;
 		   		   break;
 		   	   }
 		   case 0x00C4:
 		   	   {
 		   		   relay_ctrl = 0x00040800;
 		   		   break;
 		   	   }
 		   case 0x00C5:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x00C6:
 		   	   {
 		   		   relay_ctrl = 0x00400400;
 		   		   break;
 		   	   }
 		   case 0x00C7:
 		   	   {
 		   		   relay_ctrl = 0x00440000;
 		   		   break;
 		   	   }
 		   case 0x00C8:
 		   	   {
 		   		   relay_ctrl = 0x00440400;
 		   		   break;
 		   	   }
 		 }
 		 xil_printf("relay_ctrl: %d\n\r", relay_ctrl);
 		 xil_printf("ch_num_dat: %d\n\r", ch_num_dat);
 		 ch_num_dat = ((u32)ch_num)<<1;
 		 cpld_dat   = relay_ctrl|ch_num_dat|slot_en;
 		 sw_config_data[0] = (u8)(cpld_dat>>16);
 		 sw_config_data[1] = (u8)(cpld_dat>>8);
 		 sw_config_data[2] = (u8)(cpld_dat);
 		 xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[0]);
 		 xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[1]);
 		 xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[2]);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
 		 sw_config_data[0] = 0x00;
 		 sw_config_data[1] = 0x00;
 		 sw_config_data[2] = 0x01;
 		 spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U1);
 		 spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U2);
 		 spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U3);
 }
@@ -1,68 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(m_fun==0x04)
 		 {
 			 //xil_printf("memt_areal: %d\n\r", memt_areal);
 			 if(memt_areal==0x01)
 			 {
 				 u1_io_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_io_rc_dat);
 				 spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
 				 //xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
 			 }
 			 else
 			 {
 				 u1_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_rc_dat);
 				 spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
 				// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
 			 }
 		 }
 		 if(ch_num>=1&&ch_num<=16)
 		  {
 		 	//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
 		 	fc_dv0_dat = (0x0001<<(ch_num-1));
 		 	fc_dv0_dat = ~fc_dv0_dat;
 		 	sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 		 	sw_config_data[1] = (u8)(fc_dv0_dat);
 		 	spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	//xil_printf("CPLD_U1:\n\r");
 		 	//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 		 	//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 		 }
 }
@@ -1,108 +0,0 @@
 /*
 * GPIO_Driv.c
 *
 *  Created on: 2021年5月7日
 *      Author: Administrator
 */
 #include "GPIO_Driv.h"
 XGpioPs psGpioInstancePtr;     //端口
 XGpioPs_Config* GpioConfigPtr; //设备ID
 					//sck,cs,sdi,sdo,rst
 u32 CPLD_U1  [11] = {54,55,56,57,58,59,60,61,62,63,64};
 u32 CPLD_U2  [11] = {65,66,67,68,69,70,71,72,73,74,75};
 u32 CPLD_U3  [11] = {76,77,78,79,80,81,82,83,84,85,86};
 void EMIO_config(void)
 {
 	    int xStatus;
 		GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
 		if(GpioConfigPtr == NULL)
 			return XST_FAILURE;
 		xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
 		if(XST_SUCCESS != xStatus)
 			print(" PS GPIO INIT FAILED \n\r");
 		/*-------------------------------------CPLD_U1------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 0);//57---sdo
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 1);//58---rst_n
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 1);//57---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 0);//58---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//59
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//60
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//61
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//62
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//63
 		/*-------------------------------------CPLD_U2------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 1);//68---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 0);//69---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//70
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//71
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//72
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//73
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//74
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 1);//68---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 0);//69---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);//70
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);//71
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);//72
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);//73
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);//74
 		/*-------------------------------------CPLD_U3------------------------------------*/
 				//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//76---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//77---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//78---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 1);//79---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 0);//80---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//81
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//82
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//83
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//84
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//85
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//76---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//77---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//78---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 1);//79---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 0);//80---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);//81
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);//82
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);//83
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);//84
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);//85
 }
@@ -1,84 +0,0 @@
 /*
 * cal_meas.h
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #ifndef SRC_CAL_MEAS_H_
 #define SRC_CAL_MEAS_H_
 #include "sleep.h"
 #include "stdio.h"
 #include "xgpiops.h"
 #include "SPI_Driv.h"
 #include "GPIO_Driv.h"
 //reg addr(CPLD_U1)
 #define     U1_SW_FC_DV0  1
 #define     U1_SW_FC_DV1  2
 #define     U1_SW_FC_DV2  3
 #define     U1_SW_FC_DV3  4
 #define     U1_SW_SC_DV0  5
 #define     U1_SW_SC_DV1  6
 #define     U1_SW_SC_DV2  7
 #define     U1_SW_SC_DV3  8
 #define     U1_SW_OC_DV0  9
 #define     U1_SW_OC_DV1  10
 #define     U1_SW_OC_DV2  11
 #define     U1_SW_OC_DV3  12
 #define     U1_SW_OC_DV4  13
 #define     U1_SW_OC_DV5  14
 #define     U1_SW_OC_DV6  15
 #define     U1_SW_OC_DV7  16
 #define     U1_SW_FMC_SMC  17
 #define     U1_SW_OC_DMM   18
 #define     U1_SW_MMC      19
 #define     U1_SW_RC       20
 #define     U1_SW_IO_RC    21
 #define     U1_SW_RL1      22
 #define     U1_SW_RL2      23
 #define     U1_SW_LOFS_VPK 24
 #define     U1_SW_LOFS_APK 25
 //reg addr(CPLD_U2)
 #define     U2_SW_FC_DV0  1
 #define     U2_SW_FC_DV1  2
 #define     U2_SW_FC_DV2  3
 #define     U2_SW_FC_DV3  4
 #define     U2_SW_SC_DV0  5
 #define     U2_SW_SC_DV1  6
 #define     U2_SW_SC_DV2  7
 #define     U2_SW_SC_DV3  8
 #define     U2_SW_OC_DV0  9
 #define     U2_SW_OC_DV1  10
 #define     U2_SW_OC_DV2  11
 #define     U2_SW_OC_DV3  12
 #define     U2_SW_OC_DV4  13
 #define     U2_SW_OC_DV5  14
 #define     U2_SW_OC_DV6  15
 #define     U2_SW_OC_DV7  16
 #define     dat_width  3
 void  sw_init( void );
 void  sw_config(char *slot_start);
 void  fsmc_mmc_config(char slot,char m_fun);
 void  dmm_config(char slot, u16 ch_num);
 void  rc_config(char m_fun);
 void  fsc_oc_config(char slot,char m_fun, u16 ch_num);
 void  rl_config(char load);
 #endif /* SRC_CAL_MEAS_H_ */
@@ -1,97 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 u8      cpld_addr = 0;
 		 u32     cpld_dat  = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(slot==1)
 		 {
 			 cpld_addr = 0x82;
 		 }
 		 else if(slot==2)
 		 {
 			 cpld_addr = 0x83;
 		 }
 		 else if(slot==3)
 		 {
 			 cpld_addr = 0x84;
 		 }
 		 else
 		 {
 			 cpld_addr = 0x85;
 		 }
 		 switch(ch_num)
 		 {
 		   case 0x0001:
 		 	   {
 		 		   relay_ctrl = 0x00000000;
 		 		   break;
 		 	   }
 		   case 0x0002:
 		   	   {
 		   		   relay_ctrl = 0x00020000;
 		   		   break;
 		   	   }
 		   case 0x0003:
 		   	   {
 		   		   relay_ctrl = 0x00200000;
 		   		   break;
 		   	   }
 		   case 0x0004:
 		   	   {
 		   		   relay_ctrl = 0x00020000;
 		   		   break;
 		   	   }
 		 }
 		 if(ch_num==1|ch_num==65|ch_num==129|ch_num==193)
 		 {
 			 relay_ctrl = 0x00000000;
 		 }
 		 if(ch_num>=1&&ch_num<=16)
 		  {
 		 	//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
 		 	fc_dv0_dat = (0x0001<<(ch_num-1));
 		 	fc_dv0_dat = ~fc_dv0_dat;
 		 	sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 		 	sw_config_data[1] = (u8)(fc_dv0_dat);
 		 	spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	//xil_printf("CPLD_U1:\n\r");
 		 	//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 		 	//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 		 }
 }
@@ -1,219 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 u8      cpld_addr = 0;
 		 u32     cpld_dat  = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 ch_num_dat = ((u32)ch_num)<<1;
 		 cpld_dat  = relay_ctrl|ch_num_dat|slot_en;
 		 if(slot==1)
 		 {
 			 cpld_addr = 0x82;
 		 }
 		 else if(slot==2)
 		 {
 			 cpld_addr = 0x83;
 		 }
 		 else if(slot==3)
 		 {
 			 cpld_addr = 0x84;
 		 }
 		 else
 		 {
 			 cpld_addr = 0x85;
 		 }
 		 switch(ch_num)
 		 {
 		   case 0x0001:
 		 	   {
 		 		   relay_ctrl = 0x00000000;
 		 		   break;
 		 	   }
 		   case 0x0002:
 		   	   {
 		   		   relay_ctrl = 0x00020000;
 		   		   break;
 		   	   }
 		   case 0x0003:
 		   	   {
 		   		   relay_ctrl = 0x00200000;
 		   		   break;
 		   	   }
 		   case 0x0004:
 		   	   {
 		   		   relay_ctrl = 0x00022000;
 		   		   break;
 		   	   }
 		   case 0x0005:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0006:
 		   	   {
 		   		   relay_ctrl = 0x00810000;
 		   		   break;
 		   	   }
 		   case 0x0007:
 		   	   {
 		   		   relay_ctrl = 0x00A00000;
 		   		   break;
 		   	   }
 		   case 0x0008:
 		   	   {
 		   		   relay_ctrl = 0x00A10000;
 		   		   break;
 		   	   }
 		   case 0x0041:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0042:
 		   	   {
 		   		   relay_ctrl = 0x00008000;
 		   		   break;
 		   	   }
 		   case 0x0043:
 		   	   {
 		   		   relay_ctrl = 0x00100000;
 		   		   break;
 		   	   }
 		   case 0x0044:
 		   	   {
 		   		   relay_ctrl = 0x00108000;
 		   		   break;
 		   	   }
 		   case 0x0045:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0046:
 		   	   {
 		   		   relay_ctrl = 0x00804000;
 		   		   break;
 		   	   }
 		   case 0x0047:
 		   	   {
 		   		   relay_ctrl = 0x00900000;
 		   		   break;
 		   	   }
 		   case 0x0048:
 		   	   {
 		   		   relay_ctrl = 0x00904000;
 		   		   break;
 		   	   }
 		   case 0x0081:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0082:
 		   	   {
 		   		   relay_ctrl = 0x00002000;
 		   		   break;
 		   	   }
 		   case 0x0083:
 		   	   {
 		   		   relay_ctrl = 0x00080000;
 		   		   break;
 		   	   }
 		   case 0x0084:
 		   	   {
 		   		   relay_ctrl = 0x00082000;
 		   		   break;
 		   	   }
 		   case 0x0085:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x0086:
 		   	   {
 		   		   relay_ctrl = 0x00401000;
 		   		   break;
 		   	   }
 		   case 0x0087:
 		   	   {
 		   		   relay_ctrl = 0x00480000;
 		   		   break;
 		   	   }
 		   case 0x0088:
 		   	   {
 		   		   relay_ctrl = 0x00481000;
 		   		   break;
 		   	   }
 		   case 0x00C1:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x00C2:
 		   	   {
 		   		   relay_ctrl = 0x00000800;
 		   		   break;
 		   	   }
 		   case 0x00C3:
 		   	   {
 		   		   relay_ctrl = 0x00040000;
 		   		   break;
 		   	   }
 		   case 0x00C4:
 		   	   {
 		   		   relay_ctrl = 0x00040800;
 		   		   break;
 		   	   }
 		   case 0x00C5:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x00C6:
 		   	   {
 		   		   relay_ctrl = 0x00400400;
 		   		   break;
 		   	   }
 		   case 0x00C7:
 		   	   {
 		   		   relay_ctrl = 0x00440000;
 		   		   break;
 		   	   }
 		   case 0x00C8:
 		   	   {
 		   		   relay_ctrl = 0x00440400;
 		   		   break;
 		   	   }
 		 }
 }
@@ -1,286 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0xFF,0xFF,0xFF};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16     u1_io_rc_dat = 0;
 		 u16     u1_rc_dat = 0;
 		 u16     u1_lofs_vpk_dat = 0;
 		 u16     u1_lofs_apk_dat = 0;
 		 u16     u1_lofs_vpk_apk_dat = 0;
 		 u16 	 ch_num = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 //xil_printf("slot: %d\n\r", slot);
 		 //xil_printf("m_fun: %d\n\r", m_fun);
 		 //xil_printf("ch_num: %d\n\r", ch_num);
 		 fsc_oc_config(slot,m_fun,ch_num);
 		 if(m_fun==0x04)
 		 {
 			 dmm_config(slot,ch_num);
 			 //xil_printf("memt_areal: %d\n\r", memt_areal);
 			 if(memt_areal==0x01)
 			 {
 				 u1_io_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_io_rc_dat);
 				 spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
 				 //xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
 			 }
 			 else
 			 {
 				 u1_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_rc_dat);
 				 spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
 				// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
 			 }
 		 }
 }
 void  dmm_config(char slot, u16 ch_num)
 {
 	u16   sw_oc_dmm_dat = 0;
 	if(ch_num>=1&&ch_num<=64)
 	{
 		sw_oc_dmm_dat = (0x0001<<((slot-1)*4));
 		sw_oc_dmm_dat = ~sw_oc_dmm_dat;
 	}
 	else if(ch_num>=65&&ch_num<=128)
 	{
 		sw_oc_dmm_dat = (0x0001<<((slot-1)*4+1));
 		sw_oc_dmm_dat = ~sw_oc_dmm_dat;
 	}
 	else if(ch_num>=129&&ch_num<=192)
 	{
 		sw_oc_dmm_dat = (0x0001<<((slot-1)*4+2));
 		sw_oc_dmm_dat = ~sw_oc_dmm_dat;
 	}
 	else
 	{
 		sw_oc_dmm_dat = (0x0001<<((slot-1)*4+3));
 		sw_oc_dmm_dat = ~sw_oc_dmm_dat;
 	}
 	//xil_printf("oc_dmm_dat: %x\n\r", sw_oc_dmm_dat);
 	sw_config_data[0] = (u8)(sw_oc_dmm_dat>>8);
 	sw_config_data[1] = (u8)(sw_oc_dmm_dat);
 	spi_write_onewire(U1_SW_OC_DMM, sw_config_data, dat_width, CPLD_U1);
 }
 void  rc_config(char m_fun)
 {
 	u16     rc_dat = 0;
 	switch(m_fun)
 	{
 	   case 0x01:
 	   {
 		   rc_dat = 0xFFFD;
 		   break;
 	   }
 	   case 0x02:
 	   {
 		   rc_dat = 0xFFFB;
 		   break;
 	   }
 	   case 0x03:
 	   {
 		   rc_dat = 0xFFF9;
 		   break;
 	   }
 	}
 	//xil_printf("rc_dat: %x\n\r", rc_dat);
 	sw_config_data[0] = (u8)(rc_dat>>8);
 	sw_config_data[1] = (u8)(rc_dat);
 	spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
 }
 void  rl_config(char load)
 {
 	u16 rl_dat = 0;
 	if(load>=1&&load<=9)
 	{
 		rl_dat = (0x0001<<(load-1));
 		rl_dat = ~rl_dat;
 		//xil_printf("load: %x\n\r", load);
 		//xil_printf("rl_01_dat: %x\n\r", rl_dat);
 		sw_config_data[0] = (u8)(rl_dat>>8);
 		sw_config_data[1] = (u8)(rl_dat);
 		spi_write_onewire(U1_SW_RL1, sw_config_data, dat_width, CPLD_U1);
 	}
 	else
 	{
 		rl_dat = (0x0001<<(load-10));
 		rl_dat = ~rl_dat;
 		//xil_printf("load: %x\n\r", load);
 		//xil_printf("rl_02_dat: %x\n\r", rl_dat);
 		sw_config_data[0] = (u8)(rl_dat>>8);
 		sw_config_data[1] = (u8)(rl_dat);
 		spi_write_onewire(U1_SW_RL2, sw_config_data, dat_width, CPLD_U1);
 	}
 }
 void  fsc_oc_config(char slot,char m_fun, u16 ch_num)
 {
        u16	    fc_dv0_dat = 0;
 		switch(m_fun)
 		{
 		  case 0x01:
 		  {
 			  if(ch_num>=1&&ch_num<=16)
 			  {
 				  //xil_printf("m_fun=0x01,ch_num=1~16 \n\r");
 				  fc_dv0_dat = (0x0001<<(ch_num-1));
 				  fc_dv0_dat = ~fc_dv0_dat;
 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 				  spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 				  //xil_printf("CPLD_U1:\n\r");
 				  //xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 			  }
 			  else
 			  {
 				  //xil_printf("m_fun=0x01,ch_num=17~32 \n\r");
 				  fc_dv0_dat = (0x0001<<(ch_num-17));
 				  fc_dv0_dat = ~fc_dv0_dat;
 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 				  spi_write_onewire(U2_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
 				  //xil_printf("CPLD_U2:\n\r");
 				  //xil_printf("fc_reg_addr: %d\n\r", U2_SW_FC_DV0+slot-1);
 			  }
 			  //xil_printf("reg_data: %x\n\r", fc_dv0_dat);
 			  break;
 		  }
 		  case 0x02:
 		  {
 			  if(ch_num>=1&&ch_num<=16)
 			  {
 				  //xil_printf("m_fun=0x02,ch_num=1~16 \n\r");
 				  fc_dv0_dat = (0x0001<<(ch_num-1));
 				  fc_dv0_dat = ~fc_dv0_dat;
 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 				  spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 				  //xil_printf("CPLD_U1:\n\r");
 				  //xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 			  }
 			  else
 			  {
 				  //xil_printf("m_fun=0x02,ch_num=17~32 \n\r");
 				  fc_dv0_dat = (0x0001<<(ch_num-17));
 				  fc_dv0_dat = ~fc_dv0_dat;
 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 				  spi_write_onewire(U2_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
 				  //xil_printf("CPLD_U2:\n\r");
 				  //xil_printf("sc_reg_addr: %d\n\r", U2_SW_SC_DV0+slot-1);
 			  }
 			  //xil_printf("reg_data: %x\n\r", fc_dv0_dat);
 			  break;
 		  }
 		  case 0x03:
 		  {
 			  if(ch_num>=1&&ch_num<=16)
 			  {
 				  //xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
 				  fc_dv0_dat = (0x0001<<(ch_num-1));
 				  fc_dv0_dat = ~fc_dv0_dat;
 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 				  spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 				  spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 				  //xil_printf("CPLD_U1:\n\r");
 				  //xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 				  //xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 			  }
 			  else
 			  {
 				  //xil_printf("m_fun=0x03,ch_num=17~32 \n\r");
 				  fc_dv0_dat = (0x0001<<(ch_num-17));
 				  fc_dv0_dat = ~fc_dv0_dat;
 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 				  spi_write_onewire(U2_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
 				  spi_write_onewire(U2_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
 				  //xil_printf("CPLD_U2:\n\r");
 				  //xil_printf("fc_reg_addr: %d\n\r", U2_SW_FC_DV0+slot-1);
 				  //xil_printf("sc_reg_addr: %d\n\r", U2_SW_SC_DV0+slot-1);
 			  }
 			  //xil_printf("reg_data: %x\n\r", fc_dv0_dat);
 			  break;
 		  }
 		  case 0x04:
 		  {
 			  if(ch_num>=1&&ch_num<=64)
 			  {
 				  //xil_printf("m_fun=0x04,ch_num=1~64 \n\r");
 				  fc_dv0_dat = (0x0001<<((ch_num-1)/8));
 				  fc_dv0_dat = ~fc_dv0_dat;
 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 				  spi_write_onewire(U1_SW_OC_DV0+(slot-1)*2, sw_config_data, dat_width, CPLD_U1);
 				  //xil_printf("CPLD_U1:\n\r");
 				  //xil_printf("oc_reg_addr: %d\n\r", U1_SW_OC_DV0+(slot-1)*2);
 			  }
 			  else if(ch_num>=65&&ch_num<=128)
 			  {
 				  //xil_printf("m_fun=0x04,ch_num=65~128 \n\r");
 				  fc_dv0_dat = (0x0001<<((ch_num-65)/8));
 				  fc_dv0_dat = ~fc_dv0_dat;
 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 				  spi_write_onewire(U2_SW_OC_DV0+(slot-1)*2, sw_config_data, dat_width, CPLD_U2);
 				  //xil_printf("CPLD_U2:\n\r");
 				  //xil_printf("oc_reg_addr: %d\n\r", U2_SW_OC_DV0+(slot-1)*2);
 			  }
 			  else if(ch_num>=129&&ch_num<=192)
 			  {
 				  //xil_printf("m_fun=0x04,ch_num=129~192 \n\r");
 				  fc_dv0_dat = (0x0001<<((ch_num-129)/8));
 				  fc_dv0_dat = ~fc_dv0_dat;
 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 				  spi_write_onewire(U1_SW_OC_DV1+(slot-1)*2, sw_config_data, dat_width, CPLD_U1);
 				  //xil_printf("CPLD_U1:\n\r");
 				  //xil_printf("oc_reg_addr: %d\n\r", U1_SW_OC_DV1+(slot-1)*2);
 			  }
 			  else if(ch_num>=193&&ch_num<=256)
 			  {
 				  //xil_printf("m_fun=0x04,ch_num=193~256 \n\r");
 				  fc_dv0_dat = (0x0001<<((ch_num-193)/8));
 				  fc_dv0_dat = ~fc_dv0_dat;
 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 				  spi_write_onewire(U2_SW_OC_DV1+(slot-1)*2, sw_config_data, dat_width, CPLD_U2);
 				  //xil_printf("CPLD_U2:\n\r");
 				  //xil_printf("oc_reg_addr: %d\n\r", U2_SW_OC_DV1+(slot-1)*2);
 			  }
 			  //xil_printf("reg_data: %x\n\r", fc_dv0_dat);
 			  break;
 		  }
       }
 }
@@ -1,67 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(m_fun==0x04)
 		 {
 			 //xil_printf("memt_areal: %d\n\r", memt_areal);
 			 if(memt_areal==0x01)
 			 {
 				 u1_io_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_io_rc_dat);
 				 spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
 				 //xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
 			 }
 			 else
 			 {
 				 u1_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_rc_dat);
 				 spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
 				// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
 			 }
 		 }
 		 if(ch_num>=1&&ch_num<=16)
 		  {
 		 	//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
 		 	fc_dv0_dat = (0x0001<<(ch_num-1));
 		 	fc_dv0_dat = ~fc_dv0_dat;
 		 	sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 		 	sw_config_data[1] = (u8)(fc_dv0_dat);
 		 	spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	//xil_printf("CPLD_U1:\n\r");
 		 	//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 		 	//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 		 }
 }
@@ -1,108 +0,0 @@
 /*
 * GPIO_Driv.c
 *
 *  Created on: 2021年5月7日
 *      Author: Administrator
 */
 #include "GPIO_Driv.h"
 XGpioPs psGpioInstancePtr;     //端口
 XGpioPs_Config* GpioConfigPtr; //设备ID
 					//sck,cs,sdi,sdo,rst
 u32 CPLD_U1  [11] = {54,55,56,57,58,59,60,61,62,63,64};
 u32 CPLD_U2  [11] = {65,66,67,68,69,70,71,72,73,74,75};
 u32 CPLD_U3  [11] = {76,77,78,79,80,81,82,83,84,85,86};
 void EMIO_config(void)
 {
 	    int xStatus;
 		GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
 		if(GpioConfigPtr == NULL)
 			return XST_FAILURE;
 		xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
 		if(XST_SUCCESS != xStatus)
 			print(" PS GPIO INIT FAILED \n\r");
 		/*-------------------------------------CPLD_U1------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 0);//57---sdo
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 1);//58---rst_n
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);//57---sdo
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);//58---rst_n
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//59
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//60
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//61
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//62
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//63
 		/*-------------------------------------CPLD_U2------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//68---sdo
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//69---rst_n
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//70
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//71
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//72
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//73
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//74
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);//68---sdo
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);//69---rst_n
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);//70
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);//71
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);//72
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);//73
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);//74
 		/*-------------------------------------CPLD_U3------------------------------------*/
 				//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//76---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//78---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//79---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 0);//80---sdo
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 1);//77---rst_n
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//81
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//82
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//83
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//84
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//85
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//76---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//77---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//78---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 1);//79---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 0);//80---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);//81
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);//82
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);//83
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);//84
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);//85
 }
@@ -1,108 +0,0 @@
 /*
 * GPIO_Driv.c
 *
 *  Created on: 2021年5月7日
 *      Author: Administrator
 */
 #include "GPIO_Driv.h"
 XGpioPs psGpioInstancePtr;     //端口
 XGpioPs_Config* GpioConfigPtr; //设备ID
 					//sck,cs,sdi,sdo,rst
 u32 CPLD_U1  [11] = {54,55,56,57,58,59,60,61,62,63,64};
 u32 CPLD_U2  [11] = {65,66,67,68,69,70,71,72,73,74,75};
 u32 CPLD_U3  [11] = {76,77,78,79,80,81,82,83,84,85,86};
 void EMIO_config(void)
 {
 	    int xStatus;
 		GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
 		if(GpioConfigPtr == NULL)
 			return XST_FAILURE;
 		xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
 		if(XST_SUCCESS != xStatus)
 			print(" PS GPIO INIT FAILED \n\r");
 		/*-------------------------------------CPLD_U1------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 1);//57---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 0);//58---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 1);//57---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 0);//58---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//59
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//60
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//61
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//62
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//63
 		/*-------------------------------------CPLD_U2------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 1);//68---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 0);//69---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//70
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//71
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//72
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//73
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//74
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 1);//68---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 0);//69---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);//70
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);//71
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);//72
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);//73
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);//74
 		/*-------------------------------------CPLD_U3------------------------------------*/
 				//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//76---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//77---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//78---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 1);//79---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 0);//80---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//81
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//82
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//83
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//84
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//85
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//76---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//77---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//78---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 1);//79---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 0);//80---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);//81
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);//82
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);//83
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);//84
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);//85
 }
@@ -1,66 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num = 0;
 		 u32
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(m_fun==0x04)
 		 {
 			 //xil_printf("memt_areal: %d\n\r", memt_areal);
 			 if(memt_areal==0x01)
 			 {
 				 u1_io_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_io_rc_dat);
 				 spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
 				 //xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
 			 }
 			 else
 			 {
 				 u1_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_rc_dat);
 				 spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
 				// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
 			 }
 		 }
 		 if(ch_num>=1&&ch_num<=16)
 		  {
 		 	//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
 		 	fc_dv0_dat = (0x0001<<(ch_num-1));
 		 	fc_dv0_dat = ~fc_dv0_dat;
 		 	sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 		 	sw_config_data[1] = (u8)(fc_dv0_dat);
 		 	spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	//xil_printf("CPLD_U1:\n\r");
 		 	//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 		 	//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 		 }
 }
@@ -1,221 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start, u32 CPLD_UU[11])
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 u8      cpld_addr = 0;
 		 u32     cpld_dat  = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(slot==1)
 		 {
 			 cpld_addr = 0x82;
 		 }
 		 else if(slot==2)
 		 {
 			 cpld_addr = 0x83;
 		 }
 		 else if(slot==3)
 		 {
 			 cpld_addr = 0x84;
 		 }
 		 else
 		 {
 			 cpld_addr = 0x85;
 		 }
 		 switch(ch_num)
 		 {
 		   case 0x0001:
 		 	   {
 		 		   relay_ctrl = 0x00000000;
 		 		   break;
 		 	   }
 		   case 0x0002:
 		   	   {
 		   		   relay_ctrl = 0x00020000;
 		   		   break;
 		   	   }
 		   case 0x0003:
 		   	   {
 		   		   relay_ctrl = 0x00200000;
 		   		   break;
 		   	   }
 		   case 0x0004:
 		   	   {
 		   		   relay_ctrl = 0x00022000;
 		   		   break;
 		   	   }
 		   case 0x0005:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0006:
 		   	   {
 		   		   relay_ctrl = 0x00810000;
 		   		   break;
 		   	   }
 		   case 0x0007:
 		   	   {
 		   		   relay_ctrl = 0x00A00000;
 		   		   break;
 		   	   }
 		   case 0x0008:
 		   	   {
 		   		   relay_ctrl = 0x00A10000;
 		   		   break;
 		   	   }
 		   case 0x0041:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0042:
 		   	   {
 		   		   relay_ctrl = 0x00008000;
 		   		   break;
 		   	   }
 		   case 0x0043:
 		   	   {
 		   		   relay_ctrl = 0x00100000;
 		   		   break;
 		   	   }
 		   case 0x0044:
 		   	   {
 		   		   relay_ctrl = 0x00108000;
 		   		   break;
 		   	   }
 		   case 0x0045:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0046:
 		   	   {
 		   		   relay_ctrl = 0x00804000;
 		   		   break;
 		   	   }
 		   case 0x0047:
 		   	   {
 		   		   relay_ctrl = 0x00900000;
 		   		   break;
 		   	   }
 		   case 0x0048:
 		   	   {
 		   		   relay_ctrl = 0x00904000;
 		   		   break;
 		   	   }
 		   case 0x0081:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0082:
 		   	   {
 		   		   relay_ctrl = 0x00002000;
 		   		   break;
 		   	   }
 		   case 0x0083:
 		   	   {
 		   		   relay_ctrl = 0x00080000;
 		   		   break;
 		   	   }
 		   case 0x0084:
 		   	   {
 		   		   relay_ctrl = 0x00082000;
 		   		   break;
 		   	   }
 		   case 0x0085:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x0086:
 		   	   {
 		   		   relay_ctrl = 0x00401000;
 		   		   break;
 		   	   }
 		   case 0x0087:
 		   	   {
 		   		   relay_ctrl = 0x00480000;
 		   		   break;
 		   	   }
 		   case 0x0088:
 		   	   {
 		   		   relay_ctrl = 0x00481000;
 		   		   break;
 		   	   }
 		   case 0x00C1:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x00C2:
 		   	   {
 		   		   relay_ctrl = 0x00000800;
 		   		   break;
 		   	   }
 		   case 0x00C3:
 		   	   {
 		   		   relay_ctrl = 0x00040000;
 		   		   break;
 		   	   }
 		   case 0x00C4:
 		   	   {
 		   		   relay_ctrl = 0x00040800;
 		   		   break;
 		   	   }
 		   case 0x00C5:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x00C6:
 		   	   {
 		   		   relay_ctrl = 0x00400400;
 		   		   break;
 		   	   }
 		   case 0x00C7:
 		   	   {
 		   		   relay_ctrl = 0x00440000;
 		   		   break;
 		   	   }
 		   case 0x00C8:
 		   	   {
 		   		   relay_ctrl = 0x00440400;
 		   		   break;
 		   	   }
 		 }
 		 ch_num_dat = ((u32)ch_num)<<1;
 		 cpld_dat  = relay_ctrl|ch_num_dat|slot_en;
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
 }
@@ -1,64 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0xFF,0xFF,0xFF};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(m_fun==0x04)
 		 {
 			 //xil_printf("memt_areal: %d\n\r", memt_areal);
 			 if(memt_areal==0x01)
 			 {
 				 u1_io_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_io_rc_dat);
 				 spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
 				 //xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
 			 }
 			 else
 			 {
 				 u1_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_rc_dat);
 				 spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
 				// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
 			 }
 		 }
 		 if(ch_num>=1&&ch_num<=16)
 		  {
 		 	//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
 		 	fc_dv0_dat = (0x0001<<(ch_num-1));
 		 	fc_dv0_dat = ~fc_dv0_dat;
 		 	sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 		 	sw_config_data[1] = (u8)(fc_dv0_dat);
 		 	spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	//xil_printf("CPLD_U1:\n\r");
 		 	//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 		 	//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 		 }
 }
@@ -1,64 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0xFF,0xFF,0xFF};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(m_fun==0x04)
 		 {
 			 //xil_printf("memt_areal: %d\n\r", memt_areal);
 			 if(memt_areal==0x01)
 			 {
 				 u1_io_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_io_rc_dat);
 				 spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
 				 //xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
 			 }
 			 else
 			 {
 				 u1_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_rc_dat);
 				 spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
 				// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
 			 }
 		 }
 		 if(ch_num>=1&&ch_num<=16)
 		  {
 		 				  //xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
 		 				  fc_dv0_dat = (0x0001<<(ch_num-1));
 		 				  fc_dv0_dat = ~fc_dv0_dat;
 		 				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 		 				  sw_config_data[1] = (u8)(fc_dv0_dat);
 		 				  spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 				  spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 				  //xil_printf("CPLD_U1:\n\r");
 		 				  //xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 		 				  //xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 		 }
 }
@@ -1,555 +0,0 @@
 /*
 * SPI_Driv.c
 *
 *  Created on: 2021年4月2日
 *      Author: dell
 */
 #include "SPI_Driv.h"
 XGpioPs psGpioInstancePtr;     //端口
 XGpioPs_Config* GpioConfigPtr; //设备ID
 extern u32 K7_U0[16];
 extern u32 molex_4_bank_3[4];
 extern u32 cs_en_bank_3[4];
 /******************************************************************************
 * Function    : void interface_initial(u32* device,u32 num_wire)
 * Description : interface initial
 * Parameter   : device   -- CPLD
 * 				num_wire -- 复位线编号
 * Return      : void
 ******************************************************************************/
 void interface_initial(u32* device)  //wire_num = cs sck sdi/o
 {
 	u32   sck   = *(device+0);
 	u32	  cs    = *(device+1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
 }
 /******************************************************************************
 * Function    : void rst_CPLD(u32* device,u32 num_wire)
 * Description : CPLD reset
 * Parameter   : device   -- CPLD
 * 				num_wire -- 复位线编号
 * Return      : void
 ******************************************************************************/
 void rst_CPLD(u32* device,u32 num_wire) //wire_num = cs sck sdi/o
 {
 	u32	rst_n = *(device+num_wire);
 	XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
 	usleep(2);
 	XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
 }
 /******************************************************************************
 * Function    : void spi_write_onewire(char addr, u32 data, char width, u32* device)
 * Description : spi onewire write
 * Parameter   : addr   -- 地址
 * 				data   -- 数据
 * 				width  -- 数据长度
 * 				device -- CPLD
 * Return      : void
 ******************************************************************************/
 void spi_write_onewire(char addr, char *data, char width, u32* device)
 {
 	char  temp_addr = 0;
 	//u32   temp_data = 0;
 	u32   temp_data = 0;
 	char  i = 0,j=0;
 	u32   sck = *(device+0);
 	u32	  cs= *(device+1);
 	u32   sdi= *(device+2);
 	temp_addr = addr;
 	///temp_data = data;
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs,  0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs,  0);
 	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1);			// w/r标志位    1=w 0=r
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	for(i = 0; i < 8; i++)								// 8bit地址
 	{
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	    if(temp_addr&0x80)
 	    	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据     数据从中间变量到通信线上
 	    else
 	    	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    temp_addr = temp_addr<<1;                       //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
 	}
 	for(j=0;j<width;j++)
 	{
 		temp_data = *(data+j);
 		for(i = 0; i < 8; i++)                             //nbit数据
 		{
 			XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 			XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 			if(temp_data&0x80)							//注意数据位nbit，要从[n-1]取位
 				XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1);
 			else
 				XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 			XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 			XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 			temp_data <<=  1;
 		}
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	}
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs , 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 }
 /******************************************************************************
 * Function    : u32	spi_read_onewire(char addr, char width, u32* device)
 * Description : spi onewire read
 * Parameter   : addr   -- 地址
 * 				data   -- 数据
 * 				width  -- 数据长度
 * 				device -- CPLD
 * Return      : void
 ******************************************************************************/
 u32	spi_read_onewire(char addr, char width, u32* device)
 {
 	char  temp_addr=0;
 	u32	  temp_data=0;
 	char  i=0,j=0;
 	u32   sck = *(device+0);
 	u32	  cs= *(device+1);
 	u32   sdi= *(device+2);
 	u32   sdo= *(device+3);
 	temp_addr = addr;
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);		// w/r标志位    1=w 0=r
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	for(i = 0; i < 8; i++)								// 8bit地址
 	{
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	    if(temp_addr&0x80)
 	    	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据     数据从中间变量到通信线上
 	    else
 	    	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    temp_addr = temp_addr<<1;                       //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
 	}
 	for(j=0; j<width; j++)
 	{
 			for(i = 0; i < 8; i++)                             //nbit数据
 			{
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 				temp_data = temp_data << 1;                     //sck低电平准备数据    准备好数位，此时的数据相当于从右边的FPGA移进MCU(先准备好中间变量)
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 				if(XGpioPs_ReadPin(&psGpioInstancePtr,sdo))    //sck高电平接收数据     数据匹配到准备好的数位，等待一起传递到MCU
 					temp_data = temp_data| 0x00000001;
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 			    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 			}
 	}
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 	return temp_data;
 }
 /******************************************************************************
 * Function    : void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
 * Description : forwire write to reg
 * Parameter   : txdata--数据
 * 				sdi0,sdi1,sdi2,sdi3--IO
 * Return      : void
 ******************************************************************************/
 void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
 {
 	switch(txdata & 0x0F)
 	{
 	   case 0x00:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x01:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x02:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x03:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x04:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x05:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x06:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x07:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x08:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x09:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0A:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0B:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0C:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0D:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0E:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0F:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	}
 }
 /******************************************************************************
 * Function    : void spi_write_fourwire(char addr, u16 data, u32* device)
 * Description : spi fourwire write
 * Parameter   : addr   -- 地址
 * 				data   -- 数据
 * 				width  -- 数据长度
 *  				device -- CPLD
 * Return      : void
 ******************************************************************************/
 void spi_write_fourwire(char addr, u16 data, u32* device)
 {
 	u8    temp_addr = 0;
 	u16   temp_data = 0;
 	u8	  split_addr[2] = {0};	//将8bit地址拆分，分别给4线传输，
 	u8	  split_data[4] = {0};	//16bit数据拆成4个4bit
 	u8    i;
 	u32   sck   = *(device+0);
 	u32	  cs    = *(device+1);
 	u32	  sdi0 = *(device+2);
 	u32	  sdi1 = *(device+3);
 	u32	  sdi2 = *(device+4);
 	u32	  sdi3 = *(device+5);
 	temp_addr = addr;
 	temp_data = data;
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	fourwire_write(0x01,sdi0,sdi1,sdi2,sdi3);     			// w/r标志位    1=w 0=r
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	for(i = 0; i < 2;i++)									// 8bit地址 四根线分两次传输
 	{
 		split_addr[i] = (temp_addr>>(4*(1-i)))&0x0F;		//sck高电平准备数据		数据从MCU到中间变量上
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		fourwire_write(split_addr[i],sdi0,sdi1,sdi2,sdi3);	//sck低电平传输数据     数据从中间变量到通信线上
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	}
 	for(i = 0; i < 4;i++)									//16bit数据  4根线分四次传输
 	{
 		split_data[i] = (temp_data>>(4*(3-i)))&0x0F;
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		fourwire_write(split_data[i],sdi0,sdi1,sdi2,sdi3);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	}
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
    fourwire_write(0x00,sdi0,sdi1,sdi2,sdi3);
    //usleep(20);
 }
 /******************************************************************************
 * Function    : u16	fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
 * Description : forwire read from reg
 * Parameter   : sdo0,sdo1,sdo2,sdo3--IO
 * Return      : rxdata--数据
 ******************************************************************************/
 u16	fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
 {
 	u32 GPIO_PIN[4];
 	u16	rdata[4];
 	u16 rxdata = 0;
 	GPIO_PIN[0] = sdo0;
 	GPIO_PIN[1] = sdo1;
 	GPIO_PIN[2] = sdo2;
 	GPIO_PIN[3] = sdo3;
 	for(u8 i = 0; i < 4 ; i++)
 	{
 		rdata[i] = XGpioPs_ReadPin(&psGpioInstancePtr,GPIO_PIN[i]);
 		//xil_printf("rdata[i] = %x\r\n",rdata[i]);
 		rxdata   = ((rdata[i])<<i) + rxdata ;
 	}
 	return	rxdata;
 }
 /******************************************************************************
 * Function    : void spi_read_fourwire(char addr, u16* rxdata, u32* device)
 * Description : spi fourwire read
 * Parameter   : addr   -- 地址
 * 				rxdata -- 数据
 * 				device -- CPLD
 * Return      : void
 ******************************************************************************/
 void spi_read_fourwire(char addr, u16* rxdata, u32* device)   //接收数据使用指针传递，方便接收多个
 {
 	u8    temp_addr = 0;
 	u16   temp_data = 0;
 	u8	  split_addr[2] = {0};	//将8bit地址拆分，分别给4线传输，
 	u16	  split_data[4] = {0};	//16bit数据拆成4个4bit
 	u8    i = 0;
 	u32   sck   = *(device+0);
 	u32	  cs    = *(device+1);
 	u32	  sdio0 = *(device+2);
 	u32	  sdio1 = *(device+3);
 	u32	  sdio2 = *(device+4);
 	u32	  sdio3 = *(device+5);
 	temp_addr = addr;
 	split_addr[0] = (temp_addr >> 4)&0x0F;
 	split_addr[1] = (temp_addr)&0x0F;
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3);     			// w/r标志位    1=w 0=r
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	for(i = 0; i < 2; i++)									// 8bit地址 四根线分两次传输
 	{
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		fourwire_write(split_addr[i],sdio0,sdio1,sdio2,sdio3);	//sck低电平传输数据     数据从中间变量到通信线上
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	}
 	for(i = 0; i < 4; i++)
 	{
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),0);  //input
 	}
 	for(i = 0; i < 4; i++)									//16bit数据  4根线分四次接收
 	{
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		split_data[i] = fourwire_read(sdio0,sdio1,sdio2,sdio3);	//sck低电平准备数据     数据从通信线到中间变量上
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    temp_data = temp_data<<4;
 	    temp_data = temp_data + split_data[i];
 		//temp_data = (split_data[i]<<(4*(3-i))) + temp_data;		//sck高电平接收数据     数据从中间变量到MCU上
 //	    xil_printf("split_data[i],temp_data = %x,%x\r\n",split_data[i],temp_data);
 	}
 	for(i = 0; i < 4; i++)
 	{
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),1);  //output
 	}
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3);
 	*rxdata = temp_data;
    XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
    XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
    XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);//add 2 lines
    //usleep(20);
 }
 /******************************************************************************
 * Function    : void GPIO_dir_set(u32* device,char dir)
 * Description : change GPIO direction
 * Parameter   : device -- CPLD
 * 				dir    -- GPIO_OUT/GPIO_IN
 * Return      : void
 ******************************************************************************/
 void GPIO_dir_set_16(u32* device,char dir)
 {
 	u32   sdio[16] = {0};
 	u8    i;
 	for(i = 0; i < 16;i++)
 	{
 		sdio[i] = *(device+i);
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, sdio[i],1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir);
 	}
 }
 void GPIO_dir_set_cs_enable(u32* device,u8 dir)
 {
 	u32   sdio[4] = {0};
 	u8    i;
 	u8    dir_temp = 0;
 	for(i = 0; i < 4;i++)
 	{
 		sdio[i]  = *(device+i);
 		dir_temp =  (((dir >> (3-i))) & 0x01);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir_temp);
 	}
 }
 void  rst(char *d)
 {
 	XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, *d, 1);
 	usleep(20);
 	XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
 }
 void func_test(void)
 {
 	XGpioPs_Write(&psGpioInstancePtr, 0x03, 0x12345678);
 }
@@ -1,79 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 u8      cpld_addr = 0;
 		 u32     cpld_dat  = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(slot==1)
 		  { cpld_addr = 0x82;}
 		 else if(slot==2)
 		  { cpld_addr = 0x83;}
 		 else if(slot==3)
 		  { cpld_addr = 0x84;}
 		 else
 		  { cpld_addr = 0x85;}
 		 if(m_fun==0x04)
 		 {
 			 //xil_printf("memt_areal: %d\n\r", memt_areal);
 			 if(memt_areal==0x01)
 			 {
 				 u1_io_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_io_rc_dat);
 				 spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
 				 //xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
 			 }
 			 else
 			 {
 				 u1_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_rc_dat);
 				 spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
 				// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
 			 }
 		 }
 		 if(ch_num>=1&&ch_num<=16)
 		  {
 		 	//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
 		 	fc_dv0_dat = (0x0001<<(ch_num-1));
 		 	fc_dv0_dat = ~fc_dv0_dat;
 		 	sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 		 	sw_config_data[1] = (u8)(fc_dv0_dat);
 		 	spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	//xil_printf("CPLD_U1:\n\r");
 		 	//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 		 	//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 		 }
 }
@@ -1,79 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 u8      cpld_addr = 0;
 		 u32     cpld_dat  = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(slot==1)
 		 { cpld_addr = 0x82;}
 		 else if(slot==2)
 		 { cpld_addr = 0x83;}
 		 else if(slot==3)
 		 { cpld_addr = 0x84;}
 		 else
 		 { cpld_addr = 0x85;}
 		 if(m_fun==0x04)
 		 {
 			 //xil_printf("memt_areal: %d\n\r", memt_areal);
 			 if(memt_areal==0x01)
 			 {
 				 u1_io_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_io_rc_dat);
 				 spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
 				 //xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
 			 }
 			 else
 			 {
 				 u1_rc_dat = 0xFFFE;
 				 sw_config_data[0] = (u8)(u1_rc_dat>>8);
 				 sw_config_data[1] = (u8)(u1_rc_dat);
 				 spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
 				// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
 			 }
 		 }
 		 if(ch_num>=1&&ch_num<=16)
 		  {
 		 	//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
 		 	fc_dv0_dat = (0x0001<<(ch_num-1));
 		 	fc_dv0_dat = ~fc_dv0_dat;
 		 	sw_config_data[0] = (u8)(fc_dv0_dat>>8);
 		 	sw_config_data[1] = (u8)(fc_dv0_dat);
 		 	spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
 		 	//xil_printf("CPLD_U1:\n\r");
 		 	//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
 		 	//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
 		 }
 }
@@ -1,108 +0,0 @@
 /*
 * GPIO_Driv.c
 *
 *  Created on: 2021年5月7日
 *      Author: Administrator
 */
 #include "GPIO_Driv.h"
 XGpioPs psGpioInstancePtr;     //端口
 XGpioPs_Config* GpioConfigPtr; //设备ID
 					//sck,cs,sdi,sdo,rst
 u32 CPLD_U1  [11] = {54,55,56,57,58,59,60,61,62,63,64};
 u32 CPLD_U2  [11] = {65,66,67,68,69,70,71,72,73,74,75};
 u32 CPLD_U3  [11] = {76,77,78,79,80,81,82,83,84,85,86};
 void EMIO_config(void)
 {
 	    int xStatus;
 		GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
 		if(GpioConfigPtr == NULL)
 			return XST_FAILURE;
 		xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
 		if(XST_SUCCESS != xStatus)
 			print(" PS GPIO INIT FAILED \n\r");
 		/*-------------------------------------CPLD_U1------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 0);//57---sdo
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 1);//58---rst_n
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);//57---sdo
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);//58---rst_n
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//59
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//60
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//61
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//62
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//63
 		/*-------------------------------------CPLD_U2------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 1);//68---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 0);//69---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//70
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//71
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//72
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//73
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//74
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 1);//68---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 0);//69---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);//70
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);//71
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);//72
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);//73
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);//74
 		/*-------------------------------------CPLD_U3------------------------------------*/
 				//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//76---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//77---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//78---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 1);//79---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 0);//80---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//81
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//82
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//83
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//84
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//85
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//76---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//77---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//78---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 1);//79---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 0);//80---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);//81
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);//82
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);//83
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);//84
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);//85
 }
@@ -1,78 +0,0 @@
 /*
 * GPIO_Driv.c
 *
 *  Created on: 2021年5月7日
 *      Author: Administrator
 */
 #include "GPIO_Driv.h"
 XGpioPs psGpioInstancePtr;     //端口
 XGpioPs_Config* GpioConfigPtr; //设备ID
 					//sck,cs,sdi,sdo,rst
 u32 CPLD_U1  [11] = {54,55,56,57,58,59,60,61,62,63,64};
 u32 CPLD_U2  [11] = {65,66,67,68,69,70,71,72,73,74,75};
 u32 CPLD_U3  [11] = {76,77,78,79,80,81,82,83,84,85,86};
 void EMIO_config(void)
 {
 	    int xStatus;
 		GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
 		if(GpioConfigPtr == NULL)
 			return XST_FAILURE;
 		xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
 		if(XST_SUCCESS != xStatus)
 			print(" PS GPIO INIT FAILED \n\r");
 		/*-------------------------------------CPLD_U1------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//58---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//55---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 1);//56---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 0);//57---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59---sdio3
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60---sdio4
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//60---sdio5
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//60---sdio6
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//60---sdio7
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);
 		/*-------------------------------------CPLD_U2------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//61---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//62---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//63---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//64---sdo
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//65---rst
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66---sdio3
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67---sdio4
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67---sdio5
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67---sdio6
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67---sdio7
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
 }
@@ -1,558 +0,0 @@
 /*
 * SPI_Driv.c
 *
 *  Created on: 2021年4月2日
 *      Author: dell
 */
 #include "SPI_Driv.h"
 XGpioPs psGpioInstancePtr;     //端口
 XGpioPs_Config* GpioConfigPtr; //设备ID
 extern u32 K7_U0[16];
 extern u32 molex_4_bank_3[4];
 extern u32 cs_en_bank_3[4];
 /******************************************************************************
 * Function    : void interface_initial(u32* device,u32 num_wire)
 * Description : interface initial
 * Parameter   : device   -- CPLD
 * 				num_wire -- 复位线编号
 * Return      : void
 ******************************************************************************/
 void interface_initial(u32* device)  //wire_num = cs sck sdi/o
 {
 	u32   sck   = *(device+0);
 	u32	  cs    = *(device+1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
 }
 /******************************************************************************
 * Function    : void rst_CPLD(u32* device,u32 num_wire)
 * Description : CPLD reset
 * Parameter   : device   -- CPLD
 * 				num_wire -- 复位线编号
 * Return      : void
 ******************************************************************************/
 void rst_CPLD(u32* device,u32 num_wire) //wire_num = cs sck sdi/o
 {
 	u32	rst_n = *(device+num_wire);
 	XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
 	usleep(2);
 	XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
 }
 /******************************************************************************
 * Function    : void spi_write_onewire(char addr, u32 data, char width, u32* device)
 * Description : spi onewire write
 * Parameter   : addr   -- 地址
 * 				data   -- 数据
 * 				width  -- 数据长度
 * 				device -- CPLD
 * Return      : void
 ******************************************************************************/
 void spi_write_onewire(char addr, char *data, char width, u32* device)
 {
 	char  temp_addr = 0;
 	//u32   temp_data = 0;
 	u32   temp_data = 0;
 	char  i = 0,j=0;
 	u32   sck = *(device+0);
 	u32	  cs= *(device+1);
 	u32   sdi= *(device+2);
 	temp_addr = addr;
 	///temp_data = data;
 	//XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs,  0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs,  0);
 	//XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1);			// w/r标志位    1=w 0=r
 	//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	for(i = 0; i < 8; i++)								// 8bit地址
 	{
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	    if(temp_addr&0x80)
 	    	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据     数据从中间变量到通信线上
 	    else
 	    	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    temp_addr = temp_addr<<1;                       //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
 	}
 	for(j=0;j<width;j++)
 	{
 		temp_data = *(data+j);
 		for(i = 0; i < 8; i++)                             //nbit数据
 		{
 			XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 			XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 			if(temp_data&0x80)							//注意数据位nbit，要从[n-1]取位
 				XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1);
 			else
 				XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 			XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 			XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 			temp_data <<=  1;
 		}
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	}
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs , 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 }
 /******************************************************************************
 * Function    : u32	spi_read_onewire(char addr, char width, u32* device)
 * Description : spi onewire read
 * Parameter   : addr   -- 地址
 * 				data   -- 数据
 * 				width  -- 数据长度
 * 				device -- CPLD
 * Return      : void
 ******************************************************************************/
 u32	spi_read_onewire(char addr, char width, u32* device,char* read_data)
 {
 	char  temp_addr=0;
 	u32	  temp_data=0;
 	char  i=0,j=0;
 	u32   sck = *(device+0);
 	u32	  cs= *(device+1);
 	u32   sdi= *(device+2);
 	u32   sdo= *(device+3);
 	temp_addr = addr;
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);		// w/r标志位    1=w 0=r
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	for(i = 0; i < 8; i++)								// 8bit地址
 	{
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	    if(temp_addr&0x80)
 	    	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据     数据从中间变量到通信线上
 	    else
 	    	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    temp_addr = temp_addr<<1;                       //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
 	}
 	for(j=0; j<width; j++)
 	{
 			for(i = 0; i < 8; i++)                             //nbit数据
 			{
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 				temp_data = temp_data << 1;                     //sck低电平准备数据    准备好数位，此时的数据相当于从右边的FPGA移进MCU(先准备好中间变量)
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 				if(XGpioPs_ReadPin(&psGpioInstancePtr,sdo))    //sck高电平接收数据     数据匹配到准备好的数位，等待一起传递到MCU
 					temp_data = temp_data| 0x00000001;
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 			    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 			}
 	}
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 	read_data[0] = (u8)(temp_data>>16);
 	read_data[1] = (u8)(temp_data>>8);
 	read_data[0] = (u8)(temp_data);
 	return temp_data;
 }
 /******************************************************************************
 * Function    : void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
 * Description : forwire write to reg
 * Parameter   : txdata--数据
 * 				sdi0,sdi1,sdi2,sdi3--IO
 * Return      : void
 ******************************************************************************/
 void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
 {
 	switch(txdata & 0x0F)
 	{
 	   case 0x00:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x01:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x02:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x03:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x04:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x05:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x06:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x07:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x08:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x09:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0A:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0B:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0C:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0D:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0E:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0F:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	}
 }
 /******************************************************************************
 * Function    : void spi_write_fourwire(char addr, u16 data, u32* device)
 * Description : spi fourwire write
 * Parameter   : addr   -- 地址
 * 				data   -- 数据
 * 				width  -- 数据长度
 *  				device -- CPLD
 * Return      : void
 ******************************************************************************/
 void spi_write_fourwire(char addr, u16 data, u32* device)
 {
 	u8    temp_addr = 0;
 	u16   temp_data = 0;
 	u8	  split_addr[2] = {0};	//将8bit地址拆分，分别给4线传输，
 	u8	  split_data[4] = {0};	//16bit数据拆成4个4bit
 	u8    i;
 	u32   sck   = *(device+0);
 	u32	  cs    = *(device+1);
 	u32	  sdi0 = *(device+2);
 	u32	  sdi1 = *(device+3);
 	u32	  sdi2 = *(device+4);
 	u32	  sdi3 = *(device+5);
 	temp_addr = addr;
 	temp_data = data;
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	fourwire_write(0x01,sdi0,sdi1,sdi2,sdi3);     			// w/r标志位    1=w 0=r
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	for(i = 0; i < 2;i++)									// 8bit地址 四根线分两次传输
 	{
 		split_addr[i] = (temp_addr>>(4*(1-i)))&0x0F;		//sck高电平准备数据		数据从MCU到中间变量上
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		fourwire_write(split_addr[i],sdi0,sdi1,sdi2,sdi3);	//sck低电平传输数据     数据从中间变量到通信线上
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	}
 	for(i = 0; i < 4;i++)									//16bit数据  4根线分四次传输
 	{
 		split_data[i] = (temp_data>>(4*(3-i)))&0x0F;
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		fourwire_write(split_data[i],sdi0,sdi1,sdi2,sdi3);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	}
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
    fourwire_write(0x00,sdi0,sdi1,sdi2,sdi3);
    //usleep(20);
 }
 /******************************************************************************
 * Function    : u16	fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
 * Description : forwire read from reg
 * Parameter   : sdo0,sdo1,sdo2,sdo3--IO
 * Return      : rxdata--数据
 ******************************************************************************/
 u16	fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
 {
 	u32 GPIO_PIN[4];
 	u16	rdata[4];
 	u16 rxdata = 0;
 	GPIO_PIN[0] = sdo0;
 	GPIO_PIN[1] = sdo1;
 	GPIO_PIN[2] = sdo2;
 	GPIO_PIN[3] = sdo3;
 	for(u8 i = 0; i < 4 ; i++)
 	{
 		rdata[i] = XGpioPs_ReadPin(&psGpioInstancePtr,GPIO_PIN[i]);
 		//xil_printf("rdata[i] = %x\r\n",rdata[i]);
 		rxdata   = ((rdata[i])<<i) + rxdata ;
 	}
 	return	rxdata;
 }
 /******************************************************************************
 * Function    : void spi_read_fourwire(char addr, u16* rxdata, u32* device)
 * Description : spi fourwire read
 * Parameter   : addr   -- 地址
 * 				rxdata -- 数据
 * 				device -- CPLD
 * Return      : void
 ******************************************************************************/
 void spi_read_fourwire(char addr, u16* rxdata, u32* device)   //接收数据使用指针传递，方便接收多个
 {
 	u8    temp_addr = 0;
 	u16   temp_data = 0;
 	u8	  split_addr[2] = {0};	//将8bit地址拆分，分别给4线传输，
 	u16	  split_data[4] = {0};	//16bit数据拆成4个4bit
 	u8    i = 0;
 	u32   sck   = *(device+0);
 	u32	  cs    = *(device+1);
 	u32	  sdio0 = *(device+2);
 	u32	  sdio1 = *(device+3);
 	u32	  sdio2 = *(device+4);
 	u32	  sdio3 = *(device+5);
 	temp_addr = addr;
 	split_addr[0] = (temp_addr >> 4)&0x0F;
 	split_addr[1] = (temp_addr)&0x0F;
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3);     			// w/r标志位    1=w 0=r
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	for(i = 0; i < 2; i++)									// 8bit地址 四根线分两次传输
 	{
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		fourwire_write(split_addr[i],sdio0,sdio1,sdio2,sdio3);	//sck低电平传输数据     数据从中间变量到通信线上
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	}
 	for(i = 0; i < 4; i++)
 	{
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),0);  //input
 	}
 	for(i = 0; i < 4; i++)									//16bit数据  4根线分四次接收
 	{
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		split_data[i] = fourwire_read(sdio0,sdio1,sdio2,sdio3);	//sck低电平准备数据     数据从通信线到中间变量上
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    temp_data = temp_data<<4;
 	    temp_data = temp_data + split_data[i];
 		//temp_data = (split_data[i]<<(4*(3-i))) + temp_data;		//sck高电平接收数据     数据从中间变量到MCU上
 //	    xil_printf("split_data[i],temp_data = %x,%x\r\n",split_data[i],temp_data);
 	}
 	for(i = 0; i < 4; i++)
 	{
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),1);  //output
 	}
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3);
 	*rxdata = temp_data;
    XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
    XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
    XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);//add 2 lines
    //usleep(20);
 }
 /******************************************************************************
 * Function    : void GPIO_dir_set(u32* device,char dir)
 * Description : change GPIO direction
 * Parameter   : device -- CPLD
 * 				dir    -- GPIO_OUT/GPIO_IN
 * Return      : void
 ******************************************************************************/
 void GPIO_dir_set_16(u32* device,char dir)
 {
 	u32   sdio[16] = {0};
 	u8    i;
 	for(i = 0; i < 16;i++)
 	{
 		sdio[i] = *(device+i);
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, sdio[i],1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir);
 	}
 }
 void GPIO_dir_set_cs_enable(u32* device,u8 dir)
 {
 	u32   sdio[4] = {0};
 	u8    i;
 	u8    dir_temp = 0;
 	for(i = 0; i < 4;i++)
 	{
 		sdio[i]  = *(device+i);
 		dir_temp =  (((dir >> (3-i))) & 0x01);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir_temp);
 	}
 }
 void  rst(char *d)
 {
 	XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, *d, 1);
 	usleep(20);
 	XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
 }
 void func_test(void)
 {
 	XGpioPs_Write(&psGpioInstancePtr, 0x03, 0x12345678);
 }
@@ -1,80 +0,0 @@
 /*
 * GPIO_Driv.c
 *
 *  Created on: 2021年5月7日
 *      Author: Administrator
 */
 #include "GPIO_Driv.h"
 XGpioPs psGpioInstancePtr;     //端口
 XGpioPs_Config* GpioConfigPtr; //设备ID
 					//sck,cs,sdi,sdo,rst
 u32 CPLD_U1  [11] = {54,55,56,57,58,59,60,61,62,63,64};
 u32 CPLD_U2  [11] = {65,66,67,68,69,70,71,72,73,74,75};
 u32 CPLD_U3  [11] = {76,77,78,79,80,81,82,83,84,85,86};
 void EMIO_config(void)
 {
 	    int xStatus;
 		GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
 		if(GpioConfigPtr == NULL)
 			return XST_FAILURE;
 		xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
 		if(XST_SUCCESS != xStatus)
 			print(" PS GPIO INIT FAILED \n\r");
 		/*-------------------------------------CPLD_U1------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 1);//57---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 0);//58---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59---sdio3
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60---sdio4
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61---sdio5
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62---sdio6
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63---sdio7
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 1);//57---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 0);//58---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//---sdio3
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//---sdio4
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//---sdio5
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//---sdio6
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//---sdio7
 		/*-------------------------------------CPLD_U2------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 1);//68---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 0);//69---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66---sdio3
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67---sdio4
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67---sdio5
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67---sdio6
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67---sdio7
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
 }
@@ -1,242 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 u8      cpld_addr = 0;
 		 u32     cpld_dat  = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(slot==1)
 		 {
 			 cpld_addr = 0x82;
 		 }
 		 else if(slot==2)
 		 {
 			 cpld_addr = 0x83;
 		 }
 		 else if(slot==3)
 		 {
 			 cpld_addr = 0x84;
 		 }
 		 else
 		 {
 			 cpld_addr = 0x85;
 		 }
 		 switch(ch_num)
 		 {
 		   case 0x0001:
 		 	   {
 		 		   relay_ctrl = 0x00000000;
 		 		   break;
 		 	   }
 		   case 0x0002:
 		   	   {
 		   		   relay_ctrl = 0x00020000;
 		   		   break;
 		   	   }
 		   case 0x0003:
 		   	   {
 		   		   relay_ctrl = 0x00200000;
 		   		   break;
 		   	   }
 		   case 0x0004:
 		   	   {
 		   		   relay_ctrl = 0x00220000;
 		   		   break;
 		   	   }
 		   case 0x0005:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0006:
 		   	   {
 		   		   relay_ctrl = 0x00810000;
 		   		   break;
 		   	   }
 		   case 0x0007:
 		   	   {
 		   		   relay_ctrl = 0x00A00000;
 		   		   break;
 		   	   }
 		   case 0x0008:
 		   	   {
 		   		   relay_ctrl = 0x00A10000;
 		   		   break;
 		   	   }
 		   case 0x0041:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0042:
 		   	   {
 		   		   relay_ctrl = 0x00008000;
 		   		   break;
 		   	   }
 		   case 0x0043:
 		   	   {
 		   		   relay_ctrl = 0x00100000;
 		   		   break;
 		   	   }
 		   case 0x0044:
 		   	   {
 		   		   relay_ctrl = 0x00108000;
 		   		   break;
 		   	   }
 		   case 0x0045:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0046:
 		   	   {
 		   		   relay_ctrl = 0x00804000;
 		   		   break;
 		   	   }
 		   case 0x0047:
 		   	   {
 		   		   relay_ctrl = 0x00900000;
 		   		   break;
 		   	   }
 		   case 0x0048:
 		   	   {
 		   		   relay_ctrl = 0x00904000;
 		   		   break;
 		   	   }
 		   case 0x0081:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0082:
 		   	   {
 		   		   relay_ctrl = 0x00002000;
 		   		   break;
 		   	   }
 		   case 0x0083:
 		   	   {
 		   		   relay_ctrl = 0x00080000;
 		   		   break;
 		   	   }
 		   case 0x0084:
 		   	   {
 		   		   relay_ctrl = 0x00082000;
 		   		   break;
 		   	   }
 		   case 0x0085:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x0086:
 		   	   {
 		   		   relay_ctrl = 0x00401000;
 		   		   break;
 		   	   }
 		   case 0x0087:
 		   	   {
 		   		   relay_ctrl = 0x00480000;
 		   		   break;
 		   	   }
 		   case 0x0088:
 		   	   {
 		   		   relay_ctrl = 0x00481000;
 		   		   break;
 		   	   }
 		   case 0x00C1:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x00C2:
 		   	   {
 		   		   relay_ctrl = 0x00000800;
 		   		   break;
 		   	   }
 		   case 0x00C3:
 		   	   {
 		   		   relay_ctrl = 0x00040000;
 		   		   break;
 		   	   }
 		   case 0x00C4:
 		   	   {
 		   		   relay_ctrl = 0x00040800;
 		   		   break;
 		   	   }
 		   case 0x00C5:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x00C6:
 		   	   {
 		   		   relay_ctrl = 0x00400400;
 		   		   break;
 		   	   }
 		   case 0x00C7:
 		   	   {
 		   		   relay_ctrl = 0x00440000;
 		   		   break;
 		   	   }
 		   case 0x00C8:
 		   	   {
 		   		   relay_ctrl = 0x00440400;
 		   		   break;
 		   	   }
 		 }
 		 ch_num_dat = ((u32)ch_num)<<1;
 		 cpld_dat   = relay_ctrl|ch_num_dat|slot_en;
 		 sw_config_data[0] = (u8)(cpld_dat>>16);
 		 sw_config_data[1] = (u8)(cpld_dat>>8);
 		 sw_config_data[2] = (u8)(cpld_dat);
 		 xil_printf("relay_ctrl: %d\n\r", relay_ctrl);
 		 xil_printf("ch_num_dat: %d\n\r", ch_num_dat);
 		 xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[0]);
 		 xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[1]);
 		 xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[2]);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
 		 sw_config_data[0] = 0x00;
 		 sw_config_data[1] = 0x00;
 		 sw_config_data[2] = 0x01;
 		 spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U1);
 		 spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U2);
 		 spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U3);
 }
@@ -1,108 +0,0 @@
 /*
 * GPIO_Driv.c
 *
 *  Created on: 2021年5月7日
 *      Author: Administrator
 */
 #include "GPIO_Driv.h"
 XGpioPs psGpioInstancePtr;     //端口
 XGpioPs_Config* GpioConfigPtr; //设备ID
 					//sck,cs,sdi,sdo,rst
 u32 CPLD_U1  [11] = {54,55,56,57,58,59,60,61,62,63,64};
 u32 CPLD_U2  [11] = {65,66,67,68,69,70,71,72,73,74,75};
 u32 CPLD_U3  [11] = {76,77,78,79,80,81,82,83,84,85,86};
 void EMIO_config(void)
 {
 	    int xStatus;
 		GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
 		if(GpioConfigPtr == NULL)
 			return XST_FAILURE;
 		xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
 		if(XST_SUCCESS != xStatus)
 			print(" PS GPIO INIT FAILED \n\r");
 		/*-------------------------------------CPLD_U1------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 0);//57---sdo
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 1);//58---rst_n
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);//57---sdo
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);//58---rst_n
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//59
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//60
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//61
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//62
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//63
 		/*-------------------------------------CPLD_U2------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//68---sdo
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//69---rst_n
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//70
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//71
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//72
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//73
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//74
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 1);//68---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 0);//69---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);//70
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);//71
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);//72
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);//73
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);//74
 		/*-------------------------------------CPLD_U3------------------------------------*/
 				//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//76---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//77---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//78---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 1);//79---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 0);//80---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//81
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//82
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//83
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//84
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//85
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//76---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//77---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//78---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 1);//79---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 0);//80---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);//81
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);//82
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);//83
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);//84
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);//85
 }
@@ -1,108 +0,0 @@
 /*
 * GPIO_Driv.c
 *
 *  Created on: 2021年5月7日
 *      Author: Administrator
 */
 #include "GPIO_Driv.h"
 XGpioPs psGpioInstancePtr;     //端口
 XGpioPs_Config* GpioConfigPtr; //设备ID
 					//sck,cs,sdi,sdo,rst
 u32 CPLD_U1  [11] = {54,55,56,57,58,59,60,61,62,63,64};
 u32 CPLD_U2  [11] = {65,66,67,68,69,70,71,72,73,74,75};
 u32 CPLD_U3  [11] = {76,77,78,79,80,81,82,83,84,85,86};
 void EMIO_config(void)
 {
 	    int xStatus;
 		GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
 		if(GpioConfigPtr == NULL)
 			return XST_FAILURE;
 		xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
 		if(XST_SUCCESS != xStatus)
 			print(" PS GPIO INIT FAILED \n\r");
 		/*-------------------------------------CPLD_U1------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 1);//57---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 0);//58---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 1);//57---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 0);//58---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//
 		/*-------------------------------------CPLD_U2------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 1);//68---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 0);//69---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 1);//68---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 0);//69---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
 		/*-------------------------------------CPLD_U3------------------------------------*/
 				//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//65---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//66---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//67---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 1);//68---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 0);//69---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//66
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//67
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//67
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//67
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//67
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 1);//68---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 0);//69---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
 }
@@ -1,223 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start, u32 CPLD_UU[11])
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 u8      cpld_addr = 0;
 		 u32     cpld_dat  = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(slot==1)
 		 {
 			 cpld_addr = 0x82;
 		 }
 		 else if(slot==2)
 		 {
 			 cpld_addr = 0x83;
 		 }
 		 else if(slot==3)
 		 {
 			 cpld_addr = 0x84;
 		 }
 		 else
 		 {
 			 cpld_addr = 0x85;
 		 }
 		 switch(ch_num)
 		 {
 		   case 0x0001:
 		 	   {
 		 		   relay_ctrl = 0x00000000;
 		 		   break;
 		 	   }
 		   case 0x0002:
 		   	   {
 		   		   relay_ctrl = 0x00020000;
 		   		   break;
 		   	   }
 		   case 0x0003:
 		   	   {
 		   		   relay_ctrl = 0x00200000;
 		   		   break;
 		   	   }
 		   case 0x0004:
 		   	   {
 		   		   relay_ctrl = 0x00022000;
 		   		   break;
 		   	   }
 		   case 0x0005:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0006:
 		   	   {
 		   		   relay_ctrl = 0x00810000;
 		   		   break;
 		   	   }
 		   case 0x0007:
 		   	   {
 		   		   relay_ctrl = 0x00A00000;
 		   		   break;
 		   	   }
 		   case 0x0008:
 		   	   {
 		   		   relay_ctrl = 0x00A10000;
 		   		   break;
 		   	   }
 		   case 0x0041:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0042:
 		   	   {
 		   		   relay_ctrl = 0x00008000;
 		   		   break;
 		   	   }
 		   case 0x0043:
 		   	   {
 		   		   relay_ctrl = 0x00100000;
 		   		   break;
 		   	   }
 		   case 0x0044:
 		   	   {
 		   		   relay_ctrl = 0x00108000;
 		   		   break;
 		   	   }
 		   case 0x0045:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0046:
 		   	   {
 		   		   relay_ctrl = 0x00804000;
 		   		   break;
 		   	   }
 		   case 0x0047:
 		   	   {
 		   		   relay_ctrl = 0x00900000;
 		   		   break;
 		   	   }
 		   case 0x0048:
 		   	   {
 		   		   relay_ctrl = 0x00904000;
 		   		   break;
 		   	   }
 		   case 0x0081:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0082:
 		   	   {
 		   		   relay_ctrl = 0x00002000;
 		   		   break;
 		   	   }
 		   case 0x0083:
 		   	   {
 		   		   relay_ctrl = 0x00080000;
 		   		   break;
 		   	   }
 		   case 0x0084:
 		   	   {
 		   		   relay_ctrl = 0x00082000;
 		   		   break;
 		   	   }
 		   case 0x0085:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x0086:
 		   	   {
 		   		   relay_ctrl = 0x00401000;
 		   		   break;
 		   	   }
 		   case 0x0087:
 		   	   {
 		   		   relay_ctrl = 0x00480000;
 		   		   break;
 		   	   }
 		   case 0x0088:
 		   	   {
 		   		   relay_ctrl = 0x00481000;
 		   		   break;
 		   	   }
 		   case 0x00C1:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x00C2:
 		   	   {
 		   		   relay_ctrl = 0x00000800;
 		   		   break;
 		   	   }
 		   case 0x00C3:
 		   	   {
 		   		   relay_ctrl = 0x00040000;
 		   		   break;
 		   	   }
 		   case 0x00C4:
 		   	   {
 		   		   relay_ctrl = 0x00040800;
 		   		   break;
 		   	   }
 		   case 0x00C5:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x00C6:
 		   	   {
 		   		   relay_ctrl = 0x00400400;
 		   		   break;
 		   	   }
 		   case 0x00C7:
 		   	   {
 		   		   relay_ctrl = 0x00440000;
 		   		   break;
 		   	   }
 		   case 0x00C8:
 		   	   {
 		   		   relay_ctrl = 0x00440400;
 		   		   break;
 		   	   }
 		 }
 		 ch_num_dat = ((u32)ch_num)<<1;
 		 cpld_dat  = relay_ctrl|ch_num_dat|slot_en;
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
 }
@@ -1,235 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 u8      cpld_addr = 0;
 		 u32     cpld_dat  = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(slot==1)
 		 {
 			 cpld_addr = 0x82;
 		 }
 		 else if(slot==2)
 		 {
 			 cpld_addr = 0x83;
 		 }
 		 else if(slot==3)
 		 {
 			 cpld_addr = 0x84;
 		 }
 		 else
 		 {
 			 cpld_addr = 0x85;
 		 }
 		 switch(ch_num)
 		 {
 		   case 0x0001:
 		 	   {
 		 		   relay_ctrl = 0x00000000;
 		 		   break;
 		 	   }
 		   case 0x0002:
 		   	   {
 		   		   relay_ctrl = 0x00020000;
 		   		   break;
 		   	   }
 		   case 0x0003:
 		   	   {
 		   		   relay_ctrl = 0x00200000;
 		   		   break;
 		   	   }
 		   case 0x0004:
 		   	   {
 		   		   relay_ctrl = 0x00022000;
 		   		   break;
 		   	   }
 		   case 0x0005:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0006:
 		   	   {
 		   		   relay_ctrl = 0x00810000;
 		   		   break;
 		   	   }
 		   case 0x0007:
 		   	   {
 		   		   relay_ctrl = 0x00A00000;
 		   		   break;
 		   	   }
 		   case 0x0008:
 		   	   {
 		   		   relay_ctrl = 0x00A10000;
 		   		   break;
 		   	   }
 		   case 0x0041:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0042:
 		   	   {
 		   		   relay_ctrl = 0x00008000;
 		   		   break;
 		   	   }
 		   case 0x0043:
 		   	   {
 		   		   relay_ctrl = 0x00100000;
 		   		   break;
 		   	   }
 		   case 0x0044:
 		   	   {
 		   		   relay_ctrl = 0x00108000;
 		   		   break;
 		   	   }
 		   case 0x0045:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0046:
 		   	   {
 		   		   relay_ctrl = 0x00804000;
 		   		   break;
 		   	   }
 		   case 0x0047:
 		   	   {
 		   		   relay_ctrl = 0x00900000;
 		   		   break;
 		   	   }
 		   case 0x0048:
 		   	   {
 		   		   relay_ctrl = 0x00904000;
 		   		   break;
 		   	   }
 		   case 0x0081:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0082:
 		   	   {
 		   		   relay_ctrl = 0x00002000;
 		   		   break;
 		   	   }
 		   case 0x0083:
 		   	   {
 		   		   relay_ctrl = 0x00080000;
 		   		   break;
 		   	   }
 		   case 0x0084:
 		   	   {
 		   		   relay_ctrl = 0x00082000;
 		   		   break;
 		   	   }
 		   case 0x0085:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x0086:
 		   	   {
 		   		   relay_ctrl = 0x00401000;
 		   		   break;
 		   	   }
 		   case 0x0087:
 		   	   {
 		   		   relay_ctrl = 0x00480000;
 		   		   break;
 		   	   }
 		   case 0x0088:
 		   	   {
 		   		   relay_ctrl = 0x00481000;
 		   		   break;
 		   	   }
 		   case 0x00C1:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x00C2:
 		   	   {
 		   		   relay_ctrl = 0x00000800;
 		   		   break;
 		   	   }
 		   case 0x00C3:
 		   	   {
 		   		   relay_ctrl = 0x00040000;
 		   		   break;
 		   	   }
 		   case 0x00C4:
 		   	   {
 		   		   relay_ctrl = 0x00040800;
 		   		   break;
 		   	   }
 		   case 0x00C5:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x00C6:
 		   	   {
 		   		   relay_ctrl = 0x00400400;
 		   		   break;
 		   	   }
 		   case 0x00C7:
 		   	   {
 		   		   relay_ctrl = 0x00440000;
 		   		   break;
 		   	   }
 		   case 0x00C8:
 		   	   {
 		   		   relay_ctrl = 0x00440400;
 		   		   break;
 		   	   }
 		 }
 		 ch_num_dat = ((u32)ch_num)<<1;
 		 cpld_dat   = relay_ctrl|ch_num_dat|slot_en;
 		 sw_config_data[0] = (u8)(cpld_dat>>16);
 		 sw_config_data[1] = (u8)(cpld_dat>>8);
 		 sw_config_data[2] = (u8)(cpld_dat);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
 		 sw_config_data[0] = 0x00;
 		 sw_config_data[1] = 0x00;
 		 sw_config_data[2] = 0x01;
 		 spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U1);
 		 spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U2);
 		 spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U3);
 }
@@ -1,558 +0,0 @@
 /*
 * SPI_Driv.c
 *
 *  Created on: 2021年4月2日
 *      Author: dell
 */
 #include "SPI_Driv.h"
 XGpioPs psGpioInstancePtr;     //端口
 XGpioPs_Config* GpioConfigPtr; //设备ID
 extern u32 K7_U0[16];
 extern u32 molex_4_bank_3[4];
 extern u32 cs_en_bank_3[4];
 /******************************************************************************
 * Function    : void interface_initial(u32* device,u32 num_wire)
 * Description : interface initial
 * Parameter   : device   -- CPLD
 * 				num_wire -- 复位线编号
 * Return      : void
 ******************************************************************************/
 void interface_initial(u32* device)  //wire_num = cs sck sdi/o
 {
 	u32   sck   = *(device+0);
 	u32	  cs    = *(device+1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
 }
 /******************************************************************************
 * Function    : void rst_CPLD(u32* device,u32 num_wire)
 * Description : CPLD reset
 * Parameter   : device   -- CPLD
 * 				num_wire -- 复位线编号
 * Return      : void
 ******************************************************************************/
 void rst_CPLD(u32* device,u32 num_wire) //wire_num = cs sck sdi/o
 {
 	u32	rst_n = *(device+num_wire);
 	XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
 	usleep(2);
 	XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
 }
 /******************************************************************************
 * Function    : void spi_write_onewire(char addr, u32 data, char width, u32* device)
 * Description : spi onewire write
 * Parameter   : addr   -- 地址
 * 				data   -- 数据
 * 				width  -- 数据长度
 * 				device -- CPLD
 * Return      : void
 ******************************************************************************/
 void spi_write_onewire(char addr, char *data, char width, u32* device)
 {
 	char  temp_addr = 0;
 	//u32   temp_data = 0;
 	u32   temp_data = 0;
 	char  i = 0,j=0;
 	u32   sck = *(device+0);
 	u32	  cs= *(device+1);
 	u32   sdi= *(device+2);
 	temp_addr = addr;
 	///temp_data = data;
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs,  0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs,  0);
 	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1);			// w/r标志位    1=w 0=r
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	for(i = 0; i < 8; i++)								// 8bit地址
 	{
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	    if(temp_addr&0x80)
 	    	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据     数据从中间变量到通信线上
 	    else
 	    	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    temp_addr = temp_addr<<1;                       //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
 	}
 	for(j=0;j<width;j++)
 	{
 		temp_data = *(data+j);
 		for(i = 0; i < 8; i++)                             //nbit数据
 		{
 			XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 			XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 			if(temp_data&0x80)							//注意数据位nbit，要从[n-1]取位
 				XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1);
 			else
 				XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 			XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 			XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 			temp_data <<=  1;
 		}
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	}
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs , 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 }
 /******************************************************************************
 * Function    : u32	spi_read_onewire(char addr, char width, u32* device)
 * Description : spi onewire read
 * Parameter   : addr   -- 地址
 * 				data   -- 数据
 * 				width  -- 数据长度
 * 				device -- CPLD
 * Return      : void
 ******************************************************************************/
 u32	spi_read_onewire(char addr, char width, u32* device,char* read_data)
 {
 	char  temp_addr=0;
 	u32	  temp_data=0;
 	char  i=0,j=0;
 	u32   sck = *(device+0);
 	u32	  cs= *(device+1);
 	u32   sdi= *(device+2);
 	u32   sdo= *(device+3);
 	temp_addr = addr;
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);		// w/r标志位    1=w 0=r
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	for(i = 0; i < 8; i++)								// 8bit地址
 	{
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	    if(temp_addr&0x80)
 	    	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据     数据从中间变量到通信线上
 	    else
 	    	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    temp_addr = temp_addr<<1;                       //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
 	}
 	for(j=0; j<width; j++)
 	{
 			for(i = 0; i < 8; i++)                             //nbit数据
 			{
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 				temp_data = temp_data << 1;                     //sck低电平准备数据    准备好数位，此时的数据相当于从右边的FPGA移进MCU(先准备好中间变量)
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 				if(XGpioPs_ReadPin(&psGpioInstancePtr,sdo))    //sck高电平接收数据     数据匹配到准备好的数位，等待一起传递到MCU
 					temp_data = temp_data| 0x00000001;
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 			    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 			}
 	}
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 	read_data[0] = (u8)(temp_data>>16);
 	read_data[1] = (u8)(temp_data>>8);
 	read_data[0] = (u8)(temp_data);
 	return temp_data;
 }
 /******************************************************************************
 * Function    : void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
 * Description : forwire write to reg
 * Parameter   : txdata--数据
 * 				sdi0,sdi1,sdi2,sdi3--IO
 * Return      : void
 ******************************************************************************/
 void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
 {
 	switch(txdata & 0x0F)
 	{
 	   case 0x00:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x01:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x02:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x03:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x04:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x05:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x06:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x07:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
 			   break;
 		   }
 	   case 0x08:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x09:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0A:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0B:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0C:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0D:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0E:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	   case 0x0F:
 		   {
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
 			   XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
 			   break;
 		   }
 	}
 }
 /******************************************************************************
 * Function    : void spi_write_fourwire(char addr, u16 data, u32* device)
 * Description : spi fourwire write
 * Parameter   : addr   -- 地址
 * 				data   -- 数据
 * 				width  -- 数据长度
 *  				device -- CPLD
 * Return      : void
 ******************************************************************************/
 void spi_write_fourwire(char addr, u16 data, u32* device)
 {
 	u8    temp_addr = 0;
 	u16   temp_data = 0;
 	u8	  split_addr[2] = {0};	//将8bit地址拆分，分别给4线传输，
 	u8	  split_data[4] = {0};	//16bit数据拆成4个4bit
 	u8    i;
 	u32   sck   = *(device+0);
 	u32	  cs    = *(device+1);
 	u32	  sdi0 = *(device+2);
 	u32	  sdi1 = *(device+3);
 	u32	  sdi2 = *(device+4);
 	u32	  sdi3 = *(device+5);
 	temp_addr = addr;
 	temp_data = data;
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	fourwire_write(0x01,sdi0,sdi1,sdi2,sdi3);     			// w/r标志位    1=w 0=r
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	for(i = 0; i < 2;i++)									// 8bit地址 四根线分两次传输
 	{
 		split_addr[i] = (temp_addr>>(4*(1-i)))&0x0F;		//sck高电平准备数据		数据从MCU到中间变量上
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		fourwire_write(split_addr[i],sdi0,sdi1,sdi2,sdi3);	//sck低电平传输数据     数据从中间变量到通信线上
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	}
 	for(i = 0; i < 4;i++)									//16bit数据  4根线分四次传输
 	{
 		split_data[i] = (temp_data>>(4*(3-i)))&0x0F;
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		fourwire_write(split_data[i],sdi0,sdi1,sdi2,sdi3);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	}
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
    fourwire_write(0x00,sdi0,sdi1,sdi2,sdi3);
    //usleep(20);
 }
 /******************************************************************************
 * Function    : u16	fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
 * Description : forwire read from reg
 * Parameter   : sdo0,sdo1,sdo2,sdo3--IO
 * Return      : rxdata--数据
 ******************************************************************************/
 u16	fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
 {
 	u32 GPIO_PIN[4];
 	u16	rdata[4];
 	u16 rxdata = 0;
 	GPIO_PIN[0] = sdo0;
 	GPIO_PIN[1] = sdo1;
 	GPIO_PIN[2] = sdo2;
 	GPIO_PIN[3] = sdo3;
 	for(u8 i = 0; i < 4 ; i++)
 	{
 		rdata[i] = XGpioPs_ReadPin(&psGpioInstancePtr,GPIO_PIN[i]);
 		//xil_printf("rdata[i] = %x\r\n",rdata[i]);
 		rxdata   = ((rdata[i])<<i) + rxdata ;
 	}
 	return	rxdata;
 }
 /******************************************************************************
 * Function    : void spi_read_fourwire(char addr, u16* rxdata, u32* device)
 * Description : spi fourwire read
 * Parameter   : addr   -- 地址
 * 				rxdata -- 数据
 * 				device -- CPLD
 * Return      : void
 ******************************************************************************/
 void spi_read_fourwire(char addr, u16* rxdata, u32* device)   //接收数据使用指针传递，方便接收多个
 {
 	u8    temp_addr = 0;
 	u16   temp_data = 0;
 	u8	  split_addr[2] = {0};	//将8bit地址拆分，分别给4线传输，
 	u16	  split_data[4] = {0};	//16bit数据拆成4个4bit
 	u8    i = 0;
 	u32   sck   = *(device+0);
 	u32	  cs    = *(device+1);
 	u32	  sdio0 = *(device+2);
 	u32	  sdio1 = *(device+3);
 	u32	  sdio2 = *(device+4);
 	u32	  sdio3 = *(device+5);
 	temp_addr = addr;
 	split_addr[0] = (temp_addr >> 4)&0x0F;
 	split_addr[1] = (temp_addr)&0x0F;
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3);     			// w/r标志位    1=w 0=r
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	for(i = 0; i < 2; i++)									// 8bit地址 四根线分两次传输
 	{
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		fourwire_write(split_addr[i],sdio0,sdio1,sdio2,sdio3);	//sck低电平传输数据     数据从中间变量到通信线上
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	}
 	for(i = 0; i < 4; i++)
 	{
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),0);  //input
 	}
 	for(i = 0; i < 4; i++)									//16bit数据  4根线分四次接收
 	{
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		split_data[i] = fourwire_read(sdio0,sdio1,sdio2,sdio3);	//sck低电平准备数据     数据从通信线到中间变量上
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    temp_data = temp_data<<4;
 	    temp_data = temp_data + split_data[i];
 		//temp_data = (split_data[i]<<(4*(3-i))) + temp_data;		//sck高电平接收数据     数据从中间变量到MCU上
 //	    xil_printf("split_data[i],temp_data = %x,%x\r\n",split_data[i],temp_data);
 	}
 	for(i = 0; i < 4; i++)
 	{
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),1);  //output
 	}
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3);
 	*rxdata = temp_data;
    XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
    XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
    XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);//add 2 lines
    //usleep(20);
 }
 /******************************************************************************
 * Function    : void GPIO_dir_set(u32* device,char dir)
 * Description : change GPIO direction
 * Parameter   : device -- CPLD
 * 				dir    -- GPIO_OUT/GPIO_IN
 * Return      : void
 ******************************************************************************/
 void GPIO_dir_set_16(u32* device,char dir)
 {
 	u32   sdio[16] = {0};
 	u8    i;
 	for(i = 0; i < 16;i++)
 	{
 		sdio[i] = *(device+i);
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, sdio[i],1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir);
 	}
 }
 void GPIO_dir_set_cs_enable(u32* device,u8 dir)
 {
 	u32   sdio[4] = {0};
 	u8    i;
 	u8    dir_temp = 0;
 	for(i = 0; i < 4;i++)
 	{
 		sdio[i]  = *(device+i);
 		dir_temp =  (((dir >> (3-i))) & 0x01);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir_temp);
 	}
 }
 void  rst(char *d)
 {
 	XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, *d, 1);
 	usleep(20);
 	XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
 }
 void func_test(void)
 {
 	XGpioPs_Write(&psGpioInstancePtr, 0x03, 0x12345678);
 }
@@ -1,108 +0,0 @@
 /*
 * GPIO_Driv.c
 *
 *  Created on: 2021年5月7日
 *      Author: Administrator
 */
 #include "GPIO_Driv.h"
 XGpioPs psGpioInstancePtr;     //端口
 XGpioPs_Config* GpioConfigPtr; //设备ID
 					//sck,cs,sdi,sdo,rst
 u32 CPLD_U1  [11] = {54,55,56,57,58,59,60,61,62,63,64};
 u32 CPLD_U2  [11] = {65,66,67,68,69,70,71,72,73,74,75};
 u32 CPLD_U3  [11] = {76,77,78,79,80,81,82,83,84,85,86};
 void EMIO_config(void)
 {
 	    int xStatus;
 		GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
 		if(GpioConfigPtr == NULL)
 			return XST_FAILURE;
 		xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
 		if(XST_SUCCESS != xStatus)
 			print(" PS GPIO INIT FAILED \n\r");
 		/*-------------------------------------CPLD_U1------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 0);//57---sdo
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 1);//58---rst_n
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);//57---sdo
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);//58---rst_n
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//59
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//60
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//61
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//62
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//63
 		/*-------------------------------------CPLD_U2------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//68---sdo
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//69---rst_n
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//70
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//71
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//72
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//73
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//74
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//67---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//68---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);//69---sdo
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);//66---rst_n
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);//70
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);//71
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);//72
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);//73
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);//74
 		/*-------------------------------------CPLD_U3------------------------------------*/
 				//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//76---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//77---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//78---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 1);//79---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 0);//80---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//81
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//82
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//83
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//84
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//85
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//76---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//77---rst_n
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//78---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 1);//79---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 0);//80---sdo
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);//81
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);//82
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);//83
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);//84
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);//85
 }
@@ -1,77 +0,0 @@
 /*
 * GPIO_Driv.c
 *
 *  Created on: 2021年5月7日
 *      Author: Administrator
 */
 #include "GPIO_Driv.h"
 XGpioPs psGpioInstancePtr;     //端口
 XGpioPs_Config* GpioConfigPtr; //设备ID
 					//sck,cs,sdi,sdo,rst
 u32 CPLD_U1  [11] = {54,55,56,57,58,59,60,61,62,63,64};
 u32 CPLD_U2  [11] = {65,66,67,68,69,70,71,72,73,74,75};
 u32 CPLD_U3  [11] = {76,77,78,79,80,81,82,83,84,85,86};
 void EMIO_config(void)
 {
 	    int xStatus;
 		GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
 		if(GpioConfigPtr == NULL)
 			return XST_FAILURE;
 		xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
 		if(XST_SUCCESS != xStatus)
 			print(" PS GPIO INIT FAILED \n\r");
 		/*-------------------------------------CPLD_U1------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 0);//57---sdo
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 1);//58---rst
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59---sdio3
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60---sdio4
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//60---sdio5
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//60---sdio6
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//60---sdio7
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);
 		/*-------------------------------------CPLD_U2------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//61---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//62---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//63---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//64---sdo
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//65---rst
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66---sdio3
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67---sdio4
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67---sdio5
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67---sdio6
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67---sdio7
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
 }
@@ -1,241 +0,0 @@
 /*
 * cal_meas.c
 *
 *  Created on: 2023Äê7ÔÂ19ÈÕ
 *      Author: dell
 */
 #include "cal_meas.h"
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 void  sw_config(char *slot_start)
 {
 		 char  slot       = (*slot_start);
 		 char  m_fun      = *(slot_start+1);
 		 char  ch_num_h   = *(slot_start+2);
 		 char  ch_num_l   = *(slot_start+3);
 		 char  volt_cur   = *(slot_start+4);
 		 char  load       = *(slot_start+5);
 		 char  memt_areal = *(slot_start+6);
 		 u16 	 ch_num     = 0;
 		 u32     ch_num_dat = 0;
 		 u32     relay_ctrl = 0;
 		 u32     slot_en    = 0x00000001;
 		 u8      cpld_addr = 0;
 		 u32     cpld_dat  = 0;
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
 		 if(slot==1)
 		 {
 			 cpld_addr = 0x82;
 		 }
 		 else if(slot==2)
 		 {
 			 cpld_addr = 0x83;
 		 }
 		 else if(slot==3)
 		 {
 			 cpld_addr = 0x84;
 		 }
 		 else
 		 {
 			 cpld_addr = 0x85;
 		 }
 		 switch(ch_num)
 		 {
 		   case 0x0001:
 		 	   {
 		 		   relay_ctrl = 0x00000000;
 		 		   break;
 		 	   }
 		   case 0x0002:
 		   	   {
 		   		   relay_ctrl = 0x00020000;
 		   		   break;
 		   	   }
 		   case 0x0003:
 		   	   {
 		   		   relay_ctrl = 0x00200000;
 		   		   break;
 		   	   }
 		   case 0x0004:
 		   	   {
 		   		   relay_ctrl = 0x00220000;
 		   		   break;
 		   	   }
 		   case 0x0005:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0006:
 		   	   {
 		   		   relay_ctrl = 0x00810000;
 		   		   break;
 		   	   }
 		   case 0x0007:
 		   	   {
 		   		   relay_ctrl = 0x00A00000;
 		   		   break;
 		   	   }
 		   case 0x0008:
 		   	   {
 		   		   relay_ctrl = 0x00A10000;
 		   		   break;
 		   	   }
 		   case 0x0041:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0042:
 		   	   {
 		   		   relay_ctrl = 0x00008000;
 		   		   break;
 		   	   }
 		   case 0x0043:
 		   	   {
 		   		   relay_ctrl = 0x00100000;
 		   		   break;
 		   	   }
 		   case 0x0044:
 		   	   {
 		   		   relay_ctrl = 0x00108000;
 		   		   break;
 		   	   }
 		   case 0x0045:
 		   	   {
 		   		   relay_ctrl = 0x00800000;
 		   		   break;
 		   	   }
 		   case 0x0046:
 		   	   {
 		   		   relay_ctrl = 0x00804000;
 		   		   break;
 		   	   }
 		   case 0x0047:
 		   	   {
 		   		   relay_ctrl = 0x00900000;
 		   		   break;
 		   	   }
 		   case 0x0048:
 		   	   {
 		   		   relay_ctrl = 0x00904000;
 		   		   break;
 		   	   }
 		   case 0x0081:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x0082:
 		   	   {
 		   		   relay_ctrl = 0x00002000;
 		   		   break;
 		   	   }
 		   case 0x0083:
 		   	   {
 		   		   relay_ctrl = 0x00080000;
 		   		   break;
 		   	   }
 		   case 0x0084:
 		   	   {
 		   		   relay_ctrl = 0x00082000;
 		   		   break;
 		   	   }
 		   case 0x0085:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x0086:
 		   	   {
 		   		   relay_ctrl = 0x00401000;
 		   		   break;
 		   	   }
 		   case 0x0087:
 		   	   {
 		   		   relay_ctrl = 0x00480000;
 		   		   break;
 		   	   }
 		   case 0x0088:
 		   	   {
 		   		   relay_ctrl = 0x00481000;
 		   		   break;
 		   	   }
 		   case 0x00C1:
 		   	   {
 		   		   relay_ctrl = 0x00000000;
 		   		   break;
 		   	   }
 		   case 0x00C2:
 		   	   {
 		   		   relay_ctrl = 0x00000800;
 		   		   break;
 		   	   }
 		   case 0x00C3:
 		   	   {
 		   		   relay_ctrl = 0x00040000;
 		   		   break;
 		   	   }
 		   case 0x00C4:
 		   	   {
 		   		   relay_ctrl = 0x00040800;
 		   		   break;
 		   	   }
 		   case 0x00C5:
 		   	   {
 		   		   relay_ctrl = 0x00400000;
 		   		   break;
 		   	   }
 		   case 0x00C6:
 		   	   {
 		   		   relay_ctrl = 0x00400400;
 		   		   break;
 		   	   }
 		   case 0x00C7:
 		   	   {
 		   		   relay_ctrl = 0x00440000;
 		   		   break;
 		   	   }
 		   case 0x00C8:
 		   	   {
 		   		   relay_ctrl = 0x00440400;
 		   		   break;
 		   	   }
 		 }
 		 //xil_printf("relay_ctrl: %d\n\r", relay_ctrl);
 		 //xil_printf("ch_num_dat: %d\n\r", ch_num_dat);
 		 ch_num_dat = ((u32)ch_num)<<1;
 		 cpld_dat   = relay_ctrl|ch_num_dat|slot_en;
 		 sw_config_data[0] = (u8)(cpld_dat>>16);
 		 sw_config_data[1] = (u8)(cpld_dat>>8);
 		 sw_config_data[2] = (u8)(cpld_dat);
 		 //xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[0]);
 		 //xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[1]);
 		 //xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[2]);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
 		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
 		 sw_config_data[0] = 0x00;
 		 sw_config_data[1] = 0x00;
 		 sw_config_data[2] = 0x01;
 		 spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U1);
 		 spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U2);
 		 spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U3);
 }
@@ -1,78 +0,0 @@
 /*
 * GPIO_Driv.c
 *
 *  Created on: 2021年5月7日
 *      Author: Administrator
 */
 #include "GPIO_Driv.h"
 XGpioPs psGpioInstancePtr;     //端口
 XGpioPs_Config* GpioConfigPtr; //设备ID
 					//sck,cs,sdi,sdo,rst
 u32 CPLD_U1  [11] = {54,55,56,57,58,59,60,61,62,63,64};
 u32 CPLD_U2  [11] = {65,66,67,68,69,70,71,72,73,74,75};
 u32 CPLD_U3  [11] = {76,77,78,79,80,81,82,83,84,85,86};
 void EMIO_config(void)
 {
 	    int xStatus;
 		GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
 		if(GpioConfigPtr == NULL)
 			return XST_FAILURE;
 		xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
 		if(XST_SUCCESS != xStatus)
 			print(" PS GPIO INIT FAILED \n\r");
 		/*-------------------------------------CPLD_U1------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---rst_n
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 1);//57---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 0);//58---sdo
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59---sdio3
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60---sdio4
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61---sdio5
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62---sdio6
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63---sdio7
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---cs
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---sdi
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);//57---sdo
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);//58---rst
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);
 		/*-------------------------------------CPLD_U2------------------------------------*/
 		//--设置EMIO方向
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//61---sck
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//62---cs
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//63---sdi
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//64---sdo
 		XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//65---rst
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66---sdio3
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67---sdio4
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67---sdio5
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67---sdio6
 		//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67---sdio7
 		//使能EMIO输出 1=output 0=input
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);
 		XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
 		//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
 }
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
yuysh	05f7cfa375	Add LWIP CMD Server Stack	2026-06-18 09:59:22 +08:00
yuysh	dcb0ef6159	Add lwip cmd server	2026-06-17 15:47:27 +08:00
Jeremy Shen	6991600083	Add CPLD_Con.c/h: Move CPLD Control Code to seperate file. Add CPLD Read/Write Command.	2026-06-01 10:50:36 +08:00
yuysh	a4abf50594	Fix u_rLoad shifting bug Change char to u8	2026-05-29 18:18:49 +08:00
yuysh	893467bdfe	Add CPLD DC Processing	2026-05-29 14:11:26 +08:00
yuysh	6f02f47407	Moved echo.c -> echo.c.bak Removed lwip support from BSP Added Command_Parser(), CPLD_exec() and CPLD_Write()	2026-05-28 18:39:13 +08:00
yuysh	54777d3fd9	Add Command Parser	2026-05-28 17:46:44 +08:00
yuysh	67faaf25d2	Remove unnecessary tracked files	2026-05-28 17:30:52 +08:00
yuysh	f4150f12fe	Update gitignore	2026-05-28 17:29:55 +08:00
yuysh	0424f932a1	Remove unnecessary tracked files	2026-05-28 17:28:39 +08:00
yuysh	50d16ab13d	Merge branch 'master' of http://mkb.local:3000/yuysh/NewInstrCalBoard_Zynq	2026-05-28 17:04:05 +08:00
yuysh	480f680726	Add UART Debugging code	2026-05-28 17:02:45 +08:00
Jeremy Shen	41aeab4240	Update .gitignore: add universal .metadata/, export/, tempdsa/, RemoteSystemsTempFiles/ patterns	2026-05-28 16:48:33 +08:00
Jeremy Shen	fd6f7b6332	Add general .gitignore for Xilinx Vivado/Vitis/SDK projects Universal patterns using wildcard naming conventions: - .cache/ - Vivado IP cache - .gen//ip//sim/ - Generated sim files - .ip_user_files/sim_scripts/, .ip_user_files/bd/ - IP user artifacts - .sim/ - Simulation directories - .runs/synth_1/ and .runs/impl_1/ - Run outputs (keep control scripts) - .sdk/.metadata/, .sdk/.sdk/ - SDK workspace state - .sdk/RemoteSystemsTempFiles/, .sdk/SDK.log, *.sdk/webtalk/ - SDK logs Preserved: sources, .xpr, .project, .cproject, .xci, .xsa, .bit, .elf, BSP files, run control scripts Removed from index: cache, .metadata, export, tempdsa, RemoteSystemsTempFiles (515 build artifact files) # Conflicts: # Vitis_Classic/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/boot/fsbl.elf # Vitis_Classic/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bsplib/lib/liblwip4.a # Vitis_Classic/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bsplib/lib/libxil.a	2026-05-28 16:46:13 +08:00