NewInstrCalBoard_Zynq

T

Jeremy Shen fd6f7b6332 Add general .gitignore for Xilinx Vivado/Vitis/SDK projects

Universal patterns using wildcard naming conventions:
- *.cache/ - Vivado IP cache
- *.gen/*/ip/*/sim/ - Generated sim files
- *.ip_user_files/sim_scripts/, *.ip_user_files/bd/ - IP user artifacts
- *.sim/ - Simulation directories
- *.runs/synth_1/ and *.runs/impl_1/* - Run outputs (keep control scripts)
- *.sdk/.metadata/, *.sdk/.sdk/ - SDK workspace state
- *.sdk/RemoteSystemsTempFiles/, *.sdk/SDK.log, *.sdk/webtalk/ - SDK logs

Preserved: sources, .xpr, .project, .cproject, .xci, .xsa, .bit, .elf,
           BSP files, run control scripts

Removed from index: cache, .metadata, export, tempdsa, RemoteSystemsTempFiles
(515 build artifact files)

# Conflicts:
#	Vitis_Classic/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/boot/fsbl.elf
#	Vitis_Classic/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bsplib/lib/liblwip4.a
#	Vitis_Classic/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bsplib/lib/libxil.a

2026-05-28 16:46:13 +08:00

Debug_FW.gen/sources_1/bd

Init Commit

2026-05-27 09:56:09 +00:00

Debug_FW.hw

Init Commit

2026-05-27 09:56:09 +00:00

Debug_FW.ip_user_files

Init Commit

2026-05-27 09:56:09 +00:00

Debug_FW.runs

Init Commit