yuysh 893467bdfe Add CPLD DC Processing

2026-05-29 14:11:26 +08:00

Debug_FW.gen/sources_1/bd

Init Commit

2026-05-27 09:56:09 +00:00

Debug_FW.hw

Init Commit

2026-05-27 09:56:09 +00:00

Debug_FW.ip_user_files

Init Commit

2026-05-27 09:56:09 +00:00

Debug_FW.runs

Remove unnecessary tracked files

2026-05-28 17:30:52 +08:00

Debug_FW.sdk

Remove unnecessary tracked files

2026-05-28 17:30:52 +08:00

Debug_FW.srcs

Init Commit

2026-05-27 09:56:09 +00:00

Vitis_Classic

Add CPLD DC Processing

2026-05-29 14:11:26 +08:00

.gitignore

Update gitignore

2026-05-28 17:29:55 +08:00

Debug_FW.xpr

Init Commit

2026-05-27 09:56:09 +00:00

system_wrapper.xsa

Init Commit

2026-05-27 09:56:09 +00:00

S

Description

新仪表校准版Zynq固件

147 MiB

Releases 1

lwip_server

Latest

2026-06-18 03:11:17 +00:00

Languages

C 56.6%

VHDL 32.7%

Verilog 4.7%

Assembly 1.8%

Tcl 1.1%

Other 2.9%