408 lines
18 KiB
Verilog
408 lines
18 KiB
Verilog
module CPLD_Con (
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input i_sys_clk,
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input i_rst_n,
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input i_con_exec,
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// Freq Relay Control
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input [23:0]i_freq_relay1,
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input [23:0]i_freq_relay2,
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input [23:0]i_freq_relay3,
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input [23:0]i_freq_relay4,
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// DC related Control
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input [23:0]i_DC_Con1,
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input [23:0]i_DC_Con2,
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input [23:0]i_DC_Con3,
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input [23:0]i_DC_Con4,
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//Output RELAYs
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output [18:0]o_DMM_EN,
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output o_IO_RC1,
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output [5:0]o_RC_Tx,
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output [31:0]o_PMU_OC_1 ,
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output [31:0]o_PMU_OC_2 ,
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output [31:0]o_PMU_OC_3 ,
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output [31:0]o_PMU_OC_4 ,
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// DMM Mode Sel
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output o_RC_VSel,
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output o_RC_ISel,
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// Force/Sense Control
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output [1:0]o_RC_LOFS,
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// Output RLoad Sel
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output [17:0]o_RC_RLSel,
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// FLAGs
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output o_con_done,
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output o_err
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);
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//Relay Reg
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reg [3:0]OC_x01 ;
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reg [3:0]OC_x17 ;
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reg [18:0]DMM_en ;
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reg[5:0]RC_Tx;
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reg io_RC;
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reg RC_VSel;
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reg RC_ISel;
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reg [1:0]RC_LOFS;
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reg [17:0]RC_RLSel ;
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reg [31:0]PMU_OC_1 ;
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reg [31:0]PMU_OC_2 ;
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reg [31:0]PMU_OC_3 ;
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reg [31:0]PMU_OC_4 ;
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//Condition Tester
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reg [3:0]en_t ;
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reg [3:0]freq_t;
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reg [3:0]dc_t;
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//Flags
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reg exec_flag;
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reg err_flag;
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reg [3:0]freq_slot_flag;
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reg [3:0]dc_slot_flag ;
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reg done_flag;
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//Counter
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reg [15:0]delay_cnt;
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//Shift Counter
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wire [4:0]OC_Shifter1 = i_DC_Con1[8:4]; // Channel Number div 8
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wire [2:0]DMM_Shifter1 = i_DC_Con1[8:7]; // Channel Number div 64
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wire [4:0]RC_RLShifter1 = i_DC_Con1[21:17]; // RC_RL Shifter
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wire [4:0]OC_Shifter2 = i_DC_Con2[8:4]; // Channel Number div 8
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wire [2:0]DMM_Shifter2 = i_DC_Con2[8:7]; // Channel Number div 64
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wire [4:0]RC_RLShifter2 = i_DC_Con2[21:17]; // RC_RL Shifter
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wire [4:0]OC_Shifter3 = i_DC_Con3[8:4]; // Channel Number div 8
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wire [2:0]DMM_Shifter3 = i_DC_Con3[8:7]; // Channel Number div 64
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wire [4:0]RC_RLShifter3 = i_DC_Con3[21:17]; // RC_RL Shifter
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wire [4:0]OC_Shifter4 = i_DC_Con4[8:4]; // Channel Number div 8
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wire [2:0]DMM_Shifter4 = i_DC_Con4[8:7]; // Channel Number div 64
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wire [4:0]RC_RLShifter4 = i_DC_Con4[21:17]; // RC_RL Shifter
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wire [3:0]DC_OC1 = {PMU_OC_4[0],PMU_OC_3[0],PMU_OC_2[0],PMU_OC_1[0]} ;
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wire [3:0]DC_OC17 = {PMU_OC_4[16],PMU_OC_3[16],PMU_OC_2[16],PMU_OC_1[16]} ;
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always @(posedge i_sys_clk) begin
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if (i_rst_n == 1'b0) begin
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delay_cnt <= 'd0;
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end
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else begin
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if (exec_flag == 1'b1) begin
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delay_cnt <= delay_cnt + 1'd1;
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end
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else begin
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delay_cnt <= 'd0;
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end
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end
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end
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//Function Identify
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always @(posedge i_sys_clk) begin
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if (i_rst_n == 1'b0) begin
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en_t <= 'd0;
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freq_t <= 'd0;
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dc_t <= 'd0;
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end
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else begin
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en_t <= (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) + (i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0] );
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freq_t <= i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0];
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dc_t <= i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0];
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end
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end
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// Main Controller Function
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always @(posedge i_sys_clk) begin
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if (i_rst_n == 1'b0) begin
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exec_flag <= 1'b0;
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err_flag <= 1'b0;
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freq_slot_flag <= 'd0;
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dc_slot_flag <= 'd0;
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DMM_en <= 'd0;
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RC_VSel <= 'd1; //Vpk HIGH Disable, LOW Enable
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RC_ISel <= 'd1; //Apk HIGH Disable, LOW Enable
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RC_LOFS <= 'hf; //HIGH Disable, LOW Enable
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RC_RLSel <='hfffff;
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PMU_OC_1 <= 'd0 ;
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PMU_OC_2 <= 'd0 ;
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PMU_OC_3 <= 'd0 ;
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PMU_OC_4 <= 'd0 ;
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done_flag <= 'd1;
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end
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else begin
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if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin
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//To DO: More Sanity Check?
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if (en_t > 'd1) begin //Only ONE Enable bit should be set!
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err_flag <= 1'b1;
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end
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else begin
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exec_flag <= 1'b1;
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done_flag <= 1'b0;
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err_flag <= 1'b0;
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freq_slot_flag[0] <= i_freq_relay1[0];
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freq_slot_flag[1] <= i_freq_relay2[0];
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freq_slot_flag[2] <= i_freq_relay3[0];
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freq_slot_flag[3] <= i_freq_relay4[0];
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RC_Tx <= i_freq_relay4[17:12]; //Special Relay for slot4
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dc_slot_flag[0] <= i_DC_Con1[0];
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dc_slot_flag[1] <= i_DC_Con2[0];
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dc_slot_flag[2] <= i_DC_Con3[0];
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dc_slot_flag[3] <= i_DC_Con4[0];
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end
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end
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else if (exec_flag == 1'b1) begin
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if (freq_t == 1'b1) begin
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io_RC <= i_freq_relay1[0] || i_freq_relay2[0] || i_freq_relay3[0] || i_freq_relay4[0];
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case (freq_slot_flag)
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4'b0001: begin
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if (i_freq_relay1[9:1] < 9) begin
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PMU_OC_1 <= 'd1;
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DMM_en <= 19'b000_0000_0000_0000_0001;
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end
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else if (i_freq_relay1[9:1] < 73) begin
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DMM_en <= 19'b000_0000_0000_0000_0010;
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PMU_OC_1 <= 'd0;
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end
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else if (i_freq_relay1[9:1] < 137) begin
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PMU_OC_1 <= 1'b1 << 16;
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DMM_en <= 19'b000_0000_0000_0000_0100;
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end
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else begin
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DMM_en <= 19'b000_0000_0000_0000_1000;
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PMU_OC_1 <= 'd0;
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end
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end
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4'b0010: begin
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if (i_freq_relay2[9:1] < 9) begin
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PMU_OC_2 <= 'd1;
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DMM_en <= 19'b000_0000_0000_0001_0000;
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end
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else if (i_freq_relay2[9:1] < 73) begin
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DMM_en <= 19'b000_0000_0000_0010_0000;
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PMU_OC_2 <= 'd0;
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end
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else if (i_freq_relay2[9:1] < 137) begin
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PMU_OC_2 <= 1'b1 << 16;
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DMM_en <= 19'b000_0000_0000_0100_0000;
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end
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else begin
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PMU_OC_2 <= 'd0;
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DMM_en <= 19'b000_0000_0000_1000_0000;
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end
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end
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4'b0100: begin
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if (i_freq_relay3[9:1] < 9) begin
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PMU_OC_3 <= 'd1;
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DMM_en <= 19'b000_0000_0001_0000_0000;
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end
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else if ((i_freq_relay3[9:1] > 64)& (i_freq_relay3[9:1] < 73)) begin
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PMU_OC_3 <= 'd0;
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DMM_en <= 19'b000_0000_0010_0000_0000;
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end
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else if (i_freq_relay3[9:1] < 137) begin
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DMM_en <= 19'b000_0000_0100_0000_0000;
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PMU_OC_3 <= 1'b1 << 16;
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end
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else if (i_freq_relay3[9:1] < 201) begin
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PMU_OC_3 <= 'd0;
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DMM_en <= 19'b000_0000_1000_0000_0000;
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end
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end
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4'b1000: begin
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if (i_freq_relay4[9:1] < 9) begin
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PMU_OC_4 <= 'd1;
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DMM_en <= 19'b000_0001_0000_0000_0000;
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end
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else if (i_freq_relay4[9:1] < 72) begin
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DMM_en <= 19'b000_0010_0000_0000_0000;
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PMU_OC_4 <= 'd0;
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end
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else if (i_freq_relay4[9:1] < 137) begin
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PMU_OC_4 <= 1'b1 << 16;
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DMM_en <= 19'b000_0100_0000_0000_0000;
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end
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else begin
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PMU_OC_4 <= 'd0;
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DMM_en <= 19'b000_1000_0000_0000_0000;
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end
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end
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default: begin // You Should NOT be HERE
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PMU_OC_1 <= 'd0;
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PMU_OC_2 <= 'd0;
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PMU_OC_3 <= 'd0;
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PMU_OC_4 <= 'd0;
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DMM_en <= 'd0;
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end
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endcase
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end
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else if (dc_t == 1'b1) begin
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case (dc_slot_flag)
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4'b0001: begin
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//Here Set Mode and F/S
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if (i_DC_Con1[22] == 1'b1) begin
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RC_VSel <= 1'b1; //Select Current
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RC_ISel <= 1'b0;
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RC_LOFS <= 2'b01;
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end
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else begin
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RC_VSel <= 1'b0; //Select Voltage
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RC_ISel <= 1'b1;
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RC_LOFS <= 2'b10;
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end
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//Sanity Check
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if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18) || (i_DC_Con1[9:1] < 1) || (i_DC_Con1[9:1] > 256)) begin
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err_flag <= 1'b1;
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end
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else begin
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RC_RLSel <= (RC_RLShifter1 >= 1 && RC_RLShifter1 <= 18)
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? ~(18'b1 << (RC_RLShifter1 - 1))
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: 18'h3FFFF; //Set RLoad
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if (i_DC_Con1[23] == 1'b0) begin //Select PMU
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PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter1);
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DMM_en <= (19'b000_0000_0000_0000_0001)<<(DMM_Shifter1);
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end
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else if (i_DC_Con1[23] == 1'b1) begin //Select DPS
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end
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end
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end
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4'b0010: begin
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if (i_DC_Con2[22] == 1'b1) begin
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RC_VSel <= 1'b1; //Select Current
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RC_ISel <= 1'b0;
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RC_LOFS <= 2'b01;
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end
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else begin
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RC_VSel <= 1'b0; //Select Voltage
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RC_ISel <= 1'b1;
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RC_LOFS <= 2'b10;
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end
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//Sanity Check
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if ((i_DC_Con2[21:17] < 1) || (i_DC_Con2[21:17] > 18) || (i_DC_Con2[9:1] < 1) || (i_DC_Con2[9:1] > 256)) begin
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err_flag <= 1'b1;
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end
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else begin
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RC_RLSel <= (RC_RLShifter2 >= 1 && RC_RLShifter2 <= 18)
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? ~(18'b1 << (RC_RLShifter2 - 1))
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: 18'h3FFFF; // 否则�1（即不置 0�
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if (i_DC_Con2[23] == 1'b0) begin //Select PMU
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PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter2);
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DMM_en <= (19'b000_0000_0000_0001_0000)<<(DMM_Shifter2);
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end
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else if (i_DC_Con2[23] == 1'b1) begin //Select DPS
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end
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end
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end
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4'b0100:begin
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if (i_DC_Con3[22] == 1'b1) begin
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RC_VSel <= 1'b1; //Select Current
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RC_ISel <= 1'b0;
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RC_LOFS <= 2'b01;
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end
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else begin
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RC_VSel <= 1'b0; //Select Voltage
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RC_ISel <= 1'b1;
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RC_LOFS <= 2'b10;
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end
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//Sanity Check
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if ((i_DC_Con3[21:17] < 1) || (i_DC_Con3[21:17] > 18) || (i_DC_Con3[9:1] < 1) || (i_DC_Con3[9:1] > 256)) begin
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err_flag <= 1'b1;
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end
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else begin
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RC_RLSel <= (RC_RLShifter3 >= 1 && RC_RLShifter3 <= 18)
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? ~(18'b1 << (RC_RLShifter3 - 1))
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: 18'h3FFFF; // 否则�1（即不置 0�
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if (i_DC_Con3[23] == 1'b0) begin //Select PMU
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PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter3);
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DMM_en <= (19'b000_0000_0001_0000_0000)<<(DMM_Shifter3);
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end
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else if (i_DC_Con3[23] == 1'b1) begin //Select DPS
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end
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end
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end
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4'b1000:begin
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if (i_DC_Con4[22] == 1'b1) begin
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RC_VSel <= 1'b1; //Select Current
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RC_ISel <= 1'b0;
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RC_LOFS <= 2'b01;
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end
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else begin
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RC_VSel <= 1'b0; //Select Voltage
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RC_ISel <= 1'b1;
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RC_LOFS <= 2'b10;
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end
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//Sanity Check
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if ((i_DC_Con4[21:17] < 1) || (i_DC_Con4[21:17] > 18) || (i_DC_Con4[9:1] < 1) || (i_DC_Con4[9:1] > 256)) begin
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err_flag <= 1'b1;
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end
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else begin
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RC_RLSel <= (RC_RLShifter4 >= 1 && RC_RLShifter4 <= 18)
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? ~(18'b1 << (RC_RLShifter4 - 1))
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: 18'h3FFFF; // 否则�1（即不置 0�
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if (i_DC_Con4[23] == 1'b0) begin //Select PMU
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PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter4);
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DMM_en <= (19'b000_0001_0000_0000_0000)<<(DMM_Shifter4);
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end
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else if (i_DC_Con4[23] == 1'b1) begin //Select DPS
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end
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end
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end
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default:begin // You Should NOT be HERE
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RC_VSel <= 'd1;
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RC_ISel <= 'd1;
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RC_RLSel <= 'hf;
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RC_LOFS <= 'hf;
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PMU_OC_1 <= 'd0 ;
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PMU_OC_2 <= 'd0 ;
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PMU_OC_3 <= 'd0 ;
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PMU_OC_4 <= 'd0 ;
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DMM_en <= 'd0;
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end
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endcase
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end
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done_flag <= 1'b1;
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end
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end
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if (done_flag == 1) begin
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exec_flag <= 1'b0;
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end
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end
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assign o_con_done = done_flag;
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assign o_err = err_flag;
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assign o_DMM_EN = DMM_en;
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assign o_IO_RC1 = io_RC;
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assign o_RC_Tx = RC_Tx;
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assign o_RC_VSel = RC_VSel;
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assign o_RC_ISel = RC_ISel;
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assign o_RC_LOFS = RC_LOFS;
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assign o_RC_RLSel = RC_RLSel;
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assign o_PMU_OC_1 = PMU_OC_1;
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assign o_PMU_OC_2 = PMU_OC_2;
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assign o_PMU_OC_3 = PMU_OC_3;
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assign o_PMU_OC_4 = PMU_OC_4;
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endmodule |