Add Channel Naming for CPLD2

CPLD1/CPLD_Con.v

@@ -16,8 +16,6 @@ module CPLD_Con (
     input [23:0]i_DC_Con4,
 
     //Output RELAYs
-    output [3:0]o_OC_x01,
-    output [3:0]o_OC_x17,
     output [18:0]o_DMM_EN,
     output o_IO_RC1,
     output [5:0]o_RC_Tx,
@@ -31,6 +29,9 @@ module CPLD_Con (
     output o_RC_VSel,           
     output o_RC_ISel,
 
+//  Force/Sense Control
+    output [1:0]o_RC_LOFS,    
+
 // Output RLoad Sel
     output [17:0]o_RC_RLSel,
 
@@ -47,7 +48,9 @@ module CPLD_Con (
 	reg[5:0]RC_Tx;
     reg io_RC;
 
-    reg RC_VISel;
+    reg RC_VSel;
+    reg RC_ISel;
+    reg [1:0]RC_LOFS;
     reg [17:0]RC_RLSel ;
     reg [31:0]PMU_OC_1 ;
     reg [31:0]PMU_OC_2 ;
@@ -69,15 +72,29 @@ module CPLD_Con (
     //Counter
     reg [15:0]delay_cnt;
 
+//Reg Parsing
     //Shift Counter
     wire [4:0]OC_Shifter1 = i_DC_Con1[8:4];     // Channel Number div 8
     wire [2:0]DMM_Shifter1 = i_DC_Con1[8:7];    // Channel Number div 64
+    wire [4:0]RC_RLShifter1 = i_DC_Con1[21:17]; // RC_RL Shifter
     wire [4:0]OC_Shifter2 = i_DC_Con2[8:4];     // Channel Number div 8
     wire [2:0]DMM_Shifter2 = i_DC_Con2[8:7];    // Channel Number div 64
+    wire [4:0]RC_RLShifter2 = i_DC_Con2[21:17]; // RC_RL Shifter
     wire [4:0]OC_Shifter3 = i_DC_Con3[8:4];     // Channel Number div 8
     wire [2:0]DMM_Shifter3 = i_DC_Con3[8:7];    // Channel Number div 64
+    wire [4:0]RC_RLShifter3 = i_DC_Con3[21:17]; // RC_RL Shifter
     wire [4:0]OC_Shifter4 = i_DC_Con4[8:4];     // Channel Number div 8
     wire [2:0]DMM_Shifter4 = i_DC_Con4[8:7];    // Channel Number div 64
+    wire [4:0]RC_RLShifter4 = i_DC_Con4[21:17]; // RC_RL Shifter
+    
+    //Channels 
+    wire [8:0]Channel_1 = i_DC_Con1[9:1] ;
+    wire [8:0]Channel_2 = i_DC_Con2[9:1] ;
+    wire [8:0]Channel_3 = i_DC_Con3[9:1] ;
+    wire [8:0]Channel_4 = i_DC_Con4[9:1] ;
+
+    wire [3:0]DC_OC1 = {PMU_OC_4[0],PMU_OC_3[0],PMU_OC_2[0],PMU_OC_1[0]} ;
+    wire [3:0]DC_OC17 = {PMU_OC_4[16],PMU_OC_3[16],PMU_OC_2[16],PMU_OC_1[16]} ;
 
     always @(posedge i_sys_clk) begin
         if (i_rst_n == 1'b0) begin
@@ -116,14 +133,15 @@ module CPLD_Con (
             freq_slot_flag <= 'd0;
             dc_slot_flag <= 'd0;
 
-            OC_x01              <= 'd0;
-            OC_x17              <= 'd0;
-
             DMM_en            <= 'd0;
             
-            RC_VISel            <='d0;
+            RC_VSel            <= 'd1;      //Vpk HIGH Disable, LOW Enable
+            RC_ISel            <= 'd1;      //Apk HIGH Disable, LOW Enable
+            RC_LOFS             <= 'hf;      //HIGH Disable, LOW Enable
             RC_RLSel           <='hfffff;
 
+            RC_Tx          <= 'd0 ;
+
             PMU_OC_1       <= 'd0 ;
             PMU_OC_2       <= 'd0 ;
             PMU_OC_3       <= 'd0 ;
@@ -160,96 +178,82 @@ module CPLD_Con (
                     io_RC <= i_freq_relay1[0] || i_freq_relay2[0] || i_freq_relay3[0] || i_freq_relay4[0];
                     case (freq_slot_flag)
                         4'b0001: begin
-                            if (i_freq_relay1[9:1] < 9) begin
+                            if (Channel_1 < 9) begin
-                                OC_x01 <= 4'b0001;
+                                PMU_OC_1 <= 'd1;
-                                OC_x17 <= 'd0;
                                 DMM_en <= 19'b000_0000_0000_0000_0001;
                             end
-                            else if (i_freq_relay1[9:1] < 73) begin
+                            else if (Channel_1 < 73) begin
                                 DMM_en <= 19'b000_0000_0000_0000_0010;
-                                OC_x01 <= 'd0;
+                                PMU_OC_1 <= 'd0;
-                                OC_x17 <= 'd0;
                             end
-                            else if (i_freq_relay1[9:1] < 137) begin
+                            else if (Channel_1 < 137) begin
-                                OC_x17 <= 4'b0001;
+                                PMU_OC_1 <= 1'b1 << 16;
-                                OC_x01 <= 'd0;
                                 DMM_en <= 19'b000_0000_0000_0000_0100;
                             end
                             else begin
                                 DMM_en <= 19'b000_0000_0000_0000_1000;
-                                OC_x01 <= 'd0;
+                                PMU_OC_1 <= 'd0;
-                                OC_x17 <= 'd0;
                             end
                         end
                         4'b0010: begin
-                            if (i_freq_relay2[9:1] < 9) begin
+                            if (Channel_2 < 9) begin
-                                OC_x01 <= 4'b0010;
+                                PMU_OC_2 <= 'd1;
-                                OC_x17 <= 'd0;
                                 DMM_en <= 19'b000_0000_0000_0001_0000;
                             end
-                            else if (i_freq_relay2[9:1] < 73) begin
+                            else if (Channel_2 < 73) begin
                                 DMM_en <= 19'b000_0000_0000_0010_0000;
-                                OC_x01 <= 'd0;
+                                PMU_OC_2 <= 'd0;
-                                OC_x17 <= 'd0;
                             end
-                            else if (i_freq_relay2[9:1] < 137) begin
+                            else if (Channel_2 < 137) begin
-                                OC_x17 <= 4'b0010;
+                                PMU_OC_2 <= 1'b1 << 16;
-                                OC_x01 <= 'd0;
                                 DMM_en <= 19'b000_0000_0000_0100_0000;
                             end
                             else begin
-                                OC_x01 <= 'd0;
+                                PMU_OC_2 <= 'd0;
-                                OC_x17 <= 'd0;
                                 DMM_en <= 19'b000_0000_0000_1000_0000;
                             end
                         end
                         4'b0100: begin
-                            if (i_freq_relay3[9:1] < 9) begin
+                            if (Channel_3 < 9) begin
-                                OC_x01 <= 'b0100;
+                                PMU_OC_3 <= 'd1;
-                                OC_x17 <= 'd0;
                                 DMM_en <= 19'b000_0000_0001_0000_0000;
                             end
-                            else if ((i_freq_relay3[9:1] > 64)& (i_freq_relay3[9:1] < 73)) begin
+                            else if ((Channel_3 > 64)& (Channel_3 < 73)) begin
-                                OC_x01 <= 4'b0000;
+                                PMU_OC_3 <= 'd0;
-                                OC_x17 <= 'd0;
                                 DMM_en <= 19'b000_0000_0010_0000_0000;
                             end
-                            else if (i_freq_relay3[9:1] < 137) begin
+                            else if (Channel_3 < 137) begin
                                 DMM_en <= 19'b000_0000_0100_0000_0000;
-                                OC_x01 <= 'd0;
+                                PMU_OC_3 <= 1'b1 << 16;
-                                OC_x17 <= 'b0100;
                             end
-                            else if (i_freq_relay3[9:1] < 201) begin
+                            else if (Channel_3 < 201) begin
-                                OC_x17 <= 4'd0;
+                                PMU_OC_3 <= 'd0;
-                                OC_x01 <= 'd0;
                                 DMM_en <= 19'b000_0000_1000_0000_0000; 
                             end
                         end
                         4'b1000: begin
-                            if (i_freq_relay4[9:1] < 9) begin
+                            if (Channel_4 < 9) begin
-                                OC_x01 <= 4'b1000;
+                                PMU_OC_4 <= 'd1;
-                                OC_x17 <= 'd0;
                                 DMM_en <= 19'b000_0001_0000_0000_0000;
                             end
-                            else if (i_freq_relay4[9:1] < 72) begin
+                            else if (Channel_4 < 72) begin
                                 DMM_en <= 19'b000_0010_0000_0000_0000;
-                                OC_x01 <= 'd0;
+                                PMU_OC_4 <= 'd0;
-                                OC_x17 <= 'd0;
                             end
-                            else if (i_freq_relay4[9:1] < 137) begin
+                            else if (Channel_4 < 137) begin
-                                OC_x17 <= 4'b1000;
+                                PMU_OC_4 <= 1'b1 << 16;
-                                OC_x01 <= 'd0;
                                 DMM_en <= 19'b000_0100_0000_0000_0000;
                             end
                             else begin
-                                OC_x01 <= 'd0;
+                                PMU_OC_4 <= 'd0;
-                                OC_x17 <= 'd0;
                                 DMM_en <= 19'b000_1000_0000_0000_0000;
                             end
                         end
                         default: begin                                                                                  // You Should NOT be HERE
-                            OC_x01 <= 4'b0000;
+                            PMU_OC_1 <= 'd0;
-                            OC_x17 <= 4'b0000;
+                            PMU_OC_2 <= 'd0;
+                            PMU_OC_3 <= 'd0;
+                            PMU_OC_4 <= 'd0;
                             DMM_en <= 'd0;
                         end
                     endcase
@@ -257,18 +261,25 @@ module CPLD_Con (
                 else if (dc_t == 1'b1) begin
                     case (dc_slot_flag)
                         4'b0001: begin
+                            //Here Set Mode and F/S
                             if (i_DC_Con1[22] == 1'b1) begin
-                                RC_VISel <= 1'b1;                                   //Select Current
+                                RC_VSel <= 1'b1;                                    //Select Current
+                                RC_ISel <= 1'b0;
+                                RC_LOFS <= 2'b01;
                             end
                             else begin
-                                RC_VISel <= 1'b0;                                   //Select Voltage
+                                RC_VSel <= 1'b0;                                    //Select Voltage
+                                RC_ISel <= 1'b1;
+                                RC_LOFS <= 2'b10;
                             end
                             //Sanity Check
-                            if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18) || (i_DC_Con1[9:1] < 1) || (i_DC_Con1[9:1]  > 256)) begin
+                            if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18) || (Channel_1 < 1) || (Channel_1  > 256)) begin
                                 err_flag <= 1'b1;
                             end
                             else begin
-                                RC_RLSel <= ((18'b11_1111_1111_1111_1110)<<(i_DC_Con1[21:17] - 1)) | ((18'b11_1111_1111_1111_1110) >> (18- (i_DC_Con1[21:17] - 1)));
+                                RC_RLSel <= (RC_RLShifter1 >= 1 && RC_RLShifter1 <= 18) 
+                                            ? ~(18'b1 << (RC_RLShifter1 - 1))
+                                            : 18'h3FFFF;                        //Set RLoad
                                 if (i_DC_Con1[23] == 1'b0) begin                //Select PMU
                                     PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter1);        
                                     DMM_en <= (19'b000_0000_0000_0000_0001)<<(DMM_Shifter1);
@@ -280,17 +291,23 @@ module CPLD_Con (
                         end
                         4'b0010: begin
                             if (i_DC_Con2[22] == 1'b1) begin
-                                RC_VISel <= 1'b1;                                   //Select Current
+                                RC_VSel <= 1'b1;                                    //Select Current
+                                RC_ISel <= 1'b0;
+                                RC_LOFS <= 2'b01;
                             end
                             else begin
-                                RC_VISel <= 1'b0;                                   //Select Voltage
+                                RC_VSel <= 1'b0;                                    //Select Voltage
+                                RC_ISel <= 1'b1;
+                                RC_LOFS <= 2'b10;
                             end
                              //Sanity Check
                             if ((i_DC_Con2[21:17] < 1) || (i_DC_Con2[21:17] > 18) || (i_DC_Con2[9:1] < 1) || (i_DC_Con2[9:1]  > 256)) begin
                                 err_flag <= 1'b1;
                             end
                             else begin
-                                RC_RLSel <= ((18'b11_1111_1111_1111_1110)<<(i_DC_Con2[21:17] - 1)) | ((18'b11_1111_1111_1111_1110) >> (18- (i_DC_Con2[21:17] - 1)));
+                                RC_RLSel <= (RC_RLShifter2 >= 1 && RC_RLShifter2 <= 18) 
+                                            ? ~(18'b1 << (RC_RLShifter2 - 1))
+                                            : 18'h3FFFF;   // 否则�1（即不置 0�
                                 if (i_DC_Con2[23] == 1'b0) begin                //Select PMU
                                     PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter2);
                                     DMM_en <= (19'b000_0000_0000_0001_0000)<<(DMM_Shifter2);
@@ -302,17 +319,23 @@ module CPLD_Con (
                         end
                         4'b0100:begin
                             if (i_DC_Con3[22] == 1'b1) begin
-                                RC_VISel <= 1'b1;                                   //Select Current
+                                RC_VSel <= 1'b1;                                    //Select Current
+                                RC_ISel <= 1'b0;
+                                RC_LOFS <= 2'b01;
                             end
                             else begin
-                                RC_VISel <= 1'b0;                                   //Select Voltage
+                                RC_VSel <= 1'b0;                                    //Select Voltage
+                                RC_ISel <= 1'b1;
+                                RC_LOFS <= 2'b10;
                             end
                              //Sanity Check
                             if ((i_DC_Con3[21:17] < 1) || (i_DC_Con3[21:17] > 18) || (i_DC_Con3[9:1] < 1) || (i_DC_Con3[9:1]  > 256)) begin
                                 err_flag <= 1'b1;
                             end
                             else begin
-                                RC_RLSel <= ((18'b11_1111_1111_1111_1110)<<(i_DC_Con3[21:17] - 1)) | ((18'b11_1111_1111_1111_1110) >> (18- (i_DC_Con3[21:17] - 1)));
+                                RC_RLSel <= (RC_RLShifter3 >= 1 && RC_RLShifter3 <= 18) 
+                                            ? ~(18'b1 << (RC_RLShifter3 - 1))
+                                            : 18'h3FFFF;   // 否则�1（即不置 0�
                                 if (i_DC_Con3[23] == 1'b0) begin                //Select PMU
                                     PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter3);
                                     DMM_en <= (19'b000_0000_0001_0000_0000)<<(DMM_Shifter3);
@@ -324,18 +347,49 @@ module CPLD_Con (
                         end
                         4'b1000:begin
                             if (i_DC_Con4[22] == 1'b1) begin
-                                RC_VISel <= 1'b1;                                   //Select Current
+                                RC_VSel <= 1'b1;                                    //Select Current
+                                RC_ISel <= 1'b0;
+                                RC_LOFS <= 2'b01;
                             end
                             else begin
-                                RC_VISel <= 1'b0;                                   //Select Voltage
+                                RC_VSel <= 1'b0;                                    //Select Voltage
+                                RC_ISel <= 1'b1;
+                                RC_LOFS <= 2'b10;
                             end
                              //Sanity Check
                             if ((i_DC_Con4[21:17] < 1) || (i_DC_Con4[21:17] > 18) || (i_DC_Con4[9:1] < 1) || (i_DC_Con4[9:1]  > 256)) begin
                                 err_flag <= 1'b1;
                             end
                             else begin
-                                RC_RLSel <= ((18'b11_1111_1111_1111_1110)<<(i_DC_Con4[21:17] - 1)) | ((18'b11_1111_1111_1111_1110) >> (18- (i_DC_Con4[21:17] - 1)));
+                                RC_RLSel <= (RC_RLShifter4 >= 1 && RC_RLShifter4 <= 18) 
+                                            ? ~(18'b1 << (RC_RLShifter4 - 1))
+                                            : 18'h3FFFF;   // 否则�1（即不置 0�
                                 if (i_DC_Con4[23] == 1'b0) begin                //Select PMU
+                                //Parsing Channel
+                                //We need Speacial Handling for tthe "freq" channels
+                                    if (Channel_4[0] == 1'b0) begin
+                                        if (Channel_4 == 'd66 || Channel_4 == 'd68) begin
+                                            RC_Tx <= 'd1;
+                                        end
+                                        else if (Channel_4 == 'd70 || Channel_4 == 'd72) begin
+                                            RC_Tx <= 6'b00_0010;
+                                        end
+                                        else if (Channel_4 == 'd130 || Channel_4 == 'd132) begin
+                                            RC_Tx <= 6'b00_0100;
+                                        end
+                                        else if (Channel_4 == 'd134 || Channel_4 == 'd136) begin
+                                            RC_Tx <= 6'b00_1000;
+                                        end
+                                        else if (Channel_4 == 'd194 || Channel_4 == 'd196) begin
+                                            RC_Tx <= 6'b01_0000;
+                                        end
+                                        else if (Channel_4 == 'd198 || Channel_4 == 'd200) begin
+                                            RC_Tx <= 6'b10_0000;
+                                        end
+                                        else begin
+                                            RC_Tx <= 'd0;
+                                        end
+                                    end
                                     PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter4);
                                     DMM_en <= (19'b000_0001_0000_0000_0000)<<(DMM_Shifter4);
                                 end
@@ -345,8 +399,10 @@ module CPLD_Con (
                             end
                         end
                         default:begin                           // You Should NOT be HERE
-                            RC_VISel            <='d0;
+                            RC_VSel            <= 'd1;           
-                            RC_RLSel           <='hfffff;
+                            RC_ISel            <= 'd1;
+                            RC_RLSel           <= 'hf;
+                            RC_LOFS            <= 'hf;
 
                             PMU_OC_1       <= 'd0 ;
                             PMU_OC_2       <= 'd0 ;
@@ -365,15 +421,16 @@ module CPLD_Con (
     end 
 
     assign o_con_done = done_flag;
-    assign o_DMM_EN = DMM_en;
-    assign o_OC_x01 = OC_x01;
-    assign o_OC_x17 = OC_x17;
-    assign o_IO_RC1 = io_RC;
     assign o_err = err_flag;
-    assign o_RC_Tx = RC_Tx;
 
-    assign o_RC_ISel = (RC_VISel==1'b1)?1:0;
+    assign o_DMM_EN = DMM_en;
-    assign o_RC_VSel = (RC_VISel==1'b1)?0:1;
+    assign o_IO_RC1 = io_RC;
+    assign o_RC_Tx = RC_Tx; 
+
+    assign o_RC_VSel = RC_VSel;
+    assign o_RC_ISel = RC_ISel;
+
+    assign o_RC_LOFS = RC_LOFS;
 
     assign o_RC_RLSel = RC_RLSel;
 

CPLD1/RelayConTop.v

@@ -79,6 +79,9 @@ module RelayConTop (
 	//DMM I Select
 	wire RC_ISel;
 
+	//Force/Sense Control
+	wire [1:0]RC_LOFS ;
+
 	wire con_rvalid;
 
 	wire con_done;
@@ -139,8 +142,6 @@ module RelayConTop (
 		.i_DC_Con3(DC_Con3),
 		.i_DC_Con4(DC_Con4),
 		.o_con_done(con_done),
-		.o_OC_x01(OC_x01),
-  		.o_OC_x17(OC_x17),
 		.o_RC_Tx(RC_Tx),
   		.o_DMM_EN(DMM_EN),
 		.o_PMU_OC_1(PMU_OC_1),
@@ -149,35 +150,21 @@ module RelayConTop (
 		.o_PMU_OC_4(PMU_OC_4),
     	.o_RC_VSel(RC_VSel),
     	.o_RC_ISel(RC_ISel),
+		.o_RC_LOFS(RC_LOFS),
 		.o_RC_RLSel(RC_RLSel),
   		.o_IO_RC1(IO_RC1),
   		.o_err(cpld_err_flag)
 	);
 
 	assign o_con_done = con_done;
-	//assign o_OC_x01 = OC_x01;
-	assign o_PMU_OC_1[0] = OC_x01[0];
-	assign o_PMU_OC_2[0] = OC_x01[1];
-	assign o_PMU_OC_3[0] = OC_x01[2];
-	assign o_PMU_OC_4[0] = OC_x01[3];
-	
-	//assign o_OC_x17 = OC_x17;
-	assign o_PMU_OC_1[16] = OC_x17[0];
-	assign o_PMU_OC_2[16] = OC_x17[1];
-	assign o_PMU_OC_3[16] = OC_x17[2];
-	assign o_PMU_OC_4[16] = OC_x17[3];
 
-	assign o_PMU_OC_1[15:1] = PMU_OC_1[15:1];
+	assign o_PMU_OC_1 = PMU_OC_1;
-	assign o_PMU_OC_1[31:17] = PMU_OC_1[31:17];
 	
-	assign o_PMU_OC_2[15:1] = PMU_OC_2[15:1];
+	assign o_PMU_OC_2 = PMU_OC_2;
-	assign o_PMU_OC_2[31:17] = PMU_OC_2[31:17];
-	
-	assign o_PMU_OC_3[15:1] = PMU_OC_3[15:1];
-	assign o_PMU_OC_3[31:17] = PMU_OC_3[31:17];
 
-	assign o_PMU_OC_4[15:1] = PMU_OC_4[15:1];
+	assign o_PMU_OC_3 = PMU_OC_3;
-	assign o_PMU_OC_4[31:17] = PMU_OC_4[31:17];
+
+	assign o_PMU_OC_4 = PMU_OC_4;
 
 	assign o_DMM_EN = DMM_EN;
 	assign o_IO_RC1 = IO_RC1;
@@ -193,8 +180,8 @@ module RelayConTop (
 	assign o_RC_VSel = RC_VSel;
 	assign o_RC_ISel = RC_ISel;
 	
-	assign  o_RC_LOF = (RC_VSel == 1'b1)?2'b01:2'b10;						//if Measure V then close RC_LOF[0]
+	assign o_RC_LOF = RC_LOFS;
-	assign  o_RC_LOS = (RC_VSel == 1'b1)?2'b01:2'b10;
+	assign o_RC_LOS = RC_LOFS;
 	
 	assign o_err = bus_err_flag || reg_err_flag ||cpld_err_flag;
 	

CPLD2/BUS_Con.v

@@ -28,7 +28,6 @@ module BUS_Con (
     reg [1:0] mosi_sync;
     
     wire cs_active;
-    wire cs_rise;
     wire sclk_rise; // For Sampling MOSI
     wire sclk_fall; // For Shifting MISO
     wire mosi_data;
@@ -47,7 +46,6 @@ module BUS_Con (
     end
 
     assign cs_active = ~cs_sync[1]; 
-    assign cs_rise   = (!cs_sync[1] && cs_sync[0]); 
     
     // SPI Mode 0: Sample MOSI on Rising, Shift MISO on Falling
     assign sclk_rise = (!sclk_sync[1] && sclk_sync[0]); 
@@ -61,8 +59,9 @@ module BUS_Con (
     reg        err_flag;
 	reg [1:0] state;
 	//
-	reg [31:0] tx_buffer;  // Holds data waiting for the next CS Low
+	reg [31:0] miso_shift; // The actual shifter
-    reg [31:0] miso_shift; // The actual shifter
+    reg        wr_flag;// Flag: 1=W/0=R
+    reg        miso_loaded;
     // Output Registers
     reg [6:0]  addr_out;
     reg [23:0] data_out;
@@ -82,9 +81,10 @@ module BUS_Con (
             bit_cnt       <= 6'd0;
             data_ready    <= 1'b0;
             err_flag      <= 1'b0;
+            wr_flag       <= 1'b1;
         end 
         else begin
-            // Clear data_ready when FSM has consumed the command
+            // Clear data_ready when FSM has consumed the command (CMD_SENT = consumed)
             if (state == CMD_SENT) begin
                 data_ready <= 1'b0;
             end
@@ -92,71 +92,76 @@ module BUS_Con (
             if (cs_active) begin
                 if (sclk_rise) begin
                     recv_reg <= {recv_reg[30:0], mosi_data}; 
-                    if (bit_cnt == 6'd7) begin
+                    bit_cnt  <= bit_cnt + 1'b1;
-                        // 8th bit received: check if read (MSB=0) or write (MSB=1)
+                    
-                        if (recv_reg[0] == 1'b0) begin
+                    // After 8 bits: check WR bit (recv_reg[7] = first bit received)
-                            // Read command: set data_ready after 8 bits
+                    // Read (WR=0): set data_ready early so MISO data is prepared
+                    // Write (WR=1): wait for all 32 bits
+                    if (bit_cnt == 'd7) begin
+                        if (recv_reg[6] == 1'b0) begin
+                            // Read command: signal ready after address received
                             data_ready <= 1'b1;
+                            wr_flag <= 1'b0;
+                        end
+                        else begin
+                            wr_flag <= 1'b1;
                         end
                     end
                     else if (bit_cnt == 6'd31) begin
-                        // 32nd bit received: write command complete
+                        // Write command complete (32 bits received)
                         data_ready <= 1'b1;
                     end
-                    bit_cnt  <= bit_cnt + 1'b1;
+                    
                 end
-				else if (cs_rise) begin
+               else if (!cs_active) begin
-					if (bit_cnt == 6'd32) begin
+                    data_ready <= 1'b0;
-						data_ready <= 1'b1;
+                    if (bit_cnt == 6'd31) begin
-						err_flag   <= 1'b0;
+                        err_flag   <= 1'b0;
-						bit_cnt <= 6'd0;
+                        bit_cnt <= 6'd0;
-					end 
+                    end
-					else if (bit_cnt != 0) begin
+                    else if (bit_cnt != 0 && bit_cnt != 6'd32) begin
-						err_flag   <= 1'b1;
+                        err_flag   <= 1'b1;
-						bit_cnt <= 6'd0;
+                        bit_cnt <= 6'd0;
                         recv_reg <= 'd0;
-					end
+                    end
-				end
+                end
             end
-            if (state == DONE) begin
+            else begin
+                // CS high: reset state
+                bit_cnt <= 6'd0;
                 recv_reg <= 'd0;
-            end
+                data_ready <= 1'b0;
-        end
-    end
-
-    // --- 3. MISO (Transmit) Logic ---
-    // Protocol: We shift out 32 bits. 
-    // Format: [8 bit Status/Padding] + [24 bit i_rdata]
-    
-
-    // Capture data from backend when valid
-    always @(posedge i_sys_clk) begin
-        if (!i_rst_n) begin
-            tx_buffer <= 32'd0;
-        end else begin
-            // If backend provides valid read data, store it.
-            // We pad the top 8 bits with Zeros (or you can put status flags here)
-            if (i_rvalid) begin
-                tx_buffer <= {8'h00, i_rdata}; 
             end
         end
     end
 
-    // Shift data out
+    // --- 3. MISO (Transmit) Logic ---
+    // Protocol: We shift out 32 bits.
+    // Format: [8'h00 padding] + [24 bit i_rdata]
+    // Shift MSB out on each falling edge of SCLK (master samples on rising)
+    // Consolidated: load on first rising edge, shift on falling edges
+
     always @(posedge i_sys_clk) begin
         if (!i_rst_n) begin
-            miso_shift <= 32'd0;
+            miso_shift  <= 32'd0;
-        end else begin
+            miso_loaded <= 1'b0;
+        end 
+        else begin
             if (!cs_active) begin
                 // Reset shifter while CS is High
-                miso_shift <= 32'd0;
+                miso_shift  <= 32'd0;
-            end else if (sclk_fall) begin
-                // Shift on Falling Edge (Master samples on Rising)
-                miso_shift <= {miso_shift[30:0], 1'b0};
             end
-            // Load register data when read completes (takes priority over shift)
+            else begin
-            if (i_rvalid) begin
+                if (i_rvalid && (bit_cnt == 'd8)) begin
-                miso_shift <= {8'h00, i_rdata};
+                    miso_shift  <= {i_rdata,8'd0};
+                    miso_loaded <= 1'b1;
+                end  
+                if (miso_loaded && sclk_fall) begin
+                    // Shift out MSB on falling edges (data valid before master's rising-edge sample)
+                    if (bit_cnt > 'd8) begin
+                        miso_shift <= {miso_shift[30:0], 1'b0};
+                    end
+                end
             end
         end
     end
@@ -166,8 +171,8 @@ module BUS_Con (
     assign o_miso = (cs_active) ? miso_shift[31] : 1'bz;
 
     // --- 4. Register Control FSM ---
-
+    // Command format: [WR:1b][Addr:7b][Data:24b] = 32 bits
-    
+    // recv_reg layout after 32 bits: {WR, Addr[6:0], Data[23:0]}
 
     always @(posedge i_sys_clk) begin
         if (!i_rst_n) begin
@@ -180,9 +185,16 @@ module BUS_Con (
             case (state)
                 IDLE: begin
                     if (data_ready) begin
-                        addr_out      <= recv_reg[30:24];
+                        // Extract fields from received command
-                        data_out      <= recv_reg[23:0];
+                        if (wr_flag == 1'b1) begin
-                        wr_out        <= recv_reg[31];
+                            addr_out      <= recv_reg[30:24];
+                            data_out      <= recv_reg[23:0];
+                            wr_out        <= recv_reg[31];
+                        end
+                        else begin
+                            addr_out      <= recv_reg[6:0];
+                            wr_out        <= recv_reg[7];
+                        end
                         
                         if (!i_reg_busy) begin
                             cmd_valid_out <= 1'b1;

CPLD2/CPLD_Con.v

@@ -59,6 +59,7 @@ module CPLD_Con (
     reg [3:0]dc_slot_flag ;
 	reg err_flag;
 
+
     //Counter
     reg [15:0]delay_cnt;
 
@@ -68,6 +69,12 @@ module CPLD_Con (
     wire [4:0]OC_Shifter3 = i_DC_Con3[8:4];     // Channel Number div 8
     wire [4:0]OC_Shifter4 = i_DC_Con4[8:4];     // Channel Number div 8
 
+    //Channels 
+    wire [8:0]Channel_1 = i_DC_Con1[9:1] ;
+    wire [8:0]Channel_2 = i_DC_Con2[9:1] ;
+    wire [8:0]Channel_3 = i_DC_Con3[9:1] ;
+    wire [8:0]Channel_4 = i_DC_Con4[9:1] ;
+
     wire [8:0] freq_relay1 = i_freq_relay1[9:1];
     wire [8:0] freq_relay2 = i_freq_relay2[9:1];
     wire [8:0] freq_relay3 = i_freq_relay3[9:1];
@@ -249,6 +256,10 @@ module CPLD_Con (
                             end
                             else begin
                                 if (i_DC_Con1[23] == 1'b0) begin                //Select PMU
+                                    //Parsing Channel
+                                    //We need Speacial Handling for tthe "freq" channels
+                                    
+
                                     PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<OC_Shifter1;
                                 end
                                 else if (i_DC_Con1[23] == 1'b1) begin       //Select DPS

CPLD2/RelayConTop.v

@@ -73,7 +73,7 @@ BUS_Con BUS_Con_2(
 		.i_rdata(r_data),
 		.o_cmd_valid(cmd_valid),
 		.o_wr(wr_flag),
-  		.o_miso(o_miso),
+ 		.o_miso(o_miso),
 		.o_rvalid(o_rvalid),
 		.o_wready(o_wready),
 		.o_data(w_data),

CPLD3/BUS_Con.v

@@ -28,7 +28,6 @@ module BUS_Con (
     reg [1:0] mosi_sync;
     
     wire cs_active;
-    wire cs_rise;
     wire sclk_rise; // For Sampling MOSI
     wire sclk_fall; // For Shifting MISO
     wire mosi_data;
@@ -47,7 +46,6 @@ module BUS_Con (
     end
 
     assign cs_active = ~cs_sync[1]; 
-    assign cs_rise   = (!cs_sync[1] && cs_sync[0]); 
     
     // SPI Mode 0: Sample MOSI on Rising, Shift MISO on Falling
     assign sclk_rise = (!sclk_sync[1] && sclk_sync[0]); 
@@ -61,8 +59,9 @@ module BUS_Con (
     reg        err_flag;
 	reg [1:0] state;
 	//
-	reg [31:0] tx_buffer;  // Holds data waiting for the next CS Low
+	reg [31:0] miso_shift; // The actual shifter
-    reg [31:0] miso_shift; // The actual shifter
+    reg        wr_flag;// Flag: 1=W/0=R
+    reg        miso_loaded;
     // Output Registers
     reg [6:0]  addr_out;
     reg [23:0] data_out;
@@ -82,9 +81,10 @@ module BUS_Con (
             bit_cnt       <= 6'd0;
             data_ready    <= 1'b0;
             err_flag      <= 1'b0;
+            wr_flag       <= 1'b1;
         end 
         else begin
-            // Clear data_ready when FSM has consumed the command
+            // Clear data_ready when FSM has consumed the command (CMD_SENT = consumed)
             if (state == CMD_SENT) begin
                 data_ready <= 1'b0;
             end
@@ -92,71 +92,76 @@ module BUS_Con (
             if (cs_active) begin
                 if (sclk_rise) begin
                     recv_reg <= {recv_reg[30:0], mosi_data}; 
-                    if (bit_cnt == 6'd7) begin
+                    bit_cnt  <= bit_cnt + 1'b1;
-                        // 8th bit received: check if read (MSB=0) or write (MSB=1)
+                    
-                        if (recv_reg[0] == 1'b0) begin
+                    // After 8 bits: check WR bit (recv_reg[7] = first bit received)
-                            // Read command: set data_ready after 8 bits
+                    // Read (WR=0): set data_ready early so MISO data is prepared
+                    // Write (WR=1): wait for all 32 bits
+                    if (bit_cnt == 'd7) begin
+                        if (recv_reg[6] == 1'b0) begin
+                            // Read command: signal ready after address received
                             data_ready <= 1'b1;
+                            wr_flag <= 1'b0;
+                        end
+                        else begin
+                            wr_flag <= 1'b1;
                         end
                     end
                     else if (bit_cnt == 6'd31) begin
-                        // 32nd bit received: write command complete
+                        // Write command complete (32 bits received)
                         data_ready <= 1'b1;
                     end
-                    bit_cnt  <= bit_cnt + 1'b1;
+                    
                 end
-				else if (cs_rise) begin
+               else if (!cs_active) begin
-					if (bit_cnt == 6'd32) begin
+                    data_ready <= 1'b0;
-						data_ready <= 1'b1;
+                    if (bit_cnt == 6'd31) begin
-						err_flag   <= 1'b0;
+                        err_flag   <= 1'b0;
-						bit_cnt <= 6'd0;
+                        bit_cnt <= 6'd0;
-					end 
+                    end
-					else if (bit_cnt != 0) begin
+                    else if (bit_cnt != 0 && bit_cnt != 6'd32) begin
-						err_flag   <= 1'b1;
+                        err_flag   <= 1'b1;
-						bit_cnt <= 6'd0;
+                        bit_cnt <= 6'd0;
                         recv_reg <= 'd0;
-					end
+                    end
-				end
+                end
             end
-            if (state == DONE) begin
+            else begin
+                // CS high: reset state
+                bit_cnt <= 6'd0;
                 recv_reg <= 'd0;
-            end
+                data_ready <= 1'b0;
-        end
-    end
-
-    // --- 3. MISO (Transmit) Logic ---
-    // Protocol: We shift out 32 bits. 
-    // Format: [8 bit Status/Padding] + [24 bit i_rdata]
-    
-
-    // Capture data from backend when valid
-    always @(posedge i_sys_clk) begin
-        if (!i_rst_n) begin
-            tx_buffer <= 32'd0;
-        end else begin
-            // If backend provides valid read data, store it.
-            // We pad the top 8 bits with Zeros (or you can put status flags here)
-            if (i_rvalid) begin
-                tx_buffer <= {8'h00, i_rdata}; 
             end
         end
     end
 
-    // Shift data out
+    // --- 3. MISO (Transmit) Logic ---
+    // Protocol: We shift out 32 bits.
+    // Format: [8'h00 padding] + [24 bit i_rdata]
+    // Shift MSB out on each falling edge of SCLK (master samples on rising)
+    // Consolidated: load on first rising edge, shift on falling edges
+
     always @(posedge i_sys_clk) begin
         if (!i_rst_n) begin
-            miso_shift <= 32'd0;
+            miso_shift  <= 32'd0;
-        end else begin
+            miso_loaded <= 1'b0;
+        end 
+        else begin
             if (!cs_active) begin
                 // Reset shifter while CS is High
-                miso_shift <= 32'd0;
+                miso_shift  <= 32'd0;
-            end else if (sclk_fall) begin
-                // Shift on Falling Edge (Master samples on Rising)
-                miso_shift <= {miso_shift[30:0], 1'b0};
             end
-            // Load register data when read completes (takes priority over shift)
+            else begin
-            if (i_rvalid) begin
+                if (i_rvalid && (bit_cnt == 'd8)) begin
-                miso_shift <= {8'h00, i_rdata};
+                    miso_shift  <= {i_rdata,8'd0};
+                    miso_loaded <= 1'b1;
+                end  
+                if (miso_loaded && sclk_fall) begin
+                    // Shift out MSB on falling edges (data valid before master's rising-edge sample)
+                    if (bit_cnt > 'd8) begin
+                        miso_shift <= {miso_shift[30:0], 1'b0};
+                    end
+                end
             end
         end
     end
@@ -166,8 +171,8 @@ module BUS_Con (
     assign o_miso = (cs_active) ? miso_shift[31] : 1'bz;
 
     // --- 4. Register Control FSM ---
-
+    // Command format: [WR:1b][Addr:7b][Data:24b] = 32 bits
-    
+    // recv_reg layout after 32 bits: {WR, Addr[6:0], Data[23:0]}
 
     always @(posedge i_sys_clk) begin
         if (!i_rst_n) begin
@@ -180,9 +185,16 @@ module BUS_Con (
             case (state)
                 IDLE: begin
                     if (data_ready) begin
-                        addr_out      <= recv_reg[30:24];
+                        // Extract fields from received command
-                        data_out      <= recv_reg[23:0];
+                        if (wr_flag == 1'b1) begin
-                        wr_out        <= recv_reg[31];
+                            addr_out      <= recv_reg[30:24];
+                            data_out      <= recv_reg[23:0];
+                            wr_out        <= recv_reg[31];
+                        end
+                        else begin
+                            addr_out      <= recv_reg[6:0];
+                            wr_out        <= recv_reg[7];
+                        end
                         
                         if (!i_reg_busy) begin
                             cmd_valid_out <= 1'b1;

CPLD3/Reg_file.v

@@ -33,7 +33,7 @@ module Reg_file (
     // --- Parameters ---
     localparam REG_COUNT = 16;
     localparam [23:0]
-        IDENT      = 24'h800000 | 12'b0001_1000_0000,            //CPLD3==1,version=1.1.0
+        IDENT      = 24'h800000 | 12'b0001_0001_0000,            //CPLD3==1,version=1.1.0
         STATE_INIT = 24'h800000;
     
     // State Machine Definition