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Fix the SPI MISO logic

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Modify the tb to make it easier from all aspects
This commit is contained in:
Jeremy Shen
2026-06-02 11:23:34 +08:00
parent 070ad1c768
commit ed3fbd7cf5
5 changed files with 252 additions and 791 deletions
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CPLD1/tb_SPI_RegRW/tb_SPI_RegRW.spf
+3 -3
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@@ -1,8 +1,8 @@
<BaliSimProject version="1.3" path="." stage="0" language="-1" name="tb_SPI_RegRW" simType="QuestaSim">
<Source worklib="work" path="RelayConTop.v" type="VERILOG" langstandard="Verilog 2001" include="none"/>
<Source worklib="work" path="BUS_Con.v" type="VERILOG" langstandard="Verilog 2001" include="none"/>
<Source worklib="work" path="Reg_file.v" type="VERILOG" langstandard="Verilog 2001" include="none"/>
<Source worklib="work" path="CPLD_Con.v" type="VERILOG" langstandard="Verilog 2001" include="none"/>
<Source worklib="work" path="Reg_file.v" type="VERILOG" langstandard="Verilog 2001" include="none"/>
<Source worklib="work" path="BUS_Con.v" type="VERILOG" langstandard="Verilog 2001" include="none"/>
<Source worklib="work" path="RelayConTop.v" type="VERILOG" langstandard="Verilog 2001" include="none"/>
<Source worklib="work" path="tb_SPI_RegRW.sv" type="VERILOG" langstandard="System Verilog" include="none"/>
<SimLib value="pmi_work ovi_machxo2"/>
<GlbInc value=""/>