12 lines
805 B
Plaintext
12 lines
805 B
Plaintext
<BaliSimProject version="1.3" path="." stage="0" language="-1" name="tb_SPI_RegRW" simType="QuestaSim">
|
|
<Source worklib="work" path="CPLD_Con.v" type="VERILOG" langstandard="Verilog 2001" include="none"/>
|
|
<Source worklib="work" path="Reg_file.v" type="VERILOG" langstandard="Verilog 2001" include="none"/>
|
|
<Source worklib="work" path="BUS_Con.v" type="VERILOG" langstandard="Verilog 2001" include="none"/>
|
|
<Source worklib="work" path="RelayConTop.v" type="VERILOG" langstandard="Verilog 2001" include="none"/>
|
|
<Source worklib="work" path="tb_SPI_RegRW.sv" type="VERILOG" langstandard="System Verilog" include="none"/>
|
|
<SimLib value="pmi_work ovi_machxo2"/>
|
|
<GlbInc value=""/>
|
|
<Macro value=""/>
|
|
<TopModule instance="" language="" name="tb_SPI_RegRW"/>
|
|
</BaliSimProject>
|