Update gitignore again
This commit is contained in:
Jeremy Shen
+95
-10
@@ -7,17 +7,61 @@
|
||||
# ============================================================
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||||
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||||
# ---------- Build output ----------
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||||
impl1/
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impl1/*
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||||
*_tcr.dir/
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||||
|
||||
# Negate: files inside impl1/ that Diamond needs
|
||||
!*/impl1/*.hub
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||||
|
||||
# ---------- Synthesis (Synplify Pro / Synplify) ----------
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synlog/
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||||
synwork/
|
||||
syntmp/
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||||
*.srp
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||||
*.srm
|
||||
*.srd
|
||||
*.srs
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||||
*.srr
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||||
*.rt.csv
|
||||
*.fdep
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||||
*.szr
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||||
|
||||
# ---------- Implementation (Place & Route) ----------
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||||
*.ncd
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||||
*.par
|
||||
*.ngd
|
||||
*.pad
|
||||
*.fse
|
||||
*.twr
|
||||
*.tw1
|
||||
*.t2b
|
||||
*.p2t
|
||||
*.p3t
|
||||
*.mrp
|
||||
*.mt
|
||||
*.drc
|
||||
*.prf
|
||||
*.prs
|
||||
*.plg
|
||||
*.bgn
|
||||
*.alt
|
||||
*.gcr
|
||||
*.fdepxmr
|
||||
*.schmap
|
||||
|
||||
# ---------- PMI (Physical Model Information) ----------
|
||||
pmi_*/
|
||||
|
||||
# ---------- Auto-generated junk ----------
|
||||
# Lattice intermediate / absolute-path files
|
||||
*.lst
|
||||
*.naf
|
||||
*.tcl
|
||||
*.log
|
||||
*.tlg
|
||||
*.tgl
|
||||
*.CML
|
||||
*.tcl
|
||||
|
||||
# QuestaSim / VCS simulation junk
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||||
# ---------- QuestaSim / VCS simulation junk ----------
|
||||
*.ado
|
||||
*.adf
|
||||
*.cr.mti
|
||||
@@ -26,34 +70,65 @@ impl1/
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*.tops
|
||||
*.dmp
|
||||
*.vcd
|
||||
*.wlf
|
||||
vsim.wlf
|
||||
transcript
|
||||
hdlparser.log
|
||||
*.qdb
|
||||
*.qtl
|
||||
*.qpg
|
||||
*.ngo
|
||||
*.vmake
|
||||
*_info
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||||
work/
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||||
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# HTML reports
|
||||
# ---------- HTML / XML reports ----------
|
||||
*.html
|
||||
*.htm
|
||||
*.xml
|
||||
*.csv
|
||||
*.txt
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||||
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||||
# Generated XML
|
||||
# ---------- Generated / intermediate files ----------
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||||
promote.xml
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reportview.xml
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*.asd
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*.rptmap
|
||||
*.rpt
|
||||
*.tcr
|
||||
|
||||
# Reveal debug (re-generatable)
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# ---------- Reveal debug workspace (re-generatable) ----------
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debug.rvs
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reveal_workspace/
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*.rvp
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|
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# ---------- Bitstream / programming intermediates ----------
|
||||
*.srf
|
||||
*.sdf
|
||||
*.ibs
|
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*.lpc
|
||||
*.duruntime
|
||||
*.xdm
|
||||
*.edi
|
||||
|
||||
# ---------- Backup / temp ----------
|
||||
*.bak
|
||||
|
||||
# ---------- Per-project sub-directories ----------
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||||
# Diamond GUI configs
|
||||
*.ini
|
||||
*.cfg
|
||||
|
||||
# CPLD work directories (simulation artifacts)
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work/
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||||
# ---------- Lattice GUI state ----------
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||||
*.sort
|
||||
*.db
|
||||
|
||||
# ---------- Negate: Lattice Diamond opens project ONLY with these ----------
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||||
|
||||
# Verilog / SystemVerilog / VHDL source
|
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!*.v
|
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!*.sv
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||||
!*.vhd
|
||||
|
||||
# Lattice project definition
|
||||
!*.lpf
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||||
@@ -72,4 +147,14 @@ work/
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|
||||
# Simulation project files (.spf is needed by Diamond's sim engine)
|
||||
!*.spf
|
||||
_math_real.vhd
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||||
|
||||
# Debug / trace
|
||||
!*.hub
|
||||
!*.rvl
|
||||
|
||||
# ---------- Catch-alls (after negations — last matching rule wins) ----------
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||||
# IEEE stdlib VHDL (auto-generated by sim tool, not project source)
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*_math_real*
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*.log.bak.*
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.build_status
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@@ -0,0 +1,81 @@
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----------------------------------------------------------------------
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||||
Report for cell RelayConTop.verilog
|
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||||
Register bits: 769 of 6864 (11%)
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||||
PIC Latch: 0
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||||
I/O cells: 187
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
FD1P3AX 419 100.0
|
||||
FD1P3AY 4 100.0
|
||||
FD1P3IX 148 100.0
|
||||
FD1P3JX 1 100.0
|
||||
FD1S3AX 16 100.0
|
||||
FD1S3IX 14 100.0
|
||||
FD1S3JX 1 100.0
|
||||
GSR 1 100.0
|
||||
IB 5 100.0
|
||||
IFS1P3IX 3 100.0
|
||||
IFS1P3JX 1 100.0
|
||||
INV 2 100.0
|
||||
L6MUX21 72 100.0
|
||||
OB 181 100.0
|
||||
OBZ 1 100.0
|
||||
OFS1P3DX 36 100.0
|
||||
OFS1P3IX 126 100.0
|
||||
ORCALUT4 747 100.0
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PFUMX 104 100.0
|
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PUR 1 100.0
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VHI 4 100.0
|
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VLO 4 100.0
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||||
SUB MODULES
|
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BUS_Con 1 100.0
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CPLD_Con 1 100.0
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Reg_file 1 100.0
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TOTAL 1894
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----------------------------------------------------------------------
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Report for cell CPLD_Con.netlist
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Instance path: CPLD_Con_1
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Cell usage:
|
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cell count Res Usage(%)
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FD1P3IX 18 12.2
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FD1P3JX 1 100.0
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||||
FD1S3AX 12 75.0
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FD1S3IX 5 35.7
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INV 1 50.0
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||||
ORCALUT4 441 59.0
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PFUMX 8 7.7
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VHI 1 25.0
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VLO 1 25.0
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TOTAL 488
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----------------------------------------------------------------------
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Report for cell Reg_file.netlist
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Instance path: CPLD_Reg_1
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Cell usage:
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cell count Res Usage(%)
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||||
FD1P3AX 419 100.0
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||||
FD1P3AY 4 100.0
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||||
FD1S3AX 2 12.5
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||||
L6MUX21 72 100.0
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||||
ORCALUT4 239 32.0
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||||
PFUMX 96 92.3
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||||
VHI 1 25.0
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||||
VLO 1 25.0
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||||
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TOTAL 834
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----------------------------------------------------------------------
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Report for cell BUS_Con.netlist
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||||
Instance path: BUS_Con_1
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||||
Cell usage:
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||||
cell count Res Usage(%)
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||||
FD1P3IX 130 87.8
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FD1S3AX 2 12.5
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||||
FD1S3IX 9 64.3
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||||
FD1S3JX 1 100.0
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||||
ORCALUT4 67 9.0
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||||
VHI 1 25.0
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||||
VLO 1 25.0
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||||
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||||
TOTAL 211
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Binary file not shown.
@@ -0,0 +1 @@
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||||
HUBID_00 REVEAL_0
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,10 @@
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-v
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10
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||||
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||||
-gt
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||||
-sethld
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-sp 4
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-sphld m
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@@ -0,0 +1,135 @@
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||||
[ START MERGED ]
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||||
i_rst_n_c_i i_rst_n_c
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||||
CPLD_Con_1/g0_26_x1 DC_Con3[21]
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||||
[ END MERGED ]
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||||
[ START CLIPPED ]
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||||
GND
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VCC
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[ END CLIPPED ]
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||||
[ START DESIGN PREFS ]
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SCHEMATIC START ;
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||||
# map: version Diamond (64-bit) 3.14.0.75.2 -- WARNING: Map write only section -- Tue May 26 15:47:46 2026
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SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
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||||
LOCATE COMP "o_miso" SITE "AA14" ;
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||||
LOCATE COMP "i_sys_clk" SITE "B9" ;
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||||
LOCATE COMP "o_PMU_OC_4[23]" SITE "C21" ;
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||||
LOCATE COMP "o_PMU_OC_4[22]" SITE "B22" ;
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||||
LOCATE COMP "o_PMU_OC_4[21]" SITE "A21" ;
|
||||
LOCATE COMP "o_PMU_OC_4[20]" SITE "E12" ;
|
||||
LOCATE COMP "o_PMU_OC_4[19]" SITE "C16" ;
|
||||
LOCATE COMP "o_PMU_OC_4[18]" SITE "B16" ;
|
||||
LOCATE COMP "o_PMU_OC_4[17]" SITE "A16" ;
|
||||
LOCATE COMP "o_PMU_OC_4[16]" SITE "C15" ;
|
||||
LOCATE COMP "o_PMU_OC_4[7]" SITE "E15" ;
|
||||
LOCATE COMP "o_PMU_OC_4[6]" SITE "E14" ;
|
||||
LOCATE COMP "o_PMU_OC_4[5]" SITE "D12" ;
|
||||
LOCATE COMP "o_PMU_OC_4[4]" SITE "B19" ;
|
||||
LOCATE COMP "o_PMU_OC_4[3]" SITE "B15" ;
|
||||
LOCATE COMP "o_PMU_OC_4[2]" SITE "B14" ;
|
||||
LOCATE COMP "o_PMU_OC_4[1]" SITE "B13" ;
|
||||
LOCATE COMP "o_PMU_OC_4[0]" SITE "A13" ;
|
||||
LOCATE COMP "o_PMU_OC_3[22]" SITE "B8" ;
|
||||
LOCATE COMP "o_PMU_OC_3[21]" SITE "D8" ;
|
||||
LOCATE COMP "o_PMU_OC_3[20]" SITE "E7" ;
|
||||
LOCATE COMP "o_PMU_OC_3[19]" SITE "D11" ;
|
||||
LOCATE COMP "o_PMU_OC_3[18]" SITE "E10" ;
|
||||
LOCATE COMP "o_PMU_OC_3[17]" SITE "E9" ;
|
||||
LOCATE COMP "o_PMU_OC_3[16]" SITE "E8" ;
|
||||
LOCATE COMP "o_PMU_OC_3[7]" SITE "B20" ;
|
||||
LOCATE COMP "o_PMU_OC_3[6]" SITE "C20" ;
|
||||
LOCATE COMP "o_PMU_OC_3[5]" SITE "E19" ;
|
||||
LOCATE COMP "o_PMU_OC_3[4]" SITE "F19" ;
|
||||
LOCATE COMP "o_PMU_OC_3[3]" SITE "N1" ;
|
||||
LOCATE COMP "o_PMU_OC_3[2]" SITE "N2" ;
|
||||
LOCATE COMP "o_PMU_OC_3[1]" SITE "R1" ;
|
||||
LOCATE COMP "o_PMU_OC_3[0]" SITE "M3" ;
|
||||
LOCATE COMP "o_PMU_OC_2[23]" SITE "G12" ;
|
||||
LOCATE COMP "o_PMU_OC_2[22]" SITE "F13" ;
|
||||
LOCATE COMP "o_PMU_OC_2[21]" SITE "F15" ;
|
||||
LOCATE COMP "o_PMU_OC_2[20]" SITE "G13" ;
|
||||
LOCATE COMP "o_PMU_OC_2[19]" SITE "D18" ;
|
||||
LOCATE COMP "o_PMU_OC_2[18]" SITE "C18" ;
|
||||
LOCATE COMP "o_PMU_OC_2[17]" SITE "A18" ;
|
||||
LOCATE COMP "o_PMU_OC_2[16]" SITE "A17" ;
|
||||
LOCATE COMP "o_PMU_OC_2[7]" SITE "D22" ;
|
||||
LOCATE COMP "o_PMU_OC_2[6]" SITE "D21" ;
|
||||
LOCATE COMP "o_PMU_OC_2[5]" SITE "D20" ;
|
||||
LOCATE COMP "o_PMU_OC_2[4]" SITE "C22" ;
|
||||
LOCATE COMP "o_PMU_OC_2[3]" SITE "G15" ;
|
||||
LOCATE COMP "o_PMU_OC_2[2]" SITE "D16" ;
|
||||
LOCATE COMP "o_PMU_OC_2[1]" SITE "F16" ;
|
||||
LOCATE COMP "o_PMU_OC_2[0]" SITE "E16" ;
|
||||
LOCATE COMP "o_PMU_OC_1[23]" SITE "T5" ;
|
||||
LOCATE COMP "o_PMU_OC_1[22]" SITE "U4" ;
|
||||
LOCATE COMP "o_PMU_OC_1[21]" SITE "R6" ;
|
||||
LOCATE COMP "o_PMU_OC_1[20]" SITE "V4" ;
|
||||
LOCATE COMP "o_PMU_OC_1[19]" SITE "Y7" ;
|
||||
LOCATE COMP "o_PMU_OC_1[18]" SITE "AB6" ;
|
||||
LOCATE COMP "o_PMU_OC_1[17]" SITE "AA7" ;
|
||||
LOCATE COMP "o_PMU_OC_1[16]" SITE "W6" ;
|
||||
LOCATE COMP "o_PMU_OC_1[7]" SITE "J17" ;
|
||||
LOCATE COMP "o_PMU_OC_1[6]" SITE "H16" ;
|
||||
LOCATE COMP "o_PMU_OC_1[5]" SITE "J19" ;
|
||||
LOCATE COMP "o_PMU_OC_1[4]" SITE "G19" ;
|
||||
LOCATE COMP "o_PMU_OC_1[3]" SITE "P20" ;
|
||||
LOCATE COMP "o_PMU_OC_1[2]" SITE "N20" ;
|
||||
LOCATE COMP "o_PMU_OC_1[1]" SITE "R16" ;
|
||||
LOCATE COMP "o_PMU_OC_1[0]" SITE "M19" ;
|
||||
LOCATE COMP "o_RC_LOS[1]" SITE "L6" ;
|
||||
LOCATE COMP "o_RC_LOS[0]" SITE "G4" ;
|
||||
LOCATE COMP "o_RC_LOF[1]" SITE "H4" ;
|
||||
LOCATE COMP "o_RC_LOF[0]" SITE "F3" ;
|
||||
LOCATE COMP "o_RC_ISel" SITE "P6" ;
|
||||
LOCATE COMP "o_RC_VSel" SITE "L7" ;
|
||||
LOCATE COMP "o_RC_RLSel[17]" SITE "N5" ;
|
||||
LOCATE COMP "o_RC_RLSel[16]" SITE "D9" ;
|
||||
LOCATE COMP "o_RC_RLSel[15]" SITE "F11" ;
|
||||
LOCATE COMP "o_RC_RLSel[14]" SITE "B4" ;
|
||||
LOCATE COMP "o_RC_RLSel[13]" SITE "A5" ;
|
||||
LOCATE COMP "o_RC_RLSel[12]" SITE "B11" ;
|
||||
LOCATE COMP "o_RC_RLSel[11]" SITE "A3" ;
|
||||
LOCATE COMP "o_RC_RLSel[10]" SITE "C5" ;
|
||||
LOCATE COMP "o_RC_RLSel[9]" SITE "F8" ;
|
||||
LOCATE COMP "o_RC_RLSel[8]" SITE "B7" ;
|
||||
LOCATE COMP "o_RC_RLSel[7]" SITE "C8" ;
|
||||
LOCATE COMP "o_RC_RLSel[6]" SITE "F6" ;
|
||||
LOCATE COMP "o_RC_RLSel[5]" SITE "G10" ;
|
||||
LOCATE COMP "o_RC_RLSel[4]" SITE "F5" ;
|
||||
LOCATE COMP "o_RC_RLSel[3]" SITE "P3" ;
|
||||
LOCATE COMP "o_RC_RLSel[2]" SITE "B10" ;
|
||||
LOCATE COMP "o_RC_RLSel[1]" SITE "M4" ;
|
||||
LOCATE COMP "o_RC_RLSel[0]" SITE "M6" ;
|
||||
LOCATE COMP "o_RC_T32" SITE "V11" ;
|
||||
LOCATE COMP "o_RC_T31" SITE "U11" ;
|
||||
LOCATE COMP "o_RC_T30" SITE "T11" ;
|
||||
LOCATE COMP "o_RC_T29" SITE "T12" ;
|
||||
LOCATE COMP "o_RC_T28" SITE "U12" ;
|
||||
LOCATE COMP "o_RC_T27" SITE "U13" ;
|
||||
LOCATE COMP "o_IO_RC1" SITE "F10" ;
|
||||
LOCATE COMP "o_DMM_EN[18]" SITE "T10" ;
|
||||
LOCATE COMP "o_DMM_EN[17]" SITE "U10" ;
|
||||
LOCATE COMP "o_DMM_EN[16]" SITE "W11" ;
|
||||
LOCATE COMP "o_DMM_EN[15]" SITE "V13" ;
|
||||
LOCATE COMP "o_DMM_EN[14]" SITE "Y12" ;
|
||||
LOCATE COMP "o_DMM_EN[13]" SITE "V12" ;
|
||||
LOCATE COMP "o_DMM_EN[12]" SITE "W12" ;
|
||||
LOCATE COMP "o_DMM_EN[11]" SITE "F12" ;
|
||||
LOCATE COMP "o_DMM_EN[10]" SITE "C13" ;
|
||||
LOCATE COMP "o_DMM_EN[9]" SITE "D14" ;
|
||||
LOCATE COMP "o_DMM_EN[8]" SITE "D15" ;
|
||||
LOCATE COMP "o_DMM_EN[7]" SITE "AB13" ;
|
||||
LOCATE COMP "o_DMM_EN[6]" SITE "AA12" ;
|
||||
LOCATE COMP "o_DMM_EN[5]" SITE "AA11" ;
|
||||
LOCATE COMP "o_DMM_EN[4]" SITE "AB10" ;
|
||||
LOCATE COMP "o_DMM_EN[3]" SITE "C17" ;
|
||||
LOCATE COMP "o_DMM_EN[2]" SITE "D17" ;
|
||||
LOCATE COMP "o_DMM_EN[1]" SITE "E17" ;
|
||||
LOCATE COMP "o_DMM_EN[0]" SITE "F17" ;
|
||||
LOCATE COMP "o_err" SITE "AB16" ;
|
||||
LOCATE COMP "i_cs" SITE "AB11" ;
|
||||
LOCATE COMP "i_mosi" SITE "AB12" ;
|
||||
LOCATE COMP "i_sclk" SITE "AA10" ;
|
||||
LOCATE COMP "i_rst_n" SITE "Y14" ;
|
||||
SCHEMATIC END ;
|
||||
[ END DESIGN PREFS ]
|
||||
@@ -0,0 +1,40 @@
|
||||
---------------------------------------------------
|
||||
Report for cell RelayConTop
|
||||
Instance path: RelayConTop
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 401.00 100.0
|
||||
IOLGC 165.00 100.0
|
||||
LUT4 747.00 100.0
|
||||
IOREG 165 100.0
|
||||
IOBUF 187 100.0
|
||||
PFUREG 604 100.0
|
||||
SUB MODULES
|
||||
cell count SLC Usage(%)
|
||||
Reg_file 1 53.8
|
||||
CPLD_Con 1 31.0
|
||||
BUS_Con 1 15.1
|
||||
---------------------------------------------------
|
||||
Report for cell CPLD_Con
|
||||
Instance path: RelayConTop/CPLD_Con_1
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 124.30 31.0
|
||||
LUT4 441.00 59.0
|
||||
PFUREG 36 6.0
|
||||
---------------------------------------------------
|
||||
Report for cell Reg_file
|
||||
Instance path: RelayConTop/CPLD_Reg_1
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 215.78 53.8
|
||||
LUT4 239.00 32.0
|
||||
PFUREG 425 70.4
|
||||
---------------------------------------------------
|
||||
Report for cell BUS_Con
|
||||
Instance path: RelayConTop/BUS_Con_1
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 60.58 15.1
|
||||
LUT4 67.00 9.0
|
||||
PFUREG 142 23.5
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,21 @@
|
||||
#
|
||||
# Logical Preferences generated for Lattice by Synplify map202309lat, Build 191R.
|
||||
#
|
||||
|
||||
# Period Constraints
|
||||
#FREQUENCY PORT "i_sys_clk" 200.0 MHz;
|
||||
|
||||
|
||||
# Output Constraints
|
||||
|
||||
# Input Constraints
|
||||
|
||||
# Point-to-point Delay Constraints
|
||||
|
||||
|
||||
|
||||
# Block Path Constraints
|
||||
|
||||
BLOCK ASYNCPATHS;
|
||||
|
||||
# End of generated Logical Preferences.
|
||||
@@ -0,0 +1 @@
|
||||
-link -encrypt -top RelayConTop -osyn /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/impl1/synwork/NewExtIns_CPLD1_impl1_comp.srs /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/impl1/synwork/layer0.srs -jobname linker
|
||||
@@ -0,0 +1,52 @@
|
||||
<?xml version='1.0' encoding='utf-8' ?>
|
||||
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
|
||||
<ispXCF version="3.12">
|
||||
<Comment></Comment>
|
||||
<Chain>
|
||||
<Comm>JTAG</Comm>
|
||||
<Device>
|
||||
<SelectedProg value="TRUE"/>
|
||||
<Pos>1</Pos>
|
||||
<Vendor>Lattice</Vendor>
|
||||
<Family>MachXO2</Family>
|
||||
<Name>LCMXO2-7000HC</Name>
|
||||
<IDCode>0x012bd043</IDCode>
|
||||
<Package>All</Package>
|
||||
<PON>LCMXO2-7000HC</PON>
|
||||
<Bypass>
|
||||
<InstrLen>8</InstrLen>
|
||||
<InstrVal>11111111</InstrVal>
|
||||
<BScanLen>1</BScanLen>
|
||||
<BScanVal>0</BScanVal>
|
||||
</Bypass>
|
||||
<File>D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/impl1/NewExtIns_CPLD1_impl1.jed</File>
|
||||
<FileTime>01/19/26 12:45:04</FileTime>
|
||||
<JedecChecksum>0x75FB</JedecChecksum>
|
||||
<Operation>FLASH Erase,Program,Verify</Operation>
|
||||
<Option>
|
||||
<SVFVendor>JTAG STANDARD</SVFVendor>
|
||||
<IOState>HighZ</IOState>
|
||||
<PreloadLength>664</PreloadLength>
|
||||
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
|
||||
<TCKFrequency>1.000000 MHz</TCKFrequency>
|
||||
<SVFProcessor>SVF Processor</SVFProcessor>
|
||||
<Usercode>0x00000000</Usercode>
|
||||
<AccessMode>FLASH</AccessMode>
|
||||
</Option>
|
||||
</Device>
|
||||
</Chain>
|
||||
<ProjectOptions>
|
||||
<Program>SEQUENTIAL</Program>
|
||||
<Process>ENTIRED CHAIN</Process>
|
||||
<OperationOverride>No Override</OperationOverride>
|
||||
<StartTAP>TLR</StartTAP>
|
||||
<EndTAP>TLR</EndTAP>
|
||||
<VerifyUsercode value="FALSE"/>
|
||||
<TCKDelay>1</TCKDelay>
|
||||
</ProjectOptions>
|
||||
<CableOptions>
|
||||
<CableName>USB</CableName>
|
||||
<PortAdd>EzUSB-0</PortAdd>
|
||||
<USBID>\\?\usb#vid_1134&amp;pid_8001#9&amp;2fe42d87&amp;0&amp;2#</USBID>
|
||||
</CableOptions>
|
||||
</ispXCF>
|
||||
@@ -0,0 +1,227 @@
|
||||
(edif pmi_distributed_dpramXbnoner212pb07f9c9
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2026 1 13 11 1 36)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
|
||||
(comment "C:/lscc/diamond/3.14/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 2 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner212pb07f9c9 -pmi ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
(numberDefinition))
|
||||
(cell FD1P3DX
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port D
|
||||
(direction INPUT))
|
||||
(port SP
|
||||
(direction INPUT))
|
||||
(port CK
|
||||
(direction INPUT))
|
||||
(port CD
|
||||
(direction INPUT))
|
||||
(port Q
|
||||
(direction OUTPUT)))))
|
||||
(cell ROM16X1A
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port AD3
|
||||
(direction INPUT))
|
||||
(port AD2
|
||||
(direction INPUT))
|
||||
(port AD1
|
||||
(direction INPUT))
|
||||
(port AD0
|
||||
(direction INPUT))
|
||||
(port DO0
|
||||
(direction OUTPUT)))))
|
||||
(cell DPR16X4C
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port DI0
|
||||
(direction INPUT))
|
||||
(port DI1
|
||||
(direction INPUT))
|
||||
(port DI2
|
||||
(direction INPUT))
|
||||
(port DI3
|
||||
(direction INPUT))
|
||||
(port WCK
|
||||
(direction INPUT))
|
||||
(port WRE
|
||||
(direction INPUT))
|
||||
(port RAD0
|
||||
(direction INPUT))
|
||||
(port RAD1
|
||||
(direction INPUT))
|
||||
(port RAD2
|
||||
(direction INPUT))
|
||||
(port RAD3
|
||||
(direction INPUT))
|
||||
(port WAD0
|
||||
(direction INPUT))
|
||||
(port WAD1
|
||||
(direction INPUT))
|
||||
(port WAD2
|
||||
(direction INPUT))
|
||||
(port WAD3
|
||||
(direction INPUT))
|
||||
(port DO0
|
||||
(direction OUTPUT))
|
||||
(port DO1
|
||||
(direction OUTPUT))
|
||||
(port DO2
|
||||
(direction OUTPUT))
|
||||
(port DO3
|
||||
(direction OUTPUT)))))
|
||||
(cell VHI
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell pmi_distributed_dpramXbnoner212pb07f9c9
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port (array (rename WrAddress "WrAddress(0:0)") 1)
|
||||
(direction INPUT))
|
||||
(port (array (rename Data "Data(1:0)") 2)
|
||||
(direction INPUT))
|
||||
(port WrClock
|
||||
(direction INPUT))
|
||||
(port WE
|
||||
(direction INPUT))
|
||||
(port WrClockEn
|
||||
(direction INPUT))
|
||||
(port (array (rename RdAddress "RdAddress(0:0)") 1)
|
||||
(direction INPUT))
|
||||
(port RdClock
|
||||
(direction INPUT))
|
||||
(port RdClockEn
|
||||
(direction INPUT))
|
||||
(port Reset
|
||||
(direction INPUT))
|
||||
(port (array (rename Q "Q(1:0)") 2)
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance LUT4_0
|
||||
(viewRef view1
|
||||
(cellRef ROM16X1A))
|
||||
(property initval
|
||||
(string "0x8000")))
|
||||
(instance FF_1
|
||||
(viewRef view1
|
||||
(cellRef FD1P3DX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance FF_0
|
||||
(viewRef view1
|
||||
(cellRef FD1P3DX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance scuba_vhi_inst
|
||||
(viewRef view1
|
||||
(cellRef VHI)))
|
||||
(instance mem_0_0
|
||||
(viewRef view1
|
||||
(cellRef DPR16X4C))
|
||||
(property MEM_INIT_FILE
|
||||
(string "(0-1)(0-1)"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "pmi_distributed_dpramXbnoner212pb07f9c9__PMI__2__2__2B"))
|
||||
(property COMP
|
||||
(string "mem_0_0"))
|
||||
(property initval
|
||||
(string "0x0000000000000000")))
|
||||
(net dataout1_ffin
|
||||
(joined
|
||||
(portRef DO1 (instanceRef mem_0_0))
|
||||
(portRef D (instanceRef FF_1))))
|
||||
(net dataout0_ffin
|
||||
(joined
|
||||
(portRef DO0 (instanceRef mem_0_0))
|
||||
(portRef D (instanceRef FF_0))))
|
||||
(net dec0_wre3
|
||||
(joined
|
||||
(portRef WRE (instanceRef mem_0_0))
|
||||
(portRef DO0 (instanceRef LUT4_0))))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))
|
||||
(portRef AD0 (instanceRef LUT4_0))
|
||||
(portRef AD1 (instanceRef LUT4_0))
|
||||
(portRef RAD3 (instanceRef mem_0_0))
|
||||
(portRef RAD2 (instanceRef mem_0_0))
|
||||
(portRef RAD1 (instanceRef mem_0_0))
|
||||
(portRef WAD3 (instanceRef mem_0_0))
|
||||
(portRef WAD2 (instanceRef mem_0_0))
|
||||
(portRef WAD1 (instanceRef mem_0_0))
|
||||
(portRef DI3 (instanceRef mem_0_0))
|
||||
(portRef DI2 (instanceRef mem_0_0))))
|
||||
(net dataout1
|
||||
(joined
|
||||
(portRef (member Q 0))
|
||||
(portRef Q (instanceRef FF_1))))
|
||||
(net dataout0
|
||||
(joined
|
||||
(portRef (member Q 1))
|
||||
(portRef Q (instanceRef FF_0))))
|
||||
(net reset
|
||||
(joined
|
||||
(portRef Reset)
|
||||
(portRef CD (instanceRef FF_1))
|
||||
(portRef CD (instanceRef FF_0))))
|
||||
(net rden
|
||||
(joined
|
||||
(portRef RdClockEn)
|
||||
(portRef SP (instanceRef FF_1))
|
||||
(portRef SP (instanceRef FF_0))))
|
||||
(net rdclk
|
||||
(joined
|
||||
(portRef RdClock)
|
||||
(portRef CK (instanceRef FF_1))
|
||||
(portRef CK (instanceRef FF_0))))
|
||||
(net raddr0
|
||||
(joined
|
||||
(portRef (member RdAddress 0))
|
||||
(portRef RAD0 (instanceRef mem_0_0))))
|
||||
(net cken
|
||||
(joined
|
||||
(portRef WrClockEn)
|
||||
(portRef AD2 (instanceRef LUT4_0))))
|
||||
(net wren
|
||||
(joined
|
||||
(portRef WE)
|
||||
(portRef AD3 (instanceRef LUT4_0))))
|
||||
(net clk
|
||||
(joined
|
||||
(portRef WrClock)
|
||||
(portRef WCK (instanceRef mem_0_0))))
|
||||
(net datain1
|
||||
(joined
|
||||
(portRef (member Data 0))
|
||||
(portRef DI1 (instanceRef mem_0_0))))
|
||||
(net datain0
|
||||
(joined
|
||||
(portRef (member Data 1))
|
||||
(portRef DI0 (instanceRef mem_0_0))))
|
||||
(net waddr0
|
||||
(joined
|
||||
(portRef (member WrAddress 0))
|
||||
(portRef WAD0 (instanceRef mem_0_0))))))))
|
||||
(design pmi_distributed_dpramXbnoner212pb07f9c9
|
||||
(cellRef pmi_distributed_dpramXbnoner212pb07f9c9
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
@@ -0,0 +1,233 @@
|
||||
(edif pmi_distributed_dpramXbnoner224pb08036b
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2026 5 14 15 11 48)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
|
||||
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 4 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner224pb08036b -pmi ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
(numberDefinition))
|
||||
(cell FD1P3DX
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port D
|
||||
(direction INPUT))
|
||||
(port SP
|
||||
(direction INPUT))
|
||||
(port CK
|
||||
(direction INPUT))
|
||||
(port CD
|
||||
(direction INPUT))
|
||||
(port Q
|
||||
(direction OUTPUT)))))
|
||||
(cell ROM16X1A
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port AD3
|
||||
(direction INPUT))
|
||||
(port AD2
|
||||
(direction INPUT))
|
||||
(port AD1
|
||||
(direction INPUT))
|
||||
(port AD0
|
||||
(direction INPUT))
|
||||
(port DO0
|
||||
(direction OUTPUT)))))
|
||||
(cell DPR16X4C
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port DI0
|
||||
(direction INPUT))
|
||||
(port DI1
|
||||
(direction INPUT))
|
||||
(port DI2
|
||||
(direction INPUT))
|
||||
(port DI3
|
||||
(direction INPUT))
|
||||
(port WCK
|
||||
(direction INPUT))
|
||||
(port WRE
|
||||
(direction INPUT))
|
||||
(port RAD0
|
||||
(direction INPUT))
|
||||
(port RAD1
|
||||
(direction INPUT))
|
||||
(port RAD2
|
||||
(direction INPUT))
|
||||
(port RAD3
|
||||
(direction INPUT))
|
||||
(port WAD0
|
||||
(direction INPUT))
|
||||
(port WAD1
|
||||
(direction INPUT))
|
||||
(port WAD2
|
||||
(direction INPUT))
|
||||
(port WAD3
|
||||
(direction INPUT))
|
||||
(port DO0
|
||||
(direction OUTPUT))
|
||||
(port DO1
|
||||
(direction OUTPUT))
|
||||
(port DO2
|
||||
(direction OUTPUT))
|
||||
(port DO3
|
||||
(direction OUTPUT)))))
|
||||
(cell VHI
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell pmi_distributed_dpramXbnoner224pb08036b
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port (array (rename WrAddress "WrAddress(1:0)") 2)
|
||||
(direction INPUT))
|
||||
(port (array (rename Data "Data(1:0)") 2)
|
||||
(direction INPUT))
|
||||
(port WrClock
|
||||
(direction INPUT))
|
||||
(port WE
|
||||
(direction INPUT))
|
||||
(port WrClockEn
|
||||
(direction INPUT))
|
||||
(port (array (rename RdAddress "RdAddress(1:0)") 2)
|
||||
(direction INPUT))
|
||||
(port RdClock
|
||||
(direction INPUT))
|
||||
(port RdClockEn
|
||||
(direction INPUT))
|
||||
(port Reset
|
||||
(direction INPUT))
|
||||
(port (array (rename Q "Q(1:0)") 2)
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance LUT4_0
|
||||
(viewRef view1
|
||||
(cellRef ROM16X1A))
|
||||
(property initval
|
||||
(string "0x8000")))
|
||||
(instance FF_1
|
||||
(viewRef view1
|
||||
(cellRef FD1P3DX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance FF_0
|
||||
(viewRef view1
|
||||
(cellRef FD1P3DX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance scuba_vhi_inst
|
||||
(viewRef view1
|
||||
(cellRef VHI)))
|
||||
(instance mem_0_0
|
||||
(viewRef view1
|
||||
(cellRef DPR16X4C))
|
||||
(property MEM_INIT_FILE
|
||||
(string "(0-3)(0-1)"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "pmi_distributed_dpramXbnoner224pb08036b__PMI__4__2__2B"))
|
||||
(property COMP
|
||||
(string "mem_0_0"))
|
||||
(property initval
|
||||
(string "0x0000000000000000")))
|
||||
(net dataout1_ffin
|
||||
(joined
|
||||
(portRef DO1 (instanceRef mem_0_0))
|
||||
(portRef D (instanceRef FF_1))))
|
||||
(net dataout0_ffin
|
||||
(joined
|
||||
(portRef DO0 (instanceRef mem_0_0))
|
||||
(portRef D (instanceRef FF_0))))
|
||||
(net dec0_wre3
|
||||
(joined
|
||||
(portRef WRE (instanceRef mem_0_0))
|
||||
(portRef DO0 (instanceRef LUT4_0))))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))
|
||||
(portRef AD0 (instanceRef LUT4_0))
|
||||
(portRef AD1 (instanceRef LUT4_0))
|
||||
(portRef RAD3 (instanceRef mem_0_0))
|
||||
(portRef RAD2 (instanceRef mem_0_0))
|
||||
(portRef WAD3 (instanceRef mem_0_0))
|
||||
(portRef WAD2 (instanceRef mem_0_0))
|
||||
(portRef DI3 (instanceRef mem_0_0))
|
||||
(portRef DI2 (instanceRef mem_0_0))))
|
||||
(net dataout1
|
||||
(joined
|
||||
(portRef (member Q 0))
|
||||
(portRef Q (instanceRef FF_1))))
|
||||
(net dataout0
|
||||
(joined
|
||||
(portRef (member Q 1))
|
||||
(portRef Q (instanceRef FF_0))))
|
||||
(net reset
|
||||
(joined
|
||||
(portRef Reset)
|
||||
(portRef CD (instanceRef FF_1))
|
||||
(portRef CD (instanceRef FF_0))))
|
||||
(net rden
|
||||
(joined
|
||||
(portRef RdClockEn)
|
||||
(portRef SP (instanceRef FF_1))
|
||||
(portRef SP (instanceRef FF_0))))
|
||||
(net rdclk
|
||||
(joined
|
||||
(portRef RdClock)
|
||||
(portRef CK (instanceRef FF_1))
|
||||
(portRef CK (instanceRef FF_0))))
|
||||
(net raddr1
|
||||
(joined
|
||||
(portRef (member RdAddress 0))
|
||||
(portRef RAD1 (instanceRef mem_0_0))))
|
||||
(net raddr0
|
||||
(joined
|
||||
(portRef (member RdAddress 1))
|
||||
(portRef RAD0 (instanceRef mem_0_0))))
|
||||
(net cken
|
||||
(joined
|
||||
(portRef WrClockEn)
|
||||
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|
||||
(net wren
|
||||
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|
||||
(portRef WE)
|
||||
(portRef AD3 (instanceRef LUT4_0))))
|
||||
(net clk
|
||||
(joined
|
||||
(portRef WrClock)
|
||||
(portRef WCK (instanceRef mem_0_0))))
|
||||
(net datain1
|
||||
(joined
|
||||
(portRef (member Data 0))
|
||||
(portRef DI1 (instanceRef mem_0_0))))
|
||||
(net datain0
|
||||
(joined
|
||||
(portRef (member Data 1))
|
||||
(portRef DI0 (instanceRef mem_0_0))))
|
||||
(net waddr1
|
||||
(joined
|
||||
(portRef (member WrAddress 0))
|
||||
(portRef WAD1 (instanceRef mem_0_0))))
|
||||
(net waddr0
|
||||
(joined
|
||||
(portRef (member WrAddress 1))
|
||||
(portRef WAD0 (instanceRef mem_0_0))))))))
|
||||
(design pmi_distributed_dpramXbnoner224pb08036b
|
||||
(cellRef pmi_distributed_dpramXbnoner224pb08036b
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
@@ -0,0 +1,233 @@
|
||||
(edif pmi_distributed_dpramXbnoner224pb08036b_0
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2026 5 14 15 11 48)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
|
||||
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 4 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner224pb08036b_0 -pmi ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(view view1
|
||||
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|
||||
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|
||||
(port D
|
||||
(direction INPUT))
|
||||
(port SP
|
||||
(direction INPUT))
|
||||
(port CK
|
||||
(direction INPUT))
|
||||
(port CD
|
||||
(direction INPUT))
|
||||
(port Q
|
||||
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|
||||
(cell ROM16X1A
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
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|
||||
(port AD3
|
||||
(direction INPUT))
|
||||
(port AD2
|
||||
(direction INPUT))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(port DO0
|
||||
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|
||||
(cell DPR16X4C
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(direction INPUT))
|
||||
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|
||||
(direction INPUT))
|
||||
(port WCK
|
||||
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|
||||
(port WRE
|
||||
(direction INPUT))
|
||||
(port RAD0
|
||||
(direction INPUT))
|
||||
(port RAD1
|
||||
(direction INPUT))
|
||||
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|
||||
(direction INPUT))
|
||||
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|
||||
(direction INPUT))
|
||||
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|
||||
(direction INPUT))
|
||||
(port WAD1
|
||||
(direction INPUT))
|
||||
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|
||||
(direction INPUT))
|
||||
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|
||||
(direction INPUT))
|
||||
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|
||||
(direction OUTPUT))
|
||||
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|
||||
(direction OUTPUT))
|
||||
(port DO2
|
||||
(direction OUTPUT))
|
||||
(port DO3
|
||||
(direction OUTPUT)))))
|
||||
(cell VHI
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
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|
||||
(port Z
|
||||
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|
||||
(cell pmi_distributed_dpramXbnoner224pb08036b_0
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port (array (rename WrAddress "WrAddress(1:0)") 2)
|
||||
(direction INPUT))
|
||||
(port (array (rename Data "Data(1:0)") 2)
|
||||
(direction INPUT))
|
||||
(port WrClock
|
||||
(direction INPUT))
|
||||
(port WE
|
||||
(direction INPUT))
|
||||
(port WrClockEn
|
||||
(direction INPUT))
|
||||
(port (array (rename RdAddress "RdAddress(1:0)") 2)
|
||||
(direction INPUT))
|
||||
(port RdClock
|
||||
(direction INPUT))
|
||||
(port RdClockEn
|
||||
(direction INPUT))
|
||||
(port Reset
|
||||
(direction INPUT))
|
||||
(port (array (rename Q "Q(1:0)") 2)
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance LUT4_0
|
||||
(viewRef view1
|
||||
(cellRef ROM16X1A))
|
||||
(property initval
|
||||
(string "0x8000")))
|
||||
(instance FF_1
|
||||
(viewRef view1
|
||||
(cellRef FD1P3DX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance FF_0
|
||||
(viewRef view1
|
||||
(cellRef FD1P3DX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance scuba_vhi_inst
|
||||
(viewRef view1
|
||||
(cellRef VHI)))
|
||||
(instance mem_0_0
|
||||
(viewRef view1
|
||||
(cellRef DPR16X4C))
|
||||
(property MEM_INIT_FILE
|
||||
(string "(0-3)(0-1)"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "pmi_distributed_dpramXbnoner224pb08036b_0__PMI__4__2__2B"))
|
||||
(property COMP
|
||||
(string "mem_0_0"))
|
||||
(property initval
|
||||
(string "0x0000000000000000")))
|
||||
(net dataout1_ffin
|
||||
(joined
|
||||
(portRef DO1 (instanceRef mem_0_0))
|
||||
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|
||||
(net dataout0_ffin
|
||||
(joined
|
||||
(portRef DO0 (instanceRef mem_0_0))
|
||||
(portRef D (instanceRef FF_0))))
|
||||
(net dec0_wre3
|
||||
(joined
|
||||
(portRef WRE (instanceRef mem_0_0))
|
||||
(portRef DO0 (instanceRef LUT4_0))))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))
|
||||
(portRef AD0 (instanceRef LUT4_0))
|
||||
(portRef AD1 (instanceRef LUT4_0))
|
||||
(portRef RAD3 (instanceRef mem_0_0))
|
||||
(portRef RAD2 (instanceRef mem_0_0))
|
||||
(portRef WAD3 (instanceRef mem_0_0))
|
||||
(portRef WAD2 (instanceRef mem_0_0))
|
||||
(portRef DI3 (instanceRef mem_0_0))
|
||||
(portRef DI2 (instanceRef mem_0_0))))
|
||||
(net dataout1
|
||||
(joined
|
||||
(portRef (member Q 0))
|
||||
(portRef Q (instanceRef FF_1))))
|
||||
(net dataout0
|
||||
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|
||||
(portRef (member Q 1))
|
||||
(portRef Q (instanceRef FF_0))))
|
||||
(net reset
|
||||
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|
||||
(portRef Reset)
|
||||
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|
||||
(portRef CD (instanceRef FF_0))))
|
||||
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|
||||
(joined
|
||||
(portRef RdClockEn)
|
||||
(portRef SP (instanceRef FF_1))
|
||||
(portRef SP (instanceRef FF_0))))
|
||||
(net rdclk
|
||||
(joined
|
||||
(portRef RdClock)
|
||||
(portRef CK (instanceRef FF_1))
|
||||
(portRef CK (instanceRef FF_0))))
|
||||
(net raddr1
|
||||
(joined
|
||||
(portRef (member RdAddress 0))
|
||||
(portRef RAD1 (instanceRef mem_0_0))))
|
||||
(net raddr0
|
||||
(joined
|
||||
(portRef (member RdAddress 1))
|
||||
(portRef RAD0 (instanceRef mem_0_0))))
|
||||
(net cken
|
||||
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|
||||
(portRef WrClockEn)
|
||||
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|
||||
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|
||||
(joined
|
||||
(portRef WE)
|
||||
(portRef AD3 (instanceRef LUT4_0))))
|
||||
(net clk
|
||||
(joined
|
||||
(portRef WrClock)
|
||||
(portRef WCK (instanceRef mem_0_0))))
|
||||
(net datain1
|
||||
(joined
|
||||
(portRef (member Data 0))
|
||||
(portRef DI1 (instanceRef mem_0_0))))
|
||||
(net datain0
|
||||
(joined
|
||||
(portRef (member Data 1))
|
||||
(portRef DI0 (instanceRef mem_0_0))))
|
||||
(net waddr1
|
||||
(joined
|
||||
(portRef (member WrAddress 0))
|
||||
(portRef WAD1 (instanceRef mem_0_0))))
|
||||
(net waddr0
|
||||
(joined
|
||||
(portRef (member WrAddress 1))
|
||||
(portRef WAD0 (instanceRef mem_0_0))))))))
|
||||
(design pmi_distributed_dpramXbnoner224pb08036b_0
|
||||
(cellRef pmi_distributed_dpramXbnoner224pb08036b_0
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
@@ -0,0 +1,925 @@
|
||||
(edif pmi_ram_dpXbnonesadr3610102436101024p13959ecb
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2026 1 14 14 13 5)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2"))))
|
||||
(comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 36 -num_rows 1024 -rdata_width 36 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr3610102436101024p13959ecb -pmi ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
(numberDefinition))
|
||||
(cell VHI
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell VLO
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell DP8KC
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port DIA8
|
||||
(direction INPUT))
|
||||
(port DIA7
|
||||
(direction INPUT))
|
||||
(port DIA6
|
||||
(direction INPUT))
|
||||
(port DIA5
|
||||
(direction INPUT))
|
||||
(port DIA4
|
||||
(direction INPUT))
|
||||
(port DIA3
|
||||
(direction INPUT))
|
||||
(port DIA2
|
||||
(direction INPUT))
|
||||
(port DIA1
|
||||
(direction INPUT))
|
||||
(port DIA0
|
||||
(direction INPUT))
|
||||
(port ADA12
|
||||
(direction INPUT))
|
||||
(port ADA11
|
||||
(direction INPUT))
|
||||
(port ADA10
|
||||
(direction INPUT))
|
||||
(port ADA9
|
||||
(direction INPUT))
|
||||
(port ADA8
|
||||
(direction INPUT))
|
||||
(port ADA7
|
||||
(direction INPUT))
|
||||
(port ADA6
|
||||
(direction INPUT))
|
||||
(port ADA5
|
||||
(direction INPUT))
|
||||
(port ADA4
|
||||
(direction INPUT))
|
||||
(port ADA3
|
||||
(direction INPUT))
|
||||
(port ADA2
|
||||
(direction INPUT))
|
||||
(port ADA1
|
||||
(direction INPUT))
|
||||
(port ADA0
|
||||
(direction INPUT))
|
||||
(port CEA
|
||||
(direction INPUT))
|
||||
(port OCEA
|
||||
(direction INPUT))
|
||||
(port CLKA
|
||||
(direction INPUT))
|
||||
(port WEA
|
||||
(direction INPUT))
|
||||
(port CSA2
|
||||
(direction INPUT))
|
||||
(port CSA1
|
||||
(direction INPUT))
|
||||
(port CSA0
|
||||
(direction INPUT))
|
||||
(port RSTA
|
||||
(direction INPUT))
|
||||
(port DIB8
|
||||
(direction INPUT))
|
||||
(port DIB7
|
||||
(direction INPUT))
|
||||
(port DIB6
|
||||
(direction INPUT))
|
||||
(port DIB5
|
||||
(direction INPUT))
|
||||
(port DIB4
|
||||
(direction INPUT))
|
||||
(port DIB3
|
||||
(direction INPUT))
|
||||
(port DIB2
|
||||
(direction INPUT))
|
||||
(port DIB1
|
||||
(direction INPUT))
|
||||
(port DIB0
|
||||
(direction INPUT))
|
||||
(port ADB12
|
||||
(direction INPUT))
|
||||
(port ADB11
|
||||
(direction INPUT))
|
||||
(port ADB10
|
||||
(direction INPUT))
|
||||
(port ADB9
|
||||
(direction INPUT))
|
||||
(port ADB8
|
||||
(direction INPUT))
|
||||
(port ADB7
|
||||
(direction INPUT))
|
||||
(port ADB6
|
||||
(direction INPUT))
|
||||
(port ADB5
|
||||
(direction INPUT))
|
||||
(port ADB4
|
||||
(direction INPUT))
|
||||
(port ADB3
|
||||
(direction INPUT))
|
||||
(port ADB2
|
||||
(direction INPUT))
|
||||
(port ADB1
|
||||
(direction INPUT))
|
||||
(port ADB0
|
||||
(direction INPUT))
|
||||
(port CEB
|
||||
(direction INPUT))
|
||||
(port OCEB
|
||||
(direction INPUT))
|
||||
(port CLKB
|
||||
(direction INPUT))
|
||||
(port WEB
|
||||
(direction INPUT))
|
||||
(port CSB2
|
||||
(direction INPUT))
|
||||
(port CSB1
|
||||
(direction INPUT))
|
||||
(port CSB0
|
||||
(direction INPUT))
|
||||
(port RSTB
|
||||
(direction INPUT))
|
||||
(port DOA8
|
||||
(direction OUTPUT))
|
||||
(port DOA7
|
||||
(direction OUTPUT))
|
||||
(port DOA6
|
||||
(direction OUTPUT))
|
||||
(port DOA5
|
||||
(direction OUTPUT))
|
||||
(port DOA4
|
||||
(direction OUTPUT))
|
||||
(port DOA3
|
||||
(direction OUTPUT))
|
||||
(port DOA2
|
||||
(direction OUTPUT))
|
||||
(port DOA1
|
||||
(direction OUTPUT))
|
||||
(port DOA0
|
||||
(direction OUTPUT))
|
||||
(port DOB8
|
||||
(direction OUTPUT))
|
||||
(port DOB7
|
||||
(direction OUTPUT))
|
||||
(port DOB6
|
||||
(direction OUTPUT))
|
||||
(port DOB5
|
||||
(direction OUTPUT))
|
||||
(port DOB4
|
||||
(direction OUTPUT))
|
||||
(port DOB3
|
||||
(direction OUTPUT))
|
||||
(port DOB2
|
||||
(direction OUTPUT))
|
||||
(port DOB1
|
||||
(direction OUTPUT))
|
||||
(port DOB0
|
||||
(direction OUTPUT)))))
|
||||
(cell pmi_ram_dpXbnonesadr3610102436101024p13959ecb
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port (array (rename WrAddress "WrAddress(9:0)") 10)
|
||||
(direction INPUT))
|
||||
(port (array (rename RdAddress "RdAddress(9:0)") 10)
|
||||
(direction INPUT))
|
||||
(port (array (rename Data "Data(35:0)") 36)
|
||||
(direction INPUT))
|
||||
(port WE
|
||||
(direction INPUT))
|
||||
(port RdClock
|
||||
(direction INPUT))
|
||||
(port RdClockEn
|
||||
(direction INPUT))
|
||||
(port Reset
|
||||
(direction INPUT))
|
||||
(port WrClock
|
||||
(direction INPUT))
|
||||
(port WrClockEn
|
||||
(direction INPUT))
|
||||
(port (array (rename Q "Q(35:0)") 36)
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3
|
||||
(viewRef view1
|
||||
(cellRef DP8KC))
|
||||
(property INIT_DATA
|
||||
(string "STATIC"))
|
||||
(property ASYNC_RESET_RELEASE
|
||||
(string "ASYNC"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "pmi_ram_dpXbnonesadr3610102436101024p13959ecb__PMIP__1024__36__36__-1B"))
|
||||
(property MEM_INIT_FILE
|
||||
(string ""))
|
||||
(property CSDECODE_B
|
||||
(string "0b000"))
|
||||
(property CSDECODE_A
|
||||
(string "0b000"))
|
||||
(property WRITEMODE_B
|
||||
(string "NORMAL"))
|
||||
(property WRITEMODE_A
|
||||
(string "NORMAL"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property RESETMODE
|
||||
(string "ASYNC"))
|
||||
(property REGMODE_B
|
||||
(string "OUTREG"))
|
||||
(property REGMODE_A
|
||||
(string "OUTREG"))
|
||||
(property DATA_WIDTH_B
|
||||
(string "9"))
|
||||
(property DATA_WIDTH_A
|
||||
(string "9")))
|
||||
(instance pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2
|
||||
(viewRef view1
|
||||
(cellRef DP8KC))
|
||||
(property INIT_DATA
|
||||
(string "STATIC"))
|
||||
(property ASYNC_RESET_RELEASE
|
||||
(string "ASYNC"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "pmi_ram_dpXbnonesadr3610102436101024p13959ecb__PMIP__1024__36__36__-1B"))
|
||||
(property MEM_INIT_FILE
|
||||
(string ""))
|
||||
(property CSDECODE_B
|
||||
(string "0b000"))
|
||||
(property CSDECODE_A
|
||||
(string "0b000"))
|
||||
(property WRITEMODE_B
|
||||
(string "NORMAL"))
|
||||
(property WRITEMODE_A
|
||||
(string "NORMAL"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property RESETMODE
|
||||
(string "ASYNC"))
|
||||
(property REGMODE_B
|
||||
(string "OUTREG"))
|
||||
(property REGMODE_A
|
||||
(string "OUTREG"))
|
||||
(property DATA_WIDTH_B
|
||||
(string "9"))
|
||||
(property DATA_WIDTH_A
|
||||
(string "9")))
|
||||
(instance pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1
|
||||
(viewRef view1
|
||||
(cellRef DP8KC))
|
||||
(property INIT_DATA
|
||||
(string "STATIC"))
|
||||
(property ASYNC_RESET_RELEASE
|
||||
(string "ASYNC"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "pmi_ram_dpXbnonesadr3610102436101024p13959ecb__PMIP__1024__36__36__-1B"))
|
||||
(property MEM_INIT_FILE
|
||||
(string ""))
|
||||
(property CSDECODE_B
|
||||
(string "0b000"))
|
||||
(property CSDECODE_A
|
||||
(string "0b000"))
|
||||
(property WRITEMODE_B
|
||||
(string "NORMAL"))
|
||||
(property WRITEMODE_A
|
||||
(string "NORMAL"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property RESETMODE
|
||||
(string "ASYNC"))
|
||||
(property REGMODE_B
|
||||
(string "OUTREG"))
|
||||
(property REGMODE_A
|
||||
(string "OUTREG"))
|
||||
(property DATA_WIDTH_B
|
||||
(string "9"))
|
||||
(property DATA_WIDTH_A
|
||||
(string "9")))
|
||||
(instance scuba_vhi_inst
|
||||
(viewRef view1
|
||||
(cellRef VHI)))
|
||||
(instance scuba_vlo_inst
|
||||
(viewRef view1
|
||||
(cellRef VLO)))
|
||||
(instance pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0
|
||||
(viewRef view1
|
||||
(cellRef DP8KC))
|
||||
(property INIT_DATA
|
||||
(string "STATIC"))
|
||||
(property ASYNC_RESET_RELEASE
|
||||
(string "ASYNC"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "pmi_ram_dpXbnonesadr3610102436101024p13959ecb__PMIP__1024__36__36__-1B"))
|
||||
(property MEM_INIT_FILE
|
||||
(string ""))
|
||||
(property CSDECODE_B
|
||||
(string "0b000"))
|
||||
(property CSDECODE_A
|
||||
(string "0b000"))
|
||||
(property WRITEMODE_B
|
||||
(string "NORMAL"))
|
||||
(property WRITEMODE_A
|
||||
(string "NORMAL"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property RESETMODE
|
||||
(string "ASYNC"))
|
||||
(property REGMODE_B
|
||||
(string "OUTREG"))
|
||||
(property REGMODE_A
|
||||
(string "OUTREG"))
|
||||
(property DATA_WIDTH_B
|
||||
(string "9"))
|
||||
(property DATA_WIDTH_A
|
||||
(string "9")))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))
|
||||
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net scuba_vlo
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vlo_inst))
|
||||
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net dataout35
|
||||
(joined
|
||||
(portRef (member Q 0))
|
||||
(portRef DOB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net dataout34
|
||||
(joined
|
||||
(portRef (member Q 1))
|
||||
(portRef DOB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net dataout33
|
||||
(joined
|
||||
(portRef (member Q 2))
|
||||
(portRef DOB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net dataout32
|
||||
(joined
|
||||
(portRef (member Q 3))
|
||||
(portRef DOB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net dataout31
|
||||
(joined
|
||||
(portRef (member Q 4))
|
||||
(portRef DOB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net dataout30
|
||||
(joined
|
||||
(portRef (member Q 5))
|
||||
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net dataout29
|
||||
(joined
|
||||
(portRef (member Q 6))
|
||||
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net dataout28
|
||||
(joined
|
||||
(portRef (member Q 7))
|
||||
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net dataout27
|
||||
(joined
|
||||
(portRef (member Q 8))
|
||||
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net dataout26
|
||||
(joined
|
||||
(portRef (member Q 9))
|
||||
(portRef DOB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
|
||||
(net dataout25
|
||||
(joined
|
||||
(portRef (member Q 10))
|
||||
(portRef DOB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
|
||||
(net dataout24
|
||||
(joined
|
||||
(portRef (member Q 11))
|
||||
(portRef DOB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
|
||||
(net dataout23
|
||||
(joined
|
||||
(portRef (member Q 12))
|
||||
(portRef DOB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
|
||||
(net dataout22
|
||||
(joined
|
||||
(portRef (member Q 13))
|
||||
(portRef DOB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
|
||||
(net dataout21
|
||||
(joined
|
||||
(portRef (member Q 14))
|
||||
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
|
||||
(net dataout20
|
||||
(joined
|
||||
(portRef (member Q 15))
|
||||
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
|
||||
(net dataout19
|
||||
(joined
|
||||
(portRef (member Q 16))
|
||||
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
|
||||
(net dataout18
|
||||
(joined
|
||||
(portRef (member Q 17))
|
||||
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
|
||||
(net dataout17
|
||||
(joined
|
||||
(portRef (member Q 18))
|
||||
(portRef DOB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
|
||||
(net dataout16
|
||||
(joined
|
||||
(portRef (member Q 19))
|
||||
(portRef DOB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
|
||||
(net dataout15
|
||||
(joined
|
||||
(portRef (member Q 20))
|
||||
(portRef DOB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
|
||||
(net dataout14
|
||||
(joined
|
||||
(portRef (member Q 21))
|
||||
(portRef DOB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
|
||||
(net dataout13
|
||||
(joined
|
||||
(portRef (member Q 22))
|
||||
(portRef DOB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
|
||||
(net dataout12
|
||||
(joined
|
||||
(portRef (member Q 23))
|
||||
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
|
||||
(net dataout11
|
||||
(joined
|
||||
(portRef (member Q 24))
|
||||
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
|
||||
(net dataout10
|
||||
(joined
|
||||
(portRef (member Q 25))
|
||||
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
|
||||
(net dataout9
|
||||
(joined
|
||||
(portRef (member Q 26))
|
||||
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
|
||||
(net dataout8
|
||||
(joined
|
||||
(portRef (member Q 27))
|
||||
(portRef DOB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
|
||||
(net dataout7
|
||||
(joined
|
||||
(portRef (member Q 28))
|
||||
(portRef DOB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
|
||||
(net dataout6
|
||||
(joined
|
||||
(portRef (member Q 29))
|
||||
(portRef DOB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
|
||||
(net dataout5
|
||||
(joined
|
||||
(portRef (member Q 30))
|
||||
(portRef DOB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
|
||||
(net dataout4
|
||||
(joined
|
||||
(portRef (member Q 31))
|
||||
(portRef DOB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
|
||||
(net dataout3
|
||||
(joined
|
||||
(portRef (member Q 32))
|
||||
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
|
||||
(net dataout2
|
||||
(joined
|
||||
(portRef (member Q 33))
|
||||
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
|
||||
(net dataout1
|
||||
(joined
|
||||
(portRef (member Q 34))
|
||||
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
|
||||
(net dataout0
|
||||
(joined
|
||||
(portRef (member Q 35))
|
||||
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
|
||||
(net WrClockEn
|
||||
(joined
|
||||
(portRef WrClockEn)
|
||||
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net clk
|
||||
(joined
|
||||
(portRef WrClock)
|
||||
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net Reset
|
||||
(joined
|
||||
(portRef Reset)
|
||||
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net RdClockEn
|
||||
(joined
|
||||
(portRef RdClockEn)
|
||||
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))
|
||||
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net rdclk
|
||||
(joined
|
||||
(portRef RdClock)
|
||||
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net wren
|
||||
(joined
|
||||
(portRef WE)
|
||||
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net datain35
|
||||
(joined
|
||||
(portRef (member Data 0))
|
||||
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net datain34
|
||||
(joined
|
||||
(portRef (member Data 1))
|
||||
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net datain33
|
||||
(joined
|
||||
(portRef (member Data 2))
|
||||
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net datain32
|
||||
(joined
|
||||
(portRef (member Data 3))
|
||||
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net datain31
|
||||
(joined
|
||||
(portRef (member Data 4))
|
||||
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net datain30
|
||||
(joined
|
||||
(portRef (member Data 5))
|
||||
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net datain29
|
||||
(joined
|
||||
(portRef (member Data 6))
|
||||
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net datain28
|
||||
(joined
|
||||
(portRef (member Data 7))
|
||||
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net datain27
|
||||
(joined
|
||||
(portRef (member Data 8))
|
||||
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net datain26
|
||||
(joined
|
||||
(portRef (member Data 9))
|
||||
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
|
||||
(net datain25
|
||||
(joined
|
||||
(portRef (member Data 10))
|
||||
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
|
||||
(net datain24
|
||||
(joined
|
||||
(portRef (member Data 11))
|
||||
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
|
||||
(net datain23
|
||||
(joined
|
||||
(portRef (member Data 12))
|
||||
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
|
||||
(net datain22
|
||||
(joined
|
||||
(portRef (member Data 13))
|
||||
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
|
||||
(net datain21
|
||||
(joined
|
||||
(portRef (member Data 14))
|
||||
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
|
||||
(net datain20
|
||||
(joined
|
||||
(portRef (member Data 15))
|
||||
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
|
||||
(net datain19
|
||||
(joined
|
||||
(portRef (member Data 16))
|
||||
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
|
||||
(net datain18
|
||||
(joined
|
||||
(portRef (member Data 17))
|
||||
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))))
|
||||
(net datain17
|
||||
(joined
|
||||
(portRef (member Data 18))
|
||||
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
|
||||
(net datain16
|
||||
(joined
|
||||
(portRef (member Data 19))
|
||||
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
|
||||
(net datain15
|
||||
(joined
|
||||
(portRef (member Data 20))
|
||||
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
|
||||
(net datain14
|
||||
(joined
|
||||
(portRef (member Data 21))
|
||||
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
|
||||
(net datain13
|
||||
(joined
|
||||
(portRef (member Data 22))
|
||||
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
|
||||
(net datain12
|
||||
(joined
|
||||
(portRef (member Data 23))
|
||||
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
|
||||
(net datain11
|
||||
(joined
|
||||
(portRef (member Data 24))
|
||||
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
|
||||
(net datain10
|
||||
(joined
|
||||
(portRef (member Data 25))
|
||||
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
|
||||
(net datain9
|
||||
(joined
|
||||
(portRef (member Data 26))
|
||||
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))))
|
||||
(net datain8
|
||||
(joined
|
||||
(portRef (member Data 27))
|
||||
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
|
||||
(net datain7
|
||||
(joined
|
||||
(portRef (member Data 28))
|
||||
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
|
||||
(net datain6
|
||||
(joined
|
||||
(portRef (member Data 29))
|
||||
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
|
||||
(net datain5
|
||||
(joined
|
||||
(portRef (member Data 30))
|
||||
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
|
||||
(net datain4
|
||||
(joined
|
||||
(portRef (member Data 31))
|
||||
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
|
||||
(net datain3
|
||||
(joined
|
||||
(portRef (member Data 32))
|
||||
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
|
||||
(net datain2
|
||||
(joined
|
||||
(portRef (member Data 33))
|
||||
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
|
||||
(net datain1
|
||||
(joined
|
||||
(portRef (member Data 34))
|
||||
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
|
||||
(net datain0
|
||||
(joined
|
||||
(portRef (member Data 35))
|
||||
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))))
|
||||
(net raddr9
|
||||
(joined
|
||||
(portRef (member RdAddress 0))
|
||||
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net raddr8
|
||||
(joined
|
||||
(portRef (member RdAddress 1))
|
||||
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net raddr7
|
||||
(joined
|
||||
(portRef (member RdAddress 2))
|
||||
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net raddr6
|
||||
(joined
|
||||
(portRef (member RdAddress 3))
|
||||
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net raddr5
|
||||
(joined
|
||||
(portRef (member RdAddress 4))
|
||||
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net raddr4
|
||||
(joined
|
||||
(portRef (member RdAddress 5))
|
||||
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net raddr3
|
||||
(joined
|
||||
(portRef (member RdAddress 6))
|
||||
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net raddr2
|
||||
(joined
|
||||
(portRef (member RdAddress 7))
|
||||
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net raddr1
|
||||
(joined
|
||||
(portRef (member RdAddress 8))
|
||||
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net raddr0
|
||||
(joined
|
||||
(portRef (member RdAddress 9))
|
||||
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net waddr9
|
||||
(joined
|
||||
(portRef (member WrAddress 0))
|
||||
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net waddr8
|
||||
(joined
|
||||
(portRef (member WrAddress 1))
|
||||
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net waddr7
|
||||
(joined
|
||||
(portRef (member WrAddress 2))
|
||||
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net waddr6
|
||||
(joined
|
||||
(portRef (member WrAddress 3))
|
||||
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net waddr5
|
||||
(joined
|
||||
(portRef (member WrAddress 4))
|
||||
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net waddr4
|
||||
(joined
|
||||
(portRef (member WrAddress 5))
|
||||
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net waddr3
|
||||
(joined
|
||||
(portRef (member WrAddress 6))
|
||||
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net waddr2
|
||||
(joined
|
||||
(portRef (member WrAddress 7))
|
||||
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net waddr1
|
||||
(joined
|
||||
(portRef (member WrAddress 8))
|
||||
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))
|
||||
(net waddr0
|
||||
(joined
|
||||
(portRef (member WrAddress 9))
|
||||
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3))
|
||||
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2))
|
||||
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1))
|
||||
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0))))))))
|
||||
(design pmi_ram_dpXbnonesadr3610102436101024p13959ecb
|
||||
(cellRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,456 @@
|
||||
(edif pmi_ram_dpXbnonesadr81010248101024p1371af55
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2026 1 15 16 2 21)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2"))))
|
||||
(comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 8 -num_rows 1024 -rdata_width 8 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr81010248101024p1371af55 -pmi ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
(numberDefinition))
|
||||
(cell VHI
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell VLO
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell DP8KC
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port DIA8
|
||||
(direction INPUT))
|
||||
(port DIA7
|
||||
(direction INPUT))
|
||||
(port DIA6
|
||||
(direction INPUT))
|
||||
(port DIA5
|
||||
(direction INPUT))
|
||||
(port DIA4
|
||||
(direction INPUT))
|
||||
(port DIA3
|
||||
(direction INPUT))
|
||||
(port DIA2
|
||||
(direction INPUT))
|
||||
(port DIA1
|
||||
(direction INPUT))
|
||||
(port DIA0
|
||||
(direction INPUT))
|
||||
(port ADA12
|
||||
(direction INPUT))
|
||||
(port ADA11
|
||||
(direction INPUT))
|
||||
(port ADA10
|
||||
(direction INPUT))
|
||||
(port ADA9
|
||||
(direction INPUT))
|
||||
(port ADA8
|
||||
(direction INPUT))
|
||||
(port ADA7
|
||||
(direction INPUT))
|
||||
(port ADA6
|
||||
(direction INPUT))
|
||||
(port ADA5
|
||||
(direction INPUT))
|
||||
(port ADA4
|
||||
(direction INPUT))
|
||||
(port ADA3
|
||||
(direction INPUT))
|
||||
(port ADA2
|
||||
(direction INPUT))
|
||||
(port ADA1
|
||||
(direction INPUT))
|
||||
(port ADA0
|
||||
(direction INPUT))
|
||||
(port CEA
|
||||
(direction INPUT))
|
||||
(port OCEA
|
||||
(direction INPUT))
|
||||
(port CLKA
|
||||
(direction INPUT))
|
||||
(port WEA
|
||||
(direction INPUT))
|
||||
(port CSA2
|
||||
(direction INPUT))
|
||||
(port CSA1
|
||||
(direction INPUT))
|
||||
(port CSA0
|
||||
(direction INPUT))
|
||||
(port RSTA
|
||||
(direction INPUT))
|
||||
(port DIB8
|
||||
(direction INPUT))
|
||||
(port DIB7
|
||||
(direction INPUT))
|
||||
(port DIB6
|
||||
(direction INPUT))
|
||||
(port DIB5
|
||||
(direction INPUT))
|
||||
(port DIB4
|
||||
(direction INPUT))
|
||||
(port DIB3
|
||||
(direction INPUT))
|
||||
(port DIB2
|
||||
(direction INPUT))
|
||||
(port DIB1
|
||||
(direction INPUT))
|
||||
(port DIB0
|
||||
(direction INPUT))
|
||||
(port ADB12
|
||||
(direction INPUT))
|
||||
(port ADB11
|
||||
(direction INPUT))
|
||||
(port ADB10
|
||||
(direction INPUT))
|
||||
(port ADB9
|
||||
(direction INPUT))
|
||||
(port ADB8
|
||||
(direction INPUT))
|
||||
(port ADB7
|
||||
(direction INPUT))
|
||||
(port ADB6
|
||||
(direction INPUT))
|
||||
(port ADB5
|
||||
(direction INPUT))
|
||||
(port ADB4
|
||||
(direction INPUT))
|
||||
(port ADB3
|
||||
(direction INPUT))
|
||||
(port ADB2
|
||||
(direction INPUT))
|
||||
(port ADB1
|
||||
(direction INPUT))
|
||||
(port ADB0
|
||||
(direction INPUT))
|
||||
(port CEB
|
||||
(direction INPUT))
|
||||
(port OCEB
|
||||
(direction INPUT))
|
||||
(port CLKB
|
||||
(direction INPUT))
|
||||
(port WEB
|
||||
(direction INPUT))
|
||||
(port CSB2
|
||||
(direction INPUT))
|
||||
(port CSB1
|
||||
(direction INPUT))
|
||||
(port CSB0
|
||||
(direction INPUT))
|
||||
(port RSTB
|
||||
(direction INPUT))
|
||||
(port DOA8
|
||||
(direction OUTPUT))
|
||||
(port DOA7
|
||||
(direction OUTPUT))
|
||||
(port DOA6
|
||||
(direction OUTPUT))
|
||||
(port DOA5
|
||||
(direction OUTPUT))
|
||||
(port DOA4
|
||||
(direction OUTPUT))
|
||||
(port DOA3
|
||||
(direction OUTPUT))
|
||||
(port DOA2
|
||||
(direction OUTPUT))
|
||||
(port DOA1
|
||||
(direction OUTPUT))
|
||||
(port DOA0
|
||||
(direction OUTPUT))
|
||||
(port DOB8
|
||||
(direction OUTPUT))
|
||||
(port DOB7
|
||||
(direction OUTPUT))
|
||||
(port DOB6
|
||||
(direction OUTPUT))
|
||||
(port DOB5
|
||||
(direction OUTPUT))
|
||||
(port DOB4
|
||||
(direction OUTPUT))
|
||||
(port DOB3
|
||||
(direction OUTPUT))
|
||||
(port DOB2
|
||||
(direction OUTPUT))
|
||||
(port DOB1
|
||||
(direction OUTPUT))
|
||||
(port DOB0
|
||||
(direction OUTPUT)))))
|
||||
(cell pmi_ram_dpXbnonesadr81010248101024p1371af55
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port (array (rename WrAddress "WrAddress(9:0)") 10)
|
||||
(direction INPUT))
|
||||
(port (array (rename RdAddress "RdAddress(9:0)") 10)
|
||||
(direction INPUT))
|
||||
(port (array (rename Data "Data(7:0)") 8)
|
||||
(direction INPUT))
|
||||
(port WE
|
||||
(direction INPUT))
|
||||
(port RdClock
|
||||
(direction INPUT))
|
||||
(port RdClockEn
|
||||
(direction INPUT))
|
||||
(port Reset
|
||||
(direction INPUT))
|
||||
(port WrClock
|
||||
(direction INPUT))
|
||||
(port WrClockEn
|
||||
(direction INPUT))
|
||||
(port (array (rename Q "Q(7:0)") 8)
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance scuba_vhi_inst
|
||||
(viewRef view1
|
||||
(cellRef VHI)))
|
||||
(instance scuba_vlo_inst
|
||||
(viewRef view1
|
||||
(cellRef VLO)))
|
||||
(instance pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0
|
||||
(viewRef view1
|
||||
(cellRef DP8KC))
|
||||
(property INIT_DATA
|
||||
(string "STATIC"))
|
||||
(property ASYNC_RESET_RELEASE
|
||||
(string "ASYNC"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "pmi_ram_dpXbnonesadr81010248101024p1371af55__PMIP__1024__8__8__-1B"))
|
||||
(property MEM_INIT_FILE
|
||||
(string ""))
|
||||
(property CSDECODE_B
|
||||
(string "0b000"))
|
||||
(property CSDECODE_A
|
||||
(string "0b000"))
|
||||
(property WRITEMODE_B
|
||||
(string "NORMAL"))
|
||||
(property WRITEMODE_A
|
||||
(string "NORMAL"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property RESETMODE
|
||||
(string "ASYNC"))
|
||||
(property REGMODE_B
|
||||
(string "OUTREG"))
|
||||
(property REGMODE_A
|
||||
(string "OUTREG"))
|
||||
(property DATA_WIDTH_B
|
||||
(string "9"))
|
||||
(property DATA_WIDTH_A
|
||||
(string "9")))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))
|
||||
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net scuba_vlo
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vlo_inst))
|
||||
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net dataout7
|
||||
(joined
|
||||
(portRef (member Q 0))
|
||||
(portRef DOB7 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net dataout6
|
||||
(joined
|
||||
(portRef (member Q 1))
|
||||
(portRef DOB6 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net dataout5
|
||||
(joined
|
||||
(portRef (member Q 2))
|
||||
(portRef DOB5 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net dataout4
|
||||
(joined
|
||||
(portRef (member Q 3))
|
||||
(portRef DOB4 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net dataout3
|
||||
(joined
|
||||
(portRef (member Q 4))
|
||||
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net dataout2
|
||||
(joined
|
||||
(portRef (member Q 5))
|
||||
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net dataout1
|
||||
(joined
|
||||
(portRef (member Q 6))
|
||||
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net dataout0
|
||||
(joined
|
||||
(portRef (member Q 7))
|
||||
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net WrClockEn
|
||||
(joined
|
||||
(portRef WrClockEn)
|
||||
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net clk
|
||||
(joined
|
||||
(portRef WrClock)
|
||||
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net Reset
|
||||
(joined
|
||||
(portRef Reset)
|
||||
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net RdClockEn
|
||||
(joined
|
||||
(portRef RdClockEn)
|
||||
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))
|
||||
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net rdclk
|
||||
(joined
|
||||
(portRef RdClock)
|
||||
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net wren
|
||||
(joined
|
||||
(portRef WE)
|
||||
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net datain7
|
||||
(joined
|
||||
(portRef (member Data 0))
|
||||
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net datain6
|
||||
(joined
|
||||
(portRef (member Data 1))
|
||||
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net datain5
|
||||
(joined
|
||||
(portRef (member Data 2))
|
||||
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net datain4
|
||||
(joined
|
||||
(portRef (member Data 3))
|
||||
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net datain3
|
||||
(joined
|
||||
(portRef (member Data 4))
|
||||
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net datain2
|
||||
(joined
|
||||
(portRef (member Data 5))
|
||||
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net datain1
|
||||
(joined
|
||||
(portRef (member Data 6))
|
||||
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net datain0
|
||||
(joined
|
||||
(portRef (member Data 7))
|
||||
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net raddr9
|
||||
(joined
|
||||
(portRef (member RdAddress 0))
|
||||
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net raddr8
|
||||
(joined
|
||||
(portRef (member RdAddress 1))
|
||||
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net raddr7
|
||||
(joined
|
||||
(portRef (member RdAddress 2))
|
||||
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net raddr6
|
||||
(joined
|
||||
(portRef (member RdAddress 3))
|
||||
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net raddr5
|
||||
(joined
|
||||
(portRef (member RdAddress 4))
|
||||
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net raddr4
|
||||
(joined
|
||||
(portRef (member RdAddress 5))
|
||||
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net raddr3
|
||||
(joined
|
||||
(portRef (member RdAddress 6))
|
||||
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net raddr2
|
||||
(joined
|
||||
(portRef (member RdAddress 7))
|
||||
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net raddr1
|
||||
(joined
|
||||
(portRef (member RdAddress 8))
|
||||
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net raddr0
|
||||
(joined
|
||||
(portRef (member RdAddress 9))
|
||||
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net waddr9
|
||||
(joined
|
||||
(portRef (member WrAddress 0))
|
||||
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net waddr8
|
||||
(joined
|
||||
(portRef (member WrAddress 1))
|
||||
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net waddr7
|
||||
(joined
|
||||
(portRef (member WrAddress 2))
|
||||
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net waddr6
|
||||
(joined
|
||||
(portRef (member WrAddress 3))
|
||||
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net waddr5
|
||||
(joined
|
||||
(portRef (member WrAddress 4))
|
||||
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net waddr4
|
||||
(joined
|
||||
(portRef (member WrAddress 5))
|
||||
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net waddr3
|
||||
(joined
|
||||
(portRef (member WrAddress 6))
|
||||
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net waddr2
|
||||
(joined
|
||||
(portRef (member WrAddress 7))
|
||||
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net waddr1
|
||||
(joined
|
||||
(portRef (member WrAddress 8))
|
||||
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))
|
||||
(net waddr0
|
||||
(joined
|
||||
(portRef (member WrAddress 9))
|
||||
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0))))))))
|
||||
(design pmi_ram_dpXbnonesadr81010248101024p1371af55
|
||||
(cellRef pmi_ram_dpXbnonesadr81010248101024p1371af55
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
@@ -0,0 +1,162 @@
|
||||
----------------------------------------------------------------------
|
||||
Report for cell RelayConTop.verilog
|
||||
|
||||
Register bits: 1275 of 6864 (19%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 187
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
CCU2D 59 100.0
|
||||
FD1P3AX 427 100.0
|
||||
FD1P3AY 3 100.0
|
||||
FD1P3BX 33 100.0
|
||||
FD1P3DX 347 100.0
|
||||
FD1P3IX 175 100.0
|
||||
FD1P3JX 1 100.0
|
||||
FD1S3AX 20 100.0
|
||||
FD1S3AY 1 100.0
|
||||
FD1S3BX 4 100.0
|
||||
FD1S3DX 87 100.0
|
||||
FD1S3IX 33 100.0
|
||||
FD1S3JX 1 100.0
|
||||
GSR 1 100.0
|
||||
IB 5 100.0
|
||||
IFS1P3IX 2 100.0
|
||||
IFS1P3JX 1 100.0
|
||||
INV 18 100.0
|
||||
L6MUX21 74 100.0
|
||||
OB 181 100.0
|
||||
OBZ 1 100.0
|
||||
OFS1P3DX 4 100.0
|
||||
OFS1P3IX 136 100.0
|
||||
ORCALUT4 1290 100.0
|
||||
PFUMX 104 100.0
|
||||
PUR 1 100.0
|
||||
VHI 15 100.0
|
||||
VLO 15 100.0
|
||||
jtagconn16 1 100.0
|
||||
pmi_distributed_dpram_4s_2s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 2 100.0
|
||||
pmi_ram_dp_Z4 1 100.0
|
||||
SUB MODULES
|
||||
BUS_Con_uniq_1 1 100.0
|
||||
CPLD_Con_uniq_1 1 100.0
|
||||
Reg_file_uniq_1 1 100.0
|
||||
relaycontop_la0 1 100.0
|
||||
relaycontop_la0_trig 1 100.0
|
||||
reveal_coretop 1 100.0
|
||||
|
||||
TOTAL 3049
|
||||
----------------------------------------------------------------------
|
||||
Report for cell CPLD_Con_uniq_1.netlist
|
||||
Instance path: CPLD_Con_2
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
CCU2D 9 15.3
|
||||
FD1P3IX 44 25.1
|
||||
FD1P3JX 1 100.0
|
||||
FD1S3AX 14 70.0
|
||||
FD1S3IX 23 69.7
|
||||
INV 1 5.6
|
||||
ORCALUT4 339 26.3
|
||||
VHI 1 6.7
|
||||
VLO 1 6.7
|
||||
|
||||
TOTAL 433
|
||||
----------------------------------------------------------------------
|
||||
Report for cell Reg_file_uniq_1.netlist
|
||||
Instance path: CPLD_Reg_2
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
FD1P3AX 409 95.8
|
||||
FD1P3AY 3 100.0
|
||||
FD1S3AX 4 20.0
|
||||
FD1S3AY 1 100.0
|
||||
L6MUX21 72 97.3
|
||||
ORCALUT4 250 19.4
|
||||
PFUMX 97 93.3
|
||||
VHI 1 6.7
|
||||
VLO 1 6.7
|
||||
|
||||
TOTAL 838
|
||||
----------------------------------------------------------------------
|
||||
Report for cell BUS_Con_uniq_1.netlist
|
||||
Instance path: BUS_Con_2
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
FD1P3IX 131 74.9
|
||||
FD1S3AX 2 10.0
|
||||
FD1S3IX 10 30.3
|
||||
FD1S3JX 1 100.0
|
||||
ORCALUT4 96 7.4
|
||||
VHI 1 6.7
|
||||
VLO 1 6.7
|
||||
|
||||
TOTAL 242
|
||||
----------------------------------------------------------------------
|
||||
Report for cell reveal_coretop.verilog
|
||||
Instance path: RelayConTop_reveal_coretop_instance
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
CCU2D 50 84.7
|
||||
FD1P3AX 18 4.2
|
||||
FD1P3BX 33 100.0
|
||||
FD1P3DX 347 100.0
|
||||
FD1S3BX 4 100.0
|
||||
FD1S3DX 87 100.0
|
||||
INV 16 88.9
|
||||
L6MUX21 2 2.7
|
||||
ORCALUT4 605 46.9
|
||||
PFUMX 7 6.7
|
||||
VHI 11 73.3
|
||||
VLO 11 73.3
|
||||
jtagconn16 1 100.0
|
||||
pmi_distributed_dpram_4s_2s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 2 100.0
|
||||
pmi_ram_dp_Z4 1 100.0
|
||||
SUB MODULES
|
||||
relaycontop_la0 1 100.0
|
||||
relaycontop_la0_trig 1 100.0
|
||||
|
||||
TOTAL 1197
|
||||
----------------------------------------------------------------------
|
||||
Report for cell relaycontop_la0.netlist
|
||||
Instance path: RelayConTop_reveal_coretop_instance.relaycontop_la0_inst_0
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
CCU2D 50 84.7
|
||||
FD1P3AX 18 4.2
|
||||
FD1P3BX 33 100.0
|
||||
FD1P3DX 347 100.0
|
||||
FD1S3BX 4 100.0
|
||||
FD1S3DX 87 100.0
|
||||
INV 16 88.9
|
||||
L6MUX21 2 2.7
|
||||
ORCALUT4 605 46.9
|
||||
PFUMX 7 6.7
|
||||
VHI 10 66.7
|
||||
VLO 10 66.7
|
||||
pmi_distributed_dpram_4s_2s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 2 100.0
|
||||
pmi_ram_dp_Z4 1 100.0
|
||||
SUB MODULES
|
||||
relaycontop_la0_trig 1 100.0
|
||||
|
||||
TOTAL 1193
|
||||
----------------------------------------------------------------------
|
||||
Report for cell relaycontop_la0_trig.netlist
|
||||
Instance path: RelayConTop_reveal_coretop_instance.relaycontop_la0_inst_0.trig_u
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
CCU2D 18 30.5
|
||||
FD1P3AX 16 3.7
|
||||
FD1P3BX 1 3.0
|
||||
FD1P3DX 61 17.6
|
||||
FD1S3BX 4 100.0
|
||||
FD1S3DX 32 36.8
|
||||
INV 9 50.0
|
||||
L6MUX21 2 2.7
|
||||
ORCALUT4 193 15.0
|
||||
PFUMX 7 6.7
|
||||
VHI 7 46.7
|
||||
VLO 7 46.7
|
||||
pmi_distributed_dpram_4s_2s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 2 100.0
|
||||
|
||||
TOTAL 359
|
||||
Binary file not shown.
@@ -0,0 +1 @@
|
||||
HUBID_00 REVEAL_0
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,9 @@
|
||||
-w
|
||||
-l 5
|
||||
-i 6
|
||||
-n 1
|
||||
-t 1
|
||||
-s 1
|
||||
-c 0
|
||||
-e 0
|
||||
-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1
|
||||
@@ -0,0 +1,10 @@
|
||||
-v
|
||||
10
|
||||
|
||||
|
||||
|
||||
|
||||
-gt
|
||||
-sethld
|
||||
-sp 4
|
||||
-sphld m
|
||||
@@ -0,0 +1,258 @@
|
||||
[ START MERGED ]
|
||||
i_rst_n_c_i i_rst_n_c
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_1/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2.CN jtaghub16_jtck
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jrstn_i jtaghub16_jrstn
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/dec0_wre3 RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_en
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/genblk1.te_tt_dist_ram/dec0_wre3 RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/tt_wr_en
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/jshift_d2.CN jtaghub16_jtck
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/jrstn_i jtaghub16_jrstn
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w.CN jtaghub16_jtck
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jrstn_i jtaghub16_jrstn
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/jtck_i jtaghub16_jtck
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/jrstn_i jtaghub16_jrstn
|
||||
xo2chub/cdn.CN jtaghub16_jtck
|
||||
xo2chub/jrstn_i jtaghub16_jrstn
|
||||
[ END MERGED ]
|
||||
[ START CLIPPED ]
|
||||
xo2chub/GND
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/popfeedthru_unused
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/scuba_vlo
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/scuba_vhi
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren_jtck
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_te[2]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/VCC
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/VCC
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_te_0[2]
|
||||
CPLD_Con_2/GND
|
||||
xo2chub/VCC
|
||||
xo2chub/bit_count_cry_0_COUT[3]
|
||||
xo2chub/rom_rd_addr_cry_0_S0[0]
|
||||
xo2chub/N_2
|
||||
xo2chub/rom_rd_addr_s_0_S1[7]
|
||||
xo2chub/rom_rd_addr_s_0_COUT[7]
|
||||
xo2chub/jtdo2_int_prm_16_0_0_S1
|
||||
xo2chub/jtdo2_int_prm_16_0_0_S0
|
||||
xo2chub/N_3
|
||||
xo2chub/er2_tdo[14]
|
||||
xo2chub/er2_tdo[15]
|
||||
xo2chub/jtdo2_int_prm_15_0_0_S1
|
||||
xo2chub/jtdo2_int_prm_15_0_0_S0
|
||||
xo2chub/er2_tdo[12]
|
||||
xo2chub/er2_tdo[13]
|
||||
xo2chub/jtdo2_int_prm_13_0_0_S1
|
||||
xo2chub/jtdo2_int_prm_13_0_0_S0
|
||||
xo2chub/er2_tdo[10]
|
||||
xo2chub/er2_tdo[11]
|
||||
xo2chub/jtdo2_int_prm_11_0_0_S1
|
||||
xo2chub/jtdo2_int_prm_11_0_0_S0
|
||||
xo2chub/er2_tdo[8]
|
||||
xo2chub/er2_tdo[9]
|
||||
xo2chub/jtdo2_int_prm_9_0_0_S1
|
||||
xo2chub/jtdo2_int_prm_9_0_0_S0
|
||||
xo2chub/er2_tdo[6]
|
||||
xo2chub/er2_tdo[7]
|
||||
xo2chub/jtdo2_int_prm_7_0_0_S1
|
||||
xo2chub/jtdo2_int_prm_7_0_0_S0
|
||||
xo2chub/er2_tdo[4]
|
||||
xo2chub/er2_tdo[5]
|
||||
xo2chub/jtdo2_int_prm_5_0_0_S1
|
||||
xo2chub/jtdo2_int_prm_5_0_0_S0
|
||||
xo2chub/er2_tdo[2]
|
||||
xo2chub/er2_tdo[3]
|
||||
xo2chub/jtdo2_int_prm_3_0_0_S1
|
||||
xo2chub/jtdo2_int_prm_3_0_0_S0
|
||||
xo2chub/er2_tdo[1]
|
||||
xo2chub/jtdo2_int_prm_1_0_0_S0
|
||||
xo2chub/jtdo2_int_prm_1_0_0_COUT
|
||||
xo2chub/ip_enable[15]
|
||||
xo2chub/genblk7.un1_jtagf_u_1
|
||||
xo2chub/genblk7.un1_jtagf_u
|
||||
xo2chub/tdoa
|
||||
xo2chub/tdia
|
||||
xo2chub/tmsa
|
||||
xo2chub/tcka
|
||||
xo2chub/cdn
|
||||
xo2chub/bit_count_cry_0_S0[0]
|
||||
xo2chub/N_1
|
||||
GND
|
||||
VCC
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/VCC
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/GND
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0_S0[0]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_1
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0_COUT[9]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0_S0[0]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_2
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0_COUT[9]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0_S0[0]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_3
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0_COUT[9]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0_S0[0]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_4
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0_COUT[9]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0_S0[0]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s_0_S1[5]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s_0_COUT[5]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0_S0[0]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s_0_S1[5]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s_0_COUT[5]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/VCC
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/GND
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[4]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/te_precnt_cry_0_S0[0]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/N_1
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/te_precnt_s_0_S1[15]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/te_precnt_s_0_COUT[15]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/genblk1.te_tt_dist_ram/mem_0_0/DO2
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/genblk1.te_tt_dist_ram/mem_0_0/DO3
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/mem_0_0/DO2
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/mem_0_0/DO3
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0_S0[0]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_1
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s_0_S1[15]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s_0_COUT[15]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[3]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu_0[3]
|
||||
CPLD_Con_2/un1_delay_cnt_1_s_15_0_S1
|
||||
CPLD_Con_2/un1_delay_cnt_1_s_15_0_COUT
|
||||
CPLD_Con_2/un1_delay_cnt_1_cry_0_0_S1
|
||||
CPLD_Con_2/un1_delay_cnt_1_cry_0_0_S0
|
||||
CPLD_Con_2/N_10
|
||||
[ END CLIPPED ]
|
||||
[ START DESIGN PREFS ]
|
||||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.14.0.75.2 -- WARNING: Map write only section -- Tue May 26 15:49:45 2026
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "i_sys_clk" SITE "B9" ;
|
||||
LOCATE COMP "o_PMU_OC_4[31]" SITE "A3" ;
|
||||
LOCATE COMP "o_PMU_OC_4[30]" SITE "B3" ;
|
||||
LOCATE COMP "o_PMU_OC_4[29]" SITE "A2" ;
|
||||
LOCATE COMP "o_PMU_OC_4[28]" SITE "C11" ;
|
||||
LOCATE COMP "o_PMU_OC_4[27]" SITE "D3" ;
|
||||
LOCATE COMP "o_PMU_OC_4[26]" SITE "E2" ;
|
||||
LOCATE COMP "o_PMU_OC_4[25]" SITE "D1" ;
|
||||
LOCATE COMP "o_PMU_OC_4[24]" SITE "E1" ;
|
||||
LOCATE COMP "o_PMU_OC_4[15]" SITE "E11" ;
|
||||
LOCATE COMP "o_PMU_OC_4[14]" SITE "G11" ;
|
||||
LOCATE COMP "o_PMU_OC_4[13]" SITE "C5" ;
|
||||
LOCATE COMP "o_PMU_OC_4[12]" SITE "C4" ;
|
||||
LOCATE COMP "o_PMU_OC_4[11]" SITE "F1" ;
|
||||
LOCATE COMP "o_PMU_OC_4[10]" SITE "G3" ;
|
||||
LOCATE COMP "o_PMU_OC_4[9]" SITE "G2" ;
|
||||
LOCATE COMP "o_PMU_OC_4[8]" SITE "G1" ;
|
||||
LOCATE COMP "o_PMU_OC_3[31]" SITE "D21" ;
|
||||
LOCATE COMP "o_PMU_OC_3[30]" SITE "E20" ;
|
||||
LOCATE COMP "o_PMU_OC_3[29]" SITE "E22" ;
|
||||
LOCATE COMP "o_PMU_OC_3[28]" SITE "G21" ;
|
||||
LOCATE COMP "o_PMU_OC_3[27]" SITE "C15" ;
|
||||
LOCATE COMP "o_PMU_OC_3[26]" SITE "B15" ;
|
||||
LOCATE COMP "o_PMU_OC_3[25]" SITE "B14" ;
|
||||
LOCATE COMP "o_PMU_OC_3[24]" SITE "B13" ;
|
||||
LOCATE COMP "o_PMU_OC_3[15]" SITE "B16" ;
|
||||
LOCATE COMP "o_PMU_OC_3[14]" SITE "A17" ;
|
||||
LOCATE COMP "o_PMU_OC_3[13]" SITE "C18" ;
|
||||
LOCATE COMP "o_PMU_OC_3[12]" SITE "B19" ;
|
||||
LOCATE COMP "o_PMU_OC_3[11]" SITE "A13" ;
|
||||
LOCATE COMP "o_PMU_OC_3[10]" SITE "B12" ;
|
||||
LOCATE COMP "o_PMU_OC_3[9]" SITE "A12" ;
|
||||
LOCATE COMP "o_PMU_OC_3[8]" SITE "A11" ;
|
||||
LOCATE COMP "o_PMU_OC_2[31]" SITE "D11" ;
|
||||
LOCATE COMP "o_PMU_OC_2[30]" SITE "E10" ;
|
||||
LOCATE COMP "o_PMU_OC_2[29]" SITE "E9" ;
|
||||
LOCATE COMP "o_PMU_OC_2[28]" SITE "E8" ;
|
||||
LOCATE COMP "o_PMU_OC_2[27]" SITE "T6" ;
|
||||
LOCATE COMP "o_PMU_OC_2[26]" SITE "W5" ;
|
||||
LOCATE COMP "o_PMU_OC_2[25]" SITE "U5" ;
|
||||
LOCATE COMP "o_PMU_OC_2[24]" SITE "T7" ;
|
||||
LOCATE COMP "o_PMU_OC_2[15]" SITE "H3" ;
|
||||
LOCATE COMP "o_PMU_OC_2[14]" SITE "H2" ;
|
||||
LOCATE COMP "o_PMU_OC_2[13]" SITE "H6" ;
|
||||
LOCATE COMP "o_PMU_OC_2[12]" SITE "H5" ;
|
||||
LOCATE COMP "o_PMU_OC_2[11]" SITE "B1" ;
|
||||
LOCATE COMP "o_PMU_OC_2[10]" SITE "C3" ;
|
||||
LOCATE COMP "o_PMU_OC_2[9]" SITE "C2" ;
|
||||
LOCATE COMP "o_PMU_OC_2[8]" SITE "C1" ;
|
||||
LOCATE COMP "o_PMU_OC_1[31]" SITE "U4" ;
|
||||
LOCATE COMP "o_PMU_OC_1[30]" SITE "P6" ;
|
||||
LOCATE COMP "o_PMU_OC_1[29]" SITE "T5" ;
|
||||
LOCATE COMP "o_PMU_OC_1[28]" SITE "R6" ;
|
||||
LOCATE COMP "o_PMU_OC_1[27]" SITE "M4" ;
|
||||
LOCATE COMP "o_PMU_OC_1[26]" SITE "P3" ;
|
||||
LOCATE COMP "o_PMU_OC_1[25]" SITE "D15" ;
|
||||
LOCATE COMP "o_PMU_OC_1[24]" SITE "N5" ;
|
||||
LOCATE COMP "o_PMU_OC_1[15]" SITE "E17" ;
|
||||
LOCATE COMP "o_PMU_OC_1[14]" SITE "D17" ;
|
||||
LOCATE COMP "o_PMU_OC_1[13]" SITE "F17" ;
|
||||
LOCATE COMP "o_PMU_OC_1[12]" SITE "C17" ;
|
||||
LOCATE COMP "o_PMU_OC_1[11]" SITE "F13" ;
|
||||
LOCATE COMP "o_PMU_OC_1[10]" SITE "C13" ;
|
||||
LOCATE COMP "o_PMU_OC_1[9]" SITE "G13" ;
|
||||
LOCATE COMP "o_PMU_OC_1[8]" SITE "D14" ;
|
||||
LOCATE COMP "o_RC_T[25]" SITE "AA13" ;
|
||||
LOCATE COMP "o_RC_T[24]" SITE "T13" ;
|
||||
LOCATE COMP "o_RC_T[23]" SITE "U15" ;
|
||||
LOCATE COMP "o_RC_T[22]" SITE "T15" ;
|
||||
LOCATE COMP "o_RC_T[21]" SITE "Y17" ;
|
||||
LOCATE COMP "o_RC_T[20]" SITE "W17" ;
|
||||
LOCATE COMP "o_RC_T[19]" SITE "W19" ;
|
||||
LOCATE COMP "o_RC_T[18]" SITE "AB20" ;
|
||||
LOCATE COMP "o_RC_T[17]" SITE "AA19" ;
|
||||
LOCATE COMP "o_RC_T[16]" SITE "Y18" ;
|
||||
LOCATE COMP "o_RC_T[15]" SITE "AB17" ;
|
||||
LOCATE COMP "o_RC_T[14]" SITE "V16" ;
|
||||
LOCATE COMP "o_RC_T[13]" SITE "V14" ;
|
||||
LOCATE COMP "o_RC_T[12]" SITE "V13" ;
|
||||
LOCATE COMP "o_RC_T[11]" SITE "Y12" ;
|
||||
LOCATE COMP "o_RC_T[10]" SITE "W12" ;
|
||||
LOCATE COMP "o_RC_T[9]" SITE "V12" ;
|
||||
LOCATE COMP "o_RC_T[8]" SITE "V8" ;
|
||||
LOCATE COMP "o_RC_T[7]" SITE "AB13" ;
|
||||
LOCATE COMP "o_RC_T[6]" SITE "AA12" ;
|
||||
LOCATE COMP "o_RC_T[5]" SITE "AB11" ;
|
||||
LOCATE COMP "o_RC_T[4]" SITE "AA11" ;
|
||||
LOCATE COMP "o_RC_T[3]" SITE "AA10" ;
|
||||
LOCATE COMP "o_RC_T[2]" SITE "AB10" ;
|
||||
LOCATE COMP "o_RC_T[1]" SITE "Y10" ;
|
||||
LOCATE COMP "o_RC_T[0]" SITE "AA8" ;
|
||||
LOCATE COMP "o_RC_S[15]" SITE "AA7" ;
|
||||
LOCATE COMP "o_RC_S[14]" SITE "AB7" ;
|
||||
LOCATE COMP "o_RC_S[13]" SITE "Y7" ;
|
||||
LOCATE COMP "o_RC_S[12]" SITE "Y6" ;
|
||||
LOCATE COMP "o_RC_S[11]" SITE "AB6" ;
|
||||
LOCATE COMP "o_RC_S[10]" SITE "AB5" ;
|
||||
LOCATE COMP "o_RC_S[9]" SITE "W6" ;
|
||||
LOCATE COMP "o_RC_S[8]" SITE "Y5" ;
|
||||
LOCATE COMP "o_RC_S[7]" SITE "AA4" ;
|
||||
LOCATE COMP "o_RC_S[6]" SITE "Y4" ;
|
||||
LOCATE COMP "o_RC_S[5]" SITE "AB3" ;
|
||||
LOCATE COMP "o_RC_S[4]" SITE "AA3" ;
|
||||
LOCATE COMP "o_RC_S[3]" SITE "Y3" ;
|
||||
LOCATE COMP "o_RC_S[2]" SITE "AB2" ;
|
||||
LOCATE COMP "o_RC_S[1]" SITE "W9" ;
|
||||
LOCATE COMP "o_RC_S[0]" SITE "T10" ;
|
||||
LOCATE COMP "o_RC_F[7]" SITE "U10" ;
|
||||
LOCATE COMP "o_RC_F[6]" SITE "W11" ;
|
||||
LOCATE COMP "o_RC_F[5]" SITE "V11" ;
|
||||
LOCATE COMP "o_RC_F[4]" SITE "U11" ;
|
||||
LOCATE COMP "o_RC_F[3]" SITE "T11" ;
|
||||
LOCATE COMP "o_RC_F[2]" SITE "T12" ;
|
||||
LOCATE COMP "o_RC_F[1]" SITE "U12" ;
|
||||
LOCATE COMP "o_RC_F[0]" SITE "U13" ;
|
||||
LOCATE COMP "o_err" SITE "AB16" ;
|
||||
LOCATE COMP "i_cs" SITE "Y15" ;
|
||||
LOCATE COMP "i_mosi" SITE "AB12" ;
|
||||
LOCATE COMP "i_sclk" SITE "AA16" ;
|
||||
LOCATE COMP "i_rst_n" SITE "Y14" ;
|
||||
USE PRIMARY NET "i_sys_clk_c" ;
|
||||
SCHEMATIC END ;
|
||||
[ END DESIGN PREFS ]
|
||||
@@ -0,0 +1,209 @@
|
||||
---------------------------------------------------
|
||||
Report for cell RelayConTop
|
||||
Instance path: RelayConTop
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 760.00 100.0
|
||||
IOLGC 142.00 100.0
|
||||
LUT4 1344.00 100.0
|
||||
DISTRAM 6.00 100.0
|
||||
IOREG 142 100.0
|
||||
IOBUF 187 100.0
|
||||
PFUREG 1190 100.0
|
||||
RIPPLE 76 100.0
|
||||
EBR 10 100.0
|
||||
SUB MODULES
|
||||
cell count SLC Usage(%)
|
||||
xo2chub 1 3.2
|
||||
reveal_coretop 1 42.6
|
||||
Reg_file_uniq_1 1 28.8
|
||||
CPLD_Con_uniq_1 1 17.3
|
||||
BUS_Con_uniq_1 1 8.1
|
||||
---------------------------------------------------
|
||||
Report for cell CPLD_Con_uniq_1
|
||||
Instance path: RelayConTop/CPLD_Con_2
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 131.50 17.3
|
||||
LUT4 340.00 25.3
|
||||
PFUREG 82 6.9
|
||||
RIPPLE 9 11.8
|
||||
---------------------------------------------------
|
||||
Report for cell Reg_file_uniq_1
|
||||
Instance path: RelayConTop/CPLD_Reg_2
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 218.58 28.8
|
||||
LUT4 250.00 18.6
|
||||
PFUREG 417 35.0
|
||||
---------------------------------------------------
|
||||
Report for cell BUS_Con_uniq_1
|
||||
Instance path: RelayConTop/BUS_Con_2
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 61.75 8.1
|
||||
LUT4 96.00 7.1
|
||||
PFUREG 144 12.1
|
||||
---------------------------------------------------
|
||||
Report for cell reveal_coretop
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 323.42 42.6
|
||||
LUT4 645.00 48.0
|
||||
DISTRAM 4.00 66.7
|
||||
PFUREG 495 41.6
|
||||
RIPPLE 50 65.8
|
||||
EBR 10 100.0
|
||||
SUB MODULES
|
||||
cell count SLC Usage(%)
|
||||
relaycontop_la0 1 42.6
|
||||
---------------------------------------------------
|
||||
Report for cell relaycontop_la0
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 323.42 42.6
|
||||
LUT4 645.00 48.0
|
||||
DISTRAM 4.00 66.7
|
||||
PFUREG 495 41.6
|
||||
RIPPLE 50 65.8
|
||||
EBR 10 100.0
|
||||
SUB MODULES
|
||||
cell count SLC Usage(%)
|
||||
rvl_tm_Z3 1 15.6
|
||||
rvl_jtag_int_42s_2s_0s_0s_6s_42s_42s 1 14.4
|
||||
relaycontop_la0_trig 1 12.5
|
||||
---------------------------------------------------
|
||||
Report for cell relaycontop_la0_trig
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 95.13 12.5
|
||||
LUT4 189.00 14.1
|
||||
DISTRAM 4.00 66.7
|
||||
PFUREG 118 9.9
|
||||
RIPPLE 18 23.7
|
||||
SUB MODULES
|
||||
cell count SLC Usage(%)
|
||||
rvl_tu_1s_0s_0s_0s_1s_2 1 0.8
|
||||
rvl_tu_1s_0s_0s_0s_1s_1 1 0.8
|
||||
rvl_tcnt_2s_3s_1_0s 1 1.3
|
||||
rvl_te_Z1_0 1 4.0
|
||||
rvl_te_Z1_1 1 4.8
|
||||
rvl_decode_2s_2s 1 0.4
|
||||
---------------------------------------------------
|
||||
Report for cell rvl_decode_2s_2s
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 3.10 0.4
|
||||
LUT4 12.50 0.9
|
||||
---------------------------------------------------
|
||||
Report for cell rvl_tu_1s_0s_0s_0s_1s_2
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 6.08 0.8
|
||||
LUT4 11.00 0.8
|
||||
PFUREG 8 0.7
|
||||
---------------------------------------------------
|
||||
Report for cell rvl_tu_1s_0s_0s_0s_1s_1
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_1
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 6.18 0.8
|
||||
LUT4 12.00 0.9
|
||||
PFUREG 8 0.7
|
||||
---------------------------------------------------
|
||||
Report for cell rvl_te_Z1_1
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 36.20 4.8
|
||||
LUT4 69.50 5.2
|
||||
DISTRAM 2.00 33.3
|
||||
PFUREG 53 4.5
|
||||
RIPPLE 9 11.8
|
||||
SUB MODULES
|
||||
cell count SLC Usage(%)
|
||||
pmi_distributed_dpramXbnoner224pb08036b 1 0.3
|
||||
---------------------------------------------------
|
||||
Report for cell pmi_distributed_dpramXbnoner224pb08036b
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 2.25 0.3
|
||||
LUT4 1.00 0.1
|
||||
DISTRAM 2.00 33.3
|
||||
PFUREG 2 0.2
|
||||
---------------------------------------------------
|
||||
Report for cell rvl_te_Z1_0
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 30.33 4.0
|
||||
LUT4 53.00 3.9
|
||||
DISTRAM 2.00 33.3
|
||||
PFUREG 36 3.0
|
||||
RIPPLE 9 11.8
|
||||
SUB MODULES
|
||||
cell count SLC Usage(%)
|
||||
pmi_distributed_dpramXbnoner224pb08036b_0 1 0.3
|
||||
---------------------------------------------------
|
||||
Report for cell pmi_distributed_dpramXbnoner224pb08036b_0
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/genblk1.te_tt_dist_ram
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 2.25 0.3
|
||||
LUT4 1.00 0.1
|
||||
DISTRAM 2.00 33.3
|
||||
PFUREG 2 0.2
|
||||
---------------------------------------------------
|
||||
Report for cell rvl_tcnt_2s_3s_1_0s
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 9.73 1.3
|
||||
LUT4 22.00 1.6
|
||||
PFUREG 13 1.1
|
||||
---------------------------------------------------
|
||||
Report for cell rvl_jtag_int_42s_2s_0s_0s_6s_42s_42s
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 109.27 14.4
|
||||
LUT4 249.50 18.6
|
||||
PFUREG 168 14.1
|
||||
RIPPLE 8 10.5
|
||||
---------------------------------------------------
|
||||
Report for cell rvl_tm_Z3
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 118.57 15.6
|
||||
LUT4 205.00 15.3
|
||||
PFUREG 209 17.6
|
||||
RIPPLE 24 31.6
|
||||
EBR 10 100.0
|
||||
SUB MODULES
|
||||
cell count SLC Usage(%)
|
||||
pmi_ram_dpXbnonesadr4211204842112048p1395c895 1 1.4
|
||||
---------------------------------------------------
|
||||
Report for cell pmi_ram_dpXbnonesadr4211204842112048p1395c895
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 11.00 1.4
|
||||
LUT4 42.00 3.1
|
||||
PFUREG 2 0.2
|
||||
EBR 10 100.0
|
||||
---------------------------------------------------
|
||||
Report for cell xo2chub
|
||||
Instance path: RelayConTop/xo2chub
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 24.25 3.2
|
||||
LUT4 12.00 0.9
|
||||
PFUREG 51 4.3
|
||||
RIPPLE 17 22.4
|
||||
@@ -0,0 +1,26 @@
|
||||
#
|
||||
# Logical Preferences generated for Lattice by Synplify map202309lat, Build 191R.
|
||||
#
|
||||
|
||||
# Period Constraints
|
||||
#FREQUENCY NET "RelayConTop_reveal_coretop_instance/jtck[0]" 200.0 MHz;
|
||||
#FREQUENCY PORT "i_sys_clk" 200.0 MHz;
|
||||
|
||||
|
||||
# Output Constraints
|
||||
|
||||
# Input Constraints
|
||||
|
||||
# Point-to-point Delay Constraints
|
||||
|
||||
|
||||
|
||||
# Block Path Constraints
|
||||
#BLOCK PATH FROM CLKNET "i_sys_clk_c" TO CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]";
|
||||
#BLOCK PATH FROM CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]" TO CLKNET "i_sys_clk_c";
|
||||
#BLOCK PATH FROM CLKNET "i_sys_clk_c" TO CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]";
|
||||
#BLOCK PATH FROM CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]" TO CLKNET "i_sys_clk_c";
|
||||
|
||||
BLOCK ASYNCPATHS;
|
||||
|
||||
# End of generated Logical Preferences.
|
||||
@@ -0,0 +1 @@
|
||||
-link -encrypt -top RelayConTop -osyn /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD2/impl1/synwork/NewExtIns_CPLD2_impl1_comp.srs /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD2/impl1/synwork/layer0.srs -jobname linker
|
||||
@@ -0,0 +1,52 @@
|
||||
<?xml version='1.0' encoding='utf-8' ?>
|
||||
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
|
||||
<ispXCF version="3.12">
|
||||
<Comment></Comment>
|
||||
<Chain>
|
||||
<Comm>JTAG</Comm>
|
||||
<Device>
|
||||
<SelectedProg value="TRUE"/>
|
||||
<Pos>1</Pos>
|
||||
<Vendor>Lattice</Vendor>
|
||||
<Family>MachXO2</Family>
|
||||
<Name>LCMXO2-7000HC</Name>
|
||||
<IDCode>0x012bd043</IDCode>
|
||||
<Package>All</Package>
|
||||
<PON>LCMXO2-7000HC</PON>
|
||||
<Bypass>
|
||||
<InstrLen>8</InstrLen>
|
||||
<InstrVal>11111111</InstrVal>
|
||||
<BScanLen>1</BScanLen>
|
||||
<BScanVal>0</BScanVal>
|
||||
</Bypass>
|
||||
<File>D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD2/impl1/NewExtIns_CPLD2_impl1.jed</File>
|
||||
<FileTime>01/20/26 16:01:30</FileTime>
|
||||
<JedecChecksum>0x566E</JedecChecksum>
|
||||
<Operation>FLASH Erase,Program,Verify</Operation>
|
||||
<Option>
|
||||
<SVFVendor>JTAG STANDARD</SVFVendor>
|
||||
<IOState>HighZ</IOState>
|
||||
<PreloadLength>664</PreloadLength>
|
||||
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
|
||||
<TCKFrequency>1.000000 MHz</TCKFrequency>
|
||||
<SVFProcessor>SVF Processor</SVFProcessor>
|
||||
<Usercode>0x00000000</Usercode>
|
||||
<AccessMode>FLASH</AccessMode>
|
||||
</Option>
|
||||
</Device>
|
||||
</Chain>
|
||||
<ProjectOptions>
|
||||
<Program>SEQUENTIAL</Program>
|
||||
<Process>ENTIRED CHAIN</Process>
|
||||
<OperationOverride>No Override</OperationOverride>
|
||||
<StartTAP>TLR</StartTAP>
|
||||
<EndTAP>TLR</EndTAP>
|
||||
<VerifyUsercode value="FALSE"/>
|
||||
<TCKDelay>1</TCKDelay>
|
||||
</ProjectOptions>
|
||||
<CableOptions>
|
||||
<CableName>USB</CableName>
|
||||
<PortAdd>EzUSB-0</PortAdd>
|
||||
<USBID>\\?\usb#vid_1134&amp;pid_8001#9&amp;2fe42d87&amp;0&amp;2#</USBID>
|
||||
</CableOptions>
|
||||
</ispXCF>
|
||||
@@ -0,0 +1,233 @@
|
||||
(edif pmi_distributed_dpramXbnoner224pb08036b
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2026 5 26 15 49 44)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
|
||||
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 4 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner224pb08036b -pmi ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
(numberDefinition))
|
||||
(cell FD1P3DX
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port D
|
||||
(direction INPUT))
|
||||
(port SP
|
||||
(direction INPUT))
|
||||
(port CK
|
||||
(direction INPUT))
|
||||
(port CD
|
||||
(direction INPUT))
|
||||
(port Q
|
||||
(direction OUTPUT)))))
|
||||
(cell ROM16X1A
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port AD3
|
||||
(direction INPUT))
|
||||
(port AD2
|
||||
(direction INPUT))
|
||||
(port AD1
|
||||
(direction INPUT))
|
||||
(port AD0
|
||||
(direction INPUT))
|
||||
(port DO0
|
||||
(direction OUTPUT)))))
|
||||
(cell DPR16X4C
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port DI0
|
||||
(direction INPUT))
|
||||
(port DI1
|
||||
(direction INPUT))
|
||||
(port DI2
|
||||
(direction INPUT))
|
||||
(port DI3
|
||||
(direction INPUT))
|
||||
(port WCK
|
||||
(direction INPUT))
|
||||
(port WRE
|
||||
(direction INPUT))
|
||||
(port RAD0
|
||||
(direction INPUT))
|
||||
(port RAD1
|
||||
(direction INPUT))
|
||||
(port RAD2
|
||||
(direction INPUT))
|
||||
(port RAD3
|
||||
(direction INPUT))
|
||||
(port WAD0
|
||||
(direction INPUT))
|
||||
(port WAD1
|
||||
(direction INPUT))
|
||||
(port WAD2
|
||||
(direction INPUT))
|
||||
(port WAD3
|
||||
(direction INPUT))
|
||||
(port DO0
|
||||
(direction OUTPUT))
|
||||
(port DO1
|
||||
(direction OUTPUT))
|
||||
(port DO2
|
||||
(direction OUTPUT))
|
||||
(port DO3
|
||||
(direction OUTPUT)))))
|
||||
(cell VHI
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell pmi_distributed_dpramXbnoner224pb08036b
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port (array (rename WrAddress "WrAddress(1:0)") 2)
|
||||
(direction INPUT))
|
||||
(port (array (rename Data "Data(1:0)") 2)
|
||||
(direction INPUT))
|
||||
(port WrClock
|
||||
(direction INPUT))
|
||||
(port WE
|
||||
(direction INPUT))
|
||||
(port WrClockEn
|
||||
(direction INPUT))
|
||||
(port (array (rename RdAddress "RdAddress(1:0)") 2)
|
||||
(direction INPUT))
|
||||
(port RdClock
|
||||
(direction INPUT))
|
||||
(port RdClockEn
|
||||
(direction INPUT))
|
||||
(port Reset
|
||||
(direction INPUT))
|
||||
(port (array (rename Q "Q(1:0)") 2)
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance LUT4_0
|
||||
(viewRef view1
|
||||
(cellRef ROM16X1A))
|
||||
(property initval
|
||||
(string "0x8000")))
|
||||
(instance FF_1
|
||||
(viewRef view1
|
||||
(cellRef FD1P3DX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance FF_0
|
||||
(viewRef view1
|
||||
(cellRef FD1P3DX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance scuba_vhi_inst
|
||||
(viewRef view1
|
||||
(cellRef VHI)))
|
||||
(instance mem_0_0
|
||||
(viewRef view1
|
||||
(cellRef DPR16X4C))
|
||||
(property MEM_INIT_FILE
|
||||
(string "(0-3)(0-1)"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "pmi_distributed_dpramXbnoner224pb08036b__PMI__4__2__2B"))
|
||||
(property COMP
|
||||
(string "mem_0_0"))
|
||||
(property initval
|
||||
(string "0x0000000000000000")))
|
||||
(net dataout1_ffin
|
||||
(joined
|
||||
(portRef DO1 (instanceRef mem_0_0))
|
||||
(portRef D (instanceRef FF_1))))
|
||||
(net dataout0_ffin
|
||||
(joined
|
||||
(portRef DO0 (instanceRef mem_0_0))
|
||||
(portRef D (instanceRef FF_0))))
|
||||
(net dec0_wre3
|
||||
(joined
|
||||
(portRef WRE (instanceRef mem_0_0))
|
||||
(portRef DO0 (instanceRef LUT4_0))))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))
|
||||
(portRef AD0 (instanceRef LUT4_0))
|
||||
(portRef AD1 (instanceRef LUT4_0))
|
||||
(portRef RAD3 (instanceRef mem_0_0))
|
||||
(portRef RAD2 (instanceRef mem_0_0))
|
||||
(portRef WAD3 (instanceRef mem_0_0))
|
||||
(portRef WAD2 (instanceRef mem_0_0))
|
||||
(portRef DI3 (instanceRef mem_0_0))
|
||||
(portRef DI2 (instanceRef mem_0_0))))
|
||||
(net dataout1
|
||||
(joined
|
||||
(portRef (member Q 0))
|
||||
(portRef Q (instanceRef FF_1))))
|
||||
(net dataout0
|
||||
(joined
|
||||
(portRef (member Q 1))
|
||||
(portRef Q (instanceRef FF_0))))
|
||||
(net reset
|
||||
(joined
|
||||
(portRef Reset)
|
||||
(portRef CD (instanceRef FF_1))
|
||||
(portRef CD (instanceRef FF_0))))
|
||||
(net rden
|
||||
(joined
|
||||
(portRef RdClockEn)
|
||||
(portRef SP (instanceRef FF_1))
|
||||
(portRef SP (instanceRef FF_0))))
|
||||
(net rdclk
|
||||
(joined
|
||||
(portRef RdClock)
|
||||
(portRef CK (instanceRef FF_1))
|
||||
(portRef CK (instanceRef FF_0))))
|
||||
(net raddr1
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
@@ -0,0 +1,233 @@
|
||||
(edif pmi_distributed_dpramXbnoner224pb08036b_0
|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
(timestamp 2026 5 26 15 49 45)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
|
||||
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 4 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner224pb08036b_0 -pmi ")
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
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|
||||
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||||
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|
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|
||||
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|
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(design pmi_distributed_dpramXbnoner224pb08036b_0
|
||||
(cellRef pmi_distributed_dpramXbnoner224pb08036b_0
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
@@ -0,0 +1,239 @@
|
||||
(edif pmi_distributed_dpramXbnoner238pb0819f2
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
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|
||||
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|
||||
(written
|
||||
(timestamp 2026 5 15 18 6 2)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
|
||||
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 8 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner238pb0819f2 -pmi ")
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
@@ -0,0 +1,239 @@
|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
(timestamp 2026 5 15 18 6 2)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
|
||||
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 8 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner238pb0819f2_0 -pmi ")
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
(design pmi_distributed_dpramXbnoner238pb0819f2_0
|
||||
(cellRef pmi_distributed_dpramXbnoner238pb0819f2_0
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
@@ -0,0 +1,239 @@
|
||||
(edif pmi_distributed_dpramXbnoner238pb0819f2_1
|
||||
(edifVersion 2 0 0)
|
||||
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|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
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|
||||
(timestamp 2026 5 15 18 6 2)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
|
||||
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 8 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner238pb0819f2_1 -pmi ")
|
||||
(library ORCLIB
|
||||
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|
||||
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|
||||
(numberDefinition))
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
(cell ROM16X1A
|
||||
(cellType GENERIC)
|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
(cellType GENERIC)
|
||||
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|
||||
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||||
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||||
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|
||||
(direction INPUT))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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||||
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|
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|
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||||
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|
||||
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|
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|
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|
||||
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||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(design pmi_distributed_dpramXbnoner238pb0819f2_1
|
||||
(cellRef pmi_distributed_dpramXbnoner238pb0819f2_1
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,158 @@
|
||||
----------------------------------------------------------------------
|
||||
Report for cell RelayConTop.verilog
|
||||
|
||||
Register bits: 1206 of 6864 (18%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 14
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
CCU2D 41 100.0
|
||||
FD1P3AX 424 100.0
|
||||
FD1P3AY 2 100.0
|
||||
FD1P3BX 32 100.0
|
||||
FD1P3DX 437 100.0
|
||||
FD1P3IX 133 100.0
|
||||
FD1P3JX 1 100.0
|
||||
FD1S3AX 6 100.0
|
||||
FD1S3AY 1 100.0
|
||||
FD1S3BX 3 100.0
|
||||
FD1S3DX 140 100.0
|
||||
FD1S3IX 16 100.0
|
||||
FD1S3JX 1 100.0
|
||||
GSR 1 100.0
|
||||
IB 5 100.0
|
||||
IFS1P3IX 3 100.0
|
||||
IFS1P3JX 1 100.0
|
||||
INV 13 100.0
|
||||
L6MUX21 73 100.0
|
||||
OB 8 100.0
|
||||
OBZ 1 100.0
|
||||
OFS1P3DX 2 100.0
|
||||
OFS1P3JX 4 100.0
|
||||
ORCALUT4 1035 100.0
|
||||
PFUMX 102 100.0
|
||||
PUR 1 100.0
|
||||
VHI 13 100.0
|
||||
VLO 13 100.0
|
||||
jtagconn16 1 100.0
|
||||
pmi_distributed_dpram_2s_1s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 1 100.0
|
||||
pmi_ram_dp_Z4 1 100.0
|
||||
SUB MODULES
|
||||
BUS_Con_uniq_1 1 100.0
|
||||
CPLD_Con_uniq_1 1 100.0
|
||||
Reg_file_uniq_1 1 100.0
|
||||
relaycontop_la0 1 100.0
|
||||
relaycontop_la0_trig 1 100.0
|
||||
reveal_coretop 1 100.0
|
||||
|
||||
TOTAL 2521
|
||||
----------------------------------------------------------------------
|
||||
Report for cell CPLD_Con_uniq_1.netlist
|
||||
Instance path: CPLD_Con_3
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
FD1P3IX 8 6.0
|
||||
FD1P3JX 1 100.0
|
||||
FD1S3IX 6 37.5
|
||||
ORCALUT4 34 3.3
|
||||
VHI 1 7.7
|
||||
VLO 1 7.7
|
||||
|
||||
TOTAL 51
|
||||
----------------------------------------------------------------------
|
||||
Report for cell Reg_file_uniq_1.netlist
|
||||
Instance path: CPLD_Reg_3
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
FD1P3AX 406 95.8
|
||||
FD1P3AY 2 100.0
|
||||
FD1S3AX 4 66.7
|
||||
FD1S3AY 1 100.0
|
||||
L6MUX21 72 98.6
|
||||
ORCALUT4 243 23.5
|
||||
PFUMX 96 94.1
|
||||
VHI 1 7.7
|
||||
VLO 1 7.7
|
||||
|
||||
TOTAL 826
|
||||
----------------------------------------------------------------------
|
||||
Report for cell BUS_Con_uniq_1.netlist
|
||||
Instance path: Bus_Con_3
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
FD1P3IX 125 94.0
|
||||
FD1S3AX 2 33.3
|
||||
FD1S3IX 10 62.5
|
||||
FD1S3JX 1 100.0
|
||||
ORCALUT4 100 9.7
|
||||
VHI 1 7.7
|
||||
VLO 1 7.7
|
||||
|
||||
TOTAL 240
|
||||
----------------------------------------------------------------------
|
||||
Report for cell reveal_coretop.verilog
|
||||
Instance path: RelayConTop_reveal_coretop_instance
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
CCU2D 41 100.0
|
||||
FD1P3AX 18 4.2
|
||||
FD1P3BX 32 100.0
|
||||
FD1P3DX 437 100.0
|
||||
FD1S3BX 3 100.0
|
||||
FD1S3DX 140 100.0
|
||||
INV 12 92.3
|
||||
L6MUX21 1 1.4
|
||||
ORCALUT4 658 63.6
|
||||
PFUMX 6 5.9
|
||||
VHI 9 69.2
|
||||
VLO 9 69.2
|
||||
jtagconn16 1 100.0
|
||||
pmi_distributed_dpram_2s_1s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 1 100.0
|
||||
pmi_ram_dp_Z4 1 100.0
|
||||
SUB MODULES
|
||||
relaycontop_la0 1 100.0
|
||||
relaycontop_la0_trig 1 100.0
|
||||
|
||||
TOTAL 1371
|
||||
----------------------------------------------------------------------
|
||||
Report for cell relaycontop_la0.netlist
|
||||
Instance path: RelayConTop_reveal_coretop_instance.relaycontop_la0_inst_0
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
CCU2D 41 100.0
|
||||
FD1P3AX 18 4.2
|
||||
FD1P3BX 32 100.0
|
||||
FD1P3DX 437 100.0
|
||||
FD1S3BX 3 100.0
|
||||
FD1S3DX 140 100.0
|
||||
INV 12 92.3
|
||||
L6MUX21 1 1.4
|
||||
ORCALUT4 658 63.6
|
||||
PFUMX 6 5.9
|
||||
VHI 8 61.5
|
||||
VLO 8 61.5
|
||||
pmi_distributed_dpram_2s_1s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 1 100.0
|
||||
pmi_ram_dp_Z4 1 100.0
|
||||
SUB MODULES
|
||||
relaycontop_la0_trig 1 100.0
|
||||
|
||||
TOTAL 1367
|
||||
----------------------------------------------------------------------
|
||||
Report for cell relaycontop_la0_trig.netlist
|
||||
Instance path: RelayConTop_reveal_coretop_instance.relaycontop_la0_inst_0.trig_u
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
CCU2D 9 22.0
|
||||
FD1P3AX 16 3.8
|
||||
FD1P3DX 29 6.6
|
||||
FD1S3BX 3 100.0
|
||||
FD1S3DX 22 15.7
|
||||
INV 5 38.5
|
||||
L6MUX21 1 1.4
|
||||
ORCALUT4 119 11.5
|
||||
PFUMX 3 2.9
|
||||
VHI 5 38.5
|
||||
VLO 5 38.5
|
||||
pmi_distributed_dpram_2s_1s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 1 100.0
|
||||
|
||||
TOTAL 218
|
||||
Binary file not shown.
@@ -0,0 +1 @@
|
||||
HUBID_00 REVEAL_0
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,10 @@
|
||||
-v
|
||||
10
|
||||
|
||||
|
||||
|
||||
|
||||
-gt
|
||||
-sethld
|
||||
-sp 4
|
||||
-sphld m
|
||||
@@ -0,0 +1,126 @@
|
||||
[ START MERGED ]
|
||||
i_rst_n_c_i i_rst_n_c
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/dec0_wre3 RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_en
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2.CN jtaghub16_jtck
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jrstn_i jtaghub16_jrstn
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w.CN jtaghub16_jtck
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jrstn_i jtaghub16_jrstn
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/jtck_i jtaghub16_jtck
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/jrstn_i jtaghub16_jrstn
|
||||
xo2chub/cdn.CN jtaghub16_jtck
|
||||
xo2chub/jrstn_i jtaghub16_jrstn
|
||||
[ END MERGED ]
|
||||
[ START CLIPPED ]
|
||||
xo2chub/GND
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/popfeedthru_unused
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/scuba_vlo
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/scuba_vhi
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren_jtck
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/VCC
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_te[2]
|
||||
xo2chub/VCC
|
||||
xo2chub/bit_count_cry_0_COUT[3]
|
||||
xo2chub/rom_rd_addr_cry_0_S0[0]
|
||||
xo2chub/N_2
|
||||
xo2chub/rom_rd_addr_s_0_S1[7]
|
||||
xo2chub/rom_rd_addr_s_0_COUT[7]
|
||||
xo2chub/jtdo2_int_prm_16_0_0_S1
|
||||
xo2chub/jtdo2_int_prm_16_0_0_S0
|
||||
xo2chub/N_3
|
||||
xo2chub/er2_tdo[14]
|
||||
xo2chub/er2_tdo[15]
|
||||
xo2chub/jtdo2_int_prm_15_0_0_S1
|
||||
xo2chub/jtdo2_int_prm_15_0_0_S0
|
||||
xo2chub/er2_tdo[12]
|
||||
xo2chub/er2_tdo[13]
|
||||
xo2chub/jtdo2_int_prm_13_0_0_S1
|
||||
xo2chub/jtdo2_int_prm_13_0_0_S0
|
||||
xo2chub/er2_tdo[10]
|
||||
xo2chub/er2_tdo[11]
|
||||
xo2chub/jtdo2_int_prm_11_0_0_S1
|
||||
xo2chub/jtdo2_int_prm_11_0_0_S0
|
||||
xo2chub/er2_tdo[8]
|
||||
xo2chub/er2_tdo[9]
|
||||
xo2chub/jtdo2_int_prm_9_0_0_S1
|
||||
xo2chub/jtdo2_int_prm_9_0_0_S0
|
||||
xo2chub/er2_tdo[6]
|
||||
xo2chub/er2_tdo[7]
|
||||
xo2chub/jtdo2_int_prm_7_0_0_S1
|
||||
xo2chub/jtdo2_int_prm_7_0_0_S0
|
||||
xo2chub/er2_tdo[4]
|
||||
xo2chub/er2_tdo[5]
|
||||
xo2chub/jtdo2_int_prm_5_0_0_S1
|
||||
xo2chub/jtdo2_int_prm_5_0_0_S0
|
||||
xo2chub/er2_tdo[2]
|
||||
xo2chub/er2_tdo[3]
|
||||
xo2chub/jtdo2_int_prm_3_0_0_S1
|
||||
xo2chub/jtdo2_int_prm_3_0_0_S0
|
||||
xo2chub/er2_tdo[1]
|
||||
xo2chub/jtdo2_int_prm_1_0_0_S0
|
||||
xo2chub/jtdo2_int_prm_1_0_0_COUT
|
||||
xo2chub/ip_enable[15]
|
||||
xo2chub/genblk7.un1_jtagf_u_1
|
||||
xo2chub/genblk7.un1_jtagf_u
|
||||
xo2chub/tdoa
|
||||
xo2chub/tdia
|
||||
xo2chub/tmsa
|
||||
xo2chub/tcka
|
||||
xo2chub/cdn
|
||||
xo2chub/bit_count_cry_0_S0[0]
|
||||
xo2chub/N_1
|
||||
VCC
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/VCC
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/GND
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0_COUT[9]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0_S0[0]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_2
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0_COUT[9]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0_S0[0]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_3
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0_COUT[9]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0_S0[0]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_4
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0_COUT[9]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0_S0[0]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_1
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0_S0[0]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s_0_S1[5]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s_0_COUT[5]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0_S0[0]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0_COUT[5]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/VCC
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/GND
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[4]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0_S0[0]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_1
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s_0_S1[15]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s_0_COUT[15]
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/mem_0_0/DO2
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/mem_0_0/DO3
|
||||
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[3]
|
||||
[ END CLIPPED ]
|
||||
[ START DESIGN PREFS ]
|
||||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.14.0.75.2 -- WARNING: Map write only section -- Tue May 26 15:55:16 2026
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "o_miso" SITE "AA14" ;
|
||||
LOCATE COMP "i_sys_clk" SITE "B9" ;
|
||||
LOCATE COMP "o_err" SITE "AB16" ;
|
||||
LOCATE COMP "o_PMU_RC[3]" SITE "P18" ;
|
||||
LOCATE COMP "o_PMU_RC[2]" SITE "P19" ;
|
||||
LOCATE COMP "o_PMU_RC[1]" SITE "N18" ;
|
||||
LOCATE COMP "o_PMU_RC[0]" SITE "V2" ;
|
||||
LOCATE COMP "i_cs" SITE "AB11" ;
|
||||
LOCATE COMP "i_mosi" SITE "AB12" ;
|
||||
LOCATE COMP "i_sclk" SITE "AA10" ;
|
||||
LOCATE COMP "i_rst_n" SITE "Y14" ;
|
||||
SCHEMATIC END ;
|
||||
[ END DESIGN PREFS ]
|
||||
@@ -0,0 +1,176 @@
|
||||
---------------------------------------------------
|
||||
Report for cell RelayConTop
|
||||
Instance path: RelayConTop
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 746.00 100.0
|
||||
IOLGC 9.00 100.0
|
||||
LUT4 1154.00 100.0
|
||||
DISTRAM 3.00 100.0
|
||||
IOREG 9 100.0
|
||||
IOBUF 14 100.0
|
||||
PFUREG 1252 100.0
|
||||
RIPPLE 58 100.0
|
||||
EBR 24 100.0
|
||||
SUB MODULES
|
||||
cell count SLC Usage(%)
|
||||
xo2chub 1 4.5
|
||||
reveal_coretop 1 56.7
|
||||
Reg_file_uniq_1 1 28.6
|
||||
CPLD_Con_uniq_1 1 1.8
|
||||
BUS_Con_uniq_1 1 8.3
|
||||
---------------------------------------------------
|
||||
Report for cell CPLD_Con_uniq_1
|
||||
Instance path: RelayConTop/CPLD_Con_3
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 13.42 1.8
|
||||
LUT4 34.00 2.9
|
||||
PFUREG 15 1.2
|
||||
---------------------------------------------------
|
||||
Report for cell Reg_file_uniq_1
|
||||
Instance path: RelayConTop/CPLD_Reg_3
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 213.53 28.6
|
||||
LUT4 243.00 21.1
|
||||
PFUREG 413 33.0
|
||||
---------------------------------------------------
|
||||
Report for cell BUS_Con_uniq_1
|
||||
Instance path: RelayConTop/Bus_Con_3
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 61.75 8.3
|
||||
LUT4 100.00 8.7
|
||||
PFUREG 138 11.0
|
||||
---------------------------------------------------
|
||||
Report for cell reveal_coretop
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 423.22 56.7
|
||||
LUT4 763.00 66.1
|
||||
DISTRAM 2.00 66.7
|
||||
PFUREG 634 50.6
|
||||
RIPPLE 41 70.7
|
||||
EBR 24 100.0
|
||||
SUB MODULES
|
||||
cell count SLC Usage(%)
|
||||
relaycontop_la0 1 56.7
|
||||
---------------------------------------------------
|
||||
Report for cell relaycontop_la0
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 423.22 56.7
|
||||
LUT4 763.00 66.1
|
||||
DISTRAM 2.00 66.7
|
||||
PFUREG 634 50.6
|
||||
RIPPLE 41 70.7
|
||||
EBR 24 100.0
|
||||
SUB MODULES
|
||||
cell count SLC Usage(%)
|
||||
rvl_tm_Z3 1 26.6
|
||||
rvl_jtag_int_104s_1s_0s_0s_7s_104s_104s 1 21.3
|
||||
relaycontop_la0_trig 1 8.7
|
||||
---------------------------------------------------
|
||||
Report for cell relaycontop_la0_trig
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 65.10 8.7
|
||||
LUT4 118.00 10.2
|
||||
DISTRAM 2.00 66.7
|
||||
PFUREG 72 5.8
|
||||
RIPPLE 9 15.5
|
||||
SUB MODULES
|
||||
cell count SLC Usage(%)
|
||||
rvl_tu_1s_0s_0s_0s_1s 1 1.3
|
||||
rvl_te_Z1 1 5.6
|
||||
rvl_tcnt_1s_3s_1_0s 1 1.4
|
||||
rvl_decode_1s_1s 1 0.3
|
||||
---------------------------------------------------
|
||||
Report for cell rvl_decode_1s_1s
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 2.23 0.3
|
||||
LUT4 8.50 0.7
|
||||
---------------------------------------------------
|
||||
Report for cell rvl_tu_1s_0s_0s_0s_1s
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 9.62 1.3
|
||||
LUT4 13.00 1.1
|
||||
PFUREG 8 0.6
|
||||
---------------------------------------------------
|
||||
Report for cell rvl_te_Z1
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 41.70 5.6
|
||||
LUT4 65.50 5.7
|
||||
DISTRAM 2.00 66.7
|
||||
PFUREG 52 4.2
|
||||
RIPPLE 9 15.5
|
||||
SUB MODULES
|
||||
cell count SLC Usage(%)
|
||||
pmi_distributed_dpramXbnoner212pb07f9c9 1 0.3
|
||||
---------------------------------------------------
|
||||
Report for cell pmi_distributed_dpramXbnoner212pb07f9c9
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 2.50 0.3
|
||||
LUT4 1.00 0.1
|
||||
DISTRAM 2.00 66.7
|
||||
PFUREG 2 0.2
|
||||
---------------------------------------------------
|
||||
Report for cell rvl_tcnt_1s_3s_1_0s
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 10.32 1.4
|
||||
LUT4 27.00 2.3
|
||||
PFUREG 12 1.0
|
||||
---------------------------------------------------
|
||||
Report for cell rvl_jtag_int_104s_1s_0s_0s_7s_104s_104s
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 159.08 21.3
|
||||
LUT4 373.50 32.4
|
||||
PFUREG 229 18.3
|
||||
RIPPLE 8 13.8
|
||||
---------------------------------------------------
|
||||
Report for cell rvl_tm_Z3
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 198.58 26.6
|
||||
LUT4 270.00 23.4
|
||||
PFUREG 333 26.6
|
||||
RIPPLE 24 41.4
|
||||
EBR 24 100.0
|
||||
SUB MODULES
|
||||
cell count SLC Usage(%)
|
||||
pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b 1 3.6
|
||||
---------------------------------------------------
|
||||
Report for cell pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b
|
||||
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 26.50 3.6
|
||||
LUT4 104.00 9.0
|
||||
PFUREG 2 0.2
|
||||
EBR 24 100.0
|
||||
---------------------------------------------------
|
||||
Report for cell xo2chub
|
||||
Instance path: RelayConTop/xo2chub
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 33.50 4.5
|
||||
LUT4 12.00 1.0
|
||||
PFUREG 51 4.1
|
||||
RIPPLE 17 29.3
|
||||
@@ -0,0 +1,26 @@
|
||||
#
|
||||
# Logical Preferences generated for Lattice by Synplify map202309lat, Build 191R.
|
||||
#
|
||||
|
||||
# Period Constraints
|
||||
#FREQUENCY NET "RelayConTop_reveal_coretop_instance/jtck[0]" 200.0 MHz;
|
||||
#FREQUENCY PORT "i_sys_clk" 200.0 MHz;
|
||||
|
||||
|
||||
# Output Constraints
|
||||
|
||||
# Input Constraints
|
||||
|
||||
# Point-to-point Delay Constraints
|
||||
|
||||
|
||||
|
||||
# Block Path Constraints
|
||||
#BLOCK PATH FROM CLKNET "i_sys_clk_c" TO CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]";
|
||||
#BLOCK PATH FROM CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]" TO CLKNET "i_sys_clk_c";
|
||||
#BLOCK PATH FROM CLKNET "i_sys_clk_c" TO CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]";
|
||||
#BLOCK PATH FROM CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]" TO CLKNET "i_sys_clk_c";
|
||||
|
||||
BLOCK ASYNCPATHS;
|
||||
|
||||
# End of generated Logical Preferences.
|
||||
@@ -0,0 +1 @@
|
||||
-link -encrypt -top RelayConTop -osyn /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD3/impl1/synwork/NewExtIns_CPLD3_impl1_comp.srs /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD3/impl1/synwork/layer0.srs -jobname linker
|
||||
@@ -0,0 +1,52 @@
|
||||
<?xml version='1.0' encoding='utf-8' ?>
|
||||
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
|
||||
<ispXCF version="3.12">
|
||||
<Comment></Comment>
|
||||
<Chain>
|
||||
<Comm>JTAG</Comm>
|
||||
<Device>
|
||||
<SelectedProg value="TRUE"/>
|
||||
<Pos>1</Pos>
|
||||
<Vendor>Lattice</Vendor>
|
||||
<Family>MachXO2</Family>
|
||||
<Name>LCMXO2-7000HC</Name>
|
||||
<IDCode>0x012bd043</IDCode>
|
||||
<Package>All</Package>
|
||||
<PON>LCMXO2-7000HC</PON>
|
||||
<Bypass>
|
||||
<InstrLen>8</InstrLen>
|
||||
<InstrVal>11111111</InstrVal>
|
||||
<BScanLen>1</BScanLen>
|
||||
<BScanVal>0</BScanVal>
|
||||
</Bypass>
|
||||
<File>D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD3/impl1/NewExtIns_CPLD3_impl1.jed</File>
|
||||
<FileTime>01/19/26 18:24:04</FileTime>
|
||||
<JedecChecksum>0x4480</JedecChecksum>
|
||||
<Operation>FLASH Erase,Program,Verify</Operation>
|
||||
<Option>
|
||||
<SVFVendor>JTAG STANDARD</SVFVendor>
|
||||
<IOState>HighZ</IOState>
|
||||
<PreloadLength>664</PreloadLength>
|
||||
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
|
||||
<TCKFrequency>1.000000 MHz</TCKFrequency>
|
||||
<SVFProcessor>SVF Processor</SVFProcessor>
|
||||
<Usercode>0x00000000</Usercode>
|
||||
<AccessMode>FLASH</AccessMode>
|
||||
</Option>
|
||||
</Device>
|
||||
</Chain>
|
||||
<ProjectOptions>
|
||||
<Program>SEQUENTIAL</Program>
|
||||
<Process>ENTIRED CHAIN</Process>
|
||||
<OperationOverride>No Override</OperationOverride>
|
||||
<StartTAP>TLR</StartTAP>
|
||||
<EndTAP>TLR</EndTAP>
|
||||
<VerifyUsercode value="FALSE"/>
|
||||
<TCKDelay>1</TCKDelay>
|
||||
</ProjectOptions>
|
||||
<CableOptions>
|
||||
<CableName>USB</CableName>
|
||||
<PortAdd>EzUSB-0</PortAdd>
|
||||
<USBID>\\?\usb#vid_1134&amp;pid_8001#9&amp;2fe42d87&amp;0&amp;2#</USBID>
|
||||
</CableOptions>
|
||||
</ispXCF>
|
||||
@@ -0,0 +1,227 @@
|
||||
(edif pmi_distributed_dpramXbnoner212pb07f9c9
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2026 5 26 15 55 16)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
|
||||
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 2 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner212pb07f9c9 -pmi ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
(numberDefinition))
|
||||
(cell FD1P3DX
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port D
|
||||
(direction INPUT))
|
||||
(port SP
|
||||
(direction INPUT))
|
||||
(port CK
|
||||
(direction INPUT))
|
||||
(port CD
|
||||
(direction INPUT))
|
||||
(port Q
|
||||
(direction OUTPUT)))))
|
||||
(cell ROM16X1A
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port AD3
|
||||
(direction INPUT))
|
||||
(port AD2
|
||||
(direction INPUT))
|
||||
(port AD1
|
||||
(direction INPUT))
|
||||
(port AD0
|
||||
(direction INPUT))
|
||||
(port DO0
|
||||
(direction OUTPUT)))))
|
||||
(cell DPR16X4C
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port DI0
|
||||
(direction INPUT))
|
||||
(port DI1
|
||||
(direction INPUT))
|
||||
(port DI2
|
||||
(direction INPUT))
|
||||
(port DI3
|
||||
(direction INPUT))
|
||||
(port WCK
|
||||
(direction INPUT))
|
||||
(port WRE
|
||||
(direction INPUT))
|
||||
(port RAD0
|
||||
(direction INPUT))
|
||||
(port RAD1
|
||||
(direction INPUT))
|
||||
(port RAD2
|
||||
(direction INPUT))
|
||||
(port RAD3
|
||||
(direction INPUT))
|
||||
(port WAD0
|
||||
(direction INPUT))
|
||||
(port WAD1
|
||||
(direction INPUT))
|
||||
(port WAD2
|
||||
(direction INPUT))
|
||||
(port WAD3
|
||||
(direction INPUT))
|
||||
(port DO0
|
||||
(direction OUTPUT))
|
||||
(port DO1
|
||||
(direction OUTPUT))
|
||||
(port DO2
|
||||
(direction OUTPUT))
|
||||
(port DO3
|
||||
(direction OUTPUT)))))
|
||||
(cell VHI
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell pmi_distributed_dpramXbnoner212pb07f9c9
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port (array (rename WrAddress "WrAddress(0:0)") 1)
|
||||
(direction INPUT))
|
||||
(port (array (rename Data "Data(1:0)") 2)
|
||||
(direction INPUT))
|
||||
(port WrClock
|
||||
(direction INPUT))
|
||||
(port WE
|
||||
(direction INPUT))
|
||||
(port WrClockEn
|
||||
(direction INPUT))
|
||||
(port (array (rename RdAddress "RdAddress(0:0)") 1)
|
||||
(direction INPUT))
|
||||
(port RdClock
|
||||
(direction INPUT))
|
||||
(port RdClockEn
|
||||
(direction INPUT))
|
||||
(port Reset
|
||||
(direction INPUT))
|
||||
(port (array (rename Q "Q(1:0)") 2)
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance LUT4_0
|
||||
(viewRef view1
|
||||
(cellRef ROM16X1A))
|
||||
(property initval
|
||||
(string "0x8000")))
|
||||
(instance FF_1
|
||||
(viewRef view1
|
||||
(cellRef FD1P3DX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance FF_0
|
||||
(viewRef view1
|
||||
(cellRef FD1P3DX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance scuba_vhi_inst
|
||||
(viewRef view1
|
||||
(cellRef VHI)))
|
||||
(instance mem_0_0
|
||||
(viewRef view1
|
||||
(cellRef DPR16X4C))
|
||||
(property MEM_INIT_FILE
|
||||
(string "(0-1)(0-1)"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "pmi_distributed_dpramXbnoner212pb07f9c9__PMI__2__2__2B"))
|
||||
(property COMP
|
||||
(string "mem_0_0"))
|
||||
(property initval
|
||||
(string "0x0000000000000000")))
|
||||
(net dataout1_ffin
|
||||
(joined
|
||||
(portRef DO1 (instanceRef mem_0_0))
|
||||
(portRef D (instanceRef FF_1))))
|
||||
(net dataout0_ffin
|
||||
(joined
|
||||
(portRef DO0 (instanceRef mem_0_0))
|
||||
(portRef D (instanceRef FF_0))))
|
||||
(net dec0_wre3
|
||||
(joined
|
||||
(portRef WRE (instanceRef mem_0_0))
|
||||
(portRef DO0 (instanceRef LUT4_0))))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))
|
||||
(portRef AD0 (instanceRef LUT4_0))
|
||||
(portRef AD1 (instanceRef LUT4_0))
|
||||
(portRef RAD3 (instanceRef mem_0_0))
|
||||
(portRef RAD2 (instanceRef mem_0_0))
|
||||
(portRef RAD1 (instanceRef mem_0_0))
|
||||
(portRef WAD3 (instanceRef mem_0_0))
|
||||
(portRef WAD2 (instanceRef mem_0_0))
|
||||
(portRef WAD1 (instanceRef mem_0_0))
|
||||
(portRef DI3 (instanceRef mem_0_0))
|
||||
(portRef DI2 (instanceRef mem_0_0))))
|
||||
(net dataout1
|
||||
(joined
|
||||
(portRef (member Q 0))
|
||||
(portRef Q (instanceRef FF_1))))
|
||||
(net dataout0
|
||||
(joined
|
||||
(portRef (member Q 1))
|
||||
(portRef Q (instanceRef FF_0))))
|
||||
(net reset
|
||||
(joined
|
||||
(portRef Reset)
|
||||
(portRef CD (instanceRef FF_1))
|
||||
(portRef CD (instanceRef FF_0))))
|
||||
(net rden
|
||||
(joined
|
||||
(portRef RdClockEn)
|
||||
(portRef SP (instanceRef FF_1))
|
||||
(portRef SP (instanceRef FF_0))))
|
||||
(net rdclk
|
||||
(joined
|
||||
(portRef RdClock)
|
||||
(portRef CK (instanceRef FF_1))
|
||||
(portRef CK (instanceRef FF_0))))
|
||||
(net raddr0
|
||||
(joined
|
||||
(portRef (member RdAddress 0))
|
||||
(portRef RAD0 (instanceRef mem_0_0))))
|
||||
(net cken
|
||||
(joined
|
||||
(portRef WrClockEn)
|
||||
(portRef AD2 (instanceRef LUT4_0))))
|
||||
(net wren
|
||||
(joined
|
||||
(portRef WE)
|
||||
(portRef AD3 (instanceRef LUT4_0))))
|
||||
(net clk
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
@@ -0,0 +1,233 @@
|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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@@ -0,0 +1,233 @@
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||||
(edif pmi_distributed_dpramXbnoner224pb08036b_0
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||||
(timestamp 2026 5 14 11 40 52)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
|
||||
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 4 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner224pb08036b_0 -pmi ")
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||||
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||||
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||||
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||||
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||||
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|
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
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|
||||
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|
||||
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|
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(design pmi_distributed_dpramXbnoner224pb08036b_0
|
||||
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||||
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|
||||
)
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,413 @@
|
||||
(edif pmi_ram_dpXbnonesadr11120481112048p1371b9e1
|
||||
(edifVersion 2 0 0)
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(edifLevel 0)
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||||
(keywordMap (keywordLevel 0))
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||||
(status
|
||||
(written
|
||||
(timestamp 2026 5 22 15 39 37)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
|
||||
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 1 -num_rows 2048 -rdata_width 1 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr11120481112048p1371b9e1 -pmi ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
(numberDefinition))
|
||||
(cell VHI
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell VLO
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell DP8KC
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port DIA8
|
||||
(direction INPUT))
|
||||
(port DIA7
|
||||
(direction INPUT))
|
||||
(port DIA6
|
||||
(direction INPUT))
|
||||
(port DIA5
|
||||
(direction INPUT))
|
||||
(port DIA4
|
||||
(direction INPUT))
|
||||
(port DIA3
|
||||
(direction INPUT))
|
||||
(port DIA2
|
||||
(direction INPUT))
|
||||
(port DIA1
|
||||
(direction INPUT))
|
||||
(port DIA0
|
||||
(direction INPUT))
|
||||
(port ADA12
|
||||
(direction INPUT))
|
||||
(port ADA11
|
||||
(direction INPUT))
|
||||
(port ADA10
|
||||
(direction INPUT))
|
||||
(port ADA9
|
||||
(direction INPUT))
|
||||
(port ADA8
|
||||
(direction INPUT))
|
||||
(port ADA7
|
||||
(direction INPUT))
|
||||
(port ADA6
|
||||
(direction INPUT))
|
||||
(port ADA5
|
||||
(direction INPUT))
|
||||
(port ADA4
|
||||
(direction INPUT))
|
||||
(port ADA3
|
||||
(direction INPUT))
|
||||
(port ADA2
|
||||
(direction INPUT))
|
||||
(port ADA1
|
||||
(direction INPUT))
|
||||
(port ADA0
|
||||
(direction INPUT))
|
||||
(port CEA
|
||||
(direction INPUT))
|
||||
(port OCEA
|
||||
(direction INPUT))
|
||||
(port CLKA
|
||||
(direction INPUT))
|
||||
(port WEA
|
||||
(direction INPUT))
|
||||
(port CSA2
|
||||
(direction INPUT))
|
||||
(port CSA1
|
||||
(direction INPUT))
|
||||
(port CSA0
|
||||
(direction INPUT))
|
||||
(port RSTA
|
||||
(direction INPUT))
|
||||
(port DIB8
|
||||
(direction INPUT))
|
||||
(port DIB7
|
||||
(direction INPUT))
|
||||
(port DIB6
|
||||
(direction INPUT))
|
||||
(port DIB5
|
||||
(direction INPUT))
|
||||
(port DIB4
|
||||
(direction INPUT))
|
||||
(port DIB3
|
||||
(direction INPUT))
|
||||
(port DIB2
|
||||
(direction INPUT))
|
||||
(port DIB1
|
||||
(direction INPUT))
|
||||
(port DIB0
|
||||
(direction INPUT))
|
||||
(port ADB12
|
||||
(direction INPUT))
|
||||
(port ADB11
|
||||
(direction INPUT))
|
||||
(port ADB10
|
||||
(direction INPUT))
|
||||
(port ADB9
|
||||
(direction INPUT))
|
||||
(port ADB8
|
||||
(direction INPUT))
|
||||
(port ADB7
|
||||
(direction INPUT))
|
||||
(port ADB6
|
||||
(direction INPUT))
|
||||
(port ADB5
|
||||
(direction INPUT))
|
||||
(port ADB4
|
||||
(direction INPUT))
|
||||
(port ADB3
|
||||
(direction INPUT))
|
||||
(port ADB2
|
||||
(direction INPUT))
|
||||
(port ADB1
|
||||
(direction INPUT))
|
||||
(port ADB0
|
||||
(direction INPUT))
|
||||
(port CEB
|
||||
(direction INPUT))
|
||||
(port OCEB
|
||||
(direction INPUT))
|
||||
(port CLKB
|
||||
(direction INPUT))
|
||||
(port WEB
|
||||
(direction INPUT))
|
||||
(port CSB2
|
||||
(direction INPUT))
|
||||
(port CSB1
|
||||
(direction INPUT))
|
||||
(port CSB0
|
||||
(direction INPUT))
|
||||
(port RSTB
|
||||
(direction INPUT))
|
||||
(port DOA8
|
||||
(direction OUTPUT))
|
||||
(port DOA7
|
||||
(direction OUTPUT))
|
||||
(port DOA6
|
||||
(direction OUTPUT))
|
||||
(port DOA5
|
||||
(direction OUTPUT))
|
||||
(port DOA4
|
||||
(direction OUTPUT))
|
||||
(port DOA3
|
||||
(direction OUTPUT))
|
||||
(port DOA2
|
||||
(direction OUTPUT))
|
||||
(port DOA1
|
||||
(direction OUTPUT))
|
||||
(port DOA0
|
||||
(direction OUTPUT))
|
||||
(port DOB8
|
||||
(direction OUTPUT))
|
||||
(port DOB7
|
||||
(direction OUTPUT))
|
||||
(port DOB6
|
||||
(direction OUTPUT))
|
||||
(port DOB5
|
||||
(direction OUTPUT))
|
||||
(port DOB4
|
||||
(direction OUTPUT))
|
||||
(port DOB3
|
||||
(direction OUTPUT))
|
||||
(port DOB2
|
||||
(direction OUTPUT))
|
||||
(port DOB1
|
||||
(direction OUTPUT))
|
||||
(port DOB0
|
||||
(direction OUTPUT)))))
|
||||
(cell pmi_ram_dpXbnonesadr11120481112048p1371b9e1
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port (array (rename WrAddress "WrAddress(10:0)") 11)
|
||||
(direction INPUT))
|
||||
(port (array (rename RdAddress "RdAddress(10:0)") 11)
|
||||
(direction INPUT))
|
||||
(port (array (rename Data "Data(0:0)") 1)
|
||||
(direction INPUT))
|
||||
(port WE
|
||||
(direction INPUT))
|
||||
(port RdClock
|
||||
(direction INPUT))
|
||||
(port RdClockEn
|
||||
(direction INPUT))
|
||||
(port Reset
|
||||
(direction INPUT))
|
||||
(port WrClock
|
||||
(direction INPUT))
|
||||
(port WrClockEn
|
||||
(direction INPUT))
|
||||
(port (array (rename Q "Q(0:0)") 1)
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance scuba_vhi_inst
|
||||
(viewRef view1
|
||||
(cellRef VHI)))
|
||||
(instance scuba_vlo_inst
|
||||
(viewRef view1
|
||||
(cellRef VLO)))
|
||||
(instance pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0
|
||||
(viewRef view1
|
||||
(cellRef DP8KC))
|
||||
(property INIT_DATA
|
||||
(string "STATIC"))
|
||||
(property ASYNC_RESET_RELEASE
|
||||
(string "ASYNC"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "pmi_ram_dpXbnonesadr11120481112048p1371b9e1__PMIP__2048__1__1__-1B"))
|
||||
(property MEM_INIT_FILE
|
||||
(string ""))
|
||||
(property CSDECODE_B
|
||||
(string "0b000"))
|
||||
(property CSDECODE_A
|
||||
(string "0b000"))
|
||||
(property WRITEMODE_B
|
||||
(string "NORMAL"))
|
||||
(property WRITEMODE_A
|
||||
(string "NORMAL"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property RESETMODE
|
||||
(string "ASYNC"))
|
||||
(property REGMODE_B
|
||||
(string "OUTREG"))
|
||||
(property REGMODE_A
|
||||
(string "OUTREG"))
|
||||
(property DATA_WIDTH_B
|
||||
(string "4"))
|
||||
(property DATA_WIDTH_A
|
||||
(string "4")))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))))
|
||||
(net scuba_vlo
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vlo_inst))
|
||||
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net dataout0
|
||||
(joined
|
||||
(portRef (member Q 0))
|
||||
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net WrClockEn
|
||||
(joined
|
||||
(portRef WrClockEn)
|
||||
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net clk
|
||||
(joined
|
||||
(portRef WrClock)
|
||||
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net Reset
|
||||
(joined
|
||||
(portRef Reset)
|
||||
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net RdClockEn
|
||||
(joined
|
||||
(portRef RdClockEn)
|
||||
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))
|
||||
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net rdclk
|
||||
(joined
|
||||
(portRef RdClock)
|
||||
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net wren
|
||||
(joined
|
||||
(portRef WE)
|
||||
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net datain0
|
||||
(joined
|
||||
(portRef (member Data 0))
|
||||
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net raddr10
|
||||
(joined
|
||||
(portRef (member RdAddress 0))
|
||||
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net raddr9
|
||||
(joined
|
||||
(portRef (member RdAddress 1))
|
||||
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net raddr8
|
||||
(joined
|
||||
(portRef (member RdAddress 2))
|
||||
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net raddr7
|
||||
(joined
|
||||
(portRef (member RdAddress 3))
|
||||
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net raddr6
|
||||
(joined
|
||||
(portRef (member RdAddress 4))
|
||||
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net raddr5
|
||||
(joined
|
||||
(portRef (member RdAddress 5))
|
||||
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net raddr4
|
||||
(joined
|
||||
(portRef (member RdAddress 6))
|
||||
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net raddr3
|
||||
(joined
|
||||
(portRef (member RdAddress 7))
|
||||
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net raddr2
|
||||
(joined
|
||||
(portRef (member RdAddress 8))
|
||||
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net raddr1
|
||||
(joined
|
||||
(portRef (member RdAddress 9))
|
||||
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net raddr0
|
||||
(joined
|
||||
(portRef (member RdAddress 10))
|
||||
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net waddr10
|
||||
(joined
|
||||
(portRef (member WrAddress 0))
|
||||
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net waddr9
|
||||
(joined
|
||||
(portRef (member WrAddress 1))
|
||||
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net waddr8
|
||||
(joined
|
||||
(portRef (member WrAddress 2))
|
||||
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net waddr7
|
||||
(joined
|
||||
(portRef (member WrAddress 3))
|
||||
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net waddr6
|
||||
(joined
|
||||
(portRef (member WrAddress 4))
|
||||
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net waddr5
|
||||
(joined
|
||||
(portRef (member WrAddress 5))
|
||||
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net waddr4
|
||||
(joined
|
||||
(portRef (member WrAddress 6))
|
||||
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net waddr3
|
||||
(joined
|
||||
(portRef (member WrAddress 7))
|
||||
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net waddr2
|
||||
(joined
|
||||
(portRef (member WrAddress 8))
|
||||
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net waddr1
|
||||
(joined
|
||||
(portRef (member WrAddress 9))
|
||||
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))
|
||||
(net waddr0
|
||||
(joined
|
||||
(portRef (member WrAddress 10))
|
||||
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0))))))))
|
||||
(design pmi_ram_dpXbnonesadr11120481112048p1371b9e1
|
||||
(cellRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
@@ -0,0 +1,672 @@
|
||||
(edif pmi_ram_dpXbnonesadr1211204812112048p1395b04f
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2026 1 19 16 42 24)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2"))))
|
||||
(comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 12 -num_rows 2048 -rdata_width 12 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr1211204812112048p1395b04f -pmi ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
(numberDefinition))
|
||||
(cell VHI
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell VLO
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell DP8KC
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port DIA8
|
||||
(direction INPUT))
|
||||
(port DIA7
|
||||
(direction INPUT))
|
||||
(port DIA6
|
||||
(direction INPUT))
|
||||
(port DIA5
|
||||
(direction INPUT))
|
||||
(port DIA4
|
||||
(direction INPUT))
|
||||
(port DIA3
|
||||
(direction INPUT))
|
||||
(port DIA2
|
||||
(direction INPUT))
|
||||
(port DIA1
|
||||
(direction INPUT))
|
||||
(port DIA0
|
||||
(direction INPUT))
|
||||
(port ADA12
|
||||
(direction INPUT))
|
||||
(port ADA11
|
||||
(direction INPUT))
|
||||
(port ADA10
|
||||
(direction INPUT))
|
||||
(port ADA9
|
||||
(direction INPUT))
|
||||
(port ADA8
|
||||
(direction INPUT))
|
||||
(port ADA7
|
||||
(direction INPUT))
|
||||
(port ADA6
|
||||
(direction INPUT))
|
||||
(port ADA5
|
||||
(direction INPUT))
|
||||
(port ADA4
|
||||
(direction INPUT))
|
||||
(port ADA3
|
||||
(direction INPUT))
|
||||
(port ADA2
|
||||
(direction INPUT))
|
||||
(port ADA1
|
||||
(direction INPUT))
|
||||
(port ADA0
|
||||
(direction INPUT))
|
||||
(port CEA
|
||||
(direction INPUT))
|
||||
(port OCEA
|
||||
(direction INPUT))
|
||||
(port CLKA
|
||||
(direction INPUT))
|
||||
(port WEA
|
||||
(direction INPUT))
|
||||
(port CSA2
|
||||
(direction INPUT))
|
||||
(port CSA1
|
||||
(direction INPUT))
|
||||
(port CSA0
|
||||
(direction INPUT))
|
||||
(port RSTA
|
||||
(direction INPUT))
|
||||
(port DIB8
|
||||
(direction INPUT))
|
||||
(port DIB7
|
||||
(direction INPUT))
|
||||
(port DIB6
|
||||
(direction INPUT))
|
||||
(port DIB5
|
||||
(direction INPUT))
|
||||
(port DIB4
|
||||
(direction INPUT))
|
||||
(port DIB3
|
||||
(direction INPUT))
|
||||
(port DIB2
|
||||
(direction INPUT))
|
||||
(port DIB1
|
||||
(direction INPUT))
|
||||
(port DIB0
|
||||
(direction INPUT))
|
||||
(port ADB12
|
||||
(direction INPUT))
|
||||
(port ADB11
|
||||
(direction INPUT))
|
||||
(port ADB10
|
||||
(direction INPUT))
|
||||
(port ADB9
|
||||
(direction INPUT))
|
||||
(port ADB8
|
||||
(direction INPUT))
|
||||
(port ADB7
|
||||
(direction INPUT))
|
||||
(port ADB6
|
||||
(direction INPUT))
|
||||
(port ADB5
|
||||
(direction INPUT))
|
||||
(port ADB4
|
||||
(direction INPUT))
|
||||
(port ADB3
|
||||
(direction INPUT))
|
||||
(port ADB2
|
||||
(direction INPUT))
|
||||
(port ADB1
|
||||
(direction INPUT))
|
||||
(port ADB0
|
||||
(direction INPUT))
|
||||
(port CEB
|
||||
(direction INPUT))
|
||||
(port OCEB
|
||||
(direction INPUT))
|
||||
(port CLKB
|
||||
(direction INPUT))
|
||||
(port WEB
|
||||
(direction INPUT))
|
||||
(port CSB2
|
||||
(direction INPUT))
|
||||
(port CSB1
|
||||
(direction INPUT))
|
||||
(port CSB0
|
||||
(direction INPUT))
|
||||
(port RSTB
|
||||
(direction INPUT))
|
||||
(port DOA8
|
||||
(direction OUTPUT))
|
||||
(port DOA7
|
||||
(direction OUTPUT))
|
||||
(port DOA6
|
||||
(direction OUTPUT))
|
||||
(port DOA5
|
||||
(direction OUTPUT))
|
||||
(port DOA4
|
||||
(direction OUTPUT))
|
||||
(port DOA3
|
||||
(direction OUTPUT))
|
||||
(port DOA2
|
||||
(direction OUTPUT))
|
||||
(port DOA1
|
||||
(direction OUTPUT))
|
||||
(port DOA0
|
||||
(direction OUTPUT))
|
||||
(port DOB8
|
||||
(direction OUTPUT))
|
||||
(port DOB7
|
||||
(direction OUTPUT))
|
||||
(port DOB6
|
||||
(direction OUTPUT))
|
||||
(port DOB5
|
||||
(direction OUTPUT))
|
||||
(port DOB4
|
||||
(direction OUTPUT))
|
||||
(port DOB3
|
||||
(direction OUTPUT))
|
||||
(port DOB2
|
||||
(direction OUTPUT))
|
||||
(port DOB1
|
||||
(direction OUTPUT))
|
||||
(port DOB0
|
||||
(direction OUTPUT)))))
|
||||
(cell pmi_ram_dpXbnonesadr1211204812112048p1395b04f
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port (array (rename WrAddress "WrAddress(10:0)") 11)
|
||||
(direction INPUT))
|
||||
(port (array (rename RdAddress "RdAddress(10:0)") 11)
|
||||
(direction INPUT))
|
||||
(port (array (rename Data "Data(11:0)") 12)
|
||||
(direction INPUT))
|
||||
(port WE
|
||||
(direction INPUT))
|
||||
(port RdClock
|
||||
(direction INPUT))
|
||||
(port RdClockEn
|
||||
(direction INPUT))
|
||||
(port Reset
|
||||
(direction INPUT))
|
||||
(port WrClock
|
||||
(direction INPUT))
|
||||
(port WrClockEn
|
||||
(direction INPUT))
|
||||
(port (array (rename Q "Q(11:0)") 12)
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance scuba_vhi_inst
|
||||
(viewRef view1
|
||||
(cellRef VHI)))
|
||||
(instance pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2
|
||||
(viewRef view1
|
||||
(cellRef DP8KC))
|
||||
(property INIT_DATA
|
||||
(string "STATIC"))
|
||||
(property ASYNC_RESET_RELEASE
|
||||
(string "ASYNC"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "pmi_ram_dpXbnonesadr1211204812112048p1395b04f__PMIP__2048__12__12__-1B"))
|
||||
(property MEM_INIT_FILE
|
||||
(string ""))
|
||||
(property CSDECODE_B
|
||||
(string "0b000"))
|
||||
(property CSDECODE_A
|
||||
(string "0b000"))
|
||||
(property WRITEMODE_B
|
||||
(string "NORMAL"))
|
||||
(property WRITEMODE_A
|
||||
(string "NORMAL"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property RESETMODE
|
||||
(string "ASYNC"))
|
||||
(property REGMODE_B
|
||||
(string "OUTREG"))
|
||||
(property REGMODE_A
|
||||
(string "OUTREG"))
|
||||
(property DATA_WIDTH_B
|
||||
(string "4"))
|
||||
(property DATA_WIDTH_A
|
||||
(string "4")))
|
||||
(instance pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1
|
||||
(viewRef view1
|
||||
(cellRef DP8KC))
|
||||
(property INIT_DATA
|
||||
(string "STATIC"))
|
||||
(property ASYNC_RESET_RELEASE
|
||||
(string "ASYNC"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "pmi_ram_dpXbnonesadr1211204812112048p1395b04f__PMIP__2048__12__12__-1B"))
|
||||
(property MEM_INIT_FILE
|
||||
(string ""))
|
||||
(property CSDECODE_B
|
||||
(string "0b000"))
|
||||
(property CSDECODE_A
|
||||
(string "0b000"))
|
||||
(property WRITEMODE_B
|
||||
(string "NORMAL"))
|
||||
(property WRITEMODE_A
|
||||
(string "NORMAL"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property RESETMODE
|
||||
(string "ASYNC"))
|
||||
(property REGMODE_B
|
||||
(string "OUTREG"))
|
||||
(property REGMODE_A
|
||||
(string "OUTREG"))
|
||||
(property DATA_WIDTH_B
|
||||
(string "4"))
|
||||
(property DATA_WIDTH_A
|
||||
(string "4")))
|
||||
(instance scuba_vlo_inst
|
||||
(viewRef view1
|
||||
(cellRef VLO)))
|
||||
(instance pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0
|
||||
(viewRef view1
|
||||
(cellRef DP8KC))
|
||||
(property INIT_DATA
|
||||
(string "STATIC"))
|
||||
(property ASYNC_RESET_RELEASE
|
||||
(string "ASYNC"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "pmi_ram_dpXbnonesadr1211204812112048p1395b04f__PMIP__2048__12__12__-1B"))
|
||||
(property MEM_INIT_FILE
|
||||
(string ""))
|
||||
(property CSDECODE_B
|
||||
(string "0b000"))
|
||||
(property CSDECODE_A
|
||||
(string "0b000"))
|
||||
(property WRITEMODE_B
|
||||
(string "NORMAL"))
|
||||
(property WRITEMODE_A
|
||||
(string "NORMAL"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property RESETMODE
|
||||
(string "ASYNC"))
|
||||
(property REGMODE_B
|
||||
(string "OUTREG"))
|
||||
(property REGMODE_A
|
||||
(string "OUTREG"))
|
||||
(property DATA_WIDTH_B
|
||||
(string "4"))
|
||||
(property DATA_WIDTH_A
|
||||
(string "4")))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))))
|
||||
(net scuba_vlo
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vlo_inst))
|
||||
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net dataout11
|
||||
(joined
|
||||
(portRef (member Q 0))
|
||||
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net dataout10
|
||||
(joined
|
||||
(portRef (member Q 1))
|
||||
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net dataout9
|
||||
(joined
|
||||
(portRef (member Q 2))
|
||||
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net dataout8
|
||||
(joined
|
||||
(portRef (member Q 3))
|
||||
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net dataout7
|
||||
(joined
|
||||
(portRef (member Q 4))
|
||||
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))))
|
||||
(net dataout6
|
||||
(joined
|
||||
(portRef (member Q 5))
|
||||
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))))
|
||||
(net dataout5
|
||||
(joined
|
||||
(portRef (member Q 6))
|
||||
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))))
|
||||
(net dataout4
|
||||
(joined
|
||||
(portRef (member Q 7))
|
||||
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))))
|
||||
(net dataout3
|
||||
(joined
|
||||
(portRef (member Q 8))
|
||||
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))))
|
||||
(net dataout2
|
||||
(joined
|
||||
(portRef (member Q 9))
|
||||
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))))
|
||||
(net dataout1
|
||||
(joined
|
||||
(portRef (member Q 10))
|
||||
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))))
|
||||
(net dataout0
|
||||
(joined
|
||||
(portRef (member Q 11))
|
||||
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))))
|
||||
(net WrClockEn
|
||||
(joined
|
||||
(portRef WrClockEn)
|
||||
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net clk
|
||||
(joined
|
||||
(portRef WrClock)
|
||||
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net Reset
|
||||
(joined
|
||||
(portRef Reset)
|
||||
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net RdClockEn
|
||||
(joined
|
||||
(portRef RdClockEn)
|
||||
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))
|
||||
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net rdclk
|
||||
(joined
|
||||
(portRef RdClock)
|
||||
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net wren
|
||||
(joined
|
||||
(portRef WE)
|
||||
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net datain11
|
||||
(joined
|
||||
(portRef (member Data 0))
|
||||
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net datain10
|
||||
(joined
|
||||
(portRef (member Data 1))
|
||||
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net datain9
|
||||
(joined
|
||||
(portRef (member Data 2))
|
||||
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net datain8
|
||||
(joined
|
||||
(portRef (member Data 3))
|
||||
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net datain7
|
||||
(joined
|
||||
(portRef (member Data 4))
|
||||
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))))
|
||||
(net datain6
|
||||
(joined
|
||||
(portRef (member Data 5))
|
||||
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))))
|
||||
(net datain5
|
||||
(joined
|
||||
(portRef (member Data 6))
|
||||
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))))
|
||||
(net datain4
|
||||
(joined
|
||||
(portRef (member Data 7))
|
||||
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))))
|
||||
(net datain3
|
||||
(joined
|
||||
(portRef (member Data 8))
|
||||
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))))
|
||||
(net datain2
|
||||
(joined
|
||||
(portRef (member Data 9))
|
||||
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))))
|
||||
(net datain1
|
||||
(joined
|
||||
(portRef (member Data 10))
|
||||
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))))
|
||||
(net datain0
|
||||
(joined
|
||||
(portRef (member Data 11))
|
||||
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))))
|
||||
(net raddr10
|
||||
(joined
|
||||
(portRef (member RdAddress 0))
|
||||
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net raddr9
|
||||
(joined
|
||||
(portRef (member RdAddress 1))
|
||||
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net raddr8
|
||||
(joined
|
||||
(portRef (member RdAddress 2))
|
||||
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net raddr7
|
||||
(joined
|
||||
(portRef (member RdAddress 3))
|
||||
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net raddr6
|
||||
(joined
|
||||
(portRef (member RdAddress 4))
|
||||
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net raddr5
|
||||
(joined
|
||||
(portRef (member RdAddress 5))
|
||||
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net raddr4
|
||||
(joined
|
||||
(portRef (member RdAddress 6))
|
||||
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net raddr3
|
||||
(joined
|
||||
(portRef (member RdAddress 7))
|
||||
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net raddr2
|
||||
(joined
|
||||
(portRef (member RdAddress 8))
|
||||
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net raddr1
|
||||
(joined
|
||||
(portRef (member RdAddress 9))
|
||||
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net raddr0
|
||||
(joined
|
||||
(portRef (member RdAddress 10))
|
||||
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net waddr10
|
||||
(joined
|
||||
(portRef (member WrAddress 0))
|
||||
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net waddr9
|
||||
(joined
|
||||
(portRef (member WrAddress 1))
|
||||
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net waddr8
|
||||
(joined
|
||||
(portRef (member WrAddress 2))
|
||||
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net waddr7
|
||||
(joined
|
||||
(portRef (member WrAddress 3))
|
||||
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net waddr6
|
||||
(joined
|
||||
(portRef (member WrAddress 4))
|
||||
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net waddr5
|
||||
(joined
|
||||
(portRef (member WrAddress 5))
|
||||
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net waddr4
|
||||
(joined
|
||||
(portRef (member WrAddress 6))
|
||||
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net waddr3
|
||||
(joined
|
||||
(portRef (member WrAddress 7))
|
||||
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net waddr2
|
||||
(joined
|
||||
(portRef (member WrAddress 8))
|
||||
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net waddr1
|
||||
(joined
|
||||
(portRef (member WrAddress 9))
|
||||
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))
|
||||
(net waddr0
|
||||
(joined
|
||||
(portRef (member WrAddress 10))
|
||||
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2))
|
||||
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1))
|
||||
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0))))))))
|
||||
(design pmi_ram_dpXbnonesadr1211204812112048p1395b04f
|
||||
(cellRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
@@ -0,0 +1,434 @@
|
||||
(edif pmi_ram_dpXbnonesadr41120484112048p1371d0a0
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2026 5 15 18 14 2)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
|
||||
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 4 -num_rows 2048 -rdata_width 4 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr41120484112048p1371d0a0 -pmi ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
(numberDefinition))
|
||||
(cell VHI
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell VLO
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell DP8KC
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port DIA8
|
||||
(direction INPUT))
|
||||
(port DIA7
|
||||
(direction INPUT))
|
||||
(port DIA6
|
||||
(direction INPUT))
|
||||
(port DIA5
|
||||
(direction INPUT))
|
||||
(port DIA4
|
||||
(direction INPUT))
|
||||
(port DIA3
|
||||
(direction INPUT))
|
||||
(port DIA2
|
||||
(direction INPUT))
|
||||
(port DIA1
|
||||
(direction INPUT))
|
||||
(port DIA0
|
||||
(direction INPUT))
|
||||
(port ADA12
|
||||
(direction INPUT))
|
||||
(port ADA11
|
||||
(direction INPUT))
|
||||
(port ADA10
|
||||
(direction INPUT))
|
||||
(port ADA9
|
||||
(direction INPUT))
|
||||
(port ADA8
|
||||
(direction INPUT))
|
||||
(port ADA7
|
||||
(direction INPUT))
|
||||
(port ADA6
|
||||
(direction INPUT))
|
||||
(port ADA5
|
||||
(direction INPUT))
|
||||
(port ADA4
|
||||
(direction INPUT))
|
||||
(port ADA3
|
||||
(direction INPUT))
|
||||
(port ADA2
|
||||
(direction INPUT))
|
||||
(port ADA1
|
||||
(direction INPUT))
|
||||
(port ADA0
|
||||
(direction INPUT))
|
||||
(port CEA
|
||||
(direction INPUT))
|
||||
(port OCEA
|
||||
(direction INPUT))
|
||||
(port CLKA
|
||||
(direction INPUT))
|
||||
(port WEA
|
||||
(direction INPUT))
|
||||
(port CSA2
|
||||
(direction INPUT))
|
||||
(port CSA1
|
||||
(direction INPUT))
|
||||
(port CSA0
|
||||
(direction INPUT))
|
||||
(port RSTA
|
||||
(direction INPUT))
|
||||
(port DIB8
|
||||
(direction INPUT))
|
||||
(port DIB7
|
||||
(direction INPUT))
|
||||
(port DIB6
|
||||
(direction INPUT))
|
||||
(port DIB5
|
||||
(direction INPUT))
|
||||
(port DIB4
|
||||
(direction INPUT))
|
||||
(port DIB3
|
||||
(direction INPUT))
|
||||
(port DIB2
|
||||
(direction INPUT))
|
||||
(port DIB1
|
||||
(direction INPUT))
|
||||
(port DIB0
|
||||
(direction INPUT))
|
||||
(port ADB12
|
||||
(direction INPUT))
|
||||
(port ADB11
|
||||
(direction INPUT))
|
||||
(port ADB10
|
||||
(direction INPUT))
|
||||
(port ADB9
|
||||
(direction INPUT))
|
||||
(port ADB8
|
||||
(direction INPUT))
|
||||
(port ADB7
|
||||
(direction INPUT))
|
||||
(port ADB6
|
||||
(direction INPUT))
|
||||
(port ADB5
|
||||
(direction INPUT))
|
||||
(port ADB4
|
||||
(direction INPUT))
|
||||
(port ADB3
|
||||
(direction INPUT))
|
||||
(port ADB2
|
||||
(direction INPUT))
|
||||
(port ADB1
|
||||
(direction INPUT))
|
||||
(port ADB0
|
||||
(direction INPUT))
|
||||
(port CEB
|
||||
(direction INPUT))
|
||||
(port OCEB
|
||||
(direction INPUT))
|
||||
(port CLKB
|
||||
(direction INPUT))
|
||||
(port WEB
|
||||
(direction INPUT))
|
||||
(port CSB2
|
||||
(direction INPUT))
|
||||
(port CSB1
|
||||
(direction INPUT))
|
||||
(port CSB0
|
||||
(direction INPUT))
|
||||
(port RSTB
|
||||
(direction INPUT))
|
||||
(port DOA8
|
||||
(direction OUTPUT))
|
||||
(port DOA7
|
||||
(direction OUTPUT))
|
||||
(port DOA6
|
||||
(direction OUTPUT))
|
||||
(port DOA5
|
||||
(direction OUTPUT))
|
||||
(port DOA4
|
||||
(direction OUTPUT))
|
||||
(port DOA3
|
||||
(direction OUTPUT))
|
||||
(port DOA2
|
||||
(direction OUTPUT))
|
||||
(port DOA1
|
||||
(direction OUTPUT))
|
||||
(port DOA0
|
||||
(direction OUTPUT))
|
||||
(port DOB8
|
||||
(direction OUTPUT))
|
||||
(port DOB7
|
||||
(direction OUTPUT))
|
||||
(port DOB6
|
||||
(direction OUTPUT))
|
||||
(port DOB5
|
||||
(direction OUTPUT))
|
||||
(port DOB4
|
||||
(direction OUTPUT))
|
||||
(port DOB3
|
||||
(direction OUTPUT))
|
||||
(port DOB2
|
||||
(direction OUTPUT))
|
||||
(port DOB1
|
||||
(direction OUTPUT))
|
||||
(port DOB0
|
||||
(direction OUTPUT)))))
|
||||
(cell pmi_ram_dpXbnonesadr41120484112048p1371d0a0
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port (array (rename WrAddress "WrAddress(10:0)") 11)
|
||||
(direction INPUT))
|
||||
(port (array (rename RdAddress "RdAddress(10:0)") 11)
|
||||
(direction INPUT))
|
||||
(port (array (rename Data "Data(3:0)") 4)
|
||||
(direction INPUT))
|
||||
(port WE
|
||||
(direction INPUT))
|
||||
(port RdClock
|
||||
(direction INPUT))
|
||||
(port RdClockEn
|
||||
(direction INPUT))
|
||||
(port Reset
|
||||
(direction INPUT))
|
||||
(port WrClock
|
||||
(direction INPUT))
|
||||
(port WrClockEn
|
||||
(direction INPUT))
|
||||
(port (array (rename Q "Q(3:0)") 4)
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance scuba_vhi_inst
|
||||
(viewRef view1
|
||||
(cellRef VHI)))
|
||||
(instance scuba_vlo_inst
|
||||
(viewRef view1
|
||||
(cellRef VLO)))
|
||||
(instance pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0
|
||||
(viewRef view1
|
||||
(cellRef DP8KC))
|
||||
(property INIT_DATA
|
||||
(string "STATIC"))
|
||||
(property ASYNC_RESET_RELEASE
|
||||
(string "ASYNC"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "pmi_ram_dpXbnonesadr41120484112048p1371d0a0__PMIP__2048__4__4__-1B"))
|
||||
(property MEM_INIT_FILE
|
||||
(string ""))
|
||||
(property CSDECODE_B
|
||||
(string "0b000"))
|
||||
(property CSDECODE_A
|
||||
(string "0b000"))
|
||||
(property WRITEMODE_B
|
||||
(string "NORMAL"))
|
||||
(property WRITEMODE_A
|
||||
(string "NORMAL"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property RESETMODE
|
||||
(string "ASYNC"))
|
||||
(property REGMODE_B
|
||||
(string "OUTREG"))
|
||||
(property REGMODE_A
|
||||
(string "OUTREG"))
|
||||
(property DATA_WIDTH_B
|
||||
(string "4"))
|
||||
(property DATA_WIDTH_A
|
||||
(string "4")))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))))
|
||||
(net scuba_vlo
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vlo_inst))
|
||||
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net dataout3
|
||||
(joined
|
||||
(portRef (member Q 0))
|
||||
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net dataout2
|
||||
(joined
|
||||
(portRef (member Q 1))
|
||||
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net dataout1
|
||||
(joined
|
||||
(portRef (member Q 2))
|
||||
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net dataout0
|
||||
(joined
|
||||
(portRef (member Q 3))
|
||||
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net WrClockEn
|
||||
(joined
|
||||
(portRef WrClockEn)
|
||||
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net clk
|
||||
(joined
|
||||
(portRef WrClock)
|
||||
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net Reset
|
||||
(joined
|
||||
(portRef Reset)
|
||||
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net RdClockEn
|
||||
(joined
|
||||
(portRef RdClockEn)
|
||||
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))
|
||||
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net rdclk
|
||||
(joined
|
||||
(portRef RdClock)
|
||||
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net wren
|
||||
(joined
|
||||
(portRef WE)
|
||||
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net datain3
|
||||
(joined
|
||||
(portRef (member Data 0))
|
||||
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net datain2
|
||||
(joined
|
||||
(portRef (member Data 1))
|
||||
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net datain1
|
||||
(joined
|
||||
(portRef (member Data 2))
|
||||
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net datain0
|
||||
(joined
|
||||
(portRef (member Data 3))
|
||||
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net raddr10
|
||||
(joined
|
||||
(portRef (member RdAddress 0))
|
||||
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net raddr9
|
||||
(joined
|
||||
(portRef (member RdAddress 1))
|
||||
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net raddr8
|
||||
(joined
|
||||
(portRef (member RdAddress 2))
|
||||
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net raddr7
|
||||
(joined
|
||||
(portRef (member RdAddress 3))
|
||||
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net raddr6
|
||||
(joined
|
||||
(portRef (member RdAddress 4))
|
||||
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net raddr5
|
||||
(joined
|
||||
(portRef (member RdAddress 5))
|
||||
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net raddr4
|
||||
(joined
|
||||
(portRef (member RdAddress 6))
|
||||
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net raddr3
|
||||
(joined
|
||||
(portRef (member RdAddress 7))
|
||||
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net raddr2
|
||||
(joined
|
||||
(portRef (member RdAddress 8))
|
||||
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net raddr1
|
||||
(joined
|
||||
(portRef (member RdAddress 9))
|
||||
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net raddr0
|
||||
(joined
|
||||
(portRef (member RdAddress 10))
|
||||
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net waddr10
|
||||
(joined
|
||||
(portRef (member WrAddress 0))
|
||||
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net waddr9
|
||||
(joined
|
||||
(portRef (member WrAddress 1))
|
||||
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net waddr8
|
||||
(joined
|
||||
(portRef (member WrAddress 2))
|
||||
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net waddr7
|
||||
(joined
|
||||
(portRef (member WrAddress 3))
|
||||
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net waddr6
|
||||
(joined
|
||||
(portRef (member WrAddress 4))
|
||||
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net waddr5
|
||||
(joined
|
||||
(portRef (member WrAddress 5))
|
||||
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net waddr4
|
||||
(joined
|
||||
(portRef (member WrAddress 6))
|
||||
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net waddr3
|
||||
(joined
|
||||
(portRef (member WrAddress 7))
|
||||
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net waddr2
|
||||
(joined
|
||||
(portRef (member WrAddress 8))
|
||||
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net waddr1
|
||||
(joined
|
||||
(portRef (member WrAddress 9))
|
||||
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))
|
||||
(net waddr0
|
||||
(joined
|
||||
(portRef (member WrAddress 10))
|
||||
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0))))))))
|
||||
(design pmi_ram_dpXbnonesadr41120484112048p1371d0a0
|
||||
(cellRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,553 @@
|
||||
(edif pmi_ram_dpXbnonesadr81120488112048p1371f311
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2026 1 19 16 35 48)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2"))))
|
||||
(comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 8 -num_rows 2048 -rdata_width 8 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr81120488112048p1371f311 -pmi ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
(numberDefinition))
|
||||
(cell VHI
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell VLO
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell DP8KC
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port DIA8
|
||||
(direction INPUT))
|
||||
(port DIA7
|
||||
(direction INPUT))
|
||||
(port DIA6
|
||||
(direction INPUT))
|
||||
(port DIA5
|
||||
(direction INPUT))
|
||||
(port DIA4
|
||||
(direction INPUT))
|
||||
(port DIA3
|
||||
(direction INPUT))
|
||||
(port DIA2
|
||||
(direction INPUT))
|
||||
(port DIA1
|
||||
(direction INPUT))
|
||||
(port DIA0
|
||||
(direction INPUT))
|
||||
(port ADA12
|
||||
(direction INPUT))
|
||||
(port ADA11
|
||||
(direction INPUT))
|
||||
(port ADA10
|
||||
(direction INPUT))
|
||||
(port ADA9
|
||||
(direction INPUT))
|
||||
(port ADA8
|
||||
(direction INPUT))
|
||||
(port ADA7
|
||||
(direction INPUT))
|
||||
(port ADA6
|
||||
(direction INPUT))
|
||||
(port ADA5
|
||||
(direction INPUT))
|
||||
(port ADA4
|
||||
(direction INPUT))
|
||||
(port ADA3
|
||||
(direction INPUT))
|
||||
(port ADA2
|
||||
(direction INPUT))
|
||||
(port ADA1
|
||||
(direction INPUT))
|
||||
(port ADA0
|
||||
(direction INPUT))
|
||||
(port CEA
|
||||
(direction INPUT))
|
||||
(port OCEA
|
||||
(direction INPUT))
|
||||
(port CLKA
|
||||
(direction INPUT))
|
||||
(port WEA
|
||||
(direction INPUT))
|
||||
(port CSA2
|
||||
(direction INPUT))
|
||||
(port CSA1
|
||||
(direction INPUT))
|
||||
(port CSA0
|
||||
(direction INPUT))
|
||||
(port RSTA
|
||||
(direction INPUT))
|
||||
(port DIB8
|
||||
(direction INPUT))
|
||||
(port DIB7
|
||||
(direction INPUT))
|
||||
(port DIB6
|
||||
(direction INPUT))
|
||||
(port DIB5
|
||||
(direction INPUT))
|
||||
(port DIB4
|
||||
(direction INPUT))
|
||||
(port DIB3
|
||||
(direction INPUT))
|
||||
(port DIB2
|
||||
(direction INPUT))
|
||||
(port DIB1
|
||||
(direction INPUT))
|
||||
(port DIB0
|
||||
(direction INPUT))
|
||||
(port ADB12
|
||||
(direction INPUT))
|
||||
(port ADB11
|
||||
(direction INPUT))
|
||||
(port ADB10
|
||||
(direction INPUT))
|
||||
(port ADB9
|
||||
(direction INPUT))
|
||||
(port ADB8
|
||||
(direction INPUT))
|
||||
(port ADB7
|
||||
(direction INPUT))
|
||||
(port ADB6
|
||||
(direction INPUT))
|
||||
(port ADB5
|
||||
(direction INPUT))
|
||||
(port ADB4
|
||||
(direction INPUT))
|
||||
(port ADB3
|
||||
(direction INPUT))
|
||||
(port ADB2
|
||||
(direction INPUT))
|
||||
(port ADB1
|
||||
(direction INPUT))
|
||||
(port ADB0
|
||||
(direction INPUT))
|
||||
(port CEB
|
||||
(direction INPUT))
|
||||
(port OCEB
|
||||
(direction INPUT))
|
||||
(port CLKB
|
||||
(direction INPUT))
|
||||
(port WEB
|
||||
(direction INPUT))
|
||||
(port CSB2
|
||||
(direction INPUT))
|
||||
(port CSB1
|
||||
(direction INPUT))
|
||||
(port CSB0
|
||||
(direction INPUT))
|
||||
(port RSTB
|
||||
(direction INPUT))
|
||||
(port DOA8
|
||||
(direction OUTPUT))
|
||||
(port DOA7
|
||||
(direction OUTPUT))
|
||||
(port DOA6
|
||||
(direction OUTPUT))
|
||||
(port DOA5
|
||||
(direction OUTPUT))
|
||||
(port DOA4
|
||||
(direction OUTPUT))
|
||||
(port DOA3
|
||||
(direction OUTPUT))
|
||||
(port DOA2
|
||||
(direction OUTPUT))
|
||||
(port DOA1
|
||||
(direction OUTPUT))
|
||||
(port DOA0
|
||||
(direction OUTPUT))
|
||||
(port DOB8
|
||||
(direction OUTPUT))
|
||||
(port DOB7
|
||||
(direction OUTPUT))
|
||||
(port DOB6
|
||||
(direction OUTPUT))
|
||||
(port DOB5
|
||||
(direction OUTPUT))
|
||||
(port DOB4
|
||||
(direction OUTPUT))
|
||||
(port DOB3
|
||||
(direction OUTPUT))
|
||||
(port DOB2
|
||||
(direction OUTPUT))
|
||||
(port DOB1
|
||||
(direction OUTPUT))
|
||||
(port DOB0
|
||||
(direction OUTPUT)))))
|
||||
(cell pmi_ram_dpXbnonesadr81120488112048p1371f311
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port (array (rename WrAddress "WrAddress(10:0)") 11)
|
||||
(direction INPUT))
|
||||
(port (array (rename RdAddress "RdAddress(10:0)") 11)
|
||||
(direction INPUT))
|
||||
(port (array (rename Data "Data(7:0)") 8)
|
||||
(direction INPUT))
|
||||
(port WE
|
||||
(direction INPUT))
|
||||
(port RdClock
|
||||
(direction INPUT))
|
||||
(port RdClockEn
|
||||
(direction INPUT))
|
||||
(port Reset
|
||||
(direction INPUT))
|
||||
(port WrClock
|
||||
(direction INPUT))
|
||||
(port WrClockEn
|
||||
(direction INPUT))
|
||||
(port (array (rename Q "Q(7:0)") 8)
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance scuba_vhi_inst
|
||||
(viewRef view1
|
||||
(cellRef VHI)))
|
||||
(instance pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1
|
||||
(viewRef view1
|
||||
(cellRef DP8KC))
|
||||
(property INIT_DATA
|
||||
(string "STATIC"))
|
||||
(property ASYNC_RESET_RELEASE
|
||||
(string "ASYNC"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "pmi_ram_dpXbnonesadr81120488112048p1371f311__PMIP__2048__8__8__-1B"))
|
||||
(property MEM_INIT_FILE
|
||||
(string ""))
|
||||
(property CSDECODE_B
|
||||
(string "0b000"))
|
||||
(property CSDECODE_A
|
||||
(string "0b000"))
|
||||
(property WRITEMODE_B
|
||||
(string "NORMAL"))
|
||||
(property WRITEMODE_A
|
||||
(string "NORMAL"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property RESETMODE
|
||||
(string "ASYNC"))
|
||||
(property REGMODE_B
|
||||
(string "OUTREG"))
|
||||
(property REGMODE_A
|
||||
(string "OUTREG"))
|
||||
(property DATA_WIDTH_B
|
||||
(string "4"))
|
||||
(property DATA_WIDTH_A
|
||||
(string "4")))
|
||||
(instance scuba_vlo_inst
|
||||
(viewRef view1
|
||||
(cellRef VLO)))
|
||||
(instance pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0
|
||||
(viewRef view1
|
||||
(cellRef DP8KC))
|
||||
(property INIT_DATA
|
||||
(string "STATIC"))
|
||||
(property ASYNC_RESET_RELEASE
|
||||
(string "ASYNC"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "pmi_ram_dpXbnonesadr81120488112048p1371f311__PMIP__2048__8__8__-1B"))
|
||||
(property MEM_INIT_FILE
|
||||
(string ""))
|
||||
(property CSDECODE_B
|
||||
(string "0b000"))
|
||||
(property CSDECODE_A
|
||||
(string "0b000"))
|
||||
(property WRITEMODE_B
|
||||
(string "NORMAL"))
|
||||
(property WRITEMODE_A
|
||||
(string "NORMAL"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property RESETMODE
|
||||
(string "ASYNC"))
|
||||
(property REGMODE_B
|
||||
(string "OUTREG"))
|
||||
(property REGMODE_A
|
||||
(string "OUTREG"))
|
||||
(property DATA_WIDTH_B
|
||||
(string "4"))
|
||||
(property DATA_WIDTH_A
|
||||
(string "4")))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))))
|
||||
(net scuba_vlo
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vlo_inst))
|
||||
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net dataout7
|
||||
(joined
|
||||
(portRef (member Q 0))
|
||||
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net dataout6
|
||||
(joined
|
||||
(portRef (member Q 1))
|
||||
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net dataout5
|
||||
(joined
|
||||
(portRef (member Q 2))
|
||||
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net dataout4
|
||||
(joined
|
||||
(portRef (member Q 3))
|
||||
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net dataout3
|
||||
(joined
|
||||
(portRef (member Q 4))
|
||||
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))))
|
||||
(net dataout2
|
||||
(joined
|
||||
(portRef (member Q 5))
|
||||
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))))
|
||||
(net dataout1
|
||||
(joined
|
||||
(portRef (member Q 6))
|
||||
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))))
|
||||
(net dataout0
|
||||
(joined
|
||||
(portRef (member Q 7))
|
||||
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))))
|
||||
(net WrClockEn
|
||||
(joined
|
||||
(portRef WrClockEn)
|
||||
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net clk
|
||||
(joined
|
||||
(portRef WrClock)
|
||||
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net Reset
|
||||
(joined
|
||||
(portRef Reset)
|
||||
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net RdClockEn
|
||||
(joined
|
||||
(portRef RdClockEn)
|
||||
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))
|
||||
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net rdclk
|
||||
(joined
|
||||
(portRef RdClock)
|
||||
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net wren
|
||||
(joined
|
||||
(portRef WE)
|
||||
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net datain7
|
||||
(joined
|
||||
(portRef (member Data 0))
|
||||
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net datain6
|
||||
(joined
|
||||
(portRef (member Data 1))
|
||||
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net datain5
|
||||
(joined
|
||||
(portRef (member Data 2))
|
||||
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net datain4
|
||||
(joined
|
||||
(portRef (member Data 3))
|
||||
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net datain3
|
||||
(joined
|
||||
(portRef (member Data 4))
|
||||
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))))
|
||||
(net datain2
|
||||
(joined
|
||||
(portRef (member Data 5))
|
||||
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))))
|
||||
(net datain1
|
||||
(joined
|
||||
(portRef (member Data 6))
|
||||
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))))
|
||||
(net datain0
|
||||
(joined
|
||||
(portRef (member Data 7))
|
||||
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))))
|
||||
(net raddr10
|
||||
(joined
|
||||
(portRef (member RdAddress 0))
|
||||
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net raddr9
|
||||
(joined
|
||||
(portRef (member RdAddress 1))
|
||||
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net raddr8
|
||||
(joined
|
||||
(portRef (member RdAddress 2))
|
||||
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net raddr7
|
||||
(joined
|
||||
(portRef (member RdAddress 3))
|
||||
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net raddr6
|
||||
(joined
|
||||
(portRef (member RdAddress 4))
|
||||
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net raddr5
|
||||
(joined
|
||||
(portRef (member RdAddress 5))
|
||||
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net raddr4
|
||||
(joined
|
||||
(portRef (member RdAddress 6))
|
||||
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net raddr3
|
||||
(joined
|
||||
(portRef (member RdAddress 7))
|
||||
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net raddr2
|
||||
(joined
|
||||
(portRef (member RdAddress 8))
|
||||
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net raddr1
|
||||
(joined
|
||||
(portRef (member RdAddress 9))
|
||||
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net raddr0
|
||||
(joined
|
||||
(portRef (member RdAddress 10))
|
||||
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net waddr10
|
||||
(joined
|
||||
(portRef (member WrAddress 0))
|
||||
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net waddr9
|
||||
(joined
|
||||
(portRef (member WrAddress 1))
|
||||
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net waddr8
|
||||
(joined
|
||||
(portRef (member WrAddress 2))
|
||||
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net waddr7
|
||||
(joined
|
||||
(portRef (member WrAddress 3))
|
||||
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net waddr6
|
||||
(joined
|
||||
(portRef (member WrAddress 4))
|
||||
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net waddr5
|
||||
(joined
|
||||
(portRef (member WrAddress 5))
|
||||
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net waddr4
|
||||
(joined
|
||||
(portRef (member WrAddress 6))
|
||||
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net waddr3
|
||||
(joined
|
||||
(portRef (member WrAddress 7))
|
||||
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net waddr2
|
||||
(joined
|
||||
(portRef (member WrAddress 8))
|
||||
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net waddr1
|
||||
(joined
|
||||
(portRef (member WrAddress 9))
|
||||
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))
|
||||
(net waddr0
|
||||
(joined
|
||||
(portRef (member WrAddress 10))
|
||||
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1))
|
||||
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0))))))))
|
||||
(design pmi_ram_dpXbnonesadr81120488112048p1371f311
|
||||
(cellRef pmi_ram_dpXbnonesadr81120488112048p1371f311
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
Reference in New Issue
Block a user