diff --git a/.gitignore b/.gitignore index e071b10..101c7c5 100644 --- a/.gitignore +++ b/.gitignore @@ -1,23 +1,67 @@ # ============================================================ # Lattice Diamond .gitignore -# +# # Strategy: # 1. Ignore all junk with broad glob patterns # 2. Negate ONLY the files Lattice Diamond needs to open a project # ============================================================ # ---------- Build output ---------- -impl1/ +impl1/* *_tcr.dir/ +# Negate: files inside impl1/ that Diamond needs +!*/impl1/*.hub + +# ---------- Synthesis (Synplify Pro / Synplify) ---------- +synlog/ +synwork/ +syntmp/ +*.srp +*.srm +*.srd +*.srs +*.srr +*.rt.csv +*.fdep +*.szr + +# ---------- Implementation (Place & Route) ---------- +*.ncd +*.par +*.ngd +*.pad +*.fse +*.twr +*.tw1 +*.t2b +*.p2t +*.p3t +*.mrp +*.mt +*.drc +*.prf +*.prs +*.plg +*.bgn +*.alt +*.gcr +*.fdepxmr +*.schmap + +# ---------- PMI (Physical Model Information) ---------- +pmi_*/ + # ---------- Auto-generated junk ---------- -# Lattice intermediate / absolute-path files *.lst *.naf -*.tcl *.log +*.tlg +*.tgl +*.CML +*.tcl -# QuestaSim / VCS simulation junk +# ---------- QuestaSim / VCS simulation junk ---------- *.ado *.adf *.cr.mti @@ -26,34 +70,65 @@ impl1/ *.tops *.dmp *.vcd +*.wlf vsim.wlf transcript hdlparser.log +*.qdb +*.qtl +*.qpg +*.ngo +*.vmake +*_info +work/ -# HTML reports +# ---------- HTML / XML reports ---------- *.html *.htm +*.xml +*.csv +*.txt -# Generated XML +# ---------- Generated / intermediate files ---------- promote.xml reportview.xml +*.asd +*.rptmap +*.rpt +*.tcr -# Reveal debug (re-generatable) +# ---------- Reveal debug workspace (re-generatable) ---------- debug.rvs +reveal_workspace/ +*.rvp + +# ---------- Bitstream / programming intermediates ---------- +*.srf +*.sdf +*.ibs +*.lpc +*.duruntime +*.xdm +*.edi + +# ---------- Backup / temp ---------- +*.bak # ---------- Per-project sub-directories ---------- # Diamond GUI configs *.ini *.cfg -# CPLD work directories (simulation artifacts) -work/ +# ---------- Lattice GUI state ---------- +*.sort +*.db # ---------- Negate: Lattice Diamond opens project ONLY with these ---------- # Verilog / SystemVerilog / VHDL source !*.v !*.sv +!*.vhd # Lattice project definition !*.lpf @@ -72,4 +147,14 @@ work/ # Simulation project files (.spf is needed by Diamond's sim engine) !*.spf -_math_real.vhd + +# Debug / trace +!*.hub +!*.rvl + +# ---------- Catch-alls (after negations — last matching rule wins) ---------- + +# IEEE stdlib VHDL (auto-generated by sim tool, not project source) +*_math_real* +*.log.bak.* +.build_status diff --git a/CPLD1/impl1/NewExtIns_CPLD1_impl1.areasrr b/CPLD1/impl1/NewExtIns_CPLD1_impl1.areasrr new file mode 100644 index 0000000..0b34766 --- /dev/null +++ b/CPLD1/impl1/NewExtIns_CPLD1_impl1.areasrr @@ -0,0 +1,81 @@ +---------------------------------------------------------------------- +Report for cell RelayConTop.verilog + +Register bits: 769 of 6864 (11%) +PIC Latch: 0 +I/O cells: 187 + Cell usage: + cell count Res Usage(%) + FD1P3AX 419 100.0 + FD1P3AY 4 100.0 + FD1P3IX 148 100.0 + FD1P3JX 1 100.0 + FD1S3AX 16 100.0 + FD1S3IX 14 100.0 + FD1S3JX 1 100.0 + GSR 1 100.0 + IB 5 100.0 + IFS1P3IX 3 100.0 + IFS1P3JX 1 100.0 + INV 2 100.0 + L6MUX21 72 100.0 + OB 181 100.0 + OBZ 1 100.0 + OFS1P3DX 36 100.0 + OFS1P3IX 126 100.0 + ORCALUT4 747 100.0 + PFUMX 104 100.0 + PUR 1 100.0 + VHI 4 100.0 + VLO 4 100.0 +SUB MODULES + BUS_Con 1 100.0 + CPLD_Con 1 100.0 + Reg_file 1 100.0 + + TOTAL 1894 +---------------------------------------------------------------------- +Report for cell CPLD_Con.netlist + Instance path: CPLD_Con_1 + Cell usage: + cell count Res Usage(%) + FD1P3IX 18 12.2 + FD1P3JX 1 100.0 + FD1S3AX 12 75.0 + FD1S3IX 5 35.7 + INV 1 50.0 + ORCALUT4 441 59.0 + PFUMX 8 7.7 + VHI 1 25.0 + VLO 1 25.0 + + TOTAL 488 +---------------------------------------------------------------------- +Report for cell Reg_file.netlist + Instance path: CPLD_Reg_1 + Cell usage: + cell count Res Usage(%) + FD1P3AX 419 100.0 + FD1P3AY 4 100.0 + FD1S3AX 2 12.5 + L6MUX21 72 100.0 + ORCALUT4 239 32.0 + PFUMX 96 92.3 + VHI 1 25.0 + VLO 1 25.0 + + TOTAL 834 +---------------------------------------------------------------------- +Report for cell BUS_Con.netlist + Instance path: BUS_Con_1 + Cell usage: + cell count Res Usage(%) + FD1P3IX 130 87.8 + FD1S3AX 2 12.5 + FD1S3IX 9 64.3 + FD1S3JX 1 100.0 + ORCALUT4 67 9.0 + VHI 1 25.0 + VLO 1 25.0 + + TOTAL 211 diff --git a/CPLD1/impl1/NewExtIns_CPLD1_impl1.bit b/CPLD1/impl1/NewExtIns_CPLD1_impl1.bit new file mode 100644 index 0000000..c11e7ee Binary files /dev/null and b/CPLD1/impl1/NewExtIns_CPLD1_impl1.bit differ diff --git a/CPLD1/impl1/NewExtIns_CPLD1_impl1.hub b/CPLD1/impl1/NewExtIns_CPLD1_impl1.hub new file mode 100644 index 0000000..d8aa80f --- /dev/null +++ b/CPLD1/impl1/NewExtIns_CPLD1_impl1.hub @@ -0,0 +1 @@ +HUBID_00 REVEAL_0 diff --git a/CPLD1/impl1/NewExtIns_CPLD1_impl1.jed b/CPLD1/impl1/NewExtIns_CPLD1_impl1.jed new file mode 100644 index 0000000..499543e --- /dev/null +++ b/CPLD1/impl1/NewExtIns_CPLD1_impl1.jed @@ -0,0 +1,11472 @@ +* +NOTE Diamond (64-bit) 3.14.0.75.2 JEDEC Compatible Fuse File.* +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.* +NOTE All Rights Reserved.* +NOTE DATE CREATED: Tue May 26 15:48:04 2026* +NOTE DESIGN NAME: NewExtIns_CPLD1_impl1.ncd* +NOTE DEVICE NAME: LCMXO2-7000HC-4FPBGA484* +NOTE JEDEC FILE STATUS: Final Version 1.95* +NOTE PIN ASSIGNMENTS* +NOTE PINS o_miso : AA14 : out* +NOTE PINS o_wready : Y6 : out* +NOTE PINS i_sys_clk : B9 : in* +NOTE PINS o_PMU_OC_4[31] : AB17 : out* +NOTE PINS o_PMU_OC_4[30] : W14 : out* +NOTE PINS o_PMU_OC_4[29] : P21 : out* +NOTE PINS o_PMU_OC_4[28] : AA19 : out* +NOTE PINS o_PMU_OC_4[27] : AB15 : out* +NOTE PINS o_PMU_OC_4[26] : AB18 : out* +NOTE PINS o_PMU_OC_4[25] : AA15 : out* +NOTE PINS o_PMU_OC_4[24] : Y16 : out* +NOTE PINS o_PMU_OC_4[23] : C21 : out* +NOTE PINS o_PMU_OC_4[22] : B22 : out* +NOTE PINS o_PMU_OC_4[21] : A21 : out* +NOTE PINS o_PMU_OC_4[20] : E12 : out* +NOTE PINS o_PMU_OC_4[19] : C16 : out* +NOTE PINS o_PMU_OC_4[18] : B16 : out* +NOTE PINS o_PMU_OC_4[17] : A16 : out* +NOTE PINS o_PMU_OC_4[16] : C15 : out* +NOTE PINS o_PMU_OC_4[15] : W16 : out* +NOTE PINS o_PMU_OC_4[14] : Y18 : out* +NOTE PINS o_PMU_OC_4[13] : N16 : out* +NOTE PINS o_PMU_OC_4[12] : N18 : out* +NOTE PINS o_PMU_OC_4[11] : T13 : out* +NOTE PINS o_PMU_OC_4[10] : W15 : out* +NOTE PINS o_PMU_OC_4[9] : Y17 : out* +NOTE PINS o_PMU_OC_4[8] : AA16 : out* +NOTE PINS o_PMU_OC_4[7] : E15 : out* +NOTE PINS o_PMU_OC_4[6] : E14 : out* +NOTE PINS o_PMU_OC_4[5] : D12 : out* +NOTE PINS o_PMU_OC_4[4] : B19 : out* +NOTE PINS o_PMU_OC_4[3] : B15 : out* +NOTE PINS o_PMU_OC_4[2] : B14 : out* +NOTE PINS o_PMU_OC_4[1] : B13 : out* +NOTE PINS o_PMU_OC_4[0] : A13 : out* +NOTE PINS o_PMU_OC_3[31] : C11 : out* +NOTE PINS o_PMU_OC_3[30] : U8 : out* +NOTE PINS o_PMU_OC_3[29] : A7 : out* +NOTE PINS o_PMU_OC_3[28] : N3 : out* +NOTE PINS o_PMU_OC_3[27] : K1 : out* +NOTE PINS o_PMU_OC_3[26] : M1 : out* +NOTE PINS o_PMU_OC_3[25] : N6 : out* +NOTE PINS o_PMU_OC_3[24] : AB7 : out* +NOTE PINS o_PMU_OC_3[23] : N7 : out* +NOTE PINS o_PMU_OC_3[22] : B8 : out* +NOTE PINS o_PMU_OC_3[21] : D8 : out* +NOTE PINS o_PMU_OC_3[20] : E7 : out* +NOTE PINS o_PMU_OC_3[19] : D11 : out* +NOTE PINS o_PMU_OC_3[18] : E10 : out* +NOTE PINS o_PMU_OC_3[17] : E9 : out* +NOTE PINS o_PMU_OC_3[16] : E8 : out* +NOTE PINS o_PMU_OC_3[15] : M2 : out* +NOTE PINS o_PMU_OC_3[14] : R3 : out* +NOTE PINS o_PMU_OC_3[13] : G11 : out* +NOTE PINS o_PMU_OC_3[12] : M7 : out* +NOTE PINS o_PMU_OC_3[11] : E11 : out* +NOTE PINS o_PMU_OC_3[10] : P2 : out* +NOTE PINS o_PMU_OC_3[9] : C10 : out* +NOTE PINS o_PMU_OC_3[8] : V7 : out* +NOTE PINS o_PMU_OC_3[7] : B20 : out* +NOTE PINS o_PMU_OC_3[6] : C20 : out* +NOTE PINS o_PMU_OC_3[5] : E19 : out* +NOTE PINS o_PMU_OC_3[4] : F19 : out* +NOTE PINS o_PMU_OC_3[3] : N1 : out* +NOTE PINS o_PMU_OC_3[2] : N2 : out* +NOTE PINS o_PMU_OC_3[1] : R1 : out* +NOTE PINS o_PMU_OC_3[0] : M3 : out* +NOTE PINS o_PMU_OC_2[31] : U15 : out* +NOTE PINS o_PMU_OC_2[30] : V15 : out* +NOTE PINS o_PMU_OC_2[29] : Y13 : out* +NOTE PINS o_PMU_OC_2[28] : Y15 : out* +NOTE PINS o_PMU_OC_2[27] : M17 : out* +NOTE PINS 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a/CPLD1/impl1/NewExtIns_CPLD1_impl1.pt b/CPLD1/impl1/NewExtIns_CPLD1_impl1.pt new file mode 100644 index 0000000..e5e32de --- /dev/null +++ b/CPLD1/impl1/NewExtIns_CPLD1_impl1.pt @@ -0,0 +1,10 @@ +-v +10 + + + + +-gt +-sethld +-sp 4 +-sphld m diff --git a/CPLD1/impl1/NewExtIns_CPLD1_impl1_map.cam b/CPLD1/impl1/NewExtIns_CPLD1_impl1_map.cam new file mode 100644 index 0000000..787ded8 --- /dev/null +++ b/CPLD1/impl1/NewExtIns_CPLD1_impl1_map.cam @@ -0,0 +1,135 @@ +[ START MERGED ] +i_rst_n_c_i i_rst_n_c +CPLD_Con_1/g0_26_x1 DC_Con3[21] +[ END MERGED ] +[ START CLIPPED ] +GND +VCC +[ END CLIPPED ] +[ START DESIGN PREFS ] +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.14.0.75.2 -- WARNING: Map write only section -- Tue May 26 15:47:46 2026 + +SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; +LOCATE COMP "o_miso" SITE "AA14" ; +LOCATE COMP "i_sys_clk" SITE "B9" ; +LOCATE COMP "o_PMU_OC_4[23]" SITE "C21" ; +LOCATE COMP "o_PMU_OC_4[22]" SITE "B22" ; +LOCATE COMP "o_PMU_OC_4[21]" SITE "A21" ; +LOCATE COMP "o_PMU_OC_4[20]" SITE "E12" ; +LOCATE COMP "o_PMU_OC_4[19]" SITE "C16" ; +LOCATE COMP "o_PMU_OC_4[18]" SITE "B16" ; +LOCATE COMP "o_PMU_OC_4[17]" SITE "A16" ; +LOCATE COMP "o_PMU_OC_4[16]" SITE "C15" ; +LOCATE COMP "o_PMU_OC_4[7]" SITE "E15" ; +LOCATE COMP "o_PMU_OC_4[6]" SITE "E14" ; +LOCATE COMP "o_PMU_OC_4[5]" SITE "D12" ; +LOCATE COMP "o_PMU_OC_4[4]" SITE "B19" ; +LOCATE COMP "o_PMU_OC_4[3]" SITE "B15" ; +LOCATE COMP "o_PMU_OC_4[2]" SITE "B14" ; +LOCATE COMP "o_PMU_OC_4[1]" SITE "B13" ; +LOCATE COMP "o_PMU_OC_4[0]" SITE "A13" ; +LOCATE COMP "o_PMU_OC_3[22]" SITE "B8" ; +LOCATE COMP "o_PMU_OC_3[21]" SITE "D8" ; +LOCATE COMP "o_PMU_OC_3[20]" SITE "E7" ; +LOCATE COMP "o_PMU_OC_3[19]" SITE "D11" ; +LOCATE COMP "o_PMU_OC_3[18]" SITE "E10" ; +LOCATE COMP "o_PMU_OC_3[17]" SITE "E9" ; +LOCATE COMP "o_PMU_OC_3[16]" SITE "E8" ; +LOCATE COMP "o_PMU_OC_3[7]" SITE "B20" ; +LOCATE COMP "o_PMU_OC_3[6]" SITE "C20" ; +LOCATE COMP "o_PMU_OC_3[5]" SITE "E19" ; +LOCATE COMP "o_PMU_OC_3[4]" SITE "F19" ; +LOCATE COMP "o_PMU_OC_3[3]" SITE "N1" ; +LOCATE COMP "o_PMU_OC_3[2]" SITE "N2" ; +LOCATE COMP "o_PMU_OC_3[1]" SITE "R1" ; +LOCATE COMP "o_PMU_OC_3[0]" SITE "M3" ; +LOCATE COMP "o_PMU_OC_2[23]" SITE "G12" ; +LOCATE COMP "o_PMU_OC_2[22]" SITE "F13" ; +LOCATE COMP "o_PMU_OC_2[21]" SITE "F15" ; +LOCATE COMP "o_PMU_OC_2[20]" SITE "G13" ; +LOCATE COMP "o_PMU_OC_2[19]" SITE "D18" ; +LOCATE COMP "o_PMU_OC_2[18]" SITE "C18" ; +LOCATE COMP "o_PMU_OC_2[17]" SITE "A18" ; +LOCATE COMP "o_PMU_OC_2[16]" SITE "A17" ; +LOCATE COMP "o_PMU_OC_2[7]" SITE "D22" ; +LOCATE COMP "o_PMU_OC_2[6]" SITE "D21" ; +LOCATE COMP "o_PMU_OC_2[5]" SITE "D20" ; +LOCATE COMP "o_PMU_OC_2[4]" SITE "C22" ; +LOCATE COMP "o_PMU_OC_2[3]" SITE "G15" ; +LOCATE COMP "o_PMU_OC_2[2]" SITE "D16" ; +LOCATE COMP "o_PMU_OC_2[1]" SITE "F16" ; +LOCATE COMP "o_PMU_OC_2[0]" SITE "E16" ; +LOCATE COMP "o_PMU_OC_1[23]" SITE "T5" ; +LOCATE COMP "o_PMU_OC_1[22]" SITE "U4" ; +LOCATE COMP "o_PMU_OC_1[21]" SITE "R6" ; +LOCATE COMP "o_PMU_OC_1[20]" SITE "V4" ; +LOCATE COMP "o_PMU_OC_1[19]" SITE "Y7" ; +LOCATE COMP "o_PMU_OC_1[18]" SITE "AB6" ; +LOCATE COMP "o_PMU_OC_1[17]" SITE "AA7" ; +LOCATE COMP "o_PMU_OC_1[16]" SITE "W6" ; +LOCATE COMP "o_PMU_OC_1[7]" SITE "J17" ; +LOCATE COMP "o_PMU_OC_1[6]" SITE "H16" ; +LOCATE COMP "o_PMU_OC_1[5]" SITE "J19" ; +LOCATE COMP "o_PMU_OC_1[4]" SITE "G19" ; +LOCATE COMP "o_PMU_OC_1[3]" SITE "P20" ; +LOCATE COMP "o_PMU_OC_1[2]" SITE "N20" ; +LOCATE COMP "o_PMU_OC_1[1]" SITE "R16" ; +LOCATE COMP "o_PMU_OC_1[0]" SITE "M19" ; +LOCATE COMP "o_RC_LOS[1]" SITE "L6" ; +LOCATE COMP "o_RC_LOS[0]" SITE "G4" ; +LOCATE COMP "o_RC_LOF[1]" SITE "H4" ; +LOCATE COMP "o_RC_LOF[0]" SITE "F3" ; +LOCATE COMP "o_RC_ISel" SITE "P6" ; +LOCATE COMP "o_RC_VSel" SITE "L7" ; +LOCATE COMP "o_RC_RLSel[17]" SITE "N5" ; +LOCATE COMP "o_RC_RLSel[16]" SITE "D9" ; +LOCATE COMP "o_RC_RLSel[15]" SITE "F11" ; +LOCATE COMP "o_RC_RLSel[14]" SITE "B4" ; +LOCATE COMP "o_RC_RLSel[13]" SITE "A5" ; +LOCATE COMP "o_RC_RLSel[12]" SITE "B11" ; +LOCATE COMP "o_RC_RLSel[11]" SITE "A3" ; +LOCATE COMP "o_RC_RLSel[10]" SITE "C5" ; +LOCATE COMP "o_RC_RLSel[9]" SITE "F8" ; +LOCATE COMP "o_RC_RLSel[8]" SITE "B7" ; +LOCATE COMP "o_RC_RLSel[7]" SITE "C8" ; +LOCATE COMP "o_RC_RLSel[6]" SITE "F6" ; +LOCATE COMP "o_RC_RLSel[5]" SITE "G10" ; +LOCATE COMP "o_RC_RLSel[4]" SITE "F5" ; +LOCATE COMP "o_RC_RLSel[3]" SITE "P3" ; +LOCATE COMP "o_RC_RLSel[2]" SITE "B10" ; +LOCATE COMP "o_RC_RLSel[1]" SITE "M4" ; +LOCATE COMP "o_RC_RLSel[0]" SITE "M6" ; +LOCATE COMP "o_RC_T32" SITE "V11" ; +LOCATE COMP "o_RC_T31" SITE "U11" ; +LOCATE COMP "o_RC_T30" SITE "T11" ; +LOCATE COMP "o_RC_T29" SITE "T12" ; +LOCATE COMP "o_RC_T28" SITE "U12" ; +LOCATE COMP "o_RC_T27" SITE "U13" ; +LOCATE COMP "o_IO_RC1" SITE "F10" ; +LOCATE COMP "o_DMM_EN[18]" SITE "T10" ; +LOCATE COMP "o_DMM_EN[17]" SITE "U10" ; +LOCATE COMP "o_DMM_EN[16]" SITE "W11" ; +LOCATE COMP "o_DMM_EN[15]" SITE "V13" ; +LOCATE COMP "o_DMM_EN[14]" SITE "Y12" ; +LOCATE COMP "o_DMM_EN[13]" SITE "V12" ; +LOCATE COMP "o_DMM_EN[12]" SITE "W12" ; +LOCATE COMP "o_DMM_EN[11]" SITE "F12" ; +LOCATE COMP "o_DMM_EN[10]" SITE "C13" ; +LOCATE COMP "o_DMM_EN[9]" SITE "D14" ; +LOCATE COMP "o_DMM_EN[8]" SITE "D15" ; +LOCATE COMP "o_DMM_EN[7]" SITE "AB13" ; +LOCATE COMP "o_DMM_EN[6]" SITE "AA12" ; +LOCATE COMP "o_DMM_EN[5]" SITE "AA11" ; +LOCATE COMP "o_DMM_EN[4]" SITE "AB10" ; +LOCATE COMP "o_DMM_EN[3]" SITE "C17" ; +LOCATE COMP "o_DMM_EN[2]" SITE "D17" ; +LOCATE COMP "o_DMM_EN[1]" SITE "E17" ; +LOCATE COMP "o_DMM_EN[0]" SITE "F17" ; +LOCATE COMP "o_err" SITE "AB16" ; +LOCATE COMP "i_cs" SITE "AB11" ; +LOCATE COMP "i_mosi" SITE "AB12" ; +LOCATE COMP "i_sclk" SITE "AA10" ; +LOCATE COMP "i_rst_n" SITE "Y14" ; +SCHEMATIC END ; +[ END DESIGN PREFS ] diff --git a/CPLD1/impl1/NewExtIns_CPLD1_impl1_map.hrr b/CPLD1/impl1/NewExtIns_CPLD1_impl1_map.hrr new file mode 100644 index 0000000..11f60c8 --- /dev/null +++ b/CPLD1/impl1/NewExtIns_CPLD1_impl1_map.hrr @@ -0,0 +1,40 @@ +--------------------------------------------------- +Report for cell RelayConTop + Instance path: RelayConTop + Cell usage: + cell count Res Usage(%) + SLIC 401.00 100.0 + IOLGC 165.00 100.0 + LUT4 747.00 100.0 + IOREG 165 100.0 + IOBUF 187 100.0 + PFUREG 604 100.0 +SUB MODULES + cell count SLC Usage(%) + Reg_file 1 53.8 + CPLD_Con 1 31.0 + BUS_Con 1 15.1 +--------------------------------------------------- +Report for cell CPLD_Con + Instance path: RelayConTop/CPLD_Con_1 + Cell usage: + cell count Res Usage(%) + SLIC 124.30 31.0 + LUT4 441.00 59.0 + PFUREG 36 6.0 +--------------------------------------------------- +Report for cell Reg_file + Instance path: RelayConTop/CPLD_Reg_1 + Cell usage: + cell count Res Usage(%) + SLIC 215.78 53.8 + LUT4 239.00 32.0 + PFUREG 425 70.4 +--------------------------------------------------- +Report for cell BUS_Con + Instance path: RelayConTop/BUS_Con_1 + Cell usage: + cell count Res Usage(%) + SLIC 60.58 15.1 + LUT4 67.00 9.0 + PFUREG 142 23.5 diff --git a/CPLD1/impl1/NewExtIns_CPLD1_impl1_mapvo.vo b/CPLD1/impl1/NewExtIns_CPLD1_impl1_mapvo.vo new file mode 100644 index 0000000..29dc06b --- /dev/null +++ b/CPLD1/impl1/NewExtIns_CPLD1_impl1_mapvo.vo @@ -0,0 +1,24095 @@ + +// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.14.0.75.2 + +// ldbanno -n Verilog -o NewExtIns_CPLD1_impl1_mapvo.vo -w -neg -gui -msgset /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/promote.xml NewExtIns_CPLD1_impl1_map.ncd +// Netlist created on Tue May 26 15:47:46 2026 +// Netlist written on Tue May 26 15:47:47 2026 +// Design is for device LCMXO2-7000HC +// Design is for package FPBGA484 +// Design is for performance grade 4 + +`timescale 1 ns / 1 ps + +module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, + i_rready, i_wvalid, o_wready, o_err, o_con_done, o_DMM_EN, + o_IO_RC1, o_RC_T27, o_RC_T28, o_RC_T29, o_RC_T30, + o_RC_T31, o_RC_T32, o_RC_RLSel, o_RC_VSel, o_RC_ISel, + o_RC_LOF, o_RC_LOS, o_PMU_OC_1, o_PMU_OC_2, o_PMU_OC_3, + o_PMU_OC_4 ); + input i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, i_rready, i_wvalid; + output o_miso, o_wready, o_err, o_con_done; + output [18:0] o_DMM_EN; + output o_IO_RC1, o_RC_T27, o_RC_T28, o_RC_T29, o_RC_T30, o_RC_T31, o_RC_T32; + output [17:0] o_RC_RLSel; + output o_RC_VSel, o_RC_ISel; + output [1:0] o_RC_LOF; + output [1:0] o_RC_LOS; + output [31:0] o_PMU_OC_1; + output [31:0] o_PMU_OC_2; + output [31:0] o_PMU_OC_3; + output [31:0] o_PMU_OC_4; + wire i_rst_n_c, \CPLD_Con_1/RC_Tx_1_sqmuxa , \BUS_Con_1.cs_sync[0] , + i_rst_n_c_i_set, i_sys_clk_c, \BUS_Con_1.cs_sync_rep0[1] , + \CPLD_Con_1.err_flag_1_sqmuxa , \BUS_Con_1/N_244 , + \BUS_Con_1/cs_sync[1] , \BUS_Con_1/bit_cnt[1] , + \BUS_Con_1/bit_cnt[0] , \BUS_Con_1.sclk_sync[0] , + \BUS_Con_1/sclk_sync[1] , \BUS_Con_1/bit_cnt_6[1] , + \BUS_Con_1/bit_cnt_6[0] , + \BUS_Con_1/bit_cnt_0_sqmuxa_1_i_a2_RNISVNVG , + \BUS_Con_1/un1_bit_cnt_9_c2 , \BUS_Con_1/bit_cnt[3] , + \BUS_Con_1/bit_cnt[2] , \BUS_Con_1/bit_cnt_6[3] , + \BUS_Con_1/bit_cnt_6[2] , \BUS_Con_1/un1_bit_cnt_9_c4 , + \BUS_Con_1/bit_cnt[5] , \BUS_Con_1/bit_cnt[4] , + \BUS_Con_1/bit_cnt_6[5] , \BUS_Con_1/bit_cnt_6[4] , + \BUS_Con_1/data_readyc_2_0 , \BUS_Con_1/data_readyc_3 , + \BUS_Con_1/data_readyc , \BUS_Con_1/data_ready , + \BUS_Con_1/tx_buffer[1] , \BUS_Con_1/miso_shift[0] , + \BUS_Con_1/tx_buffer[0] , \BUS_Con_1/miso_shift_6[1] , + \BUS_Con_1/miso_shift_6[0] , \BUS_Con_1/miso_shift_1_sqmuxa_i_0 , + \BUS_Con_1/miso_shift[1] , \BUS_Con_1/tx_buffer[3] , + \BUS_Con_1/miso_shift[2] , \BUS_Con_1/tx_buffer[2] , + \BUS_Con_1/miso_shift_6[3] , \BUS_Con_1/miso_shift_6[2] , + \BUS_Con_1/miso_shift[3] , \BUS_Con_1/tx_buffer[5] , + \BUS_Con_1/miso_shift[4] , \BUS_Con_1/tx_buffer[4] , + \BUS_Con_1/miso_shift_6[5] , \BUS_Con_1/miso_shift_6[4] , + \BUS_Con_1/miso_shift[5] , \BUS_Con_1/tx_buffer[7] , + \BUS_Con_1/miso_shift[6] , \BUS_Con_1/tx_buffer[6] , + \BUS_Con_1/miso_shift_6[7] , \BUS_Con_1/miso_shift_6[6] , + \BUS_Con_1/miso_shift[7] , \BUS_Con_1/tx_buffer[9] , + \BUS_Con_1/miso_shift[8] , \BUS_Con_1/tx_buffer[8] , + \BUS_Con_1/miso_shift_6[9] , \BUS_Con_1/miso_shift_6[8] , + \BUS_Con_1/miso_shift[9] , \BUS_Con_1/tx_buffer[11] , + \BUS_Con_1/miso_shift[10] , \BUS_Con_1/tx_buffer[10] , + \BUS_Con_1/miso_shift_6[11] , \BUS_Con_1/miso_shift_6[10] , + \BUS_Con_1/miso_shift[11] , \BUS_Con_1/tx_buffer[13] , + \BUS_Con_1/miso_shift[12] , \BUS_Con_1/tx_buffer[12] , + \BUS_Con_1/miso_shift_6[13] , \BUS_Con_1/miso_shift_6[12] , + \BUS_Con_1/miso_shift[13] , \BUS_Con_1/tx_buffer[15] , + \BUS_Con_1/miso_shift[14] , \BUS_Con_1/tx_buffer[14] , + \BUS_Con_1/miso_shift_6[15] , \BUS_Con_1/miso_shift_6[14] , + \BUS_Con_1/miso_shift[15] , \BUS_Con_1/tx_buffer[17] , + \BUS_Con_1/miso_shift[16] , \BUS_Con_1/tx_buffer[16] , + \BUS_Con_1/miso_shift_6[17] , \BUS_Con_1/miso_shift_6[16] , + \BUS_Con_1/miso_shift[17] , \BUS_Con_1/tx_buffer[19] , + \BUS_Con_1/miso_shift[18] , \BUS_Con_1/tx_buffer[18] , + \BUS_Con_1/miso_shift_6[19] , \BUS_Con_1/miso_shift_6[18] , + \BUS_Con_1/miso_shift[19] , \BUS_Con_1/tx_buffer[21] , + \BUS_Con_1/miso_shift[20] , \BUS_Con_1/tx_buffer[20] , + \BUS_Con_1/miso_shift_6[21] , \BUS_Con_1/miso_shift_6[20] , + \BUS_Con_1/miso_shift[21] , \BUS_Con_1/tx_buffer[23] , + \BUS_Con_1/miso_shift[22] , \BUS_Con_1/tx_buffer[22] , + \BUS_Con_1/miso_shift_6[23] , \BUS_Con_1/miso_shift_6[22] , + \BUS_Con_1/miso_shift[23] , \BUS_Con_1/miso_shift[24] , + \BUS_Con_1/miso_shift_6[25] , \BUS_Con_1/miso_shift_6[24] , + \BUS_Con_1/miso_shift[25] , \BUS_Con_1/miso_shift[26] , + \BUS_Con_1/miso_shift_6[27] , \BUS_Con_1/miso_shift_6[26] , + \BUS_Con_1/miso_shift[27] , \BUS_Con_1/miso_shift[28] , + \BUS_Con_1/miso_shift_6[29] , \BUS_Con_1/miso_shift_6[28] , + \BUS_Con_1/miso_shift[29] , \BUS_Con_1/miso_shift_6[30] , + \BUS_Con_1/miso_shift[30] , \BUS_Con_1/N_249 , \BUS_Con_1/state[1] , + \BUS_Con_1/state[0] , reg_busy, \BUS_Con_1/m3_i_o2 , + \BUS_Con_1/state_nss[1] , \BUS_Con_1/state_nss[0] , \DC_Con4[0] , + \DC_Con3[0] , \DC_Con2[0] , \DC_Con1[0] , \CPLD_Con_1/dc_t_2 , + \BUS_Con_1.mosi_sync[0] , \CPLD_Con_1/dc_t , \CPLD_Con_1/CO0 , + \BUS_Con_1/mosi_sync[1] , \CPLD_Con_1/N_6_0 , \CPLD_Con_1/N_18_c1 , + \CPLD_Con_1/N_18_0_c1 , \CPLD_Con_1/N_20 , \CPLD_Con_1/N_19 , + \CPLD_Con_1/en_t[1] , \CPLD_Con_1/en_t[2] , \freq1_relay[0] , + \CPLD_Con_1/m2 , \CPLD_Con_1/SUM0 , \CPLD_Con_1/N_21 , + \CPLD_Con_1/en_t[3] , \freq4_relay[0] , \freq3_relay[0] , + \freq2_relay[0] , \CPLD_Con_1/freq_t_2 , \CPLD_Con_1/freq_t , + \CPLD_Con_1.io_RC_2 , \w_data[8] , \CPLD_Reg_1/regtable[9]_1_sqmuxa , + \CPLD_Reg_1.regtable[9]_fast[8] , \reg_addr[6] , \reg_addr[5] , + \reg_addr[4] , \CPLD_Reg_1/N_1167 , con_exec, cmd_valid, + \CPLD_Reg_1/state[0] , \CPLD_Reg_1/err_flag8 , \CPLD_Reg_1/N_812 , + \CPLD_Reg_1/un10_0 , \CPLD_Reg_1/reg_err_flag , o_con_done_c, + \CPLD_Reg_1/state[1] , \w_data[23] , \CPLD_Reg_1/regtable[1][23] , + \CPLD_Reg_1/N_1057_i , \CPLD_Reg_1/un12_i , \CPLD_Reg_1/N_22 , + \w_data[15] , \w_data[16] , \CPLD_Reg_1/regtable[9][16] , + \CPLD_Reg_1/regtable[9][15] , \CPLD_Reg_1/N_25 , \CPLD_Reg_1/N_21 , + \CPLD_Reg_1/state_ns[1] , \CPLD_Reg_1/state_ns[0] , \w_data[20] , + \w_data[21] , \DC_Con4[21] , \DC_Con4[20] , \w_data[22] , + \DC_Con4[23] , \DC_Con4[22] , \BUS_Con_1/err_flag_1_sqmuxa_0_a2_0_0 , + \BUS_Con_1/N_241 , \BUS_Con_1/N_243_i , \BUS_Con_1/N_238_i , + bus_err_flag, \BUS_Con_1/N_34_i_0 , \w_data[0] , + \CPLD_Reg_1/regtable[1]_RNO[0] , \CPLD_Reg_1/un11_0 , con_rvalid, + \CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNILT4CU4 , \CPLD_Con_1/g0_2 , + \CPLD_Con_1/err_flag_0_sqmuxa_0_0 , \CPLD_Con_1/err_flag25 , + \CPLD_Con_1/un1_err_flag_0_sqmuxa , \CPLD_Con_1/g0_8_1_0 , + \CPLD_Con_1/RC_Tx_0_sqmuxa , \CPLD_Con_1/un1_RC_Tx_0_sqmuxa_1 , + \CPLD_Con_1/err_flag_RNO , cpld_err_flag, \o_PMU_OC_2_c[3] , + \CPLD_Con_1/un1_exec_flag_3_0_0_RNISFCLD4 , \CPLD_Con_1/N_103 , + \CPLD_Con_1.un1_exec_flag_3_i , \o_PMU_OC_2_c[1] , + \CPLD_Con_1/PMU_OC_2_8[1] , \CPLD_Con_1/PMU_OC_2d_0[3] , + \CPLD_Con_1/PMU_OC_2d_0[1] , \o_PMU_OC_2_c[7] , \CPLD_Con_1/N_64 , + \o_PMU_OC_2_c[5] , \CPLD_Con_1/N_63 , \CPLD_Con_1/PMU_OC_2d_0[7] , + \CPLD_Con_1/PMU_OC_2d_0[5] , \o_PMU_OC_3_c[3] , + \CPLD_Con_1/un1_exec_flag_2_0_0_RNI3RHOG1 , \CPLD_Con_1/N_144 , + \CPLD_Con_1.un1_exec_flag_2_i , \o_PMU_OC_3_c[1] , + \CPLD_Con_1/PMU_OC_3_8[1] , \CPLD_Con_1/PMU_OC_3d_0[3] , + \CPLD_Con_1/PMU_OC_3d_0[1] , \o_PMU_OC_3_c[7] , \CPLD_Con_1/N_148 , + \o_PMU_OC_3_c[5] , \CPLD_Con_1/N_147 , \CPLD_Con_1/PMU_OC_3d_0[7] , + \CPLD_Con_1/PMU_OC_3d_0[5] , \o_PMU_OC_4_c[4] , + \CPLD_Con_1/PMU_OC_4_8_0_a2_RNIL1I393[20] , N_195, + \CPLD_Con_1.un1_exec_flag_8_i , \o_PMU_OC_4_c[1] , \CPLD_Con_1/N_198 , + \CPLD_Con_1/PMU_OC_4d_0[4] , \CPLD_Con_1/PMU_OC_4d_0[1] , + \o_PMU_OC_4_c[20] , N_193, \o_PMU_OC_4_c[5] , N_194, + \CPLD_Con_1/PMU_OC_4d_0[20] , \CPLD_Con_1/PMU_OC_4d_0[5] , + \DC_Con3[22] , \CPLD_Con_1/dc_slot_flag[3] , + \CPLD_Con_1/dc_slot_flag[2] , \CPLD_Con_1/dc_slot_flag[1] , + \CPLD_Con_1/dc_slot_flag[0] , \CPLD_Con_1/m9_0_1_tz , + \CPLD_Con_1/m9_0_0 , \CPLD_Con_1/RC_VISel_6 , o_RC_ISel_c, + reg_addr_3_rep1, \CPLD_Reg_1/regtable[14][0] , reg_addr_3_rep2, + \CPLD_Reg_1/regtable[10][0] , \CPLD_Reg_1/rdata_reg_2[0] , + \reg_addr[1] , reg_addr_2_rep1, \CPLD_Reg_1/N_350 , + \CPLD_Reg_1/N_326 , \CPLD_Reg_1/rdata_reg_1_sqmuxa , + \CPLD_Reg_1/N_230 , \r_data[0] , \DC_Con1[1] , + \CPLD_Reg_1/regtable[14][1] , \freq1_relay[1] , + \CPLD_Reg_1/regtable[10][1] , \CPLD_Reg_1/rdata_reg_2[1] , + \CPLD_Reg_1/N_351 , \CPLD_Reg_1/N_327 , \CPLD_Reg_1/N_231 , + \r_data[1] , \DC_Con1[2] , \CPLD_Reg_1/regtable[14][2] , + \freq1_relay[2] , \CPLD_Reg_1/regtable[10][2] , + \CPLD_Reg_1/rdata_reg_2[2] , \CPLD_Reg_1/N_352 , \CPLD_Reg_1/N_328 , + \CPLD_Reg_1/N_232 , \r_data[2] , \DC_Con1[3] , + \CPLD_Reg_1/regtable[14][3] , \freq1_relay[3] , + \CPLD_Reg_1/regtable[10][3] , \CPLD_Reg_1/rdata_reg_2[3] , + \CPLD_Reg_1/N_353 , \CPLD_Reg_1/N_329 , \CPLD_Reg_1/N_233 , + \r_data[3] , \DC_Con1[4] , \CPLD_Reg_1/regtable[14][4] , + \freq1_relay[4] , \CPLD_Reg_1/regtable[10][4] , + \CPLD_Reg_1/rdata_reg_2[4] , \CPLD_Reg_1/N_354 , \CPLD_Reg_1/N_330 , + \CPLD_Reg_1/N_234 , \r_data[4] , \DC_Con1[5] , + \CPLD_Reg_1/regtable[14][5] , \freq1_relay[5] , + \CPLD_Reg_1/regtable[10][5] , \CPLD_Reg_1/rdata_reg_2[5] , + \CPLD_Reg_1/N_355 , \CPLD_Reg_1/N_331 , \CPLD_Reg_1/N_235 , + \r_data[5] , \DC_Con1[6] , \CPLD_Reg_1/regtable[14][6] , + \freq1_relay[6] , \CPLD_Reg_1/regtable[10][6] , + \CPLD_Reg_1/rdata_reg_2[6] , \CPLD_Reg_1/N_356 , \CPLD_Reg_1/N_332 , + \CPLD_Reg_1/N_236 , \r_data[6] , \DC_Con1[7] , + \CPLD_Reg_1/regtable[14][7] , \freq1_relay[7] , + \CPLD_Reg_1/regtable[10][7] , \CPLD_Reg_1/rdata_reg_2[7] , + \CPLD_Reg_1/N_357 , \CPLD_Reg_1/N_333 , \CPLD_Reg_1/N_237 , + \r_data[7] , \DC_Con1[8] , \CPLD_Reg_1/regtable[14][8] , + \reg_addr[3] , \freq1_relay[8] , \CPLD_Reg_1/regtable[10][8] , + \CPLD_Reg_1/rdata_reg_2[8] , \CPLD_Reg_1/N_358 , \CPLD_Reg_1/N_334 , + \CPLD_Reg_1/N_238 , \r_data[8] , \DC_Con1[9] , + \CPLD_Reg_1/regtable[14][9] , \freq1_relay[9] , + \CPLD_Reg_1/regtable[10][9] , \CPLD_Reg_1/rdata_reg_2[9] , + \CPLD_Reg_1/N_359 , \CPLD_Reg_1/N_335 , \CPLD_Reg_1/N_239 , + \r_data[9] , \CPLD_Reg_1/regtable[14][10] , + \CPLD_Reg_1/regtable[6][10] , \CPLD_Reg_1/regtable[10][10] , + \CPLD_Reg_1/regtable[2][10] , \CPLD_Reg_1/rdata_reg_2[10] , + \CPLD_Reg_1/N_118 , \CPLD_Reg_1/N_336 , \CPLD_Reg_1/N_1234 , + \r_data[10] , \CPLD_Reg_1/regtable[14][11] , + \CPLD_Reg_1/regtable[6][11] , \CPLD_Reg_1/regtable[10][11] , + \CPLD_Reg_1/regtable[2][11] , \CPLD_Reg_1/rdata_reg_2[11] , + \CPLD_Reg_1/N_1246 , \CPLD_Reg_1/N_337 , \CPLD_Reg_1/N_1235 , + \r_data[11] , \CPLD_Reg_1/regtable[14][12] , + \CPLD_Reg_1/regtable[6][12] , \CPLD_Reg_1/regtable[10][12] , + \CPLD_Reg_1/regtable[2][12] , \CPLD_Reg_1/rdata_reg_2[12] , + \CPLD_Reg_1/N_1245 , \CPLD_Reg_1/N_338 , \CPLD_Reg_1/N_1236 , + \r_data[12] , \CPLD_Reg_1/regtable[14][13] , + \CPLD_Reg_1/regtable[6][13] , \CPLD_Reg_1/regtable[10][13] , + \CPLD_Reg_1/regtable[2][13] , \CPLD_Reg_1/rdata_reg_2[13] , + \CPLD_Reg_1/N_1244 , \CPLD_Reg_1/N_339 , \CPLD_Reg_1/N_1237 , + \r_data[13] , \CPLD_Reg_1/regtable[14][14] , + \CPLD_Reg_1/regtable[6][14] , \CPLD_Reg_1/regtable[10][14] , + \CPLD_Reg_1/regtable[2][14] , \CPLD_Reg_1/rdata_reg_2[14] , + \CPLD_Reg_1/N_1243 , \CPLD_Reg_1/N_340 , \CPLD_Reg_1/N_1238 , + \r_data[14] , \CPLD_Reg_1/regtable[14][15] , + \CPLD_Reg_1/regtable[6][15] , \CPLD_Reg_1/regtable[10][15] , + \CPLD_Reg_1/regtable[2][15] , \CPLD_Reg_1/rdata_reg_2[15] , + \CPLD_Reg_1/N_1242 , \CPLD_Reg_1/N_341 , \CPLD_Reg_1/N_1239 , + \r_data[15] , \CPLD_Reg_1/regtable[14][16] , + \CPLD_Reg_1/regtable[6][16] , \CPLD_Reg_1/regtable[10][16] , + \CPLD_Reg_1/regtable[2][16] , \CPLD_Reg_1/rdata_reg_2[16] , + \CPLD_Reg_1/N_1241 , \CPLD_Reg_1/N_342 , \CPLD_Reg_1/N_1240 , + \r_data[16] , \DC_Con1[17] , \CPLD_Reg_1/regtable[14][17] , + \CPLD_Reg_1/regtable[10][17] , \CPLD_Reg_1/regtable[2][17] , + \CPLD_Reg_1/rdata_reg_2[17] , \CPLD_Reg_1/N_367 , \CPLD_Reg_1/N_343 , + \CPLD_Reg_1/N_247 , \r_data[17] , \DC_Con1[18] , + \CPLD_Reg_1/regtable[14][18] , \CPLD_Reg_1/regtable[10][18] , + \CPLD_Reg_1/regtable[2][18] , \CPLD_Reg_1/rdata_reg_2[18] , + \CPLD_Reg_1/N_368 , \CPLD_Reg_1/N_344 , \CPLD_Reg_1/N_248 , + \r_data[18] , \DC_Con1[19] , \CPLD_Reg_1/regtable[14][19] , + \CPLD_Reg_1/regtable[10][19] , \CPLD_Reg_1/regtable[2][19] , + \CPLD_Reg_1/rdata_reg_2[19] , \CPLD_Reg_1/N_369 , \CPLD_Reg_1/N_345 , + \CPLD_Reg_1/N_249 , \r_data[19] , \DC_Con1[20] , + \CPLD_Reg_1/regtable[14][20] , \CPLD_Reg_1/regtable[10][20] , + \CPLD_Reg_1/regtable[2][20] , \CPLD_Reg_1/rdata_reg_2[20] , + \CPLD_Reg_1/N_370 , \CPLD_Reg_1/N_346 , \CPLD_Reg_1/N_250 , + \r_data[20] , \DC_Con1[21] , \CPLD_Reg_1/regtable[14][21] , + \CPLD_Reg_1/regtable[10][21] , \CPLD_Reg_1/regtable[2][21] , + \CPLD_Reg_1/rdata_reg_2[21] , \CPLD_Reg_1/N_371 , \CPLD_Reg_1/N_347 , + \CPLD_Reg_1/N_251 , \r_data[21] , \DC_Con1[22] , + \CPLD_Reg_1/regtable[14][22] , \CPLD_Reg_1/regtable[10][22] , + \CPLD_Reg_1/regtable[2][22] , \CPLD_Reg_1/rdata_reg_2[22] , + \CPLD_Reg_1/N_372 , \CPLD_Reg_1/N_348 , \CPLD_Reg_1/N_252 , + \r_data[22] , \DC_Con1[23] , \CPLD_Reg_1/regtable[14][23] , + \CPLD_Reg_1/regtable[10][23] , \CPLD_Reg_1/regtable[2][23] , + \CPLD_Reg_1/rdata_reg_2[23] , \CPLD_Reg_1/N_373 , \CPLD_Reg_1/N_349 , + \CPLD_Reg_1/N_253 , \r_data[23] , \BUS_Con_1/recv_reg[25] , + \BUS_Con_1/recv_reg[26] , \BUS_Con_1/N_237_i , + \BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK , \reg_addr[2] , + \BUS_Con_1/recv_reg[27] , \BUS_Con_1/recv_reg[28] , + \BUS_Con_1/recv_reg[29] , \BUS_Con_1/recv_reg[30] , + \CPLD_Reg_1/busy_flag_1_i_a3_0_0 , \CPLD_Reg_1/N_43_i , + \CPLD_Reg_1/state_6_d_i , \BUS_Con_1/recv_reg[0] , \reg_addr_fast[3] , + \BUS_Con_1/recv_reg[1] , \BUS_Con_1/recv_reg[2] , \w_data[2] , + \w_data[1] , \BUS_Con_1/recv_reg[3] , \BUS_Con_1/recv_reg[4] , + \w_data[4] , \w_data[3] , \BUS_Con_1/recv_reg[5] , + \BUS_Con_1/recv_reg[6] , \w_data[6] , \w_data[5] , + \BUS_Con_1/recv_reg[7] , \BUS_Con_1/recv_reg[8] , \w_data[7] , + \BUS_Con_1/recv_reg[13] , \BUS_Con_1/recv_reg[12] , o_wready_c, + \w_data[12] , \w_data[13] , \BUS_Con_1/recv_reg[15] , + \BUS_Con_1/recv_reg[14] , o_RC_ISel_c_i, \w_data[14] , + \CPLD_Reg_1/un34_regtable_5[1] , \DC_Con2[2] , \DC_Con2[1] , + \DC_Con4[3] , \DC_Con4[2] , \CPLD_Reg_1.regtable[9]_fast[4] , + \BUS_Con_1/recv_reg[17] , \BUS_Con_1/recv_reg[16] , + \CPLD_Con_1/g0_19_1 , \CPLD_Con_1/g0_21_N_3L3 , \w_data[17] , + \CPLD_Reg_1.regtable[8]_fast[6] , \CPLD_Reg_1.regtable[8]_fast[5] , + \BUS_Con_1/recv_reg[19] , \BUS_Con_1/recv_reg[18] , + \CPLD_Con_1/OC_x0112lto2_0 , \w_data[18] , \CPLD_Con_1/g0_3_1_N_2L1 , + \w_data[19] , \DC_Con2[20] , \DC_Con2[19] , \BUS_Con_1/recv_reg[21] , + \BUS_Con_1/recv_reg[20] , \CPLD_Con_1/N_51 , + \CPLD_Con_1/OC_x0112lto8_0 , \DC_Con4[19] , + \CPLD_Con_1/dc_slot_flag_3_rep1 , \CPLD_Con_1.exec_flag , + \BUS_Con_1/recv_reg[23] , \BUS_Con_1/recv_reg[22] , + \CPLD_Con_1/err_flag39 , \CPLD_Con_1/N_165 , \freq2_relay[3] , + \freq2_relay[2] , \freq2_relay[1] , \CPLD_Con_1/N_100 , + \CPLD_Con_1/N_96 , \DC_Con2[6] , \DC_Con2[5] , + \BUS_Con_1/recv_reg[24] , \BUS_Con_1/wr_out_6 , + \CPLD_Con_1.PMU_OC_2_8[21] , wr_flag, \CPLD_Con_1/OC_x0126lt3 , + \reg_addr[0] , \CPLD_Con_1/m9_0_a5_1_1 , \DC_Con2[22] , + \CPLD_Con_1/un1_i_freq_relay1lt8 , \CPLD_Con_1/un1_i_freq_relay1_1 , + \CPLD_Con_1/DMM_en_2_sqmuxa_1_0 , \CPLD_Con_1/un1_i_DC_Con1_1[3] , + \CPLD_Con_1/un1_DMM_en_1[0] , \CPLD_Con_1/N_41_1 , \CPLD_Con_1/N_311 , + \CPLD_Con_1.DMM_en_22[2] , \freq3_relay[9] , \freq3_relay[8] , + \CPLD_Con_1/N_90 , \CPLD_Con_1/DMM_en_12_sqmuxa_1_1 , + \CPLD_Con_1/N_42_1 , \CPLD_Con_1.DMM_en_22[11] , + \CPLD_Con_1/OC_x0112 , \CPLD_Con_1/N_40_1 , \CPLD_Con_1.DMM_en_22[1] , + \CPLD_Con_1/N_349 , \CPLD_Con_1/un1_i_freq_relay3lt8 , + \CPLD_Con_1/OC_x0163 , \CPLD_Con_1/DMM_en_10_sqmuxa_1 , + \CPLD_Con_1.DMM_en_22[9] , \CPLD_Con_1/DMM_en_1_sqmuxa_1_0 , + \CPLD_Con_1/N_39_1 , \CPLD_Con_1.DMM_en_22[0] , \CPLD_Con_1/N_9 , + \CPLD_Con_1/OC_x0138_3 , \CPLD_Con_1.DMM_en_22[8] , + \CPLD_Reg_1/regtable[15][0] , \CPLD_Reg_1/regtable[11][0] , + reg_addr_0_rep2, reg_addr_2_rep2, \CPLD_Reg_1/N_278 , + \CPLD_Reg_1/regtable[13][23] , \DC_Con3[23] , + \CPLD_Reg_1/regtable[12][23] , reg_addr_0_rep1, \CPLD_Reg_1/N_325 , + \CPLD_Reg_1/N_277 , \CPLD_Reg_1/regtable[13][0] , + \CPLD_Reg_1/regtable[12][0] , \CPLD_Reg_1/N_302 , \CPLD_Reg_1/N_254 , + \DC_Con4[9] , \CPLD_Reg_1/regtable[13][9] , \DC_Con3[9] , + \CPLD_Reg_1/regtable[12][9] , \CPLD_Reg_1/N_311 , \CPLD_Reg_1/N_263 , + \CPLD_Reg_1/regtable[13][16] , \CPLD_Reg_1/regtable[12][16] , + \CPLD_Reg_1/regtable[8][16] , \CPLD_Reg_1/N_1233 , \CPLD_Reg_1/N_270 , + \CPLD_Reg_1/regtable[13][15] , \CPLD_Reg_1/regtable[12][15] , + \CPLD_Reg_1/regtable[8][15] , \CPLD_Reg_1/N_1232 , \CPLD_Reg_1/N_269 , + \CPLD_Reg_1/regtable[13][14] , \CPLD_Reg_1/regtable[9][14] , + \CPLD_Reg_1/regtable[12][14] , \CPLD_Reg_1/regtable[8][14] , + \CPLD_Reg_1/N_1231 , \CPLD_Reg_1/N_268 , + \CPLD_Reg_1/regtable[13][13] , \CPLD_Reg_1/regtable[9][13] , + \CPLD_Reg_1/regtable[12][13] , \CPLD_Reg_1/regtable[8][13] , + \CPLD_Reg_1/N_1230 , \CPLD_Reg_1/N_267 , + \CPLD_Reg_1/regtable[13][12] , \CPLD_Reg_1/regtable[9][12] , + \CPLD_Reg_1/regtable[12][12] , \CPLD_Reg_1/regtable[8][12] , + \CPLD_Reg_1/N_1229 , \CPLD_Reg_1/N_266 , + \CPLD_Reg_1/regtable[13][11] , \CPLD_Reg_1/regtable[9][11] , + \CPLD_Reg_1/regtable[12][11] , \CPLD_Reg_1/regtable[8][11] , + \CPLD_Reg_1/N_1228 , \CPLD_Reg_1/N_265 , + \CPLD_Reg_1/regtable[13][10] , \CPLD_Reg_1/regtable[9][10] , + \CPLD_Reg_1/regtable[12][10] , \CPLD_Reg_1/regtable[8][10] , + \CPLD_Reg_1/N_1227 , \CPLD_Reg_1/N_264 , \DC_Con4[18] , + \CPLD_Reg_1/regtable[13][18] , \DC_Con3[18] , + \CPLD_Reg_1/regtable[12][18] , \CPLD_Reg_1/N_320 , \CPLD_Reg_1/N_272 , + \DC_Con4[1] , \CPLD_Reg_1/regtable[13][1] , \DC_Con3[1] , + \CPLD_Reg_1/regtable[12][1] , \CPLD_Reg_1/N_303 , \CPLD_Reg_1/N_255 , + \CPLD_Reg_1/regtable[13][2] , \DC_Con3[2] , + \CPLD_Reg_1/regtable[12][2] , \CPLD_Reg_1/N_304 , \CPLD_Reg_1/N_256 , + \CPLD_Reg_1/regtable[13][3] , \DC_Con3[3] , + \CPLD_Reg_1/regtable[12][3] , \CPLD_Reg_1/N_305 , \CPLD_Reg_1/N_257 , + \DC_Con4[4] , \CPLD_Reg_1/regtable[13][4] , \DC_Con3[4] , + \CPLD_Reg_1/regtable[12][4] , \CPLD_Reg_1/N_306 , \CPLD_Reg_1/N_258 , + \DC_Con4[5] , \CPLD_Reg_1/regtable[13][5] , \DC_Con3[5] , + \CPLD_Reg_1/regtable[12][5] , \CPLD_Reg_1/N_307 , \CPLD_Reg_1/N_259 , + \DC_Con4[6] , \CPLD_Reg_1/regtable[13][6] , \DC_Con3[6] , + \CPLD_Reg_1/regtable[12][6] , \CPLD_Reg_1/N_308 , \CPLD_Reg_1/N_260 , + \DC_Con4[7] , \CPLD_Reg_1/regtable[13][7] , \DC_Con3[7] , + \CPLD_Reg_1/regtable[12][7] , \CPLD_Reg_1/N_309 , \CPLD_Reg_1/N_261 , + \DC_Con4[8] , \CPLD_Reg_1/regtable[13][8] , \DC_Con3[8] , + \CPLD_Reg_1/regtable[12][8] , \CPLD_Reg_1/N_310 , \CPLD_Reg_1/N_262 , + \DC_Con4[17] , \CPLD_Reg_1/regtable[13][17] , \DC_Con3[17] , + \CPLD_Reg_1/regtable[12][17] , \CPLD_Reg_1/N_319 , \CPLD_Reg_1/N_271 , + \CPLD_Reg_1/regtable[13][19] , \DC_Con3[19] , + \CPLD_Reg_1/regtable[12][19] , \CPLD_Reg_1/N_321 , \CPLD_Reg_1/N_273 , + \CPLD_Reg_1/regtable[13][20] , \DC_Con3[20] , + \CPLD_Reg_1/regtable[12][20] , \CPLD_Reg_1/N_322 , \CPLD_Reg_1/N_274 , + \CPLD_Reg_1/regtable[13][21] , \DC_Con3[21] , + \CPLD_Reg_1/regtable[12][21] , \CPLD_Reg_1/N_323 , \CPLD_Reg_1/N_275 , + \CPLD_Reg_1/regtable[13][22] , \CPLD_Reg_1/regtable[12][22] , + \CPLD_Reg_1/N_324 , \CPLD_Reg_1/N_276 , \DC_Con2[23] , + \CPLD_Reg_1/regtable[15][23] , \CPLD_Reg_1/regtable[11][23] , + \CPLD_Reg_1/regtable[3][23] , \CPLD_Reg_1/N_301 , + \CPLD_Reg_1/regtable[5][23] , \CPLD_Reg_1/regtable[4][23] , + \CPLD_Reg_1/regtable[0][23] , \CPLD_Reg_1/regtable[0][0] , + \DC_Con2[9] , \CPLD_Reg_1/regtable[15][9] , \freq2_relay[9] , + \CPLD_Reg_1/regtable[11][9] , \CPLD_Reg_1/N_287 , \freq4_relay[9] , + \CPLD_Reg_1/regtable[1][9] , \CPLD_Reg_1/regtable[0][9] , + \CPLD_Reg_1/regtable[15][16] , \CPLD_Reg_1/regtable[7][16] , + \CPLD_Reg_1/regtable[11][16] , \CPLD_Reg_1/regtable[3][16] , + \CPLD_Reg_1/N_79 , \CPLD_Reg_1/regtable[15][15] , + \CPLD_Reg_1/regtable[7][15] , \CPLD_Reg_1/regtable[11][15] , + \CPLD_Reg_1/regtable[3][15] , \CPLD_Reg_1/N_80 , + \CPLD_Reg_1/regtable[15][14] , \CPLD_Reg_1/regtable[7][14] , + \CPLD_Reg_1/regtable[11][14] , \CPLD_Reg_1/regtable[3][14] , + \CPLD_Reg_1/N_81 , \CPLD_Reg_1/regtable[15][13] , + \CPLD_Reg_1/regtable[7][13] , \CPLD_Reg_1/regtable[11][13] , + \CPLD_Reg_1/regtable[3][13] , \CPLD_Reg_1/N_82 , + \CPLD_Reg_1/regtable[15][12] , \CPLD_Reg_1/regtable[7][12] , + \CPLD_Reg_1/regtable[11][12] , \CPLD_Reg_1/regtable[3][12] , + \CPLD_Reg_1/N_83 , \CPLD_Reg_1/regtable[15][11] , + \CPLD_Reg_1/regtable[7][11] , \CPLD_Reg_1/regtable[11][11] , + \CPLD_Reg_1/regtable[3][11] , \CPLD_Reg_1/N_1267 , + \CPLD_Reg_1/regtable[15][10] , \CPLD_Reg_1/regtable[7][10] , + \CPLD_Reg_1/regtable[11][10] , \CPLD_Reg_1/regtable[3][10] , + \CPLD_Reg_1/N_1268 , \freq4_relay[16] , \CPLD_Reg_1/regtable[4][16] , + \CPLD_Reg_1/regtable[1][16] , \CPLD_Reg_1/regtable[0][16] , + \freq4_relay[15] , \CPLD_Reg_1/regtable[4][15] , + \CPLD_Reg_1/regtable[1][15] , \CPLD_Reg_1/regtable[0][15] , + \freq4_relay[14] , \CPLD_Reg_1/regtable[4][14] , + \CPLD_Reg_1/regtable[1][14] , \CPLD_Reg_1/regtable[0][14] , + \freq4_relay[13] , \CPLD_Reg_1/regtable[4][13] , + \CPLD_Reg_1/regtable[1][13] , \CPLD_Reg_1/regtable[0][13] , + \freq4_relay[12] , \CPLD_Reg_1/regtable[4][12] , + \CPLD_Reg_1/regtable[1][12] , \CPLD_Reg_1/regtable[0][12] , + \CPLD_Reg_1/regtable[5][11] , \CPLD_Reg_1/regtable[4][11] , + \CPLD_Reg_1/regtable[1][11] , \CPLD_Reg_1/regtable[0][11] , + \CPLD_Reg_1/regtable[5][10] , \CPLD_Reg_1/regtable[4][10] , + \CPLD_Reg_1/regtable[1][10] , \CPLD_Reg_1/regtable[0][10] , + \DC_Con2[18] , \CPLD_Reg_1/regtable[15][18] , + \CPLD_Reg_1/regtable[11][18] , \CPLD_Reg_1/regtable[3][18] , + \CPLD_Reg_1/N_296 , \CPLD_Reg_1/regtable[5][18] , + \CPLD_Reg_1/regtable[4][18] , \CPLD_Reg_1/regtable[1][18] , + \CPLD_Reg_1/regtable[0][18] , \CPLD_Reg_1/regtable[15][1] , + \CPLD_Reg_1/regtable[11][1] , \CPLD_Reg_1/N_279 , \freq4_relay[1] , + \freq3_relay[1] , \CPLD_Reg_1/regtable[1][1] , + \CPLD_Reg_1/regtable[0][1] , \freq4_relay[2] , \freq3_relay[2] , + \CPLD_Reg_1/regtable[1][2] , \CPLD_Reg_1/regtable[0][2] , + \CPLD_Reg_1/regtable[15][2] , \CPLD_Reg_1/regtable[11][2] , + \CPLD_Reg_1/N_280 , \freq4_relay[3] , \freq3_relay[3] , + \CPLD_Reg_1/regtable[1][3] , \CPLD_Reg_1/regtable[0][3] , + \DC_Con2[3] , \CPLD_Reg_1/regtable[15][3] , + \CPLD_Reg_1/regtable[11][3] , \CPLD_Reg_1/N_281 , \freq4_relay[4] , + \freq3_relay[4] , \CPLD_Reg_1/regtable[1][4] , + \CPLD_Reg_1/regtable[0][4] , \DC_Con2[4] , + \CPLD_Reg_1/regtable[15][4] , \freq2_relay[4] , + \CPLD_Reg_1/regtable[11][4] , \CPLD_Reg_1/N_282 , \freq4_relay[5] , + \freq3_relay[5] , \CPLD_Reg_1/regtable[1][5] , + \CPLD_Reg_1/regtable[0][5] , \CPLD_Reg_1/regtable[15][5] , + \freq2_relay[5] , \CPLD_Reg_1/regtable[11][5] , \CPLD_Reg_1/N_283 , + \freq4_relay[6] , \freq3_relay[6] , \CPLD_Reg_1/regtable[1][6] , + \CPLD_Reg_1/regtable[0][6] , \CPLD_Reg_1/regtable[15][6] , + \freq2_relay[6] , \CPLD_Reg_1/regtable[11][6] , \CPLD_Reg_1/N_284 , + \freq4_relay[7] , \freq3_relay[7] , \CPLD_Reg_1/regtable[1][7] , + \CPLD_Reg_1/regtable[0][7] , \DC_Con2[7] , + \CPLD_Reg_1/regtable[15][7] , \freq2_relay[7] , + \CPLD_Reg_1/regtable[11][7] , \CPLD_Reg_1/N_285 , \freq4_relay[8] , + \CPLD_Reg_1/regtable[1][8] , \CPLD_Reg_1/regtable[0][8] , + \DC_Con2[8] , \CPLD_Reg_1/regtable[15][8] , \freq2_relay[8] , + \CPLD_Reg_1/regtable[11][8] , \CPLD_Reg_1/N_286 , \freq4_relay[17] , + \CPLD_Reg_1/regtable[4][17] , \CPLD_Reg_1/regtable[1][17] , + \CPLD_Reg_1/regtable[0][17] , \DC_Con2[17] , + \CPLD_Reg_1/regtable[15][17] , \CPLD_Reg_1/regtable[11][17] , + \CPLD_Reg_1/regtable[3][17] , \CPLD_Reg_1/N_295 , + \CPLD_Reg_1/regtable[5][19] , \CPLD_Reg_1/regtable[4][19] , + \CPLD_Reg_1/regtable[1][19] , \CPLD_Reg_1/regtable[0][19] , + \CPLD_Reg_1/regtable[15][19] , \CPLD_Reg_1/regtable[11][19] , + \CPLD_Reg_1/regtable[3][19] , \CPLD_Reg_1/N_297 , + \CPLD_Reg_1/regtable[5][20] , \CPLD_Reg_1/regtable[4][20] , + \CPLD_Reg_1/regtable[1][20] , \CPLD_Reg_1/regtable[0][20] , + \CPLD_Reg_1/regtable[15][20] , \CPLD_Reg_1/regtable[11][20] , + \CPLD_Reg_1/regtable[3][20] , \CPLD_Reg_1/N_298 , + \CPLD_Reg_1/regtable[5][21] , \CPLD_Reg_1/regtable[4][21] , + \CPLD_Reg_1/regtable[1][21] , \CPLD_Reg_1/regtable[0][21] , + \DC_Con2[21] , \CPLD_Reg_1/regtable[15][21] , + \CPLD_Reg_1/regtable[11][21] , \CPLD_Reg_1/regtable[3][21] , + \CPLD_Reg_1/N_299 , \CPLD_Reg_1/regtable[5][22] , + \CPLD_Reg_1/regtable[4][22] , \CPLD_Reg_1/regtable[1][22] , + \CPLD_Reg_1/regtable[0][22] , \CPLD_Reg_1/regtable[15][22] , + \CPLD_Reg_1/regtable[11][22] , \CPLD_Reg_1/regtable[3][22] , + \CPLD_Reg_1/N_300 , \CPLD_Con_1/un1_i_DC_Con1_iv_1[1] , + \CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] , + \CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] , + \CPLD_Con_1/un1_i_DC_Con1_iv_0[1] , \CPLD_Con_1/N_216 , + \CPLD_Con_1/un1_i_DC_Con1_4_axbxc1 , + \CPLD_Reg_1/regtable[4]_1_sqmuxa , N_235, \CPLD_Con_1/N_353 , + \CPLD_Con_1/N_344 , \CPLD_Con_1/N_85 , \CPLD_Con_1/N_338 , + \CPLD_Con_1/DMM_en_22_0_0[15] , \BUS_Con_1/un1_addr_out_0_sqmuxa_0_i , + \BUS_Con_1/recv_reg_1_sqmuxa_1_i , + \BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O , \CPLD_Con_1/N_357 , + \CPLD_Con_1/DMM_en_22_0_a2_2[10] , \CPLD_Con_1/N_305 , + \CPLD_Con_1/N_330 , \w_data[11] , \CPLD_Reg_1/regtable[6]_1_sqmuxa , + \CPLD_Con_1/N_298 , \CPLD_Con_1/DMM_en_3_sqmuxa_1_0_a2_0_a2_0_a2_1 , + \w_data[9] , \CPLD_Reg_1/regtable[8]_1_sqmuxa , \CPLD_Con_1.N_259 , + \CPLD_Con_1/g0_14_N_2L1 , \CPLD_Con_1/N_30 , + \CPLD_Con_1/DMM_en_11_sqmuxa_0_147_i_i_0_0_tz , \CPLD_Con_1/g0_26_x0 , + \CPLD_Con_1/g1_0_0 , \CPLD_Con_1/RC_VISel41 , \CPLD_Con_1/N_192 , + \CPLD_Reg_1/regtable[3]_1_sqmuxa , \CPLD_Con_1.PMU_OC_4_8[13] , + \CPLD_Con_1/N_190 , \CPLD_Con_1.PMU_OC_4_8[15] , \CPLD_Con_1/N_350 , + \CPLD_Con_1/DMM_en_1_sqmuxa_1_0_a2_0_a2_0_a2_2 , + \CPLD_Con_1/DMM_en_1_sqmuxa_1_0_a2_0_a2_0_a2_0 , \CPLD_Con_1.N_333 , + \CPLD_Con_1/PMU_OC_4_8_0_a2_2[3] , \w_data[10] , + \CPLD_Con_1.PMU_OC_4_8[3] , \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[4] , + \CPLD_Con_1/i_DC_Con4_m[8] , \CPLD_Con_1/dc_slot_flag_2_rep1 , + \CPLD_Con_1/un1_i_DC_Con1_1[4] , \CPLD_Con_1/un1_i_DC_Con1_1[5] , + \CPLD_Reg_1/regtable[11]_1_sqmuxa , \CPLD_Con_1/un1_DMM_en[3] , + \CPLD_Con_1/N_113 , \CPLD_Con_1/N_116 , + \CPLD_Reg_1/regtable[12]_1_sqmuxa , \CPLD_Con_1.PMU_OC_1_8[27] , + \CPLD_Con_1/N_115 , \CPLD_Con_1.PMU_OC_1_8[29] , \CPLD_Con_1/N_118 , + \CPLD_Reg_1/regtable[13]_1_sqmuxa , \CPLD_Con_1.PMU_OC_1_8[31] , + \CPLD_Con_1/RC_VISel38 , \CPLD_Con_1.PMU_OC_1_8[11] , + \CPLD_Con_1/N_117 , \CPLD_Con_1.PMU_OC_1_8[15] , + \CPLD_Reg_1.regtable[6]_fast[6] , \CPLD_Reg_1.regtable[6]_fast[5] , + \CPLD_Con_1/N_38 , \CPLD_Reg_1/regtable[14]_1_sqmuxa , + \CPLD_Con_1.PMU_OC_1_8[17] , \CPLD_Con_1/N_119 , + \CPLD_Con_1.PMU_OC_1_8[23] , \CPLD_Con_1/N_43 , + \CPLD_Con_1.PMU_OC_2_8[17] , \CPLD_Con_1/RC_VISel39 , + \CPLD_Con_1/N_95 , \CPLD_Con_1.PMU_OC_2_8[9] , + \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[5] , \CPLD_Con_1/i_DC_Con3_m[9] , + \CPLD_Con_1/N_351 , \CPLD_Con_1/N_114 , \CPLD_Con_1.PMU_OC_1_8[24] , + \CPLD_Con_1/N_67_i , \CPLD_Con_1/g0_12_N_3L3 , \CPLD_Con_1/N_214 , + \CPLD_Con_1/DMM_en_0_sqmuxa_7 , \CPLD_Reg_1/regtable[7]_1_sqmuxa , + \CPLD_Reg_1.regtable[7]_fast[5] , \CPLD_Reg_1.regtable[7]_fast[6] , + \CPLD_Con_1/N_196 , \CPLD_Con_1/un1_exec_flag_8_0_0 , + \CPLD_Con_1/N_191 , \PMU_OC_4_8_0_a2_RNIS7H393[18] , + \CPLD_Con_1/un1_i_DC_Con1_1_iv_1[2] , + \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[2] , + \CPLD_Con_1/DMM_en_22_0_a2_2_1[4] , \CPLD_Con_1/N_360 , + \CPLD_Con_1/N_323 , \CPLD_Con_1/un1_i_DC_Con1_1[1] , + \CPLD_Con_1/un1_i_DC_Con1_1[0] , \CPLD_Con_1.DMM_en_22[5] , + \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[1] , \CPLD_Con_1/i_DC_Con4_m[5] , + \CPLD_Con_1/N_325 , \CPLD_Con_1.DMM_en_22[6] , + \CPLD_Con_1/DMM_en_22_0_a2_1_1[12] , \CPLD_Con_1/N_363 , + \CPLD_Con_1/N_333 , \CPLD_Con_1.DMM_en_22[12] , \CPLD_Con_1/N_70 , + \CPLD_Con_1/un1_i_DC_Con1_1_iv_0_0[0] , \CPLD_Con_1/N_336 , + \CPLD_Con_1.DMM_en_22[14] , \CPLD_Con_1/N_364 , \CPLD_Con_1/N_307 , + \CPLD_Con_1/N_306 , \CPLD_Con_1/DMM_en_22_0_RNO[13] , + \CPLD_Con_1.DMM_en_22[13] , \BUS_Con_1/recv_reg[9] , + \CPLD_Con_1/g2_0 , \CPLD_Con_1/RC_VISel40 , \CPLD_Con_1/N_140 , + \CPLD_Con_1/un1_exec_flag_2_0_0 , \CPLD_Con_1/DMM_en_0_sqmuxa_6 , + \CPLD_Con_1/g0_13_sn , \CPLD_Con_1/g0_13_rn_0 , + \CPLD_Con_1/err_flag19_0_0_0 , \CPLD_Con_1/N_99 , + \CPLD_Con_1/un1_exec_flag_3_0_0 , \CPLD_Con_1/DMM_en_0_sqmuxa_5 , + \CPLD_Con_1/N_407 , \CPLD_Con_1/N_329 , + \CPLD_Con_1/DMM_en_22_0_a2_1[7] , \CPLD_Con_1/DMM_en_22_0_0[7] , + \CPLD_Con_1.DMM_en_22[7] , \CPLD_Con_1/freq_slot_flag[2] , + \CPLD_Con_1/freq_slot_flag[0] , \CPLD_Con_1.DMM_en_22[3] , + \CPLD_Con_1/dc_slot_flag_1_rep1 , \CPLD_Con_1/dc_slot_flag_0_rep1 , + \CPLD_Con_1/un1_exec_flag_4_0_0 , \CPLD_Con_1/DMM_en_0_sqmuxa_3 , + \CPLD_Con_1.un1_exec_flag_4_i , \CPLD_Con_1/N_202 , + \CPLD_Con_1/RC_RLSel_13_0_a3_2_N_4L5 , + \CPLD_Con_1/RC_RLSel_13_0_a3_2_N_3L3 , + \CPLD_Con_1/RC_RLSel_13_0_a3_2_N_2L1 , + \CPLD_Reg_1/regtable[5]_1_sqmuxa , N_234, N_233, + \CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 , + \CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 , \CPLD_Con_1.RC_RLSel_13[12] , + N_232, \CPLD_Con_1.RC_RLSel_13[11] , \CPLD_Con_1/N_78 , + \CPLD_Con_1/err_flag25_0_o2_2 , \CPLD_Con_1/err_flag25_0_0_0 , + \CPLD_Con_1/err_flag19 , \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[3] , + \CPLD_Con_1/i_DC_Con4_m[7] , \CPLD_Con_1/DMM_en_22_0_0[10] , + \CPLD_Con_1.DMM_en_22[10] , \CPLD_Con_1/un1_i_DC_Con1_iv_0_1[4] , + \CPLD_Con_1/un1_i_DC_Con1_iv_0_0[4] , \CPLD_Con_1/RC_RLSel_13_1[16] , + \CPLD_Con_1.RC_RLSel_13[17] , \CPLD_Con_1.RC_RLSel_13[16] , + \CPLD_Con_1/DMM_en_22_2[16] , \CPLD_Con_1.DMM_en_22[16] , + \CPLD_Con_1/un1_DMM_en_1_sqmuxa_tz , \CPLD_Con_1/N_59_1 , + \CPLD_Con_1.DMM_en_22[17] , \CPLD_Con_1/N_60_1 , + \CPLD_Con_1.DMM_en_22[18] , \CPLD_Con_1/N_356 , \CPLD_Con_1/N_342 , + \CPLD_Con_1/N_308 , \CPLD_Con_1.N_315 , + \CPLD_Con_1/freq_slot_flag[3] , \CPLD_Con_1/freq_slot_flag[1] , + \CPLD_Con_1/DMM_en_7_sqmuxa_0_121_a2_0_a2_0 , + \DMM_en_22_0_o2_0_RNI5A4QI[7] , \CPLD_Con_1/DMM_en_22_0_a2_0[6] , + \CPLD_Reg_1/regtable[10]_1_sqmuxa , + \CPLD_Con_1/DMM_en_22_0_a2_0_1[10] , \CPLD_Con_1/un1_err_flag41_i , + \CPLD_Con_1.RC_Tx_0_sqmuxa_1_i , \CPLD_Con_1/OC_x0112lto8_4_0 , N_22, + \CPLD_Con_1/N_143 , \CPLD_Con_1/N_136 , + \CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 , + \CPLD_Con_1.PMU_OC_3_8[26] , \CPLD_Con_1/N_141 , + \CPLD_Con_1.PMU_OC_3_8[27] , \CPLD_Con_1.PMU_OC_3_8[28] , + \CPLD_Con_1/N_150 , \CPLD_Reg_1/regtable[15]_1_sqmuxa , + \CPLD_Con_1.PMU_OC_3_8[10] , \CPLD_Con_1.PMU_OC_3_8[11] , + \CPLD_Con_1/N_137 , \CPLD_Con_1.PMU_OC_3_8[18] , + \CPLD_Con_1.PMU_OC_3_8[2] , \CPLD_Reg_1/regtable[2]_1_sqmuxa , + \CPLD_Con_1.PMU_OC_3_8[4] , \CPLD_Con_1.PMU_OC_3_8[6] , + \CPLD_Con_1/N_102 , \CPLD_Con_1.PMU_OC_2_8[26] , + \CPLD_Con_1.PMU_OC_2_8[27] , \CPLD_Con_1/N_111 , + \CPLD_Con_1.PMU_OC_2_8[10] , \CPLD_Con_1.PMU_OC_2_8[11] , + \CPLD_Con_1.PMU_OC_2_8[18] , \CPLD_Con_1.PMU_OC_2_8[2] , + \CPLD_Con_1.PMU_OC_2_8[4] , \CPLD_Con_1.PMU_OC_2_8[6] , + \CPLD_Con_1/err_flag13_0_o2_0_2 , \CPLD_Con_1/N_65 , + \CPLD_Con_1/err_flag13_0_0_0 , \CPLD_Con_1/N_365 , + \DMM_en_22_0_a2_3_RNIK2BQH[4] , \DMM_en_22_0_o2_RNI8QTBL[15] , + \CPLD_Con_1.PMU_OC_3_8[8] , \CPLD_Con_1/N_227 , \CPLD_Con_1/N_206 , + \CPLD_Con_1.PMU_OC_4_8[29] , \CPLD_Con_1/N_188 , + \CPLD_Con_1.PMU_OC_4_8[17] , \CPLD_Con_1.PMU_OC_4_8[21] , + \CPLD_Con_1/N_361 , \CPLD_Con_1/OC_x0153lt3 , + \CPLD_Con_1/dc_slot_flag_fast[3] , \CPLD_Con_1/dc_slot_flag_fast[2] , + \CPLD_Con_1/dc_slot_flag_fast[1] , \CPLD_Con_1/dc_slot_flag_fast[0] , + \CPLD_Con_1/N_215 , \CPLD_Con_1/PMU_OC_4_8_0[25] , + \CPLD_Con_1.PMU_OC_4_8[25] , + \CPLD_Con_1/err_flag13_0_o2_0_2_RNIH4D9O_0 , \CPLD_Con_1/N_57 , + \CPLD_Con_1/err_flag13_0_0_0_RNIM0FM71 , + \CPLD_Con_1/err_flag19_0_o2_2_RNIDVKG21 , + \CPLD_Con_1/dc_slot_flag_RNIQ9AIV[0] , + \CPLD_Con_1/err_flag19_0_0_0_RNIAI9L43 , + \CPLD_Con_1/DMM_en_12_sqmuxa_1_0 , + \CPLD_Con_1/un1_i_DC_Con1_iv_0_0[2] , + \CPLD_Con_1/RC_RLSel_141_N_2_3_0 , \CPLD_Con_1/N_173 , + \CPLD_Con_1/un1_i_DC_Con1_iv_0_0[3] , \CPLD_Con_1/g0_8_1 , + \CPLD_Con_1/g0_2_N_5L7_N_6L9_0_1 , \CPLD_Con_1/g0_2_1 , + \CPLD_Con_1/err_flag19_0_o2_2 , \CPLD_Reg_1.regtable[7]_fast[7] , + \CPLD_Con_1/g2_0_0 , \CPLD_Con_1/OC_x17_0_sqmuxa_i_1 , + \CPLD_Con_1/g0_21_N_2L1 , \CPLD_Con_1/N_60 , \CPLD_Con_1/g0_7_2 , + \CPLD_Con_1/g0_6_2 , \CPLD_Con_1/g0_2_N_2L1_1_N_2L1 , + \CPLD_Con_1/g0_2_1_1 , \CPLD_Reg_1.regtable[9]_fast[6] , + \CPLD_Con_1/g1_1_3 , \CPLD_Reg_1.regtable[9]_fast[7] , + \CPLD_Reg_1.regtable[9]_fast[5] , \CPLD_Con_1/un1_exec_flag_10_i_1 , + \CPLD_Con_1.un1_exec_flag_10_i , \CPLD_Con_1/g0_3_1_N_5L8 , + \CPLD_Con_1/g0_1_2_0 , \CPLD_Con_1/g0_1_0_0_1 , + \CPLD_Con_1/un1_exec_flag_10_0 , + \CPLD_Con_1/un1_i_DC_Con1_iv_0_RNIL5OH12[2] , + \CPLD_Con_1/g0_10_N_3L3 , \CPLD_Con_1/g0_10_N_2L1 , + \CPLD_Con_1/g0_1_0 , \CPLD_Con_1/err_flag13_0_0_0_RNI92FNE1_0 , + err_flag13_0_0_0_RNILOU7L8, \CPLD_Con_1/err_flag19_0_0_0_RNI2M1DH2 , + \CPLD_Con_1/DMM_en_22_0_N_2L1_0 , \CPLD_Con_1.DMM_en_22[4] , + \CPLD_Con_1/g0_12_N_2L1 , + \CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNI54G4K2_0 , \CPLD_Con_1/g0_3_1 , + \CPLD_Con_1/dc_slot_flag_0_rep1_RNIULU4R , + \CPLD_Con_1/dc_t_RNI2Q6P8_0 , \CPLD_Con_1/g0_2_1_0 , + \CPLD_Con_1/dc_slot_flag_RNIANH1R_3[0] , + \CPLD_Con_1/freq_t_RNIDK1OA3 , + \CPLD_Con_1/freq_slot_flag_RNIBOV481[0] , + \CPLD_Con_1/dc_slot_flag_0_rep1_RNI421QK , + \CPLD_Con_1/freq_t_RNI8PH26 , \CPLD_Con_1.DMM_en_0_sqmuxa_9_i , + \CPLD_Con_1/g0_2_x1_N_2L1 , \CPLD_Reg_1/un34_regtable_1_0_0 , + \CPLD_Reg_1/state_ns_0_a4_0_1[1] , + \CPLD_Reg_1/regtable[0]_1_sqmuxa_1 , + \CPLD_Reg_1/rdata_reg_1_sqmuxa_2 , \reg_addr_fast[0] , + \CPLD_Reg_1/N_1185 , \reg_addr_fast[2] , + \CPLD_Reg_1/regtable[0]_1_sqmuxa , \CPLD_Reg_1/regtable[1]_1_sqmuxa , + \CPLD_Reg_1/N_1186 , \CPLD_Reg_1/regtable[7]_1_sqmuxa_2 , + \CPLD_Reg_1/N_1169 , \CPLD_Reg_1/N_1171 , + \CPLD_Reg_1/regtable[5]_1_sqmuxa_0_a2_0 , \CPLD_Reg_1/un10_0_a3_0 , + \BUS_Con_1/N_240 , \BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNIVM1LH , + \BUS_Con_1/recv_reg[10] , \BUS_Con_1/recv_reg[11] , \BUS_Con_1/N_253 , + \BUS_Con_1/N_242 , \CPLD_Con_1.PMU_OC_4_8[9] , + \CPLD_Con_1.PMU_OC_4_8[8] , \CPLD_Con_1.PMU_OC_4_8[11] , + \CPLD_Con_1.PMU_OC_4_8[31] , \CPLD_Con_1.PMU_OC_4_8[28] , + \CPLD_Con_1.PMU_OC_4_8[24] , \CPLD_Con_1.PMU_OC_4_8[27] , + \CPLD_Con_1.PMU_OC_4_8[14] , \CPLD_Con_1.PMU_OC_1_8[13] , + \CPLD_Con_1.PMU_OC_1_8[5] , \CPLD_Con_1.PMU_OC_1_8[19] , + \CPLD_Con_1.PMU_OC_1_8[3] , \CPLD_Con_1.PMU_OC_1_8[25] , + \CPLD_Con_1.PMU_OC_1_8[1] , \CPLD_Con_1.PMU_OC_4_8[26] , + \CPLD_Con_1.PMU_OC_4_8[10] , \CPLD_Con_1.PMU_OC_2_8[25] , + \CPLD_Con_1.PMU_OC_2_8[8] , \CPLD_Con_1.PMU_OC_1_8[22] , + \CPLD_Con_1.PMU_OC_1_8[6] , \CPLD_Con_1.PMU_OC_1_8[20] , + \CPLD_Con_1.PMU_OC_1_8[4] , \CPLD_Con_1.PMU_OC_1_8[18] , + \CPLD_Con_1.PMU_OC_1_8[2] , \CPLD_Con_1.PMU_OC_1_8[12] , + \CPLD_Con_1.PMU_OC_1_8[28] , \CPLD_Con_1.PMU_OC_1_8[10] , + \CPLD_Con_1.PMU_OC_1_8[26] , \CPLD_Con_1.PMU_OC_3_8[29] , + \CPLD_Con_1.PMU_OC_3_8[25] , \CPLD_Con_1.PMU_OC_3_8[30] , + \CPLD_Con_1.PMU_OC_3_8[24] , \CPLD_Con_1.PMU_OC_3_8[13] , + \CPLD_Con_1.PMU_OC_3_8[9] , \CPLD_Con_1.PMU_OC_3_8[19] , + \CPLD_Con_1.PMU_OC_3_8[17] , \CPLD_Con_1.PMU_OC_3_8[20] , + \CPLD_Con_1.PMU_OC_3_8[22] , \CPLD_Con_1.PMU_OC_3_8[21] , + \CPLD_Con_1.PMU_OC_3_8[23] , \CPLD_Con_1.PMU_OC_2_8[28] , + \CPLD_Con_1.PMU_OC_2_8[30] , \CPLD_Con_1.PMU_OC_2_8[29] , + \CPLD_Con_1.PMU_OC_2_8[31] , \CPLD_Con_1.PMU_OC_2_8[13] , + \CPLD_Con_1.PMU_OC_2_8[15] , \CPLD_Con_1.PMU_OC_2_8[19] , + \CPLD_Con_1.PMU_OC_2_8[23] , \CPLD_Con_1.PMU_OC_2_8[20] , + \CPLD_Con_1.PMU_OC_2_8[22] , \CPLD_Con_1.PMU_OC_4_8[23] , N_197, + \CPLD_Con_1.PMU_OC_4_8[12] , N_155_i, \CPLD_Con_1.PMU_OC_1_8[21] , + \CPLD_Con_1.PMU_OC_1_8[7] , \CPLD_Con_1.PMU_OC_1_8[9] , + \CPLD_Con_1.PMU_OC_1_8[8] , \CPLD_Con_1.PMU_OC_1_8[14] , + \CPLD_Con_1.PMU_OC_1_8[30] , \CPLD_Con_1.PMU_OC_3_8[31] , + \CPLD_Con_1.PMU_OC_3_8[15] , \CPLD_Con_1.PMU_OC_3_8[12] , + \CPLD_Con_1.PMU_OC_3_8[14] , \CPLD_Con_1.N_364 , + \CPLD_Con_1.PMU_OC_2_8[12] , \CPLD_Con_1.PMU_OC_2_8[14] , + \CPLD_Con_1.io_RC_1_sqmuxa , \CPLD_Con_1.OC_x17_0_sqmuxa_i , + \CPLD_Con_1.RC_RLSel_13[8] , \CPLD_Con_1.RC_RLSel_13[4] , + \CPLD_Con_1.RC_RLSel_13[7] , \CPLD_Con_1.RC_RLSel_13[15] , + \CPLD_Con_1.RC_RLSel_13[6] , \CPLD_Con_1.RC_RLSel_13[10] , + \CPLD_Con_1.RC_RLSel_13[5] , \CPLD_Con_1.RC_RLSel_13[9] , + i_rst_n_c_i_en, \CPLD_Con_1.PMU_OC_2_8[24] , + \CPLD_Con_1.RC_RLSel_13[14] , \CPLD_Con_1.RC_RLSel_13[13] , + \CPLD_Con_1.PMU_OC_4_8[30] , \CPLD_Con_1.PMU_OC_4_8[19] , + i_rst_n_c_i_rst, o_err_c, \CPLD_Con_1.DMM_en_22[15] , miso_shift31, + \o_PMU_OC_4_c[31] , \o_PMU_OC_4_c[30] , \o_PMU_OC_4_c[29] , + \o_PMU_OC_4_c[28] , \o_PMU_OC_4_c[27] , \o_PMU_OC_4_c[26] , + \o_PMU_OC_4_c[25] , \o_PMU_OC_4_c[24] , \o_PMU_OC_4_c[23] , + \o_PMU_OC_4_c[22] , \o_PMU_OC_4_c[21] , \o_PMU_OC_4_c[19] , + \o_PMU_OC_4_c[18] , \o_PMU_OC_4_c[17] , \o_PMU_OC_4_c[16] , + \o_PMU_OC_4_c[15] , \o_PMU_OC_4_c[14] , \o_PMU_OC_4_c[13] , + \o_PMU_OC_4_c[12] , \o_PMU_OC_4_c[11] , \o_PMU_OC_4_c[10] , + \o_PMU_OC_4_c[9] , \o_PMU_OC_4_c[8] , \o_PMU_OC_4_c[7] , + \o_PMU_OC_4_c[6] , \o_PMU_OC_4_c[3] , \o_PMU_OC_4_c[2] , + \o_PMU_OC_4_c[0] , \o_PMU_OC_3_c[31] , \o_PMU_OC_3_c[30] , + \o_PMU_OC_3_c[29] , \o_PMU_OC_3_c[28] , \o_PMU_OC_3_c[27] , + \o_PMU_OC_3_c[26] , \o_PMU_OC_3_c[25] , \o_PMU_OC_3_c[24] , + \o_PMU_OC_3_c[23] , \o_PMU_OC_3_c[22] , \o_PMU_OC_3_c[21] , + \o_PMU_OC_3_c[20] , \o_PMU_OC_3_c[19] , \o_PMU_OC_3_c[18] , + \o_PMU_OC_3_c[17] , \o_PMU_OC_3_c[16] , \o_PMU_OC_3_c[15] , + \o_PMU_OC_3_c[14] , \o_PMU_OC_3_c[13] , \o_PMU_OC_3_c[12] , + \o_PMU_OC_3_c[11] , \o_PMU_OC_3_c[10] , \o_PMU_OC_3_c[9] , + \o_PMU_OC_3_c[8] , \o_PMU_OC_3_c[6] , \o_PMU_OC_3_c[4] , + \o_PMU_OC_3_c[2] , \o_PMU_OC_3_c[0] , \o_PMU_OC_2_c[31] , + \o_PMU_OC_2_c[30] , \o_PMU_OC_2_c[29] , \o_PMU_OC_2_c[28] , + \o_PMU_OC_2_c[27] , \o_PMU_OC_2_c[26] , \o_PMU_OC_2_c[25] , + \o_PMU_OC_2_c[24] , \o_PMU_OC_2_c[23] , \o_PMU_OC_2_c[22] , + \o_PMU_OC_2_c[21] , \o_PMU_OC_2_c[20] , \o_PMU_OC_2_c[19] , + \o_PMU_OC_2_c[18] , \o_PMU_OC_2_c[17] , \o_PMU_OC_2_c[16] , + \o_PMU_OC_2_c[15] , \o_PMU_OC_2_c[14] , \o_PMU_OC_2_c[13] , + \o_PMU_OC_2_c[12] , \o_PMU_OC_2_c[11] , \o_PMU_OC_2_c[10] , + \o_PMU_OC_2_c[9] , \o_PMU_OC_2_c[8] , \o_PMU_OC_2_c[6] , + \o_PMU_OC_2_c[4] , \o_PMU_OC_2_c[2] , \o_PMU_OC_2_c[0] , + \o_PMU_OC_1_c[31] , \o_PMU_OC_1_c[30] , \o_PMU_OC_1_c[29] , + \o_PMU_OC_1_c[28] , \o_PMU_OC_1_c[27] , \o_PMU_OC_1_c[26] , + \o_PMU_OC_1_c[25] , \o_PMU_OC_1_c[24] , \o_PMU_OC_1_c[23] , + \o_PMU_OC_1_c[22] , \o_PMU_OC_1_c[21] , \o_PMU_OC_1_c[20] , + \o_PMU_OC_1_c[19] , \o_PMU_OC_1_c[18] , \o_PMU_OC_1_c[17] , + \o_PMU_OC_1_c[16] , \o_PMU_OC_1_c[15] , \o_PMU_OC_1_c[14] , + \o_PMU_OC_1_c[13] , \o_PMU_OC_1_c[12] , \o_PMU_OC_1_c[11] , + \o_PMU_OC_1_c[10] , \o_PMU_OC_1_c[9] , \o_PMU_OC_1_c[8] , + \o_PMU_OC_1_c[7] , \o_PMU_OC_1_c[6] , \o_PMU_OC_1_c[5] , + \o_PMU_OC_1_c[4] , \o_PMU_OC_1_c[3] , \o_PMU_OC_1_c[2] , + \o_PMU_OC_1_c[1] , \o_PMU_OC_1_c[0] , \o_RC_RLSel_c[17] , + \o_RC_RLSel_c[16] , \o_RC_RLSel_c[15] , \o_RC_RLSel_c[14] , + \o_RC_RLSel_c[13] , \o_RC_RLSel_c[12] , \o_RC_RLSel_c[11] , + \o_RC_RLSel_c[10] , \o_RC_RLSel_c[9] , \o_RC_RLSel_c[8] , + \o_RC_RLSel_c[7] , \o_RC_RLSel_c[6] , \o_RC_RLSel_c[5] , + \o_RC_RLSel_c[4] , \o_RC_RLSel_c[3] , \o_RC_RLSel_c[2] , + \o_RC_RLSel_c[1] , \o_RC_RLSel_c[0] , o_RC_T32_c, o_RC_T31_c, + o_RC_T30_c, o_RC_T29_c, o_RC_T28_c, o_RC_T27_c, o_IO_RC1_c, + \o_DMM_EN_c[18] , \o_DMM_EN_c[17] , \o_DMM_EN_c[16] , + \o_DMM_EN_c[15] , \o_DMM_EN_c[14] , \o_DMM_EN_c[13] , + \o_DMM_EN_c[12] , \o_DMM_EN_c[11] , \o_DMM_EN_c[10] , \o_DMM_EN_c[9] , + \o_DMM_EN_c[8] , \o_DMM_EN_c[7] , \o_DMM_EN_c[6] , \o_DMM_EN_c[5] , + \o_DMM_EN_c[4] , \o_DMM_EN_c[3] , \o_DMM_EN_c[2] , \o_DMM_EN_c[1] , + \o_DMM_EN_c[0] , i_cs_c, i_mosi_c, i_sclk_c, VCCI; + + SLICE_0 SLICE_0( .B1(i_rst_n_c), .A1(\CPLD_Con_1/RC_Tx_1_sqmuxa ), + .B0(i_rst_n_c), .A0(\BUS_Con_1.cs_sync[0] ), .DI0(i_rst_n_c_i_set), + .CLK(i_sys_clk_c), .F0(i_rst_n_c_i_set), .Q0(\BUS_Con_1.cs_sync_rep0[1] ), + .F1(\CPLD_Con_1.err_flag_1_sqmuxa )); + BUS_Con_1_SLICE_1 \BUS_Con_1/SLICE_1 ( .D1(\BUS_Con_1/N_244 ), + .C1(\BUS_Con_1/cs_sync[1] ), .B1(\BUS_Con_1/bit_cnt[1] ), + .A1(\BUS_Con_1/bit_cnt[0] ), .D0(\BUS_Con_1.sclk_sync[0] ), + .C0(\BUS_Con_1/sclk_sync[1] ), .B0(\BUS_Con_1/bit_cnt[0] ), + .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/bit_cnt_6[1] ), + .DI0(\BUS_Con_1/bit_cnt_6[0] ), + .LSR(\BUS_Con_1/bit_cnt_0_sqmuxa_1_i_a2_RNISVNVG ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/bit_cnt_6[0] ), .Q0(\BUS_Con_1/bit_cnt[0] ), + .F1(\BUS_Con_1/bit_cnt_6[1] ), .Q1(\BUS_Con_1/bit_cnt[1] )); + BUS_Con_1_SLICE_2 \BUS_Con_1/SLICE_2 ( .C1(\BUS_Con_1/un1_bit_cnt_9_c2 ), + .B1(\BUS_Con_1/bit_cnt[3] ), .A1(\BUS_Con_1/bit_cnt[2] ), + .B0(\BUS_Con_1/un1_bit_cnt_9_c2 ), .A0(\BUS_Con_1/bit_cnt[2] ), + .DI1(\BUS_Con_1/bit_cnt_6[3] ), .DI0(\BUS_Con_1/bit_cnt_6[2] ), + .LSR(\BUS_Con_1/bit_cnt_0_sqmuxa_1_i_a2_RNISVNVG ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/bit_cnt_6[2] ), .Q0(\BUS_Con_1/bit_cnt[2] ), + .F1(\BUS_Con_1/bit_cnt_6[3] ), .Q1(\BUS_Con_1/bit_cnt[3] )); + BUS_Con_1_SLICE_3 \BUS_Con_1/SLICE_3 ( .C1(\BUS_Con_1/un1_bit_cnt_9_c4 ), + .B1(\BUS_Con_1/bit_cnt[5] ), .A1(\BUS_Con_1/bit_cnt[4] ), + .D0(\BUS_Con_1/un1_bit_cnt_9_c2 ), .C0(\BUS_Con_1/bit_cnt[4] ), + .B0(\BUS_Con_1/bit_cnt[3] ), .A0(\BUS_Con_1/bit_cnt[2] ), + .DI1(\BUS_Con_1/bit_cnt_6[5] ), .DI0(\BUS_Con_1/bit_cnt_6[4] ), + .LSR(\BUS_Con_1/bit_cnt_0_sqmuxa_1_i_a2_RNISVNVG ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/bit_cnt_6[4] ), .Q0(\BUS_Con_1/bit_cnt[4] ), + .F1(\BUS_Con_1/bit_cnt_6[5] ), .Q1(\BUS_Con_1/bit_cnt[5] )); + BUS_Con_1_SLICE_5 \BUS_Con_1/SLICE_5 ( .D1(\BUS_Con_1/bit_cnt[5] ), + .C1(\BUS_Con_1/bit_cnt[3] ), .B1(\BUS_Con_1/bit_cnt[1] ), + .A1(\BUS_Con_1/bit_cnt[0] ), .D0(\BUS_Con_1.sclk_sync[0] ), + .C0(\BUS_Con_1/sclk_sync[1] ), .B0(\BUS_Con_1/data_readyc_2_0 ), + .A0(\BUS_Con_1/data_readyc_3 ), .DI0(\BUS_Con_1/data_readyc ), + .M1(\BUS_Con_1.cs_sync[0] ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/data_readyc ), .Q0(\BUS_Con_1/data_ready ), + .F1(\BUS_Con_1/data_readyc_2_0 ), .Q1(\BUS_Con_1/cs_sync[1] )); + BUS_Con_1_SLICE_6 \BUS_Con_1/SLICE_6 ( .C1(\BUS_Con_1/tx_buffer[1] ), + .B1(\BUS_Con_1/miso_shift[0] ), .A1(\BUS_Con_1/cs_sync[1] ), + .B0(\BUS_Con_1/tx_buffer[0] ), .A0(\BUS_Con_1/cs_sync[1] ), + .DI1(\BUS_Con_1/miso_shift_6[1] ), .DI0(\BUS_Con_1/miso_shift_6[0] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[0] ), + .Q0(\BUS_Con_1/miso_shift[0] ), .F1(\BUS_Con_1/miso_shift_6[1] ), + .Q1(\BUS_Con_1/miso_shift[1] )); + BUS_Con_1_SLICE_7 \BUS_Con_1/SLICE_7 ( .C1(\BUS_Con_1/tx_buffer[3] ), + .B1(\BUS_Con_1/miso_shift[2] ), .A1(\BUS_Con_1/cs_sync[1] ), + .C0(\BUS_Con_1/tx_buffer[2] ), .B0(\BUS_Con_1/miso_shift[1] ), + .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[3] ), + .DI0(\BUS_Con_1/miso_shift_6[2] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[2] ), + .Q0(\BUS_Con_1/miso_shift[2] ), .F1(\BUS_Con_1/miso_shift_6[3] ), + .Q1(\BUS_Con_1/miso_shift[3] )); + BUS_Con_1_SLICE_8 \BUS_Con_1/SLICE_8 ( .C1(\BUS_Con_1/tx_buffer[5] ), + .B1(\BUS_Con_1/miso_shift[4] ), .A1(\BUS_Con_1/cs_sync[1] ), + .C0(\BUS_Con_1/tx_buffer[4] ), .B0(\BUS_Con_1/miso_shift[3] ), + .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[5] ), + .DI0(\BUS_Con_1/miso_shift_6[4] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[4] ), + .Q0(\BUS_Con_1/miso_shift[4] ), .F1(\BUS_Con_1/miso_shift_6[5] ), + .Q1(\BUS_Con_1/miso_shift[5] )); + BUS_Con_1_SLICE_9 \BUS_Con_1/SLICE_9 ( .C1(\BUS_Con_1/tx_buffer[7] ), + .B1(\BUS_Con_1/miso_shift[6] ), .A1(\BUS_Con_1/cs_sync[1] ), + .C0(\BUS_Con_1/tx_buffer[6] ), .B0(\BUS_Con_1/miso_shift[5] ), + .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[7] ), + .DI0(\BUS_Con_1/miso_shift_6[6] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[6] ), + .Q0(\BUS_Con_1/miso_shift[6] ), .F1(\BUS_Con_1/miso_shift_6[7] ), + .Q1(\BUS_Con_1/miso_shift[7] )); + BUS_Con_1_SLICE_10 \BUS_Con_1/SLICE_10 ( .C1(\BUS_Con_1/tx_buffer[9] ), + .B1(\BUS_Con_1/miso_shift[8] ), .A1(\BUS_Con_1/cs_sync[1] ), + .C0(\BUS_Con_1/tx_buffer[8] ), .B0(\BUS_Con_1/miso_shift[7] ), + .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[9] ), + .DI0(\BUS_Con_1/miso_shift_6[8] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[8] ), + .Q0(\BUS_Con_1/miso_shift[8] ), .F1(\BUS_Con_1/miso_shift_6[9] ), + .Q1(\BUS_Con_1/miso_shift[9] )); + BUS_Con_1_SLICE_11 \BUS_Con_1/SLICE_11 ( .C1(\BUS_Con_1/tx_buffer[11] ), + .B1(\BUS_Con_1/miso_shift[10] ), .A1(\BUS_Con_1/cs_sync[1] ), + .C0(\BUS_Con_1/tx_buffer[10] ), .B0(\BUS_Con_1/miso_shift[9] ), + .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[11] ), + .DI0(\BUS_Con_1/miso_shift_6[10] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[10] ), + .Q0(\BUS_Con_1/miso_shift[10] ), .F1(\BUS_Con_1/miso_shift_6[11] ), + .Q1(\BUS_Con_1/miso_shift[11] )); + BUS_Con_1_SLICE_12 \BUS_Con_1/SLICE_12 ( .C1(\BUS_Con_1/tx_buffer[13] ), + .B1(\BUS_Con_1/miso_shift[12] ), .A1(\BUS_Con_1/cs_sync[1] ), + .C0(\BUS_Con_1/tx_buffer[12] ), .B0(\BUS_Con_1/miso_shift[11] ), + .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[13] ), + .DI0(\BUS_Con_1/miso_shift_6[12] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[12] ), + .Q0(\BUS_Con_1/miso_shift[12] ), .F1(\BUS_Con_1/miso_shift_6[13] ), + .Q1(\BUS_Con_1/miso_shift[13] )); + BUS_Con_1_SLICE_13 \BUS_Con_1/SLICE_13 ( .C1(\BUS_Con_1/tx_buffer[15] ), + .B1(\BUS_Con_1/miso_shift[14] ), .A1(\BUS_Con_1/cs_sync[1] ), + .C0(\BUS_Con_1/tx_buffer[14] ), .B0(\BUS_Con_1/miso_shift[13] ), + .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[15] ), + .DI0(\BUS_Con_1/miso_shift_6[14] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[14] ), + .Q0(\BUS_Con_1/miso_shift[14] ), .F1(\BUS_Con_1/miso_shift_6[15] ), + .Q1(\BUS_Con_1/miso_shift[15] )); + BUS_Con_1_SLICE_14 \BUS_Con_1/SLICE_14 ( .C1(\BUS_Con_1/tx_buffer[17] ), + .B1(\BUS_Con_1/miso_shift[16] ), .A1(\BUS_Con_1/cs_sync[1] ), + .C0(\BUS_Con_1/tx_buffer[16] ), .B0(\BUS_Con_1/miso_shift[15] ), + .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[17] ), + .DI0(\BUS_Con_1/miso_shift_6[16] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[16] ), + .Q0(\BUS_Con_1/miso_shift[16] ), .F1(\BUS_Con_1/miso_shift_6[17] ), + .Q1(\BUS_Con_1/miso_shift[17] )); + BUS_Con_1_SLICE_15 \BUS_Con_1/SLICE_15 ( .C1(\BUS_Con_1/tx_buffer[19] ), + .B1(\BUS_Con_1/miso_shift[18] ), .A1(\BUS_Con_1/cs_sync[1] ), + .C0(\BUS_Con_1/tx_buffer[18] ), .B0(\BUS_Con_1/miso_shift[17] ), + .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[19] ), + .DI0(\BUS_Con_1/miso_shift_6[18] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[18] ), + .Q0(\BUS_Con_1/miso_shift[18] ), .F1(\BUS_Con_1/miso_shift_6[19] ), + .Q1(\BUS_Con_1/miso_shift[19] )); + BUS_Con_1_SLICE_16 \BUS_Con_1/SLICE_16 ( .C1(\BUS_Con_1/tx_buffer[21] ), + .B1(\BUS_Con_1/miso_shift[20] ), .A1(\BUS_Con_1/cs_sync[1] ), + .C0(\BUS_Con_1/tx_buffer[20] ), .B0(\BUS_Con_1/miso_shift[19] ), + .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[21] ), + .DI0(\BUS_Con_1/miso_shift_6[20] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[20] ), + .Q0(\BUS_Con_1/miso_shift[20] ), .F1(\BUS_Con_1/miso_shift_6[21] ), + .Q1(\BUS_Con_1/miso_shift[21] )); + BUS_Con_1_SLICE_17 \BUS_Con_1/SLICE_17 ( .C1(\BUS_Con_1/tx_buffer[23] ), + .B1(\BUS_Con_1/miso_shift[22] ), .A1(\BUS_Con_1/cs_sync[1] ), + .C0(\BUS_Con_1/tx_buffer[22] ), .B0(\BUS_Con_1/miso_shift[21] ), + .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[23] ), + .DI0(\BUS_Con_1/miso_shift_6[22] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[22] ), + .Q0(\BUS_Con_1/miso_shift[22] ), .F1(\BUS_Con_1/miso_shift_6[23] ), + .Q1(\BUS_Con_1/miso_shift[23] )); + BUS_Con_1_SLICE_18 \BUS_Con_1/SLICE_18 ( .B1(\BUS_Con_1/miso_shift[24] ), + .A1(\BUS_Con_1/cs_sync[1] ), .B0(\BUS_Con_1/miso_shift[23] ), + .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[25] ), + .DI0(\BUS_Con_1/miso_shift_6[24] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[24] ), + .Q0(\BUS_Con_1/miso_shift[24] ), .F1(\BUS_Con_1/miso_shift_6[25] ), + .Q1(\BUS_Con_1/miso_shift[25] )); + BUS_Con_1_SLICE_19 \BUS_Con_1/SLICE_19 ( .B1(\BUS_Con_1/miso_shift[26] ), + .A1(\BUS_Con_1/cs_sync[1] ), .B0(\BUS_Con_1/miso_shift[25] ), + .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[27] ), + .DI0(\BUS_Con_1/miso_shift_6[26] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[26] ), + .Q0(\BUS_Con_1/miso_shift[26] ), .F1(\BUS_Con_1/miso_shift_6[27] ), + .Q1(\BUS_Con_1/miso_shift[27] )); + BUS_Con_1_SLICE_20 \BUS_Con_1/SLICE_20 ( .B1(\BUS_Con_1/miso_shift[28] ), + .A1(\BUS_Con_1/cs_sync[1] ), .B0(\BUS_Con_1/miso_shift[27] ), + .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[29] ), + .DI0(\BUS_Con_1/miso_shift_6[28] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[28] ), + .Q0(\BUS_Con_1/miso_shift[28] ), .F1(\BUS_Con_1/miso_shift_6[29] ), + .Q1(\BUS_Con_1/miso_shift[29] )); + BUS_Con_1_SLICE_21 \BUS_Con_1/SLICE_21 ( .D1(\BUS_Con_1/cs_sync[1] ), + .C1(\BUS_Con_1.cs_sync[0] ), .B1(\BUS_Con_1/bit_cnt[4] ), + .A1(\BUS_Con_1/bit_cnt[2] ), .B0(\BUS_Con_1/miso_shift[29] ), + .A0(\BUS_Con_1/cs_sync[1] ), .DI0(\BUS_Con_1/miso_shift_6[30] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[30] ), + .Q0(\BUS_Con_1/miso_shift[30] ), .F1(\BUS_Con_1/data_readyc_3 )); + BUS_Con_1_SLICE_40 \BUS_Con_1/SLICE_40 ( .D1(i_rst_n_c), + .C1(\BUS_Con_1/N_249 ), .B1(\BUS_Con_1/state[1] ), + .A1(\BUS_Con_1/state[0] ), .D0(reg_busy), .C0(i_rst_n_c), + .B0(\BUS_Con_1/state[0] ), .A0(\BUS_Con_1/m3_i_o2 ), + .DI1(\BUS_Con_1/state_nss[1] ), .DI0(\BUS_Con_1/state_nss[0] ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/state_nss[0] ), + .Q0(\BUS_Con_1/state[0] ), .F1(\BUS_Con_1/state_nss[1] ), + .Q1(\BUS_Con_1/state[1] )); + SLICE_62 SLICE_62( .C1(\DC_Con4[0] ), .B1(\DC_Con3[0] ), .A1(\DC_Con2[0] ), + .D0(\DC_Con4[0] ), .C0(\DC_Con3[0] ), .B0(\DC_Con2[0] ), .A0(\DC_Con1[0] ), + .DI0(\CPLD_Con_1/dc_t_2 ), .M1(\BUS_Con_1.mosi_sync[0] ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/dc_t_2 ), .Q0(\CPLD_Con_1/dc_t ), + .F1(\CPLD_Con_1/CO0 ), .Q1(\BUS_Con_1/mosi_sync[1] )); + CPLD_Con_1_SLICE_63 \CPLD_Con_1/SLICE_63 ( .D1(\CPLD_Con_1/N_6_0 ), + .C1(\CPLD_Con_1/CO0 ), .B1(\CPLD_Con_1/N_18_c1 ), + .A1(\CPLD_Con_1/N_18_0_c1 ), .D0(\CPLD_Con_1/N_6_0 ), + .C0(\CPLD_Con_1/CO0 ), .B0(\CPLD_Con_1/N_18_c1 ), + .A0(\CPLD_Con_1/N_18_0_c1 ), .DI1(\CPLD_Con_1/N_20 ), + .DI0(\CPLD_Con_1/N_19 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_19 ), .Q0(\CPLD_Con_1/en_t[1] ), .F1(\CPLD_Con_1/N_20 ), + .Q1(\CPLD_Con_1/en_t[2] )); + SLICE_64 SLICE_64( .C1(\freq1_relay[0] ), .B1(\CPLD_Con_1/m2 ), + .A1(\CPLD_Con_1/SUM0 ), .D0(\CPLD_Con_1/N_6_0 ), .C0(\CPLD_Con_1/CO0 ), + .B0(\CPLD_Con_1/N_18_c1 ), .A0(\CPLD_Con_1/N_18_0_c1 ), + .DI0(\CPLD_Con_1/N_21 ), .M1(\BUS_Con_1.sclk_sync[0] ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_21 ), .Q0(\CPLD_Con_1/en_t[3] ), + .F1(\CPLD_Con_1/N_18_0_c1 ), .Q1(\BUS_Con_1/sclk_sync[1] )); + CPLD_Con_1_SLICE_67 \CPLD_Con_1/SLICE_67 ( .D1(\freq4_relay[0] ), + .C1(\freq3_relay[0] ), .B1(\freq2_relay[0] ), .A1(\freq1_relay[0] ), + .D0(\freq4_relay[0] ), .C0(\freq3_relay[0] ), .B0(\freq2_relay[0] ), + .A0(\freq1_relay[0] ), .DI0(\CPLD_Con_1/freq_t_2 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/freq_t_2 ), .Q0(\CPLD_Con_1/freq_t ), + .F1(\CPLD_Con_1.io_RC_2 )); + CPLD_Reg_1_SLICE_74 \CPLD_Reg_1/SLICE_74 ( .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + .Q0(\CPLD_Reg_1.regtable[9]_fast[8] )); + CPLD_Reg_1_SLICE_75 \CPLD_Reg_1/SLICE_75 ( .D1(\reg_addr[6] ), + .C1(\reg_addr[5] ), .B1(\reg_addr[4] ), .A1(\CPLD_Reg_1/N_1167 ), + .D0(con_exec), .C0(cmd_valid), .B0(\CPLD_Reg_1/state[0] ), + .A0(\CPLD_Reg_1/err_flag8 ), .DI0(\CPLD_Reg_1/N_812 ), + .CE(\CPLD_Reg_1/un10_0 ), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/N_812 ), + .Q0(\CPLD_Reg_1/reg_err_flag ), .F1(\CPLD_Reg_1/err_flag8 )); + CPLD_Reg_1_SLICE_171 \CPLD_Reg_1/SLICE_171 ( .B1(o_con_done_c), + .A1(\CPLD_Reg_1/state[1] ), .D0(\w_data[23] ), .C0(o_con_done_c), + .B0(\CPLD_Reg_1/state[1] ), .A0(\CPLD_Reg_1/regtable[1][23] ), + .DI0(\CPLD_Reg_1/N_1057_i ), .CE(\CPLD_Reg_1/un12_i ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/N_1057_i ), .Q0(\CPLD_Reg_1/regtable[1][23] ), + .F1(\CPLD_Reg_1/N_22 )); + CPLD_Reg_1_SLICE_212 \CPLD_Reg_1/SLICE_212 ( .M1(\w_data[15] ), + .M0(\w_data[16] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), + .CLK(i_sys_clk_c), .Q0(\CPLD_Reg_1/regtable[9][16] ), + .Q1(\CPLD_Reg_1/regtable[9][15] )); + CPLD_Reg_1_SLICE_213 \CPLD_Reg_1/SLICE_213 ( .D1(\CPLD_Reg_1/state[0] ), + .C1(\CPLD_Reg_1/N_25 ), .B1(\CPLD_Reg_1/N_22 ), .A1(\CPLD_Reg_1/N_21 ), + .D0(cmd_valid), .C0(\CPLD_Reg_1/state[0] ), .B0(\CPLD_Reg_1/N_22 ), + .A0(\CPLD_Reg_1/N_21 ), .DI1(\CPLD_Reg_1/state_ns[1] ), + .DI0(\CPLD_Reg_1/state_ns[0] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/state_ns[0] ), .Q0(\CPLD_Reg_1/state[0] ), + .F1(\CPLD_Reg_1/state_ns[1] ), .Q1(\CPLD_Reg_1/state[1] )); + CPLD_Reg_1_SLICE_248 \CPLD_Reg_1/SLICE_248 ( .M1(\w_data[20] ), + .M0(\w_data[21] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), + .CLK(i_sys_clk_c), .Q0(\DC_Con4[21] ), .Q1(\DC_Con4[20] )); + CPLD_Reg_1_SLICE_249 \CPLD_Reg_1/SLICE_249 ( .M1(\w_data[22] ), + .M0(\w_data[23] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), + .CLK(i_sys_clk_c), .Q0(\DC_Con4[23] ), .Q1(\DC_Con4[22] )); + BUS_Con_1_SLICE_250 \BUS_Con_1/SLICE_250 ( + .D1(\BUS_Con_1/err_flag_1_sqmuxa_0_a2_0_0 ), .C1(\BUS_Con_1.cs_sync[0] ), + .B1(\BUS_Con_1/bit_cnt[4] ), .A1(\BUS_Con_1/bit_cnt[2] ), + .D0(\BUS_Con_1/cs_sync[1] ), .C0(\BUS_Con_1.sclk_sync[0] ), + .B0(\BUS_Con_1/sclk_sync[1] ), .A0(\BUS_Con_1/N_241 ), + .DI0(\BUS_Con_1/N_243_i ), .CE(\BUS_Con_1/N_238_i ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_243_i ), .Q0(bus_err_flag), + .F1(\BUS_Con_1/N_241 )); + BUS_Con_1_SLICE_251 \BUS_Con_1/SLICE_251 ( .D1(\BUS_Con_1/data_ready ), + .C1(reg_busy), .B1(\BUS_Con_1/state[0] ), .A1(\BUS_Con_1/state[1] ), + .D0(reg_busy), .C0(\BUS_Con_1/state[1] ), .B0(\BUS_Con_1/state[0] ), + .A0(\BUS_Con_1/data_ready ), .DI0(\BUS_Con_1/N_34_i_0 ), + .CE(\BUS_Con_1/m3_i_o2 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/N_34_i_0 ), .Q0(cmd_valid), .F1(\BUS_Con_1/m3_i_o2 )); + CPLD_Reg_1_SLICE_252 \CPLD_Reg_1/SLICE_252 ( .B1(con_exec), + .A1(\CPLD_Reg_1/state[1] ), .D0(o_con_done_c), .C0(\CPLD_Reg_1/state[1] ), + .B0(con_exec), .A0(\w_data[0] ), .DI0(\CPLD_Reg_1/regtable[1]_RNO[0] ), + .CE(\CPLD_Reg_1/un12_i ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[1]_RNO[0] ), .Q0(con_exec), + .F1(\CPLD_Reg_1/N_21 )); + CPLD_Reg_1_SLICE_253 \CPLD_Reg_1/SLICE_253 ( .M0(\CPLD_Reg_1/state[0] ), + .CE(\CPLD_Reg_1/un11_0 ), .CLK(i_sys_clk_c), .Q0(con_rvalid)); + CPLD_Con_1_SLICE_254 \CPLD_Con_1/SLICE_254 ( + .D1(\CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNILT4CU4 ), .C1(\CPLD_Con_1/g0_2 ), + .B1(\CPLD_Con_1/err_flag_0_sqmuxa_0_0 ), .A1(\CPLD_Con_1/err_flag25 ), + .C0(\CPLD_Con_1/un1_err_flag_0_sqmuxa ), .B0(\CPLD_Con_1/g0_8_1_0 ), + .A0(\CPLD_Con_1/RC_Tx_0_sqmuxa ), .DI0(\CPLD_Con_1/un1_RC_Tx_0_sqmuxa_1 ), + .CE(\CPLD_Con_1/err_flag_RNO ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/un1_RC_Tx_0_sqmuxa_1 ), .Q0(cpld_err_flag), + .F1(\CPLD_Con_1/un1_err_flag_0_sqmuxa )); + CPLD_Con_1_SLICE_278 \CPLD_Con_1/SLICE_278 ( .D1(\o_PMU_OC_2_c[3] ), + .C1(\CPLD_Con_1/un1_exec_flag_3_0_0_RNISFCLD4 ), .B1(\CPLD_Con_1/N_103 ), + .A1(\CPLD_Con_1.un1_exec_flag_3_i ), .D0(\o_PMU_OC_2_c[1] ), + .C0(\CPLD_Con_1/un1_exec_flag_3_0_0_RNISFCLD4 ), + .B0(\CPLD_Con_1.un1_exec_flag_3_i ), .A0(\CPLD_Con_1/PMU_OC_2_8[1] ), + .DI1(\CPLD_Con_1/PMU_OC_2d_0[3] ), .DI0(\CPLD_Con_1/PMU_OC_2d_0[1] ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_2d_0[1] ), + .Q0(\o_PMU_OC_2_c[1] ), .F1(\CPLD_Con_1/PMU_OC_2d_0[3] ), + .Q1(\o_PMU_OC_2_c[3] )); + CPLD_Con_1_SLICE_279 \CPLD_Con_1/SLICE_279 ( .D1(\o_PMU_OC_2_c[7] ), + .C1(\CPLD_Con_1/un1_exec_flag_3_0_0_RNISFCLD4 ), .B1(\CPLD_Con_1/N_64 ), + .A1(\CPLD_Con_1.un1_exec_flag_3_i ), .D0(\o_PMU_OC_2_c[5] ), + .C0(\CPLD_Con_1/un1_exec_flag_3_0_0_RNISFCLD4 ), .B0(\CPLD_Con_1/N_63 ), + .A0(\CPLD_Con_1.un1_exec_flag_3_i ), .DI1(\CPLD_Con_1/PMU_OC_2d_0[7] ), + .DI0(\CPLD_Con_1/PMU_OC_2d_0[5] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/PMU_OC_2d_0[5] ), .Q0(\o_PMU_OC_2_c[5] ), + .F1(\CPLD_Con_1/PMU_OC_2d_0[7] ), .Q1(\o_PMU_OC_2_c[7] )); + CPLD_Con_1_SLICE_280 \CPLD_Con_1/SLICE_280 ( .D1(\o_PMU_OC_3_c[3] ), + .C1(\CPLD_Con_1/un1_exec_flag_2_0_0_RNI3RHOG1 ), .B1(\CPLD_Con_1/N_144 ), + .A1(\CPLD_Con_1.un1_exec_flag_2_i ), .D0(\o_PMU_OC_3_c[1] ), + .C0(\CPLD_Con_1/un1_exec_flag_2_0_0_RNI3RHOG1 ), + .B0(\CPLD_Con_1.un1_exec_flag_2_i ), .A0(\CPLD_Con_1/PMU_OC_3_8[1] ), + .DI1(\CPLD_Con_1/PMU_OC_3d_0[3] ), .DI0(\CPLD_Con_1/PMU_OC_3d_0[1] ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_3d_0[1] ), + .Q0(\o_PMU_OC_3_c[1] ), .F1(\CPLD_Con_1/PMU_OC_3d_0[3] ), + .Q1(\o_PMU_OC_3_c[3] )); + CPLD_Con_1_SLICE_281 \CPLD_Con_1/SLICE_281 ( .D1(\o_PMU_OC_3_c[7] ), + .C1(\CPLD_Con_1/un1_exec_flag_2_0_0_RNI3RHOG1 ), .B1(\CPLD_Con_1/N_148 ), + .A1(\CPLD_Con_1.un1_exec_flag_2_i ), .D0(\o_PMU_OC_3_c[5] ), + .C0(\CPLD_Con_1/un1_exec_flag_2_0_0_RNI3RHOG1 ), .B0(\CPLD_Con_1/N_147 ), + .A0(\CPLD_Con_1.un1_exec_flag_2_i ), .DI1(\CPLD_Con_1/PMU_OC_3d_0[7] ), + .DI0(\CPLD_Con_1/PMU_OC_3d_0[5] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/PMU_OC_3d_0[5] ), .Q0(\o_PMU_OC_3_c[5] ), + .F1(\CPLD_Con_1/PMU_OC_3d_0[7] ), .Q1(\o_PMU_OC_3_c[7] )); + CPLD_Con_1_SLICE_282 \CPLD_Con_1/SLICE_282 ( .D1(\o_PMU_OC_4_c[4] ), + .C1(\CPLD_Con_1/PMU_OC_4_8_0_a2_RNIL1I393[20] ), .B1(N_195), + .A1(\CPLD_Con_1.un1_exec_flag_8_i ), .D0(\o_PMU_OC_4_c[1] ), + .C0(\CPLD_Con_1/PMU_OC_4_8_0_a2_RNIL1I393[20] ), .B0(\CPLD_Con_1/N_198 ), + .A0(\CPLD_Con_1.un1_exec_flag_8_i ), .DI1(\CPLD_Con_1/PMU_OC_4d_0[4] ), + .DI0(\CPLD_Con_1/PMU_OC_4d_0[1] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/PMU_OC_4d_0[1] ), .Q0(\o_PMU_OC_4_c[1] ), + .F1(\CPLD_Con_1/PMU_OC_4d_0[4] ), .Q1(\o_PMU_OC_4_c[4] )); + CPLD_Con_1_SLICE_283 \CPLD_Con_1/SLICE_283 ( .D1(\o_PMU_OC_4_c[20] ), + .C1(\CPLD_Con_1/PMU_OC_4_8_0_a2_RNIL1I393[20] ), .B1(N_193), + .A1(\CPLD_Con_1.un1_exec_flag_8_i ), .D0(\o_PMU_OC_4_c[5] ), + .C0(\CPLD_Con_1/PMU_OC_4_8_0_a2_RNIL1I393[20] ), .B0(N_194), + .A0(\CPLD_Con_1.un1_exec_flag_8_i ), .DI1(\CPLD_Con_1/PMU_OC_4d_0[20] ), + .DI0(\CPLD_Con_1/PMU_OC_4d_0[5] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/PMU_OC_4d_0[5] ), .Q0(\o_PMU_OC_4_c[5] ), + .F1(\CPLD_Con_1/PMU_OC_4d_0[20] ), .Q1(\o_PMU_OC_4_c[20] )); + CPLD_Con_1_SLICE_284 \CPLD_Con_1/SLICE_284 ( .D1(\DC_Con4[22] ), + .C1(\DC_Con3[22] ), .B1(\CPLD_Con_1/dc_slot_flag[3] ), + .A1(\CPLD_Con_1/dc_slot_flag[2] ), .D0(\CPLD_Con_1/dc_slot_flag[1] ), + .C0(\CPLD_Con_1/dc_slot_flag[0] ), .B0(\CPLD_Con_1/m9_0_1_tz ), + .A0(\CPLD_Con_1/m9_0_0 ), .DI0(\CPLD_Con_1/RC_VISel_6 ), + .CE(\CPLD_Con_1/g0_8_1_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/RC_VISel_6 ), .Q0(o_RC_ISel_c), + .F1(\CPLD_Con_1/m9_0_1_tz )); + CPLD_Reg_1_SLICE_286 \CPLD_Reg_1/SLICE_286 ( .C1(reg_addr_3_rep1), + .B1(\DC_Con1[0] ), .A1(\CPLD_Reg_1/regtable[14][0] ), .C0(reg_addr_3_rep2), + .B0(\freq1_relay[0] ), .A0(\CPLD_Reg_1/regtable[10][0] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[0] ), .M1(\reg_addr[1] ), + .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_350 ), .FXA(\CPLD_Reg_1/N_326 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_230 ), .Q1(\r_data[0] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[0] )); + CPLD_Reg_1_SLICE_287 \CPLD_Reg_1/SLICE_287 ( .C1(reg_addr_3_rep1), + .B1(\DC_Con1[1] ), .A1(\CPLD_Reg_1/regtable[14][1] ), .C0(reg_addr_3_rep2), + .B0(\freq1_relay[1] ), .A0(\CPLD_Reg_1/regtable[10][1] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[1] ), .M1(\reg_addr[1] ), + .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_351 ), .FXA(\CPLD_Reg_1/N_327 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_231 ), .Q1(\r_data[1] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[1] )); + CPLD_Reg_1_SLICE_288 \CPLD_Reg_1/SLICE_288 ( .C1(reg_addr_3_rep1), + .B1(\DC_Con1[2] ), .A1(\CPLD_Reg_1/regtable[14][2] ), .C0(reg_addr_3_rep2), + .B0(\freq1_relay[2] ), .A0(\CPLD_Reg_1/regtable[10][2] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[2] ), .M1(\reg_addr[1] ), + .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_352 ), .FXA(\CPLD_Reg_1/N_328 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_232 ), .Q1(\r_data[2] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[2] )); + CPLD_Reg_1_SLICE_289 \CPLD_Reg_1/SLICE_289 ( .C1(reg_addr_3_rep1), + .B1(\DC_Con1[3] ), .A1(\CPLD_Reg_1/regtable[14][3] ), .C0(reg_addr_3_rep2), + .B0(\freq1_relay[3] ), .A0(\CPLD_Reg_1/regtable[10][3] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[3] ), .M1(\reg_addr[1] ), + .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_353 ), .FXA(\CPLD_Reg_1/N_329 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_233 ), .Q1(\r_data[3] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[3] )); + CPLD_Reg_1_SLICE_290 \CPLD_Reg_1/SLICE_290 ( .C1(reg_addr_3_rep1), + .B1(\DC_Con1[4] ), .A1(\CPLD_Reg_1/regtable[14][4] ), .C0(reg_addr_3_rep2), + .B0(\freq1_relay[4] ), .A0(\CPLD_Reg_1/regtable[10][4] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[4] ), .M1(\reg_addr[1] ), + .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_354 ), .FXA(\CPLD_Reg_1/N_330 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_234 ), .Q1(\r_data[4] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[4] )); + CPLD_Reg_1_SLICE_291 \CPLD_Reg_1/SLICE_291 ( .C1(reg_addr_3_rep1), + .B1(\DC_Con1[5] ), .A1(\CPLD_Reg_1/regtable[14][5] ), .C0(reg_addr_3_rep2), + .B0(\freq1_relay[5] ), .A0(\CPLD_Reg_1/regtable[10][5] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[5] ), .M1(\reg_addr[1] ), + .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_355 ), .FXA(\CPLD_Reg_1/N_331 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_235 ), .Q1(\r_data[5] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[5] )); + CPLD_Reg_1_SLICE_292 \CPLD_Reg_1/SLICE_292 ( .C1(reg_addr_3_rep1), + .B1(\DC_Con1[6] ), .A1(\CPLD_Reg_1/regtable[14][6] ), .C0(reg_addr_3_rep2), + .B0(\freq1_relay[6] ), .A0(\CPLD_Reg_1/regtable[10][6] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[6] ), .M1(\reg_addr[1] ), + .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_356 ), .FXA(\CPLD_Reg_1/N_332 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_236 ), .Q1(\r_data[6] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[6] )); + CPLD_Reg_1_SLICE_293 \CPLD_Reg_1/SLICE_293 ( .C1(reg_addr_3_rep1), + .B1(\DC_Con1[7] ), .A1(\CPLD_Reg_1/regtable[14][7] ), .C0(reg_addr_3_rep2), + .B0(\freq1_relay[7] ), .A0(\CPLD_Reg_1/regtable[10][7] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[7] ), .M1(\reg_addr[1] ), + .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_357 ), .FXA(\CPLD_Reg_1/N_333 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_237 ), .Q1(\r_data[7] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[7] )); + CPLD_Reg_1_SLICE_294 \CPLD_Reg_1/SLICE_294 ( .C1(reg_addr_3_rep1), + .B1(\DC_Con1[8] ), .A1(\CPLD_Reg_1/regtable[14][8] ), .C0(\reg_addr[3] ), + .B0(\freq1_relay[8] ), .A0(\CPLD_Reg_1/regtable[10][8] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[8] ), .M1(\reg_addr[1] ), + .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_358 ), .FXA(\CPLD_Reg_1/N_334 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_238 ), .Q1(\r_data[8] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[8] )); + CPLD_Reg_1_SLICE_295 \CPLD_Reg_1/SLICE_295 ( .C1(reg_addr_3_rep1), + .B1(\DC_Con1[9] ), .A1(\CPLD_Reg_1/regtable[14][9] ), .C0(\reg_addr[3] ), + .B0(\freq1_relay[9] ), .A0(\CPLD_Reg_1/regtable[10][9] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[9] ), .M1(\reg_addr[1] ), + .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_359 ), .FXA(\CPLD_Reg_1/N_335 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_239 ), .Q1(\r_data[9] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[9] )); + CPLD_Reg_1_SLICE_296 \CPLD_Reg_1/SLICE_296 ( .C1(reg_addr_3_rep2), + .B1(\CPLD_Reg_1/regtable[14][10] ), .A1(\CPLD_Reg_1/regtable[6][10] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][10] ), + .A0(\CPLD_Reg_1/regtable[2][10] ), .DI1(\CPLD_Reg_1/rdata_reg_2[10] ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_118 ), + .FXA(\CPLD_Reg_1/N_336 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1234 ), .Q1(\r_data[10] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[10] )); + CPLD_Reg_1_SLICE_297 \CPLD_Reg_1/SLICE_297 ( .C1(reg_addr_3_rep2), + .B1(\CPLD_Reg_1/regtable[14][11] ), .A1(\CPLD_Reg_1/regtable[6][11] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][11] ), + .A0(\CPLD_Reg_1/regtable[2][11] ), .DI1(\CPLD_Reg_1/rdata_reg_2[11] ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_1246 ), + .FXA(\CPLD_Reg_1/N_337 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1235 ), .Q1(\r_data[11] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[11] )); + CPLD_Reg_1_SLICE_298 \CPLD_Reg_1/SLICE_298 ( .C1(reg_addr_3_rep2), + .B1(\CPLD_Reg_1/regtable[14][12] ), .A1(\CPLD_Reg_1/regtable[6][12] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][12] ), + .A0(\CPLD_Reg_1/regtable[2][12] ), .DI1(\CPLD_Reg_1/rdata_reg_2[12] ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_1245 ), + .FXA(\CPLD_Reg_1/N_338 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1236 ), .Q1(\r_data[12] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[12] )); + CPLD_Reg_1_SLICE_299 \CPLD_Reg_1/SLICE_299 ( .C1(reg_addr_3_rep2), + .B1(\CPLD_Reg_1/regtable[14][13] ), .A1(\CPLD_Reg_1/regtable[6][13] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][13] ), + .A0(\CPLD_Reg_1/regtable[2][13] ), .DI1(\CPLD_Reg_1/rdata_reg_2[13] ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_1244 ), + .FXA(\CPLD_Reg_1/N_339 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1237 ), .Q1(\r_data[13] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[13] )); + CPLD_Reg_1_SLICE_300 \CPLD_Reg_1/SLICE_300 ( .C1(reg_addr_3_rep2), + .B1(\CPLD_Reg_1/regtable[14][14] ), .A1(\CPLD_Reg_1/regtable[6][14] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][14] ), + .A0(\CPLD_Reg_1/regtable[2][14] ), .DI1(\CPLD_Reg_1/rdata_reg_2[14] ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_1243 ), + .FXA(\CPLD_Reg_1/N_340 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1238 ), .Q1(\r_data[14] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[14] )); + CPLD_Reg_1_SLICE_301 \CPLD_Reg_1/SLICE_301 ( .C1(reg_addr_3_rep2), + .B1(\CPLD_Reg_1/regtable[14][15] ), .A1(\CPLD_Reg_1/regtable[6][15] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][15] ), + .A0(\CPLD_Reg_1/regtable[2][15] ), .DI1(\CPLD_Reg_1/rdata_reg_2[15] ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_1242 ), + .FXA(\CPLD_Reg_1/N_341 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1239 ), .Q1(\r_data[15] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[15] )); + CPLD_Reg_1_SLICE_302 \CPLD_Reg_1/SLICE_302 ( .C1(reg_addr_3_rep2), + .B1(\CPLD_Reg_1/regtable[14][16] ), .A1(\CPLD_Reg_1/regtable[6][16] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][16] ), + .A0(\CPLD_Reg_1/regtable[2][16] ), .DI1(\CPLD_Reg_1/rdata_reg_2[16] ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_1241 ), + .FXA(\CPLD_Reg_1/N_342 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1240 ), .Q1(\r_data[16] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[16] )); + CPLD_Reg_1_SLICE_303 \CPLD_Reg_1/SLICE_303 ( .C1(reg_addr_3_rep1), + .B1(\DC_Con1[17] ), .A1(\CPLD_Reg_1/regtable[14][17] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][17] ), .A0(\CPLD_Reg_1/regtable[2][17] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[17] ), .M1(\reg_addr[1] ), + .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_367 ), .FXA(\CPLD_Reg_1/N_343 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_247 ), .Q1(\r_data[17] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[17] )); + CPLD_Reg_1_SLICE_304 \CPLD_Reg_1/SLICE_304 ( .C1(reg_addr_3_rep1), + .B1(\DC_Con1[18] ), .A1(\CPLD_Reg_1/regtable[14][18] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][18] ), .A0(\CPLD_Reg_1/regtable[2][18] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[18] ), .M1(\reg_addr[1] ), + .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_368 ), .FXA(\CPLD_Reg_1/N_344 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_248 ), .Q1(\r_data[18] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[18] )); + CPLD_Reg_1_SLICE_305 \CPLD_Reg_1/SLICE_305 ( .C1(reg_addr_3_rep1), + .B1(\DC_Con1[19] ), .A1(\CPLD_Reg_1/regtable[14][19] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][19] ), .A0(\CPLD_Reg_1/regtable[2][19] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[19] ), .M1(\reg_addr[1] ), + .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_369 ), .FXA(\CPLD_Reg_1/N_345 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_249 ), .Q1(\r_data[19] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[19] )); + CPLD_Reg_1_SLICE_306 \CPLD_Reg_1/SLICE_306 ( .C1(reg_addr_3_rep1), + .B1(\DC_Con1[20] ), .A1(\CPLD_Reg_1/regtable[14][20] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][20] ), .A0(\CPLD_Reg_1/regtable[2][20] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[20] ), .M1(\reg_addr[1] ), + .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_370 ), .FXA(\CPLD_Reg_1/N_346 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_250 ), .Q1(\r_data[20] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[20] )); + CPLD_Reg_1_SLICE_307 \CPLD_Reg_1/SLICE_307 ( .C1(reg_addr_3_rep1), + .B1(\DC_Con1[21] ), .A1(\CPLD_Reg_1/regtable[14][21] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][21] ), .A0(\CPLD_Reg_1/regtable[2][21] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[21] ), .M1(\reg_addr[1] ), + .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_371 ), .FXA(\CPLD_Reg_1/N_347 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_251 ), .Q1(\r_data[21] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[21] )); + CPLD_Reg_1_SLICE_308 \CPLD_Reg_1/SLICE_308 ( .C1(reg_addr_3_rep1), + .B1(\DC_Con1[22] ), .A1(\CPLD_Reg_1/regtable[14][22] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][22] ), .A0(\CPLD_Reg_1/regtable[2][22] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[22] ), .M1(\reg_addr[1] ), + .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_372 ), .FXA(\CPLD_Reg_1/N_348 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_252 ), .Q1(\r_data[22] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[22] )); + CPLD_Reg_1_SLICE_309 \CPLD_Reg_1/SLICE_309 ( .C1(reg_addr_3_rep1), + .B1(\DC_Con1[23] ), .A1(\CPLD_Reg_1/regtable[14][23] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][23] ), .A0(\CPLD_Reg_1/regtable[2][23] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[23] ), .M1(\reg_addr[1] ), + .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_373 ), .FXA(\CPLD_Reg_1/N_349 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_253 ), .Q1(\r_data[23] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[23] )); + BUS_Con_1_SLICE_311 \BUS_Con_1/SLICE_311 ( .M1(\BUS_Con_1/recv_reg[25] ), + .M0(\BUS_Con_1/recv_reg[26] ), .CE(\BUS_Con_1/N_237_i ), + .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), + .Q0(\reg_addr[2] ), .Q1(\reg_addr[1] )); + BUS_Con_1_SLICE_312 \BUS_Con_1/SLICE_312 ( .M1(\BUS_Con_1/recv_reg[27] ), + .M0(\BUS_Con_1/recv_reg[28] ), .CE(\BUS_Con_1/N_237_i ), + .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), + .Q0(\reg_addr[4] ), .Q1(\reg_addr[3] )); + BUS_Con_1_SLICE_313 \BUS_Con_1/SLICE_313 ( .M1(\BUS_Con_1/recv_reg[29] ), + .M0(\BUS_Con_1/recv_reg[30] ), .CE(\BUS_Con_1/N_237_i ), + .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), + .Q0(\reg_addr[6] ), .Q1(\reg_addr[5] )); + CPLD_Reg_1_SLICE_319 \CPLD_Reg_1/SLICE_319 ( .B1(con_exec), .A1(cmd_valid), + .D0(o_con_done_c), .C0(\CPLD_Reg_1/state[1] ), .B0(\CPLD_Reg_1/state[0] ), + .A0(\CPLD_Reg_1/busy_flag_1_i_a3_0_0 ), .DI0(\CPLD_Reg_1/N_43_i ), + .CE(\CPLD_Reg_1/state_6_d_i ), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/N_43_i ), + .Q0(reg_busy), .F1(\CPLD_Reg_1/busy_flag_1_i_a3_0_0 )); + BUS_Con_1_SLICE_320 \BUS_Con_1/SLICE_320 ( .M1(\BUS_Con_1/recv_reg[27] ), + .M0(\BUS_Con_1/recv_reg[0] ), .CE(\BUS_Con_1/N_237_i ), + .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), + .Q0(\w_data[0] ), .Q1(\reg_addr_fast[3] )); + BUS_Con_1_SLICE_321 \BUS_Con_1/SLICE_321 ( .M1(\BUS_Con_1/recv_reg[1] ), + .M0(\BUS_Con_1/recv_reg[2] ), .CE(\BUS_Con_1/N_237_i ), + .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), + .Q0(\w_data[2] ), .Q1(\w_data[1] )); + BUS_Con_1_SLICE_322 \BUS_Con_1/SLICE_322 ( .M1(\BUS_Con_1/recv_reg[3] ), + .M0(\BUS_Con_1/recv_reg[4] ), .CE(\BUS_Con_1/N_237_i ), + .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), + .Q0(\w_data[4] ), .Q1(\w_data[3] )); + BUS_Con_1_SLICE_323 \BUS_Con_1/SLICE_323 ( .M1(\BUS_Con_1/recv_reg[5] ), + .M0(\BUS_Con_1/recv_reg[6] ), .CE(\BUS_Con_1/N_237_i ), + .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), + .Q0(\w_data[6] ), .Q1(\w_data[5] )); + BUS_Con_1_SLICE_324 \BUS_Con_1/SLICE_324 ( .M1(\BUS_Con_1/recv_reg[7] ), + .M0(\BUS_Con_1/recv_reg[8] ), .CE(\BUS_Con_1/N_237_i ), + .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), + .Q0(\w_data[8] ), .Q1(\w_data[7] )); + BUS_Con_1_SLICE_326 \BUS_Con_1/SLICE_326 ( .B0(\BUS_Con_1/state[1] ), + .A0(\BUS_Con_1/state[0] ), .M1(\BUS_Con_1/recv_reg[13] ), + .M0(\BUS_Con_1/recv_reg[12] ), .CE(\BUS_Con_1/N_237_i ), + .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), + .F0(o_wready_c), .Q0(\w_data[12] ), .Q1(\w_data[13] )); + SLICE_327 SLICE_327( .C1(\reg_addr[6] ), .B1(\reg_addr[5] ), + .A1(\reg_addr[4] ), .A0(o_RC_ISel_c), .M1(\BUS_Con_1/recv_reg[15] ), + .M0(\BUS_Con_1/recv_reg[14] ), .CE(\BUS_Con_1/N_237_i ), + .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), + .F0(o_RC_ISel_c_i), .Q0(\w_data[14] ), + .F1(\CPLD_Reg_1/un34_regtable_5[1] ), .Q1(\w_data[15] )); + SLICE_328 SLICE_328( .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), .C0(\DC_Con4[3] ), + .B0(\DC_Con4[2] ), .A0(\CPLD_Reg_1.regtable[9]_fast[4] ), + .M1(\BUS_Con_1/recv_reg[17] ), .M0(\BUS_Con_1/recv_reg[16] ), + .CE(\BUS_Con_1/N_237_i ), + .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/g0_19_1 ), .Q0(\w_data[16] ), + .F1(\CPLD_Con_1/g0_21_N_3L3 ), .Q1(\w_data[17] )); + SLICE_329 SLICE_329( .B1(\CPLD_Reg_1.regtable[8]_fast[6] ), + .A1(\CPLD_Reg_1.regtable[8]_fast[5] ), .B0(\freq1_relay[2] ), + .A0(\freq1_relay[1] ), .M1(\BUS_Con_1/recv_reg[19] ), + .M0(\BUS_Con_1/recv_reg[18] ), .CE(\BUS_Con_1/N_237_i ), + .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/OC_x0112lto2_0 ), .Q0(\w_data[18] ), + .F1(\CPLD_Con_1/g0_3_1_N_2L1 ), .Q1(\w_data[19] )); + SLICE_330 SLICE_330( .B1(\freq1_relay[9] ), .A1(\freq1_relay[8] ), + .B0(\DC_Con2[20] ), .A0(\DC_Con2[19] ), .M1(\BUS_Con_1/recv_reg[21] ), + .M0(\BUS_Con_1/recv_reg[20] ), .CE(\BUS_Con_1/N_237_i ), + .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_51 ), .Q0(\w_data[20] ), + .F1(\CPLD_Con_1/OC_x0112lto8_0 ), .Q1(\w_data[21] )); + SLICE_331 SLICE_331( .B1(\DC_Con4[19] ), + .A1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), .B0(con_exec), + .A0(\CPLD_Con_1.exec_flag ), .M1(\BUS_Con_1/recv_reg[23] ), + .M0(\BUS_Con_1/recv_reg[22] ), .CE(\BUS_Con_1/N_237_i ), + .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/err_flag39 ), .Q0(\w_data[22] ), .F1(\CPLD_Con_1/N_165 ), + .Q1(\w_data[23] )); + SLICE_332 SLICE_332( .C1(\freq2_relay[3] ), .B1(\freq2_relay[2] ), + .A1(\freq2_relay[1] ), .D0(\CPLD_Con_1/N_100 ), .C0(\CPLD_Con_1/N_96 ), + .B0(\DC_Con2[6] ), .A0(\DC_Con2[5] ), .M1(\BUS_Con_1/recv_reg[24] ), + .M0(\BUS_Con_1/wr_out_6 ), .CE(\BUS_Con_1/N_237_i ), + .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_2_8[21] ), .Q0(wr_flag), + .F1(\CPLD_Con_1/OC_x0126lt3 ), .Q1(\reg_addr[0] )); + CPLD_Con_1_RC_VISel_6_m9_0_0_SLICE_333 + \CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333 ( .C1(\CPLD_Con_1/m9_0_a5_1_1 ), + .B1(\DC_Con1[22] ), .A1(\CPLD_Con_1/dc_slot_flag[2] ), + .D0(\CPLD_Con_1/dc_slot_flag[1] ), .C0(\DC_Con2[22] ), + .B0(\CPLD_Con_1/dc_slot_flag[2] ), .A0(\CPLD_Con_1/dc_slot_flag[3] ), + .M0(\CPLD_Con_1/dc_slot_flag[0] ), .OFX0(\CPLD_Con_1/m9_0_0 )); + CPLD_Con_1_DMM_en_22_2__SLICE_334 \CPLD_Con_1/DMM_en_22[2]/SLICE_334 ( + .D1(\CPLD_Con_1/un1_i_freq_relay1lt8 ), + .C1(\CPLD_Con_1/un1_i_freq_relay1_1 ), .B1(\CPLD_Con_1/OC_x0112lto8_0 ), + .A1(\CPLD_Con_1/DMM_en_2_sqmuxa_1_0 ), + .C0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), .B0(\CPLD_Con_1/un1_DMM_en_1[0] ), + .A0(\CPLD_Con_1/N_41_1 ), .M0(\CPLD_Con_1/N_311 ), + .OFX0(\CPLD_Con_1.DMM_en_22[2] )); + CPLD_Con_1_DMM_en_22_11__SLICE_335 \CPLD_Con_1/DMM_en_22[11]/SLICE_335 ( + .D1(\freq3_relay[9] ), .C1(\freq3_relay[8] ), .B1(\CPLD_Con_1/N_90 ), + .A1(\CPLD_Con_1/DMM_en_12_sqmuxa_1_1 ), + .C0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), .B0(\CPLD_Con_1/un1_DMM_en_1[0] ), + .A0(\CPLD_Con_1/N_42_1 ), .M0(\CPLD_Con_1/N_311 ), + .OFX0(\CPLD_Con_1.DMM_en_22[11] )); + CPLD_Con_1_DMM_en_22_1__SLICE_336 \CPLD_Con_1/DMM_en_22[1]/SLICE_336 ( + .D1(\CPLD_Con_1/un1_i_freq_relay1lt8 ), .C1(\CPLD_Con_1/OC_x0112lto8_0 ), + .B1(\CPLD_Con_1/OC_x0112 ), .A1(\CPLD_Con_1/DMM_en_2_sqmuxa_1_0 ), + .C0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), .B0(\CPLD_Con_1/un1_DMM_en_1[0] ), + .A0(\CPLD_Con_1/N_40_1 ), .M0(\CPLD_Con_1/N_311 ), + .OFX0(\CPLD_Con_1.DMM_en_22[1] )); + CPLD_Con_1_DMM_en_22_9__SLICE_337 \CPLD_Con_1/DMM_en_22[9]/SLICE_337 ( + .D1(\CPLD_Con_1/N_349 ), .C1(\CPLD_Con_1/un1_i_freq_relay3lt8 ), + .B1(\CPLD_Con_1/OC_x0163 ), .A1(\CPLD_Con_1/DMM_en_10_sqmuxa_1 ), + .C0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), .B0(\CPLD_Con_1/un1_DMM_en_1[0] ), + .A0(\CPLD_Con_1/N_40_1 ), .M0(\CPLD_Con_1/N_311 ), + .OFX0(\CPLD_Con_1.DMM_en_22[9] )); + CPLD_Con_1_DMM_en_22_0__SLICE_338 \CPLD_Con_1/DMM_en_22[0]/SLICE_338 ( + .B1(\CPLD_Con_1/OC_x0112 ), .A1(\CPLD_Con_1/DMM_en_1_sqmuxa_1_0 ), + .C0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), .B0(\CPLD_Con_1/un1_DMM_en_1[0] ), + .A0(\CPLD_Con_1/N_39_1 ), .M0(\CPLD_Con_1/N_311 ), + .OFX0(\CPLD_Con_1.DMM_en_22[0] )); + CPLD_Con_1_DMM_en_22_8__SLICE_339 \CPLD_Con_1/DMM_en_22[8]/SLICE_339 ( + .D1(\CPLD_Con_1/N_90 ), .C1(\CPLD_Con_1/N_9 ), .B1(\CPLD_Con_1/OC_x0163 ), + .A1(\CPLD_Con_1/OC_x0138_3 ), .C0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), + .B0(\CPLD_Con_1/un1_DMM_en_1[0] ), .A0(\CPLD_Con_1/N_39_1 ), + .M0(\CPLD_Con_1/N_311 ), .OFX0(\CPLD_Con_1.DMM_en_22[8] )); + CPLD_Reg_1_rdata_reg_2_10_0__SLICE_340 + \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340 ( .C1(reg_addr_3_rep2), + .B1(\DC_Con2[0] ), .A1(\CPLD_Reg_1/regtable[15][0] ), .C0(\reg_addr[3] ), + .B0(\freq2_relay[0] ), .A0(\CPLD_Reg_1/regtable[11][0] ), + .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_278 ), + .FXA(\CPLD_Reg_1/N_230 ), .OFX0(\CPLD_Reg_1/N_278 ), + .OFX1(\CPLD_Reg_1/N_350 )); + CPLD_Reg_1_rdata_reg_2_11_23__SLICE_341 + \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341 ( .C1(\DC_Con4[23] ), + .B1(\CPLD_Reg_1/regtable[13][23] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[23] ), .A0(\CPLD_Reg_1/regtable[12][23] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_325 ), + .FXA(\CPLD_Reg_1/N_277 ), .OFX0(\CPLD_Reg_1/N_325 ), + .OFX1(\CPLD_Reg_1/N_349 )); + CPLD_Reg_1_rdata_reg_2_11_0__SLICE_342 + \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342 ( .C1(reg_addr_2_rep2), + .B1(\DC_Con4[0] ), .A1(\CPLD_Reg_1/regtable[13][0] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[0] ), .A0(\CPLD_Reg_1/regtable[12][0] ), + .M1(\reg_addr_fast[3] ), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_302 ), + .FXA(\CPLD_Reg_1/N_254 ), .OFX0(\CPLD_Reg_1/N_302 ), + .OFX1(\CPLD_Reg_1/N_326 )); + CPLD_Reg_1_rdata_reg_2_11_9__SLICE_343 + \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343 ( .C1(\DC_Con4[9] ), + .B1(\CPLD_Reg_1/regtable[13][9] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[9] ), .A0(\CPLD_Reg_1/regtable[12][9] ), .M1(reg_addr_3_rep1), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_311 ), .FXA(\CPLD_Reg_1/N_263 ), + .OFX0(\CPLD_Reg_1/N_311 ), .OFX1(\CPLD_Reg_1/N_335 )); + CPLD_Reg_1_rdata_reg_2_11_16__SLICE_344 + \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344 ( + .C1(\CPLD_Reg_1/regtable[13][16] ), .B1(\CPLD_Reg_1/regtable[9][16] ), + .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][16] ), + .A0(\CPLD_Reg_1/regtable[8][16] ), .M1(reg_addr_3_rep1), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1233 ), .FXA(\CPLD_Reg_1/N_270 ), + .OFX0(\CPLD_Reg_1/N_1233 ), .OFX1(\CPLD_Reg_1/N_342 )); + CPLD_Reg_1_rdata_reg_2_11_15__SLICE_345 + \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345 ( + .C1(\CPLD_Reg_1/regtable[13][15] ), .B1(\CPLD_Reg_1/regtable[9][15] ), + .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][15] ), + .A0(\CPLD_Reg_1/regtable[8][15] ), .M1(reg_addr_3_rep1), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1232 ), .FXA(\CPLD_Reg_1/N_269 ), + .OFX0(\CPLD_Reg_1/N_1232 ), .OFX1(\CPLD_Reg_1/N_341 )); + CPLD_Reg_1_rdata_reg_2_11_14__SLICE_346 + \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346 ( + .C1(\CPLD_Reg_1/regtable[13][14] ), .B1(\CPLD_Reg_1/regtable[9][14] ), + .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][14] ), + .A0(\CPLD_Reg_1/regtable[8][14] ), .M1(reg_addr_3_rep1), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1231 ), .FXA(\CPLD_Reg_1/N_268 ), + .OFX0(\CPLD_Reg_1/N_1231 ), .OFX1(\CPLD_Reg_1/N_340 )); + CPLD_Reg_1_rdata_reg_2_11_13__SLICE_347 + \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347 ( + .C1(\CPLD_Reg_1/regtable[13][13] ), .B1(\CPLD_Reg_1/regtable[9][13] ), + .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][13] ), + .A0(\CPLD_Reg_1/regtable[8][13] ), .M1(reg_addr_3_rep1), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1230 ), .FXA(\CPLD_Reg_1/N_267 ), + .OFX0(\CPLD_Reg_1/N_1230 ), .OFX1(\CPLD_Reg_1/N_339 )); + CPLD_Reg_1_rdata_reg_2_11_12__SLICE_348 + \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348 ( + .C1(\CPLD_Reg_1/regtable[13][12] ), .B1(\CPLD_Reg_1/regtable[9][12] ), + .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][12] ), + .A0(\CPLD_Reg_1/regtable[8][12] ), .M1(reg_addr_3_rep1), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1229 ), .FXA(\CPLD_Reg_1/N_266 ), + .OFX0(\CPLD_Reg_1/N_1229 ), .OFX1(\CPLD_Reg_1/N_338 )); + CPLD_Reg_1_rdata_reg_2_11_11__SLICE_349 + \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349 ( + .C1(\CPLD_Reg_1/regtable[13][11] ), .B1(\CPLD_Reg_1/regtable[9][11] ), + .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][11] ), + .A0(\CPLD_Reg_1/regtable[8][11] ), .M1(reg_addr_3_rep1), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1228 ), .FXA(\CPLD_Reg_1/N_265 ), + .OFX0(\CPLD_Reg_1/N_1228 ), .OFX1(\CPLD_Reg_1/N_337 )); + CPLD_Reg_1_rdata_reg_2_11_10__SLICE_350 + \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350 ( + .C1(\CPLD_Reg_1/regtable[13][10] ), .B1(\CPLD_Reg_1/regtable[9][10] ), + .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][10] ), + .A0(\CPLD_Reg_1/regtable[8][10] ), .M1(reg_addr_3_rep1), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1227 ), .FXA(\CPLD_Reg_1/N_264 ), + .OFX0(\CPLD_Reg_1/N_1227 ), .OFX1(\CPLD_Reg_1/N_336 )); + CPLD_Reg_1_rdata_reg_2_11_18__SLICE_351 + \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351 ( .C1(\DC_Con4[18] ), + .B1(\CPLD_Reg_1/regtable[13][18] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[18] ), .A0(\CPLD_Reg_1/regtable[12][18] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_320 ), + .FXA(\CPLD_Reg_1/N_272 ), .OFX0(\CPLD_Reg_1/N_320 ), + .OFX1(\CPLD_Reg_1/N_344 )); + CPLD_Reg_1_rdata_reg_2_11_1__SLICE_352 + \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352 ( .C1(reg_addr_2_rep2), + .B1(\DC_Con4[1] ), .A1(\CPLD_Reg_1/regtable[13][1] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[1] ), .A0(\CPLD_Reg_1/regtable[12][1] ), + .M1(\reg_addr_fast[3] ), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_303 ), + .FXA(\CPLD_Reg_1/N_255 ), .OFX0(\CPLD_Reg_1/N_303 ), + .OFX1(\CPLD_Reg_1/N_327 )); + CPLD_Reg_1_rdata_reg_2_11_2__SLICE_353 + \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353 ( .C1(reg_addr_2_rep2), + .B1(\DC_Con4[2] ), .A1(\CPLD_Reg_1/regtable[13][2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[2] ), .A0(\CPLD_Reg_1/regtable[12][2] ), + .M1(\reg_addr_fast[3] ), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_304 ), + .FXA(\CPLD_Reg_1/N_256 ), .OFX0(\CPLD_Reg_1/N_304 ), + .OFX1(\CPLD_Reg_1/N_328 )); + CPLD_Reg_1_rdata_reg_2_11_3__SLICE_354 + \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354 ( .C1(\DC_Con4[3] ), + .B1(\CPLD_Reg_1/regtable[13][3] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[3] ), .A0(\CPLD_Reg_1/regtable[12][3] ), + .M1(\reg_addr_fast[3] ), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_305 ), + .FXA(\CPLD_Reg_1/N_257 ), .OFX0(\CPLD_Reg_1/N_305 ), + .OFX1(\CPLD_Reg_1/N_329 )); + CPLD_Reg_1_rdata_reg_2_11_4__SLICE_355 + \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355 ( .C1(\DC_Con4[4] ), + .B1(\CPLD_Reg_1/regtable[13][4] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[4] ), .A0(\CPLD_Reg_1/regtable[12][4] ), .M1(reg_addr_3_rep1), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_306 ), .FXA(\CPLD_Reg_1/N_258 ), + .OFX0(\CPLD_Reg_1/N_306 ), .OFX1(\CPLD_Reg_1/N_330 )); + CPLD_Reg_1_rdata_reg_2_11_5__SLICE_356 + \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356 ( .C1(\DC_Con4[5] ), + .B1(\CPLD_Reg_1/regtable[13][5] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[5] ), .A0(\CPLD_Reg_1/regtable[12][5] ), .M1(reg_addr_3_rep1), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_307 ), .FXA(\CPLD_Reg_1/N_259 ), + .OFX0(\CPLD_Reg_1/N_307 ), .OFX1(\CPLD_Reg_1/N_331 )); + CPLD_Reg_1_rdata_reg_2_11_6__SLICE_357 + \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357 ( .C1(\DC_Con4[6] ), + .B1(\CPLD_Reg_1/regtable[13][6] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[6] ), .A0(\CPLD_Reg_1/regtable[12][6] ), .M1(reg_addr_3_rep1), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_308 ), .FXA(\CPLD_Reg_1/N_260 ), + .OFX0(\CPLD_Reg_1/N_308 ), .OFX1(\CPLD_Reg_1/N_332 )); + CPLD_Reg_1_rdata_reg_2_11_7__SLICE_358 + \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358 ( .C1(\DC_Con4[7] ), + .B1(\CPLD_Reg_1/regtable[13][7] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[7] ), .A0(\CPLD_Reg_1/regtable[12][7] ), .M1(reg_addr_3_rep1), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_309 ), .FXA(\CPLD_Reg_1/N_261 ), + .OFX0(\CPLD_Reg_1/N_309 ), .OFX1(\CPLD_Reg_1/N_333 )); + CPLD_Reg_1_rdata_reg_2_11_8__SLICE_359 + \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359 ( .C1(\DC_Con4[8] ), + .B1(\CPLD_Reg_1/regtable[13][8] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[8] ), .A0(\CPLD_Reg_1/regtable[12][8] ), .M1(reg_addr_3_rep1), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_310 ), .FXA(\CPLD_Reg_1/N_262 ), + .OFX0(\CPLD_Reg_1/N_310 ), .OFX1(\CPLD_Reg_1/N_334 )); + CPLD_Reg_1_rdata_reg_2_11_17__SLICE_360 + \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360 ( .C1(\DC_Con4[17] ), + .B1(\CPLD_Reg_1/regtable[13][17] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[17] ), .A0(\CPLD_Reg_1/regtable[12][17] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_319 ), + .FXA(\CPLD_Reg_1/N_271 ), .OFX0(\CPLD_Reg_1/N_319 ), + .OFX1(\CPLD_Reg_1/N_343 )); + CPLD_Reg_1_rdata_reg_2_11_19__SLICE_361 + \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361 ( .C1(\DC_Con4[19] ), + .B1(\CPLD_Reg_1/regtable[13][19] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[19] ), .A0(\CPLD_Reg_1/regtable[12][19] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_321 ), + .FXA(\CPLD_Reg_1/N_273 ), .OFX0(\CPLD_Reg_1/N_321 ), + .OFX1(\CPLD_Reg_1/N_345 )); + CPLD_Reg_1_rdata_reg_2_11_20__SLICE_362 + \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362 ( .C1(\DC_Con4[20] ), + .B1(\CPLD_Reg_1/regtable[13][20] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[20] ), .A0(\CPLD_Reg_1/regtable[12][20] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_322 ), + .FXA(\CPLD_Reg_1/N_274 ), .OFX0(\CPLD_Reg_1/N_322 ), + .OFX1(\CPLD_Reg_1/N_346 )); + CPLD_Reg_1_rdata_reg_2_11_21__SLICE_363 + \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363 ( .C1(\DC_Con4[21] ), + .B1(\CPLD_Reg_1/regtable[13][21] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[21] ), .A0(\CPLD_Reg_1/regtable[12][21] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_323 ), + .FXA(\CPLD_Reg_1/N_275 ), .OFX0(\CPLD_Reg_1/N_323 ), + .OFX1(\CPLD_Reg_1/N_347 )); + CPLD_Reg_1_rdata_reg_2_11_22__SLICE_364 + \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364 ( .C1(\DC_Con4[22] ), + .B1(\CPLD_Reg_1/regtable[13][22] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[22] ), .A0(\CPLD_Reg_1/regtable[12][22] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_324 ), + .FXA(\CPLD_Reg_1/N_276 ), .OFX0(\CPLD_Reg_1/N_324 ), + .OFX1(\CPLD_Reg_1/N_348 )); + CPLD_Reg_1_rdata_reg_2_10_23__SLICE_365 + \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365 ( .C1(reg_addr_3_rep2), + .B1(\DC_Con2[23] ), .A1(\CPLD_Reg_1/regtable[15][23] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][23] ), .A0(\CPLD_Reg_1/regtable[3][23] ), + .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_301 ), + .FXA(\CPLD_Reg_1/N_253 ), .OFX0(\CPLD_Reg_1/N_301 ), + .OFX1(\CPLD_Reg_1/N_373 )); + CPLD_Reg_1_rdata_reg_2_9_23__SLICE_366 + \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366 ( + .C1(\CPLD_Reg_1/regtable[5][23] ), .B1(\CPLD_Reg_1/regtable[4][23] ), + .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][23] ), + .A0(\CPLD_Reg_1/regtable[0][23] ), .M0(reg_addr_2_rep2), + .OFX0(\CPLD_Reg_1/N_277 )); + CPLD_Reg_1_rdata_reg_2_9_0__SLICE_367 + \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367 ( .C1(reg_addr_0_rep2), + .B1(\freq4_relay[0] ), .A1(\freq3_relay[0] ), .C0(\reg_addr[0] ), + .B0(con_exec), .A0(\CPLD_Reg_1/regtable[0][0] ), .M0(reg_addr_2_rep1), + .OFX0(\CPLD_Reg_1/N_254 )); + CPLD_Reg_1_rdata_reg_2_10_9__SLICE_368 + \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368 ( .C1(reg_addr_3_rep2), + .B1(\DC_Con2[9] ), .A1(\CPLD_Reg_1/regtable[15][9] ), .C0(\reg_addr[3] ), + .B0(\freq2_relay[9] ), .A0(\CPLD_Reg_1/regtable[11][9] ), + .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_287 ), + .FXA(\CPLD_Reg_1/N_239 ), .OFX0(\CPLD_Reg_1/N_287 ), + .OFX1(\CPLD_Reg_1/N_359 )); + CPLD_Reg_1_rdata_reg_2_9_9__SLICE_369 + \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369 ( .C1(reg_addr_0_rep2), + .B1(\freq4_relay[9] ), .A1(\freq3_relay[9] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][9] ), .A0(\CPLD_Reg_1/regtable[0][9] ), + .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_263 )); + CPLD_Reg_1_rdata_reg_2_10_i_m2_16__SLICE_370 + \CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370 ( .C1(reg_addr_3_rep2), + .B1(\CPLD_Reg_1/regtable[15][16] ), .A1(\CPLD_Reg_1/regtable[7][16] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][16] ), + .A0(\CPLD_Reg_1/regtable[3][16] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_79 ), .FXA(\CPLD_Reg_1/N_1240 ), + .OFX0(\CPLD_Reg_1/N_79 ), .OFX1(\CPLD_Reg_1/N_1241 )); + CPLD_Reg_1_rdata_reg_2_10_i_m2_15__SLICE_371 + \CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371 ( .C1(reg_addr_3_rep2), + .B1(\CPLD_Reg_1/regtable[15][15] ), .A1(\CPLD_Reg_1/regtable[7][15] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][15] ), + .A0(\CPLD_Reg_1/regtable[3][15] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_80 ), .FXA(\CPLD_Reg_1/N_1239 ), + .OFX0(\CPLD_Reg_1/N_80 ), .OFX1(\CPLD_Reg_1/N_1242 )); + CPLD_Reg_1_rdata_reg_2_10_i_m2_14__SLICE_372 + \CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372 ( .C1(reg_addr_3_rep2), + .B1(\CPLD_Reg_1/regtable[15][14] ), .A1(\CPLD_Reg_1/regtable[7][14] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][14] ), + .A0(\CPLD_Reg_1/regtable[3][14] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_81 ), .FXA(\CPLD_Reg_1/N_1238 ), + .OFX0(\CPLD_Reg_1/N_81 ), .OFX1(\CPLD_Reg_1/N_1243 )); + CPLD_Reg_1_rdata_reg_2_10_i_m2_13__SLICE_373 + \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373 ( .C1(reg_addr_3_rep2), + .B1(\CPLD_Reg_1/regtable[15][13] ), .A1(\CPLD_Reg_1/regtable[7][13] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][13] ), + .A0(\CPLD_Reg_1/regtable[3][13] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_82 ), .FXA(\CPLD_Reg_1/N_1237 ), + .OFX0(\CPLD_Reg_1/N_82 ), .OFX1(\CPLD_Reg_1/N_1244 )); + CPLD_Reg_1_rdata_reg_2_10_i_m2_12__SLICE_374 + \CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374 ( .C1(reg_addr_3_rep2), + .B1(\CPLD_Reg_1/regtable[15][12] ), .A1(\CPLD_Reg_1/regtable[7][12] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][12] ), + .A0(\CPLD_Reg_1/regtable[3][12] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_83 ), .FXA(\CPLD_Reg_1/N_1236 ), + .OFX0(\CPLD_Reg_1/N_83 ), .OFX1(\CPLD_Reg_1/N_1245 )); + CPLD_Reg_1_rdata_reg_2_10_i_m2_11__SLICE_375 + \CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375 ( .C1(reg_addr_3_rep2), + .B1(\CPLD_Reg_1/regtable[15][11] ), .A1(\CPLD_Reg_1/regtable[7][11] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][11] ), + .A0(\CPLD_Reg_1/regtable[3][11] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_1267 ), .FXA(\CPLD_Reg_1/N_1235 ), + .OFX0(\CPLD_Reg_1/N_1267 ), .OFX1(\CPLD_Reg_1/N_1246 )); + CPLD_Reg_1_rdata_reg_2_10_i_m2_10__SLICE_376 + \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376 ( .C1(reg_addr_3_rep2), + .B1(\CPLD_Reg_1/regtable[15][10] ), .A1(\CPLD_Reg_1/regtable[7][10] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][10] ), + .A0(\CPLD_Reg_1/regtable[3][10] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_1268 ), .FXA(\CPLD_Reg_1/N_1234 ), + .OFX0(\CPLD_Reg_1/N_1268 ), .OFX1(\CPLD_Reg_1/N_118 )); + CPLD_Reg_1_rdata_reg_2_9_16__SLICE_377 + \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377 ( .C1(\freq4_relay[16] ), + .B1(\CPLD_Reg_1/regtable[4][16] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][16] ), .A0(\CPLD_Reg_1/regtable[0][16] ), + .M0(reg_addr_2_rep2), .OFX0(\CPLD_Reg_1/N_270 )); + CPLD_Reg_1_rdata_reg_2_9_15__SLICE_378 + \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378 ( .C1(\freq4_relay[15] ), + .B1(\CPLD_Reg_1/regtable[4][15] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][15] ), .A0(\CPLD_Reg_1/regtable[0][15] ), + .M0(reg_addr_2_rep2), .OFX0(\CPLD_Reg_1/N_269 )); + CPLD_Reg_1_rdata_reg_2_9_14__SLICE_379 + \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379 ( .C1(\freq4_relay[14] ), + .B1(\CPLD_Reg_1/regtable[4][14] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][14] ), .A0(\CPLD_Reg_1/regtable[0][14] ), + .M0(reg_addr_2_rep2), .OFX0(\CPLD_Reg_1/N_268 )); + CPLD_Reg_1_rdata_reg_2_9_13__SLICE_380 + \CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380 ( .C1(\freq4_relay[13] ), + .B1(\CPLD_Reg_1/regtable[4][13] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][13] ), .A0(\CPLD_Reg_1/regtable[0][13] ), + .M0(reg_addr_2_rep2), .OFX0(\CPLD_Reg_1/N_267 )); + CPLD_Reg_1_rdata_reg_2_9_12__SLICE_381 + \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381 ( .C1(\freq4_relay[12] ), + .B1(\CPLD_Reg_1/regtable[4][12] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][12] ), .A0(\CPLD_Reg_1/regtable[0][12] ), + .M0(reg_addr_2_rep2), .OFX0(\CPLD_Reg_1/N_266 )); + CPLD_Reg_1_rdata_reg_2_9_11__SLICE_382 + \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382 ( + .C1(\CPLD_Reg_1/regtable[5][11] ), .B1(\CPLD_Reg_1/regtable[4][11] ), + .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][11] ), + .A0(\CPLD_Reg_1/regtable[0][11] ), .M0(reg_addr_2_rep2), + .OFX0(\CPLD_Reg_1/N_265 )); + CPLD_Reg_1_rdata_reg_2_9_10__SLICE_383 + \CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383 ( .C1(reg_addr_0_rep2), + .B1(\CPLD_Reg_1/regtable[5][10] ), .A1(\CPLD_Reg_1/regtable[4][10] ), + .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][10] ), + .A0(\CPLD_Reg_1/regtable[0][10] ), .M0(reg_addr_2_rep2), + .OFX0(\CPLD_Reg_1/N_264 )); + CPLD_Reg_1_rdata_reg_2_10_18__SLICE_384 + \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384 ( .C1(reg_addr_3_rep2), + .B1(\DC_Con2[18] ), .A1(\CPLD_Reg_1/regtable[15][18] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][18] ), .A0(\CPLD_Reg_1/regtable[3][18] ), + .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_296 ), + .FXA(\CPLD_Reg_1/N_248 ), .OFX0(\CPLD_Reg_1/N_296 ), + .OFX1(\CPLD_Reg_1/N_368 )); + CPLD_Reg_1_rdata_reg_2_9_18__SLICE_385 + \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385 ( + .C1(\CPLD_Reg_1/regtable[5][18] ), .B1(\CPLD_Reg_1/regtable[4][18] ), + .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][18] ), + .A0(\CPLD_Reg_1/regtable[0][18] ), .M0(reg_addr_2_rep2), + .OFX0(\CPLD_Reg_1/N_272 )); + CPLD_Reg_1_rdata_reg_2_10_1__SLICE_386 + \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386 ( .C1(reg_addr_3_rep2), + .B1(\DC_Con2[1] ), .A1(\CPLD_Reg_1/regtable[15][1] ), .C0(\reg_addr[3] ), + .B0(\freq2_relay[1] ), .A0(\CPLD_Reg_1/regtable[11][1] ), + .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_279 ), + .FXA(\CPLD_Reg_1/N_231 ), .OFX0(\CPLD_Reg_1/N_279 ), + .OFX1(\CPLD_Reg_1/N_351 )); + CPLD_Reg_1_rdata_reg_2_9_1__SLICE_387 + \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387 ( .C1(reg_addr_0_rep2), + .B1(\freq4_relay[1] ), .A1(\freq3_relay[1] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][1] ), .A0(\CPLD_Reg_1/regtable[0][1] ), + .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_255 )); + CPLD_Reg_1_rdata_reg_2_9_2__SLICE_388 + \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388 ( .C1(reg_addr_0_rep2), + .B1(\freq4_relay[2] ), .A1(\freq3_relay[2] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][2] ), .A0(\CPLD_Reg_1/regtable[0][2] ), + .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_256 )); + CPLD_Reg_1_rdata_reg_2_10_2__SLICE_389 + \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389 ( .C1(reg_addr_3_rep2), + .B1(\DC_Con2[2] ), .A1(\CPLD_Reg_1/regtable[15][2] ), .C0(\reg_addr[3] ), + .B0(\freq2_relay[2] ), .A0(\CPLD_Reg_1/regtable[11][2] ), + .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_280 ), + .FXA(\CPLD_Reg_1/N_232 ), .OFX0(\CPLD_Reg_1/N_280 ), + .OFX1(\CPLD_Reg_1/N_352 )); + CPLD_Reg_1_rdata_reg_2_9_3__SLICE_390 + \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390 ( .C1(reg_addr_0_rep2), + .B1(\freq4_relay[3] ), .A1(\freq3_relay[3] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][3] ), .A0(\CPLD_Reg_1/regtable[0][3] ), + .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_257 )); + CPLD_Reg_1_rdata_reg_2_10_3__SLICE_391 + \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391 ( .C1(reg_addr_3_rep2), + .B1(\DC_Con2[3] ), .A1(\CPLD_Reg_1/regtable[15][3] ), .C0(\reg_addr[3] ), + .B0(\freq2_relay[3] ), .A0(\CPLD_Reg_1/regtable[11][3] ), + .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_281 ), + .FXA(\CPLD_Reg_1/N_233 ), .OFX0(\CPLD_Reg_1/N_281 ), + .OFX1(\CPLD_Reg_1/N_353 )); + CPLD_Reg_1_rdata_reg_2_9_4__SLICE_392 + \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392 ( .C1(reg_addr_0_rep2), + .B1(\freq4_relay[4] ), .A1(\freq3_relay[4] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][4] ), .A0(\CPLD_Reg_1/regtable[0][4] ), + .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_258 )); + CPLD_Reg_1_rdata_reg_2_10_4__SLICE_393 + \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393 ( .C1(reg_addr_3_rep2), + .B1(\DC_Con2[4] ), .A1(\CPLD_Reg_1/regtable[15][4] ), .C0(\reg_addr[3] ), + .B0(\freq2_relay[4] ), .A0(\CPLD_Reg_1/regtable[11][4] ), + .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_282 ), + .FXA(\CPLD_Reg_1/N_234 ), .OFX0(\CPLD_Reg_1/N_282 ), + .OFX1(\CPLD_Reg_1/N_354 )); + CPLD_Reg_1_rdata_reg_2_9_5__SLICE_394 + \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394 ( .C1(reg_addr_0_rep2), + .B1(\freq4_relay[5] ), .A1(\freq3_relay[5] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][5] ), .A0(\CPLD_Reg_1/regtable[0][5] ), + .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_259 )); + CPLD_Reg_1_rdata_reg_2_10_5__SLICE_395 + \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395 ( .C1(reg_addr_3_rep2), + .B1(\DC_Con2[5] ), .A1(\CPLD_Reg_1/regtable[15][5] ), .C0(\reg_addr[3] ), + .B0(\freq2_relay[5] ), .A0(\CPLD_Reg_1/regtable[11][5] ), + .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_283 ), + .FXA(\CPLD_Reg_1/N_235 ), .OFX0(\CPLD_Reg_1/N_283 ), + .OFX1(\CPLD_Reg_1/N_355 )); + CPLD_Reg_1_rdata_reg_2_9_6__SLICE_396 + \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396 ( .C1(reg_addr_0_rep2), + .B1(\freq4_relay[6] ), .A1(\freq3_relay[6] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][6] ), .A0(\CPLD_Reg_1/regtable[0][6] ), + .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_260 )); + CPLD_Reg_1_rdata_reg_2_10_6__SLICE_397 + \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397 ( .C1(reg_addr_3_rep2), + .B1(\DC_Con2[6] ), .A1(\CPLD_Reg_1/regtable[15][6] ), .C0(\reg_addr[3] ), + .B0(\freq2_relay[6] ), .A0(\CPLD_Reg_1/regtable[11][6] ), + .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_284 ), + .FXA(\CPLD_Reg_1/N_236 ), .OFX0(\CPLD_Reg_1/N_284 ), + .OFX1(\CPLD_Reg_1/N_356 )); + CPLD_Reg_1_rdata_reg_2_9_7__SLICE_398 + \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398 ( .C1(reg_addr_0_rep2), + .B1(\freq4_relay[7] ), .A1(\freq3_relay[7] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][7] ), .A0(\CPLD_Reg_1/regtable[0][7] ), + .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_261 )); + CPLD_Reg_1_rdata_reg_2_10_7__SLICE_399 + \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399 ( .C1(reg_addr_3_rep2), + .B1(\DC_Con2[7] ), .A1(\CPLD_Reg_1/regtable[15][7] ), .C0(\reg_addr[3] ), + .B0(\freq2_relay[7] ), .A0(\CPLD_Reg_1/regtable[11][7] ), + .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_285 ), + .FXA(\CPLD_Reg_1/N_237 ), .OFX0(\CPLD_Reg_1/N_285 ), + .OFX1(\CPLD_Reg_1/N_357 )); + CPLD_Reg_1_rdata_reg_2_9_8__SLICE_400 + \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400 ( .C1(reg_addr_0_rep2), + .B1(\freq4_relay[8] ), .A1(\freq3_relay[8] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][8] ), .A0(\CPLD_Reg_1/regtable[0][8] ), + .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_262 )); + CPLD_Reg_1_rdata_reg_2_10_8__SLICE_401 + \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401 ( .C1(reg_addr_3_rep2), + .B1(\DC_Con2[8] ), .A1(\CPLD_Reg_1/regtable[15][8] ), .C0(\reg_addr[3] ), + .B0(\freq2_relay[8] ), .A0(\CPLD_Reg_1/regtable[11][8] ), + .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_286 ), + .FXA(\CPLD_Reg_1/N_238 ), .OFX0(\CPLD_Reg_1/N_286 ), + .OFX1(\CPLD_Reg_1/N_358 )); + CPLD_Reg_1_rdata_reg_2_9_17__SLICE_402 + \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402 ( .C1(\freq4_relay[17] ), + .B1(\CPLD_Reg_1/regtable[4][17] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][17] ), .A0(\CPLD_Reg_1/regtable[0][17] ), + .M0(reg_addr_2_rep2), .OFX0(\CPLD_Reg_1/N_271 )); + CPLD_Reg_1_rdata_reg_2_10_17__SLICE_403 + \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403 ( .C1(reg_addr_3_rep2), + .B1(\DC_Con2[17] ), .A1(\CPLD_Reg_1/regtable[15][17] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][17] ), .A0(\CPLD_Reg_1/regtable[3][17] ), + .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_295 ), + .FXA(\CPLD_Reg_1/N_247 ), .OFX0(\CPLD_Reg_1/N_295 ), + .OFX1(\CPLD_Reg_1/N_367 )); + CPLD_Reg_1_rdata_reg_2_9_19__SLICE_404 + \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404 ( + .C1(\CPLD_Reg_1/regtable[5][19] ), .B1(\CPLD_Reg_1/regtable[4][19] ), + .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][19] ), + .A0(\CPLD_Reg_1/regtable[0][19] ), .M0(reg_addr_2_rep2), + .OFX0(\CPLD_Reg_1/N_273 )); + CPLD_Reg_1_rdata_reg_2_10_19__SLICE_405 + \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405 ( .C1(reg_addr_3_rep2), + .B1(\DC_Con2[19] ), .A1(\CPLD_Reg_1/regtable[15][19] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][19] ), .A0(\CPLD_Reg_1/regtable[3][19] ), + .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_297 ), + .FXA(\CPLD_Reg_1/N_249 ), .OFX0(\CPLD_Reg_1/N_297 ), + .OFX1(\CPLD_Reg_1/N_369 )); + CPLD_Reg_1_rdata_reg_2_9_20__SLICE_406 + \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406 ( + .C1(\CPLD_Reg_1/regtable[5][20] ), .B1(\CPLD_Reg_1/regtable[4][20] ), + .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][20] ), + .A0(\CPLD_Reg_1/regtable[0][20] ), .M0(reg_addr_2_rep2), + .OFX0(\CPLD_Reg_1/N_274 )); + CPLD_Reg_1_rdata_reg_2_10_20__SLICE_407 + \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407 ( .C1(reg_addr_3_rep2), + .B1(\DC_Con2[20] ), .A1(\CPLD_Reg_1/regtable[15][20] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][20] ), .A0(\CPLD_Reg_1/regtable[3][20] ), + .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_298 ), + .FXA(\CPLD_Reg_1/N_250 ), .OFX0(\CPLD_Reg_1/N_298 ), + .OFX1(\CPLD_Reg_1/N_370 )); + CPLD_Reg_1_rdata_reg_2_9_21__SLICE_408 + \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408 ( + .C1(\CPLD_Reg_1/regtable[5][21] ), .B1(\CPLD_Reg_1/regtable[4][21] ), + .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][21] ), + .A0(\CPLD_Reg_1/regtable[0][21] ), .M0(reg_addr_2_rep2), + .OFX0(\CPLD_Reg_1/N_275 )); + CPLD_Reg_1_rdata_reg_2_10_21__SLICE_409 + \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409 ( .C1(reg_addr_3_rep2), + .B1(\DC_Con2[21] ), .A1(\CPLD_Reg_1/regtable[15][21] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][21] ), .A0(\CPLD_Reg_1/regtable[3][21] ), + .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_299 ), + .FXA(\CPLD_Reg_1/N_251 ), .OFX0(\CPLD_Reg_1/N_299 ), + .OFX1(\CPLD_Reg_1/N_371 )); + CPLD_Reg_1_rdata_reg_2_9_22__SLICE_410 + \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410 ( + .C1(\CPLD_Reg_1/regtable[5][22] ), .B1(\CPLD_Reg_1/regtable[4][22] ), + .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][22] ), + .A0(\CPLD_Reg_1/regtable[0][22] ), .M0(reg_addr_2_rep2), + .OFX0(\CPLD_Reg_1/N_276 )); + CPLD_Reg_1_rdata_reg_2_10_22__SLICE_411 + \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411 ( .C1(reg_addr_3_rep2), + .B1(\DC_Con2[22] ), .A1(\CPLD_Reg_1/regtable[15][22] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][22] ), .A0(\CPLD_Reg_1/regtable[3][22] ), + .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_300 ), + .FXA(\CPLD_Reg_1/N_252 ), .OFX0(\CPLD_Reg_1/N_300 ), + .OFX1(\CPLD_Reg_1/N_372 )); + SLICE_412 SLICE_412( .D1(\CPLD_Con_1/un1_i_DC_Con1_iv_1[1] ), + .C1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ), + .B1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ), + .A1(\CPLD_Con_1/un1_i_DC_Con1_iv_0[1] ), .D0(\CPLD_Con_1/N_216 ), + .C0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ), + .B0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ), + .A0(\CPLD_Con_1/un1_i_DC_Con1_4_axbxc1 ), .M1(\w_data[5] ), + .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(N_235), .Q0(\freq3_relay[4] ), + .F1(\CPLD_Con_1/un1_i_DC_Con1_4_axbxc1 ), .Q1(\freq3_relay[5] )); + SLICE_413 SLICE_413( .D1(\freq4_relay[8] ), .C1(\CPLD_Con_1/N_353 ), + .B1(\CPLD_Con_1/N_344 ), .A1(\CPLD_Con_1/N_85 ), .D0(\freq4_relay[9] ), + .C0(\CPLD_Con_1/N_353 ), .B0(\CPLD_Con_1/N_344 ), .A0(\CPLD_Con_1/N_338 ), + .M1(\r_data[23] ), .M0(\r_data[22] ), .CE(con_rvalid), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_22_0_0[15] ), + .Q0(\BUS_Con_1/tx_buffer[22] ), .F1(\CPLD_Con_1/N_338 ), + .Q1(\BUS_Con_1/tx_buffer[23] )); + BUS_Con_1_SLICE_414 \BUS_Con_1/SLICE_414 ( .D1(reg_busy), + .C1(\BUS_Con_1/state[1] ), .B1(\BUS_Con_1/state[0] ), + .A1(\BUS_Con_1/data_ready ), .D0(\BUS_Con_1/state[0] ), + .C0(\BUS_Con_1/state[1] ), .B0(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i ), + .A0(i_rst_n_c), .M1(\BUS_Con_1/recv_reg[15] ), + .M0(\BUS_Con_1/recv_reg[14] ), .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), + .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), + .Q0(\BUS_Con_1/recv_reg[15] ), .F1(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i ), + .Q1(\BUS_Con_1/recv_reg[16] )); + SLICE_415 SLICE_415( .D1(\freq3_relay[9] ), .C1(\freq3_relay[7] ), + .B1(\CPLD_Con_1/N_357 ), .A1(\CPLD_Con_1/freq_t ), .D0(\freq3_relay[8] ), + .C0(\freq3_relay[9] ), .B0(\CPLD_Con_1/DMM_en_22_0_a2_2[10] ), + .A0(\CPLD_Con_1/N_305 ), .M1(\r_data[3] ), .M0(\r_data[2] ), + .CE(con_rvalid), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_330 ), .Q0(\BUS_Con_1/tx_buffer[2] ), + .F1(\CPLD_Con_1/DMM_en_22_0_a2_2[10] ), .Q1(\BUS_Con_1/tx_buffer[3] )); + SLICE_416 SLICE_416( .C1(\CPLD_Con_1/freq_t ), .B1(\CPLD_Con_1.exec_flag ), + .A1(\CPLD_Con_1/dc_t ), .D0(\CPLD_Con_1.exec_flag ), .C0(con_exec), + .B0(\CPLD_Con_1/g0_8_1_0 ), .A0(\CPLD_Con_1/un1_err_flag_0_sqmuxa ), + .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/err_flag_RNO ), .Q0(\CPLD_Reg_1/regtable[6][11] ), + .F1(\CPLD_Con_1/g0_8_1_0 ), .Q1(\CPLD_Reg_1/regtable[6][12] )); + SLICE_417 SLICE_417( .D1(\freq1_relay[8] ), .C1(\CPLD_Con_1/N_298 ), + .B1(\CPLD_Con_1/un1_i_freq_relay1lt8 ), + .A1(\CPLD_Con_1/DMM_en_3_sqmuxa_1_0_a2_0_a2_0_a2_1 ), + .C0(\freq1_relay[7] ), .B0(\freq1_relay[6] ), .A0(\CPLD_Con_1/N_298 ), + .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_freq_relay1lt8 ), + .Q0(\DC_Con3[8] ), .F1(\CPLD_Con_1.N_259 ), .Q1(\DC_Con3[9] )); + SLICE_418 SLICE_418( .D1(\freq3_relay[6] ), .C1(\freq3_relay[5] ), + .B1(\freq3_relay[4] ), .A1(\CPLD_Con_1/g0_14_N_2L1 ), + .D0(\freq3_relay[7] ), .C0(\freq3_relay[4] ), .B0(\CPLD_Con_1/N_305 ), + .A0(\CPLD_Con_1/N_30 ), .M1(\BUS_Con_1/recv_reg[20] ), + .M0(\BUS_Con_1/recv_reg[19] ), .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), + .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/DMM_en_11_sqmuxa_0_147_i_i_0_0_tz ), + .Q0(\BUS_Con_1/recv_reg[20] ), .F1(\CPLD_Con_1/N_305 ), + .Q1(\BUS_Con_1/recv_reg[21] )); + SLICE_419 SLICE_419( .D1(\DC_Con3[23] ), .C1(\DC_Con3[20] ), + .B1(\DC_Con3[21] ), .A1(\CPLD_Con_1/g0_26_x0 ), .D0(\DC_Con3[21] ), + .C0(\DC_Con3[19] ), .B0(\DC_Con3[18] ), .A0(\DC_Con3[17] ), + .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_26_x0 ), .Q0(\DC_Con1[4] ), + .F1(\CPLD_Con_1/g1_0_0 ), .Q1(\DC_Con1[5] )); + SLICE_420 SLICE_420( .D1(\DC_Con4[9] ), .C1(\DC_Con4[7] ), .B1(\DC_Con4[5] ), + .A1(\CPLD_Con_1/RC_VISel41 ), .D0(\DC_Con4[4] ), .C0(\DC_Con4[6] ), + .B0(\CPLD_Con_1/N_192 ), .A0(\DC_Con4[8] ), .M1(\w_data[23] ), + .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_4_8[13] ), + .Q0(\CPLD_Reg_1/regtable[3][22] ), .F1(\CPLD_Con_1/N_192 ), + .Q1(\CPLD_Reg_1/regtable[3][23] )); + SLICE_421 SLICE_421( .D1(\DC_Con4[9] ), .C1(\DC_Con4[7] ), .B1(\DC_Con4[5] ), + .A1(\CPLD_Con_1/RC_VISel41 ), .D0(\DC_Con4[4] ), .C0(\DC_Con4[6] ), + .B0(\CPLD_Con_1/N_190 ), .A0(\DC_Con4[8] ), .M1(\w_data[14] ), + .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_4_8[15] ), + .Q0(\CPLD_Reg_1/regtable[3][13] ), .F1(\CPLD_Con_1/N_190 ), + .Q1(\CPLD_Reg_1/regtable[3][14] )); + SLICE_422 SLICE_422( .D1(\CPLD_Con_1/N_350 ), .C1(\CPLD_Con_1/N_298 ), + .B1(\CPLD_Con_1/DMM_en_1_sqmuxa_1_0_a2_0_a2_0_a2_2 ), + .A1(\CPLD_Con_1/DMM_en_1_sqmuxa_1_0_a2_0_a2_0_a2_0 ), + .C0(\freq1_relay[6] ), .B0(\freq1_relay[7] ), .A0(\freq1_relay[8] ), + .M1(\BUS_Con_1/recv_reg[24] ), .M0(\BUS_Con_1/recv_reg[23] ), + .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), + .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/DMM_en_1_sqmuxa_1_0_a2_0_a2_0_a2_0 ), + .Q0(\BUS_Con_1/recv_reg[24] ), .F1(\CPLD_Con_1.N_333 ), + .Q1(\BUS_Con_1/recv_reg[25] )); + SLICE_423 SLICE_423( .D1(\DC_Con4[9] ), .C1(\DC_Con4[8] ), .B1(\DC_Con4[7] ), + .A1(\DC_Con4[5] ), .D0(\DC_Con4[4] ), .C0(\DC_Con4[6] ), + .B0(\CPLD_Con_1/PMU_OC_4_8_0_a2_2[3] ), .A0(\CPLD_Con_1/RC_VISel41 ), + .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_4_8[3] ), .Q0(\freq2_relay[0] ), + .F1(\CPLD_Con_1/PMU_OC_4_8_0_a2_2[3] ), .Q1(\CPLD_Reg_1/regtable[3][10] )); + SLICE_424 SLICE_424( .D1(\DC_Con3[8] ), + .C1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[4] ), + .B1(\CPLD_Con_1/i_DC_Con4_m[8] ), .A1(\CPLD_Con_1/dc_slot_flag_2_rep1 ), + .D0(\CPLD_Con_1/un1_i_DC_Con1_1[4] ), .C0(\CPLD_Con_1/un1_i_DC_Con1_1[5] ), + .B0(\CPLD_Con_1/N_42_1 ), .A0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), + .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/un1_DMM_en[3] ), .Q0(\CPLD_Reg_1/regtable[11][4] ), + .F1(\CPLD_Con_1/un1_i_DC_Con1_1[4] ), .Q1(\CPLD_Reg_1/regtable[11][5] )); + SLICE_425 SLICE_425( .B1(\DC_Con1[6] ), .A1(\DC_Con1[5] ), .D0(\DC_Con1[7] ), + .C0(\DC_Con1[8] ), .B0(\CPLD_Con_1/N_113 ), .A0(\CPLD_Con_1/N_116 ), + .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_1_8[27] ), .Q0(\CPLD_Reg_1/regtable[12][20] ), + .F1(\CPLD_Con_1/N_116 ), .Q1(\CPLD_Reg_1/regtable[12][21] )); + SLICE_426 SLICE_426( .B1(\DC_Con1[6] ), .A1(\DC_Con1[5] ), .D0(\DC_Con1[7] ), + .C0(\DC_Con1[8] ), .B0(\CPLD_Con_1/N_113 ), .A0(\CPLD_Con_1/N_115 ), + .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_1_8[29] ), .Q0(\CPLD_Reg_1/regtable[12][4] ), + .F1(\CPLD_Con_1/N_115 ), .Q1(\CPLD_Reg_1/regtable[12][5] )); + SLICE_427 SLICE_427( .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), .D0(\DC_Con1[5] ), + .C0(\DC_Con1[6] ), .B0(\CPLD_Con_1/N_113 ), .A0(\CPLD_Con_1/N_118 ), + .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_1_8[31] ), .Q0(\CPLD_Reg_1/regtable[13][22] ), + .F1(\CPLD_Con_1/N_118 ), .Q1(\CPLD_Reg_1/regtable[13][23] )); + SLICE_428 SLICE_428( .C1(\DC_Con1[9] ), .B1(\DC_Con1[4] ), + .A1(\CPLD_Con_1/RC_VISel38 ), .D0(\DC_Con1[7] ), .C0(\DC_Con1[8] ), + .B0(\CPLD_Con_1/N_113 ), .A0(\CPLD_Con_1/N_116 ), .M1(\w_data[23] ), + .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_8[11] ), + .Q0(\CPLD_Reg_1/regtable[12][22] ), .F1(\CPLD_Con_1/N_113 ), + .Q1(\CPLD_Reg_1/regtable[12][23] )); + SLICE_429 SLICE_429( .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), .D0(\DC_Con1[5] ), + .C0(\DC_Con1[6] ), .B0(\CPLD_Con_1/N_113 ), .A0(\CPLD_Con_1/N_117 ), + .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_1_8[15] ), .Q0(\CPLD_Reg_1/regtable[13][13] ), + .F1(\CPLD_Con_1/N_117 ), .Q1(\CPLD_Reg_1/regtable[13][14] )); + SLICE_430 SLICE_430( .B1(\CPLD_Reg_1.regtable[6]_fast[6] ), + .A1(\CPLD_Reg_1.regtable[6]_fast[5] ), .D0(\DC_Con1[7] ), + .C0(\DC_Con1[8] ), .B0(\CPLD_Con_1/N_38 ), .A0(\CPLD_Con_1/N_113 ), + .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_1_8[17] ), .Q0(\CPLD_Reg_1/regtable[14][0] ), + .F1(\CPLD_Con_1/N_38 ), .Q1(\CPLD_Reg_1/regtable[14][10] )); + SLICE_431 SLICE_431( .B1(\DC_Con1[6] ), .A1(\DC_Con1[5] ), .D0(\DC_Con1[7] ), + .C0(\DC_Con1[8] ), .B0(\CPLD_Con_1/N_113 ), .A0(\CPLD_Con_1/N_119 ), + .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_1_8[23] ), .Q0(\CPLD_Reg_1/regtable[13][2] ), + .F1(\CPLD_Con_1/N_119 ), .Q1(\CPLD_Reg_1/regtable[13][3] )); + SLICE_432 SLICE_432( .B1(\DC_Con2[6] ), .A1(\DC_Con2[5] ), .D0(\DC_Con2[4] ), + .C0(\DC_Con2[8] ), .B0(\CPLD_Con_1/N_43 ), .A0(\CPLD_Con_1/N_96 ), + .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_2_8[17] ), .Q0(\CPLD_Reg_1/regtable[14][11] ), + .F1(\CPLD_Con_1/N_43 ), .Q1(\CPLD_Reg_1/regtable[14][12] )); + SLICE_433 SLICE_433( .C1(\DC_Con2[9] ), .B1(\DC_Con2[7] ), + .A1(\CPLD_Con_1/RC_VISel39 ), .D0(\DC_Con2[4] ), .C0(\DC_Con2[8] ), + .B0(\CPLD_Con_1/N_43 ), .A0(\CPLD_Con_1/N_95 ), .M1(\w_data[16] ), + .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_8[9] ), + .Q0(\CPLD_Reg_1/regtable[14][15] ), .F1(\CPLD_Con_1/N_95 ), + .Q1(\CPLD_Reg_1/regtable[14][16] )); + SLICE_434 SLICE_434( .D1(\DC_Con4[9] ), + .C1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[5] ), + .B1(\CPLD_Con_1/i_DC_Con3_m[9] ), .A1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), + .C0(\CPLD_Con_1/un1_i_DC_Con1_1[4] ), .B0(\CPLD_Con_1/un1_i_DC_Con1_1[5] ), + .A0(\CPLD_Con_1/N_311 ), .M1(\r_data[5] ), .M0(\r_data[4] ), + .CE(con_rvalid), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_351 ), .Q0(\BUS_Con_1/tx_buffer[4] ), + .F1(\CPLD_Con_1/un1_i_DC_Con1_1[5] ), .Q1(\BUS_Con_1/tx_buffer[5] )); + SLICE_435 SLICE_435( .C1(\DC_Con1[9] ), .B1(\DC_Con1[4] ), + .A1(\CPLD_Con_1/RC_VISel38 ), .D0(\DC_Con1[7] ), .C0(\DC_Con1[8] ), + .B0(\CPLD_Con_1/N_38 ), .A0(\CPLD_Con_1/N_114 ), .M1(\w_data[5] ), + .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_8[24] ), + .Q0(\CPLD_Reg_1/regtable[13][4] ), .F1(\CPLD_Con_1/N_114 ), + .Q1(\CPLD_Reg_1/regtable[13][5] )); + SLICE_436 SLICE_436( .D1(\CPLD_Con_1/N_67_i ), .C1(\DC_Con4[23] ), + .B1(\CPLD_Con_1/g0_12_N_3L3 ), .A1(\CPLD_Con_1/RC_VISel41 ), + .D0(\CPLD_Con_1/RC_VISel38 ), .C0(\CPLD_Con_1/g0_8_1_0 ), + .B0(\CPLD_Con_1/N_214 ), .A0(\CPLD_Con_1/DMM_en_0_sqmuxa_7 ), + .M1(\w_data[6] ), .M0(\w_data[5] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.un1_exec_flag_8_i ), + .Q0(\CPLD_Reg_1.regtable[7]_fast[5] ), .F1(\CPLD_Con_1/DMM_en_0_sqmuxa_7 ), + .Q1(\CPLD_Reg_1.regtable[7]_fast[6] )); + SLICE_437 SLICE_437( .C1(\CPLD_Con_1/N_214 ), .B1(\CPLD_Con_1/g0_8_1_0 ), + .A1(\CPLD_Con_1/RC_VISel38 ), .D0(i_rst_n_c), .C0(\CPLD_Con_1/N_196 ), + .B0(\CPLD_Con_1/un1_exec_flag_8_0_0 ), .A0(\CPLD_Con_1/DMM_en_0_sqmuxa_7 ), + .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/PMU_OC_4_8_0_a2_RNIL1I393[20] ), + .Q0(\CPLD_Reg_1/regtable[3][11] ), .F1(\CPLD_Con_1/un1_exec_flag_8_0_0 ), + .Q1(\CPLD_Reg_1/regtable[3][12] )); + SLICE_438 SLICE_438( .D1(\DC_Con4[9] ), .C1(\DC_Con4[7] ), .B1(\DC_Con4[5] ), + .A1(\CPLD_Con_1/RC_VISel41 ), .D0(i_rst_n_c), .C0(\CPLD_Con_1/N_191 ), + .B0(\CPLD_Con_1/un1_exec_flag_8_0_0 ), .A0(\CPLD_Con_1/DMM_en_0_sqmuxa_7 ), + .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\PMU_OC_4_8_0_a2_RNIS7H393[18] ), + .Q0(\freq2_relay[8] ), .F1(\CPLD_Con_1/N_191 ), .Q1(\freq2_relay[9] )); + SLICE_439 SLICE_439( .D1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_1[2] ), + .C1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[2] ), + .B1(\CPLD_Con_1/un1_DMM_en_1[0] ), .A1(\CPLD_Con_1/DMM_en_22_0_a2_2_1[4] ), + .D0(\CPLD_Con_1/N_360 ), .C0(\CPLD_Con_1/N_323 ), + .B0(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), .A0(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), + .M1(\r_data[16] ), .M0(\r_data[15] ), .CE(con_rvalid), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.DMM_en_22[5] ), + .Q0(\BUS_Con_1/tx_buffer[15] ), .F1(\CPLD_Con_1/N_360 ), + .Q1(\BUS_Con_1/tx_buffer[16] )); + SLICE_440 SLICE_440( .D1(\CPLD_Reg_1.regtable[8]_fast[5] ), + .C1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[1] ), + .B1(\CPLD_Con_1/i_DC_Con4_m[5] ), .A1(\CPLD_Con_1/dc_slot_flag[2] ), + .D0(\CPLD_Con_1/N_360 ), .C0(\CPLD_Con_1/N_325 ), + .B0(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), .A0(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), + .M1(\r_data[18] ), .M0(\r_data[17] ), .CE(con_rvalid), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.DMM_en_22[6] ), + .Q0(\BUS_Con_1/tx_buffer[17] ), .F1(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), + .Q1(\BUS_Con_1/tx_buffer[18] )); + SLICE_441 SLICE_441( .D1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_1[2] ), + .C1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[2] ), + .B1(\CPLD_Con_1/un1_DMM_en_1[0] ), + .A1(\CPLD_Con_1/DMM_en_22_0_a2_1_1[12] ), .D0(\CPLD_Con_1/N_363 ), + .C0(\CPLD_Con_1/N_333 ), .B0(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), + .A0(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), .M1(\BUS_Con_1/recv_reg[6] ), + .M0(\BUS_Con_1/recv_reg[5] ), .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), + .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.DMM_en_22[12] ), .Q0(\BUS_Con_1/recv_reg[6] ), + .F1(\CPLD_Con_1/N_363 ), .Q1(\BUS_Con_1/recv_reg[7] )); + SLICE_442 SLICE_442( .D1(\CPLD_Con_1/N_70 ), .C1(\DC_Con3[4] ), + .B1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0_0[0] ), + .A1(\CPLD_Con_1/dc_slot_flag[2] ), .D0(\CPLD_Con_1/N_363 ), + .C0(\CPLD_Con_1/N_336 ), .B0(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), + .A0(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), .M1(\r_data[10] ), .M0(\r_data[0] ), + .CE(con_rvalid), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.DMM_en_22[14] ), .Q0(\BUS_Con_1/tx_buffer[0] ), + .F1(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), .Q1(\BUS_Con_1/tx_buffer[10] )); + SLICE_443 SLICE_443( .D1(\freq4_relay[7] ), .C1(\CPLD_Con_1/N_364 ), + .B1(\CPLD_Con_1/N_307 ), .A1(\CPLD_Con_1/N_306 ), + .D0(\CPLD_Con_1/DMM_en_22_0_RNO[13] ), .C0(\CPLD_Con_1/N_363 ), + .B0(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), .A0(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), + .M1(\BUS_Con_1/recv_reg[8] ), .M0(\BUS_Con_1/recv_reg[7] ), + .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), + .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.DMM_en_22[13] ), .Q0(\BUS_Con_1/recv_reg[8] ), + .F1(\CPLD_Con_1/DMM_en_22_0_RNO[13] ), .Q1(\BUS_Con_1/recv_reg[9] )); + SLICE_444 SLICE_444( .D1(\DC_Con3[9] ), .C1(\CPLD_Con_1/g2_0 ), + .B1(\CPLD_Con_1/g1_0_0 ), .A1(\CPLD_Con_1/RC_VISel40 ), .D0(i_rst_n_c), + .C0(\CPLD_Con_1/N_140 ), .B0(\CPLD_Con_1/un1_exec_flag_2_0_0 ), + .A0(\CPLD_Con_1/DMM_en_0_sqmuxa_6 ), .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/un1_exec_flag_2_0_0_RNI3RHOG1 ), .Q0(\DC_Con2[20] ), + .F1(\CPLD_Con_1/DMM_en_0_sqmuxa_6 ), .Q1(\DC_Con2[21] )); + SLICE_445 SLICE_445( .C1(\CPLD_Con_1/g0_13_sn ), + .B1(\CPLD_Con_1/g0_13_rn_0 ), .A1(\CPLD_Con_1/err_flag19_0_0_0 ), + .D0(i_rst_n_c), .C0(\CPLD_Con_1/N_99 ), + .B0(\CPLD_Con_1/un1_exec_flag_3_0_0 ), .A0(\CPLD_Con_1/DMM_en_0_sqmuxa_5 ), + .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_3_0_0_RNISFCLD4 ), + .Q0(\DC_Con2[4] ), .F1(\CPLD_Con_1/DMM_en_0_sqmuxa_5 ), .Q1(\DC_Con2[5] )); + SLICE_446 SLICE_446( .D1(\freq2_relay[7] ), .C1(\CPLD_Con_1/N_407 ), + .B1(\CPLD_Con_1/N_329 ), .A1(\CPLD_Con_1/DMM_en_22_0_a2_1[7] ), + .D0(\CPLD_Con_1/N_360 ), .C0(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), + .B0(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), .A0(\CPLD_Con_1/DMM_en_22_0_0[7] ), + .M1(\r_data[1] ), .M0(\r_data[19] ), .CE(con_rvalid), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.DMM_en_22[7] ), + .Q0(\BUS_Con_1/tx_buffer[19] ), .F1(\CPLD_Con_1/DMM_en_22_0_0[7] ), + .Q1(\BUS_Con_1/tx_buffer[1] )); + SLICE_447 SLICE_447( .D1(\CPLD_Con_1/N_350 ), .C1(\CPLD_Con_1/N_9 ), + .B1(\CPLD_Con_1/freq_slot_flag[2] ), .A1(\CPLD_Con_1/freq_slot_flag[0] ), + .D0(\CPLD_Con_1/N_311 ), .C0(\CPLD_Con_1/un1_i_freq_relay1_1 ), + .B0(\CPLD_Con_1/un1_DMM_en[3] ), .A0(\CPLD_Con_1/DMM_en_1_sqmuxa_1_0 ), + .M1(\BUS_Con_1/recv_reg[2] ), .M0(\BUS_Con_1/recv_reg[30] ), + .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), + .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.DMM_en_22[3] ), .Q0(\BUS_Con_1/wr_out_6 ), + .F1(\CPLD_Con_1/DMM_en_1_sqmuxa_1_0 ), .Q1(\BUS_Con_1/recv_reg[3] )); + SLICE_448 SLICE_448( .D1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), + .C1(\CPLD_Con_1/dc_slot_flag_2_rep1 ), + .B1(\CPLD_Con_1/dc_slot_flag_1_rep1 ), + .A1(\CPLD_Con_1/dc_slot_flag_0_rep1 ), + .C0(\CPLD_Con_1/un1_exec_flag_4_0_0 ), .B0(\CPLD_Con_1/RC_VISel38 ), + .A0(\CPLD_Con_1/DMM_en_0_sqmuxa_3 ), .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.un1_exec_flag_4_i ), .Q0(\DC_Con2[8] ), + .F1(\CPLD_Con_1/RC_VISel38 ), .Q1(\DC_Con2[9] )); + SLICE_449 SLICE_449( .D1(\CPLD_Con_1/N_202 ), + .C1(\CPLD_Con_1/RC_RLSel_13_0_a3_2_N_4L5 ), + .B1(\CPLD_Con_1/RC_RLSel_13_0_a3_2_N_3L3 ), + .A1(\CPLD_Con_1/RC_RLSel_13_0_a3_2_N_2L1 ), .D0(\CPLD_Con_1/N_216 ), + .C0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ), + .B0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ), + .A0(\CPLD_Con_1/un1_i_DC_Con1_4_axbxc1 ), .M1(\w_data[10] ), + .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(N_234), .Q0(\freq4_relay[0] ), + .F1(\CPLD_Con_1/N_216 ), .Q1(\CPLD_Reg_1/regtable[5][10] )); + SLICE_450 SLICE_450( .C1(N_233), .B1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), + .A1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .D0(\CPLD_Con_1/N_216 ), + .C0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ), + .B0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ), + .A0(\CPLD_Con_1/un1_i_DC_Con1_4_axbxc1 ), .M1(\w_data[9] ), + .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(N_233), .Q0(\freq3_relay[8] ), + .F1(\CPLD_Con_1.RC_RLSel_13[12] ), .Q1(\freq3_relay[9] )); + SLICE_451 SLICE_451( .C1(N_232), .B1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), + .A1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .D0(\CPLD_Con_1/N_216 ), + .C0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ), + .B0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ), + .A0(\CPLD_Con_1/un1_i_DC_Con1_4_axbxc1 ), .M1(\w_data[7] ), + .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(N_232), .Q0(\freq3_relay[6] ), + .F1(\CPLD_Con_1.RC_RLSel_13[11] ), .Q1(\freq3_relay[7] )); + SLICE_452 SLICE_452( .D1(\CPLD_Con_1/N_78 ), .C1(\DC_Con3[9] ), + .B1(\CPLD_Con_1/err_flag25_0_o2_2 ), .A1(\CPLD_Con_1/err_flag25_0_0_0 ), + .D0(\DC_Con3[23] ), .C0(\CPLD_Con_1/un1_exec_flag_2_0_0 ), + .B0(\CPLD_Con_1/err_flag25 ), .A0(\CPLD_Con_1/RC_VISel40 ), + .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.un1_exec_flag_2_i ), .Q0(\DC_Con2[22] ), + .F1(\CPLD_Con_1/err_flag25 ), .Q1(\DC_Con2[23] )); + SLICE_453 SLICE_453( .D1(\CPLD_Con_1/dc_slot_flag[3] ), + .C1(\CPLD_Con_1/dc_slot_flag[2] ), .B1(\CPLD_Con_1/dc_slot_flag[1] ), + .A1(\CPLD_Con_1/dc_slot_flag[0] ), .D0(\DC_Con2[23] ), + .C0(\CPLD_Con_1/un1_exec_flag_3_0_0 ), .B0(\CPLD_Con_1/err_flag19 ), + .A0(\CPLD_Con_1/RC_VISel39 ), .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.un1_exec_flag_3_i ), .Q0(\DC_Con2[2] ), + .F1(\CPLD_Con_1/RC_VISel39 ), .Q1(\DC_Con2[3] )); + SLICE_454 SLICE_454( .D1(\DC_Con3[7] ), + .C1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[3] ), + .B1(\CPLD_Con_1/i_DC_Con4_m[7] ), .A1(\CPLD_Con_1/dc_slot_flag[2] ), + .D0(\CPLD_Con_1/N_351 ), .C0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), + .B0(\CPLD_Con_1/N_41_1 ), .A0(\CPLD_Con_1/DMM_en_22_0_0[10] ), + .M1(\BUS_Con_1/recv_reg[4] ), .M0(\BUS_Con_1/recv_reg[3] ), + .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), + .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.DMM_en_22[10] ), .Q0(\BUS_Con_1/recv_reg[4] ), + .F1(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), .Q1(\BUS_Con_1/recv_reg[5] )); + SLICE_455 SLICE_455( .C1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[4] ), + .B1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[4] ), + .A1(\CPLD_Con_1/un1_i_DC_Con1_4_axbxc1 ), .D0(\CPLD_Con_1/N_202 ), + .C0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ), + .B0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ), + .A0(\CPLD_Con_1/RC_RLSel_13_1[16] ), .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.RC_RLSel_13[17] ), .Q0(\CPLD_Reg_1/regtable[4][17] ), + .F1(\CPLD_Con_1/RC_RLSel_13_1[16] ), .Q1(\CPLD_Reg_1/regtable[4][18] )); + SLICE_456 SLICE_456( .D1(\DC_Con4[17] ), .C1(\DC_Con3[17] ), + .B1(\CPLD_Con_1/dc_slot_flag[3] ), .A1(\CPLD_Con_1/dc_slot_flag[2] ), + .D0(\CPLD_Con_1/N_202 ), .C0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ), + .B0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ), + .A0(\CPLD_Con_1/RC_RLSel_13_1[16] ), .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.RC_RLSel_13[16] ), .Q0(\CPLD_Reg_1/regtable[4][15] ), + .F1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ), + .Q1(\CPLD_Reg_1/regtable[4][16] )); + SLICE_457 SLICE_457( .D1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_1[2] ), + .C1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[2] ), + .B1(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), .A1(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), + .D0(\CPLD_Con_1/un1_i_DC_Con1_1[5] ), .C0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), + .B0(\CPLD_Con_1/N_39_1 ), .A0(\CPLD_Con_1/DMM_en_22_2[16] ), + .M1(\BUS_Con_1/recv_reg[26] ), .M0(\BUS_Con_1/recv_reg[25] ), + .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), + .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.DMM_en_22[16] ), .Q0(\BUS_Con_1/recv_reg[26] ), + .F1(\CPLD_Con_1/N_39_1 ), .Q1(\BUS_Con_1/recv_reg[27] )); + SLICE_458 SLICE_458( .D1(i_rst_n_c), + .C1(\CPLD_Con_1/un1_DMM_en_1_sqmuxa_tz ), .B1(\CPLD_Con_1/freq_t ), + .A1(\CPLD_Con_1/dc_t ), .D0(\CPLD_Con_1/N_311 ), + .C0(\CPLD_Con_1/un1_i_DC_Con1_1[5] ), .B0(\CPLD_Con_1/un1_i_DC_Con1_1[4] ), + .A0(\CPLD_Con_1/N_59_1 ), .M1(\BUS_Con_1/recv_reg[28] ), + .M0(\BUS_Con_1/recv_reg[27] ), .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), + .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.DMM_en_22[17] ), .Q0(\BUS_Con_1/recv_reg[28] ), + .F1(\CPLD_Con_1/N_311 ), .Q1(\BUS_Con_1/recv_reg[29] )); + SLICE_459 SLICE_459( .B1(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), + .A1(\CPLD_Con_1/N_41_1 ), .D0(\CPLD_Con_1/N_311 ), + .C0(\CPLD_Con_1/un1_i_DC_Con1_1[5] ), .B0(\CPLD_Con_1/un1_i_DC_Con1_1[4] ), + .A0(\CPLD_Con_1/N_60_1 ), .M1(\BUS_Con_1/recv_reg[29] ), + .M0(\BUS_Con_1/recv_reg[1] ), .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), + .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.DMM_en_22[18] ), .Q0(\BUS_Con_1/recv_reg[2] ), + .F1(\CPLD_Con_1/N_60_1 ), .Q1(\BUS_Con_1/recv_reg[30] )); + SLICE_460 SLICE_460( .C1(i_rst_n_c), .B1(\CPLD_Con_1/freq_slot_flag[2] ), + .A1(\CPLD_Con_1/freq_slot_flag[0] ), .C0(\CPLD_Con_1/N_356 ), + .B0(\CPLD_Con_1/N_342 ), .A0(\CPLD_Con_1/N_308 ), .M1(\w_data[21] ), + .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.N_315 ), + .Q0(\CPLD_Reg_1/regtable[11][20] ), .F1(\CPLD_Con_1/N_342 ), + .Q1(\CPLD_Reg_1/regtable[11][21] )); + SLICE_461 SLICE_461( .D1(\freq2_relay[9] ), .C1(\CPLD_Con_1/N_342 ), + .B1(\CPLD_Con_1/freq_slot_flag[3] ), .A1(\CPLD_Con_1/freq_slot_flag[1] ), + .D0(\freq2_relay[8] ), .C0(\freq2_relay[7] ), .B0(\CPLD_Con_1/N_407 ), + .A0(\CPLD_Con_1/DMM_en_7_sqmuxa_0_121_a2_0_a2_0 ), .M1(\w_data[1] ), + .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\DMM_en_22_0_o2_0_RNI5A4QI[7] ), + .Q0(\CPLD_Reg_1/regtable[11][19] ), + .F1(\CPLD_Con_1/DMM_en_7_sqmuxa_0_121_a2_0_a2_0 ), + .Q1(\CPLD_Reg_1/regtable[11][1] )); + SLICE_462 SLICE_462( .C1(\freq4_relay[9] ), + .B1(\CPLD_Con_1/freq_slot_flag[3] ), .A1(\CPLD_Con_1/freq_slot_flag[1] ), + .C0(\CPLD_Con_1/N_356 ), .B0(\CPLD_Con_1/N_344 ), .A0(\CPLD_Con_1/N_308 ), + .M1(\r_data[9] ), .M0(\r_data[8] ), .CE(con_rvalid), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_336 ), .Q0(\BUS_Con_1/tx_buffer[8] ), + .F1(\CPLD_Con_1/N_356 ), .Q1(\BUS_Con_1/tx_buffer[9] )); + SLICE_463 SLICE_463( .D1(\freq2_relay[9] ), .C1(\CPLD_Con_1/N_344 ), + .B1(\CPLD_Con_1/freq_slot_flag[3] ), .A1(\CPLD_Con_1/freq_slot_flag[1] ), + .D0(\freq2_relay[8] ), .C0(\freq2_relay[7] ), .B0(\CPLD_Con_1/N_407 ), + .A0(\CPLD_Con_1/DMM_en_22_0_a2_0[6] ), .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_325 ), .Q0(\CPLD_Reg_1/regtable[10][4] ), + .F1(\CPLD_Con_1/DMM_en_22_0_a2_0[6] ), .Q1(\CPLD_Reg_1/regtable[10][5] )); + SLICE_464 SLICE_464( .D1(\freq3_relay[6] ), .C1(\freq3_relay[5] ), + .B1(\freq3_relay[4] ), .A1(\CPLD_Con_1/N_30 ), .D0(\CPLD_Con_1/N_349 ), + .C0(\CPLD_Con_1/N_330 ), .B0(\CPLD_Con_1/un1_i_freq_relay3lt8 ), + .A0(\CPLD_Con_1/DMM_en_22_0_a2_0_1[10] ), .M1(\r_data[21] ), + .M0(\r_data[20] ), .CE(con_rvalid), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/DMM_en_22_0_0[10] ), .Q0(\BUS_Con_1/tx_buffer[20] ), + .F1(\CPLD_Con_1/N_349 ), .Q1(\BUS_Con_1/tx_buffer[21] )); + CPLD_Con_1_SLICE_465 \CPLD_Con_1/SLICE_465 ( .D1(\CPLD_Con_1/err_flag39 ), + .C1(\CPLD_Con_1/en_t[3] ), .B1(\CPLD_Con_1/en_t[2] ), + .A1(\CPLD_Con_1/en_t[1] ), .C0(con_exec), .B0(\CPLD_Con_1.exec_flag ), + .A0(\CPLD_Con_1/RC_Tx_0_sqmuxa ), .M0(\CPLD_Con_1.exec_flag ), + .CE(\CPLD_Con_1/un1_err_flag41_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/un1_err_flag41_i ), .Q0(o_con_done_c), + .F1(\CPLD_Con_1/RC_Tx_0_sqmuxa )); + SLICE_466 SLICE_466( .D1(\CPLD_Con_1/err_flag39 ), .C1(\CPLD_Con_1/en_t[3] ), + .B1(\CPLD_Con_1/en_t[2] ), .A1(\CPLD_Con_1/en_t[1] ), .B0(i_rst_n_c), + .A0(\CPLD_Con_1/RC_Tx_1_sqmuxa ), .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.RC_Tx_0_sqmuxa_1_i ), .Q0(\freq4_relay[13] ), + .F1(\CPLD_Con_1/RC_Tx_1_sqmuxa ), .Q1(\freq4_relay[14] )); + SLICE_467 SLICE_467( .B1(\freq1_relay[7] ), .A1(\freq1_relay[6] ), + .D0(\freq1_relay[9] ), .C0(\freq1_relay[8] ), .B0(\CPLD_Con_1/N_298 ), + .A0(\CPLD_Con_1/OC_x0112lto8_4_0 ), .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/un1_i_freq_relay1_1 ), .Q0(\DC_Con3[6] ), + .F1(\CPLD_Con_1/OC_x0112lto8_4_0 ), .Q1(\DC_Con3[7] )); + SLICE_468 SLICE_468( .C1(\freq4_relay[6] ), .B1(\freq4_relay[5] ), + .A1(\freq4_relay[4] ), .D0(\freq4_relay[8] ), .C0(\freq4_relay[7] ), + .B0(\CPLD_Con_1/N_307 ), .A0(\CPLD_Con_1/N_306 ), .M1(\w_data[18] ), + .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_308 ), + .Q0(\CPLD_Reg_1/regtable[11][17] ), .F1(\CPLD_Con_1/N_307 ), + .Q1(\CPLD_Reg_1/regtable[11][18] )); + SLICE_469 SLICE_469( .D1(i_rst_n_c), .C1(\CPLD_Con_1/N_350 ), + .B1(\CPLD_Con_1/freq_slot_flag[2] ), .A1(\CPLD_Con_1/freq_slot_flag[0] ), + .D0(\freq3_relay[8] ), .C0(\CPLD_Con_1/N_357 ), .B0(\CPLD_Con_1/N_90 ), + .A0(\CPLD_Con_1/DMM_en_11_sqmuxa_0_147_i_i_0_0_tz ), .M1(\w_data[6] ), + .M0(\w_data[5] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(N_22), .Q0(\CPLD_Reg_1.regtable[8]_fast[5] ), + .F1(\CPLD_Con_1/N_357 ), .Q1(\CPLD_Reg_1.regtable[8]_fast[6] )); + SLICE_470 SLICE_470( .B1(\DC_Con3[8] ), .A1(\DC_Con3[4] ), + .D0(\CPLD_Con_1/N_143 ), .C0(\CPLD_Con_1/N_136 ), .B0(\DC_Con3[6] ), + .A0(\DC_Con3[5] ), .M1(\w_data[19] ), .M0(\w_data[18] ), + .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_3_8[26] ), .Q0(\CPLD_Reg_1/regtable[1][18] ), + .F1(\CPLD_Con_1/N_143 ), .Q1(\CPLD_Reg_1/regtable[1][19] )); + SLICE_471 SLICE_471( .B1(\DC_Con3[8] ), .A1(\DC_Con3[4] ), + .D0(\CPLD_Con_1/N_141 ), .C0(\CPLD_Con_1/N_136 ), .B0(\DC_Con3[6] ), + .A0(\DC_Con3[5] ), .M1(\w_data[20] ), .M0(\w_data[1] ), + .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_3_8[27] ), .Q0(\CPLD_Reg_1/regtable[1][1] ), + .F1(\CPLD_Con_1/N_141 ), .Q1(\CPLD_Reg_1/regtable[1][20] )); + SLICE_472 SLICE_472( .C1(\DC_Con3[9] ), .B1(\DC_Con3[7] ), + .A1(\CPLD_Con_1/RC_VISel40 ), .D0(\CPLD_Con_1/N_143 ), + .C0(\CPLD_Con_1/N_136 ), .B0(\DC_Con3[6] ), .A0(\DC_Con3[5] ), + .M1(\w_data[22] ), .M0(\w_data[21] ), + .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_3_8[28] ), .Q0(\CPLD_Reg_1/regtable[1][21] ), + .F1(\CPLD_Con_1/N_136 ), .Q1(\CPLD_Reg_1/regtable[1][22] )); + SLICE_473 SLICE_473( .C1(\CPLD_Con_1/N_136 ), .B1(\DC_Con3[8] ), + .A1(\DC_Con3[4] ), .C0(\CPLD_Con_1/N_150 ), .B0(\DC_Con3[6] ), + .A0(\DC_Con3[5] ), .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_3_8[10] ), .Q0(\CPLD_Reg_1/regtable[15][2] ), + .F1(\CPLD_Con_1/N_150 ), .Q1(\CPLD_Reg_1/regtable[15][3] )); + SLICE_474 SLICE_474( .B1(\DC_Con3[8] ), .A1(\DC_Con3[4] ), + .D0(\CPLD_Con_1/N_140 ), .C0(\CPLD_Con_1/N_136 ), .B0(\DC_Con3[6] ), + .A0(\DC_Con3[5] ), .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_3_8[11] ), .Q0(\CPLD_Reg_1/regtable[15][4] ), + .F1(\CPLD_Con_1/N_140 ), .Q1(\CPLD_Reg_1/regtable[15][5] )); + SLICE_475 SLICE_475( .C1(\DC_Con3[9] ), .B1(\DC_Con3[7] ), + .A1(\CPLD_Con_1/RC_VISel40 ), .D0(\CPLD_Con_1/N_143 ), + .C0(\CPLD_Con_1/N_137 ), .B0(\DC_Con3[6] ), .A0(\DC_Con3[5] ), + .M1(\w_data[11] ), .M0(\w_data[10] ), + .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_3_8[18] ), .Q0(\CPLD_Reg_1/regtable[1][10] ), + .F1(\CPLD_Con_1/N_137 ), .Q1(\CPLD_Reg_1/regtable[1][11] )); + SLICE_476 SLICE_476( .C1(\CPLD_Con_1/N_137 ), .B1(\DC_Con3[6] ), + .A1(\DC_Con3[5] ), .C0(\CPLD_Con_1/N_144 ), .B0(\DC_Con3[8] ), + .A0(\DC_Con3[4] ), .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_3_8[2] ), .Q0(\CPLD_Reg_1/regtable[1][4] ), + .F1(\CPLD_Con_1/N_144 ), .Q1(\CPLD_Reg_1/regtable[1][5] )); + SLICE_477 SLICE_477( .C1(\CPLD_Con_1/N_137 ), .B1(\DC_Con3[6] ), + .A1(\DC_Con3[5] ), .C0(\CPLD_Con_1/N_147 ), .B0(\DC_Con3[8] ), + .A0(\DC_Con3[4] ), .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_3_8[4] ), .Q0(\freq1_relay[0] ), + .F1(\CPLD_Con_1/N_147 ), .Q1(\CPLD_Reg_1/regtable[2][10] )); + SLICE_478 SLICE_478( .C1(\CPLD_Con_1/N_137 ), .B1(\DC_Con3[6] ), + .A1(\DC_Con3[5] ), .C0(\CPLD_Con_1/N_148 ), .B0(\DC_Con3[8] ), + .A0(\DC_Con3[4] ), .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_3_8[6] ), .Q0(\CPLD_Reg_1/regtable[2][11] ), + .F1(\CPLD_Con_1/N_148 ), .Q1(\CPLD_Reg_1/regtable[2][12] )); + SLICE_479 SLICE_479( .B1(\DC_Con2[8] ), .A1(\DC_Con2[4] ), + .D0(\CPLD_Con_1/N_102 ), .C0(\CPLD_Con_1/N_95 ), .B0(\DC_Con2[6] ), + .A0(\DC_Con2[5] ), .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_2_8[26] ), .Q0(\CPLD_Reg_1/regtable[15][0] ), + .F1(\CPLD_Con_1/N_102 ), .Q1(\CPLD_Reg_1/regtable[15][10] )); + SLICE_480 SLICE_480( .B1(\DC_Con2[8] ), .A1(\DC_Con2[4] ), + .D0(\CPLD_Con_1/N_100 ), .C0(\CPLD_Con_1/N_95 ), .B0(\DC_Con2[6] ), + .A0(\DC_Con2[5] ), .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_2_8[27] ), .Q0(\CPLD_Reg_1/regtable[15][11] ), + .F1(\CPLD_Con_1/N_100 ), .Q1(\CPLD_Reg_1/regtable[15][12] )); + SLICE_481 SLICE_481( .C1(\CPLD_Con_1/N_95 ), .B1(\DC_Con2[8] ), + .A1(\DC_Con2[4] ), .C0(\CPLD_Con_1/N_111 ), .B0(\DC_Con2[6] ), + .A0(\DC_Con2[5] ), .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_2_8[10] ), .Q0(\CPLD_Reg_1/regtable[14][19] ), + .F1(\CPLD_Con_1/N_111 ), .Q1(\CPLD_Reg_1/regtable[14][1] )); + SLICE_482 SLICE_482( .B1(\DC_Con2[8] ), .A1(\DC_Con2[4] ), + .D0(\CPLD_Con_1/N_99 ), .C0(\CPLD_Con_1/N_95 ), .B0(\DC_Con2[6] ), + .A0(\DC_Con2[5] ), .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_2_8[11] ), .Q0(\CPLD_Reg_1/regtable[14][20] ), + .F1(\CPLD_Con_1/N_99 ), .Q1(\CPLD_Reg_1/regtable[14][21] )); + SLICE_483 SLICE_483( .C1(\DC_Con2[9] ), .B1(\DC_Con2[7] ), + .A1(\CPLD_Con_1/RC_VISel39 ), .D0(\CPLD_Con_1/N_102 ), + .C0(\CPLD_Con_1/N_96 ), .B0(\DC_Con2[6] ), .A0(\DC_Con2[5] ), + .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_2_8[18] ), .Q0(\CPLD_Reg_1/regtable[14][4] ), + .F1(\CPLD_Con_1/N_96 ), .Q1(\CPLD_Reg_1/regtable[14][5] )); + SLICE_484 SLICE_484( .C1(\CPLD_Con_1/N_96 ), .B1(\DC_Con2[6] ), + .A1(\DC_Con2[5] ), .C0(\CPLD_Con_1/N_103 ), .B0(\DC_Con2[8] ), + .A0(\DC_Con2[4] ), .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_2_8[2] ), .Q0(\CPLD_Reg_1/regtable[15][17] ), + .F1(\CPLD_Con_1/N_103 ), .Q1(\CPLD_Reg_1/regtable[15][18] )); + SLICE_485 SLICE_485( .C1(\CPLD_Con_1/N_96 ), .B1(\DC_Con2[6] ), + .A1(\DC_Con2[5] ), .C0(\CPLD_Con_1/N_63 ), .B0(\DC_Con2[8] ), + .A0(\DC_Con2[4] ), .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_2_8[4] ), .Q0(\CPLD_Reg_1/regtable[15][19] ), + .F1(\CPLD_Con_1/N_63 ), .Q1(\CPLD_Reg_1/regtable[15][1] )); + SLICE_486 SLICE_486( .C1(\CPLD_Con_1/N_96 ), .B1(\DC_Con2[6] ), + .A1(\DC_Con2[5] ), .C0(\CPLD_Con_1/N_64 ), .B0(\DC_Con2[8] ), + .A0(\DC_Con2[4] ), .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_2_8[6] ), .Q0(\CPLD_Reg_1/regtable[15][20] ), + .F1(\CPLD_Con_1/N_64 ), .Q1(\CPLD_Reg_1/regtable[15][21] )); + SLICE_487 SLICE_487( .D1(i_rst_n_c), .C1(\CPLD_Con_1/freq_t ), + .B1(\CPLD_Con_1/freq_slot_flag[2] ), .A1(\CPLD_Con_1/freq_slot_flag[0] ), + .D0(\freq4_relay[8] ), .C0(\CPLD_Con_1/N_356 ), .B0(\CPLD_Con_1/N_344 ), + .A0(\CPLD_Con_1/N_85 ), .M1(\r_data[7] ), .M0(\r_data[6] ), + .CE(con_rvalid), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_333 ), .Q0(\BUS_Con_1/tx_buffer[6] ), + .F1(\CPLD_Con_1/N_344 ), .Q1(\BUS_Con_1/tx_buffer[7] )); + SLICE_488 SLICE_488( .D1(\CPLD_Con_1/N_38 ), .C1(\DC_Con1[8] ), + .B1(\DC_Con1[7] ), .A1(\CPLD_Con_1/err_flag13_0_o2_0_2 ), + .D0(\CPLD_Con_1/N_65 ), .C0(\DC_Con1[23] ), .B0(\DC_Con1[9] ), + .A0(\CPLD_Con_1/err_flag13_0_0_0 ), .M1(\BUS_Con_1/recv_reg[0] ), + .M0(\BUS_Con_1/recv_reg[18] ), .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), + .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/DMM_en_0_sqmuxa_3 ), .Q0(\BUS_Con_1/recv_reg[19] ), + .F1(\CPLD_Con_1/N_65 ), .Q1(\BUS_Con_1/recv_reg[1] )); + SLICE_489 SLICE_489( .D1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_1[2] ), + .C1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[2] ), + .B1(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), .A1(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), + .B0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), .A0(\CPLD_Con_1/N_40_1 ), + .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_59_1 ), .Q0(\DC_Con2[17] ), .F1(\CPLD_Con_1/N_40_1 ), + .Q1(\DC_Con2[18] )); + SLICE_490 SLICE_490( .D1(\freq2_relay[9] ), .C1(\freq2_relay[8] ), + .B1(\CPLD_Con_1/freq_slot_flag[3] ), .A1(\CPLD_Con_1/freq_slot_flag[1] ), + .D0(\freq2_relay[7] ), .C0(\CPLD_Con_1/N_407 ), .B0(\CPLD_Con_1/N_365 ), + .A0(\CPLD_Con_1/N_344 ), .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_323 ), .Q0(\CPLD_Reg_1/regtable[10][2] ), + .F1(\CPLD_Con_1/N_365 ), .Q1(\CPLD_Reg_1/regtable[10][3] )); + SLICE_491 SLICE_491( .D1(\freq2_relay[6] ), .C1(\freq2_relay[5] ), + .B1(\freq2_relay[4] ), .A1(\CPLD_Con_1/OC_x0126lt3 ), + .D0(\freq2_relay[7] ), .C0(\CPLD_Con_1/N_407 ), .B0(\CPLD_Con_1/N_365 ), + .A0(\CPLD_Con_1/N_342 ), .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\DMM_en_22_0_a2_3_RNIK2BQH[4] ), .Q0(\CPLD_Reg_1/regtable[11][13] ), + .F1(\CPLD_Con_1/N_407 ), .Q1(\CPLD_Reg_1/regtable[11][14] )); + SLICE_492 SLICE_492( .B1(\freq4_relay[7] ), .A1(\CPLD_Con_1/N_306 ), + .D0(\freq4_relay[8] ), .C0(\CPLD_Con_1/N_356 ), .B0(\CPLD_Con_1/N_342 ), + .A0(\CPLD_Con_1/N_85 ), .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\DMM_en_22_0_o2_RNI8QTBL[15] ), .Q0(\CPLD_Reg_1/regtable[11][22] ), + .F1(\CPLD_Con_1/N_85 ), .Q1(\CPLD_Reg_1/regtable[11][23] )); + SLICE_493 SLICE_493( .D1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), + .C1(\CPLD_Con_1/dc_slot_flag_2_rep1 ), + .B1(\CPLD_Con_1/dc_slot_flag_1_rep1 ), + .A1(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .D0(\CPLD_Con_1/N_78 ), + .C0(\DC_Con3[9] ), .B0(\DC_Con3[7] ), .A0(\CPLD_Con_1/RC_VISel40 ), + .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_3_8[8] ), .Q0(\CPLD_Reg_1/regtable[2][13] ), + .F1(\CPLD_Con_1/RC_VISel40 ), .Q1(\CPLD_Reg_1/regtable[2][14] )); + SLICE_494 SLICE_494( .D1(\DC_Con4[6] ), + .C1(\CPLD_Reg_1.regtable[8]_fast[6] ), .B1(\CPLD_Con_1/dc_slot_flag[3] ), + .A1(\CPLD_Con_1/dc_slot_flag[2] ), + .D0(\CPLD_Con_1/un1_i_DC_Con1_1_iv_1[2] ), + .C0(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[2] ), + .B0(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), .A0(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), + .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_41_1 ), .Q0(\CPLD_Reg_1/regtable[7][13] ), + .F1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_1[2] ), + .Q1(\CPLD_Reg_1/regtable[7][14] )); + SLICE_495 SLICE_495( .D1(\DC_Con2[6] ), .C1(\DC_Con1[6] ), + .B1(\CPLD_Con_1/dc_slot_flag[1] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), + .D0(\CPLD_Con_1/un1_i_DC_Con1_1_iv_1[2] ), + .C0(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[2] ), + .B0(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), .A0(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), + .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_42_1 ), .Q0(\CPLD_Reg_1/regtable[7][15] ), + .F1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[2] ), + .Q1(\CPLD_Reg_1/regtable[7][16] )); + SLICE_496 SLICE_496( .C1(\DC_Con4[0] ), .B1(\DC_Con3[0] ), .A1(\DC_Con2[0] ), + .D0(\freq2_relay[0] ), .C0(\freq1_relay[0] ), .B0(\CPLD_Con_1/m2 ), + .A0(\CPLD_Con_1/SUM0 ), .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_18_c1 ), .Q0(\CPLD_Reg_1/regtable[12][11] ), + .F1(\CPLD_Con_1/SUM0 ), .Q1(\CPLD_Reg_1/regtable[12][12] )); + SLICE_497 SLICE_497( .B1(\DC_Con4[6] ), .A1(\DC_Con4[4] ), + .D0(\CPLD_Con_1/N_227 ), .C0(\CPLD_Con_1/N_206 ), .B0(\DC_Con4[7] ), + .A0(\DC_Con4[5] ), .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_4_8[29] ), .Q0(\freq1_relay[8] ), + .F1(\CPLD_Con_1/N_206 ), .Q1(\freq1_relay[9] )); + SLICE_498 SLICE_498( .B1(\DC_Con4[6] ), .A1(\DC_Con4[4] ), + .D0(\CPLD_Con_1/N_227 ), .C0(\CPLD_Con_1/N_188 ), .B0(\DC_Con4[7] ), + .A0(\DC_Con4[5] ), .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_4_8[17] ), .Q0(\CPLD_Reg_1/regtable[2][22] ), + .F1(\CPLD_Con_1/N_188 ), .Q1(\CPLD_Reg_1/regtable[2][23] )); + SLICE_499 SLICE_499( .C1(\DC_Con4[9] ), .B1(\DC_Con4[8] ), + .A1(\CPLD_Con_1/RC_VISel41 ), .D0(\CPLD_Con_1/N_227 ), + .C0(\CPLD_Con_1/N_206 ), .B0(\DC_Con4[7] ), .A0(\DC_Con4[5] ), + .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_4_8[21] ), .Q0(\freq1_relay[6] ), + .F1(\CPLD_Con_1/N_227 ), .Q1(\freq1_relay[7] )); + SLICE_500 SLICE_500( .B1(\freq3_relay[8] ), .A1(\CPLD_Con_1/N_357 ), + .D0(\freq3_relay[9] ), .C0(\freq3_relay[7] ), .B0(\CPLD_Con_1/N_361 ), + .A0(\CPLD_Con_1/freq_t ), .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/DMM_en_22_0_a2_0_1[10] ), + .Q0(\CPLD_Reg_1/regtable[10][6] ), .F1(\CPLD_Con_1/N_361 ), + .Q1(\CPLD_Reg_1/regtable[10][7] )); + SLICE_501 SLICE_501( .D1(\freq1_relay[8] ), .C1(\freq1_relay[9] ), + .B1(\CPLD_Con_1/OC_x0112lto8_4_0 ), .A1(\CPLD_Con_1/N_298 ), + .D0(\freq1_relay[5] ), .C0(\freq1_relay[4] ), .B0(\freq1_relay[3] ), + .A0(\CPLD_Con_1/OC_x0112lto2_0 ), .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_298 ), .Q0(\CPLD_Reg_1/regtable[12][13] ), + .F1(\CPLD_Con_1/OC_x0112 ), .Q1(\CPLD_Reg_1/regtable[12][14] )); + SLICE_502 SLICE_502( .C1(\freq4_relay[3] ), .B1(\freq4_relay[2] ), + .A1(\freq4_relay[1] ), .D0(\freq4_relay[6] ), .C0(\freq4_relay[5] ), + .B0(\freq4_relay[4] ), .A0(\CPLD_Con_1/OC_x0153lt3 ), .M1(\w_data[16] ), + .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_306 ), + .Q0(\CPLD_Reg_1/regtable[11][15] ), .F1(\CPLD_Con_1/OC_x0153lt3 ), + .Q1(\CPLD_Reg_1/regtable[11][16] )); + SLICE_503 SLICE_503( .D1(\CPLD_Con_1/dc_slot_flag_fast[3] ), + .C1(\CPLD_Con_1/dc_slot_flag_fast[2] ), + .B1(\CPLD_Con_1/dc_slot_flag_fast[1] ), + .A1(\CPLD_Con_1/dc_slot_flag_fast[0] ), .D0(\DC_Con4[9] ), + .C0(\DC_Con4[7] ), .B0(\DC_Con4[5] ), .A0(\CPLD_Con_1/RC_VISel41 ), + .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_196 ), .Q0(\freq1_relay[4] ), + .F1(\CPLD_Con_1/RC_VISel41 ), .Q1(\freq1_relay[5] )); + SLICE_504 SLICE_504( .D1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), + .C1(\CPLD_Con_1/dc_slot_flag_2_rep1 ), + .B1(\CPLD_Con_1/dc_slot_flag_1_rep1 ), + .A1(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .D0(\CPLD_Con_1/N_215 ), + .C0(\CPLD_Con_1/N_214 ), .B0(\CPLD_Con_1/freq_t ), .A0(\CPLD_Con_1/dc_t ), + .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_202 ), .Q0(\CPLD_Reg_1/regtable[5][11] ), + .F1(\CPLD_Con_1/N_215 ), .Q1(\freq4_relay[12] )); + SLICE_505 SLICE_505( .C1(\DC_Con4[9] ), .B1(\DC_Con4[7] ), .A1(\DC_Con4[5] ), + .D0(\CPLD_Con_1/N_188 ), .C0(\DC_Con4[8] ), .B0(\CPLD_Con_1/RC_VISel41 ), + .A0(\CPLD_Con_1/PMU_OC_4_8_0[25] ), .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_4_8[25] ), .Q0(\CPLD_Reg_1/regtable[2][19] ), + .F1(\CPLD_Con_1/PMU_OC_4_8_0[25] ), .Q1(\freq1_relay[1] )); + SLICE_506 SLICE_506( .D1(\DC_Con1[23] ), .C1(\DC_Con1[9] ), + .B1(\CPLD_Con_1/err_flag13_0_o2_0_2_RNIH4D9O_0 ), + .A1(\CPLD_Con_1/err_flag13_0_0_0 ), .D0(\CPLD_Con_1/N_57 ), + .C0(\DC_Con1[21] ), .B0(\DC_Con1[18] ), .A0(\DC_Con1[17] ), + .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/err_flag13_0_0_0 ), .Q0(\CPLD_Reg_1/regtable[5][20] ), + .F1(\CPLD_Con_1/err_flag13_0_0_0_RNIM0FM71 ), + .Q1(\CPLD_Reg_1/regtable[5][21] )); + SLICE_507 SLICE_507( .D1(\CPLD_Con_1/g0_13_rn_0 ), + .C1(\CPLD_Con_1/err_flag19_0_o2_2_RNIDVKG21 ), + .B1(\CPLD_Con_1/dc_slot_flag_RNIQ9AIV[0] ), + .A1(\CPLD_Con_1/err_flag19_0_0_0 ), .D0(\CPLD_Con_1/N_51 ), + .C0(\DC_Con2[21] ), .B0(\DC_Con2[18] ), .A0(\DC_Con2[17] ), + .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag19_0_0_0 ), + .Q0(\freq4_relay[6] ), .F1(\CPLD_Con_1/err_flag19_0_0_0_RNIAI9L43 ), + .Q1(\freq4_relay[7] )); + SLICE_508 SLICE_508( .B1(i_rst_n_c), .A1(\CPLD_Con_1/freq_t ), + .D0(\CPLD_Con_1/N_350 ), .C0(\CPLD_Con_1/freq_slot_flag[2] ), + .B0(\CPLD_Con_1/freq_slot_flag[0] ), + .A0(\CPLD_Con_1/DMM_en_12_sqmuxa_1_0 ), .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/DMM_en_12_sqmuxa_1_1 ), .Q0(\CPLD_Reg_1/regtable[11][6] ), + .F1(\CPLD_Con_1/DMM_en_12_sqmuxa_1_0 ), .Q1(\CPLD_Reg_1/regtable[11][7] )); + SLICE_509 SLICE_509( .D1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), + .C1(\CPLD_Con_1/dc_slot_flag_2_rep1 ), + .B1(\CPLD_Con_1/dc_slot_flag_1_rep1 ), + .A1(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .C0(\CPLD_Con_1/N_214 ), + .B0(\CPLD_Con_1/g0_8_1_0 ), .A0(\CPLD_Con_1/RC_VISel41 ), .M1(\w_data[7] ), + .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_4_0_0 ), + .Q0(\DC_Con2[6] ), .F1(\CPLD_Con_1/N_214 ), .Q1(\DC_Con2[7] )); + SLICE_510 SLICE_510( .B1(\CPLD_Con_1/freq_slot_flag[3] ), + .A1(\CPLD_Con_1/freq_slot_flag[1] ), .D0(\CPLD_Con_1/N_350 ), + .C0(\CPLD_Con_1/freq_slot_flag[2] ), .B0(\CPLD_Con_1/freq_slot_flag[0] ), + .A0(\CPLD_Con_1/DMM_en_12_sqmuxa_1_0 ), .M1(\w_data[18] ), + .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_2_sqmuxa_1_0 ), + .Q0(\CPLD_Reg_1/regtable[12][17] ), .F1(\CPLD_Con_1/N_350 ), + .Q1(\CPLD_Reg_1/regtable[12][18] )); + SLICE_511 SLICE_511( .D1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ), + .C1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ), + .B1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), + .A1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .D0(\CPLD_Con_1/N_165 ), + .C0(\DC_Con3[19] ), .B0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[2] ), + .A0(\CPLD_Con_1/dc_slot_flag_2_rep1 ), .M1(\w_data[14] ), + .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), + .Q0(\CPLD_Reg_1/regtable[8][13] ), + .F1(\CPLD_Con_1/RC_RLSel_13_0_a3_2_N_4L5 ), + .Q1(\CPLD_Reg_1/regtable[8][14] )); + SLICE_512 SLICE_512( .C1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), + .B1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), + .A1(\CPLD_Con_1/RC_RLSel_141_N_2_3_0 ), .D0(\CPLD_Con_1/N_173 ), + .C0(\DC_Con3[20] ), .B0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[3] ), + .A0(\CPLD_Con_1/dc_slot_flag_fast[2] ), .M1(\w_data[16] ), + .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), + .Q0(\CPLD_Reg_1/regtable[8][15] ), .F1(\CPLD_Con_1/g0_8_1 ), + .Q1(\CPLD_Reg_1/regtable[8][16] )); + SLICE_513 SLICE_513( .B1(i_rst_n_c), .A1(\CPLD_Con_1/freq_t ), + .D0(\freq3_relay[9] ), .C0(\freq3_relay[8] ), .B0(\freq3_relay[7] ), + .A0(\CPLD_Con_1/N_9 ), .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/DMM_en_10_sqmuxa_1 ), .Q0(\CPLD_Reg_1/regtable[11][8] ), + .F1(\CPLD_Con_1/N_9 ), .Q1(\CPLD_Reg_1/regtable[11][9] )); + SLICE_514 SLICE_514( .B1(\CPLD_Con_1/N_78 ), + .A1(\CPLD_Con_1/err_flag25_0_o2_2 ), .D0(\DC_Con3[8] ), .C0(\DC_Con3[4] ), + .B0(\CPLD_Reg_1.regtable[8]_fast[6] ), + .A0(\CPLD_Reg_1.regtable[8]_fast[5] ), .M1(\w_data[18] ), + .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_78 ), + .Q0(\CPLD_Reg_1/regtable[2][17] ), .F1(\CPLD_Con_1/g2_0 ), + .Q1(\CPLD_Reg_1/regtable[2][18] )); + CPLD_Con_1_SLICE_515 \CPLD_Con_1/SLICE_515 ( .D1(\freq1_relay[8] ), + .C1(\CPLD_Con_1/N_350 ), .B1(\CPLD_Con_1/OC_x0112lto8_4_0 ), + .A1(\CPLD_Con_1/DMM_en_1_sqmuxa_1_0_a2_0_a2_0_a2_2 ), .D0(i_rst_n_c), + .C0(\freq1_relay[9] ), .B0(\CPLD_Con_1/freq_slot_flag[2] ), + .A0(\CPLD_Con_1/freq_slot_flag[0] ), .M1(\freq2_relay[0] ), + .M0(\freq1_relay[0] ), .CE(\CPLD_Con_1/RC_Tx_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_1_sqmuxa_1_0_a2_0_a2_0_a2_2 ), + .Q0(\CPLD_Con_1/freq_slot_flag[0] ), + .F1(\CPLD_Con_1/DMM_en_3_sqmuxa_1_0_a2_0_a2_0_a2_1 ), + .Q1(\CPLD_Con_1/freq_slot_flag[1] )); + SLICE_516 SLICE_516( .B1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[4] ), + .A1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[4] ), .D0(\DC_Con2[21] ), + .C0(\DC_Con1[21] ), .B0(\CPLD_Con_1/dc_slot_flag[1] ), + .A0(\CPLD_Con_1/dc_slot_flag[0] ), .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[4] ), .Q0(\DC_Con3[20] ), + .F1(\CPLD_Con_1/RC_RLSel_13_0_a3_2_N_2L1 ), .Q1(\DC_Con3[21] )); + SLICE_517 SLICE_517( .B1(\CPLD_Con_1/un1_i_DC_Con1_iv_1[1] ), + .A1(\CPLD_Con_1/un1_i_DC_Con1_iv_0[1] ), .D0(\DC_Con2[18] ), + .C0(\DC_Con1[18] ), .B0(\CPLD_Con_1/dc_slot_flag_1_rep1 ), + .A0(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .M1(\w_data[12] ), + .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con1_iv_0[1] ), + .Q0(\CPLD_Reg_1/regtable[8][11] ), + .F1(\CPLD_Con_1/RC_RLSel_13_0_a3_2_N_3L3 ), + .Q1(\CPLD_Reg_1/regtable[8][12] )); + SLICE_518 SLICE_518( .D1(\CPLD_Con_1/un1_i_DC_Con1_iv_1[1] ), + .C1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ), + .B1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ), + .A1(\CPLD_Con_1/un1_i_DC_Con1_iv_0[1] ), .D0(\DC_Con4[18] ), + .C0(\DC_Con3[18] ), .B0(\CPLD_Con_1/dc_slot_flag_3_rep1 ), + .A0(\CPLD_Con_1/dc_slot_flag_2_rep1 ), .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/un1_i_DC_Con1_iv_1[1] ), .Q0(\DC_Con3[4] ), + .F1(\CPLD_Con_1/RC_RLSel_141_N_2_3_0 ), .Q1(\DC_Con3[5] )); + SLICE_519 SLICE_519( .D1(\DC_Con2[9] ), + .C1(\CPLD_Con_1/g0_2_N_5L7_N_6L9_0_1 ), .B1(\CPLD_Con_1/g0_2_1 ), + .A1(\CPLD_Con_1/err_flag19_0_o2_2 ), .D0(\DC_Con2[3] ), .C0(\DC_Con2[2] ), + .B0(\DC_Con2[1] ), .A0(\CPLD_Reg_1.regtable[7]_fast[7] ), + .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/err_flag19_0_o2_2 ), .Q0(\DC_Con1[0] ), + .F1(\CPLD_Con_1/err_flag19_0_o2_2_RNIDVKG21 ), + .Q1(\CPLD_Reg_1/regtable[6][10] )); + SLICE_520 SLICE_520( .D1(\CPLD_Con_1/N_38 ), .C1(\DC_Con1[8] ), + .B1(\DC_Con1[7] ), .A1(\CPLD_Con_1/err_flag13_0_o2_0_2 ), + .D0(\DC_Con1[4] ), .C0(\DC_Con1[3] ), .B0(\DC_Con1[2] ), .A0(\DC_Con1[1] ), + .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag13_0_o2_0_2 ), + .Q0(\freq4_relay[4] ), .F1(\CPLD_Con_1/err_flag13_0_o2_0_2_RNIH4D9O_0 ), + .Q1(\freq4_relay[5] )); + SLICE_521 SLICE_521( .D1(\freq3_relay[9] ), .C1(\CPLD_Con_1/N_305 ), + .B1(\CPLD_Con_1/g2_0_0 ), .A1(\CPLD_Con_1/OC_x0163 ), + .D0(\CPLD_Con_1/freq_slot_flag[3] ), .C0(\CPLD_Con_1/freq_slot_flag[2] ), + .B0(\CPLD_Con_1/freq_slot_flag[1] ), .A0(\CPLD_Con_1/freq_slot_flag[0] ), + .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/OC_x0163 ), .Q0(\CPLD_Reg_1/regtable[6][13] ), + .F1(\CPLD_Con_1/OC_x17_0_sqmuxa_i_1 ), .Q1(\CPLD_Reg_1/regtable[6][14] )); + SLICE_522 SLICE_522( .D1(\DC_Con2[8] ), .C1(\DC_Con2[4] ), + .B1(\CPLD_Con_1/g0_21_N_3L3 ), .A1(\CPLD_Con_1/g0_21_N_2L1 ), + .C0(\CPLD_Con_1/N_60 ), .B0(\DC_Con2[9] ), + .A0(\CPLD_Con_1/err_flag19_0_0_0 ), .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/err_flag19 ), .Q0(\freq4_relay[8] ), + .F1(\CPLD_Con_1/N_60 ), .Q1(\freq4_relay[9] )); + CPLD_Con_1_SLICE_523 \CPLD_Con_1/SLICE_523 ( .D1(\CPLD_Con_1/N_60 ), + .C1(\DC_Con2[23] ), .B1(\DC_Con2[9] ), .A1(\CPLD_Con_1/g0_7_2 ), + .D0(\CPLD_Con_1/dc_slot_flag[3] ), .C0(\CPLD_Con_1/dc_slot_flag[2] ), + .B0(\CPLD_Con_1/dc_slot_flag[1] ), .A0(\CPLD_Con_1/dc_slot_flag[0] ), + .M1(\DC_Con4[0] ), .M0(\DC_Con3[0] ), .CE(\CPLD_Con_1/RC_Tx_1_sqmuxa ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_7_2 ), + .Q0(\CPLD_Con_1/dc_slot_flag_2_rep1 ), .F1(\CPLD_Con_1/g0_13_sn ), + .Q1(\CPLD_Con_1/dc_slot_flag_3_rep1 )); + CPLD_Con_1_SLICE_524 \CPLD_Con_1/SLICE_524 ( .D1(\CPLD_Con_1/g0_6_2 ), + .C1(\CPLD_Con_1/g0_2_N_2L1_1_N_2L1 ), .B1(\CPLD_Con_1/freq_t ), + .A1(\CPLD_Con_1.exec_flag ), .D0(\CPLD_Con_1/freq_slot_flag[3] ), + .C0(\CPLD_Con_1/freq_slot_flag[2] ), .B0(\CPLD_Con_1/freq_slot_flag[1] ), + .A0(\CPLD_Con_1/freq_slot_flag[0] ), .M1(\freq4_relay[0] ), + .M0(\freq3_relay[0] ), .CE(\CPLD_Con_1/RC_Tx_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_6_2 ), + .Q0(\CPLD_Con_1/freq_slot_flag[2] ), .F1(\CPLD_Con_1/g0_2_1_1 ), + .Q1(\CPLD_Con_1/freq_slot_flag[3] )); + SLICE_525 SLICE_525( .D1(\DC_Con4[9] ), + .C1(\CPLD_Reg_1.regtable[9]_fast[6] ), .B1(\CPLD_Con_1/g1_1_3 ), + .A1(\CPLD_Con_1/g0_19_1 ), .D0(\DC_Con4[1] ), + .C0(\CPLD_Reg_1.regtable[9]_fast[8] ), + .B0(\CPLD_Reg_1.regtable[9]_fast[7] ), + .A0(\CPLD_Reg_1.regtable[9]_fast[5] ), .M1(\w_data[6] ), .M0(\w_data[5] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/g1_1_3 ), .Q0(\CPLD_Reg_1.regtable[6]_fast[5] ), + .F1(\CPLD_Con_1/N_67_i ), .Q1(\CPLD_Reg_1.regtable[6]_fast[6] )); + SLICE_526 SLICE_526( .D1(\CPLD_Con_1/un1_exec_flag_10_i_1 ), + .C1(\CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNILT4CU4 ), .B1(\CPLD_Con_1/freq_t ), + .A1(\CPLD_Con_1/err_flag_0_sqmuxa_0_0 ), .D0(\CPLD_Con_1/N_65 ), + .C0(\DC_Con1[9] ), .B0(\CPLD_Con_1/err_flag13_0_0_0 ), + .A0(\CPLD_Con_1/RC_VISel38 ), .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/err_flag_0_sqmuxa_0_0 ), .Q0(\CPLD_Reg_1/regtable[5][22] ), + .F1(\CPLD_Con_1.un1_exec_flag_10_i ), .Q1(\CPLD_Reg_1/regtable[5][23] )); + SLICE_527 SLICE_527( .D1(\DC_Con3[8] ), .C1(\DC_Con3[4] ), + .B1(\CPLD_Con_1/g0_3_1_N_2L1 ), .A1(\CPLD_Con_1/err_flag25_0_o2_2 ), + .D0(\DC_Con3[7] ), .C0(\DC_Con3[3] ), .B0(\DC_Con3[2] ), .A0(\DC_Con3[1] ), + .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag25_0_o2_2 ), .Q0(\DC_Con1[6] ), + .F1(\CPLD_Con_1/g0_3_1_N_5L8 ), .Q1(\DC_Con1[7] )); + CPLD_Con_1_SLICE_528 \CPLD_Con_1/SLICE_528 ( .D1(\CPLD_Con_1/N_60 ), + .C1(\DC_Con2[9] ), .B1(\CPLD_Con_1/g0_1_2_0 ), + .A1(\CPLD_Con_1/err_flag19_0_0_0 ), .D0(\CPLD_Con_1/dc_slot_flag_3_rep1 ), + .C0(\CPLD_Con_1/dc_slot_flag_2_rep1 ), + .B0(\CPLD_Con_1/dc_slot_flag_1_rep1 ), + .A0(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .M1(\DC_Con2[0] ), + .M0(\DC_Con1[0] ), .CE(\CPLD_Con_1/RC_Tx_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_1_2_0 ), + .Q0(\CPLD_Con_1/dc_slot_flag[0] ), .F1(\CPLD_Con_1/g0_1_0_0_1 ), + .Q1(\CPLD_Con_1/dc_slot_flag[1] )); + CPLD_Con_1_SLICE_529 \CPLD_Con_1/SLICE_529 ( + .D1(\CPLD_Con_1/un1_exec_flag_10_0 ), .C1(\CPLD_Con_1/g0_8_1 ), + .B1(\CPLD_Con_1/g0_2 ), .A1(\CPLD_Con_1/err_flag25 ), + .C0(\CPLD_Con_1/freq_t ), .B0(\CPLD_Con_1.exec_flag ), + .A0(\CPLD_Con_1/dc_t ), .M1(\DC_Con2[0] ), .M0(\DC_Con1[0] ), + .CE(\CPLD_Con_1/RC_Tx_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/un1_exec_flag_10_0 ), + .Q0(\CPLD_Con_1/dc_slot_flag_fast[0] ), + .F1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_RNIL5OH12[2] ), + .Q1(\CPLD_Con_1/dc_slot_flag_fast[1] )); + CPLD_Con_1_SLICE_530 \CPLD_Con_1/SLICE_530 ( .D1(\CPLD_Con_1/g0_2 ), + .C1(\CPLD_Con_1.exec_flag ), .B1(\CPLD_Con_1/err_flag25 ), + .A1(\CPLD_Con_1/dc_t ), .D0(\CPLD_Con_1/dc_slot_flag[3] ), + .C0(\CPLD_Con_1/dc_slot_flag[2] ), .B0(\CPLD_Con_1/dc_slot_flag[1] ), + .A0(\CPLD_Con_1/dc_slot_flag[0] ), .M1(\DC_Con2[0] ), .M0(\DC_Con1[0] ), + .CE(\CPLD_Con_1/RC_Tx_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/g0_2 ), .Q0(\CPLD_Con_1/dc_slot_flag_0_rep1 ), + .F1(\CPLD_Con_1/un1_exec_flag_10_i_1 ), + .Q1(\CPLD_Con_1/dc_slot_flag_1_rep1 )); + SLICE_531 SLICE_531( .D1(\CPLD_Con_1/N_67_i ), .C1(\CPLD_Con_1/g0_10_N_3L3 ), + .B1(\CPLD_Con_1/g0_1_0_0_1 ), .A1(\CPLD_Con_1/RC_VISel41 ), + .D0(\DC_Con4[21] ), .C0(\DC_Con4[18] ), .B0(\DC_Con4[17] ), + .A0(\CPLD_Con_1/g0_10_N_2L1 ), .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/g0_10_N_3L3 ), .Q0(\DC_Con1[20] ), + .F1(\CPLD_Con_1/g0_1_0 ), .Q1(\DC_Con1[21] )); + SLICE_532 SLICE_532( .D1(\CPLD_Con_1/N_65 ), .C1(\DC_Con1[9] ), + .B1(\CPLD_Con_1/err_flag13_0_0_0 ), .A1(\CPLD_Con_1/RC_VISel38 ), + .D0(i_rst_n_c), .C0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_RNIL5OH12[2] ), + .B0(\CPLD_Con_1/err_flag13_0_0_0_RNI92FNE1_0 ), .A0(\CPLD_Con_1/g0_1_0 ), + .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(err_flag13_0_0_0_RNILOU7L8), .Q0(\freq4_relay[2] ), + .F1(\CPLD_Con_1/err_flag13_0_0_0_RNI92FNE1_0 ), .Q1(\freq4_relay[3] )); + SLICE_533 SLICE_533( .D1(\CPLD_Con_1/N_60 ), .C1(\DC_Con2[9] ), + .B1(\CPLD_Con_1/g0_1_2_0 ), .A1(\CPLD_Con_1/err_flag19_0_0_0 ), + .D0(\CPLD_Con_1/N_67_i ), .C0(\CPLD_Con_1/err_flag19_0_0_0_RNI2M1DH2 ), + .B0(\CPLD_Con_1/g0_10_N_3L3 ), .A0(\CPLD_Con_1/RC_VISel41 ), + .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNILT4CU4 ), .Q0(\freq4_relay[15] ), + .F1(\CPLD_Con_1/err_flag19_0_0_0_RNI2M1DH2 ), .Q1(\freq4_relay[16] )); + SLICE_534 SLICE_534( .D1(\freq2_relay[7] ), .C1(\CPLD_Con_1/N_407 ), + .B1(\CPLD_Con_1/N_365 ), .A1(\CPLD_Con_1/N_344 ), .D0(\CPLD_Con_1/N_360 ), + .C0(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), .B0(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), + .A0(\CPLD_Con_1/DMM_en_22_0_N_2L1_0 ), .M1(\r_data[14] ), + .M0(\r_data[13] ), .CE(con_rvalid), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.DMM_en_22[4] ), .Q0(\BUS_Con_1/tx_buffer[13] ), + .F1(\CPLD_Con_1/DMM_en_22_0_N_2L1_0 ), .Q1(\BUS_Con_1/tx_buffer[14] )); + SLICE_535 SLICE_535( .D1(\CPLD_Con_1/N_67_i ), .C1(\DC_Con4[23] ), + .B1(\CPLD_Con_1/g0_12_N_3L3 ), .A1(\CPLD_Con_1/RC_VISel41 ), + .D0(\DC_Con4[21] ), .C0(\DC_Con4[18] ), .B0(\DC_Con4[17] ), + .A0(\CPLD_Con_1/g0_12_N_2L1 ), .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/g0_12_N_3L3 ), .Q0(\DC_Con1[22] ), + .F1(\CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNI54G4K2_0 ), .Q1(\DC_Con1[23] )); + SLICE_536 SLICE_536( .D1(\CPLD_Con_1/g0_3_1 ), + .C1(\CPLD_Con_1/err_flag19_0_0_0_RNIAI9L43 ), + .B1(\CPLD_Con_1/dc_slot_flag_0_rep1_RNIULU4R ), + .A1(\CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNI54G4K2_0 ), .D0(\DC_Con3[9] ), + .C0(\CPLD_Con_1/g0_3_1_N_5L8 ), .B0(\CPLD_Con_1/dc_t_RNI2Q6P8_0 ), + .A0(\CPLD_Con_1/RC_VISel40 ), .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/g0_3_1 ), .Q0(\CPLD_Reg_1/regtable[5][19] ), + .F1(\CPLD_Con_1/g0_2_1_0 ), .Q1(\freq4_relay[1] )); + SLICE_537 SLICE_537( .C1(\CPLD_Con_1/err_flag25_0_0_0 ), .B1(\DC_Con3[23] ), + .A1(\CPLD_Con_1/RC_VISel40 ), .C0(\DC_Con3[20] ), .B0(\DC_Con3[21] ), + .A0(\CPLD_Con_1/g0_26_x0 ), .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/err_flag25_0_0_0 ), .Q0(\DC_Con1[2] ), + .F1(\CPLD_Con_1/dc_slot_flag_0_rep1_RNIULU4R ), .Q1(\DC_Con1[3] )); + SLICE_538 SLICE_538( .D1(\CPLD_Con_1/dc_slot_flag[3] ), + .C1(\CPLD_Con_1/dc_slot_flag[2] ), .B1(\CPLD_Con_1/dc_slot_flag[1] ), + .A1(\CPLD_Con_1/dc_slot_flag[0] ), .B0(\DC_Con2[23] ), + .A0(\CPLD_Con_1/dc_slot_flag_RNIANH1R_3[0] ), .M1(\w_data[18] ), + .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/dc_slot_flag_RNIQ9AIV[0] ), + .Q0(\freq4_relay[17] ), .F1(\CPLD_Con_1/dc_slot_flag_RNIANH1R_3[0] ), + .Q1(\CPLD_Reg_1/regtable[5][18] )); + SLICE_539 SLICE_539( .D1(i_rst_n_c), .C1(\CPLD_Con_1/freq_t_RNIDK1OA3 ), + .B1(\CPLD_Con_1/g0_2_1_1 ), .A1(\CPLD_Con_1/g0_2_1_0 ), + .D0(\CPLD_Con_1/freq_slot_flag_RNIBOV481[0] ), + .C0(\CPLD_Con_1/dc_slot_flag_0_rep1_RNI421QK ), + .B0(\CPLD_Con_1/freq_t_RNI8PH26 ), + .A0(\CPLD_Con_1/err_flag13_0_0_0_RNIM0FM71 ), .M1(\w_data[18] ), + .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/freq_t_RNIDK1OA3 ), .Q0(\DC_Con1[17] ), + .F1(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), .Q1(\DC_Con1[18] )); + SLICE_540 SLICE_540( .B1(\freq3_relay[8] ), .A1(\freq3_relay[7] ), + .D0(\freq3_relay[9] ), .C0(\CPLD_Con_1/N_305 ), .B0(\CPLD_Con_1/g0_6_2 ), + .A0(\CPLD_Con_1/g0_2_x1_N_2L1 ), .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/freq_slot_flag_RNIBOV481[0] ), + .Q0(\CPLD_Reg_1/regtable[6][15] ), .F1(\CPLD_Con_1/g0_2_x1_N_2L1 ), + .Q1(\CPLD_Reg_1/regtable[6][16] )); + CPLD_Reg_1_SLICE_541 \CPLD_Reg_1/SLICE_541 ( + .D1(\CPLD_Reg_1/un34_regtable_5[1] ), + .C1(\CPLD_Reg_1/un34_regtable_1_0_0 ), + .B1(\CPLD_Reg_1/state_ns_0_a4_0_1[1] ), .A1(\CPLD_Reg_1/N_21 ), + .D0(\CPLD_Reg_1/reg_err_flag ), .C0(wr_flag), .B0(\CPLD_Reg_1/state[0] ), + .A0(\w_data[0] ), .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/state_ns_0_a4_0_1[1] ), .Q0(\CPLD_Reg_1/regtable[10][0] ), + .F1(\CPLD_Reg_1/N_25 ), .Q1(\CPLD_Reg_1/regtable[10][10] )); + CPLD_Reg_1_SLICE_542 \CPLD_Reg_1/SLICE_542 ( .D1(\reg_addr_fast[3] ), + .C1(\CPLD_Reg_1/un34_regtable_5[1] ), + .B1(\CPLD_Reg_1/regtable[0]_1_sqmuxa_1 ), + .A1(\CPLD_Reg_1/rdata_reg_1_sqmuxa_2 ), .D0(\reg_addr[1] ), + .C0(\reg_addr_fast[0] ), .B0(\CPLD_Reg_1/N_1185 ), .A0(\reg_addr_fast[2] ), + .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), + .Q0(\CPLD_Reg_1/regtable[0][6] ), .F1(\CPLD_Reg_1/N_1185 ), + .Q1(\CPLD_Reg_1/regtable[0][7] )); + CPLD_Reg_1_SLICE_543 \CPLD_Reg_1/SLICE_543 ( .D1(\CPLD_Reg_1/reg_err_flag ), + .C1(\CPLD_Reg_1/un34_regtable_5[1] ), + .B1(\CPLD_Reg_1/un34_regtable_1_0_0 ), + .A1(\CPLD_Reg_1/regtable[0]_1_sqmuxa_1 ), .C0(\CPLD_Reg_1/state[1] ), + .B0(\CPLD_Reg_1/state[0] ), .A0(\CPLD_Reg_1/regtable[1]_1_sqmuxa ), + .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), + .Q0(\CPLD_Reg_1/regtable[0][13] ), .F1(\CPLD_Reg_1/regtable[1]_1_sqmuxa ), + .Q1(\CPLD_Reg_1/regtable[0][14] )); + CPLD_Reg_1_SLICE_544 \CPLD_Reg_1/SLICE_544 ( + .D1(\CPLD_Reg_1/un34_regtable_5[1] ), + .C1(\CPLD_Reg_1/regtable[0]_1_sqmuxa_1 ), + .B1(\CPLD_Reg_1/rdata_reg_1_sqmuxa_2 ), .A1(\CPLD_Reg_1/N_1186 ), + .C0(\reg_addr_fast[3] ), .B0(\reg_addr_fast[2] ), + .A0(\CPLD_Reg_1/regtable[7]_1_sqmuxa_2 ), .M1(\w_data[23] ), + .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), + .Q0(\CPLD_Reg_1/regtable[0][22] ), + .F1(\CPLD_Reg_1/regtable[7]_1_sqmuxa_2 ), + .Q1(\CPLD_Reg_1/regtable[0][23] )); + CPLD_Reg_1_SLICE_545 \CPLD_Reg_1/SLICE_545 ( + .D1(\CPLD_Reg_1/un34_regtable_5[1] ), + .C1(\CPLD_Reg_1/regtable[0]_1_sqmuxa_1 ), + .B1(\CPLD_Reg_1/rdata_reg_1_sqmuxa_2 ), .A1(\CPLD_Reg_1/N_1169 ), + .C0(\reg_addr_fast[2] ), .B0(\reg_addr[1] ), .A0(\CPLD_Reg_1/N_1171 ), + .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][15] ), + .F1(\CPLD_Reg_1/N_1171 ), .Q1(\CPLD_Reg_1/regtable[0][16] )); + CPLD_Reg_1_SLICE_546 \CPLD_Reg_1/SLICE_546 ( .B1(wr_flag), .A1(con_exec), + .D0(\CPLD_Reg_1/un34_regtable_5[1] ), + .C0(\CPLD_Reg_1/regtable[5]_1_sqmuxa_0_a2_0 ), + .B0(\CPLD_Reg_1/regtable[0]_1_sqmuxa_1 ), + .A0(\CPLD_Reg_1/rdata_reg_1_sqmuxa_2 ), .M1(\w_data[1] ), + .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), + .Q0(\CPLD_Reg_1/regtable[0][19] ), + .F1(\CPLD_Reg_1/regtable[0]_1_sqmuxa_1 ), .Q1(\CPLD_Reg_1/regtable[0][1] )); + CPLD_Reg_1_SLICE_547 \CPLD_Reg_1/SLICE_547 ( .B1(wr_flag), + .A1(\CPLD_Reg_1/reg_err_flag ), .D0(con_exec), + .C0(\CPLD_Reg_1/un10_0_a3_0 ), .B0(\CPLD_Reg_1/state[1] ), + .A0(\CPLD_Reg_1/state[0] ), .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/un10_0 ), .Q0(\CPLD_Reg_1/regtable[10][11] ), + .F1(\CPLD_Reg_1/un10_0_a3_0 ), .Q1(\CPLD_Reg_1/regtable[10][12] )); + CPLD_Reg_1_SLICE_548 \CPLD_Reg_1/SLICE_548 ( .C1(\CPLD_Reg_1/reg_err_flag ), + .B1(\CPLD_Reg_1/state[1] ), .A1(\CPLD_Reg_1/state[0] ), .C0(wr_flag), + .B0(i_rst_n_c), .A0(\CPLD_Reg_1/rdata_reg_1_sqmuxa_2 ), .M1(\w_data[14] ), + .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .Q0(\CPLD_Reg_1/regtable[9][13] ), .F1(\CPLD_Reg_1/rdata_reg_1_sqmuxa_2 ), + .Q1(\CPLD_Reg_1/regtable[9][14] )); + CPLD_Reg_1_SLICE_549 \CPLD_Reg_1/SLICE_549 ( .B1(\reg_addr_fast[3] ), + .A1(\reg_addr_fast[0] ), .D0(wr_flag), .C0(reg_addr_2_rep1), + .B0(\reg_addr[1] ), .A0(\CPLD_Reg_1/N_1169 ), .M1(\w_data[12] ), + .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/N_1167 ), + .Q0(\CPLD_Reg_1/regtable[9][11] ), .F1(\CPLD_Reg_1/N_1169 ), + .Q1(\CPLD_Reg_1/regtable[9][12] )); + BUS_Con_1_SLICE_550 \BUS_Con_1/SLICE_550 ( .D1(\BUS_Con_1/N_244 ), + .C1(\BUS_Con_1/N_241 ), .B1(\BUS_Con_1/N_240 ), + .A1(\BUS_Con_1/cs_sync[1] ), .B0(i_rst_n_c), + .A0(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNIVM1LH ), + .M1(\BUS_Con_1/recv_reg[9] ), .M0(\BUS_Con_1/mosi_sync[1] ), + .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), + .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), + .Q0(\BUS_Con_1/recv_reg[0] ), + .F1(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNIVM1LH ), + .Q1(\BUS_Con_1/recv_reg[10] )); + BUS_Con_1_SLICE_551 \BUS_Con_1/SLICE_551 ( .B1(\BUS_Con_1/state[1] ), + .A1(\BUS_Con_1/state[0] ), .D0(\BUS_Con_1/N_244 ), .C0(\BUS_Con_1/N_241 ), + .B0(\BUS_Con_1/N_240 ), .A0(\BUS_Con_1/cs_sync[1] ), + .M1(\BUS_Con_1/recv_reg[11] ), .M0(\BUS_Con_1/recv_reg[10] ), + .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), + .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), .Q0(\BUS_Con_1/recv_reg[11] ), + .F1(\BUS_Con_1/N_240 ), .Q1(\BUS_Con_1/recv_reg[12] )); + SLICE_552 SLICE_552( .C1(\BUS_Con_1/sclk_sync[1] ), + .B1(\BUS_Con_1.sclk_sync[0] ), .A1(\BUS_Con_1/cs_sync[1] ), + .C0(\BUS_Con_1/N_253 ), .B0(\BUS_Con_1/N_242 ), + .A0(\BUS_Con_1.cs_sync[0] ), .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/N_238_i ), .Q0(\CPLD_Reg_1/regtable[10][22] ), + .F1(\BUS_Con_1/N_242 ), .Q1(\CPLD_Reg_1/regtable[10][23] )); + SLICE_553 SLICE_553( .D1(\BUS_Con_1/err_flag_1_sqmuxa_0_a2_0_0 ), + .C1(\BUS_Con_1/bit_cnt[5] ), .B1(\BUS_Con_1/bit_cnt[4] ), + .A1(\BUS_Con_1/bit_cnt[2] ), .D0(i_rst_n_c), .C0(\BUS_Con_1/N_253 ), + .B0(\BUS_Con_1/N_242 ), .A0(\BUS_Con_1.cs_sync[0] ), .M1(\w_data[18] ), + .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/bit_cnt_0_sqmuxa_1_i_a2_RNISVNVG ), + .Q0(\CPLD_Reg_1/regtable[10][17] ), .F1(\BUS_Con_1/N_253 ), + .Q1(\CPLD_Reg_1/regtable[10][18] )); + BUS_Con_1_SLICE_554 \BUS_Con_1/SLICE_554 ( .D1(\BUS_Con_1/N_244 ), + .C1(\BUS_Con_1/cs_sync[1] ), .B1(\BUS_Con_1/bit_cnt[1] ), + .A1(\BUS_Con_1/bit_cnt[0] ), .C0(\BUS_Con_1/un1_bit_cnt_9_c2 ), + .B0(\BUS_Con_1/bit_cnt[3] ), .A0(\BUS_Con_1/bit_cnt[2] ), + .M1(\BUS_Con_1/recv_reg[17] ), .M0(\BUS_Con_1/recv_reg[16] ), + .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), + .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/un1_bit_cnt_9_c4 ), .Q0(\BUS_Con_1/recv_reg[17] ), + .F1(\BUS_Con_1/un1_bit_cnt_9_c2 ), .Q1(\BUS_Con_1/recv_reg[18] )); + SLICE_555 SLICE_555( .D1(\CPLD_Con_1/N_192 ), .C1(\DC_Con4[8] ), + .B1(\DC_Con4[6] ), .A1(\DC_Con4[4] ), .D0(\DC_Con4[4] ), .C0(\DC_Con4[6] ), + .B0(\CPLD_Con_1/N_192 ), .A0(\DC_Con4[8] ), .M1(\w_data[3] ), + .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_4_8[9] ), .Q0(\freq2_relay[2] ), + .F1(\CPLD_Con_1.PMU_OC_4_8[8] ), .Q1(\freq2_relay[3] )); + SLICE_556 SLICE_556( .D1(\DC_Con4[8] ), .C1(\CPLD_Con_1/N_190 ), + .B1(\DC_Con4[6] ), .A1(\DC_Con4[4] ), .D0(\DC_Con4[4] ), .C0(\DC_Con4[6] ), + .B0(\CPLD_Con_1/N_190 ), .A0(\DC_Con4[8] ), .M1(\w_data[18] ), + .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_4_8[11] ), + .Q0(\CPLD_Reg_1/regtable[3][17] ), .F1(\CPLD_Con_1.PMU_OC_4_8[31] ), + .Q1(\CPLD_Reg_1/regtable[3][18] )); + SLICE_557 SLICE_557( .D1(\DC_Con4[4] ), .C1(\DC_Con4[6] ), .B1(\DC_Con4[8] ), + .A1(\CPLD_Con_1/N_192 ), .D0(\DC_Con4[4] ), .C0(\DC_Con4[6] ), + .B0(\DC_Con4[8] ), .A0(\CPLD_Con_1/N_192 ), .M1(\w_data[5] ), + .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_4_8[28] ), .Q0(\freq2_relay[4] ), + .F1(\CPLD_Con_1.PMU_OC_4_8[24] ), .Q1(\freq2_relay[5] )); + SLICE_558 SLICE_558( .D1(\DC_Con4[4] ), .C1(\DC_Con4[6] ), .B1(\DC_Con4[8] ), + .A1(\CPLD_Con_1/N_190 ), .D0(\DC_Con4[4] ), .C0(\DC_Con4[6] ), + .B0(\DC_Con4[8] ), .A0(\CPLD_Con_1/N_190 ), .M1(\w_data[16] ), + .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_4_8[27] ), + .Q0(\CPLD_Reg_1/regtable[3][15] ), .F1(\CPLD_Con_1.PMU_OC_4_8[14] ), + .Q1(\CPLD_Reg_1/regtable[3][16] )); + SLICE_559 SLICE_559( .D1(\CPLD_Con_1/N_115 ), .C1(\CPLD_Con_1/N_113 ), + .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), .D0(\DC_Con1[7] ), .C0(\DC_Con1[8] ), + .B0(\CPLD_Con_1/N_113 ), .A0(\CPLD_Con_1/N_115 ), .M1(\w_data[7] ), + .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_8[13] ), + .Q0(\CPLD_Reg_1/regtable[12][6] ), .F1(\CPLD_Con_1.PMU_OC_1_8[5] ), + .Q1(\CPLD_Reg_1/regtable[12][7] )); + SLICE_560 SLICE_560( .D1(\CPLD_Con_1/N_116 ), .C1(\CPLD_Con_1/N_113 ), + .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), .D0(\DC_Con1[7] ), .C0(\DC_Con1[8] ), + .B0(\CPLD_Con_1/N_113 ), .A0(\CPLD_Con_1/N_116 ), .M1(\w_data[3] ), + .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_8[19] ), + .Q0(\CPLD_Reg_1/regtable[12][2] ), .F1(\CPLD_Con_1.PMU_OC_1_8[3] ), + .Q1(\CPLD_Reg_1/regtable[12][3] )); + SLICE_561 SLICE_561( .D1(\CPLD_Con_1/N_113 ), .C1(\CPLD_Con_1/N_38 ), + .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), .D0(\DC_Con1[7] ), .C0(\DC_Con1[8] ), + .B0(\CPLD_Con_1/N_38 ), .A0(\CPLD_Con_1/N_113 ), .M1(\w_data[7] ), + .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_8[25] ), + .Q0(\CPLD_Reg_1/regtable[13][6] ), .F1(\CPLD_Con_1.PMU_OC_1_8[1] ), + .Q1(\CPLD_Reg_1/regtable[13][7] )); + SLICE_562 SLICE_562( .D1(\DC_Con4[4] ), .C1(\DC_Con4[6] ), .B1(\DC_Con4[8] ), + .A1(\CPLD_Con_1/N_190 ), .D0(\DC_Con4[4] ), .C0(\DC_Con4[6] ), + .B0(\DC_Con4[8] ), .A0(\CPLD_Con_1/N_190 ), .M1(\w_data[21] ), + .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_4_8[26] ), + .Q0(\CPLD_Reg_1/regtable[3][20] ), .F1(\CPLD_Con_1.PMU_OC_4_8[10] ), + .Q1(\CPLD_Reg_1/regtable[3][21] )); + SLICE_563 SLICE_563( .D1(\CPLD_Con_1/N_95 ), .C1(\CPLD_Con_1/N_43 ), + .B1(\DC_Con2[8] ), .A1(\DC_Con2[4] ), .D0(\DC_Con2[4] ), .C0(\DC_Con2[8] ), + .B0(\CPLD_Con_1/N_43 ), .A0(\CPLD_Con_1/N_95 ), .M1(\w_data[14] ), + .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_8[25] ), + .Q0(\CPLD_Reg_1/regtable[14][13] ), .F1(\CPLD_Con_1.PMU_OC_2_8[8] ), + .Q1(\CPLD_Reg_1/regtable[14][14] )); + SLICE_564 SLICE_564( .D1(\CPLD_Con_1/N_119 ), .C1(\CPLD_Con_1/N_114 ), + .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), .D0(\DC_Con1[7] ), .C0(\DC_Con1[8] ), + .B0(\CPLD_Con_1/N_114 ), .A0(\CPLD_Con_1/N_119 ), .M1(\w_data[12] ), + .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_8[22] ), + .Q0(\CPLD_Reg_1/regtable[13][11] ), .F1(\CPLD_Con_1.PMU_OC_1_8[6] ), + .Q1(\CPLD_Reg_1/regtable[13][12] )); + SLICE_565 SLICE_565( .D1(\CPLD_Con_1/N_115 ), .C1(\CPLD_Con_1/N_114 ), + .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), .D0(\DC_Con1[7] ), .C0(\DC_Con1[8] ), + .B0(\CPLD_Con_1/N_114 ), .A0(\CPLD_Con_1/N_115 ), .M1(\w_data[21] ), + .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_8[20] ), + .Q0(\CPLD_Reg_1/regtable[13][20] ), .F1(\CPLD_Con_1.PMU_OC_1_8[4] ), + .Q1(\CPLD_Reg_1/regtable[13][21] )); + SLICE_566 SLICE_566( .D1(\CPLD_Con_1/N_116 ), .C1(\CPLD_Con_1/N_114 ), + .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), .D0(\DC_Con1[7] ), .C0(\DC_Con1[8] ), + .B0(\CPLD_Con_1/N_114 ), .A0(\CPLD_Con_1/N_116 ), .M1(\w_data[18] ), + .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_8[18] ), + .Q0(\CPLD_Reg_1/regtable[13][17] ), .F1(\CPLD_Con_1.PMU_OC_1_8[2] ), + .Q1(\CPLD_Reg_1/regtable[13][18] )); + SLICE_567 SLICE_567( .D1(\DC_Con1[7] ), .C1(\DC_Con1[8] ), + .B1(\CPLD_Con_1/N_114 ), .A1(\CPLD_Con_1/N_115 ), .D0(\DC_Con1[7] ), + .C0(\DC_Con1[8] ), .B0(\CPLD_Con_1/N_114 ), .A0(\CPLD_Con_1/N_115 ), + .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_1_8[12] ), .Q0(\CPLD_Reg_1/regtable[13][19] ), + .F1(\CPLD_Con_1.PMU_OC_1_8[28] ), .Q1(\CPLD_Reg_1/regtable[13][1] )); + SLICE_568 SLICE_568( .D1(\DC_Con1[7] ), .C1(\DC_Con1[8] ), + .B1(\CPLD_Con_1/N_114 ), .A1(\CPLD_Con_1/N_116 ), .D0(\DC_Con1[7] ), + .C0(\DC_Con1[8] ), .B0(\CPLD_Con_1/N_114 ), .A0(\CPLD_Con_1/N_116 ), + .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_1_8[10] ), .Q0(\CPLD_Reg_1/regtable[13][15] ), + .F1(\CPLD_Con_1.PMU_OC_1_8[26] ), .Q1(\CPLD_Reg_1/regtable[13][16] )); + SLICE_569 SLICE_569( .D1(\CPLD_Con_1/N_141 ), .C1(\CPLD_Con_1/N_136 ), + .B1(\DC_Con3[6] ), .A1(\DC_Con3[5] ), .D0(\CPLD_Con_1/N_141 ), + .C0(\CPLD_Con_1/N_136 ), .B0(\DC_Con3[6] ), .A0(\DC_Con3[5] ), + .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_3_8[29] ), .Q0(\CPLD_Reg_1/regtable[1][2] ), + .F1(\CPLD_Con_1.PMU_OC_3_8[25] ), .Q1(\CPLD_Reg_1/regtable[1][3] )); + SLICE_570 SLICE_570( .D1(\CPLD_Con_1/N_143 ), .C1(\CPLD_Con_1/N_136 ), + .B1(\DC_Con3[6] ), .A1(\DC_Con3[5] ), .D0(\CPLD_Con_1/N_143 ), + .C0(\CPLD_Con_1/N_136 ), .B0(\DC_Con3[6] ), .A0(\DC_Con3[5] ), + .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_3_8[30] ), .Q0(\CPLD_Reg_1/regtable[1][6] ), + .F1(\CPLD_Con_1.PMU_OC_3_8[24] ), .Q1(\CPLD_Reg_1/regtable[1][7] )); + SLICE_571 SLICE_571( .D1(\CPLD_Con_1/N_140 ), .C1(\CPLD_Con_1/N_136 ), + .B1(\DC_Con3[6] ), .A1(\DC_Con3[5] ), .D0(\CPLD_Con_1/N_140 ), + .C0(\CPLD_Con_1/N_136 ), .B0(\DC_Con3[6] ), .A0(\DC_Con3[5] ), + .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_3_8[13] ), .Q0(\CPLD_Reg_1/regtable[15][8] ), + .F1(\CPLD_Con_1.PMU_OC_3_8[9] ), .Q1(\CPLD_Reg_1/regtable[15][9] )); + SLICE_572 SLICE_572( .D1(\CPLD_Con_1/N_141 ), .C1(\CPLD_Con_1/N_137 ), + .B1(\DC_Con3[6] ), .A1(\DC_Con3[5] ), .D0(\CPLD_Con_1/N_141 ), + .C0(\CPLD_Con_1/N_137 ), .B0(\DC_Con3[6] ), .A0(\DC_Con3[5] ), + .M1(\w_data[13] ), .M0(\w_data[12] ), + .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_3_8[19] ), .Q0(\CPLD_Reg_1/regtable[1][12] ), + .F1(\CPLD_Con_1.PMU_OC_3_8[17] ), .Q1(\CPLD_Reg_1/regtable[1][13] )); + SLICE_573 SLICE_573( .D1(\CPLD_Con_1/N_143 ), .C1(\CPLD_Con_1/N_137 ), + .B1(\DC_Con3[6] ), .A1(\DC_Con3[5] ), .D0(\CPLD_Con_1/N_143 ), + .C0(\CPLD_Con_1/N_137 ), .B0(\DC_Con3[6] ), .A0(\DC_Con3[5] ), + .M1(\w_data[15] ), .M0(\w_data[14] ), + .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_3_8[20] ), .Q0(\CPLD_Reg_1/regtable[1][14] ), + .F1(\CPLD_Con_1.PMU_OC_3_8[22] ), .Q1(\CPLD_Reg_1/regtable[1][15] )); + SLICE_574 SLICE_574( .D1(\CPLD_Con_1/N_141 ), .C1(\CPLD_Con_1/N_137 ), + .B1(\DC_Con3[6] ), .A1(\DC_Con3[5] ), .D0(\CPLD_Con_1/N_141 ), + .C0(\CPLD_Con_1/N_137 ), .B0(\DC_Con3[6] ), .A0(\DC_Con3[5] ), + .M1(\w_data[17] ), .M0(\w_data[16] ), + .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_3_8[21] ), .Q0(\CPLD_Reg_1/regtable[1][16] ), + .F1(\CPLD_Con_1.PMU_OC_3_8[23] ), .Q1(\CPLD_Reg_1/regtable[1][17] )); + SLICE_575 SLICE_575( .D1(\CPLD_Con_1/N_102 ), .C1(\CPLD_Con_1/N_95 ), + .B1(\DC_Con2[6] ), .A1(\DC_Con2[5] ), .D0(\CPLD_Con_1/N_102 ), + .C0(\CPLD_Con_1/N_95 ), .B0(\DC_Con2[6] ), .A0(\DC_Con2[5] ), + .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_2_8[28] ), .Q0(\CPLD_Reg_1/regtable[15][13] ), + .F1(\CPLD_Con_1.PMU_OC_2_8[30] ), .Q1(\CPLD_Reg_1/regtable[15][14] )); + SLICE_576 SLICE_576( .D1(\CPLD_Con_1/N_100 ), .C1(\CPLD_Con_1/N_95 ), + .B1(\DC_Con2[6] ), .A1(\DC_Con2[5] ), .D0(\CPLD_Con_1/N_100 ), + .C0(\CPLD_Con_1/N_95 ), .B0(\DC_Con2[6] ), .A0(\DC_Con2[5] ), + .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_2_8[29] ), .Q0(\CPLD_Reg_1/regtable[15][15] ), + .F1(\CPLD_Con_1.PMU_OC_2_8[31] ), .Q1(\CPLD_Reg_1/regtable[15][16] )); + SLICE_577 SLICE_577( .D1(\CPLD_Con_1/N_99 ), .C1(\CPLD_Con_1/N_95 ), + .B1(\DC_Con2[6] ), .A1(\DC_Con2[5] ), .D0(\CPLD_Con_1/N_99 ), + .C0(\CPLD_Con_1/N_95 ), .B0(\DC_Con2[6] ), .A0(\DC_Con2[5] ), + .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_2_8[13] ), .Q0(\CPLD_Reg_1/regtable[14][2] ), + .F1(\CPLD_Con_1.PMU_OC_2_8[15] ), .Q1(\CPLD_Reg_1/regtable[14][3] )); + SLICE_578 SLICE_578( .D1(\CPLD_Con_1/N_100 ), .C1(\CPLD_Con_1/N_96 ), + .B1(\DC_Con2[6] ), .A1(\DC_Con2[5] ), .D0(\CPLD_Con_1/N_100 ), + .C0(\CPLD_Con_1/N_96 ), .B0(\DC_Con2[6] ), .A0(\DC_Con2[5] ), + .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_2_8[19] ), .Q0(\CPLD_Reg_1/regtable[14][6] ), + .F1(\CPLD_Con_1.PMU_OC_2_8[23] ), .Q1(\CPLD_Reg_1/regtable[14][7] )); + SLICE_579 SLICE_579( .D1(\CPLD_Con_1/N_102 ), .C1(\CPLD_Con_1/N_96 ), + .B1(\DC_Con2[6] ), .A1(\DC_Con2[5] ), .D0(\CPLD_Con_1/N_102 ), + .C0(\CPLD_Con_1/N_96 ), .B0(\DC_Con2[6] ), .A0(\DC_Con2[5] ), + .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_2_8[20] ), .Q0(\CPLD_Reg_1/regtable[14][8] ), + .F1(\CPLD_Con_1.PMU_OC_2_8[22] ), .Q1(\CPLD_Reg_1/regtable[14][9] )); + SLICE_580 SLICE_580( .D1(\CPLD_Con_1/dc_slot_flag[0] ), + .C1(\CPLD_Con_1/dc_slot_flag[1] ), .B1(\CPLD_Con_1/dc_slot_flag[2] ), + .A1(\CPLD_Con_1/dc_slot_flag[3] ), .D0(\CPLD_Con_1/dc_slot_flag[3] ), + .C0(\CPLD_Con_1/dc_slot_flag[2] ), .B0(\CPLD_Con_1/dc_slot_flag[1] ), + .A0(\CPLD_Con_1/dc_slot_flag[0] ), .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/un1_DMM_en_1_sqmuxa_tz ), + .Q0(\CPLD_Reg_1/regtable[7][11] ), .F1(\CPLD_Con_1/g0_13_rn_0 ), + .Q1(\CPLD_Reg_1/regtable[7][12] )); + CPLD_Reg_1_SLICE_581 \CPLD_Reg_1/SLICE_581 ( .D1(\reg_addr_fast[2] ), + .C1(\reg_addr_fast[0] ), .B1(\reg_addr[1] ), .A1(\CPLD_Reg_1/N_1185 ), + .D0(\reg_addr[1] ), .C0(\reg_addr_fast[0] ), .B0(\CPLD_Reg_1/N_1185 ), + .A0(\reg_addr_fast[2] ), .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][4] ), + .F1(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .Q1(\CPLD_Reg_1/regtable[0][5] )); + CPLD_Reg_1_SLICE_582 \CPLD_Reg_1/SLICE_582 ( .D1(\reg_addr_fast[2] ), + .C1(reg_addr_0_rep1), .B1(\reg_addr[1] ), .A1(\CPLD_Reg_1/N_1185 ), + .D0(\reg_addr_fast[2] ), .C0(reg_addr_0_rep1), .B0(\reg_addr[1] ), + .A0(\CPLD_Reg_1/N_1185 ), .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][0] ), + .F1(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .Q1(\CPLD_Reg_1/regtable[0][10] )); + CPLD_Reg_1_SLICE_583 \CPLD_Reg_1/SLICE_583 ( .D1(\reg_addr_fast[2] ), + .C1(\reg_addr_fast[0] ), .B1(\reg_addr[1] ), .A1(\CPLD_Reg_1/N_1185 ), + .D0(\reg_addr_fast[2] ), .C0(\reg_addr_fast[0] ), .B0(\reg_addr[1] ), + .A0(\CPLD_Reg_1/N_1185 ), .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][8] ), + .F1(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .Q1(\CPLD_Reg_1/regtable[0][9] )); + CPLD_Reg_1_SLICE_584 \CPLD_Reg_1/SLICE_584 ( .D1(\reg_addr_fast[3] ), + .C1(\reg_addr_fast[2] ), .B1(\reg_addr_fast[0] ), .A1(\reg_addr[1] ), + .D0(\reg_addr_fast[3] ), .C0(\reg_addr_fast[2] ), .B0(\reg_addr_fast[0] ), + .A0(\reg_addr[1] ), .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/un34_regtable_1_0_0 ), .Q0(\CPLD_Reg_1/regtable[10][15] ), + .F1(\CPLD_Reg_1/regtable[5]_1_sqmuxa_0_a2_0 ), + .Q1(\CPLD_Reg_1/regtable[10][16] )); + SLICE_585 SLICE_585( .C1(\DC_Con4[8] ), .B1(\DC_Con4[6] ), .A1(\DC_Con4[4] ), + .C0(\DC_Con4[4] ), .B0(\DC_Con4[6] ), .A0(\DC_Con4[8] ), .M1(\w_data[10] ), + .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_4_8[23] ), .Q0(\freq3_relay[0] ), + .F1(N_193), .Q1(\CPLD_Reg_1/regtable[4][10] )); + SLICE_586 SLICE_586( .C1(\DC_Con4[8] ), .B1(\DC_Con4[6] ), .A1(\DC_Con4[4] ), + .C0(\DC_Con4[4] ), .B0(\DC_Con4[6] ), .A0(\DC_Con4[8] ), .M1(\w_data[21] ), + .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(N_194), .Q0(\CPLD_Reg_1/regtable[2][20] ), + .F1(N_195), .Q1(\CPLD_Reg_1/regtable[2][21] )); + SLICE_587 SLICE_587( .C1(\DC_Con4[8] ), .B1(\DC_Con4[6] ), .A1(\DC_Con4[4] ), + .C0(\DC_Con4[4] ), .B0(\DC_Con4[6] ), .A0(\DC_Con4[8] ), .M1(\w_data[12] ), + .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_198 ), + .Q0(\CPLD_Reg_1/regtable[4][11] ), .F1(N_197), + .Q1(\CPLD_Reg_1/regtable[4][12] )); + SLICE_588 SLICE_588( .C1(\DC_Con4[4] ), .B1(\DC_Con4[6] ), .A1(\DC_Con4[8] ), + .D0(\DC_Con4[4] ), .C0(\DC_Con4[6] ), .B0(\DC_Con4[8] ), + .A0(\CPLD_Con_1/N_192 ), .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_4_8[12] ), .Q0(\freq2_relay[6] ), .F1(N_155_i), + .Q1(\freq2_relay[7] )); + SLICE_589 SLICE_589( .D1(\CPLD_Con_1/N_119 ), .C1(\CPLD_Con_1/N_113 ), + .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), .D0(\DC_Con1[7] ), .C0(\DC_Con1[8] ), + .B0(\CPLD_Con_1/N_113 ), .A0(\CPLD_Con_1/N_115 ), .M1(\w_data[9] ), + .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_8[21] ), + .Q0(\CPLD_Reg_1/regtable[12][8] ), .F1(\CPLD_Con_1.PMU_OC_1_8[7] ), + .Q1(\CPLD_Reg_1/regtable[12][9] )); + SLICE_590 SLICE_590( .D1(\DC_Con1[7] ), .C1(\DC_Con1[8] ), + .B1(\CPLD_Con_1/N_38 ), .A1(\CPLD_Con_1/N_114 ), .D0(\DC_Con1[7] ), + .C0(\DC_Con1[8] ), .B0(\CPLD_Con_1/N_38 ), .A0(\CPLD_Con_1/N_113 ), + .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_1_8[9] ), .Q0(\CPLD_Reg_1/regtable[13][8] ), + .F1(\CPLD_Con_1.PMU_OC_1_8[8] ), .Q1(\CPLD_Reg_1/regtable[13][9] )); + SLICE_591 SLICE_591( .D1(\DC_Con1[5] ), .C1(\DC_Con1[6] ), + .B1(\CPLD_Con_1/N_114 ), .A1(\CPLD_Con_1/N_118 ), .D0(\DC_Con1[5] ), + .C0(\DC_Con1[6] ), .B0(\CPLD_Con_1/N_114 ), .A0(\CPLD_Con_1/N_117 ), + .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_1_8[14] ), .Q0(\CPLD_Reg_1/regtable[13][0] ), + .F1(\CPLD_Con_1.PMU_OC_1_8[30] ), .Q1(\CPLD_Reg_1/regtable[13][10] )); + SLICE_592 SLICE_592( .D1(\CPLD_Con_1/N_140 ), .C1(\CPLD_Con_1/N_136 ), + .B1(\DC_Con3[6] ), .A1(\DC_Con3[5] ), .D0(\CPLD_Con_1/N_141 ), + .C0(\CPLD_Con_1/N_136 ), .B0(\DC_Con3[6] ), .A0(\DC_Con3[5] ), + .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_3_8[31] ), .Q0(\CPLD_Reg_1/regtable[1][8] ), + .F1(\CPLD_Con_1.PMU_OC_3_8[15] ), .Q1(\CPLD_Reg_1/regtable[1][9] )); + SLICE_593 SLICE_593( .C1(\CPLD_Con_1/N_150 ), .B1(\DC_Con3[6] ), + .A1(\DC_Con3[5] ), .C0(\CPLD_Con_1/N_150 ), .B0(\DC_Con3[6] ), + .A0(\DC_Con3[5] ), .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_3_8[12] ), .Q0(\CPLD_Reg_1/regtable[15][6] ), + .F1(\CPLD_Con_1.PMU_OC_3_8[14] ), .Q1(\CPLD_Reg_1/regtable[15][7] )); + SLICE_594 SLICE_594( .D1(\freq3_relay[9] ), .C1(\freq3_relay[8] ), + .B1(\freq3_relay[7] ), .A1(\CPLD_Con_1/N_305 ), .D0(\freq3_relay[8] ), + .C0(\freq3_relay[7] ), .B0(\CPLD_Con_1/N_357 ), .A0(\CPLD_Con_1/N_305 ), + .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.N_364 ), .Q0(\CPLD_Reg_1/regtable[12][19] ), + .F1(\CPLD_Con_1/g0_2_N_2L1_1_N_2L1 ), .Q1(\CPLD_Reg_1/regtable[12][1] )); + SLICE_595 SLICE_595( .C1(\CPLD_Con_1/N_111 ), .B1(\DC_Con2[6] ), + .A1(\DC_Con2[5] ), .C0(\CPLD_Con_1/N_111 ), .B0(\DC_Con2[6] ), + .A0(\DC_Con2[5] ), .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_2_8[12] ), .Q0(\CPLD_Reg_1/regtable[14][22] ), + .F1(\CPLD_Con_1.PMU_OC_2_8[14] ), .Q1(\CPLD_Reg_1/regtable[14][23] )); + SLICE_596 SLICE_596( .D1(\freq2_relay[8] ), .C1(\CPLD_Con_1/N_344 ), + .B1(\CPLD_Con_1/freq_slot_flag[3] ), .A1(\CPLD_Con_1/freq_slot_flag[1] ), + .D0(\freq2_relay[9] ), .C0(\CPLD_Con_1/N_344 ), + .B0(\CPLD_Con_1/freq_slot_flag[3] ), .A0(\CPLD_Con_1/freq_slot_flag[1] ), + .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_329 ), .Q0(\CPLD_Reg_1/regtable[10][8] ), + .F1(\CPLD_Con_1/DMM_en_22_0_a2_1[7] ), .Q1(\CPLD_Reg_1/regtable[10][9] )); + SLICE_597 SLICE_597( .C1(\freq4_relay[0] ), .B1(\freq3_relay[0] ), + .A1(\DC_Con1[0] ), .C0(\freq4_relay[0] ), .B0(\freq3_relay[0] ), + .A0(\DC_Con1[0] ), .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_6_0 ), .Q0(\CPLD_Reg_1/regtable[12][0] ), + .F1(\CPLD_Con_1/m2 ), .Q1(\CPLD_Reg_1/regtable[12][10] )); + SLICE_598 SLICE_598( .D1(i_rst_n_c), .C1(\CPLD_Con_1/freq_t ), + .B1(\CPLD_Con_1.exec_flag ), .A1(\CPLD_Con_1/OC_x17_0_sqmuxa_i_1 ), + .C0(i_rst_n_c), .B0(\CPLD_Con_1/freq_t ), .A0(\CPLD_Con_1.exec_flag ), + .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.io_RC_1_sqmuxa ), .Q0(\DC_Con2[0] ), + .F1(\CPLD_Con_1.OC_x17_0_sqmuxa_i ), .Q1(\CPLD_Reg_1/regtable[7][10] )); + SLICE_599 SLICE_599( .C1(\freq3_relay[3] ), .B1(\freq3_relay[2] ), + .A1(\freq3_relay[1] ), .C0(\freq3_relay[3] ), .B0(\freq3_relay[2] ), + .A0(\freq3_relay[1] ), .M1(\BUS_Con_1/recv_reg[22] ), + .M0(\BUS_Con_1/recv_reg[21] ), .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), + .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_30 ), .Q0(\BUS_Con_1/recv_reg[22] ), + .F1(\CPLD_Con_1/g0_14_N_2L1 ), .Q1(\BUS_Con_1/recv_reg[23] )); + SLICE_600 SLICE_600( .C1(N_233), .B1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), + .A1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .C0(N_233), + .B0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), + .A0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .M1(\w_data[3] ), + .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.RC_RLSel_13[8] ), .Q0(\freq3_relay[2] ), + .F1(\CPLD_Con_1.RC_RLSel_13[4] ), .Q1(\freq3_relay[3] )); + SLICE_601 SLICE_601( .C1(N_232), .B1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), + .A1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .C0(N_232), + .B0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), + .A0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .M1(\w_data[23] ), + .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.RC_RLSel_13[7] ), + .Q0(\CPLD_Reg_1/regtable[4][22] ), .F1(\CPLD_Con_1.RC_RLSel_13[15] ), + .Q1(\CPLD_Reg_1/regtable[4][23] )); + SLICE_602 SLICE_602( .C1(N_235), .B1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), + .A1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .C0(N_235), + .B0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), + .A0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .M1(\w_data[21] ), + .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.RC_RLSel_13[6] ), + .Q0(\CPLD_Reg_1/regtable[4][20] ), .F1(\CPLD_Con_1.RC_RLSel_13[10] ), + .Q1(\CPLD_Reg_1/regtable[4][21] )); + SLICE_603 SLICE_603( .C1(N_234), .B1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), + .A1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .C0(N_234), + .B0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), + .A0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .M1(\w_data[1] ), + .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.RC_RLSel_13[5] ), + .Q0(\CPLD_Reg_1/regtable[4][19] ), .F1(\CPLD_Con_1.RC_RLSel_13[9] ), + .Q1(\freq3_relay[1] )); + CPLD_Reg_1_SLICE_604 \CPLD_Reg_1/SLICE_604 ( .C1(\reg_addr_fast[2] ), + .B1(\reg_addr[1] ), .A1(\CPLD_Reg_1/N_1171 ), .C0(\reg_addr_fast[2] ), + .B0(\reg_addr[1] ), .A0(\CPLD_Reg_1/N_1171 ), .M1(\w_data[21] ), + .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), + .Q0(\CPLD_Reg_1/regtable[0][20] ), .F1(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), + .Q1(\CPLD_Reg_1/regtable[0][21] )); + BUS_Con_1_SLICE_605 \BUS_Con_1/SLICE_605 ( .C1(\BUS_Con_1/sclk_sync[1] ), + .B1(\BUS_Con_1.sclk_sync[0] ), .A1(\BUS_Con_1/cs_sync[1] ), + .D0(\BUS_Con_1/cs_sync[1] ), .C0(\BUS_Con_1.sclk_sync[0] ), + .B0(\BUS_Con_1/sclk_sync[1] ), .A0(i_rst_n_c), + .M1(\BUS_Con_1/recv_reg[13] ), .M0(\BUS_Con_1/recv_reg[12] ), + .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), + .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), + .F0(i_rst_n_c_i_en), .Q0(\BUS_Con_1/recv_reg[13] ), + .F1(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .Q1(\BUS_Con_1/recv_reg[14] )); + SLICE_606 SLICE_606( .C1(reg_busy), .B1(\BUS_Con_1/state[1] ), + .A1(\BUS_Con_1/data_ready ), .D0(reg_busy), .C0(\BUS_Con_1/state[1] ), + .B0(\BUS_Con_1/state[0] ), .A0(\BUS_Con_1/data_ready ), .M1(\w_data[1] ), + .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_237_i ), + .Q0(\CPLD_Reg_1/regtable[10][19] ), .F1(\BUS_Con_1/N_249 ), + .Q1(\CPLD_Reg_1/regtable[10][1] )); + SLICE_607 SLICE_607( .B1(\DC_Con2[8] ), .A1(\DC_Con2[4] ), .D0(\DC_Con2[4] ), + .C0(\DC_Con2[8] ), .B0(\CPLD_Con_1/N_43 ), .A0(\CPLD_Con_1/N_95 ), + .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_2_8[24] ), .Q0(\CPLD_Reg_1/regtable[14][17] ), + .F1(\CPLD_Con_1/g0_2_N_5L7_N_6L9_0_1 ), .Q1(\CPLD_Reg_1/regtable[14][18] )); + SLICE_608 SLICE_608( .B1(\freq3_relay[7] ), .A1(\CPLD_Con_1/N_305 ), + .B0(\freq3_relay[7] ), .A0(\CPLD_Con_1/N_305 ), .M1(\w_data[10] ), + .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_freq_relay3lt8 ), + .Q0(\DC_Con4[0] ), .F1(\CPLD_Con_1/N_90 ), + .Q1(\CPLD_Reg_1/regtable[9][10] )); + SLICE_609 SLICE_609( .C1(\CPLD_Con_1/N_215 ), .B1(\CPLD_Con_1/g0_8_1_0 ), + .A1(\CPLD_Con_1/RC_VISel40 ), .C0(\CPLD_Con_1/N_215 ), + .B0(\CPLD_Con_1/g0_8_1_0 ), .A0(\CPLD_Con_1/RC_VISel39 ), .M1(\w_data[1] ), + .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_2_0_0 ), + .Q0(\DC_Con2[19] ), .F1(\CPLD_Con_1/un1_exec_flag_3_0_0 ), + .Q1(\DC_Con2[1] )); + SLICE_610 SLICE_610( .D1(\DC_Con2[8] ), .C1(\DC_Con1[8] ), + .B1(\CPLD_Con_1/dc_slot_flag_fast[1] ), + .A1(\CPLD_Con_1/dc_slot_flag_fast[0] ), .D0(\DC_Con2[20] ), + .C0(\DC_Con1[20] ), .B0(\CPLD_Con_1/dc_slot_flag_fast[1] ), + .A0(\CPLD_Con_1/dc_slot_flag_fast[0] ), .M1(\w_data[1] ), + .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[3] ), + .Q0(\DC_Con3[19] ), .F1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[4] ), + .Q1(\DC_Con3[1] )); + SLICE_611 SLICE_611( .D1(\DC_Con2[17] ), .C1(\DC_Con1[17] ), + .B1(\CPLD_Con_1/dc_slot_flag[1] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), + .D0(\DC_Con2[4] ), .C0(\DC_Con1[4] ), .B0(\CPLD_Con_1/dc_slot_flag[1] ), + .A0(\CPLD_Con_1/dc_slot_flag[0] ), .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0_0[0] ), .Q0(\DC_Con3[0] ), + .F1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ), + .Q1(\CPLD_Reg_1/regtable[8][10] )); + SLICE_612 SLICE_612( .D1(\DC_Con2[7] ), .C1(\DC_Con1[7] ), + .B1(\CPLD_Con_1/dc_slot_flag[1] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), + .D0(\DC_Con1[5] ), .C0(\CPLD_Reg_1.regtable[7]_fast[5] ), + .B0(\CPLD_Con_1/dc_slot_flag[1] ), .A0(\CPLD_Con_1/dc_slot_flag[0] ), + .M0(\w_data[7] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[1] ), + .Q0(\CPLD_Reg_1.regtable[7]_fast[7] ), + .F1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[3] )); + SLICE_613 SLICE_613( .C1(N_234), .B1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), + .A1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .C0(N_235), + .B0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), + .A0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .M1(\w_data[14] ), + .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.RC_RLSel_13[14] ), + .Q0(\CPLD_Reg_1/regtable[4][13] ), .F1(\CPLD_Con_1.RC_RLSel_13[13] ), + .Q1(\CPLD_Reg_1/regtable[4][14] )); + SLICE_614 SLICE_614( .D1(\DC_Con2[3] ), + .C1(\CPLD_Reg_1.regtable[7]_fast[7] ), + .B1(\CPLD_Reg_1.regtable[7]_fast[6] ), + .A1(\CPLD_Reg_1.regtable[7]_fast[5] ), + .B0(\CPLD_Reg_1.regtable[7]_fast[6] ), + .A0(\CPLD_Reg_1.regtable[7]_fast[5] ), .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/g0_2_1 ), .Q0(\DC_Con1[8] ), .F1(\CPLD_Con_1/g0_21_N_2L1 ), + .Q1(\DC_Con1[9] )); + SLICE_615 SLICE_615( .B1(\DC_Con4[20] ), .A1(\DC_Con4[19] ), + .B0(\DC_Con4[20] ), .A0(\DC_Con4[19] ), .M1(\w_data[1] ), + .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_10_N_2L1 ), .Q0(\DC_Con1[19] ), + .F1(\CPLD_Con_1/g0_12_N_2L1 ), .Q1(\DC_Con1[1] )); + SLICE_616 SLICE_616( .B1(\CPLD_Con_1/N_311 ), + .A1(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), .B0(\CPLD_Con_1/N_311 ), + .A0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/DMM_en_22_0_a2_1_1[12] ), + .Q0(\CPLD_Reg_1/regtable[11][0] ), .F1(\CPLD_Con_1/DMM_en_22_0_a2_2_1[4] ), + .Q1(\CPLD_Reg_1/regtable[11][10] )); + CPLD_Con_1_SLICE_617 \CPLD_Con_1/SLICE_617 ( .B1(\CPLD_Con_1/freq_t ), + .A1(\CPLD_Con_1.exec_flag ), .C0(\CPLD_Con_1/freq_t ), + .B0(\CPLD_Con_1.exec_flag ), .A0(\CPLD_Con_1/dc_t ), .M1(\DC_Con4[0] ), + .M0(\DC_Con3[0] ), .CE(\CPLD_Con_1/RC_Tx_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/dc_t_RNI2Q6P8_0 ), + .Q0(\CPLD_Con_1/dc_slot_flag_fast[2] ), .F1(\CPLD_Con_1/freq_t_RNI8PH26 ), + .Q1(\CPLD_Con_1/dc_slot_flag_fast[3] )); + CPLD_Reg_1_SLICE_618 \CPLD_Reg_1/SLICE_618 ( .B1(\CPLD_Reg_1/state[1] ), + .A1(\CPLD_Reg_1/state[0] ), .C0(\CPLD_Reg_1/state[1] ), + .B0(\CPLD_Reg_1/state[0] ), .A0(\CPLD_Reg_1/regtable[1]_1_sqmuxa ), + .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/un12_i ), .Q0(\CPLD_Reg_1/regtable[0][11] ), + .F1(\CPLD_Reg_1/state_6_d_i ), .Q1(\CPLD_Reg_1/regtable[0][12] )); + CPLD_Reg_1_SLICE_619 \CPLD_Reg_1/SLICE_619 ( .B1(\reg_addr_fast[0] ), + .A1(\reg_addr[1] ), .D0(\reg_addr_fast[2] ), .C0(\reg_addr_fast[0] ), + .B0(\reg_addr[1] ), .A0(\CPLD_Reg_1/N_1185 ), .M1(\w_data[3] ), + .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), + .Q0(\CPLD_Reg_1/regtable[0][2] ), .F1(\CPLD_Reg_1/N_1186 ), + .Q1(\CPLD_Reg_1/regtable[0][3] )); + SLICE_620 SLICE_620( .B1(\DC_Con4[4] ), .A1(\CPLD_Con_1/dc_slot_flag[3] ), + .D0(\DC_Con4[4] ), .C0(\DC_Con4[6] ), .B0(\DC_Con4[8] ), + .A0(\CPLD_Con_1/N_190 ), .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_4_8[30] ), .Q0(\CPLD_Reg_1/regtable[3][19] ), + .F1(\CPLD_Con_1/N_70 ), .Q1(\freq2_relay[1] )); + SLICE_621 SLICE_621( .B1(\CPLD_Con_1/un1_i_DC_Con1_1[5] ), + .A1(\CPLD_Con_1/un1_i_DC_Con1_1[4] ), .B0(\CPLD_Con_1/N_311 ), + .A0(\CPLD_Con_1/un1_i_DC_Con1_1[4] ), .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/DMM_en_22_2[16] ), .Q0(\CPLD_Reg_1/regtable[11][2] ), + .F1(\CPLD_Con_1/un1_DMM_en_1[0] ), .Q1(\CPLD_Reg_1/regtable[11][3] )); + SLICE_622 SLICE_622( .D1(\DC_Con2[9] ), .C1(\DC_Con1[9] ), + .B1(\CPLD_Con_1/dc_slot_flag_fast[1] ), + .A1(\CPLD_Con_1/dc_slot_flag_fast[0] ), .D0(\CPLD_Con_1/N_43 ), + .C0(\DC_Con2[9] ), .B0(\DC_Con2[7] ), .A0(\CPLD_Con_1/RC_VISel39 ), + .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/PMU_OC_2_8[1] ), .Q0(\CPLD_Reg_1/regtable[15][22] ), + .F1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[5] ), + .Q1(\CPLD_Reg_1/regtable[15][23] )); + SLICE_623 SLICE_623( .B1(\DC_Con4[7] ), .A1(\CPLD_Con_1/dc_slot_flag[3] ), + .D0(\CPLD_Con_1/N_227 ), .C0(\CPLD_Con_1/N_188 ), .B0(\DC_Con4[7] ), + .A0(\DC_Con4[5] ), .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.PMU_OC_4_8[19] ), .Q0(\freq1_relay[2] ), + .F1(\CPLD_Con_1/i_DC_Con4_m[7] ), .Q1(\freq1_relay[3] )); + SLICE_624 SLICE_624( .B1(\CPLD_Con_1/dc_slot_flag[3] ), + .A1(\CPLD_Con_1/dc_slot_flag[1] ), .D0(\DC_Con4[21] ), .C0(\DC_Con3[21] ), + .B0(\CPLD_Con_1/dc_slot_flag[3] ), .A0(\CPLD_Con_1/dc_slot_flag[2] ), + .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[4] ), .Q0(\DC_Con3[22] ), + .F1(\CPLD_Con_1/m9_0_a5_1_1 ), .Q1(\DC_Con3[23] )); + SLICE_625 SLICE_625( .B1(\DC_Con1[20] ), .A1(\DC_Con1[19] ), + .D0(\DC_Con2[19] ), .C0(\DC_Con1[19] ), + .B0(\CPLD_Con_1/dc_slot_flag_1_rep1 ), + .A0(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .M1(\w_data[18] ), + .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[2] ), + .Q0(\DC_Con3[17] ), .F1(\CPLD_Con_1/N_57 ), .Q1(\DC_Con3[18] )); + SLICE_626 SLICE_626( .B1(\freq3_relay[8] ), .A1(\freq3_relay[7] ), + .B0(\freq3_relay[9] ), .A0(\freq3_relay[8] ), .M1(\w_data[16] ), + .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/OC_x0138_3 ), + .Q0(\CPLD_Reg_1/regtable[12][15] ), .F1(\CPLD_Con_1/g2_0_0 ), + .Q1(\CPLD_Reg_1/regtable[12][16] )); + SLICE_627 SLICE_627( .B1(\CPLD_Reg_1.regtable[9]_fast[8] ), + .A1(\CPLD_Con_1/dc_slot_flag_fast[3] ), .B0(\DC_Con4[20] ), + .A0(\CPLD_Con_1/dc_slot_flag_fast[3] ), .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_173 ), .Q0(\DC_Con3[2] ), + .F1(\CPLD_Con_1/i_DC_Con4_m[8] ), .Q1(\DC_Con3[3] )); + SLICE_628 SLICE_628( .C1(i_rst_n_c), .B1(\BUS_Con_1/miso_shift[30] ), + .A1(\BUS_Con_1/cs_sync[1] ), .B0(i_rst_n_c), .A0(\CPLD_Con_1/RC_VISel38 ), + .M1(\DC_Con4[0] ), .M0(\DC_Con3[0] ), .CE(\CPLD_Con_1/RC_Tx_1_sqmuxa ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/dc_slot_flag_0_rep1_RNI421QK ), + .Q0(\CPLD_Con_1/dc_slot_flag[2] ), .F1(i_rst_n_c_i_rst), + .Q1(\CPLD_Con_1/dc_slot_flag[3] )); + CPLD_Reg_1_SLICE_629 \CPLD_Reg_1/SLICE_629 ( .C1(\reg_addr_fast[2] ), + .B1(\reg_addr[1] ), .A1(\CPLD_Reg_1/N_1171 ), .C0(\reg_addr_fast[3] ), + .B0(\reg_addr_fast[2] ), .A0(\CPLD_Reg_1/regtable[7]_1_sqmuxa_2 ), + .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][17] ), + .F1(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .Q1(\CPLD_Reg_1/regtable[0][18] )); + CPLD_Reg_1_SLICE_630 \CPLD_Reg_1/SLICE_630 ( .C1(\CPLD_Reg_1/reg_err_flag ), + .B1(cpld_err_flag), .A1(bus_err_flag), .D0(wr_flag), + .C0(\CPLD_Reg_1/reg_err_flag ), .B0(\CPLD_Reg_1/state[1] ), + .A0(\CPLD_Reg_1/state[0] ), .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/un11_0 ), .Q0(\CPLD_Reg_1/regtable[10][13] ), .F1(o_err_c), + .Q1(\CPLD_Reg_1/regtable[10][14] )); + SLICE_631 SLICE_631( .C1(\BUS_Con_1/bit_cnt[3] ), + .B1(\BUS_Con_1/bit_cnt[1] ), .A1(\BUS_Con_1/bit_cnt[0] ), + .B0(\BUS_Con_1/sclk_sync[1] ), .A0(\BUS_Con_1.sclk_sync[0] ), + .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/N_244 ), .Q0(\CPLD_Reg_1/regtable[10][20] ), + .F1(\BUS_Con_1/err_flag_1_sqmuxa_0_a2_0_0 ), + .Q1(\CPLD_Reg_1/regtable[10][21] )); + SLICE_632 SLICE_632( .B1(\DC_Con4[5] ), .A1(\CPLD_Con_1/dc_slot_flag[3] ), + .D0(\CPLD_Con_1/N_363 ), .C0(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), + .B0(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), .A0(\CPLD_Con_1/DMM_en_22_0_0[15] ), + .M1(\r_data[12] ), .M0(\r_data[11] ), .CE(con_rvalid), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.DMM_en_22[15] ), + .Q0(\BUS_Con_1/tx_buffer[11] ), .F1(\CPLD_Con_1/i_DC_Con4_m[5] ), + .Q1(\BUS_Con_1/tx_buffer[12] )); + SLICE_633 SLICE_633( .D1(\freq4_relay[8] ), .C1(\CPLD_Con_1/N_356 ), + .B1(\CPLD_Con_1/N_342 ), .A1(\CPLD_Con_1/freq_t ), + .B0(\CPLD_Con_1/freq_slot_flag[3] ), .A0(\CPLD_Con_1/freq_slot_flag[1] ), + .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_353 ), .Q0(\CPLD_Reg_1/regtable[11][11] ), + .F1(\CPLD_Con_1/N_364 ), .Q1(\CPLD_Reg_1/regtable[11][12] )); + SLICE_634 SLICE_634( .B1(\DC_Con3[9] ), + .A1(\CPLD_Con_1/dc_slot_flag_fast[2] ), .C0(\CPLD_Con_1/N_137 ), + .B0(\DC_Con3[6] ), .A0(\DC_Con3[5] ), .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/PMU_OC_3_8[1] ), .Q0(\CPLD_Reg_1/regtable[2][15] ), + .F1(\CPLD_Con_1/i_DC_Con3_m[9] ), .Q1(\CPLD_Reg_1/regtable[2][16] )); + CPLD_Reg_1_SLICE_672 \CPLD_Reg_1/SLICE_672 ( .M1(\w_data[4] ), + .M0(\w_data[5] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), + .CLK(i_sys_clk_c), .Q0(\CPLD_Reg_1.regtable[9]_fast[5] ), + .Q1(\CPLD_Reg_1.regtable[9]_fast[4] )); + CPLD_Reg_1_SLICE_673 \CPLD_Reg_1/SLICE_673 ( .M1(\w_data[6] ), + .M0(\w_data[7] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), + .CLK(i_sys_clk_c), .Q0(\CPLD_Reg_1.regtable[9]_fast[7] ), + .Q1(\CPLD_Reg_1.regtable[9]_fast[6] )); + CPLD_Reg_1_SLICE_830 \CPLD_Reg_1/SLICE_830 ( .M1(\w_data[19] ), + .M0(\w_data[1] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), + .CLK(i_sys_clk_c), .Q0(\DC_Con4[1] ), .Q1(\DC_Con4[19] )); + CPLD_Reg_1_SLICE_831 \CPLD_Reg_1/SLICE_831 ( .M1(\w_data[2] ), + .M0(\w_data[3] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), + .CLK(i_sys_clk_c), .Q0(\DC_Con4[3] ), .Q1(\DC_Con4[2] )); + CPLD_Reg_1_SLICE_832 \CPLD_Reg_1/SLICE_832 ( .M1(\w_data[4] ), + .M0(\w_data[5] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), + .CLK(i_sys_clk_c), .Q0(\DC_Con4[5] ), .Q1(\DC_Con4[4] )); + CPLD_Reg_1_SLICE_833 \CPLD_Reg_1/SLICE_833 ( .M1(\w_data[6] ), + .M0(\w_data[7] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), + .CLK(i_sys_clk_c), .Q0(\DC_Con4[7] ), .Q1(\DC_Con4[6] )); + CPLD_Reg_1_SLICE_834 \CPLD_Reg_1/SLICE_834 ( .M1(\w_data[8] ), + .M0(\w_data[9] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), + .CLK(i_sys_clk_c), .Q0(\DC_Con4[9] ), .Q1(\DC_Con4[8] )); + CPLD_Reg_1_SLICE_835 \CPLD_Reg_1/SLICE_835 ( .M1(\w_data[17] ), + .M0(\w_data[18] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), + .CLK(i_sys_clk_c), .Q0(\DC_Con4[18] ), .Q1(\DC_Con4[17] )); + BUS_Con_1_SLICE_864 \BUS_Con_1/SLICE_864 ( .M1(\BUS_Con_1/recv_reg[24] ), + .M0(\BUS_Con_1/recv_reg[24] ), .CE(\BUS_Con_1/N_237_i ), + .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), + .Q0(reg_addr_0_rep2), .Q1(reg_addr_0_rep1)); + BUS_Con_1_SLICE_865 \BUS_Con_1/SLICE_865 ( .M1(\BUS_Con_1/recv_reg[26] ), + .M0(\BUS_Con_1/recv_reg[26] ), .CE(\BUS_Con_1/N_237_i ), + .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), + .Q0(reg_addr_2_rep2), .Q1(reg_addr_2_rep1)); + BUS_Con_1_SLICE_866 \BUS_Con_1/SLICE_866 ( .M1(\BUS_Con_1/recv_reg[27] ), + .M0(\BUS_Con_1/recv_reg[27] ), .CE(\BUS_Con_1/N_237_i ), + .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), + .Q0(reg_addr_3_rep2), .Q1(reg_addr_3_rep1)); + BUS_Con_1_SLICE_867 \BUS_Con_1/SLICE_867 ( .M1(\BUS_Con_1/recv_reg[24] ), + .M0(\BUS_Con_1/recv_reg[26] ), .CE(\BUS_Con_1/N_237_i ), + .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), + .Q0(\reg_addr_fast[2] ), .Q1(\reg_addr_fast[0] )); + BUS_Con_1_SLICE_872 \BUS_Con_1/SLICE_872 ( .M0(\BUS_Con_1/recv_reg[9] ), + .CE(\BUS_Con_1/N_237_i ), + .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), + .Q0(\w_data[9] )); + BUS_Con_1_SLICE_873 \BUS_Con_1/SLICE_873 ( .M1(\BUS_Con_1/recv_reg[10] ), + .M0(\BUS_Con_1/recv_reg[11] ), .CE(\BUS_Con_1/N_237_i ), + .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), + .Q0(\w_data[11] ), .Q1(\w_data[10] )); + o_miso o_miso_I( .IOLDO(miso_shift31), .PADDT(\BUS_Con_1.cs_sync_rep0[1] ), + .o_miso(o_miso)); + o_miso_MGIOL o_miso_MGIOL( .IOLDO(miso_shift31), .OPOS(i_rst_n_c_i_rst), + .CE(i_rst_n_c_i_en), .CLK(i_sys_clk_c)); + o_wready o_wready_I( .PADDO(o_wready_c), .o_wready(o_wready)); + i_sys_clk i_sys_clk_I( .PADDI(i_sys_clk_c), .i_sys_clk(i_sys_clk)); + o_PMU_OC_4_31_ \o_PMU_OC_4[31]_I ( .IOLDO(\o_PMU_OC_4_c[31] ), + .oPMUOC431(o_PMU_OC_4[31])); + o_PMU_OC_4_31__MGIOL \o_PMU_OC_4[31]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[31] ), + .OPOS(\CPLD_Con_1.PMU_OC_4_8[31] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_4_30_ \o_PMU_OC_4[30]_I ( .IOLDO(\o_PMU_OC_4_c[30] ), + .oPMUOC430(o_PMU_OC_4[30])); + o_PMU_OC_4_30__MGIOL \o_PMU_OC_4[30]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[30] ), + .OPOS(\CPLD_Con_1.PMU_OC_4_8[30] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_4_29_ \o_PMU_OC_4[29]_I ( .IOLDO(\o_PMU_OC_4_c[29] ), + .oPMUOC429(o_PMU_OC_4[29])); + o_PMU_OC_4_29__MGIOL \o_PMU_OC_4[29]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[29] ), + .OPOS(\CPLD_Con_1.PMU_OC_4_8[29] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_4_28_ \o_PMU_OC_4[28]_I ( .IOLDO(\o_PMU_OC_4_c[28] ), + .oPMUOC428(o_PMU_OC_4[28])); + o_PMU_OC_4_28__MGIOL \o_PMU_OC_4[28]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[28] ), + .OPOS(\CPLD_Con_1.PMU_OC_4_8[28] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_4_27_ \o_PMU_OC_4[27]_I ( .IOLDO(\o_PMU_OC_4_c[27] ), + .oPMUOC427(o_PMU_OC_4[27])); + o_PMU_OC_4_27__MGIOL \o_PMU_OC_4[27]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[27] ), + .OPOS(\CPLD_Con_1.PMU_OC_4_8[27] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_4_26_ \o_PMU_OC_4[26]_I ( .IOLDO(\o_PMU_OC_4_c[26] ), + .oPMUOC426(o_PMU_OC_4[26])); + o_PMU_OC_4_26__MGIOL \o_PMU_OC_4[26]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[26] ), + .OPOS(\CPLD_Con_1.PMU_OC_4_8[26] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_4_25_ \o_PMU_OC_4[25]_I ( .IOLDO(\o_PMU_OC_4_c[25] ), + .oPMUOC425(o_PMU_OC_4[25])); + o_PMU_OC_4_25__MGIOL \o_PMU_OC_4[25]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[25] ), + .OPOS(\CPLD_Con_1.PMU_OC_4_8[25] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_4_24_ \o_PMU_OC_4[24]_I ( .IOLDO(\o_PMU_OC_4_c[24] ), + .oPMUOC424(o_PMU_OC_4[24])); + o_PMU_OC_4_24__MGIOL \o_PMU_OC_4[24]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[24] ), + .OPOS(\CPLD_Con_1.PMU_OC_4_8[24] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_4_23_ \o_PMU_OC_4[23]_I ( .IOLDO(\o_PMU_OC_4_c[23] ), + .oPMUOC423(o_PMU_OC_4[23])); + o_PMU_OC_4_23__MGIOL \o_PMU_OC_4[23]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[23] ), + .OPOS(\CPLD_Con_1.PMU_OC_4_8[23] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(\PMU_OC_4_8_0_a2_RNIS7H393[18] ), .CLK(i_sys_clk_c)); + o_PMU_OC_4_22_ \o_PMU_OC_4[22]_I ( .IOLDO(\o_PMU_OC_4_c[22] ), + .oPMUOC422(o_PMU_OC_4[22])); + o_PMU_OC_4_22__MGIOL \o_PMU_OC_4[22]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[22] ), + .OPOS(N_193), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(\PMU_OC_4_8_0_a2_RNIS7H393[18] ), .CLK(i_sys_clk_c)); + o_PMU_OC_4_21_ \o_PMU_OC_4[21]_I ( .IOLDO(\o_PMU_OC_4_c[21] ), + .oPMUOC421(o_PMU_OC_4[21])); + o_PMU_OC_4_21__MGIOL \o_PMU_OC_4[21]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[21] ), + .OPOS(\CPLD_Con_1.PMU_OC_4_8[21] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_4_20_ \o_PMU_OC_4[20]_I ( .PADDO(\o_PMU_OC_4_c[20] ), + .oPMUOC420(o_PMU_OC_4[20])); + o_PMU_OC_4_19_ \o_PMU_OC_4[19]_I ( .IOLDO(\o_PMU_OC_4_c[19] ), + .oPMUOC419(o_PMU_OC_4[19])); + o_PMU_OC_4_19__MGIOL \o_PMU_OC_4[19]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[19] ), + .OPOS(\CPLD_Con_1.PMU_OC_4_8[19] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_4_18_ \o_PMU_OC_4[18]_I ( .IOLDO(\o_PMU_OC_4_c[18] ), + .oPMUOC418(o_PMU_OC_4[18])); + o_PMU_OC_4_18__MGIOL \o_PMU_OC_4[18]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[18] ), + .OPOS(N_197), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(\PMU_OC_4_8_0_a2_RNIS7H393[18] ), .CLK(i_sys_clk_c)); + o_PMU_OC_4_17_ \o_PMU_OC_4[17]_I ( .IOLDO(\o_PMU_OC_4_c[17] ), + .oPMUOC417(o_PMU_OC_4[17])); + o_PMU_OC_4_17__MGIOL \o_PMU_OC_4[17]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[17] ), + .OPOS(\CPLD_Con_1.PMU_OC_4_8[17] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_4_16_ \o_PMU_OC_4[16]_I ( .IOLDO(\o_PMU_OC_4_c[16] ), + .oPMUOC416(o_PMU_OC_4[16])); + o_PMU_OC_4_16__MGIOL \o_PMU_OC_4[16]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[16] ), + .OPOS(\CPLD_Con_1.N_315 ), .CE(\CPLD_Con_1.OC_x17_0_sqmuxa_i ), + .CLK(i_sys_clk_c)); + o_PMU_OC_4_15_ \o_PMU_OC_4[15]_I ( .IOLDO(\o_PMU_OC_4_c[15] ), + .oPMUOC415(o_PMU_OC_4[15])); + o_PMU_OC_4_15__MGIOL \o_PMU_OC_4[15]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[15] ), + .OPOS(\CPLD_Con_1.PMU_OC_4_8[15] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_4_14_ \o_PMU_OC_4[14]_I ( .IOLDO(\o_PMU_OC_4_c[14] ), + .oPMUOC414(o_PMU_OC_4[14])); + o_PMU_OC_4_14__MGIOL \o_PMU_OC_4[14]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[14] ), + .OPOS(\CPLD_Con_1.PMU_OC_4_8[14] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_4_13_ \o_PMU_OC_4[13]_I ( .IOLDO(\o_PMU_OC_4_c[13] ), + .oPMUOC413(o_PMU_OC_4[13])); + o_PMU_OC_4_13__MGIOL \o_PMU_OC_4[13]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[13] ), + .OPOS(\CPLD_Con_1.PMU_OC_4_8[13] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_4_12_ \o_PMU_OC_4[12]_I ( .IOLDO(\o_PMU_OC_4_c[12] ), + .oPMUOC412(o_PMU_OC_4[12])); + o_PMU_OC_4_12__MGIOL \o_PMU_OC_4[12]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[12] ), + .OPOS(\CPLD_Con_1.PMU_OC_4_8[12] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_4_11_ \o_PMU_OC_4[11]_I ( .IOLDO(\o_PMU_OC_4_c[11] ), + .oPMUOC411(o_PMU_OC_4[11])); + o_PMU_OC_4_11__MGIOL \o_PMU_OC_4[11]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[11] ), + .OPOS(\CPLD_Con_1.PMU_OC_4_8[11] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_4_10_ \o_PMU_OC_4[10]_I ( .IOLDO(\o_PMU_OC_4_c[10] ), + .oPMUOC410(o_PMU_OC_4[10])); + o_PMU_OC_4_10__MGIOL \o_PMU_OC_4[10]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[10] ), + .OPOS(\CPLD_Con_1.PMU_OC_4_8[10] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_4_9_ \o_PMU_OC_4[9]_I ( .IOLDO(\o_PMU_OC_4_c[9] ), + .oPMUOC49(o_PMU_OC_4[9])); + o_PMU_OC_4_9__MGIOL \o_PMU_OC_4[9]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[9] ), + .OPOS(\CPLD_Con_1.PMU_OC_4_8[9] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_4_8_ \o_PMU_OC_4[8]_I ( .IOLDO(\o_PMU_OC_4_c[8] ), + .oPMUOC48(o_PMU_OC_4[8])); + o_PMU_OC_4_8__MGIOL \o_PMU_OC_4[8]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[8] ), + .OPOS(\CPLD_Con_1.PMU_OC_4_8[8] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_4_7_ \o_PMU_OC_4[7]_I ( .IOLDO(\o_PMU_OC_4_c[7] ), + .oPMUOC47(o_PMU_OC_4[7])); + o_PMU_OC_4_7__MGIOL \o_PMU_OC_4[7]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[7] ), + .OPOS(N_194), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(\PMU_OC_4_8_0_a2_RNIS7H393[18] ), .CLK(i_sys_clk_c)); + o_PMU_OC_4_6_ \o_PMU_OC_4[6]_I ( .IOLDO(\o_PMU_OC_4_c[6] ), + .oPMUOC46(o_PMU_OC_4[6])); + o_PMU_OC_4_6__MGIOL \o_PMU_OC_4[6]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[6] ), + .OPOS(N_195), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(\PMU_OC_4_8_0_a2_RNIS7H393[18] ), .CLK(i_sys_clk_c)); + o_PMU_OC_4_5_ \o_PMU_OC_4[5]_I ( .PADDO(\o_PMU_OC_4_c[5] ), + .oPMUOC45(o_PMU_OC_4[5])); + o_PMU_OC_4_4_ \o_PMU_OC_4[4]_I ( .PADDO(\o_PMU_OC_4_c[4] ), + .oPMUOC44(o_PMU_OC_4[4])); + o_PMU_OC_4_3_ \o_PMU_OC_4[3]_I ( .IOLDO(\o_PMU_OC_4_c[3] ), + .oPMUOC43(o_PMU_OC_4[3])); + o_PMU_OC_4_3__MGIOL \o_PMU_OC_4[3]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[3] ), + .OPOS(\CPLD_Con_1.PMU_OC_4_8[3] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_4_2_ \o_PMU_OC_4[2]_I ( .IOLDO(\o_PMU_OC_4_c[2] ), + .oPMUOC42(o_PMU_OC_4[2])); + o_PMU_OC_4_2__MGIOL \o_PMU_OC_4[2]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[2] ), + .OPOS(N_155_i), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), + .LSR(\PMU_OC_4_8_0_a2_RNIS7H393[18] ), .CLK(i_sys_clk_c)); + o_PMU_OC_4_1_ \o_PMU_OC_4[1]_I ( .PADDO(\o_PMU_OC_4_c[1] ), + .oPMUOC41(o_PMU_OC_4[1])); + o_PMU_OC_4_0_ \o_PMU_OC_4[0]_I ( .IOLDO(\o_PMU_OC_4_c[0] ), + .oPMUOC40(o_PMU_OC_4[0])); + o_PMU_OC_4_0__MGIOL \o_PMU_OC_4[0]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[0] ), + .OPOS(\DMM_en_22_0_o2_RNI8QTBL[15] ), .CE(\CPLD_Con_1.OC_x17_0_sqmuxa_i ), + .CLK(i_sys_clk_c)); + o_PMU_OC_3_31_ \o_PMU_OC_3[31]_I ( .IOLDO(\o_PMU_OC_3_c[31] ), + .oPMUOC331(o_PMU_OC_3[31])); + o_PMU_OC_3_31__MGIOL \o_PMU_OC_3[31]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[31] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[31] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_30_ \o_PMU_OC_3[30]_I ( .IOLDO(\o_PMU_OC_3_c[30] ), + .oPMUOC330(o_PMU_OC_3[30])); + o_PMU_OC_3_30__MGIOL \o_PMU_OC_3[30]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[30] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[30] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_29_ \o_PMU_OC_3[29]_I ( .IOLDO(\o_PMU_OC_3_c[29] ), + .oPMUOC329(o_PMU_OC_3[29])); + o_PMU_OC_3_29__MGIOL \o_PMU_OC_3[29]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[29] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[29] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_28_ \o_PMU_OC_3[28]_I ( .IOLDO(\o_PMU_OC_3_c[28] ), + .oPMUOC328(o_PMU_OC_3[28])); + o_PMU_OC_3_28__MGIOL \o_PMU_OC_3[28]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[28] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[28] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_27_ \o_PMU_OC_3[27]_I ( .IOLDO(\o_PMU_OC_3_c[27] ), + .oPMUOC327(o_PMU_OC_3[27])); + o_PMU_OC_3_27__MGIOL \o_PMU_OC_3[27]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[27] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[27] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_26_ \o_PMU_OC_3[26]_I ( .IOLDO(\o_PMU_OC_3_c[26] ), + .oPMUOC326(o_PMU_OC_3[26])); + o_PMU_OC_3_26__MGIOL \o_PMU_OC_3[26]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[26] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[26] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_25_ \o_PMU_OC_3[25]_I ( .IOLDO(\o_PMU_OC_3_c[25] ), + .oPMUOC325(o_PMU_OC_3[25])); + o_PMU_OC_3_25__MGIOL \o_PMU_OC_3[25]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[25] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[25] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_24_ \o_PMU_OC_3[24]_I ( .IOLDO(\o_PMU_OC_3_c[24] ), + .oPMUOC324(o_PMU_OC_3[24])); + o_PMU_OC_3_24__MGIOL \o_PMU_OC_3[24]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[24] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[24] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_23_ \o_PMU_OC_3[23]_I ( .IOLDO(\o_PMU_OC_3_c[23] ), + .oPMUOC323(o_PMU_OC_3[23])); + o_PMU_OC_3_23__MGIOL \o_PMU_OC_3[23]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[23] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[23] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_22_ \o_PMU_OC_3[22]_I ( .IOLDO(\o_PMU_OC_3_c[22] ), + .oPMUOC322(o_PMU_OC_3[22])); + o_PMU_OC_3_22__MGIOL \o_PMU_OC_3[22]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[22] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[22] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_21_ \o_PMU_OC_3[21]_I ( .IOLDO(\o_PMU_OC_3_c[21] ), + .oPMUOC321(o_PMU_OC_3[21])); + o_PMU_OC_3_21__MGIOL \o_PMU_OC_3[21]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[21] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[21] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_20_ \o_PMU_OC_3[20]_I ( .IOLDO(\o_PMU_OC_3_c[20] ), + .oPMUOC320(o_PMU_OC_3[20])); + o_PMU_OC_3_20__MGIOL \o_PMU_OC_3[20]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[20] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[20] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_19_ \o_PMU_OC_3[19]_I ( .IOLDO(\o_PMU_OC_3_c[19] ), + .oPMUOC319(o_PMU_OC_3[19])); + o_PMU_OC_3_19__MGIOL \o_PMU_OC_3[19]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[19] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[19] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_18_ \o_PMU_OC_3[18]_I ( .IOLDO(\o_PMU_OC_3_c[18] ), + .oPMUOC318(o_PMU_OC_3[18])); + o_PMU_OC_3_18__MGIOL \o_PMU_OC_3[18]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[18] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[18] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_17_ \o_PMU_OC_3[17]_I ( .IOLDO(\o_PMU_OC_3_c[17] ), + .oPMUOC317(o_PMU_OC_3[17])); + o_PMU_OC_3_17__MGIOL \o_PMU_OC_3[17]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[17] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[17] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_16_ \o_PMU_OC_3[16]_I ( .IOLDO(\o_PMU_OC_3_c[16] ), + .oPMUOC316(o_PMU_OC_3[16])); + o_PMU_OC_3_16__MGIOL \o_PMU_OC_3[16]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[16] ), + .OPOS(N_22), .CE(\CPLD_Con_1.OC_x17_0_sqmuxa_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_3_15_ \o_PMU_OC_3[15]_I ( .IOLDO(\o_PMU_OC_3_c[15] ), + .oPMUOC315(o_PMU_OC_3[15])); + o_PMU_OC_3_15__MGIOL \o_PMU_OC_3[15]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[15] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[15] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_14_ \o_PMU_OC_3[14]_I ( .IOLDO(\o_PMU_OC_3_c[14] ), + .oPMUOC314(o_PMU_OC_3[14])); + o_PMU_OC_3_14__MGIOL \o_PMU_OC_3[14]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[14] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[14] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_13_ \o_PMU_OC_3[13]_I ( .IOLDO(\o_PMU_OC_3_c[13] ), + .oPMUOC313(o_PMU_OC_3[13])); + o_PMU_OC_3_13__MGIOL \o_PMU_OC_3[13]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[13] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[13] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_12_ \o_PMU_OC_3[12]_I ( .IOLDO(\o_PMU_OC_3_c[12] ), + .oPMUOC312(o_PMU_OC_3[12])); + o_PMU_OC_3_12__MGIOL \o_PMU_OC_3[12]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[12] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[12] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_11_ \o_PMU_OC_3[11]_I ( .IOLDO(\o_PMU_OC_3_c[11] ), + .oPMUOC311(o_PMU_OC_3[11])); + o_PMU_OC_3_11__MGIOL \o_PMU_OC_3[11]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[11] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[11] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_10_ \o_PMU_OC_3[10]_I ( .IOLDO(\o_PMU_OC_3_c[10] ), + .oPMUOC310(o_PMU_OC_3[10])); + o_PMU_OC_3_10__MGIOL \o_PMU_OC_3[10]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[10] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[10] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_9_ \o_PMU_OC_3[9]_I ( .IOLDO(\o_PMU_OC_3_c[9] ), + .oPMUOC39(o_PMU_OC_3[9])); + o_PMU_OC_3_9__MGIOL \o_PMU_OC_3[9]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[9] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[9] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_8_ \o_PMU_OC_3[8]_I ( .IOLDO(\o_PMU_OC_3_c[8] ), + .oPMUOC38(o_PMU_OC_3[8])); + o_PMU_OC_3_8__MGIOL \o_PMU_OC_3[8]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[8] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[8] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_7_ \o_PMU_OC_3[7]_I ( .PADDO(\o_PMU_OC_3_c[7] ), + .oPMUOC37(o_PMU_OC_3[7])); + o_PMU_OC_3_6_ \o_PMU_OC_3[6]_I ( .IOLDO(\o_PMU_OC_3_c[6] ), + .oPMUOC36(o_PMU_OC_3[6])); + o_PMU_OC_3_6__MGIOL \o_PMU_OC_3[6]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[6] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[6] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_5_ \o_PMU_OC_3[5]_I ( .PADDO(\o_PMU_OC_3_c[5] ), + .oPMUOC35(o_PMU_OC_3[5])); + o_PMU_OC_3_4_ \o_PMU_OC_3[4]_I ( .IOLDO(\o_PMU_OC_3_c[4] ), + .oPMUOC34(o_PMU_OC_3[4])); + o_PMU_OC_3_4__MGIOL \o_PMU_OC_3[4]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[4] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[4] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_3_ \o_PMU_OC_3[3]_I ( .PADDO(\o_PMU_OC_3_c[3] ), + .oPMUOC33(o_PMU_OC_3[3])); + o_PMU_OC_3_2_ \o_PMU_OC_3[2]_I ( .IOLDO(\o_PMU_OC_3_c[2] ), + .oPMUOC32(o_PMU_OC_3[2])); + o_PMU_OC_3_2__MGIOL \o_PMU_OC_3[2]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[2] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_8[2] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_3_1_ \o_PMU_OC_3[1]_I ( .PADDO(\o_PMU_OC_3_c[1] ), + .oPMUOC31(o_PMU_OC_3[1])); + o_PMU_OC_3_0_ \o_PMU_OC_3[0]_I ( .IOLDO(\o_PMU_OC_3_c[0] ), + .oPMUOC30(o_PMU_OC_3[0])); + o_PMU_OC_3_0__MGIOL \o_PMU_OC_3[0]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[0] ), + .OPOS(\CPLD_Con_1.N_364 ), .CE(\CPLD_Con_1.OC_x17_0_sqmuxa_i ), + .CLK(i_sys_clk_c)); + o_PMU_OC_2_31_ \o_PMU_OC_2[31]_I ( .IOLDO(\o_PMU_OC_2_c[31] ), + .oPMUOC231(o_PMU_OC_2[31])); + o_PMU_OC_2_31__MGIOL \o_PMU_OC_2[31]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[31] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[31] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_30_ \o_PMU_OC_2[30]_I ( .IOLDO(\o_PMU_OC_2_c[30] ), + .oPMUOC230(o_PMU_OC_2[30])); + o_PMU_OC_2_30__MGIOL \o_PMU_OC_2[30]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[30] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[30] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_29_ \o_PMU_OC_2[29]_I ( .IOLDO(\o_PMU_OC_2_c[29] ), + .oPMUOC229(o_PMU_OC_2[29])); + o_PMU_OC_2_29__MGIOL \o_PMU_OC_2[29]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[29] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[29] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_28_ \o_PMU_OC_2[28]_I ( .IOLDO(\o_PMU_OC_2_c[28] ), + .oPMUOC228(o_PMU_OC_2[28])); + o_PMU_OC_2_28__MGIOL \o_PMU_OC_2[28]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[28] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[28] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_27_ \o_PMU_OC_2[27]_I ( .IOLDO(\o_PMU_OC_2_c[27] ), + .oPMUOC227(o_PMU_OC_2[27])); + o_PMU_OC_2_27__MGIOL \o_PMU_OC_2[27]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[27] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[27] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_26_ \o_PMU_OC_2[26]_I ( .IOLDO(\o_PMU_OC_2_c[26] ), + .oPMUOC226(o_PMU_OC_2[26])); + o_PMU_OC_2_26__MGIOL \o_PMU_OC_2[26]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[26] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[26] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_25_ \o_PMU_OC_2[25]_I ( .IOLDO(\o_PMU_OC_2_c[25] ), + .oPMUOC225(o_PMU_OC_2[25])); + o_PMU_OC_2_25__MGIOL \o_PMU_OC_2[25]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[25] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[25] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_24_ \o_PMU_OC_2[24]_I ( .IOLDO(\o_PMU_OC_2_c[24] ), + .oPMUOC224(o_PMU_OC_2[24])); + o_PMU_OC_2_24__MGIOL \o_PMU_OC_2[24]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[24] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[24] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_23_ \o_PMU_OC_2[23]_I ( .IOLDO(\o_PMU_OC_2_c[23] ), + .oPMUOC223(o_PMU_OC_2[23])); + o_PMU_OC_2_23__MGIOL \o_PMU_OC_2[23]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[23] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[23] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_22_ \o_PMU_OC_2[22]_I ( .IOLDO(\o_PMU_OC_2_c[22] ), + .oPMUOC222(o_PMU_OC_2[22])); + o_PMU_OC_2_22__MGIOL \o_PMU_OC_2[22]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[22] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[22] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_21_ \o_PMU_OC_2[21]_I ( .IOLDO(\o_PMU_OC_2_c[21] ), + .oPMUOC221(o_PMU_OC_2[21])); + o_PMU_OC_2_21__MGIOL \o_PMU_OC_2[21]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[21] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[21] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_20_ \o_PMU_OC_2[20]_I ( .IOLDO(\o_PMU_OC_2_c[20] ), + .oPMUOC220(o_PMU_OC_2[20])); + o_PMU_OC_2_20__MGIOL \o_PMU_OC_2[20]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[20] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[20] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_19_ \o_PMU_OC_2[19]_I ( .IOLDO(\o_PMU_OC_2_c[19] ), + .oPMUOC219(o_PMU_OC_2[19])); + o_PMU_OC_2_19__MGIOL \o_PMU_OC_2[19]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[19] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[19] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_18_ \o_PMU_OC_2[18]_I ( .IOLDO(\o_PMU_OC_2_c[18] ), + .oPMUOC218(o_PMU_OC_2[18])); + o_PMU_OC_2_18__MGIOL \o_PMU_OC_2[18]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[18] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[18] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_17_ \o_PMU_OC_2[17]_I ( .IOLDO(\o_PMU_OC_2_c[17] ), + .oPMUOC217(o_PMU_OC_2[17])); + o_PMU_OC_2_17__MGIOL \o_PMU_OC_2[17]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[17] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[17] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_16_ \o_PMU_OC_2[16]_I ( .IOLDO(\o_PMU_OC_2_c[16] ), + .oPMUOC216(o_PMU_OC_2[16])); + o_PMU_OC_2_16__MGIOL \o_PMU_OC_2[16]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[16] ), + .OPOS(\DMM_en_22_0_o2_0_RNI5A4QI[7] ), .CE(\CPLD_Con_1.OC_x17_0_sqmuxa_i ), + .CLK(i_sys_clk_c)); + o_PMU_OC_2_15_ \o_PMU_OC_2[15]_I ( .IOLDO(\o_PMU_OC_2_c[15] ), + .oPMUOC215(o_PMU_OC_2[15])); + o_PMU_OC_2_15__MGIOL \o_PMU_OC_2[15]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[15] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[15] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_14_ \o_PMU_OC_2[14]_I ( .IOLDO(\o_PMU_OC_2_c[14] ), + .oPMUOC214(o_PMU_OC_2[14])); + o_PMU_OC_2_14__MGIOL \o_PMU_OC_2[14]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[14] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[14] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_13_ \o_PMU_OC_2[13]_I ( .IOLDO(\o_PMU_OC_2_c[13] ), + .oPMUOC213(o_PMU_OC_2[13])); + o_PMU_OC_2_13__MGIOL \o_PMU_OC_2[13]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[13] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[13] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_12_ \o_PMU_OC_2[12]_I ( .IOLDO(\o_PMU_OC_2_c[12] ), + .oPMUOC212(o_PMU_OC_2[12])); + o_PMU_OC_2_12__MGIOL \o_PMU_OC_2[12]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[12] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[12] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_11_ \o_PMU_OC_2[11]_I ( .IOLDO(\o_PMU_OC_2_c[11] ), + .oPMUOC211(o_PMU_OC_2[11])); + o_PMU_OC_2_11__MGIOL \o_PMU_OC_2[11]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[11] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[11] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_10_ \o_PMU_OC_2[10]_I ( .IOLDO(\o_PMU_OC_2_c[10] ), + .oPMUOC210(o_PMU_OC_2[10])); + o_PMU_OC_2_10__MGIOL \o_PMU_OC_2[10]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[10] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[10] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_9_ \o_PMU_OC_2[9]_I ( .IOLDO(\o_PMU_OC_2_c[9] ), + .oPMUOC29(o_PMU_OC_2[9])); + o_PMU_OC_2_9__MGIOL \o_PMU_OC_2[9]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[9] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[9] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_8_ \o_PMU_OC_2[8]_I ( .IOLDO(\o_PMU_OC_2_c[8] ), + .oPMUOC28(o_PMU_OC_2[8])); + o_PMU_OC_2_8__MGIOL \o_PMU_OC_2[8]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[8] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[8] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_7_ \o_PMU_OC_2[7]_I ( .PADDO(\o_PMU_OC_2_c[7] ), + .oPMUOC27(o_PMU_OC_2[7])); + o_PMU_OC_2_6_ \o_PMU_OC_2[6]_I ( .IOLDO(\o_PMU_OC_2_c[6] ), + .oPMUOC26(o_PMU_OC_2[6])); + o_PMU_OC_2_6__MGIOL \o_PMU_OC_2[6]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[6] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[6] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_5_ \o_PMU_OC_2[5]_I ( .PADDO(\o_PMU_OC_2_c[5] ), + .oPMUOC25(o_PMU_OC_2[5])); + o_PMU_OC_2_4_ \o_PMU_OC_2[4]_I ( .IOLDO(\o_PMU_OC_2_c[4] ), + .oPMUOC24(o_PMU_OC_2[4])); + o_PMU_OC_2_4__MGIOL \o_PMU_OC_2[4]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[4] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[4] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_3_ \o_PMU_OC_2[3]_I ( .PADDO(\o_PMU_OC_2_c[3] ), + .oPMUOC23(o_PMU_OC_2[3])); + o_PMU_OC_2_2_ \o_PMU_OC_2[2]_I ( .IOLDO(\o_PMU_OC_2_c[2] ), + .oPMUOC22(o_PMU_OC_2[2])); + o_PMU_OC_2_2__MGIOL \o_PMU_OC_2[2]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[2] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_8[2] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_2_1_ \o_PMU_OC_2[1]_I ( .PADDO(\o_PMU_OC_2_c[1] ), + .oPMUOC21(o_PMU_OC_2[1])); + o_PMU_OC_2_0_ \o_PMU_OC_2[0]_I ( .IOLDO(\o_PMU_OC_2_c[0] ), + .oPMUOC20(o_PMU_OC_2[0])); + o_PMU_OC_2_0__MGIOL \o_PMU_OC_2[0]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[0] ), + .OPOS(\DMM_en_22_0_a2_3_RNIK2BQH[4] ), .CE(\CPLD_Con_1.OC_x17_0_sqmuxa_i ), + .CLK(i_sys_clk_c)); + o_PMU_OC_1_31_ \o_PMU_OC_1[31]_I ( .IOLDO(\o_PMU_OC_1_c[31] ), + .oPMUOC131(o_PMU_OC_1[31])); + o_PMU_OC_1_31__MGIOL \o_PMU_OC_1[31]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[31] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[31] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_30_ \o_PMU_OC_1[30]_I ( .IOLDO(\o_PMU_OC_1_c[30] ), + .oPMUOC130(o_PMU_OC_1[30])); + o_PMU_OC_1_30__MGIOL \o_PMU_OC_1[30]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[30] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[30] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_29_ \o_PMU_OC_1[29]_I ( .IOLDO(\o_PMU_OC_1_c[29] ), + .oPMUOC129(o_PMU_OC_1[29])); + o_PMU_OC_1_29__MGIOL \o_PMU_OC_1[29]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[29] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[29] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_28_ \o_PMU_OC_1[28]_I ( .IOLDO(\o_PMU_OC_1_c[28] ), + .oPMUOC128(o_PMU_OC_1[28])); + o_PMU_OC_1_28__MGIOL \o_PMU_OC_1[28]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[28] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[28] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_27_ \o_PMU_OC_1[27]_I ( .IOLDO(\o_PMU_OC_1_c[27] ), + .oPMUOC127(o_PMU_OC_1[27])); + o_PMU_OC_1_27__MGIOL \o_PMU_OC_1[27]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[27] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[27] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_26_ \o_PMU_OC_1[26]_I ( .IOLDO(\o_PMU_OC_1_c[26] ), + .oPMUOC126(o_PMU_OC_1[26])); + o_PMU_OC_1_26__MGIOL \o_PMU_OC_1[26]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[26] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[26] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_25_ \o_PMU_OC_1[25]_I ( .IOLDO(\o_PMU_OC_1_c[25] ), + .oPMUOC125(o_PMU_OC_1[25])); + o_PMU_OC_1_25__MGIOL \o_PMU_OC_1[25]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[25] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[25] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_24_ \o_PMU_OC_1[24]_I ( .IOLDO(\o_PMU_OC_1_c[24] ), + .oPMUOC124(o_PMU_OC_1[24])); + o_PMU_OC_1_24__MGIOL \o_PMU_OC_1[24]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[24] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[24] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_23_ \o_PMU_OC_1[23]_I ( .IOLDO(\o_PMU_OC_1_c[23] ), + .oPMUOC123(o_PMU_OC_1[23])); + o_PMU_OC_1_23__MGIOL \o_PMU_OC_1[23]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[23] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[23] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_22_ \o_PMU_OC_1[22]_I ( .IOLDO(\o_PMU_OC_1_c[22] ), + .oPMUOC122(o_PMU_OC_1[22])); + o_PMU_OC_1_22__MGIOL \o_PMU_OC_1[22]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[22] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[22] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_21_ \o_PMU_OC_1[21]_I ( .IOLDO(\o_PMU_OC_1_c[21] ), + .oPMUOC121(o_PMU_OC_1[21])); + o_PMU_OC_1_21__MGIOL \o_PMU_OC_1[21]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[21] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[21] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_20_ \o_PMU_OC_1[20]_I ( .IOLDO(\o_PMU_OC_1_c[20] ), + .oPMUOC120(o_PMU_OC_1[20])); + o_PMU_OC_1_20__MGIOL \o_PMU_OC_1[20]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[20] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[20] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_19_ \o_PMU_OC_1[19]_I ( .IOLDO(\o_PMU_OC_1_c[19] ), + .oPMUOC119(o_PMU_OC_1[19])); + o_PMU_OC_1_19__MGIOL \o_PMU_OC_1[19]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[19] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[19] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_18_ \o_PMU_OC_1[18]_I ( .IOLDO(\o_PMU_OC_1_c[18] ), + .oPMUOC118(o_PMU_OC_1[18])); + o_PMU_OC_1_18__MGIOL \o_PMU_OC_1[18]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[18] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[18] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_17_ \o_PMU_OC_1[17]_I ( .IOLDO(\o_PMU_OC_1_c[17] ), + .oPMUOC117(o_PMU_OC_1[17])); + o_PMU_OC_1_17__MGIOL \o_PMU_OC_1[17]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[17] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[17] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_16_ \o_PMU_OC_1[16]_I ( .IOLDO(\o_PMU_OC_1_c[16] ), + .oPMUOC116(o_PMU_OC_1[16])); + o_PMU_OC_1_16__MGIOL \o_PMU_OC_1[16]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[16] ), + .OPOS(\CPLD_Con_1.N_259 ), .CE(\CPLD_Con_1.OC_x17_0_sqmuxa_i ), + .CLK(i_sys_clk_c)); + o_PMU_OC_1_15_ \o_PMU_OC_1[15]_I ( .IOLDO(\o_PMU_OC_1_c[15] ), + .oPMUOC115(o_PMU_OC_1[15])); + o_PMU_OC_1_15__MGIOL \o_PMU_OC_1[15]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[15] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[15] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_14_ \o_PMU_OC_1[14]_I ( .IOLDO(\o_PMU_OC_1_c[14] ), + .oPMUOC114(o_PMU_OC_1[14])); + o_PMU_OC_1_14__MGIOL \o_PMU_OC_1[14]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[14] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[14] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_13_ \o_PMU_OC_1[13]_I ( .IOLDO(\o_PMU_OC_1_c[13] ), + .oPMUOC113(o_PMU_OC_1[13])); + o_PMU_OC_1_13__MGIOL \o_PMU_OC_1[13]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[13] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[13] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_12_ \o_PMU_OC_1[12]_I ( .IOLDO(\o_PMU_OC_1_c[12] ), + .oPMUOC112(o_PMU_OC_1[12])); + o_PMU_OC_1_12__MGIOL \o_PMU_OC_1[12]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[12] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[12] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_11_ \o_PMU_OC_1[11]_I ( .IOLDO(\o_PMU_OC_1_c[11] ), + .oPMUOC111(o_PMU_OC_1[11])); + o_PMU_OC_1_11__MGIOL \o_PMU_OC_1[11]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[11] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[11] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_10_ \o_PMU_OC_1[10]_I ( .IOLDO(\o_PMU_OC_1_c[10] ), + .oPMUOC110(o_PMU_OC_1[10])); + o_PMU_OC_1_10__MGIOL \o_PMU_OC_1[10]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[10] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[10] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_9_ \o_PMU_OC_1[9]_I ( .IOLDO(\o_PMU_OC_1_c[9] ), + .oPMUOC19(o_PMU_OC_1[9])); + o_PMU_OC_1_9__MGIOL \o_PMU_OC_1[9]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[9] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[9] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_8_ \o_PMU_OC_1[8]_I ( .IOLDO(\o_PMU_OC_1_c[8] ), + .oPMUOC18(o_PMU_OC_1[8])); + o_PMU_OC_1_8__MGIOL \o_PMU_OC_1[8]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[8] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[8] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_7_ \o_PMU_OC_1[7]_I ( .IOLDO(\o_PMU_OC_1_c[7] ), + .oPMUOC17(o_PMU_OC_1[7])); + o_PMU_OC_1_7__MGIOL \o_PMU_OC_1[7]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[7] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[7] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_6_ \o_PMU_OC_1[6]_I ( .IOLDO(\o_PMU_OC_1_c[6] ), + .oPMUOC16(o_PMU_OC_1[6])); + o_PMU_OC_1_6__MGIOL \o_PMU_OC_1[6]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[6] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[6] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_5_ \o_PMU_OC_1[5]_I ( .IOLDO(\o_PMU_OC_1_c[5] ), + .oPMUOC15(o_PMU_OC_1[5])); + o_PMU_OC_1_5__MGIOL \o_PMU_OC_1[5]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[5] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[5] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_4_ \o_PMU_OC_1[4]_I ( .IOLDO(\o_PMU_OC_1_c[4] ), + .oPMUOC14(o_PMU_OC_1[4])); + o_PMU_OC_1_4__MGIOL \o_PMU_OC_1[4]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[4] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[4] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_3_ \o_PMU_OC_1[3]_I ( .IOLDO(\o_PMU_OC_1_c[3] ), + .oPMUOC13(o_PMU_OC_1[3])); + o_PMU_OC_1_3__MGIOL \o_PMU_OC_1[3]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[3] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[3] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_2_ \o_PMU_OC_1[2]_I ( .IOLDO(\o_PMU_OC_1_c[2] ), + .oPMUOC12(o_PMU_OC_1[2])); + o_PMU_OC_1_2__MGIOL \o_PMU_OC_1[2]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[2] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[2] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_1_ \o_PMU_OC_1[1]_I ( .IOLDO(\o_PMU_OC_1_c[1] ), + .oPMUOC11(o_PMU_OC_1[1])); + o_PMU_OC_1_1__MGIOL \o_PMU_OC_1[1]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[1] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_8[1] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_PMU_OC_1_0_ \o_PMU_OC_1[0]_I ( .IOLDO(\o_PMU_OC_1_c[0] ), + .oPMUOC10(o_PMU_OC_1[0])); + o_PMU_OC_1_0__MGIOL \o_PMU_OC_1[0]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[0] ), + .OPOS(\CPLD_Con_1.N_333 ), .CE(\CPLD_Con_1.OC_x17_0_sqmuxa_i ), + .CLK(i_sys_clk_c)); + o_RC_LOS_1_ \o_RC_LOS[1]_I ( .PADDO(o_RC_ISel_c), .oRCLOS1(o_RC_LOS[1])); + o_RC_LOS_0_ \o_RC_LOS[0]_I ( .PADDO(o_RC_ISel_c_i), .oRCLOS0(o_RC_LOS[0])); + o_RC_LOF_1_ \o_RC_LOF[1]_I ( .PADDO(o_RC_ISel_c), .oRCLOF1(o_RC_LOF[1])); + o_RC_LOF_0_ \o_RC_LOF[0]_I ( .PADDO(o_RC_ISel_c_i), .oRCLOF0(o_RC_LOF[0])); + o_RC_ISel o_RC_ISel_I( .PADDO(o_RC_ISel_c), .o_RC_ISel(o_RC_ISel)); + o_RC_VSel o_RC_VSel_I( .PADDO(o_RC_ISel_c_i), .o_RC_VSel(o_RC_VSel)); + o_RC_RLSel_17_ \o_RC_RLSel[17]_I ( .IOLDO(\o_RC_RLSel_c[17] ), + .oRCRLSel17(o_RC_RLSel[17])); + o_RC_RLSel_17__MGIOL \o_RC_RLSel[17]_MGIOL ( .IOLDO(\o_RC_RLSel_c[17] ), + .OPOS(\CPLD_Con_1.RC_RLSel_13[17] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), + .LSR(err_flag13_0_0_0_RNILOU7L8), .CLK(i_sys_clk_c)); + o_RC_RLSel_16_ \o_RC_RLSel[16]_I ( .IOLDO(\o_RC_RLSel_c[16] ), + .oRCRLSel16(o_RC_RLSel[16])); + o_RC_RLSel_16__MGIOL \o_RC_RLSel[16]_MGIOL ( .IOLDO(\o_RC_RLSel_c[16] ), + .OPOS(\CPLD_Con_1.RC_RLSel_13[16] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), + .LSR(err_flag13_0_0_0_RNILOU7L8), .CLK(i_sys_clk_c)); + o_RC_RLSel_15_ \o_RC_RLSel[15]_I ( .IOLDO(\o_RC_RLSel_c[15] ), + .oRCRLSel15(o_RC_RLSel[15])); + o_RC_RLSel_15__MGIOL \o_RC_RLSel[15]_MGIOL ( .IOLDO(\o_RC_RLSel_c[15] ), + .OPOS(\CPLD_Con_1.RC_RLSel_13[15] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_RC_RLSel_14_ \o_RC_RLSel[14]_I ( .IOLDO(\o_RC_RLSel_c[14] ), + .oRCRLSel14(o_RC_RLSel[14])); + o_RC_RLSel_14__MGIOL \o_RC_RLSel[14]_MGIOL ( .IOLDO(\o_RC_RLSel_c[14] ), + .OPOS(\CPLD_Con_1.RC_RLSel_13[14] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_RC_RLSel_13_ \o_RC_RLSel[13]_I ( .IOLDO(\o_RC_RLSel_c[13] ), + .oRCRLSel13(o_RC_RLSel[13])); + o_RC_RLSel_13__MGIOL \o_RC_RLSel[13]_MGIOL ( .IOLDO(\o_RC_RLSel_c[13] ), + .OPOS(\CPLD_Con_1.RC_RLSel_13[13] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_RC_RLSel_12_ \o_RC_RLSel[12]_I ( .IOLDO(\o_RC_RLSel_c[12] ), + .oRCRLSel12(o_RC_RLSel[12])); + o_RC_RLSel_12__MGIOL \o_RC_RLSel[12]_MGIOL ( .IOLDO(\o_RC_RLSel_c[12] ), + .OPOS(\CPLD_Con_1.RC_RLSel_13[12] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_RC_RLSel_11_ \o_RC_RLSel[11]_I ( .IOLDO(\o_RC_RLSel_c[11] ), + .oRCRLSel11(o_RC_RLSel[11])); + o_RC_RLSel_11__MGIOL \o_RC_RLSel[11]_MGIOL ( .IOLDO(\o_RC_RLSel_c[11] ), + .OPOS(\CPLD_Con_1.RC_RLSel_13[11] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_RC_RLSel_10_ \o_RC_RLSel[10]_I ( .IOLDO(\o_RC_RLSel_c[10] ), + .oRCRLSel10(o_RC_RLSel[10])); + o_RC_RLSel_10__MGIOL \o_RC_RLSel[10]_MGIOL ( .IOLDO(\o_RC_RLSel_c[10] ), + .OPOS(\CPLD_Con_1.RC_RLSel_13[10] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_RC_RLSel_9_ \o_RC_RLSel[9]_I ( .IOLDO(\o_RC_RLSel_c[9] ), + .oRCRLSel9(o_RC_RLSel[9])); + o_RC_RLSel_9__MGIOL \o_RC_RLSel[9]_MGIOL ( .IOLDO(\o_RC_RLSel_c[9] ), + .OPOS(\CPLD_Con_1.RC_RLSel_13[9] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_RC_RLSel_8_ \o_RC_RLSel[8]_I ( .IOLDO(\o_RC_RLSel_c[8] ), + .oRCRLSel8(o_RC_RLSel[8])); + o_RC_RLSel_8__MGIOL \o_RC_RLSel[8]_MGIOL ( .IOLDO(\o_RC_RLSel_c[8] ), + .OPOS(\CPLD_Con_1.RC_RLSel_13[8] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_RC_RLSel_7_ \o_RC_RLSel[7]_I ( .IOLDO(\o_RC_RLSel_c[7] ), + .oRCRLSel7(o_RC_RLSel[7])); + o_RC_RLSel_7__MGIOL \o_RC_RLSel[7]_MGIOL ( .IOLDO(\o_RC_RLSel_c[7] ), + .OPOS(\CPLD_Con_1.RC_RLSel_13[7] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_RC_RLSel_6_ \o_RC_RLSel[6]_I ( .IOLDO(\o_RC_RLSel_c[6] ), + .oRCRLSel6(o_RC_RLSel[6])); + o_RC_RLSel_6__MGIOL \o_RC_RLSel[6]_MGIOL ( .IOLDO(\o_RC_RLSel_c[6] ), + .OPOS(\CPLD_Con_1.RC_RLSel_13[6] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_RC_RLSel_5_ \o_RC_RLSel[5]_I ( .IOLDO(\o_RC_RLSel_c[5] ), + .oRCRLSel5(o_RC_RLSel[5])); + o_RC_RLSel_5__MGIOL \o_RC_RLSel[5]_MGIOL ( .IOLDO(\o_RC_RLSel_c[5] ), + .OPOS(\CPLD_Con_1.RC_RLSel_13[5] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_RC_RLSel_4_ \o_RC_RLSel[4]_I ( .IOLDO(\o_RC_RLSel_c[4] ), + .oRCRLSel4(o_RC_RLSel[4])); + o_RC_RLSel_4__MGIOL \o_RC_RLSel[4]_MGIOL ( .IOLDO(\o_RC_RLSel_c[4] ), + .OPOS(\CPLD_Con_1.RC_RLSel_13[4] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + o_RC_RLSel_3_ \o_RC_RLSel[3]_I ( .IOLDO(\o_RC_RLSel_c[3] ), + .oRCRLSel3(o_RC_RLSel[3])); + o_RC_RLSel_3__MGIOL \o_RC_RLSel[3]_MGIOL ( .IOLDO(\o_RC_RLSel_c[3] ), + .OPOS(N_232), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), + .LSR(err_flag13_0_0_0_RNILOU7L8), .CLK(i_sys_clk_c)); + o_RC_RLSel_2_ \o_RC_RLSel[2]_I ( .IOLDO(\o_RC_RLSel_c[2] ), + .oRCRLSel2(o_RC_RLSel[2])); + o_RC_RLSel_2__MGIOL \o_RC_RLSel[2]_MGIOL ( .IOLDO(\o_RC_RLSel_c[2] ), + .OPOS(N_235), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), + .LSR(err_flag13_0_0_0_RNILOU7L8), .CLK(i_sys_clk_c)); + o_RC_RLSel_1_ \o_RC_RLSel[1]_I ( .IOLDO(\o_RC_RLSel_c[1] ), + .oRCRLSel1(o_RC_RLSel[1])); + o_RC_RLSel_1__MGIOL \o_RC_RLSel[1]_MGIOL ( .IOLDO(\o_RC_RLSel_c[1] ), + .OPOS(N_234), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), + .LSR(err_flag13_0_0_0_RNILOU7L8), .CLK(i_sys_clk_c)); + o_RC_RLSel_0_ \o_RC_RLSel[0]_I ( .IOLDO(\o_RC_RLSel_c[0] ), + .oRCRLSel0(o_RC_RLSel[0])); + o_RC_RLSel_0__MGIOL \o_RC_RLSel[0]_MGIOL ( .IOLDO(\o_RC_RLSel_c[0] ), + .OPOS(N_233), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), + .LSR(err_flag13_0_0_0_RNILOU7L8), .CLK(i_sys_clk_c)); + o_RC_T32 o_RC_T32_I( .IOLDO(o_RC_T32_c), .o_RC_T32(o_RC_T32)); + o_RC_T32_MGIOL o_RC_T32_MGIOL( .IOLDO(o_RC_T32_c), .OPOS(\freq4_relay[12] ), + .CE(\CPLD_Con_1.err_flag_1_sqmuxa ), .CLK(i_sys_clk_c)); + o_RC_T31 o_RC_T31_I( .IOLDO(o_RC_T31_c), .o_RC_T31(o_RC_T31)); + o_RC_T31_MGIOL o_RC_T31_MGIOL( .IOLDO(o_RC_T31_c), .OPOS(\freq4_relay[13] ), + .CE(\CPLD_Con_1.err_flag_1_sqmuxa ), .CLK(i_sys_clk_c)); + o_RC_T30 o_RC_T30_I( .IOLDO(o_RC_T30_c), .o_RC_T30(o_RC_T30)); + o_RC_T30_MGIOL o_RC_T30_MGIOL( .IOLDO(o_RC_T30_c), .OPOS(\freq4_relay[14] ), + .CE(\CPLD_Con_1.err_flag_1_sqmuxa ), .CLK(i_sys_clk_c)); + o_RC_T29 o_RC_T29_I( .IOLDO(o_RC_T29_c), .o_RC_T29(o_RC_T29)); + o_RC_T29_MGIOL o_RC_T29_MGIOL( .IOLDO(o_RC_T29_c), .OPOS(\freq4_relay[15] ), + .CE(\CPLD_Con_1.err_flag_1_sqmuxa ), .CLK(i_sys_clk_c)); + o_RC_T28 o_RC_T28_I( .IOLDO(o_RC_T28_c), .o_RC_T28(o_RC_T28)); + o_RC_T28_MGIOL o_RC_T28_MGIOL( .IOLDO(o_RC_T28_c), .OPOS(\freq4_relay[16] ), + .CE(\CPLD_Con_1.err_flag_1_sqmuxa ), .CLK(i_sys_clk_c)); + o_RC_T27 o_RC_T27_I( .IOLDO(o_RC_T27_c), .o_RC_T27(o_RC_T27)); + o_RC_T27_MGIOL o_RC_T27_MGIOL( .IOLDO(o_RC_T27_c), .OPOS(\freq4_relay[17] ), + .CE(\CPLD_Con_1.err_flag_1_sqmuxa ), .CLK(i_sys_clk_c)); + o_IO_RC1 o_IO_RC1_I( .IOLDO(o_IO_RC1_c), .o_IO_RC1(o_IO_RC1)); + o_IO_RC1_MGIOL o_IO_RC1_MGIOL( .IOLDO(o_IO_RC1_c), + .OPOS(\CPLD_Con_1.io_RC_2 ), .CE(\CPLD_Con_1.io_RC_1_sqmuxa ), + .CLK(i_sys_clk_c)); + o_DMM_EN_18_ \o_DMM_EN[18]_I ( .IOLDO(\o_DMM_EN_c[18] ), + .oDMMEN18(o_DMM_EN[18])); + o_DMM_EN_18__MGIOL \o_DMM_EN[18]_MGIOL ( .IOLDO(\o_DMM_EN_c[18] ), + .OPOS(\CPLD_Con_1.DMM_en_22[18] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), + .CLK(i_sys_clk_c)); + o_DMM_EN_17_ \o_DMM_EN[17]_I ( .IOLDO(\o_DMM_EN_c[17] ), + .oDMMEN17(o_DMM_EN[17])); + o_DMM_EN_17__MGIOL \o_DMM_EN[17]_MGIOL ( .IOLDO(\o_DMM_EN_c[17] ), + .OPOS(\CPLD_Con_1.DMM_en_22[17] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), + .CLK(i_sys_clk_c)); + o_DMM_EN_16_ \o_DMM_EN[16]_I ( .IOLDO(\o_DMM_EN_c[16] ), + .oDMMEN16(o_DMM_EN[16])); + o_DMM_EN_16__MGIOL \o_DMM_EN[16]_MGIOL ( .IOLDO(\o_DMM_EN_c[16] ), + .OPOS(\CPLD_Con_1.DMM_en_22[16] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), + .CLK(i_sys_clk_c)); + o_DMM_EN_15_ \o_DMM_EN[15]_I ( .IOLDO(\o_DMM_EN_c[15] ), + .oDMMEN15(o_DMM_EN[15])); + o_DMM_EN_15__MGIOL \o_DMM_EN[15]_MGIOL ( .IOLDO(\o_DMM_EN_c[15] ), + .OPOS(\CPLD_Con_1.DMM_en_22[15] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), + .CLK(i_sys_clk_c)); + o_DMM_EN_14_ \o_DMM_EN[14]_I ( .IOLDO(\o_DMM_EN_c[14] ), + .oDMMEN14(o_DMM_EN[14])); + o_DMM_EN_14__MGIOL \o_DMM_EN[14]_MGIOL ( .IOLDO(\o_DMM_EN_c[14] ), + .OPOS(\CPLD_Con_1.DMM_en_22[14] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), + .CLK(i_sys_clk_c)); + o_DMM_EN_13_ \o_DMM_EN[13]_I ( .IOLDO(\o_DMM_EN_c[13] ), + .oDMMEN13(o_DMM_EN[13])); + o_DMM_EN_13__MGIOL \o_DMM_EN[13]_MGIOL ( .IOLDO(\o_DMM_EN_c[13] ), + .OPOS(\CPLD_Con_1.DMM_en_22[13] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), + .CLK(i_sys_clk_c)); + o_DMM_EN_12_ \o_DMM_EN[12]_I ( .IOLDO(\o_DMM_EN_c[12] ), + .oDMMEN12(o_DMM_EN[12])); + o_DMM_EN_12__MGIOL \o_DMM_EN[12]_MGIOL ( .IOLDO(\o_DMM_EN_c[12] ), + .OPOS(\CPLD_Con_1.DMM_en_22[12] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), + .CLK(i_sys_clk_c)); + o_DMM_EN_11_ \o_DMM_EN[11]_I ( .IOLDO(\o_DMM_EN_c[11] ), + .oDMMEN11(o_DMM_EN[11])); + o_DMM_EN_11__MGIOL \o_DMM_EN[11]_MGIOL ( .IOLDO(\o_DMM_EN_c[11] ), + .OPOS(\CPLD_Con_1.DMM_en_22[11] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), + .CLK(i_sys_clk_c)); + o_DMM_EN_10_ \o_DMM_EN[10]_I ( .IOLDO(\o_DMM_EN_c[10] ), + .oDMMEN10(o_DMM_EN[10])); + o_DMM_EN_10__MGIOL \o_DMM_EN[10]_MGIOL ( .IOLDO(\o_DMM_EN_c[10] ), + .OPOS(\CPLD_Con_1.DMM_en_22[10] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), + .CLK(i_sys_clk_c)); + o_DMM_EN_9_ \o_DMM_EN[9]_I ( .IOLDO(\o_DMM_EN_c[9] ), .oDMMEN9(o_DMM_EN[9])); + o_DMM_EN_9__MGIOL \o_DMM_EN[9]_MGIOL ( .IOLDO(\o_DMM_EN_c[9] ), + .OPOS(\CPLD_Con_1.DMM_en_22[9] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), + .CLK(i_sys_clk_c)); + o_DMM_EN_8_ \o_DMM_EN[8]_I ( .IOLDO(\o_DMM_EN_c[8] ), .oDMMEN8(o_DMM_EN[8])); + o_DMM_EN_8__MGIOL \o_DMM_EN[8]_MGIOL ( .IOLDO(\o_DMM_EN_c[8] ), + .OPOS(\CPLD_Con_1.DMM_en_22[8] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), + .CLK(i_sys_clk_c)); + o_DMM_EN_7_ \o_DMM_EN[7]_I ( .IOLDO(\o_DMM_EN_c[7] ), .oDMMEN7(o_DMM_EN[7])); + o_DMM_EN_7__MGIOL \o_DMM_EN[7]_MGIOL ( .IOLDO(\o_DMM_EN_c[7] ), + .OPOS(\CPLD_Con_1.DMM_en_22[7] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), + .CLK(i_sys_clk_c)); + o_DMM_EN_6_ \o_DMM_EN[6]_I ( .IOLDO(\o_DMM_EN_c[6] ), .oDMMEN6(o_DMM_EN[6])); + o_DMM_EN_6__MGIOL \o_DMM_EN[6]_MGIOL ( .IOLDO(\o_DMM_EN_c[6] ), + .OPOS(\CPLD_Con_1.DMM_en_22[6] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), + .CLK(i_sys_clk_c)); + o_DMM_EN_5_ \o_DMM_EN[5]_I ( .IOLDO(\o_DMM_EN_c[5] ), .oDMMEN5(o_DMM_EN[5])); + o_DMM_EN_5__MGIOL \o_DMM_EN[5]_MGIOL ( .IOLDO(\o_DMM_EN_c[5] ), + .OPOS(\CPLD_Con_1.DMM_en_22[5] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), + .CLK(i_sys_clk_c)); + o_DMM_EN_4_ \o_DMM_EN[4]_I ( .IOLDO(\o_DMM_EN_c[4] ), .oDMMEN4(o_DMM_EN[4])); + o_DMM_EN_4__MGIOL \o_DMM_EN[4]_MGIOL ( .IOLDO(\o_DMM_EN_c[4] ), + .OPOS(\CPLD_Con_1.DMM_en_22[4] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), + .CLK(i_sys_clk_c)); + o_DMM_EN_3_ \o_DMM_EN[3]_I ( .IOLDO(\o_DMM_EN_c[3] ), .oDMMEN3(o_DMM_EN[3])); + o_DMM_EN_3__MGIOL \o_DMM_EN[3]_MGIOL ( .IOLDO(\o_DMM_EN_c[3] ), + .OPOS(\CPLD_Con_1.DMM_en_22[3] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), + .CLK(i_sys_clk_c)); + o_DMM_EN_2_ \o_DMM_EN[2]_I ( .IOLDO(\o_DMM_EN_c[2] ), .oDMMEN2(o_DMM_EN[2])); + o_DMM_EN_2__MGIOL \o_DMM_EN[2]_MGIOL ( .IOLDO(\o_DMM_EN_c[2] ), + .OPOS(\CPLD_Con_1.DMM_en_22[2] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), + .CLK(i_sys_clk_c)); + o_DMM_EN_1_ \o_DMM_EN[1]_I ( .IOLDO(\o_DMM_EN_c[1] ), .oDMMEN1(o_DMM_EN[1])); + o_DMM_EN_1__MGIOL \o_DMM_EN[1]_MGIOL ( .IOLDO(\o_DMM_EN_c[1] ), + .OPOS(\CPLD_Con_1.DMM_en_22[1] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), + .CLK(i_sys_clk_c)); + o_DMM_EN_0_ \o_DMM_EN[0]_I ( .IOLDO(\o_DMM_EN_c[0] ), .oDMMEN0(o_DMM_EN[0])); + o_DMM_EN_0__MGIOL \o_DMM_EN[0]_MGIOL ( .IOLDO(\o_DMM_EN_c[0] ), + .OPOS(\CPLD_Con_1.DMM_en_22[0] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), + .CLK(i_sys_clk_c)); + o_con_done o_con_done_I( .PADDO(o_con_done_c), .o_con_done(o_con_done)); + o_err o_err_I( .PADDO(o_err_c), .o_err(o_err)); + i_cs i_cs_I( .PADDI(i_cs_c), .i_cs(i_cs)); + i_cs_MGIOL i_cs_MGIOL( .DI(i_cs_c), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .IN(\BUS_Con_1.cs_sync[0] )); + i_mosi i_mosi_I( .PADDI(i_mosi_c), .i_mosi(i_mosi)); + i_mosi_MGIOL i_mosi_MGIOL( .DI(i_mosi_c), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .IN(\BUS_Con_1.mosi_sync[0] )); + i_sclk i_sclk_I( .PADDI(i_sclk_c), .i_sclk(i_sclk)); + i_sclk_MGIOL i_sclk_MGIOL( .DI(i_sclk_c), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .IN(\BUS_Con_1.sclk_sync[0] )); + i_rst_n i_rst_n_I( .PADDI(i_rst_n_c), .i_rst_n(i_rst_n)); + i_rst_n_MGIOL i_rst_n_MGIOL( .DI(i_rst_n_c), + .CE(\CPLD_Con_1.RC_Tx_0_sqmuxa_1_i ), .LSR(o_con_done_c), + .CLK(i_sys_clk_c), .IN(\CPLD_Con_1.exec_flag )); + GSR_INST GSR_INST( .GSRNET(i_rst_n_c)); + VHI VHI_INST( .Z(VCCI)); + PUR PUR_INST( .PUR(VCCI)); +endmodule + +module SLICE_0 ( input B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut4 \CPLD_Con_1/err_flag_1_sqmuxa ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40001 \BUS_Con_1/cs_sync_rep0_set[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre \BUS_Con_1_cs_sync_rep0io[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut4 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module gnd ( output PWR0 ); + + VLO INST1( .Z(PWR0)); +endmodule + +module lut40001 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module vcc ( output PWR1 ); + + VHI INST1( .Z(PWR1)); +endmodule + +module BUS_Con_1_SLICE_1 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; + + lut40002 \BUS_Con_1/un1_bit_cnt_9_axbxc1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40003 \BUS_Con_1/bit_cnt_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 \BUS_Con_1/bit_cnt[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0004 \BUS_Con_1/bit_cnt[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40002 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCCC6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40003 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC9CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0004 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module BUS_Con_1_SLICE_2 ( input C1, B1, A1, B0, A0, DI1, DI0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; + + lut40005 \BUS_Con_1/un1_bit_cnt_9_axbxc3 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40006 \BUS_Con_1/un1_bit_cnt_9_axbxc2 ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + vmuxregsre0004 \BUS_Con_1/bit_cnt[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0004 \BUS_Con_1/bit_cnt[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40005 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h6C6C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40006 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_3 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; + + lut40005 \BUS_Con_1/un1_bit_cnt_9_axbxc5 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40007 \BUS_Con_1/un1_bit_cnt_9_axbxc4 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/bit_cnt[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0004 \BUS_Con_1/bit_cnt[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40007 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h78F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_5 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; + + lut40008 \BUS_Con_1/data_readyc_2_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40009 \BUS_Con_1/data_ready_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0010 \BUS_Con_1/cs_sync[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/data_ready ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40008 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40009 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0010 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module inverter ( input I, output Z ); + + INV INST1( .A(I), .Z(Z)); +endmodule + +module BUS_Con_1_SLICE_6 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40011 \BUS_Con_1/miso_shift_6[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut4 \BUS_Con_1/miso_shift_6[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0004 \BUS_Con_1/miso_shift[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/miso_shift[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40011 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_7 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40011 \BUS_Con_1/miso_shift_6[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40011 \BUS_Con_1/miso_shift_6[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/miso_shift[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/miso_shift[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_8 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40011 \BUS_Con_1/miso_shift_6[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40011 \BUS_Con_1/miso_shift_6[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/miso_shift[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/miso_shift[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_9 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40011 \BUS_Con_1/miso_shift_6[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40011 \BUS_Con_1/miso_shift_6[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/miso_shift[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/miso_shift[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_10 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40011 \BUS_Con_1/miso_shift_6[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40011 \BUS_Con_1/miso_shift_6[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/miso_shift[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/miso_shift[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_11 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40011 \BUS_Con_1/miso_shift_6[11] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40011 \BUS_Con_1/miso_shift_6[10] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/miso_shift[11] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/miso_shift[10] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_12 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40011 \BUS_Con_1/miso_shift_6[13] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40011 \BUS_Con_1/miso_shift_6[12] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/miso_shift[13] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/miso_shift[12] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_13 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40011 \BUS_Con_1/miso_shift_6[15] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40011 \BUS_Con_1/miso_shift_6[14] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/miso_shift[15] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/miso_shift[14] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_14 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40011 \BUS_Con_1/miso_shift_6[17] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40011 \BUS_Con_1/miso_shift_6[16] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/miso_shift[17] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/miso_shift[16] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_15 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40011 \BUS_Con_1/miso_shift_6[19] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40011 \BUS_Con_1/miso_shift_6[18] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/miso_shift[19] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/miso_shift[18] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_16 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40011 \BUS_Con_1/miso_shift_6[21] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40011 \BUS_Con_1/miso_shift_6[20] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/miso_shift[21] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/miso_shift[20] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_17 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40011 \BUS_Con_1/miso_shift_6[23] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40011 \BUS_Con_1/miso_shift_6[22] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/miso_shift[23] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/miso_shift[22] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_18 ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40012 \BUS_Con_1/miso_shift_6[25] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40012 \BUS_Con_1/miso_shift_6[24] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/miso_shift[25] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/miso_shift[24] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40012 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_19 ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40012 \BUS_Con_1/miso_shift_6[27] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40012 \BUS_Con_1/miso_shift_6[26] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/miso_shift[27] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/miso_shift[26] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_20 ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40012 \BUS_Con_1/miso_shift_6[29] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40012 \BUS_Con_1/miso_shift_6[28] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/miso_shift[29] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/miso_shift[28] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_21 ( input D1, C1, B1, A1, B0, A0, DI0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40013 \BUS_Con_1/data_readyc_3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40012 \BUS_Con_1/miso_shift_6[30] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/miso_shift[30] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40013 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_40 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + lut40014 \BUS_Con_1/state_srsts[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40015 \BUS_Con_1/state_srsts[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \BUS_Con_1/state[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \BUS_Con_1/state[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40014 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40015 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_62 ( input C1, B1, A1, D0, C0, B0, A0, DI0, M1, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; + + lut40016 \CPLD_Con_1/N_11_1.CO0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40017 \CPLD_Con_1/dc_t_2_2.SUM0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 \BUS_Con_1/mosi_sync[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \CPLD_Con_1/dc_t ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40016 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE8E8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40017 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h6996) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, LSR_dly; + + lut40018 \CPLD_Con_1/en_t_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40019 \CPLD_Con_1/en_t_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 \CPLD_Con_1/en_t[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \CPLD_Con_1/en_t[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40018 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE87E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40019 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h9669) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, DI0, M1, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; + + lut40016 \CPLD_Con_1/N_18_0_c1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40020 \CPLD_Con_1/en_t_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 \BUS_Con_1/sclk_sync[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \CPLD_Con_1/en_t[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40020 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_67 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, + CLK, output F0, Q0, F1 ); + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40021 \CPLD_Con_1/io_RC_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40017 \CPLD_Con_1/freq_t_2_2.SUM0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0004 \CPLD_Con_1/freq_t ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40021 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_74 ( input M0, CE, CLK, output Q0 ); + wire VCCI, GNDI, M0_dly, CLK_dly, CE_dly; + + vmuxregsre0022 \CPLD_Reg_1/regtable[9]_fast[8] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module vmuxregsre0022 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "ENABLED"; +endmodule + +module CPLD_Reg_1_SLICE_75 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, + CLK, output F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40021 \CPLD_Reg_1/err_flag8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40023 \CPLD_Reg_1/err_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/err_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40023 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_171 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40024 \CPLD_Reg_1/state_RNI7UVD8[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40025 \CPLD_Reg_1/regtable[1]_RNO[23] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0026 \CPLD_Reg_1/regtable[1][23] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40024 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40025 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFBC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0026 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "ENABLED"; +endmodule + +module CPLD_Reg_1_SLICE_212 ( input M1, M0, CE, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre0022 \CPLD_Reg_1/regtable[9][15] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[9][16] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_213 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + lut40027 \CPLD_Reg_1/state_ns_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40028 \CPLD_Reg_1/state_ns_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/state[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/state[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40027 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFCFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40028 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCDCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_248 ( input M1, M0, CE, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre0022 \CPLD_Reg_1/regtable[9][20] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[9][21] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_249 ( input M1, M0, CE, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre0022 \CPLD_Reg_1/regtable[9][22] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[9][23] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_250 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, + LSR, CLK, output F0, Q0, F1 ); + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40029 \BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_0 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40030 \BUS_Con_1/err_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 \BUS_Con_1/err_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40029 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40030 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0045) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_251 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, + LSR, CLK, output F0, Q0, F1 ); + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40031 \BUS_Con_1/state_ns_1_0_.m3_i_o2 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40032 \BUS_Con_1/cmd_valid_out_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/cmd_valid_out ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40031 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4746) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40032 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_252 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40033 \CPLD_Reg_1/state_ns_0_o4[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40034 \CPLD_Reg_1/regtable[1]_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][0] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40033 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40034 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0ACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_253 ( input M0, CE, CLK, output Q0 ); + wire VCCI, GNDI, M0_dly, CLK_dly, CE_dly; + + vmuxregsre0022 \CPLD_Reg_1/rvalid_flag ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_254 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, + CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40035 \CPLD_Con_1/err_flag13_0_0_0_RNI0U1AS7 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40036 \CPLD_Con_1/un1_RC_Tx_0_sqmuxa_1 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \CPLD_Con_1/err_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40035 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hECFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40036 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_278 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + lut40037 \CPLD_Con_1/PMU_OC_2d[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40038 \CPLD_Con_1/PMU_OC_2d[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Con_1/PMU_OC_2[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Con_1/PMU_OC_2[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40037 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0D08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40038 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0B08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_279 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + lut40037 \CPLD_Con_1/PMU_OC_2d[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40037 \CPLD_Con_1/PMU_OC_2d[5] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Con_1/PMU_OC_2[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Con_1/PMU_OC_2[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_280 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + lut40037 \CPLD_Con_1/PMU_OC_3d[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40038 \CPLD_Con_1/PMU_OC_3d[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Con_1/PMU_OC_3[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Con_1/PMU_OC_3[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_281 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + lut40037 \CPLD_Con_1/PMU_OC_3d[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40037 \CPLD_Con_1/PMU_OC_3d[5] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Con_1/PMU_OC_3[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Con_1/PMU_OC_3[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_282 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + lut40037 \CPLD_Con_1/PMU_OC_4d[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40037 \CPLD_Con_1/PMU_OC_4d[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Con_1/PMU_OC_4[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Con_1/PMU_OC_4[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_283 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + lut40037 \CPLD_Con_1/PMU_OC_4d[20] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40037 \CPLD_Con_1/PMU_OC_4d[5] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Con_1/PMU_OC_4[20] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Con_1/PMU_OC_4[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_284 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, + LSR, CLK, output F0, Q0, F1 ); + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40039 \CPLD_Con_1/RC_VISel_6.m9_0_1_tz ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40040 \CPLD_Con_1/RC_VISel_6.m9_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0004 \CPLD_Con_1/RC_VISel ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40039 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h6420) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40040 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_286 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_286/CPLD_Reg_1/rdata_reg_2_8[0]/GATE_H1 , + \CPLD_Reg_1/SLICE_286/CPLD_Reg_1/SLICE_286_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40041 \CPLD_Reg_1/rdata_reg_2_8[0]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_286/CPLD_Reg_1/rdata_reg_2_8[0]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/SLICE_286_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_286/CPLD_Reg_1/SLICE_286_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_286_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_286/CPLD_Reg_1/SLICE_286_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_286/CPLD_Reg_1/rdata_reg_2_8[0]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_286_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40041 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module selmux2 ( input D0, D1, SD, output Z ); + + MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); +endmodule + +module CPLD_Reg_1_SLICE_287 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_287/CPLD_Reg_1/rdata_reg_2_8[1]/GATE_H1 , + \CPLD_Reg_1/SLICE_287/CPLD_Reg_1/SLICE_287_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40041 \CPLD_Reg_1/rdata_reg_2_8[1]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_287/CPLD_Reg_1/rdata_reg_2_8[1]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/SLICE_287_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_287/CPLD_Reg_1/SLICE_287_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_287_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_287/CPLD_Reg_1/SLICE_287_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_287/CPLD_Reg_1/rdata_reg_2_8[1]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_287_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_288 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_288/CPLD_Reg_1/rdata_reg_2_8[2]/GATE_H1 , + \CPLD_Reg_1/SLICE_288/CPLD_Reg_1/SLICE_288_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40041 \CPLD_Reg_1/rdata_reg_2_8[2]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_288/CPLD_Reg_1/rdata_reg_2_8[2]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/SLICE_288_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_288/CPLD_Reg_1/SLICE_288_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_288_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_288/CPLD_Reg_1/SLICE_288_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_288/CPLD_Reg_1/rdata_reg_2_8[2]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_288_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_289 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_289/CPLD_Reg_1/rdata_reg_2_8[3]/GATE_H1 , + \CPLD_Reg_1/SLICE_289/CPLD_Reg_1/SLICE_289_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40041 \CPLD_Reg_1/rdata_reg_2_8[3]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_289/CPLD_Reg_1/rdata_reg_2_8[3]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/SLICE_289_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_289/CPLD_Reg_1/SLICE_289_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_289_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_289/CPLD_Reg_1/SLICE_289_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_289/CPLD_Reg_1/rdata_reg_2_8[3]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_289_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_290 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_290/CPLD_Reg_1/rdata_reg_2_8[4]/GATE_H1 , + \CPLD_Reg_1/SLICE_290/CPLD_Reg_1/SLICE_290_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40041 \CPLD_Reg_1/rdata_reg_2_8[4]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_290/CPLD_Reg_1/rdata_reg_2_8[4]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/SLICE_290_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_290/CPLD_Reg_1/SLICE_290_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_290_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_290/CPLD_Reg_1/SLICE_290_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_290/CPLD_Reg_1/rdata_reg_2_8[4]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_290_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_291 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_291/CPLD_Reg_1/rdata_reg_2_8[5]/GATE_H1 , + \CPLD_Reg_1/SLICE_291/CPLD_Reg_1/SLICE_291_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40041 \CPLD_Reg_1/rdata_reg_2_8[5]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_291/CPLD_Reg_1/rdata_reg_2_8[5]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/SLICE_291_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_291/CPLD_Reg_1/SLICE_291_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_291_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_291/CPLD_Reg_1/SLICE_291_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_291/CPLD_Reg_1/rdata_reg_2_8[5]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_291_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_292 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_292/CPLD_Reg_1/rdata_reg_2_8[6]/GATE_H1 , + \CPLD_Reg_1/SLICE_292/CPLD_Reg_1/SLICE_292_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40041 \CPLD_Reg_1/rdata_reg_2_8[6]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_292/CPLD_Reg_1/rdata_reg_2_8[6]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/SLICE_292_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_292/CPLD_Reg_1/SLICE_292_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_292_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_292/CPLD_Reg_1/SLICE_292_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_292/CPLD_Reg_1/rdata_reg_2_8[6]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_292_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_293 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_293/CPLD_Reg_1/rdata_reg_2_8[7]/GATE_H1 , + \CPLD_Reg_1/SLICE_293/CPLD_Reg_1/SLICE_293_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40041 \CPLD_Reg_1/rdata_reg_2_8[7]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_293/CPLD_Reg_1/rdata_reg_2_8[7]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/SLICE_293_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_293/CPLD_Reg_1/SLICE_293_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_293_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_293/CPLD_Reg_1/SLICE_293_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_293/CPLD_Reg_1/rdata_reg_2_8[7]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_293_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_294 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_294/CPLD_Reg_1/rdata_reg_2_8[8]/GATE_H1 , + \CPLD_Reg_1/SLICE_294/CPLD_Reg_1/SLICE_294_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40041 \CPLD_Reg_1/rdata_reg_2_8[8]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_294/CPLD_Reg_1/rdata_reg_2_8[8]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/SLICE_294_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_294/CPLD_Reg_1/SLICE_294_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_294_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_294/CPLD_Reg_1/SLICE_294_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_294/CPLD_Reg_1/rdata_reg_2_8[8]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_294_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_295 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_295/CPLD_Reg_1/rdata_reg_2_8[9]/GATE_H1 , + \CPLD_Reg_1/SLICE_295/CPLD_Reg_1/SLICE_295_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40041 \CPLD_Reg_1/rdata_reg_2_8[9]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_295/CPLD_Reg_1/rdata_reg_2_8[9]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/SLICE_295_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_295/CPLD_Reg_1/SLICE_295_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_295_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_295/CPLD_Reg_1/SLICE_295_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_295/CPLD_Reg_1/rdata_reg_2_8[9]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_295_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_296 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, + \CPLD_Reg_1/SLICE_296/CPLD_Reg_1/rdata_reg_2_8_i_m2[10]/GATE_H1 , + \CPLD_Reg_1/SLICE_296/CPLD_Reg_1/SLICE_296_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40042 \CPLD_Reg_1/rdata_reg_2_8_i_m2[10]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_296/CPLD_Reg_1/rdata_reg_2_8_i_m2[10]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/SLICE_296_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_296/CPLD_Reg_1/SLICE_296_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_296_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_296/CPLD_Reg_1/SLICE_296_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_296/CPLD_Reg_1/rdata_reg_2_8_i_m2[10]/GATE_H1 ), + .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_296_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40042 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_297 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, + \CPLD_Reg_1/SLICE_297/CPLD_Reg_1/rdata_reg_2_8_i_m2[11]/GATE_H1 , + \CPLD_Reg_1/SLICE_297/CPLD_Reg_1/SLICE_297_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40042 \CPLD_Reg_1/rdata_reg_2_8_i_m2[11]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_297/CPLD_Reg_1/rdata_reg_2_8_i_m2[11]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/SLICE_297_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_297/CPLD_Reg_1/SLICE_297_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_297_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_297/CPLD_Reg_1/SLICE_297_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_297/CPLD_Reg_1/rdata_reg_2_8_i_m2[11]/GATE_H1 ), + .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_297_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_298 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, + \CPLD_Reg_1/SLICE_298/CPLD_Reg_1/rdata_reg_2_8_i_m2[12]/GATE_H1 , + \CPLD_Reg_1/SLICE_298/CPLD_Reg_1/SLICE_298_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40042 \CPLD_Reg_1/rdata_reg_2_8_i_m2[12]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_298/CPLD_Reg_1/rdata_reg_2_8_i_m2[12]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/SLICE_298_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_298/CPLD_Reg_1/SLICE_298_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_298_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_298/CPLD_Reg_1/SLICE_298_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_298/CPLD_Reg_1/rdata_reg_2_8_i_m2[12]/GATE_H1 ), + .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_298_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_299 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, + \CPLD_Reg_1/SLICE_299/CPLD_Reg_1/rdata_reg_2_8_i_m2[13]/GATE_H1 , + \CPLD_Reg_1/SLICE_299/CPLD_Reg_1/SLICE_299_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40042 \CPLD_Reg_1/rdata_reg_2_8_i_m2[13]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_299/CPLD_Reg_1/rdata_reg_2_8_i_m2[13]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/SLICE_299_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_299/CPLD_Reg_1/SLICE_299_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_299_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_299/CPLD_Reg_1/SLICE_299_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_299/CPLD_Reg_1/rdata_reg_2_8_i_m2[13]/GATE_H1 ), + .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_299_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_300 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, + \CPLD_Reg_1/SLICE_300/CPLD_Reg_1/rdata_reg_2_8_i_m2[14]/GATE_H1 , + \CPLD_Reg_1/SLICE_300/CPLD_Reg_1/SLICE_300_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40042 \CPLD_Reg_1/rdata_reg_2_8_i_m2[14]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_300/CPLD_Reg_1/rdata_reg_2_8_i_m2[14]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/SLICE_300_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_300/CPLD_Reg_1/SLICE_300_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_300_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_300/CPLD_Reg_1/SLICE_300_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_300/CPLD_Reg_1/rdata_reg_2_8_i_m2[14]/GATE_H1 ), + .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_300_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_301 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, + \CPLD_Reg_1/SLICE_301/CPLD_Reg_1/rdata_reg_2_8_i_m2[15]/GATE_H1 , + \CPLD_Reg_1/SLICE_301/CPLD_Reg_1/SLICE_301_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40042 \CPLD_Reg_1/rdata_reg_2_8_i_m2[15]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_301/CPLD_Reg_1/rdata_reg_2_8_i_m2[15]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/SLICE_301_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_301/CPLD_Reg_1/SLICE_301_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_301_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_301/CPLD_Reg_1/SLICE_301_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_301/CPLD_Reg_1/rdata_reg_2_8_i_m2[15]/GATE_H1 ), + .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_301_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_302 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, + \CPLD_Reg_1/SLICE_302/CPLD_Reg_1/rdata_reg_2_8_i_m2[16]/GATE_H1 , + \CPLD_Reg_1/SLICE_302/CPLD_Reg_1/SLICE_302_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40042 \CPLD_Reg_1/rdata_reg_2_8_i_m2[16]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_302/CPLD_Reg_1/rdata_reg_2_8_i_m2[16]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/SLICE_302_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_302/CPLD_Reg_1/SLICE_302_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[16] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_302_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_302/CPLD_Reg_1/SLICE_302_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_302/CPLD_Reg_1/rdata_reg_2_8_i_m2[16]/GATE_H1 ), + .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_302_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_303 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_303/CPLD_Reg_1/rdata_reg_2_8[17]/GATE_H1 , + \CPLD_Reg_1/SLICE_303/CPLD_Reg_1/SLICE_303_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40041 \CPLD_Reg_1/rdata_reg_2_8[17]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_303/CPLD_Reg_1/rdata_reg_2_8[17]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/SLICE_303_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_303/CPLD_Reg_1/SLICE_303_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[17] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_303_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_303/CPLD_Reg_1/SLICE_303_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_303/CPLD_Reg_1/rdata_reg_2_8[17]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_303_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_304 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_304/CPLD_Reg_1/rdata_reg_2_8[18]/GATE_H1 , + \CPLD_Reg_1/SLICE_304/CPLD_Reg_1/SLICE_304_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40041 \CPLD_Reg_1/rdata_reg_2_8[18]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_304/CPLD_Reg_1/rdata_reg_2_8[18]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/SLICE_304_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_304/CPLD_Reg_1/SLICE_304_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[18] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_304_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_304/CPLD_Reg_1/SLICE_304_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_304/CPLD_Reg_1/rdata_reg_2_8[18]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_304_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_305 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_305/CPLD_Reg_1/rdata_reg_2_8[19]/GATE_H1 , + \CPLD_Reg_1/SLICE_305/CPLD_Reg_1/SLICE_305_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40041 \CPLD_Reg_1/rdata_reg_2_8[19]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_305/CPLD_Reg_1/rdata_reg_2_8[19]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/SLICE_305_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_305/CPLD_Reg_1/SLICE_305_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[19] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_305_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_305/CPLD_Reg_1/SLICE_305_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_305/CPLD_Reg_1/rdata_reg_2_8[19]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_305_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_306 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_306/CPLD_Reg_1/rdata_reg_2_8[20]/GATE_H1 , + \CPLD_Reg_1/SLICE_306/CPLD_Reg_1/SLICE_306_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40041 \CPLD_Reg_1/rdata_reg_2_8[20]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_306/CPLD_Reg_1/rdata_reg_2_8[20]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/SLICE_306_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_306/CPLD_Reg_1/SLICE_306_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[20] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_306_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_306/CPLD_Reg_1/SLICE_306_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_306/CPLD_Reg_1/rdata_reg_2_8[20]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_306_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_307 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_307/CPLD_Reg_1/rdata_reg_2_8[21]/GATE_H1 , + \CPLD_Reg_1/SLICE_307/CPLD_Reg_1/SLICE_307_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40041 \CPLD_Reg_1/rdata_reg_2_8[21]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_307/CPLD_Reg_1/rdata_reg_2_8[21]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/SLICE_307_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_307/CPLD_Reg_1/SLICE_307_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[21] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_307_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_307/CPLD_Reg_1/SLICE_307_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_307/CPLD_Reg_1/rdata_reg_2_8[21]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_307_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_308 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_308/CPLD_Reg_1/rdata_reg_2_8[22]/GATE_H1 , + \CPLD_Reg_1/SLICE_308/CPLD_Reg_1/SLICE_308_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40041 \CPLD_Reg_1/rdata_reg_2_8[22]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_308/CPLD_Reg_1/rdata_reg_2_8[22]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/SLICE_308_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_308/CPLD_Reg_1/SLICE_308_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[22] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_308_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_308/CPLD_Reg_1/SLICE_308_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_308/CPLD_Reg_1/rdata_reg_2_8[22]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_308_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_309 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_309/CPLD_Reg_1/rdata_reg_2_8[23]/GATE_H1 , + \CPLD_Reg_1/SLICE_309/CPLD_Reg_1/SLICE_309_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40041 \CPLD_Reg_1/rdata_reg_2_8[23]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_309/CPLD_Reg_1/rdata_reg_2_8[23]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/SLICE_309_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_309/CPLD_Reg_1/SLICE_309_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[23] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_309_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_309/CPLD_Reg_1/SLICE_309_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_309/CPLD_Reg_1/rdata_reg_2_8[23]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_309_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_311 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + vmuxregsre0004 \BUS_Con_1/addr_out[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/addr_out[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_312 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + vmuxregsre0004 \BUS_Con_1/addr_out[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/addr_out[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_313 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + vmuxregsre0004 \BUS_Con_1/addr_out[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/addr_out[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_319 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40043 \CPLD_Reg_1/busy_flag_1_i_a3_0_0_0 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40044 \CPLD_Reg_1/busy_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/busy_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40043 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40044 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3DFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_320 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + vmuxregsre0004 \BUS_Con_1/addr_out_fast[3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/data_out[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_321 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + vmuxregsre0004 \BUS_Con_1/data_out[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/data_out[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_322 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + vmuxregsre0004 \BUS_Con_1/data_out[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/data_out[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_323 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + vmuxregsre0004 \BUS_Con_1/data_out[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/data_out[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_324 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + vmuxregsre0004 \BUS_Con_1/data_out[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/data_out[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_326 ( input B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40043 \BUS_Con_1/state_s0_0_a2_0_a4 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/data_out[13] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0004 \BUS_Con_1/data_out[12] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_327 ( input C1, B1, A1, A0, M1, M0, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40045 \CPLD_Reg_1/regtable[0]_1_sqmuxa_8_0_a2 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40046 \CPLD_Con_1/RC_VISel_RNIN1MR2 ( .A(A0), .B(GNDI), .C(GNDI), + .D(GNDI), .Z(F0)); + vmuxregsre0004 \BUS_Con_1/data_out[15] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0004 \BUS_Con_1/data_out[14] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40045 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40046 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_328 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40043 \CPLD_Con_1/g0_21_N_3L3 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40045 \CPLD_Con_1/g0_19_1 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0004 \BUS_Con_1/data_out[17] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0004 \BUS_Con_1/data_out[16] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_329 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40043 \CPLD_Con_1/g0_3_1_N_2L1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40043 \CPLD_Con_1/OC_x0112lto2_0 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/data_out[19] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0004 \BUS_Con_1/data_out[18] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_330 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40043 \CPLD_Con_1/OC_x0112lto8_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40033 \CPLD_Con_1/err_flag19_0_0_0_RNO ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + vmuxregsre0004 \BUS_Con_1/data_out[21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0004 \BUS_Con_1/data_out[20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_331 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut4 \CPLD_Con_1/un1_i_DC_Con1_iv_0_a5_2[2] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40012 \CPLD_Con_1/err_flag39 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0004 \BUS_Con_1/data_out[23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0004 \BUS_Con_1/data_out[22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_332 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40045 \CPLD_Con_1/OC_x0126lto2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40047 \CPLD_Con_1/PMU_OC_2_8_0_a4[21] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/addr_out[0] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0004 \BUS_Con_1/wr_out ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40047 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_RC_VISel_6_m9_0_0_SLICE_333 ( input C1, B1, A1, D0, C0, B0, + A0, M0, output OFX0 ); + wire GNDI, + \CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333/CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333_K1_H1 + , + \CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333/CPLD_Con_1/RC_VISel_6.m9_0_0/GATE_H0 + ; + + lut40048 \CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333/CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40049 \CPLD_Con_1/RC_VISel_6.m9_0_0/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333/CPLD_Con_1/RC_VISel_6.m9_0_0/GATE_H0 ) + ); + selmux2 \CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333_K0K1MUX ( + .D0(\CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333/CPLD_Con_1/RC_VISel_6.m9_0_0/GATE_H0 ) + , + .D1(\CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333/CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40048 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_DMM_en_22_2__SLICE_334 ( input D1, C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire + \CPLD_Con_1/DMM_en_22[2]/SLICE_334/CPLD_Con_1/DMM_en_22[2]/SLICE_334_K1_H1 + , GNDI, + \CPLD_Con_1/DMM_en_22[2]/SLICE_334/CPLD_Con_1/DMM_en_22[2]/GATE_H0 ; + + lut40050 \CPLD_Con_1/DMM_en_22[2]/SLICE_334_K1 ( .A(A1), .B(B1), .C(C1), + .D(D1), + .Z(\CPLD_Con_1/DMM_en_22[2]/SLICE_334/CPLD_Con_1/DMM_en_22[2]/SLICE_334_K1_H1 ) + ); + lut40051 \CPLD_Con_1/DMM_en_22[2]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Con_1/DMM_en_22[2]/SLICE_334/CPLD_Con_1/DMM_en_22[2]/GATE_H0 )); + gnd DRIVEGND( .PWR0(GNDI)); + selmux2 \CPLD_Con_1/DMM_en_22[2]/SLICE_334_K0K1MUX ( + .D0(\CPLD_Con_1/DMM_en_22[2]/SLICE_334/CPLD_Con_1/DMM_en_22[2]/GATE_H0 ), + .D1(\CPLD_Con_1/DMM_en_22[2]/SLICE_334/CPLD_Con_1/DMM_en_22[2]/SLICE_334_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40050 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h20A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40051 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_DMM_en_22_11__SLICE_335 ( input D1, C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire + \CPLD_Con_1/DMM_en_22[11]/SLICE_335/CPLD_Con_1/DMM_en_22[11]/SLICE_335_K1_H1 + , GNDI, + \CPLD_Con_1/DMM_en_22[11]/SLICE_335/CPLD_Con_1/DMM_en_22[11]/GATE_H0 ; + + lut40052 \CPLD_Con_1/DMM_en_22[11]/SLICE_335_K1 ( .A(A1), .B(B1), .C(C1), + .D(D1), + .Z(\CPLD_Con_1/DMM_en_22[11]/SLICE_335/CPLD_Con_1/DMM_en_22[11]/SLICE_335_K1_H1 ) + ); + lut40053 \CPLD_Con_1/DMM_en_22[11]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Con_1/DMM_en_22[11]/SLICE_335/CPLD_Con_1/DMM_en_22[11]/GATE_H0 )); + gnd DRIVEGND( .PWR0(GNDI)); + selmux2 \CPLD_Con_1/DMM_en_22[11]/SLICE_335_K0K1MUX ( + .D0(\CPLD_Con_1/DMM_en_22[11]/SLICE_335/CPLD_Con_1/DMM_en_22[11]/GATE_H0 ), + .D1(\CPLD_Con_1/DMM_en_22[11]/SLICE_335/CPLD_Con_1/DMM_en_22[11]/SLICE_335_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAA80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40053 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_DMM_en_22_1__SLICE_336 ( input D1, C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire + \CPLD_Con_1/DMM_en_22[1]/SLICE_336/CPLD_Con_1/DMM_en_22[1]/SLICE_336_K1_H1 + , GNDI, + \CPLD_Con_1/DMM_en_22[1]/SLICE_336/CPLD_Con_1/DMM_en_22[1]/GATE_H0 ; + + lut40054 \CPLD_Con_1/DMM_en_22[1]/SLICE_336_K1 ( .A(A1), .B(B1), .C(C1), + .D(D1), + .Z(\CPLD_Con_1/DMM_en_22[1]/SLICE_336/CPLD_Con_1/DMM_en_22[1]/SLICE_336_K1_H1 ) + ); + lut40051 \CPLD_Con_1/DMM_en_22[1]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Con_1/DMM_en_22[1]/SLICE_336/CPLD_Con_1/DMM_en_22[1]/GATE_H0 )); + gnd DRIVEGND( .PWR0(GNDI)); + selmux2 \CPLD_Con_1/DMM_en_22[1]/SLICE_336_K0K1MUX ( + .D0(\CPLD_Con_1/DMM_en_22[1]/SLICE_336/CPLD_Con_1/DMM_en_22[1]/GATE_H0 ), + .D1(\CPLD_Con_1/DMM_en_22[1]/SLICE_336/CPLD_Con_1/DMM_en_22[1]/SLICE_336_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40054 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_DMM_en_22_9__SLICE_337 ( input D1, C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire + \CPLD_Con_1/DMM_en_22[9]/SLICE_337/CPLD_Con_1/DMM_en_22[9]/SLICE_337_K1_H1 + , GNDI, + \CPLD_Con_1/DMM_en_22[9]/SLICE_337/CPLD_Con_1/DMM_en_22[9]/GATE_H0 ; + + lut40055 \CPLD_Con_1/DMM_en_22[9]/SLICE_337_K1 ( .A(A1), .B(B1), .C(C1), + .D(D1), + .Z(\CPLD_Con_1/DMM_en_22[9]/SLICE_337/CPLD_Con_1/DMM_en_22[9]/SLICE_337_K1_H1 ) + ); + lut40053 \CPLD_Con_1/DMM_en_22[9]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Con_1/DMM_en_22[9]/SLICE_337/CPLD_Con_1/DMM_en_22[9]/GATE_H0 )); + gnd DRIVEGND( .PWR0(GNDI)); + selmux2 \CPLD_Con_1/DMM_en_22[9]/SLICE_337_K0K1MUX ( + .D0(\CPLD_Con_1/DMM_en_22[9]/SLICE_337/CPLD_Con_1/DMM_en_22[9]/GATE_H0 ), + .D1(\CPLD_Con_1/DMM_en_22[9]/SLICE_337/CPLD_Con_1/DMM_en_22[9]/SLICE_337_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40055 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_DMM_en_22_0__SLICE_338 ( input B1, A1, C0, B0, A0, M0, + output OFX0 ); + wire GNDI, + \CPLD_Con_1/DMM_en_22[0]/SLICE_338/CPLD_Con_1/DMM_en_22[0]/SLICE_338_K1_H1 + , \CPLD_Con_1/DMM_en_22[0]/SLICE_338/CPLD_Con_1/DMM_en_22[0]/GATE_H0 ; + + lut40056 \CPLD_Con_1/DMM_en_22[0]/SLICE_338_K1 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), + .Z(\CPLD_Con_1/DMM_en_22[0]/SLICE_338/CPLD_Con_1/DMM_en_22[0]/SLICE_338_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40051 \CPLD_Con_1/DMM_en_22[0]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Con_1/DMM_en_22[0]/SLICE_338/CPLD_Con_1/DMM_en_22[0]/GATE_H0 )); + selmux2 \CPLD_Con_1/DMM_en_22[0]/SLICE_338_K0K1MUX ( + .D0(\CPLD_Con_1/DMM_en_22[0]/SLICE_338/CPLD_Con_1/DMM_en_22[0]/GATE_H0 ), + .D1(\CPLD_Con_1/DMM_en_22[0]/SLICE_338/CPLD_Con_1/DMM_en_22[0]/SLICE_338_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40056 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_DMM_en_22_8__SLICE_339 ( input D1, C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire + \CPLD_Con_1/DMM_en_22[8]/SLICE_339/CPLD_Con_1/DMM_en_22[8]/SLICE_339_K1_H1 + , GNDI, + \CPLD_Con_1/DMM_en_22[8]/SLICE_339/CPLD_Con_1/DMM_en_22[8]/GATE_H0 ; + + lut40057 \CPLD_Con_1/DMM_en_22[8]/SLICE_339_K1 ( .A(A1), .B(B1), .C(C1), + .D(D1), + .Z(\CPLD_Con_1/DMM_en_22[8]/SLICE_339/CPLD_Con_1/DMM_en_22[8]/SLICE_339_K1_H1 ) + ); + lut40053 \CPLD_Con_1/DMM_en_22[8]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Con_1/DMM_en_22[8]/SLICE_339/CPLD_Con_1/DMM_en_22[8]/GATE_H0 )); + gnd DRIVEGND( .PWR0(GNDI)); + selmux2 \CPLD_Con_1/DMM_en_22[8]/SLICE_339_K0K1MUX ( + .D0(\CPLD_Con_1/DMM_en_22[8]/SLICE_339/CPLD_Con_1/DMM_en_22[8]/GATE_H0 ), + .D1(\CPLD_Con_1/DMM_en_22[8]/SLICE_339/CPLD_Con_1/DMM_en_22[8]/SLICE_339_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40057 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_0__SLICE_340 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340/CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340/CPLD_Reg_1/rdata_reg_2_10[0]/GATE_H0 + ; + + lut40041 \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340/CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_10[0]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340/CPLD_Reg_1/rdata_reg_2_10[0]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340/CPLD_Reg_1/rdata_reg_2_10[0]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340/CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_23__SLICE_341 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341/CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341/CPLD_Reg_1/rdata_reg_2_11[23]/GATE_H0 + ; + + lut40058 \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341/CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_11[23]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341/CPLD_Reg_1/rdata_reg_2_11[23]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341/CPLD_Reg_1/rdata_reg_2_11[23]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341/CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40058 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD8D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_0__SLICE_342 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342/CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342/CPLD_Reg_1/rdata_reg_2_11[0]/GATE_H0 + ; + + lut40041 \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342/CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_11[0]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342/CPLD_Reg_1/rdata_reg_2_11[0]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342/CPLD_Reg_1/rdata_reg_2_11[0]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342/CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_9__SLICE_343 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343/CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343/CPLD_Reg_1/rdata_reg_2_11[9]/GATE_H0 + ; + + lut40058 \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343/CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_11[9]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343/CPLD_Reg_1/rdata_reg_2_11[9]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343/CPLD_Reg_1/rdata_reg_2_11[9]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343/CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_16__SLICE_344 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344/CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344/CPLD_Reg_1/rdata_reg_2_11[16]/GATE_H0 + ; + + lut40059 \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344/CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_11[16]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344/CPLD_Reg_1/rdata_reg_2_11[16]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344/CPLD_Reg_1/rdata_reg_2_11[16]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344/CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40059 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_15__SLICE_345 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345/CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345/CPLD_Reg_1/rdata_reg_2_11[15]/GATE_H0 + ; + + lut40059 \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345/CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_11[15]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345/CPLD_Reg_1/rdata_reg_2_11[15]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345/CPLD_Reg_1/rdata_reg_2_11[15]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345/CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_14__SLICE_346 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346/CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346/CPLD_Reg_1/rdata_reg_2_11[14]/GATE_H0 + ; + + lut40059 \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346/CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_11[14]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346/CPLD_Reg_1/rdata_reg_2_11[14]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346/CPLD_Reg_1/rdata_reg_2_11[14]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346/CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_13__SLICE_347 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347/CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347/CPLD_Reg_1/rdata_reg_2_11[13]/GATE_H0 + ; + + lut40059 \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347/CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_11[13]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347/CPLD_Reg_1/rdata_reg_2_11[13]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347/CPLD_Reg_1/rdata_reg_2_11[13]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347/CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_12__SLICE_348 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348/CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348/CPLD_Reg_1/rdata_reg_2_11[12]/GATE_H0 + ; + + lut40059 \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348/CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_11[12]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348/CPLD_Reg_1/rdata_reg_2_11[12]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348/CPLD_Reg_1/rdata_reg_2_11[12]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348/CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_11__SLICE_349 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349/CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349/CPLD_Reg_1/rdata_reg_2_11[11]/GATE_H0 + ; + + lut40059 \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349/CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_11[11]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349/CPLD_Reg_1/rdata_reg_2_11[11]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349/CPLD_Reg_1/rdata_reg_2_11[11]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349/CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_10__SLICE_350 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350/CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350/CPLD_Reg_1/rdata_reg_2_11[10]/GATE_H0 + ; + + lut40059 \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350/CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_11[10]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350/CPLD_Reg_1/rdata_reg_2_11[10]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350/CPLD_Reg_1/rdata_reg_2_11[10]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350/CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_18__SLICE_351 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351/CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351/CPLD_Reg_1/rdata_reg_2_11[18]/GATE_H0 + ; + + lut40058 \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351/CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_11[18]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351/CPLD_Reg_1/rdata_reg_2_11[18]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351/CPLD_Reg_1/rdata_reg_2_11[18]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351/CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_1__SLICE_352 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352/CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352/CPLD_Reg_1/rdata_reg_2_11[1]/GATE_H0 + ; + + lut40041 \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352/CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_11[1]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352/CPLD_Reg_1/rdata_reg_2_11[1]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352/CPLD_Reg_1/rdata_reg_2_11[1]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352/CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_2__SLICE_353 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353/CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353/CPLD_Reg_1/rdata_reg_2_11[2]/GATE_H0 + ; + + lut40041 \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353/CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_11[2]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353/CPLD_Reg_1/rdata_reg_2_11[2]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353/CPLD_Reg_1/rdata_reg_2_11[2]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353/CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_3__SLICE_354 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354/CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354/CPLD_Reg_1/rdata_reg_2_11[3]/GATE_H0 + ; + + lut40058 \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354/CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_11[3]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354/CPLD_Reg_1/rdata_reg_2_11[3]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354/CPLD_Reg_1/rdata_reg_2_11[3]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354/CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_4__SLICE_355 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355/CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355/CPLD_Reg_1/rdata_reg_2_11[4]/GATE_H0 + ; + + lut40058 \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355/CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_11[4]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355/CPLD_Reg_1/rdata_reg_2_11[4]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355/CPLD_Reg_1/rdata_reg_2_11[4]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355/CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_5__SLICE_356 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356/CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356/CPLD_Reg_1/rdata_reg_2_11[5]/GATE_H0 + ; + + lut40058 \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356/CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_11[5]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356/CPLD_Reg_1/rdata_reg_2_11[5]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356/CPLD_Reg_1/rdata_reg_2_11[5]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356/CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_6__SLICE_357 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357/CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357/CPLD_Reg_1/rdata_reg_2_11[6]/GATE_H0 + ; + + lut40058 \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357/CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_11[6]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357/CPLD_Reg_1/rdata_reg_2_11[6]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357/CPLD_Reg_1/rdata_reg_2_11[6]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357/CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_7__SLICE_358 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358/CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358/CPLD_Reg_1/rdata_reg_2_11[7]/GATE_H0 + ; + + lut40058 \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358/CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_11[7]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358/CPLD_Reg_1/rdata_reg_2_11[7]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358/CPLD_Reg_1/rdata_reg_2_11[7]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358/CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_8__SLICE_359 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359/CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359/CPLD_Reg_1/rdata_reg_2_11[8]/GATE_H0 + ; + + lut40058 \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359/CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_11[8]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359/CPLD_Reg_1/rdata_reg_2_11[8]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359/CPLD_Reg_1/rdata_reg_2_11[8]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359/CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_17__SLICE_360 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360/CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360/CPLD_Reg_1/rdata_reg_2_11[17]/GATE_H0 + ; + + lut40058 \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360/CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_11[17]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360/CPLD_Reg_1/rdata_reg_2_11[17]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360/CPLD_Reg_1/rdata_reg_2_11[17]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360/CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_19__SLICE_361 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361/CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361/CPLD_Reg_1/rdata_reg_2_11[19]/GATE_H0 + ; + + lut40058 \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361/CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_11[19]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361/CPLD_Reg_1/rdata_reg_2_11[19]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361/CPLD_Reg_1/rdata_reg_2_11[19]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361/CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_20__SLICE_362 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362/CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362/CPLD_Reg_1/rdata_reg_2_11[20]/GATE_H0 + ; + + lut40058 \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362/CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_11[20]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362/CPLD_Reg_1/rdata_reg_2_11[20]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362/CPLD_Reg_1/rdata_reg_2_11[20]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362/CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_21__SLICE_363 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363/CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363/CPLD_Reg_1/rdata_reg_2_11[21]/GATE_H0 + ; + + lut40058 \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363/CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_11[21]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363/CPLD_Reg_1/rdata_reg_2_11[21]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363/CPLD_Reg_1/rdata_reg_2_11[21]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363/CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_22__SLICE_364 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364/CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364/CPLD_Reg_1/rdata_reg_2_11[22]/GATE_H0 + ; + + lut40058 \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364/CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_11[22]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364/CPLD_Reg_1/rdata_reg_2_11[22]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364/CPLD_Reg_1/rdata_reg_2_11[22]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364/CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_23__SLICE_365 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365/CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365/CPLD_Reg_1/rdata_reg_2_10[23]/GATE_H0 + ; + + lut40041 \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365/CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_10[23]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365/CPLD_Reg_1/rdata_reg_2_10[23]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365/CPLD_Reg_1/rdata_reg_2_10[23]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365/CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_23__SLICE_366 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366/CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366/CPLD_Reg_1/rdata_reg_2_9[23]/GATE_H0 + ; + + lut40059 \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366/CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[23]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366/CPLD_Reg_1/rdata_reg_2_9[23]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366/CPLD_Reg_1/rdata_reg_2_9[23]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366/CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_0__SLICE_367 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367/CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367/CPLD_Reg_1/rdata_reg_2_9[0]/GATE_H0 + ; + + lut40042 \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367/CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[0]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367/CPLD_Reg_1/rdata_reg_2_9[0]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367/CPLD_Reg_1/rdata_reg_2_9[0]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367/CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_9__SLICE_368 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368/CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368/CPLD_Reg_1/rdata_reg_2_10[9]/GATE_H0 + ; + + lut40041 \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368/CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_10[9]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368/CPLD_Reg_1/rdata_reg_2_10[9]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368/CPLD_Reg_1/rdata_reg_2_10[9]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368/CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_9__SLICE_369 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369/CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369/CPLD_Reg_1/rdata_reg_2_9[9]/GATE_H0 + ; + + lut40042 \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369/CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[9]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369/CPLD_Reg_1/rdata_reg_2_9[9]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369/CPLD_Reg_1/rdata_reg_2_9[9]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369/CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_i_m2_16__SLICE_370 ( input C1, B1, A1, C0, B0, + A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370/CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370/CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/GATE_H0 + ; + + lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370/CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370/CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370/CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370/CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370_FXMUX ( .D0(FXA), + .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_i_m2_15__SLICE_371 ( input C1, B1, A1, C0, B0, + A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371/CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371/CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/GATE_H0 + ; + + lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371/CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371/CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371/CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371/CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371_FXMUX ( .D0(FXA), + .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_i_m2_14__SLICE_372 ( input C1, B1, A1, C0, B0, + A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372/CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372/CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/GATE_H0 + ; + + lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372/CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372/CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372/CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372/CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372_FXMUX ( .D0(FXA), + .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_i_m2_13__SLICE_373 ( input C1, B1, A1, C0, B0, + A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/GATE_H0 + ; + + lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373_FXMUX ( .D0(FXA), + .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_i_m2_12__SLICE_374 ( input C1, B1, A1, C0, B0, + A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374/CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374/CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/GATE_H0 + ; + + lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374/CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374/CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374/CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374/CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374_FXMUX ( .D0(FXA), + .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_i_m2_11__SLICE_375 ( input C1, B1, A1, C0, B0, + A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375/CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375/CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/GATE_H0 + ; + + lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375/CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375/CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375/CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375/CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375_FXMUX ( .D0(FXA), + .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_i_m2_10__SLICE_376 ( input C1, B1, A1, C0, B0, + A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/GATE_H0 + ; + + lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376_FXMUX ( .D0(FXA), + .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_16__SLICE_377 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377/CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377/CPLD_Reg_1/rdata_reg_2_9[16]/GATE_H0 + ; + + lut40059 \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377/CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[16]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377/CPLD_Reg_1/rdata_reg_2_9[16]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377/CPLD_Reg_1/rdata_reg_2_9[16]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377/CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_15__SLICE_378 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378/CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378/CPLD_Reg_1/rdata_reg_2_9[15]/GATE_H0 + ; + + lut40059 \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378/CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[15]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378/CPLD_Reg_1/rdata_reg_2_9[15]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378/CPLD_Reg_1/rdata_reg_2_9[15]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378/CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_14__SLICE_379 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379/CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379/CPLD_Reg_1/rdata_reg_2_9[14]/GATE_H0 + ; + + lut40059 \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379/CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[14]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379/CPLD_Reg_1/rdata_reg_2_9[14]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379/CPLD_Reg_1/rdata_reg_2_9[14]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379/CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_13__SLICE_380 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380/CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380/CPLD_Reg_1/rdata_reg_2_9[13]/GATE_H0 + ; + + lut40059 \CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380/CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[13]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380/CPLD_Reg_1/rdata_reg_2_9[13]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380/CPLD_Reg_1/rdata_reg_2_9[13]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380/CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_12__SLICE_381 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381/CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381/CPLD_Reg_1/rdata_reg_2_9[12]/GATE_H0 + ; + + lut40059 \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381/CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[12]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381/CPLD_Reg_1/rdata_reg_2_9[12]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381/CPLD_Reg_1/rdata_reg_2_9[12]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381/CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_11__SLICE_382 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382/CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382/CPLD_Reg_1/rdata_reg_2_9[11]/GATE_H0 + ; + + lut40059 \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382/CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[11]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382/CPLD_Reg_1/rdata_reg_2_9[11]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382/CPLD_Reg_1/rdata_reg_2_9[11]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382/CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_10__SLICE_383 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383/CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383/CPLD_Reg_1/rdata_reg_2_9[10]/GATE_H0 + ; + + lut40042 \CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383/CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[10]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383/CPLD_Reg_1/rdata_reg_2_9[10]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383/CPLD_Reg_1/rdata_reg_2_9[10]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383/CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_18__SLICE_384 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384/CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384/CPLD_Reg_1/rdata_reg_2_10[18]/GATE_H0 + ; + + lut40041 \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384/CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_10[18]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384/CPLD_Reg_1/rdata_reg_2_10[18]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384/CPLD_Reg_1/rdata_reg_2_10[18]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384/CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_18__SLICE_385 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385/CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385/CPLD_Reg_1/rdata_reg_2_9[18]/GATE_H0 + ; + + lut40059 \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385/CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[18]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385/CPLD_Reg_1/rdata_reg_2_9[18]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385/CPLD_Reg_1/rdata_reg_2_9[18]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385/CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_1__SLICE_386 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386/CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386/CPLD_Reg_1/rdata_reg_2_10[1]/GATE_H0 + ; + + lut40041 \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386/CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_10[1]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386/CPLD_Reg_1/rdata_reg_2_10[1]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386/CPLD_Reg_1/rdata_reg_2_10[1]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386/CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_1__SLICE_387 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387/CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387/CPLD_Reg_1/rdata_reg_2_9[1]/GATE_H0 + ; + + lut40042 \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387/CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[1]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387/CPLD_Reg_1/rdata_reg_2_9[1]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387/CPLD_Reg_1/rdata_reg_2_9[1]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387/CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_2__SLICE_388 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388/CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388/CPLD_Reg_1/rdata_reg_2_9[2]/GATE_H0 + ; + + lut40042 \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388/CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[2]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388/CPLD_Reg_1/rdata_reg_2_9[2]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388/CPLD_Reg_1/rdata_reg_2_9[2]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388/CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_2__SLICE_389 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389/CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389/CPLD_Reg_1/rdata_reg_2_10[2]/GATE_H0 + ; + + lut40041 \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389/CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_10[2]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389/CPLD_Reg_1/rdata_reg_2_10[2]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389/CPLD_Reg_1/rdata_reg_2_10[2]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389/CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_3__SLICE_390 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390/CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390/CPLD_Reg_1/rdata_reg_2_9[3]/GATE_H0 + ; + + lut40042 \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390/CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[3]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390/CPLD_Reg_1/rdata_reg_2_9[3]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390/CPLD_Reg_1/rdata_reg_2_9[3]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390/CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_3__SLICE_391 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391/CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391/CPLD_Reg_1/rdata_reg_2_10[3]/GATE_H0 + ; + + lut40041 \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391/CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_10[3]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391/CPLD_Reg_1/rdata_reg_2_10[3]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391/CPLD_Reg_1/rdata_reg_2_10[3]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391/CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_4__SLICE_392 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392/CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392/CPLD_Reg_1/rdata_reg_2_9[4]/GATE_H0 + ; + + lut40042 \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392/CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[4]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392/CPLD_Reg_1/rdata_reg_2_9[4]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392/CPLD_Reg_1/rdata_reg_2_9[4]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392/CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_4__SLICE_393 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393/CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393/CPLD_Reg_1/rdata_reg_2_10[4]/GATE_H0 + ; + + lut40041 \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393/CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_10[4]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393/CPLD_Reg_1/rdata_reg_2_10[4]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393/CPLD_Reg_1/rdata_reg_2_10[4]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393/CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_5__SLICE_394 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394/CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394/CPLD_Reg_1/rdata_reg_2_9[5]/GATE_H0 + ; + + lut40042 \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394/CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[5]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394/CPLD_Reg_1/rdata_reg_2_9[5]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394/CPLD_Reg_1/rdata_reg_2_9[5]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394/CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_5__SLICE_395 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395/CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395/CPLD_Reg_1/rdata_reg_2_10[5]/GATE_H0 + ; + + lut40041 \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395/CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_10[5]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395/CPLD_Reg_1/rdata_reg_2_10[5]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395/CPLD_Reg_1/rdata_reg_2_10[5]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395/CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_6__SLICE_396 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396/CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396/CPLD_Reg_1/rdata_reg_2_9[6]/GATE_H0 + ; + + lut40042 \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396/CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[6]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396/CPLD_Reg_1/rdata_reg_2_9[6]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396/CPLD_Reg_1/rdata_reg_2_9[6]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396/CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_6__SLICE_397 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397/CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397/CPLD_Reg_1/rdata_reg_2_10[6]/GATE_H0 + ; + + lut40041 \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397/CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_10[6]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397/CPLD_Reg_1/rdata_reg_2_10[6]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397/CPLD_Reg_1/rdata_reg_2_10[6]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397/CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_7__SLICE_398 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398/CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398/CPLD_Reg_1/rdata_reg_2_9[7]/GATE_H0 + ; + + lut40042 \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398/CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[7]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398/CPLD_Reg_1/rdata_reg_2_9[7]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398/CPLD_Reg_1/rdata_reg_2_9[7]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398/CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_7__SLICE_399 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399/CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399/CPLD_Reg_1/rdata_reg_2_10[7]/GATE_H0 + ; + + lut40041 \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399/CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_10[7]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399/CPLD_Reg_1/rdata_reg_2_10[7]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399/CPLD_Reg_1/rdata_reg_2_10[7]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399/CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_8__SLICE_400 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400/CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400/CPLD_Reg_1/rdata_reg_2_9[8]/GATE_H0 + ; + + lut40042 \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400/CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[8]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400/CPLD_Reg_1/rdata_reg_2_9[8]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400/CPLD_Reg_1/rdata_reg_2_9[8]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400/CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_8__SLICE_401 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401/CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401/CPLD_Reg_1/rdata_reg_2_10[8]/GATE_H0 + ; + + lut40041 \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401/CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Reg_1/rdata_reg_2_10[8]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401/CPLD_Reg_1/rdata_reg_2_10[8]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401/CPLD_Reg_1/rdata_reg_2_10[8]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401/CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_17__SLICE_402 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402/CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402/CPLD_Reg_1/rdata_reg_2_9[17]/GATE_H0 + ; + + lut40059 \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402/CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[17]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402/CPLD_Reg_1/rdata_reg_2_9[17]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402/CPLD_Reg_1/rdata_reg_2_9[17]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402/CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_17__SLICE_403 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403/CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403/CPLD_Reg_1/rdata_reg_2_10[17]/GATE_H0 + ; + + lut40041 \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403/CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_10[17]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403/CPLD_Reg_1/rdata_reg_2_10[17]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403/CPLD_Reg_1/rdata_reg_2_10[17]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403/CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_19__SLICE_404 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404/CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404/CPLD_Reg_1/rdata_reg_2_9[19]/GATE_H0 + ; + + lut40059 \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404/CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[19]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404/CPLD_Reg_1/rdata_reg_2_9[19]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404/CPLD_Reg_1/rdata_reg_2_9[19]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404/CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_19__SLICE_405 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405/CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405/CPLD_Reg_1/rdata_reg_2_10[19]/GATE_H0 + ; + + lut40041 \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405/CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_10[19]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405/CPLD_Reg_1/rdata_reg_2_10[19]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405/CPLD_Reg_1/rdata_reg_2_10[19]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405/CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_20__SLICE_406 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406/CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406/CPLD_Reg_1/rdata_reg_2_9[20]/GATE_H0 + ; + + lut40059 \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406/CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[20]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406/CPLD_Reg_1/rdata_reg_2_9[20]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406/CPLD_Reg_1/rdata_reg_2_9[20]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406/CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_20__SLICE_407 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407/CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407/CPLD_Reg_1/rdata_reg_2_10[20]/GATE_H0 + ; + + lut40041 \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407/CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_10[20]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407/CPLD_Reg_1/rdata_reg_2_10[20]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407/CPLD_Reg_1/rdata_reg_2_10[20]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407/CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_21__SLICE_408 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408/CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408/CPLD_Reg_1/rdata_reg_2_9[21]/GATE_H0 + ; + + lut40059 \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408/CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[21]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408/CPLD_Reg_1/rdata_reg_2_9[21]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408/CPLD_Reg_1/rdata_reg_2_9[21]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408/CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_21__SLICE_409 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409/CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409/CPLD_Reg_1/rdata_reg_2_10[21]/GATE_H0 + ; + + lut40041 \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409/CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_10[21]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409/CPLD_Reg_1/rdata_reg_2_10[21]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409/CPLD_Reg_1/rdata_reg_2_10[21]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409/CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_22__SLICE_410 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410/CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410/CPLD_Reg_1/rdata_reg_2_9[22]/GATE_H0 + ; + + lut40059 \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410/CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_9[22]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410/CPLD_Reg_1/rdata_reg_2_9[22]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410/CPLD_Reg_1/rdata_reg_2_9[22]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410/CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_22__SLICE_411 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411/CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411/CPLD_Reg_1/rdata_reg_2_10[22]/GATE_H0 + ; + + lut40041 \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411/CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 \CPLD_Reg_1/rdata_reg_2_10[22]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411/CPLD_Reg_1/rdata_reg_2_10[22]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411/CPLD_Reg_1/rdata_reg_2_10[22]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411/CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_412 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40060 \CPLD_Con_1/un1_i_DC_Con1_4_axbxc1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40061 \CPLD_Con_1/RC_RLSel_13_0_a3[10] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][5] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][4] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40060 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFCA9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40061 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_413 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40062 \CPLD_Con_1/DMM_en_22_0_a2[15] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40063 \CPLD_Con_1/DMM_en_22_0_0[15] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40062 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40063 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_414 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40064 \BUS_Con_1/un1_addr_out_0_sqmuxa_0_i ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40065 \BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 \BUS_Con_1/recv_reg[16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/recv_reg[15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40064 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFD3D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40065 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7775) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_415 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40066 \CPLD_Con_1/DMM_en_22_0_a2_2[10] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40067 \CPLD_Con_1/DMM_en_22_0_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40066 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40067 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4448) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_416 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40068 \CPLD_Con_1/RC_VISel_1_sqmuxa ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40069 \CPLD_Con_1/err_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][12] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][11] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40068 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40069 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h88F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_417 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40070 \CPLD_Con_1/un1_i_freq_relay1lto6_RNI064ES ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40071 \CPLD_Con_1/un1_i_freq_relay1lto6 ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][9] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][8] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40070 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0511) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40071 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1F1F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_418 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40072 \CPLD_Con_1/g0_14 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40028 \CPLD_Con_1/DMM_en_11_sqmuxa_0_147_i_i_0_0_tz ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 \BUS_Con_1/recv_reg[21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/recv_reg[20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40072 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_419 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40073 \CPLD_Con_1/g1_0_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40074 \CPLD_Con_1/g0_26_x0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][5] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][4] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40073 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFCA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40074 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF801) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_420 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40075 \CPLD_Con_1/PMU_OC_4_8_0_a2[28] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40047 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNIPVVMC[28] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][23] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][22] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40075 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_421 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40020 \CPLD_Con_1/PMU_OC_4_8_0_a2[26] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40047 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNINTVMC[26] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][14] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][13] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_422 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40076 \CPLD_Con_1/OC_x0112lto8_1_i_RNI7NLPL ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40045 \CPLD_Con_1/DMM_en_1_sqmuxa_1_0_a2_0_a2_0_a2_0_0 ( .A(A0), .B(B0), + .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/recv_reg[25] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0004 \BUS_Con_1/recv_reg[24] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40076 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_423 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40077 \CPLD_Con_1/PMU_OC_4_8_0_a2_2[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40076 \CPLD_Con_1/PMU_OC_4_8_0_a2_2_RNID4RHA[3] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][10] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40077 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_424 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40078 \CPLD_Con_1/un1_i_DC_Con1_1_iv[4] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40079 \CPLD_Con_1/DMM_en_22_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][5] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][4] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40078 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40079 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_425 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40024 \CPLD_Con_1/PMU_OC_1_8_0_a2[27] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40062 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNI3C04G[27] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][21] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][20] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_426 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40012 \CPLD_Con_1/PMU_OC_1_8_0_a2[29] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40062 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNI5E04G[29] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][5] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][4] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_427 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut4 \CPLD_Con_1/PMU_OC_1_8_0_a2[26] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40062 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNIU604G[26] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][23] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][22] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_428 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40068 \CPLD_Con_1/PMU_OC_1_8_0_a2[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40076 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNI3C04G_0[27] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][23] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][22] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_429 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40024 \CPLD_Con_1/PMU_OC_1_8_0_a2[10] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40062 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNINUU3G[10] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][14] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][13] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_430 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40033 \CPLD_Con_1/PMU_OC_1_8_0_o2[17] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40075 \CPLD_Con_1/PMU_OC_1_8_0_o2_RNIGGDKI_1[17] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][10] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_431 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut4 \CPLD_Con_1/PMU_OC_1_8_0_a2[31] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40020 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNIU714G[31] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_432 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40033 \CPLD_Con_1/g0_27 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40080 \CPLD_Con_1/PMU_OC_2_8_0_a2_RNIFF75V[17] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][12] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][11] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40080 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_433 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40068 \CPLD_Con_1/PMU_OC_2_8_0_a2[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40081 \CPLD_Con_1/PMU_OC_2_8_0_a2_RNIV5H461_0[8] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][16] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][15] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40081 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_434 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40078 \CPLD_Con_1/un1_i_DC_Con1_1_iv[5] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40045 \CPLD_Con_1/DMM_en_22_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_435 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40082 \CPLD_Con_1/PMU_OC_1_8_0_a2[24] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40080 \CPLD_Con_1/PMU_OC_1_8_0_o2_RNI5VQ7I[17] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][5] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][4] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40082 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_436 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40083 \CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNI54G4K2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40013 \CPLD_Con_1/un1_exec_flag_8_0_a3_RNIM00E93 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7]_fast[6] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7]_fast[5] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40083 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA2AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_437 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40084 \CPLD_Con_1/un1_exec_flag_8_0_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40085 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNIL1I393[20] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][12] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][11] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40084 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40085 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h01FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_438 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40066 \CPLD_Con_1/PMU_OC_4_8_0_a2[18] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40085 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNIS7H393[18] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][9] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][8] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_439 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40086 \CPLD_Con_1/DMM_en_22_0_a2_2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40087 \CPLD_Con_1/DMM_en_22_0[5] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40086 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8880) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40087 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF2F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_440 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40078 \CPLD_Con_1/un1_i_DC_Con1_1_iv[1] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40088 \CPLD_Con_1/DMM_en_22_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40088 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_441 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40086 \CPLD_Con_1/DMM_en_22_0_a2_1[12] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40089 \CPLD_Con_1/DMM_en_22_0[12] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/recv_reg[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/recv_reg[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40089 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF1F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_442 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40090 \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[0] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40088 \CPLD_Con_1/DMM_en_22_0[14] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40090 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_443 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40091 \CPLD_Con_1/DMM_en_22_0_RNO[13] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40092 \CPLD_Con_1/DMM_en_22_0[13] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/recv_reg[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/recv_reg[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40091 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h30A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40092 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_444 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40093 \CPLD_Con_1/PMU_OC_3_8_0_o2_RNIBDD741[8] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40085 \CPLD_Con_1/un1_exec_flag_2_0_0_RNI3RHOG1 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][21] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][20] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40093 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8AA8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_445 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40094 \CPLD_Con_1/err_flag19_0_0_0_RNI48FPT3 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40085 \CPLD_Con_1/un1_exec_flag_3_0_0_RNISFCLD4 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][5] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][4] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40094 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_446 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40095 \CPLD_Con_1/DMM_en_22_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40063 \CPLD_Con_1/DMM_en_22_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40095 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEEEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_447 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40081 \CPLD_Con_1/OC_x0161_1_RNI65N7D_0 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40096 \CPLD_Con_1/DMM_en_22[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 \BUS_Con_1/recv_reg[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/recv_reg[31] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40096 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0ACC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_448 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40077 \CPLD_Con_1/dc_slot_flag_0_rep1_RNI2FE7E_1 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40097 \CPLD_Con_1/un1_exec_flag_4_0_0_RNIJDPEM ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][9] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][8] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40097 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0B0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_449 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40098 \CPLD_Con_1/RC_RLSel_13_0_a3_2[12] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40008 \CPLD_Con_1/RC_RLSel_13_0_a3_0[9] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][10] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40098 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h6A00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_450 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40099 \CPLD_Con_1/RC_RLSel_13_0_a2[12] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40100 \CPLD_Con_1/RC_RLSel_13_0_a3_0[12] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][9] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][8] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40099 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40100 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_451 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40099 \CPLD_Con_1/RC_RLSel_13_0_a2[11] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40081 \CPLD_Con_1/RC_RLSel_13_0_a3[11] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][7] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][6] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_452 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40101 \CPLD_Con_1/PMU_OC_3_8_0_o2_RNIO6S4K[8] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40102 \CPLD_Con_1/un1_exec_flag_2_0_0_RNIB6HR41 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][23] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][22] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40101 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFAEB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40102 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0507) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_453 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40079 \CPLD_Con_1/dc_slot_flag_RNIANH1R_1[0] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40102 \CPLD_Con_1/un1_exec_flag_3_0_0_RNIRD7G43 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_454 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40078 \CPLD_Con_1/un1_i_DC_Con1_1_iv[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40063 \CPLD_Con_1/DMM_en_22_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/recv_reg[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/recv_reg[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_455 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40103 \CPLD_Con_1/RC_RLSel_13_0_a2_1[16] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40081 \CPLD_Con_1/RC_RLSel_13_0_a2[17] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][18] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][17] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40103 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5454) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_456 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40104 \CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40061 \CPLD_Con_1/RC_RLSel_13_0_a2[16] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][16] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][15] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40104 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_457 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40105 \CPLD_Con_1/un1_DMM_en_42 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40066 \CPLD_Con_1/DMM_en_22[16] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 \BUS_Con_1/recv_reg[27] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/recv_reg[26] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40105 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_458 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40106 \CPLD_Con_1/un1_i_rst_n_i_o2 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40066 \CPLD_Con_1/DMM_en_22[17] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 \BUS_Con_1/recv_reg[29] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/recv_reg[28] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40106 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_459 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40024 \CPLD_Con_1/un1_DMM_en_64 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40066 \CPLD_Con_1/DMM_en_22[18] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 \BUS_Con_1/recv_reg[30] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0004 \BUS_Con_1/recv_reg[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_460 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40107 \CPLD_Con_1/freq_slot_flag_RNI40NF7[0] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40099 \CPLD_Con_1/DMM_en_22_0_o2_RNI6TDVF[14] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][21] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][20] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40107 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_461 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40075 \CPLD_Con_1/freq_slot_flag_RNI84VGB[1] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40108 \CPLD_Con_1/DMM_en_22_0_o2_0_RNI5A4QI[7] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][19] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40108 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0280) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_462 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40109 \CPLD_Con_1/DMM_en_22_0_a2_3[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40099 \CPLD_Con_1/DMM_en_22_0_a2[14] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40109 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_463 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40075 \CPLD_Con_1/DMM_en_22_0_a2_0_0[6] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40108 \CPLD_Con_1/DMM_en_22_0_a2[6] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][5] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][4] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_464 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40105 \CPLD_Con_1/OC_x0139_i_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40110 \CPLD_Con_1/DMM_en_22_0_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40110 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFAF2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_465 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, LSR, + CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40111 \CPLD_Con_1/RC_Tx_0_sqmuxa ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40103 \CPLD_Con_1/done_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0010 \CPLD_Con_1/done_flag ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40111 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFE00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_466 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40008 \CPLD_Con_1/RC_Tx_1_sqmuxa ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40001 \CPLD_Con_1/RC_Tx_1_sqmuxa_RNIGOE0D ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][14] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][13] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_467 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40043 \CPLD_Con_1/DMM_en_1_sqmuxa_1_0_a2_0_a2_0_a2_0 ( .A(A1), .B(B1), + .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40112 \CPLD_Con_1/un1_i_freq_relay1_1lto8 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][7] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][6] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40112 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h002F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_468 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40113 \CPLD_Con_1/DMM_en_22_0_o2_1[13] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40114 \CPLD_Con_1/DMM_en_22_0_o2[14] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][18] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][17] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40113 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40114 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h05C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_469 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40047 \CPLD_Con_1/OC_x0161_1_RNI5O3CC ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40091 \CPLD_Con_1/un1_i_freq_relay3_1lto8_i_o2_RNIASAE02 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8]_fast[6] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8]_fast[5] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_470 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40012 \CPLD_Con_1/PMU_OC_3_8_0_a2[18] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40080 \CPLD_Con_1/PMU_OC_3_8_0_a4[26] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][19] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][18] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_471 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut4 \CPLD_Con_1/PMU_OC_3_8_0_a2_0[17] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40080 \CPLD_Con_1/PMU_OC_3_8_0_a4[27] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][20] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][1] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_472 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40068 \CPLD_Con_1/PMU_OC_3_8_0_a2[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40047 \CPLD_Con_1/PMU_OC_3_8_0_a4[28] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][22] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][21] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_473 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40107 \CPLD_Con_1/PMU_OC_3_8_0_a2[10] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40115 \CPLD_Con_1/PMU_OC_3_8_0_a4[10] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40115 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_474 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40024 \CPLD_Con_1/PMU_OC_3_8_0_a2[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40080 \CPLD_Con_1/PMU_OC_3_8_0_a4[11] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][5] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][4] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_475 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40082 \CPLD_Con_1/PMU_OC_3_8_0_a2[17] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40080 \CPLD_Con_1/PMU_OC_3_8_0_a4[18] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][11] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][10] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_476 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40115 \CPLD_Con_1/PMU_OC_3_8_0_a2_0[18] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40107 \CPLD_Con_1/PMU_OC_3_8_0_a4[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][5] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][4] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_477 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40116 \CPLD_Con_1/PMU_OC_3_8_0_a2[20] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40107 \CPLD_Con_1/PMU_OC_3_8_0_a4[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][10] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40116 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_478 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40099 \CPLD_Con_1/PMU_OC_3_8_0_a2[22] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40107 \CPLD_Con_1/PMU_OC_3_8_0_a4[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][12] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][11] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_479 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40012 \CPLD_Con_1/PMU_OC_2_8_0_a2[18] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40080 \CPLD_Con_1/PMU_OC_2_8_0_a4[26] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][10] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_480 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut4 \CPLD_Con_1/PMU_OC_2_8_0_a2_0[17] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40080 \CPLD_Con_1/PMU_OC_2_8_0_a4[27] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][12] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][11] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_481 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40107 \CPLD_Con_1/PMU_OC_2_8_0_a2[10] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40115 \CPLD_Con_1/PMU_OC_2_8_0_a4[10] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][19] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_482 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40024 \CPLD_Con_1/PMU_OC_2_8_0_a2[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40080 \CPLD_Con_1/PMU_OC_2_8_0_a4[11] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][21] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][20] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_483 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40082 \CPLD_Con_1/PMU_OC_2_8_0_a2[17] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40080 \CPLD_Con_1/PMU_OC_2_8_0_a4[18] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][5] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][4] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_484 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40115 \CPLD_Con_1/PMU_OC_2_8_0_a2_0[18] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40107 \CPLD_Con_1/PMU_OC_2_8_0_a4[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][18] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][17] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_485 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40116 \CPLD_Con_1/PMU_OC_2_8_0_a2[20] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40107 \CPLD_Con_1/PMU_OC_2_8_0_a4[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][19] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_486 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40099 \CPLD_Con_1/PMU_OC_2_8_0_a2[22] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40107 \CPLD_Con_1/PMU_OC_2_8_0_a4[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][21] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][20] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_487 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40117 \CPLD_Con_1/DMM_en_22_0_a2_1[4] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40118 \CPLD_Con_1/DMM_en_22_0_a2[12] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40117 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40118 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_488 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40021 \CPLD_Con_1/err_flag13_0_o2_0_2_RNIH4D9O ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40119 \CPLD_Con_1/DMM_en_0_sqmuxa_3 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/recv_reg[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/recv_reg[19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40119 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0104) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_489 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40077 \CPLD_Con_1/un1_DMM_en_43 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40024 \CPLD_Con_1/un1_DMM_en_63 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][18] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][17] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_490 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40077 \CPLD_Con_1/DMM_en_22_0_a2_3[4] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40120 \CPLD_Con_1/DMM_en_22_0_a2[5] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40120 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0880) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_491 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40072 \CPLD_Con_1/DMM_en_22_0_o2_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40066 \CPLD_Con_1/DMM_en_22_0_a2_3_RNIK2BQH[4] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][14] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][13] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_492 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40033 \CPLD_Con_1/DMM_en_22_0_o2[15] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40118 \CPLD_Con_1/DMM_en_22_0_o2_RNI8QTBL[15] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][23] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][22] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_493 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40013 \CPLD_Con_1/dc_slot_flag_0_rep1_RNI2FE7E ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40066 \CPLD_Con_1/PMU_OC_3_8_0_a4[8] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][14] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][13] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_494 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40104 \CPLD_Con_1/un1_i_DC_Con1_1_iv_1[2] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40079 \CPLD_Con_1/un1_DMM_en_44_0_a2 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][14] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][13] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_495 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40104 \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[2] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40066 \CPLD_Con_1/un1_DMM_en_45 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][16] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][15] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_496 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40121 \CPLD_Con_1/N_11_1.SUM0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40122 \CPLD_Con_1/N_18_ac0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][12] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][11] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40121 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h9696) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40122 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h9600) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_497 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40123 \CPLD_Con_1/PMU_OC_2_2_500_0_a2_i_o2 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40124 \CPLD_Con_1/PMU_OC_4_8_0_a2[29] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][9] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][8] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40123 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40124 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_498 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40024 \CPLD_Con_1/PMU_OC_2_2_504_a2_0_0_a3 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40117 \CPLD_Con_1/PMU_OC_4_8_0_a2[17] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][23] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][22] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_499 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40068 \CPLD_Con_1/PMU_OC_4_8_0_a3[29] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40008 \CPLD_Con_1/PMU_OC_4_8_0_a2[21] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][7] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][6] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_500 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40024 \CPLD_Con_1/DMM_en_22_0_a2_0_2_RNO[10] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40020 \CPLD_Con_1/DMM_en_22_0_a2_0_2[10] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][7] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][6] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_501 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40079 \CPLD_Con_1/OC_x0112lto8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40125 \CPLD_Con_1/OC_x0112lto8_1_i ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][14] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][13] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40125 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFD0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_502 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40045 \CPLD_Con_1/OC_x0153lto2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40072 \CPLD_Con_1/DMM_en_22_0_o2[13] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][16] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][15] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_503 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40008 \CPLD_Con_1/RC_VISel41_0_a2_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40077 \CPLD_Con_1/PMU_OC_4_8_0_a2[20] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][5] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][4] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_504 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40126 \CPLD_Con_1/un1_exec_flag_3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40127 \CPLD_Con_1/RC_RLSel_13_0_o3[16] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][12] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][11] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40126 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0102) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40127 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_505 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40109 \CPLD_Con_1/PMU_OC_4_8_0[25] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40062 \CPLD_Con_1/PMU_OC_4_8[25] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][19] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_506 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40128 \CPLD_Con_1/err_flag13_0_0_0_RNIM0FM71 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40129 \CPLD_Con_1/err_flag13_0_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][21] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][20] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40128 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0041) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40129 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF081) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_507 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40130 \CPLD_Con_1/err_flag19_0_0_0_RNIAI9L43 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40129 \CPLD_Con_1/err_flag19_0_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][7] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][6] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40130 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h407F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_508 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut4 \CPLD_Con_1/freq_t_RNI306E7 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40080 \CPLD_Con_1/DMM_en_22_bm_RNO[11] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][7] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][6] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_509 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40131 \CPLD_Con_1/un1_exec_flag_8_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40084 \CPLD_Con_1/un1_exec_flag_4_0_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][7] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][6] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40131 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0014) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_510 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40043 \CPLD_Con_1/OC_x0161_1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40076 \CPLD_Con_1/OC_x0161_1_RNI65N7D ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][18] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][17] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_511 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40105 \CPLD_Con_1/RC_RLSel_13_0_a3_2_N_4L5 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40090 \CPLD_Con_1/un1_i_DC_Con1_iv_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][14] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][13] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_512 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40132 \CPLD_Con_1/un1_i_DC_Con1_iv_0_RNIHD3I9[2] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40090 \CPLD_Con_1/un1_i_DC_Con1_iv_0[3] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][16] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][15] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40132 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0909) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_513 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40123 \CPLD_Con_1/freq_t_RNI306E7_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40079 \CPLD_Con_1/DMM_en_22_bm_RNO[9] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][9] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][8] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_514 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40043 \CPLD_Con_1/PMU_OC_3_8_0_o2_RNI8EC98[8] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 \CPLD_Con_1/PMU_OC_3_8_0_o2[8] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][18] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][17] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_515 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40133 \CPLD_Con_1/OC_x0161_1_RNIRLPBK ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40081 \CPLD_Con_1/freq_slot_flag_RNI3HKF9[0] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0004 \CPLD_Con_1/freq_slot_flag[1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \CPLD_Con_1/freq_slot_flag[0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40133 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7F5F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_516 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40043 \CPLD_Con_1/RC_RLSel_13_0_a3_2_N_2L1 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40104 \CPLD_Con_1/un1_i_DC_Con1_iv_0_0[4] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][21] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][20] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_517 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40043 \CPLD_Con_1/RC_RLSel_13_0_a3_2_N_3L3 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40104 \CPLD_Con_1/un1_i_DC_Con1_iv_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][12] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][11] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_518 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40105 \CPLD_Con_1/un1_i_DC_Con1_iv_0_RNIUHIA9[1] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40104 \CPLD_Con_1/un1_i_DC_Con1_iv_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][5] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][4] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_519 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40134 \CPLD_Con_1/err_flag19_0_o2_2_RNIDVKG21 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40021 \CPLD_Con_1/err_flag19_0_o2_2 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][10] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40134 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h10EF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_520 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40105 \CPLD_Con_1/err_flag13_0_o2_0_2_RNIH4D9O_0 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40021 \CPLD_Con_1/err_flag13_0_o2_0_2 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][5] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][4] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_521 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40135 \CPLD_Con_1/freq_slot_flag_RNIBOV481_0[0] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40013 \CPLD_Con_1/freq_slot_flag_RNI6S8Q1_0[0] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][14] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][13] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40135 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h55DF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_522 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40136 \CPLD_Con_1/g0_21 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40137 \CPLD_Con_1/err_flag19_0_0_0_RNI07J532 ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][9] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][8] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40136 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40137 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEBEB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_523 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40138 \CPLD_Con_1/dc_slot_flag_RNI1V47R2[0] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40079 \CPLD_Con_1/dc_slot_flag_RNIANH1R_2[0] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0004 \CPLD_Con_1/dc_slot_flag_3_rep1 ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \CPLD_Con_1/dc_slot_flag_2_rep1 ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40138 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0208) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_524 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40139 \CPLD_Con_1/freq_t_RNIJHH7E1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40140 \CPLD_Con_1/freq_slot_flag_RNI6S8Q1[0] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0004 \CPLD_Con_1/freq_slot_flag[3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \CPLD_Con_1/freq_slot_flag[2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40139 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h777F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40140 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_525 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40141 \CPLD_Con_1/g0_19 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 \CPLD_Con_1/g1_1_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6]_fast[6] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6]_fast[5] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40141 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h02FD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_526 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40117 \CPLD_Con_1/freq_t_RNI2O8358 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40142 \CPLD_Con_1/err_flag13_0_0_0_RNI92FNE1 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][23] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][22] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40142 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA88A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_527 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40079 \CPLD_Con_1/g0_3_1_N_5L8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 \CPLD_Con_1/g0_29 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][7] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][6] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_528 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40143 \CPLD_Con_1/err_flag19_0_0_0_RNI2M1DH2_0 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40079 \CPLD_Con_1/dc_slot_flag_0_rep1_RNI2FE7E_0 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0004 \CPLD_Con_1/dc_slot_flag[1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \CPLD_Con_1/dc_slot_flag[0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40143 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3773) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_529 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40144 \CPLD_Con_1/un1_i_DC_Con1_iv_0_RNIL5OH12[2] ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40145 \CPLD_Con_1/dc_t_RNI2Q6P8 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \CPLD_Con_1/dc_slot_flag_fast[1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \CPLD_Con_1/dc_slot_flag_fast[0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40144 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0007) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40145 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_530 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40146 \CPLD_Con_1/dc_t_RNI3B14N1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40013 \CPLD_Con_1/dc_slot_flag_RNIANH1R[0] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0004 \CPLD_Con_1/dc_slot_flag_1_rep1 ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \CPLD_Con_1/dc_slot_flag_0_rep1 ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40146 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h20A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_531 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40147 \CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNILT4CU4_0 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40148 \CPLD_Con_1/g0_10_N_3L3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][21] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][20] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40147 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3BBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40148 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2AFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_532 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40149 \CPLD_Con_1/err_flag13_0_0_0_RNI92FNE1_0 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40150 \CPLD_Con_1/err_flag13_0_0_0_RNILOU7L8 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40149 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5775) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40150 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h40FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_533 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40143 \CPLD_Con_1/err_flag19_0_0_0_RNI2M1DH2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40151 \CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNILT4CU4 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][16] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][15] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40151 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_534 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40066 \CPLD_Con_1/DMM_en_22_0_N_2L1_0 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40152 \CPLD_Con_1/DMM_en_22_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40152 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hABAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_535 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40153 \CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNI54G4K2_0 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40148 \CPLD_Con_1/g0_12_N_3L3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][23] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][22] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40153 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5D55) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_536 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40020 \CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNIKV6UQ7 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40154 \CPLD_Con_1/dc_t_RNI7JEV61 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][19] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40154 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3BB3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_537 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40155 \CPLD_Con_1/dc_slot_flag_0_rep1_RNIULU4R ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40156 \CPLD_Con_1/g0_26/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40155 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5757) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40156 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_538 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40079 \CPLD_Con_1/dc_slot_flag_RNIANH1R_3[0] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40024 \CPLD_Con_1/dc_slot_flag_RNIQ9AIV[0] ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][18] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[5][17] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_539 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40157 \CPLD_Con_1/freq_t_RNIMOCGQC ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40158 \CPLD_Con_1/freq_t_RNIDK1OA3 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][18] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][17] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40157 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hB1F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40158 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFAFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_540 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40123 \CPLD_Con_1/g0_2_x1_N_2L1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40159 \CPLD_Con_1/freq_slot_flag_RNIBOV481[0] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][16] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][15] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40159 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3310) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_541 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40047 \CPLD_Reg_1/state_ns_0_a4_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40020 \CPLD_Reg_1/state_ns_0_a4_0_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][10] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_542 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40062 \CPLD_Reg_1/regtable[8]_1_sqmuxa_0_a2_1 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40047 \CPLD_Reg_1/regtable[8]_1_sqmuxa_0_a2_1_RNIJS6KB_0 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[0][7] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[0][6] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_543 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40020 \CPLD_Reg_1/regtable[1]_1_sqmuxa ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40068 \CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ( .A(A0), .B(B0), + .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[0][14] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[0][13] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_544 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40062 \CPLD_Reg_1/regtable[7]_1_sqmuxa_0_a2_2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40068 \CPLD_Reg_1/regtable[7]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[0][23] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[0][22] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_545 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40062 \CPLD_Reg_1/regtable[6]_1_sqmuxa_0_a2_0 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40068 \CPLD_Reg_1/regtable[2]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[0][16] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[0][15] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_546 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40012 \CPLD_Reg_1/regtable[0]_1_sqmuxa_1 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40062 \CPLD_Reg_1/regtable[5]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[0][1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[0][19] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_547 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40012 \CPLD_Reg_1/state_ns_0_a4_0_0[1] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40160 \CPLD_Reg_1/un10_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][12] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][11] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40160 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_548 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40082 \CPLD_Reg_1/rdata_reg_1_sqmuxa_2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40068 \CPLD_Reg_1/rdata_reg_1_sqmuxa ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[9][14] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[9][13] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_549 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40043 \CPLD_Reg_1/err_flag8_1_0_a2_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40081 \CPLD_Reg_1/err_flag8_1_0_a2 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[9][12] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[9][11] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_550 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40161 \BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNIVM1LH ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40001 \BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ( .A(A0), .B(B0), + .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/recv_reg[10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0004 \BUS_Con_1/recv_reg[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40161 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3733) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_551 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40123 \BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40162 \BUS_Con_1/recv_reg_1_sqmuxa_1_i ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/recv_reg[12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0004 \BUS_Con_1/recv_reg[11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40162 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_552 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40163 \BUS_Con_1/bit_cnt_0_sqmuxa_1_i_o2 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40082 \BUS_Con_1/err_flag_RNO_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][23] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][22] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40163 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAEAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_553 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40008 \BUS_Con_1/bit_cnt_0_sqmuxa_1_i_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40164 \BUS_Con_1/bit_cnt_0_sqmuxa_1_i_a2_RNISVNVG ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][18] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][17] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40164 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h02FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_554 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40066 \BUS_Con_1/un1_bit_cnt_9_ac0_1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40099 \BUS_Con_1/un1_bit_cnt_9_ac0_5 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/recv_reg[18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0004 \BUS_Con_1/recv_reg[17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_555 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40165 \CPLD_Con_1/PMU_OC_4_8_0_a5[8] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40124 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNIPVVMC_0[28] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40165 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_556 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40166 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNINTVMC_0[26] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40124 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNINTVMC_2[26] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][18] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][17] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40166 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_557 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40066 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNIPVVMC_3[28] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40020 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNIPVVMC_1[28] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][5] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][4] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_558 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40075 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNINTVMC_4[26] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40076 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNINTVMC_1[26] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][16] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][15] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_559 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40117 \CPLD_Con_1/PMU_OC_1_8_0_a5[5] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40076 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNI5E04G_0[29] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][7] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][6] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_560 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40117 \CPLD_Con_1/PMU_OC_1_8_0_a5[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40020 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNI3C04G_1[27] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_561 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40008 \CPLD_Con_1/PMU_OC_1_8_0_a5[1] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40080 \CPLD_Con_1/PMU_OC_1_8_0_o2_RNIGGDKI[17] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][7] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][6] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_562 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40077 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNINTVMC_6[26] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40066 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNINTVMC_5[26] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][21] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][20] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_563 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40008 \CPLD_Con_1/PMU_OC_2_8_0_a4[8] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40080 \CPLD_Con_1/PMU_OC_2_8_0_a2_RNIV5H461[8] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][14] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][13] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_564 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40117 \CPLD_Con_1/PMU_OC_1_8_0_a5[6] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40020 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNIJMENF[31] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][12] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][11] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_565 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40117 \CPLD_Con_1/PMU_OC_1_8_0_a5[4] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40020 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNIQSDNF_1[29] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][21] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][20] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_566 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40117 \CPLD_Con_1/PMU_OC_1_8_0_a5[2] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40020 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNIOQDNF_1[27] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][18] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][17] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_567 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40062 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNIQSDNF[29] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40076 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNIQSDNF_0[29] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][19] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_568 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40062 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNIOQDNF[27] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40076 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNIOQDNF_0[27] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][16] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][15] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_569 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40117 \CPLD_Con_1/PMU_OC_3_8_0_a4[25] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40047 \CPLD_Con_1/PMU_OC_3_8_0_a4[29] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_570 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40117 \CPLD_Con_1/PMU_OC_3_8_0_a4[24] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40062 \CPLD_Con_1/PMU_OC_3_8_0_a4[30] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][7] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][6] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_571 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40117 \CPLD_Con_1/PMU_OC_3_8_0_a4[9] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40047 \CPLD_Con_1/PMU_OC_3_8_0_a4[13] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][9] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][8] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_572 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40117 \CPLD_Con_1/PMU_OC_3_8_0_a4[17] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40080 \CPLD_Con_1/PMU_OC_3_8_0_a4[19] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][13] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][12] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_573 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40062 \CPLD_Con_1/PMU_OC_3_8_0_a4[22] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40047 \CPLD_Con_1/PMU_OC_3_8_0_a4[20] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][15] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][14] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_574 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40062 \CPLD_Con_1/PMU_OC_3_8_0_a4[23] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40047 \CPLD_Con_1/PMU_OC_3_8_0_a4[21] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][17] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][16] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_575 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40062 \CPLD_Con_1/PMU_OC_2_8_0_a4[30] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40047 \CPLD_Con_1/PMU_OC_2_8_0_a4[28] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][14] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][13] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_576 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40062 \CPLD_Con_1/PMU_OC_2_8_0_a4[31] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40047 \CPLD_Con_1/PMU_OC_2_8_0_a4[29] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][16] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][15] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_577 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40062 \CPLD_Con_1/PMU_OC_2_8_0_a4[15] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40047 \CPLD_Con_1/PMU_OC_2_8_0_a4[13] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_578 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40062 \CPLD_Con_1/PMU_OC_2_8_0_a4[23] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40080 \CPLD_Con_1/PMU_OC_2_8_0_a4[19] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][7] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][6] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_579 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40062 \CPLD_Con_1/PMU_OC_2_8_0_a4[22] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40047 \CPLD_Con_1/PMU_OC_2_8_0_a4[20] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][9] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][8] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_580 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40013 \CPLD_Con_1/dc_slot_flag_RNIANH1R_0[0] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40167 \CPLD_Con_1/un1_DMM_en_1_sqmuxa_tz ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][12] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][11] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40167 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0116) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_581 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40081 \CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40062 \CPLD_Reg_1/regtable[8]_1_sqmuxa_0_a2_1_RNIJS6KB ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[0][5] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0026 \CPLD_Reg_1/regtable[0][4] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_582 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40076 \CPLD_Reg_1/regtable[14]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40080 \CPLD_Reg_1/regtable[13]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[0][10] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[0][0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_583 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40066 \CPLD_Reg_1/regtable[10]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40075 \CPLD_Reg_1/regtable[9]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[0][9] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0026 \CPLD_Reg_1/regtable[0][8] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_584 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40118 \CPLD_Reg_1/regtable[5]_1_sqmuxa_0_a2_0_0 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40079 \CPLD_Reg_1/un34_regtable_1_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][16] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][15] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_585 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40116 \CPLD_Con_1/PMU_OC_4_8_0_a2_0[28] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40099 \CPLD_Con_1/PMU_OC_4_8_0_a5[23] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][10] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_586 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40109 \CPLD_Con_1/PMU_OC_4_8_0_a2[12] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40116 \CPLD_Con_1/PMU_OC_4_8_0_a2[13] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][21] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][20] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_587 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40107 \CPLD_Con_1/PMU_OC_4_8_0_a2_0[26] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40107 \CPLD_Con_1/PMU_OC_4d_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][12] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][11] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_588 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40045 \CPLD_Con_1/N_155_i ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40075 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNIPVVMC_2[28] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][7] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][6] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_589 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40117 \CPLD_Con_1/PMU_OC_1_8_0_a5[7] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40020 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNI5E04G_1[29] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][9] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][8] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_590 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40081 \CPLD_Con_1/PMU_OC_1_8_0_o2_RNI5VQ7I_0[17] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40081 \CPLD_Con_1/PMU_OC_1_8_0_o2_RNIGGDKI_0[17] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][9] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][8] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_591 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40062 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNIJLDNF[26] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40062 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNICDCNF[10] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][10] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[13][0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_592 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40062 \CPLD_Con_1/PMU_OC_3_8_0_a4[15] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40062 \CPLD_Con_1/PMU_OC_3_8_0_a4[31] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][9] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[1][8] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_593 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40099 \CPLD_Con_1/PMU_OC_3_8_0_a4[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40116 \CPLD_Con_1/PMU_OC_3_8_0_a4[12] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][7] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][6] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_594 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40168 \CPLD_Con_1/g0_2_N_2L1_1_N_2L1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40079 \CPLD_Con_1/OC_x0161_1_RNI9RGEE1 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][19] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40168 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h007F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_595 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40099 \CPLD_Con_1/PMU_OC_2_8_0_a4[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40116 \CPLD_Con_1/PMU_OC_2_8_0_a4[12] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][23] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][22] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_596 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40080 \CPLD_Con_1/DMM_en_22_0_a2_1_1[7] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40080 \CPLD_Con_1/DMM_en_22_0_a2_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][9] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][8] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_597 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40121 \CPLD_Con_1/N_13_1.m2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40169 \CPLD_Con_1/N_13_1.m5 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][10] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40169 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1717) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_598 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40170 \CPLD_Con_1/freq_t_RNIL44QK1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40099 \CPLD_Con_1/io_RC_1_sqmuxa ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][10] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40170 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h80FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_599 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40045 \CPLD_Con_1/g0_14_N_2L1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40113 \CPLD_Con_1/DMM_en_11_sqmuxa_0_147_i_i_o2 ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre0004 \BUS_Con_1/recv_reg[23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0004 \BUS_Con_1/recv_reg[22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_600 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40115 \CPLD_Con_1/RC_RLSel_13_0_a2[4] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40116 \CPLD_Con_1/RC_RLSel_13_0_a2[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_601 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40107 \CPLD_Con_1/RC_RLSel_13_0_a2[15] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40116 \CPLD_Con_1/RC_RLSel_13_0_a2[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][23] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][22] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_602 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40116 \CPLD_Con_1/RC_RLSel_13_0_a2[10] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40115 \CPLD_Con_1/RC_RLSel_13_0_a2[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][21] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][20] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_603 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40116 \CPLD_Con_1/RC_RLSel_13_0_a2[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40115 \CPLD_Con_1/RC_RLSel_13_0_a2[5] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][19] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_604 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40115 \CPLD_Reg_1/regtable[4]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40099 \CPLD_Reg_1/regtable[6]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre0026 \CPLD_Reg_1/regtable[0][21] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[0][20] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_605 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40171 \BUS_Con_1/miso_shift_1_sqmuxa_i_0 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40172 \BUS_Con_1/sclk_sync_RNIUSFSG[1] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/recv_reg[14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0004 \BUS_Con_1/recv_reg[13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40171 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBABA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40172 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF5D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_606 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40173 \BUS_Con_1/state_ns_1_0_.m6_i_a2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40174 \BUS_Con_1/data_ready_RNIG4BLN ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][19] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40173 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40174 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h02C2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_607 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40043 \CPLD_Con_1/g0_2_N_5L7_N_6L9_0_1 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40075 \CPLD_Con_1/PMU_OC_2_8_0_a2_RNIV5H461_1[8] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][18] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[14][17] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_608 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40033 \CPLD_Con_1/un1_i_freq_relay3_1lto8_i_o2 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40123 \CPLD_Con_1/un1_i_freq_relay3_2lto7_1 ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[9][10] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[9][0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_609 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40084 \CPLD_Con_1/un1_exec_flag_3_0_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40084 \CPLD_Con_1/un1_exec_flag_2_0_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7][19] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_610 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40104 \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[4] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40104 \CPLD_Con_1/un1_i_DC_Con1_iv_0_0[3] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][19] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_611 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40104 \CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40104 \CPLD_Con_1/un1_i_DC_Con1_1_iv_0_0[0] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][10] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_612 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, M0_dly, CLK_dly, CE_dly; + + lut40104 \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[3] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40175 \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[1] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[7]_fast[7] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40175 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_613 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40099 \CPLD_Con_1/RC_RLSel_13_0_a2[13] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40099 \CPLD_Con_1/RC_RLSel_13_0_a2[14] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][14] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[4][13] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_614 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40105 \CPLD_Con_1/g0_21_N_2L1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40033 \CPLD_Con_1/g0_2_1 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][9] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][8] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_615 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40043 \CPLD_Con_1/g0_12_N_2L1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40043 \CPLD_Con_1/g0_10_N_2L1 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[6][19] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_616 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40043 \CPLD_Con_1/DMM_en_22_0_a2_2_1[4] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40024 \CPLD_Con_1/DMM_en_22_0_a2_1_1[12] ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][10] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_617 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40123 \CPLD_Con_1/freq_t_RNI8PH26 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40068 \CPLD_Con_1/dc_t_RNI2Q6P8_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0004 \CPLD_Con_1/dc_slot_flag_fast[3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \CPLD_Con_1/dc_slot_flag_fast[2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_618 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40176 \CPLD_Reg_1/busy_flag_RNO_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40177 \CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[0][12] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[0][11] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40176 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40177 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC8C8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_619 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut4 \CPLD_Reg_1/regtable[7]_1_sqmuxa_0_a2_0 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40077 \CPLD_Reg_1/regtable[8]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[0][3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[0][2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_620 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut4 \CPLD_Con_1/un1_i_DC_Con1_1_iv_0_a5_1[0] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40020 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNINTVMC_3[26] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[3][19] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_621 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40043 \CPLD_Con_1/un1_DMM_en_102_1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40024 \CPLD_Con_1/DMM_en_22_2[16] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_622 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40104 \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[5] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40077 \CPLD_Con_1/PMU_OC_2_8_0_a4_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][23] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[15][22] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_623 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut4 \CPLD_Con_1/un1_i_DC_Con1_1_iv_RNO[3] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40080 \CPLD_Con_1/PMU_OC_4_8_0_a2[19] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_624 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40043 \CPLD_Con_1/RC_VISel_6.m9_0_a5_1_1 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40104 \CPLD_Con_1/un1_i_DC_Con1_iv_0_1[4] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][23] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][22] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_625 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40033 \CPLD_Con_1/err_flag13_0_o2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40104 \CPLD_Con_1/un1_i_DC_Con1_iv_0_0[2] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][18] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][17] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_626 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40123 \CPLD_Con_1/g0_15 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40043 \CPLD_Con_1/OC_x0138lto8_3 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][16] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[12][15] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_627 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut4 \CPLD_Con_1/un1_i_DC_Con1_1_iv_RNO[4] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut4 \CPLD_Con_1/un1_i_DC_Con1_iv_0_a5_2[3] ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[8][2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_628 ( input C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40116 \BUS_Con_1/miso_shift_rst[31] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40123 \CPLD_Con_1/dc_slot_flag_0_rep1_RNI421QK ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + vmuxregsre0004 \CPLD_Con_1/dc_slot_flag[3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \CPLD_Con_1/dc_slot_flag[2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_629 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40082 \CPLD_Reg_1/regtable[0]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40082 \CPLD_Reg_1/regtable[3]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[0][18] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[0][17] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_630 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40113 \CPLD_Reg_1/o_err ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40178 \CPLD_Reg_1/un11_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][14] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][13] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40178 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1113) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_631 ( input C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40045 \BUS_Con_1/err_flag_1_sqmuxa_0_a2_0_0 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40176 \BUS_Con_1/err_flag_1_sqmuxa_0_o4 ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][21] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[10][20] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_632 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut4 \CPLD_Con_1/un1_i_DC_Con1_1_iv_RNO[1] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40063 \CPLD_Con_1/DMM_en_22_0[15] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 \BUS_Con_1/tx_buffer[11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_633 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40020 \CPLD_Con_1/DMM_en_22_0_a2_2[12] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40012 \CPLD_Con_1/DMM_en_22_0_a2_2[15] ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][12] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[11][11] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_634 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut4 \CPLD_Con_1/un1_i_DC_Con1_1_iv_RNO[5] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40107 \CPLD_Con_1/PMU_OC_3_8_0_a4_1[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][16] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[2][15] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_672 ( input M1, M0, CE, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre0022 \CPLD_Reg_1/regtable[9]_fast[4] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[9]_fast[5] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_673 ( input M1, M0, CE, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre0022 \CPLD_Reg_1/regtable[9]_fast[6] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[9]_fast[7] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_830 ( input M1, M0, CE, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre0022 \CPLD_Reg_1/regtable[9][19] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[9][1] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_831 ( input M1, M0, CE, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre0022 \CPLD_Reg_1/regtable[9][2] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[9][3] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_832 ( input M1, M0, CE, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre0022 \CPLD_Reg_1/regtable[9][4] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[9][5] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_833 ( input M1, M0, CE, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre0022 \CPLD_Reg_1/regtable[9][6] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[9][7] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_834 ( input M1, M0, CE, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre0022 \CPLD_Reg_1/regtable[9][8] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[9][9] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_835 ( input M1, M0, CE, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre0022 \CPLD_Reg_1/regtable[9][17] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0022 \CPLD_Reg_1/regtable[9][18] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_864 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + vmuxregsre0004 \BUS_Con_1/addr_out_0_rep1 ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/addr_out_0_rep2 ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_865 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + vmuxregsre0004 \BUS_Con_1/addr_out_2_rep1 ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/addr_out_2_rep2 ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_866 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + vmuxregsre0004 \BUS_Con_1/addr_out_3_rep1 ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/addr_out_3_rep2 ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_867 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + vmuxregsre0004 \BUS_Con_1/addr_out_fast[0] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/addr_out_fast[2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_872 ( input M0, CE, LSR, CLK, output Q0 ); + wire VCCI, GNDI, M0_dly, CLK_dly, CE_dly, LSR_dly; + + vmuxregsre0004 \BUS_Con_1/data_out[9] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_873 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + vmuxregsre0004 \BUS_Con_1/data_out[10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 \BUS_Con_1/data_out[11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_miso ( input IOLDO, PADDT, output o_miso ); + + xo2iobuf o_miso_pad( .I(IOLDO), .T(PADDT), .PAD(o_miso)); + + specify + (IOLDO => o_miso) = (0:0:0,0:0:0); + (PADDT => o_miso) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf ( input I, T, output PAD ); + + OBZ INST5( .I(I), .T(T), .O(PAD)); +endmodule + +module o_miso_MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \BUS_Con_1_miso_shiftio[31] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module mfflsre ( input D0, SP, CK, LSR, output Q ); + + FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module o_wready ( input PADDO, output o_wready ); + + xo2iobuf0179 o_wready_pad( .I(PADDO), .PAD(o_wready)); + + specify + (PADDO => o_wready) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0179 ( input I, output PAD ); + + OB INST5( .I(I), .O(PAD)); +endmodule + +module i_sys_clk ( output PADDI, input i_sys_clk ); + + xo2iobuf0180 i_sys_clk_pad( .Z(PADDI), .PAD(i_sys_clk)); + + specify + (i_sys_clk => PADDI) = (0:0:0,0:0:0); + $width (posedge i_sys_clk, 0:0:0); + $width (negedge i_sys_clk, 0:0:0); + endspecify + +endmodule + +module xo2iobuf0180 ( output Z, input PAD ); + + IBPD INST1( .I(PAD), .O(Z)); +endmodule + +module o_PMU_OC_4_31_ ( input IOLDO, output oPMUOC431 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[31] ( .I(IOLDO), .PAD(oPMUOC431)); + + specify + (IOLDO => oPMUOC431) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_31__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[31] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module mfflsre0181 ( input D0, SP, CK, LSR, output Q ); + + FD1P3IX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module o_PMU_OC_4_30_ ( input IOLDO, output oPMUOC430 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[30] ( .I(IOLDO), .PAD(oPMUOC430)); + + specify + (IOLDO => oPMUOC430) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_30__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[30] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_29_ ( input IOLDO, output oPMUOC429 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[29] ( .I(IOLDO), .PAD(oPMUOC429)); + + specify + (IOLDO => oPMUOC429) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_29__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[29] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_28_ ( input IOLDO, output oPMUOC428 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[28] ( .I(IOLDO), .PAD(oPMUOC428)); + + specify + (IOLDO => oPMUOC428) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_28__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[28] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_27_ ( input IOLDO, output oPMUOC427 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[27] ( .I(IOLDO), .PAD(oPMUOC427)); + + specify + (IOLDO => oPMUOC427) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_27__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[27] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_26_ ( input IOLDO, output oPMUOC426 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[26] ( .I(IOLDO), .PAD(oPMUOC426)); + + specify + (IOLDO => oPMUOC426) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_26__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[26] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_25_ ( input IOLDO, output oPMUOC425 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[25] ( .I(IOLDO), .PAD(oPMUOC425)); + + specify + (IOLDO => oPMUOC425) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_25__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[25] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_24_ ( input IOLDO, output oPMUOC424 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[24] ( .I(IOLDO), .PAD(oPMUOC424)); + + specify + (IOLDO => oPMUOC424) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_24__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[24] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_23_ ( input IOLDO, output oPMUOC423 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[23] ( .I(IOLDO), .PAD(oPMUOC423)); + + specify + (IOLDO => oPMUOC423) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_23__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[23] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_22_ ( input IOLDO, output oPMUOC422 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[22] ( .I(IOLDO), .PAD(oPMUOC422)); + + specify + (IOLDO => oPMUOC422) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_22__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[22] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_21_ ( input IOLDO, output oPMUOC421 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[21] ( .I(IOLDO), .PAD(oPMUOC421)); + + specify + (IOLDO => oPMUOC421) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_21__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[21] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_20_ ( input PADDO, output oPMUOC420 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[20] ( .I(PADDO), .PAD(oPMUOC420)); + + specify + (PADDO => oPMUOC420) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_19_ ( input IOLDO, output oPMUOC419 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[19] ( .I(IOLDO), .PAD(oPMUOC419)); + + specify + (IOLDO => oPMUOC419) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_19__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[19] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_18_ ( input IOLDO, output oPMUOC418 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[18] ( .I(IOLDO), .PAD(oPMUOC418)); + + specify + (IOLDO => oPMUOC418) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_18__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[18] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_17_ ( input IOLDO, output oPMUOC417 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[17] ( .I(IOLDO), .PAD(oPMUOC417)); + + specify + (IOLDO => oPMUOC417) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_17__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[17] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_16_ ( input IOLDO, output oPMUOC416 ); + wire GNDI; + + xo2iobuf0182 \o_PMU_OC_4_pad[16] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC416)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC416) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0182 ( input I, T, output PAD ); + + OBZPD INST5( .I(I), .T(T), .O(PAD)); +endmodule + +module o_PMU_OC_4_16__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_OC_x17io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_15_ ( input IOLDO, output oPMUOC415 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[15] ( .I(IOLDO), .PAD(oPMUOC415)); + + specify + (IOLDO => oPMUOC415) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_15__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[15] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_14_ ( input IOLDO, output oPMUOC414 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[14] ( .I(IOLDO), .PAD(oPMUOC414)); + + specify + (IOLDO => oPMUOC414) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_14__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[14] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_13_ ( input IOLDO, output oPMUOC413 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[13] ( .I(IOLDO), .PAD(oPMUOC413)); + + specify + (IOLDO => oPMUOC413) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_13__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[13] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_12_ ( input IOLDO, output oPMUOC412 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[12] ( .I(IOLDO), .PAD(oPMUOC412)); + + specify + (IOLDO => oPMUOC412) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_12__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[12] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_11_ ( input IOLDO, output oPMUOC411 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[11] ( .I(IOLDO), .PAD(oPMUOC411)); + + specify + (IOLDO => oPMUOC411) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_11__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[11] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_10_ ( input IOLDO, output oPMUOC410 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[10] ( .I(IOLDO), .PAD(oPMUOC410)); + + specify + (IOLDO => oPMUOC410) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_10__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[10] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_9_ ( input IOLDO, output oPMUOC49 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[9] ( .I(IOLDO), .PAD(oPMUOC49)); + + specify + (IOLDO => oPMUOC49) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_9__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[9] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_8_ ( input IOLDO, output oPMUOC48 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[8] ( .I(IOLDO), .PAD(oPMUOC48)); + + specify + (IOLDO => oPMUOC48) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_8__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[8] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_7_ ( input IOLDO, output oPMUOC47 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[7] ( .I(IOLDO), .PAD(oPMUOC47)); + + specify + (IOLDO => oPMUOC47) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_7__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[7] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_6_ ( input IOLDO, output oPMUOC46 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[6] ( .I(IOLDO), .PAD(oPMUOC46)); + + specify + (IOLDO => oPMUOC46) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_6__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[6] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_5_ ( input PADDO, output oPMUOC45 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[5] ( .I(PADDO), .PAD(oPMUOC45)); + + specify + (PADDO => oPMUOC45) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_4_ ( input PADDO, output oPMUOC44 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[4] ( .I(PADDO), .PAD(oPMUOC44)); + + specify + (PADDO => oPMUOC44) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_3_ ( input IOLDO, output oPMUOC43 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[3] ( .I(IOLDO), .PAD(oPMUOC43)); + + specify + (IOLDO => oPMUOC43) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_3__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[3] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_2_ ( input IOLDO, output oPMUOC42 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[2] ( .I(IOLDO), .PAD(oPMUOC42)); + + specify + (IOLDO => oPMUOC42) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_2__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_4io[2] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_1_ ( input PADDO, output oPMUOC41 ); + + xo2iobuf0179 \o_PMU_OC_4_pad[1] ( .I(PADDO), .PAD(oPMUOC41)); + + specify + (PADDO => oPMUOC41) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_0_ ( input IOLDO, output oPMUOC40 ); + wire GNDI; + + xo2iobuf0182 \o_PMU_OC_4_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC40)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC40) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_OC_x01io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_31_ ( input IOLDO, output oPMUOC331 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[31] ( .I(IOLDO), .PAD(oPMUOC331)); + + specify + (IOLDO => oPMUOC331) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_31__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[31] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_30_ ( input IOLDO, output oPMUOC330 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[30] ( .I(IOLDO), .PAD(oPMUOC330)); + + specify + (IOLDO => oPMUOC330) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_30__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[30] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_29_ ( input IOLDO, output oPMUOC329 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[29] ( .I(IOLDO), .PAD(oPMUOC329)); + + specify + (IOLDO => oPMUOC329) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_29__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[29] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_28_ ( input IOLDO, output oPMUOC328 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[28] ( .I(IOLDO), .PAD(oPMUOC328)); + + specify + (IOLDO => oPMUOC328) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_28__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[28] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_27_ ( input IOLDO, output oPMUOC327 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[27] ( .I(IOLDO), .PAD(oPMUOC327)); + + specify + (IOLDO => oPMUOC327) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_27__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[27] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_26_ ( input IOLDO, output oPMUOC326 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[26] ( .I(IOLDO), .PAD(oPMUOC326)); + + specify + (IOLDO => oPMUOC326) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_26__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[26] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_25_ ( input IOLDO, output oPMUOC325 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[25] ( .I(IOLDO), .PAD(oPMUOC325)); + + specify + (IOLDO => oPMUOC325) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_25__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[25] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_24_ ( input IOLDO, output oPMUOC324 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[24] ( .I(IOLDO), .PAD(oPMUOC324)); + + specify + (IOLDO => oPMUOC324) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_24__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[24] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_23_ ( input IOLDO, output oPMUOC323 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[23] ( .I(IOLDO), .PAD(oPMUOC323)); + + specify + (IOLDO => oPMUOC323) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_23__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[23] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_22_ ( input IOLDO, output oPMUOC322 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[22] ( .I(IOLDO), .PAD(oPMUOC322)); + + specify + (IOLDO => oPMUOC322) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_22__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[22] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_21_ ( input IOLDO, output oPMUOC321 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[21] ( .I(IOLDO), .PAD(oPMUOC321)); + + specify + (IOLDO => oPMUOC321) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_21__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[21] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_20_ ( input IOLDO, output oPMUOC320 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[20] ( .I(IOLDO), .PAD(oPMUOC320)); + + specify + (IOLDO => oPMUOC320) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_20__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[20] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_19_ ( input IOLDO, output oPMUOC319 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[19] ( .I(IOLDO), .PAD(oPMUOC319)); + + specify + (IOLDO => oPMUOC319) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_19__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[19] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_18_ ( input IOLDO, output oPMUOC318 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[18] ( .I(IOLDO), .PAD(oPMUOC318)); + + specify + (IOLDO => oPMUOC318) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_18__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[18] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_17_ ( input IOLDO, output oPMUOC317 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[17] ( .I(IOLDO), .PAD(oPMUOC317)); + + specify + (IOLDO => oPMUOC317) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_17__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[17] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_16_ ( input IOLDO, output oPMUOC316 ); + wire GNDI; + + xo2iobuf0182 \o_PMU_OC_3_pad[16] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC316)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC316) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_16__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_OC_x17io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_15_ ( input IOLDO, output oPMUOC315 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[15] ( .I(IOLDO), .PAD(oPMUOC315)); + + specify + (IOLDO => oPMUOC315) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_15__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[15] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_14_ ( input IOLDO, output oPMUOC314 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[14] ( .I(IOLDO), .PAD(oPMUOC314)); + + specify + (IOLDO => oPMUOC314) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_14__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[14] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_13_ ( input IOLDO, output oPMUOC313 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[13] ( .I(IOLDO), .PAD(oPMUOC313)); + + specify + (IOLDO => oPMUOC313) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_13__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[13] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_12_ ( input IOLDO, output oPMUOC312 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[12] ( .I(IOLDO), .PAD(oPMUOC312)); + + specify + (IOLDO => oPMUOC312) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_12__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[12] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_11_ ( input IOLDO, output oPMUOC311 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[11] ( .I(IOLDO), .PAD(oPMUOC311)); + + specify + (IOLDO => oPMUOC311) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_11__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[11] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_10_ ( input IOLDO, output oPMUOC310 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[10] ( .I(IOLDO), .PAD(oPMUOC310)); + + specify + (IOLDO => oPMUOC310) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_10__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[10] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_9_ ( input IOLDO, output oPMUOC39 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[9] ( .I(IOLDO), .PAD(oPMUOC39)); + + specify + (IOLDO => oPMUOC39) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_9__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[9] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_8_ ( input IOLDO, output oPMUOC38 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[8] ( .I(IOLDO), .PAD(oPMUOC38)); + + specify + (IOLDO => oPMUOC38) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_8__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[8] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_7_ ( input PADDO, output oPMUOC37 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[7] ( .I(PADDO), .PAD(oPMUOC37)); + + specify + (PADDO => oPMUOC37) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_6_ ( input IOLDO, output oPMUOC36 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[6] ( .I(IOLDO), .PAD(oPMUOC36)); + + specify + (IOLDO => oPMUOC36) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_6__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[6] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_5_ ( input PADDO, output oPMUOC35 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[5] ( .I(PADDO), .PAD(oPMUOC35)); + + specify + (PADDO => oPMUOC35) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_4_ ( input IOLDO, output oPMUOC34 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[4] ( .I(IOLDO), .PAD(oPMUOC34)); + + specify + (IOLDO => oPMUOC34) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_4__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[4] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_3_ ( input PADDO, output oPMUOC33 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[3] ( .I(PADDO), .PAD(oPMUOC33)); + + specify + (PADDO => oPMUOC33) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_2_ ( input IOLDO, output oPMUOC32 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[2] ( .I(IOLDO), .PAD(oPMUOC32)); + + specify + (IOLDO => oPMUOC32) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_2__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_3io[2] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_1_ ( input PADDO, output oPMUOC31 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[1] ( .I(PADDO), .PAD(oPMUOC31)); + + specify + (PADDO => oPMUOC31) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_0_ ( input IOLDO, output oPMUOC30 ); + + xo2iobuf0179 \o_PMU_OC_3_pad[0] ( .I(IOLDO), .PAD(oPMUOC30)); + + specify + (IOLDO => oPMUOC30) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_OC_x01io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_31_ ( input IOLDO, output oPMUOC231 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[31] ( .I(IOLDO), .PAD(oPMUOC231)); + + specify + (IOLDO => oPMUOC231) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_31__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[31] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_30_ ( input IOLDO, output oPMUOC230 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[30] ( .I(IOLDO), .PAD(oPMUOC230)); + + specify + (IOLDO => oPMUOC230) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_30__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[30] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_29_ ( input IOLDO, output oPMUOC229 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[29] ( .I(IOLDO), .PAD(oPMUOC229)); + + specify + (IOLDO => oPMUOC229) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_29__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[29] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_28_ ( input IOLDO, output oPMUOC228 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[28] ( .I(IOLDO), .PAD(oPMUOC228)); + + specify + (IOLDO => oPMUOC228) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_28__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[28] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_27_ ( input IOLDO, output oPMUOC227 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[27] ( .I(IOLDO), .PAD(oPMUOC227)); + + specify + (IOLDO => oPMUOC227) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_27__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[27] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_26_ ( input IOLDO, output oPMUOC226 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[26] ( .I(IOLDO), .PAD(oPMUOC226)); + + specify + (IOLDO => oPMUOC226) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_26__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[26] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_25_ ( input IOLDO, output oPMUOC225 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[25] ( .I(IOLDO), .PAD(oPMUOC225)); + + specify + (IOLDO => oPMUOC225) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_25__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[25] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_24_ ( input IOLDO, output oPMUOC224 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[24] ( .I(IOLDO), .PAD(oPMUOC224)); + + specify + (IOLDO => oPMUOC224) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_24__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[24] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_23_ ( input IOLDO, output oPMUOC223 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[23] ( .I(IOLDO), .PAD(oPMUOC223)); + + specify + (IOLDO => oPMUOC223) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_23__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[23] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_22_ ( input IOLDO, output oPMUOC222 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[22] ( .I(IOLDO), .PAD(oPMUOC222)); + + specify + (IOLDO => oPMUOC222) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_22__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[22] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_21_ ( input IOLDO, output oPMUOC221 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[21] ( .I(IOLDO), .PAD(oPMUOC221)); + + specify + (IOLDO => oPMUOC221) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_21__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[21] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_20_ ( input IOLDO, output oPMUOC220 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[20] ( .I(IOLDO), .PAD(oPMUOC220)); + + specify + (IOLDO => oPMUOC220) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_20__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[20] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_19_ ( input IOLDO, output oPMUOC219 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[19] ( .I(IOLDO), .PAD(oPMUOC219)); + + specify + (IOLDO => oPMUOC219) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_19__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[19] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_18_ ( input IOLDO, output oPMUOC218 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[18] ( .I(IOLDO), .PAD(oPMUOC218)); + + specify + (IOLDO => oPMUOC218) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_18__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[18] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_17_ ( input IOLDO, output oPMUOC217 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[17] ( .I(IOLDO), .PAD(oPMUOC217)); + + specify + (IOLDO => oPMUOC217) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_17__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[17] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_16_ ( input IOLDO, output oPMUOC216 ); + wire GNDI; + + xo2iobuf0182 \o_PMU_OC_2_pad[16] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC216)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC216) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_16__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_OC_x17io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_15_ ( input IOLDO, output oPMUOC215 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[15] ( .I(IOLDO), .PAD(oPMUOC215)); + + specify + (IOLDO => oPMUOC215) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_15__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[15] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_14_ ( input IOLDO, output oPMUOC214 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[14] ( .I(IOLDO), .PAD(oPMUOC214)); + + specify + (IOLDO => oPMUOC214) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_14__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[14] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_13_ ( input IOLDO, output oPMUOC213 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[13] ( .I(IOLDO), .PAD(oPMUOC213)); + + specify + (IOLDO => oPMUOC213) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_13__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[13] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_12_ ( input IOLDO, output oPMUOC212 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[12] ( .I(IOLDO), .PAD(oPMUOC212)); + + specify + (IOLDO => oPMUOC212) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_12__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[12] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_11_ ( input IOLDO, output oPMUOC211 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[11] ( .I(IOLDO), .PAD(oPMUOC211)); + + specify + (IOLDO => oPMUOC211) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_11__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[11] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_10_ ( input IOLDO, output oPMUOC210 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[10] ( .I(IOLDO), .PAD(oPMUOC210)); + + specify + (IOLDO => oPMUOC210) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_10__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[10] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_9_ ( input IOLDO, output oPMUOC29 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[9] ( .I(IOLDO), .PAD(oPMUOC29)); + + specify + (IOLDO => oPMUOC29) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_9__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[9] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_8_ ( input IOLDO, output oPMUOC28 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[8] ( .I(IOLDO), .PAD(oPMUOC28)); + + specify + (IOLDO => oPMUOC28) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_8__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[8] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_7_ ( input PADDO, output oPMUOC27 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[7] ( .I(PADDO), .PAD(oPMUOC27)); + + specify + (PADDO => oPMUOC27) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_6_ ( input IOLDO, output oPMUOC26 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[6] ( .I(IOLDO), .PAD(oPMUOC26)); + + specify + (IOLDO => oPMUOC26) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_6__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[6] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_5_ ( input PADDO, output oPMUOC25 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[5] ( .I(PADDO), .PAD(oPMUOC25)); + + specify + (PADDO => oPMUOC25) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_4_ ( input IOLDO, output oPMUOC24 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[4] ( .I(IOLDO), .PAD(oPMUOC24)); + + specify + (IOLDO => oPMUOC24) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_4__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[4] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_3_ ( input PADDO, output oPMUOC23 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[3] ( .I(PADDO), .PAD(oPMUOC23)); + + specify + (PADDO => oPMUOC23) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_2_ ( input IOLDO, output oPMUOC22 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[2] ( .I(IOLDO), .PAD(oPMUOC22)); + + specify + (IOLDO => oPMUOC22) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_2__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_2io[2] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_1_ ( input PADDO, output oPMUOC21 ); + + xo2iobuf0179 \o_PMU_OC_2_pad[1] ( .I(PADDO), .PAD(oPMUOC21)); + + specify + (PADDO => oPMUOC21) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_0_ ( input IOLDO, output oPMUOC20 ); + wire GNDI; + + xo2iobuf0182 \o_PMU_OC_2_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC20)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC20) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_OC_x01io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_31_ ( input IOLDO, output oPMUOC131 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[31] ( .I(IOLDO), .PAD(oPMUOC131)); + + specify + (IOLDO => oPMUOC131) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_31__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[31] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_30_ ( input IOLDO, output oPMUOC130 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[30] ( .I(IOLDO), .PAD(oPMUOC130)); + + specify + (IOLDO => oPMUOC130) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_30__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[30] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_29_ ( input IOLDO, output oPMUOC129 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[29] ( .I(IOLDO), .PAD(oPMUOC129)); + + specify + (IOLDO => oPMUOC129) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_29__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[29] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_28_ ( input IOLDO, output oPMUOC128 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[28] ( .I(IOLDO), .PAD(oPMUOC128)); + + specify + (IOLDO => oPMUOC128) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_28__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[28] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_27_ ( input IOLDO, output oPMUOC127 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[27] ( .I(IOLDO), .PAD(oPMUOC127)); + + specify + (IOLDO => oPMUOC127) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_27__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[27] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_26_ ( input IOLDO, output oPMUOC126 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[26] ( .I(IOLDO), .PAD(oPMUOC126)); + + specify + (IOLDO => oPMUOC126) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_26__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[26] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_25_ ( input IOLDO, output oPMUOC125 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[25] ( .I(IOLDO), .PAD(oPMUOC125)); + + specify + (IOLDO => oPMUOC125) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_25__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[25] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_24_ ( input IOLDO, output oPMUOC124 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[24] ( .I(IOLDO), .PAD(oPMUOC124)); + + specify + (IOLDO => oPMUOC124) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_24__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[24] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_23_ ( input IOLDO, output oPMUOC123 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[23] ( .I(IOLDO), .PAD(oPMUOC123)); + + specify + (IOLDO => oPMUOC123) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_23__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[23] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_22_ ( input IOLDO, output oPMUOC122 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[22] ( .I(IOLDO), .PAD(oPMUOC122)); + + specify + (IOLDO => oPMUOC122) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_22__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[22] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_21_ ( input IOLDO, output oPMUOC121 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[21] ( .I(IOLDO), .PAD(oPMUOC121)); + + specify + (IOLDO => oPMUOC121) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_21__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[21] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_20_ ( input IOLDO, output oPMUOC120 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[20] ( .I(IOLDO), .PAD(oPMUOC120)); + + specify + (IOLDO => oPMUOC120) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_20__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[20] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_19_ ( input IOLDO, output oPMUOC119 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[19] ( .I(IOLDO), .PAD(oPMUOC119)); + + specify + (IOLDO => oPMUOC119) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_19__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[19] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_18_ ( input IOLDO, output oPMUOC118 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[18] ( .I(IOLDO), .PAD(oPMUOC118)); + + specify + (IOLDO => oPMUOC118) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_18__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[18] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_17_ ( input IOLDO, output oPMUOC117 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[17] ( .I(IOLDO), .PAD(oPMUOC117)); + + specify + (IOLDO => oPMUOC117) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_17__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[17] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_16_ ( input IOLDO, output oPMUOC116 ); + wire GNDI; + + xo2iobuf0182 \o_PMU_OC_1_pad[16] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC116)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC116) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_16__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_OC_x17io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_15_ ( input IOLDO, output oPMUOC115 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[15] ( .I(IOLDO), .PAD(oPMUOC115)); + + specify + (IOLDO => oPMUOC115) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_15__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[15] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_14_ ( input IOLDO, output oPMUOC114 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[14] ( .I(IOLDO), .PAD(oPMUOC114)); + + specify + (IOLDO => oPMUOC114) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_14__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[14] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_13_ ( input IOLDO, output oPMUOC113 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[13] ( .I(IOLDO), .PAD(oPMUOC113)); + + specify + (IOLDO => oPMUOC113) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_13__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[13] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_12_ ( input IOLDO, output oPMUOC112 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[12] ( .I(IOLDO), .PAD(oPMUOC112)); + + specify + (IOLDO => oPMUOC112) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_12__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[12] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_11_ ( input IOLDO, output oPMUOC111 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[11] ( .I(IOLDO), .PAD(oPMUOC111)); + + specify + (IOLDO => oPMUOC111) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_11__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[11] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_10_ ( input IOLDO, output oPMUOC110 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[10] ( .I(IOLDO), .PAD(oPMUOC110)); + + specify + (IOLDO => oPMUOC110) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_10__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[10] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_9_ ( input IOLDO, output oPMUOC19 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[9] ( .I(IOLDO), .PAD(oPMUOC19)); + + specify + (IOLDO => oPMUOC19) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_9__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[9] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_8_ ( input IOLDO, output oPMUOC18 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[8] ( .I(IOLDO), .PAD(oPMUOC18)); + + specify + (IOLDO => oPMUOC18) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_8__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[8] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_7_ ( input IOLDO, output oPMUOC17 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[7] ( .I(IOLDO), .PAD(oPMUOC17)); + + specify + (IOLDO => oPMUOC17) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_7__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[7] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_6_ ( input IOLDO, output oPMUOC16 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[6] ( .I(IOLDO), .PAD(oPMUOC16)); + + specify + (IOLDO => oPMUOC16) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_6__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[6] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_5_ ( input IOLDO, output oPMUOC15 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[5] ( .I(IOLDO), .PAD(oPMUOC15)); + + specify + (IOLDO => oPMUOC15) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_5__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[5] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_4_ ( input IOLDO, output oPMUOC14 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[4] ( .I(IOLDO), .PAD(oPMUOC14)); + + specify + (IOLDO => oPMUOC14) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_4__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[4] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_3_ ( input IOLDO, output oPMUOC13 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[3] ( .I(IOLDO), .PAD(oPMUOC13)); + + specify + (IOLDO => oPMUOC13) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_3__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[3] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_2_ ( input IOLDO, output oPMUOC12 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[2] ( .I(IOLDO), .PAD(oPMUOC12)); + + specify + (IOLDO => oPMUOC12) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_2__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[2] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_1_ ( input IOLDO, output oPMUOC11 ); + + xo2iobuf0179 \o_PMU_OC_1_pad[1] ( .I(IOLDO), .PAD(oPMUOC11)); + + specify + (IOLDO => oPMUOC11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_1__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_PMU_OC_1io[1] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_0_ ( input IOLDO, output oPMUOC10 ); + wire GNDI; + + xo2iobuf0182 \o_PMU_OC_1_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC10)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_OC_x01io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_LOS_1_ ( input PADDO, output oRCLOS1 ); + wire GNDI; + + xo2iobuf0182 \o_RC_LOS_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oRCLOS1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oRCLOS1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_LOS_0_ ( input PADDO, output oRCLOS0 ); + wire GNDI; + + xo2iobuf0182 \o_RC_LOS_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oRCLOS0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oRCLOS0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_LOF_1_ ( input PADDO, output oRCLOF1 ); + wire GNDI; + + xo2iobuf0182 \o_RC_LOF_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oRCLOF1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oRCLOF1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_LOF_0_ ( input PADDO, output oRCLOF0 ); + wire GNDI; + + xo2iobuf0182 \o_RC_LOF_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oRCLOF0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oRCLOF0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_ISel ( input PADDO, output o_RC_ISel ); + wire GNDI; + + xo2iobuf0182 o_RC_ISel_pad( .I(PADDO), .T(GNDI), .PAD(o_RC_ISel)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => o_RC_ISel) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_VSel ( input PADDO, output o_RC_VSel ); + wire GNDI; + + xo2iobuf0182 o_RC_VSel_pad( .I(PADDO), .T(GNDI), .PAD(o_RC_VSel)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => o_RC_VSel) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_17_ ( input IOLDO, output oRCRLSel17 ); + wire GNDI; + + xo2iobuf0182 \o_RC_RLSel_pad[17] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel17)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oRCRLSel17) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_17__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_RC_RLSelio[17] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_16_ ( input IOLDO, output oRCRLSel16 ); + wire GNDI; + + xo2iobuf0182 \o_RC_RLSel_pad[16] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel16)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oRCRLSel16) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_16__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_RC_RLSelio[16] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_15_ ( input IOLDO, output oRCRLSel15 ); + wire GNDI; + + xo2iobuf0182 \o_RC_RLSel_pad[15] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel15)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oRCRLSel15) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_15__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_RC_RLSelio[15] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_14_ ( input IOLDO, output oRCRLSel14 ); + wire GNDI; + + xo2iobuf0182 \o_RC_RLSel_pad[14] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel14)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oRCRLSel14) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_14__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_RC_RLSelio[14] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_13_ ( input IOLDO, output oRCRLSel13 ); + wire GNDI; + + xo2iobuf0182 \o_RC_RLSel_pad[13] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel13)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oRCRLSel13) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_13__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_RC_RLSelio[13] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_12_ ( input IOLDO, output oRCRLSel12 ); + wire GNDI; + + xo2iobuf0182 \o_RC_RLSel_pad[12] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel12)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oRCRLSel12) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_12__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_RC_RLSelio[12] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_11_ ( input IOLDO, output oRCRLSel11 ); + wire GNDI; + + xo2iobuf0182 \o_RC_RLSel_pad[11] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel11)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oRCRLSel11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_11__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_RC_RLSelio[11] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_10_ ( input IOLDO, output oRCRLSel10 ); + wire GNDI; + + xo2iobuf0182 \o_RC_RLSel_pad[10] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel10)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oRCRLSel10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_10__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_RC_RLSelio[10] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_9_ ( input IOLDO, output oRCRLSel9 ); + wire GNDI; + + xo2iobuf0182 \o_RC_RLSel_pad[9] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel9)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oRCRLSel9) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_9__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_RC_RLSelio[9] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_8_ ( input IOLDO, output oRCRLSel8 ); + wire GNDI; + + xo2iobuf0182 \o_RC_RLSel_pad[8] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel8)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oRCRLSel8) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_8__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_RC_RLSelio[8] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_7_ ( input IOLDO, output oRCRLSel7 ); + wire GNDI; + + xo2iobuf0182 \o_RC_RLSel_pad[7] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel7)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oRCRLSel7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_7__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_RC_RLSelio[7] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_6_ ( input IOLDO, output oRCRLSel6 ); + wire GNDI; + + xo2iobuf0182 \o_RC_RLSel_pad[6] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel6)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oRCRLSel6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_6__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_RC_RLSelio[6] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_5_ ( input IOLDO, output oRCRLSel5 ); + wire GNDI; + + xo2iobuf0182 \o_RC_RLSel_pad[5] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel5)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oRCRLSel5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_5__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_RC_RLSelio[5] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_4_ ( input IOLDO, output oRCRLSel4 ); + wire GNDI; + + xo2iobuf0182 \o_RC_RLSel_pad[4] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel4)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oRCRLSel4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_4__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_RC_RLSelio[4] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_3_ ( input IOLDO, output oRCRLSel3 ); + wire GNDI; + + xo2iobuf0182 \o_RC_RLSel_pad[3] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel3)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oRCRLSel3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_3__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_RC_RLSelio[3] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_2_ ( input IOLDO, output oRCRLSel2 ); + wire GNDI; + + xo2iobuf0182 \o_RC_RLSel_pad[2] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel2)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oRCRLSel2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_2__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_RC_RLSelio[2] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_1_ ( input IOLDO, output oRCRLSel1 ); + wire GNDI; + + xo2iobuf0182 \o_RC_RLSel_pad[1] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oRCRLSel1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_1__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_RC_RLSelio[1] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_0_ ( input IOLDO, output oRCRLSel0 ); + wire GNDI; + + xo2iobuf0182 \o_RC_RLSel_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oRCRLSel0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_RLSel_0__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0181 \CPLD_Con_1_RC_RLSelio[0] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_T32 ( input IOLDO, output o_RC_T32 ); + wire GNDI; + + xo2iobuf0182 o_RC_T32_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T32)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => o_RC_T32) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_T32_MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_RC_Txio[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_T31 ( input IOLDO, output o_RC_T31 ); + wire GNDI; + + xo2iobuf0182 o_RC_T31_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T31)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => o_RC_T31) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_T31_MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_RC_Txio[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_T30 ( input IOLDO, output o_RC_T30 ); + wire GNDI; + + xo2iobuf0182 o_RC_T30_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T30)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => o_RC_T30) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_T30_MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_RC_Txio[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_T29 ( input IOLDO, output o_RC_T29 ); + wire GNDI; + + xo2iobuf0182 o_RC_T29_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T29)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => o_RC_T29) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_T29_MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_RC_Txio[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_T28 ( input IOLDO, output o_RC_T28 ); + wire GNDI; + + xo2iobuf0182 o_RC_T28_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T28)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => o_RC_T28) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_T28_MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_RC_Txio[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_T27 ( input IOLDO, output o_RC_T27 ); + wire GNDI; + + xo2iobuf0182 o_RC_T27_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T27)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => o_RC_T27) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_T27_MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_RC_Txio[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_IO_RC1 ( input IOLDO, output o_IO_RC1 ); + wire GNDI; + + xo2iobuf0182 o_IO_RC1_pad( .I(IOLDO), .T(GNDI), .PAD(o_IO_RC1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => o_IO_RC1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_IO_RC1_MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre CPLD_Con_1_io_RCio( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_DMM_EN_18_ ( input IOLDO, output oDMMEN18 ); + wire GNDI; + + xo2iobuf0182 \o_DMM_EN_pad[18] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN18)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oDMMEN18) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DMM_EN_18__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_DMM_enio[18] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_DMM_EN_17_ ( input IOLDO, output oDMMEN17 ); + wire GNDI; + + xo2iobuf0182 \o_DMM_EN_pad[17] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN17)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oDMMEN17) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DMM_EN_17__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_DMM_enio[17] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_DMM_EN_16_ ( input IOLDO, output oDMMEN16 ); + wire GNDI; + + xo2iobuf0182 \o_DMM_EN_pad[16] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN16)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oDMMEN16) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DMM_EN_16__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_DMM_enio[16] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_DMM_EN_15_ ( input IOLDO, output oDMMEN15 ); + wire GNDI; + + xo2iobuf0182 \o_DMM_EN_pad[15] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN15)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oDMMEN15) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DMM_EN_15__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_DMM_enio[15] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_DMM_EN_14_ ( input IOLDO, output oDMMEN14 ); + wire GNDI; + + xo2iobuf0182 \o_DMM_EN_pad[14] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN14)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oDMMEN14) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DMM_EN_14__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_DMM_enio[14] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_DMM_EN_13_ ( input IOLDO, output oDMMEN13 ); + wire GNDI; + + xo2iobuf0182 \o_DMM_EN_pad[13] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN13)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oDMMEN13) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DMM_EN_13__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_DMM_enio[13] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_DMM_EN_12_ ( input IOLDO, output oDMMEN12 ); + wire GNDI; + + xo2iobuf0182 \o_DMM_EN_pad[12] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN12)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oDMMEN12) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DMM_EN_12__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_DMM_enio[12] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_DMM_EN_11_ ( input IOLDO, output oDMMEN11 ); + wire GNDI; + + xo2iobuf0182 \o_DMM_EN_pad[11] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN11)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oDMMEN11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DMM_EN_11__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_DMM_enio[11] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_DMM_EN_10_ ( input IOLDO, output oDMMEN10 ); + wire GNDI; + + xo2iobuf0182 \o_DMM_EN_pad[10] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN10)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oDMMEN10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DMM_EN_10__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_DMM_enio[10] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_DMM_EN_9_ ( input IOLDO, output oDMMEN9 ); + wire GNDI; + + xo2iobuf0182 \o_DMM_EN_pad[9] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN9)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oDMMEN9) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DMM_EN_9__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_DMM_enio[9] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_DMM_EN_8_ ( input IOLDO, output oDMMEN8 ); + wire GNDI; + + xo2iobuf0182 \o_DMM_EN_pad[8] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN8)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oDMMEN8) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DMM_EN_8__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_DMM_enio[8] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_DMM_EN_7_ ( input IOLDO, output oDMMEN7 ); + wire GNDI; + + xo2iobuf0182 \o_DMM_EN_pad[7] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN7)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oDMMEN7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DMM_EN_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_DMM_enio[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_DMM_EN_6_ ( input IOLDO, output oDMMEN6 ); + wire GNDI; + + xo2iobuf0182 \o_DMM_EN_pad[6] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN6)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oDMMEN6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DMM_EN_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_DMM_enio[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_DMM_EN_5_ ( input IOLDO, output oDMMEN5 ); + wire GNDI; + + xo2iobuf0182 \o_DMM_EN_pad[5] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN5)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oDMMEN5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DMM_EN_5__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_DMM_enio[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_DMM_EN_4_ ( input IOLDO, output oDMMEN4 ); + wire GNDI; + + xo2iobuf0182 \o_DMM_EN_pad[4] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN4)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oDMMEN4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DMM_EN_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_DMM_enio[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_DMM_EN_3_ ( input IOLDO, output oDMMEN3 ); + wire GNDI; + + xo2iobuf0182 \o_DMM_EN_pad[3] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN3)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oDMMEN3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DMM_EN_3__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_DMM_enio[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_DMM_EN_2_ ( input IOLDO, output oDMMEN2 ); + wire GNDI; + + xo2iobuf0182 \o_DMM_EN_pad[2] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN2)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oDMMEN2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DMM_EN_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_DMM_enio[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_DMM_EN_1_ ( input IOLDO, output oDMMEN1 ); + wire GNDI; + + xo2iobuf0182 \o_DMM_EN_pad[1] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oDMMEN1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DMM_EN_1__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_DMM_enio[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_DMM_EN_0_ ( input IOLDO, output oDMMEN0 ); + wire GNDI; + + xo2iobuf0182 \o_DMM_EN_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oDMMEN0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DMM_EN_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_DMM_enio[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_con_done ( input PADDO, output o_con_done ); + wire GNDI; + + xo2iobuf0182 o_con_done_pad( .I(PADDO), .T(GNDI), .PAD(o_con_done)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => o_con_done) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_err ( input PADDO, output o_err ); + wire GNDI; + + xo2iobuf0182 o_err_pad( .I(PADDO), .T(GNDI), .PAD(o_err)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => o_err) = (0:0:0,0:0:0); + endspecify + +endmodule + +module i_cs ( output PADDI, input i_cs ); + + xo2iobuf0180 i_cs_pad( .Z(PADDI), .PAD(i_cs)); + + specify + (i_cs => PADDI) = (0:0:0,0:0:0); + $width (posedge i_cs, 0:0:0); + $width (negedge i_cs, 0:0:0); + endspecify + +endmodule + +module i_cs_MGIOL ( input DI, LSR, CLK, output IN ); + wire VCCI, LSR_NOTIN, DI_dly, CLK_dly, LSR_dly; + + smuxlregsre \BUS_Con_1_cs_syncio[0] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module smuxlregsre ( input D0, SP, CK, LSR, output Q ); + + IFS1P3JX INST01( .D(D0), .SP(SP), .SCLK(CK), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module i_mosi ( output PADDI, input i_mosi ); + + xo2iobuf0180 i_mosi_pad( .Z(PADDI), .PAD(i_mosi)); + + specify + (i_mosi => PADDI) = (0:0:0,0:0:0); + $width (posedge i_mosi, 0:0:0); + $width (negedge i_mosi, 0:0:0); + endspecify + +endmodule + +module i_mosi_MGIOL ( input DI, LSR, CLK, output IN ); + wire VCCI, LSR_NOTIN, DI_dly, CLK_dly, LSR_dly; + + smuxlregsre0183 \BUS_Con_1_mosi_syncio[0] ( .D0(DI_dly), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module smuxlregsre0183 ( input D0, SP, CK, LSR, output Q ); + + IFS1P3IX INST01( .D(D0), .SP(SP), .SCLK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module i_sclk ( output PADDI, input i_sclk ); + + xo2iobuf0180 i_sclk_pad( .Z(PADDI), .PAD(i_sclk)); + + specify + (i_sclk => PADDI) = (0:0:0,0:0:0); + $width (posedge i_sclk, 0:0:0); + $width (negedge i_sclk, 0:0:0); + endspecify + +endmodule + +module i_sclk_MGIOL ( input DI, LSR, CLK, output IN ); + wire VCCI, LSR_NOTIN, DI_dly, CLK_dly, LSR_dly; + + smuxlregsre0183 \BUS_Con_1_sclk_syncio[0] ( .D0(DI_dly), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module i_rst_n ( output PADDI, input i_rst_n ); + + xo2iobuf0180 i_rst_n_pad( .Z(PADDI), .PAD(i_rst_n)); + + specify + (i_rst_n => PADDI) = (0:0:0,0:0:0); + $width (posedge i_rst_n, 0:0:0); + $width (negedge i_rst_n, 0:0:0); + endspecify + +endmodule + +module i_rst_n_MGIOL ( input DI, CE, LSR, CLK, output IN ); + wire DI_dly, CLK_dly, CE_dly, LSR_dly; + + smuxlregsre0183 CPLD_Con_1_exec_flagio( .D0(DI_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IN)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module GSR_INST ( input GSRNET ); + + GSR5MODE GSR_INST_GSRMODE( .GSR(GSRNET)); + + specify + endspecify + +endmodule + +module GSR5MODE ( input GSR ); + wire GSRMODE; + + BUFBA INST10( .A(GSR), .Z(GSRMODE)); + GSR INST20( .GSR(GSRMODE)); +endmodule diff --git a/CPLD1/impl1/NewExtIns_CPLD1_impl1_synplify.lpf b/CPLD1/impl1/NewExtIns_CPLD1_impl1_synplify.lpf new file mode 100644 index 0000000..300d6f2 --- /dev/null +++ b/CPLD1/impl1/NewExtIns_CPLD1_impl1_synplify.lpf @@ -0,0 +1,21 @@ +# +# Logical Preferences generated for Lattice by Synplify map202309lat, Build 191R. +# + +# Period Constraints +#FREQUENCY PORT "i_sys_clk" 200.0 MHz; + + +# Output Constraints + +# Input Constraints + +# Point-to-point Delay Constraints + + + +# Block Path Constraints + +BLOCK ASYNCPATHS; + +# End of generated Logical Preferences. diff --git a/CPLD1/impl1/NewExtIns_CPLD1_impl1_synplify_tmp2.lpf b/CPLD1/impl1/NewExtIns_CPLD1_impl1_synplify_tmp2.lpf new file mode 100644 index 0000000..e69de29 diff --git a/CPLD1/impl1/NewExtIns_CPLD1_impl1_synplify_tmp4.lpf b/CPLD1/impl1/NewExtIns_CPLD1_impl1_synplify_tmp4.lpf new file mode 100644 index 0000000..e69de29 diff --git a/CPLD1/impl1/NewExtIns_CPLD1_impl1_synplify_tmp8.lpf b/CPLD1/impl1/NewExtIns_CPLD1_impl1_synplify_tmp8.lpf new file mode 100644 index 0000000..e69de29 diff --git a/CPLD1/impl1/_cmd._cml b/CPLD1/impl1/_cmd._cml new file mode 100644 index 0000000..506b537 --- /dev/null +++ b/CPLD1/impl1/_cmd._cml @@ -0,0 +1 @@ +-link -encrypt -top RelayConTop -osyn /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/impl1/synwork/NewExtIns_CPLD1_impl1_comp.srs /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/impl1/synwork/layer0.srs -jobname linker \ No newline at end of file diff --git a/CPLD1/impl1/impl1.xcf b/CPLD1/impl1/impl1.xcf new file mode 100644 index 0000000..49222ea --- /dev/null +++ b/CPLD1/impl1/impl1.xcf @@ -0,0 +1,52 @@ + + + + + + JTAG + + + 1 + Lattice + MachXO2 + LCMXO2-7000HC + 0x012bd043 + All + LCMXO2-7000HC + + 8 + 11111111 + 1 + 0 + + D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/impl1/NewExtIns_CPLD1_impl1.jed + 01/19/26 12:45:04 + 0x75FB + FLASH Erase,Program,Verify + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB + EzUSB-0 + \\?\usb#vid_1134&pid_8001#9&2fe42d87&0&2# + + diff --git a/CPLD1/impl1/pmi_distributed_dpramXbnoner212pb07f9c9.edn b/CPLD1/impl1/pmi_distributed_dpramXbnoner212pb07f9c9.edn new file mode 100644 index 0000000..098a65c --- /dev/null +++ b/CPLD1/impl1/pmi_distributed_dpramXbnoner212pb07f9c9.edn @@ -0,0 +1,227 @@ +(edif pmi_distributed_dpramXbnoner212pb07f9c9 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 13 11 1 36) + (program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2")))) + (comment "C:/lscc/diamond/3.14/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 2 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner212pb07f9c9 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell ROM16X1A + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port AD3 + (direction INPUT)) + (port AD2 + (direction INPUT)) + (port AD1 + (direction INPUT)) + (port AD0 + (direction INPUT)) + (port DO0 + (direction OUTPUT))))) + (cell DPR16X4C + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DI0 + (direction INPUT)) + (port DI1 + (direction INPUT)) + (port DI2 + (direction INPUT)) + (port DI3 + (direction INPUT)) + (port WCK + (direction INPUT)) + (port WRE + (direction INPUT)) + (port RAD0 + (direction INPUT)) + (port RAD1 + (direction INPUT)) + (port RAD2 + (direction INPUT)) + (port RAD3 + (direction INPUT)) + (port WAD0 + (direction INPUT)) + (port WAD1 + (direction INPUT)) + (port WAD2 + (direction INPUT)) + (port WAD3 + (direction INPUT)) + (port DO0 + (direction OUTPUT)) + (port DO1 + (direction OUTPUT)) + (port DO2 + (direction OUTPUT)) + (port DO3 + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell pmi_distributed_dpramXbnoner212pb07f9c9 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(0:0)") 1) + (direction INPUT)) + (port (array (rename Data "Data(1:0)") 2) + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WE + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(0:0)") 1) + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port (array (rename Q "Q(1:0)") 2) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance LUT4_0 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance mem_0_0 + (viewRef view1 + (cellRef DPR16X4C)) + (property MEM_INIT_FILE + (string "(0-1)(0-1)")) + (property MEM_LPC_FILE + (string "pmi_distributed_dpramXbnoner212pb07f9c9__PMI__2__2__2B")) + (property COMP + (string "mem_0_0")) + (property initval + (string "0x0000000000000000"))) + (net dataout1_ffin + (joined + (portRef DO1 (instanceRef mem_0_0)) + (portRef D (instanceRef FF_1)))) + (net dataout0_ffin + (joined + (portRef DO0 (instanceRef mem_0_0)) + (portRef D (instanceRef FF_0)))) + (net dec0_wre3 + (joined + (portRef WRE (instanceRef mem_0_0)) + (portRef DO0 (instanceRef LUT4_0)))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef AD0 (instanceRef LUT4_0)) + (portRef AD1 (instanceRef LUT4_0)) + (portRef RAD3 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(joined + (portRef WE) + (portRef AD3 (instanceRef LUT4_0)))) + (net clk + (joined + (portRef WrClock) + (portRef WCK (instanceRef mem_0_0)))) + (net datain1 + (joined + (portRef (member Data 0)) + (portRef DI1 (instanceRef mem_0_0)))) + (net datain0 + (joined + (portRef (member Data 1)) + (portRef DI0 (instanceRef mem_0_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 0)) + (portRef WAD0 (instanceRef mem_0_0)))))))) + (design pmi_distributed_dpramXbnoner212pb07f9c9 + (cellRef pmi_distributed_dpramXbnoner212pb07f9c9 + (libraryRef ORCLIB))) +) diff --git a/CPLD1/impl1/pmi_distributed_dpramXbnoner224pb08036b.edn b/CPLD1/impl1/pmi_distributed_dpramXbnoner224pb08036b.edn new file mode 100644 index 0000000..a33f1a3 --- /dev/null +++ b/CPLD1/impl1/pmi_distributed_dpramXbnoner224pb08036b.edn @@ -0,0 +1,233 @@ +(edif pmi_distributed_dpramXbnoner224pb08036b + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 5 14 15 11 48) + (program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2")))) + (comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 4 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner224pb08036b -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell ROM16X1A + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port AD3 + (direction INPUT)) + (port AD2 + (direction INPUT)) + (port AD1 + (direction INPUT)) + (port AD0 + (direction INPUT)) + (port DO0 + (direction OUTPUT))))) + (cell DPR16X4C + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DI0 + (direction INPUT)) + (port DI1 + (direction INPUT)) + (port DI2 + (direction INPUT)) + (port DI3 + (direction INPUT)) + (port WCK + (direction INPUT)) + (port WRE + (direction INPUT)) + (port RAD0 + (direction INPUT)) + (port RAD1 + (direction INPUT)) + (port RAD2 + (direction INPUT)) + (port RAD3 + (direction INPUT)) + (port WAD0 + (direction INPUT)) + (port WAD1 + (direction INPUT)) + (port WAD2 + (direction INPUT)) + (port WAD3 + (direction INPUT)) + (port DO0 + (direction OUTPUT)) + (port DO1 + (direction OUTPUT)) + (port DO2 + (direction OUTPUT)) + (port DO3 + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell pmi_distributed_dpramXbnoner224pb08036b + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(1:0)") 2) + (direction INPUT)) + (port (array (rename Data "Data(1:0)") 2) + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WE + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(1:0)") 2) + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port (array (rename Q "Q(1:0)") 2) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance LUT4_0 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance mem_0_0 + (viewRef view1 + (cellRef DPR16X4C)) + (property MEM_INIT_FILE + (string "(0-3)(0-1)")) + (property MEM_LPC_FILE + (string "pmi_distributed_dpramXbnoner224pb08036b__PMI__4__2__2B")) + (property COMP + (string "mem_0_0")) + (property initval + (string "0x0000000000000000"))) + (net dataout1_ffin + (joined + (portRef DO1 (instanceRef mem_0_0)) + (portRef D (instanceRef FF_1)))) + (net dataout0_ffin + (joined + (portRef DO0 (instanceRef mem_0_0)) + (portRef D (instanceRef FF_0)))) + (net dec0_wre3 + (joined + (portRef WRE (instanceRef mem_0_0)) + (portRef DO0 (instanceRef LUT4_0)))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef AD0 (instanceRef LUT4_0)) + (portRef AD1 (instanceRef LUT4_0)) + (portRef RAD3 (instanceRef mem_0_0)) + (portRef RAD2 (instanceRef mem_0_0)) + (portRef WAD3 (instanceRef mem_0_0)) + (portRef WAD2 (instanceRef mem_0_0)) + (portRef DI3 (instanceRef mem_0_0)) + (portRef DI2 (instanceRef mem_0_0)))) + (net dataout1 + (joined + (portRef (member Q 0)) + (portRef Q (instanceRef FF_1)))) + (net dataout0 + (joined + (portRef (member Q 1)) + (portRef Q (instanceRef FF_0)))) + (net reset + (joined + (portRef Reset) + (portRef CD (instanceRef FF_1)) + (portRef CD (instanceRef FF_0)))) + (net rden + (joined + (portRef RdClockEn) + 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mem_0_0)))))))) + (design pmi_distributed_dpramXbnoner224pb08036b + (cellRef pmi_distributed_dpramXbnoner224pb08036b + (libraryRef ORCLIB))) +) diff --git a/CPLD1/impl1/pmi_distributed_dpramXbnoner224pb08036b_0.edn b/CPLD1/impl1/pmi_distributed_dpramXbnoner224pb08036b_0.edn new file mode 100644 index 0000000..3855be2 --- /dev/null +++ b/CPLD1/impl1/pmi_distributed_dpramXbnoner224pb08036b_0.edn @@ -0,0 +1,233 @@ +(edif pmi_distributed_dpramXbnoner224pb08036b_0 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 5 14 15 11 48) + (program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2")))) + (comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 4 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner224pb08036b_0 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell ROM16X1A + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port AD3 + (direction INPUT)) + (port AD2 + (direction INPUT)) + (port AD1 + (direction INPUT)) + (port AD0 + (direction INPUT)) + (port DO0 + (direction OUTPUT))))) + (cell DPR16X4C + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DI0 + (direction INPUT)) + (port DI1 + (direction INPUT)) + (port DI2 + (direction INPUT)) + (port DI3 + (direction INPUT)) + (port WCK + (direction INPUT)) + (port WRE + (direction INPUT)) + (port RAD0 + (direction INPUT)) + (port RAD1 + (direction INPUT)) + (port RAD2 + (direction INPUT)) + (port RAD3 + (direction INPUT)) + (port WAD0 + (direction INPUT)) + (port WAD1 + (direction INPUT)) + (port WAD2 + (direction INPUT)) + (port WAD3 + (direction INPUT)) + (port DO0 + (direction OUTPUT)) + (port DO1 + (direction OUTPUT)) + (port DO2 + (direction OUTPUT)) + (port DO3 + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell pmi_distributed_dpramXbnoner224pb08036b_0 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(1:0)") 2) + (direction INPUT)) + (port (array (rename Data "Data(1:0)") 2) + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WE + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(1:0)") 2) + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port (array (rename Q "Q(1:0)") 2) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance LUT4_0 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance mem_0_0 + (viewRef view1 + (cellRef DPR16X4C)) + (property MEM_INIT_FILE + (string "(0-3)(0-1)")) + (property MEM_LPC_FILE + (string "pmi_distributed_dpramXbnoner224pb08036b_0__PMI__4__2__2B")) + (property COMP + (string "mem_0_0")) + (property initval + (string "0x0000000000000000"))) + (net dataout1_ffin + (joined + (portRef DO1 (instanceRef mem_0_0)) + (portRef D (instanceRef FF_1)))) + (net dataout0_ffin + (joined + (portRef DO0 (instanceRef mem_0_0)) + (portRef D (instanceRef FF_0)))) + (net dec0_wre3 + (joined + (portRef WRE (instanceRef mem_0_0)) + (portRef DO0 (instanceRef LUT4_0)))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef AD0 (instanceRef LUT4_0)) + (portRef AD1 (instanceRef LUT4_0)) + (portRef RAD3 (instanceRef mem_0_0)) + (portRef RAD2 (instanceRef mem_0_0)) + (portRef WAD3 (instanceRef mem_0_0)) + (portRef WAD2 (instanceRef mem_0_0)) + (portRef DI3 (instanceRef mem_0_0)) + (portRef DI2 (instanceRef mem_0_0)))) + (net dataout1 + (joined + (portRef (member Q 0)) + (portRef Q (instanceRef FF_1)))) + (net dataout0 + (joined + (portRef (member Q 1)) + (portRef Q (instanceRef FF_0)))) + (net reset + (joined + (portRef Reset) + (portRef CD (instanceRef FF_1)) + (portRef CD (instanceRef FF_0)))) + (net rden + (joined + (portRef RdClockEn) + (portRef SP (instanceRef FF_1)) + (portRef SP (instanceRef FF_0)))) + (net rdclk + (joined + (portRef RdClock) + (portRef CK (instanceRef FF_1)) + (portRef CK (instanceRef FF_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 0)) + (portRef RAD1 (instanceRef mem_0_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 1)) + (portRef RAD0 (instanceRef mem_0_0)))) + (net cken + (joined + (portRef WrClockEn) + (portRef AD2 (instanceRef LUT4_0)))) + (net wren + (joined + (portRef WE) + (portRef AD3 (instanceRef LUT4_0)))) + (net clk + (joined + (portRef WrClock) + (portRef WCK (instanceRef mem_0_0)))) + (net datain1 + (joined + (portRef (member Data 0)) + (portRef DI1 (instanceRef mem_0_0)))) + (net datain0 + (joined + (portRef (member Data 1)) + (portRef DI0 (instanceRef mem_0_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 0)) + (portRef WAD1 (instanceRef mem_0_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 1)) + (portRef WAD0 (instanceRef mem_0_0)))))))) + (design pmi_distributed_dpramXbnoner224pb08036b_0 + (cellRef pmi_distributed_dpramXbnoner224pb08036b_0 + (libraryRef ORCLIB))) +) diff --git a/CPLD1/impl1/pmi_ram_dpXbnonesadr3610102436101024p13959ecb.edn b/CPLD1/impl1/pmi_ram_dpXbnonesadr3610102436101024p13959ecb.edn new file mode 100644 index 0000000..7a7ee85 --- /dev/null +++ b/CPLD1/impl1/pmi_ram_dpXbnonesadr3610102436101024p13959ecb.edn @@ -0,0 +1,925 @@ +(edif pmi_ram_dpXbnonesadr3610102436101024p13959ecb + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 14 14 13 5) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 36 -num_rows 1024 -rdata_width 36 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr3610102436101024p13959ecb -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + 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(direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(35:0)") 36) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3610102436101024p13959ecb__PMIP__1024__36__36__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3610102436101024p13959ecb__PMIP__1024__36__36__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property 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ADA9 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_0_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_1_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_2_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb_0_3_0)))))))) + (design pmi_ram_dpXbnonesadr3610102436101024p13959ecb + (cellRef pmi_ram_dpXbnonesadr3610102436101024p13959ecb + (libraryRef ORCLIB))) +) diff --git a/CPLD1/impl1/pmi_ram_dpXbnonesadr3611204836112048p1395e304.edn b/CPLD1/impl1/pmi_ram_dpXbnonesadr3611204836112048p1395e304.edn new file mode 100644 index 0000000..f2c32f6 --- /dev/null +++ b/CPLD1/impl1/pmi_ram_dpXbnonesadr3611204836112048p1395e304.edn @@ -0,0 +1,1779 @@ +(edif pmi_ram_dpXbnonesadr3611204836112048p1395e304 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 15 16 12 6) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 36 -num_rows 2048 -rdata_width 36 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr3611204836112048p1395e304 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr3611204836112048p1395e304 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(35:0)") 36) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(35:0)") 36) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3611204836112048p1395e304__PMIP__2048__36__36__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3611204836112048p1395e304__PMIP__2048__36__36__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_2_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3611204836112048p1395e304__PMIP__2048__36__36__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_3_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3611204836112048p1395e304__PMIP__2048__36__36__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_0_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3611204836112048p1395e304__PMIP__2048__36__36__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_1_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3611204836112048p1395e304__PMIP__2048__36__36__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_2_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3611204836112048p1395e304__PMIP__2048__36__36__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_3_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3611204836112048p1395e304__PMIP__2048__36__36__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_2_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_3_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_0_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_1_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_2_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_3_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_2_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_2_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_2_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_2_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_2_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_2_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_2_5)) + (portRef ADB1 (instanceRef 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pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_0_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_1_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_2_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_3_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_2_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_3_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_0_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_1_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_2_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_3_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_2_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_3_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_0_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_1_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_2_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_3_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_2_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_3_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_0_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_1_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_2_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_3_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_2_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_3_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_0_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_1_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_2_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_3_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_2_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_3_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_0_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_1_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_2_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_3_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_2_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_3_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_0_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_1_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_2_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_3_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_2_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_3_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_0_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_1_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_2_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_3_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_2_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_3_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_0_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_1_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_2_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_3_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_2_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_3_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_0_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_1_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_2_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_3_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_2_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_3_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_0_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_1_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_2_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_3_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_0_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_1_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_2_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_0_3_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_0_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_1_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_2_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3611204836112048p1395e304_1_3_0)))))))) + (design pmi_ram_dpXbnonesadr3611204836112048p1395e304 + (cellRef pmi_ram_dpXbnonesadr3611204836112048p1395e304 + (libraryRef ORCLIB))) +) diff --git a/CPLD1/impl1/pmi_ram_dpXbnonesadr3811204838112048p1395f327.edn b/CPLD1/impl1/pmi_ram_dpXbnonesadr3811204838112048p1395f327.edn new file mode 100644 index 0000000..82e5af6 --- /dev/null +++ b/CPLD1/impl1/pmi_ram_dpXbnonesadr3811204838112048p1395f327.edn @@ -0,0 +1,1491 @@ +(edif pmi_ram_dpXbnonesadr3811204838112048p1395f327 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 19 12 38 13) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 38 -num_rows 2048 -rdata_width 38 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr3811204838112048p1395f327 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr3811204838112048p1395f327 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(37:0)") 38) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(37:0)") 38) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA1 (instanceRef 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pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net Reset + (joined + (portRef Reset) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net RdClockEn + (joined + (portRef RdClockEn) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net rdclk + (joined + (portRef RdClock) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net wren + (joined + (portRef WE) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net datain37 + (joined + (portRef (member Data 0)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net datain36 + (joined + (portRef (member Data 1)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net datain35 + (joined + (portRef (member Data 2)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)))) + (net datain34 + (joined + (portRef (member Data 3)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)))) + (net datain33 + (joined + (portRef (member Data 4)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)))) + (net datain32 + (joined + (portRef (member Data 5)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)))) + (net datain31 + (joined + (portRef (member Data 6)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)))) + (net datain30 + (joined + (portRef (member Data 7)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)))) + (net datain29 + (joined + (portRef (member Data 8)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)))) + (net datain28 + (joined + (portRef (member Data 9)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)))) + (net datain27 + (joined + (portRef (member Data 10)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)))) + (net datain26 + (joined + (portRef (member Data 11)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)))) + (net datain25 + (joined + (portRef (member Data 12)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)))) + (net datain24 + (joined + (portRef (member Data 13)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)))) + (net datain23 + (joined + (portRef (member Data 14)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)))) + (net datain22 + (joined + (portRef (member Data 15)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)))) + (net datain21 + (joined + (portRef (member Data 16)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)))) + (net datain20 + (joined + (portRef (member Data 17)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)))) + (net datain19 + (joined + (portRef (member Data 18)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)))) + (net datain18 + (joined + (portRef (member Data 19)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)))) + (net datain17 + (joined + (portRef (member Data 20)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)))) + (net datain16 + (joined + (portRef (member Data 21)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)))) + (net datain15 + (joined + (portRef (member Data 22)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)))) + (net datain14 + (joined + (portRef (member Data 23)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)))) + (net datain13 + (joined + (portRef (member Data 24)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)))) + (net datain12 + (joined + (portRef (member Data 25)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)))) + (net datain11 + (joined + (portRef (member Data 26)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)))) + (net datain10 + (joined + (portRef (member Data 27)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)))) + (net datain9 + (joined + (portRef (member Data 28)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)))) + (net datain8 + (joined + (portRef (member Data 29)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)))) + (net datain7 + (joined + (portRef (member Data 30)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)))) + (net datain6 + (joined + (portRef (member Data 31)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)))) + (net datain5 + (joined + (portRef (member Data 32)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)))) + (net datain4 + (joined + (portRef (member Data 33)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)))) + (net datain3 + (joined + (portRef (member Data 34)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)))) + (net datain2 + (joined + (portRef (member Data 35)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)))) + (net datain1 + (joined + (portRef (member Data 36)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)))) + (net datain0 + (joined + (portRef (member Data 37)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)))) + (net raddr10 + (joined + (portRef (member RdAddress 0)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net raddr9 + (joined + (portRef (member RdAddress 1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net raddr8 + (joined + (portRef (member RdAddress 2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net raddr7 + (joined + (portRef (member RdAddress 3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))))))) + (design pmi_ram_dpXbnonesadr3811204838112048p1395f327 + (cellRef pmi_ram_dpXbnonesadr3811204838112048p1395f327 + (libraryRef ORCLIB))) +) diff --git a/CPLD1/impl1/pmi_ram_dpXbnonesadr3911204839112048p1395fa29.edn b/CPLD1/impl1/pmi_ram_dpXbnonesadr3911204839112048p1395fa29.edn new file mode 100644 index 0000000..9a3c286 --- /dev/null +++ b/CPLD1/impl1/pmi_ram_dpXbnonesadr3911204839112048p1395fa29.edn @@ -0,0 +1,1498 @@ +(edif pmi_ram_dpXbnonesadr3911204839112048p1395fa29 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 5 14 15 11 48) + (program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2")))) + (comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 39 -num_rows 2048 -rdata_width 39 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr3911204839112048p1395fa29 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction 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pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_8_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_9_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_0_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_1_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_2_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_3_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_4_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_5_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_6_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_7_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_8_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_9_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_0_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_1_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_2_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_3_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_4_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_5_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_6_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_7_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_8_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_9_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_0_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_1_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_2_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_3_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_4_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_5_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_6_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_7_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_8_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_9_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_0_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_1_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_2_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_3_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_4_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_5_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_6_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_7_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_8_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_9_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_0_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_1_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_2_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_3_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_4_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_5_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_6_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_7_2)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_8_1)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29_0_9_0)))))))) + (design pmi_ram_dpXbnonesadr3911204839112048p1395fa29 + (cellRef pmi_ram_dpXbnonesadr3911204839112048p1395fa29 + (libraryRef ORCLIB))) +) diff --git a/CPLD1/impl1/pmi_ram_dpXbnonesadr4311204843112048p1395d432.edn b/CPLD1/impl1/pmi_ram_dpXbnonesadr4311204843112048p1395d432.edn new file mode 100644 index 0000000..23217a5 --- /dev/null +++ b/CPLD1/impl1/pmi_ram_dpXbnonesadr4311204843112048p1395d432.edn @@ -0,0 +1,2094 @@ +(edif pmi_ram_dpXbnonesadr4311204843112048p1395d432 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 15 16 43 51) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 43 -num_rows 2048 -rdata_width 43 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr4311204843112048p1395d432 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr4311204843112048p1395d432 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(42:0)") 43) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(42:0)") 43) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4311204843112048p1395d432__PMIP__2048__43__43__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4311204843112048p1395d432__PMIP__2048__43__43__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4311204843112048p1395d432__PMIP__2048__43__43__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4311204843112048p1395d432__PMIP__2048__43__43__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4311204843112048p1395d432__PMIP__2048__43__43__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4311204843112048p1395d432__PMIP__2048__43__43__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4311204843112048p1395d432__PMIP__2048__43__43__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4311204843112048p1395d432__PMIP__2048__43__43__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4311204843112048p1395d432__PMIP__2048__43__43__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4311204843112048p1395d432__PMIP__2048__43__43__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)) + (portRef CSA1 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pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))))))) + (design pmi_ram_dpXbnonesadr4311204843112048p1395d432 + (cellRef pmi_ram_dpXbnonesadr4311204843112048p1395d432 + (libraryRef ORCLIB))) +) diff --git a/CPLD1/impl1/pmi_ram_dpXbnonesadr7111204871112048p1395dc00.edn b/CPLD1/impl1/pmi_ram_dpXbnonesadr7111204871112048p1395dc00.edn new file mode 100644 index 0000000..997665e --- /dev/null +++ b/CPLD1/impl1/pmi_ram_dpXbnonesadr7111204871112048p1395dc00.edn @@ -0,0 +1,3172 @@ +(edif pmi_ram_dpXbnonesadr7111204871112048p1395dc00 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 15 16 37 49) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 71 -num_rows 2048 -rdata_width 71 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr7111204871112048p1395dc00 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr7111204871112048p1395dc00 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(70:0)") 71) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(70:0)") 71) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7111204871112048p1395dc00__PMIP__2048__71__71__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7111204871112048p1395dc00__PMIP__2048__71__71__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7111204871112048p1395dc00__PMIP__2048__71__71__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7111204871112048p1395dc00__PMIP__2048__71__71__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7111204871112048p1395dc00__PMIP__2048__71__71__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7111204871112048p1395dc00__PMIP__2048__71__71__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7111204871112048p1395dc00__PMIP__2048__71__71__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7111204871112048p1395dc00__PMIP__2048__71__71__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7111204871112048p1395dc00__PMIP__2048__71__71__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7111204871112048p1395dc00__PMIP__2048__71__71__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7111204871112048p1395dc00__PMIP__2048__71__71__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7111204871112048p1395dc00__PMIP__2048__71__71__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7111204871112048p1395dc00__PMIP__2048__71__71__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7111204871112048p1395dc00__PMIP__2048__71__71__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7111204871112048p1395dc00__PMIP__2048__71__71__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7111204871112048p1395dc00__PMIP__2048__71__71__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_70 + (viewRef view1 + (cellRef MUX21))) + (instance mux_69 + (viewRef view1 + (cellRef MUX21))) + (instance mux_68 + (viewRef view1 + (cellRef MUX21))) + (instance mux_67 + (viewRef view1 + (cellRef MUX21))) + (instance mux_66 + (viewRef view1 + (cellRef MUX21))) + (instance mux_65 + (viewRef view1 + (cellRef MUX21))) + (instance mux_64 + (viewRef view1 + (cellRef MUX21))) + (instance mux_63 + (viewRef view1 + (cellRef MUX21))) + (instance mux_62 + (viewRef view1 + (cellRef MUX21))) + (instance mux_61 + (viewRef view1 + (cellRef MUX21))) + (instance mux_60 + (viewRef view1 + (cellRef MUX21))) + (instance mux_59 + (viewRef view1 + (cellRef MUX21))) + (instance mux_58 + (viewRef view1 + (cellRef MUX21))) + (instance mux_57 + (viewRef view1 + (cellRef MUX21))) + (instance mux_56 + (viewRef view1 + (cellRef MUX21))) + (instance mux_55 + (viewRef view1 + (cellRef MUX21))) + (instance mux_54 + (viewRef view1 + (cellRef MUX21))) + (instance mux_53 + (viewRef view1 + (cellRef MUX21))) + (instance mux_52 + (viewRef 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mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADB0 (instanceRef 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mdout1_1_2 + (joined + (portRef D1 (instanceRef mux_68)) + (portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)))) + (net mdout1_0_2 + (joined + (portRef D0 (instanceRef mux_68)) + (portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)))) + (net mdout1_1_3 + (joined + (portRef D1 (instanceRef mux_67)) + (portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)))) + (net mdout1_0_3 + (joined + (portRef D0 (instanceRef mux_67)) + (portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)))) + (net mdout1_1_4 + (joined + (portRef D1 (instanceRef mux_66)) + (portRef DOB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)))) + (net mdout1_0_4 + (joined + (portRef D0 (instanceRef mux_66)) + (portRef DOB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)))) + (net mdout1_1_5 + (joined + (portRef D1 (instanceRef mux_65)) + (portRef DOB5 (instanceRef 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pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)))) + (net datain2 + (joined + (portRef (member Data 68)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)))) + (net datain1 + (joined + (portRef (member Data 69)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)))) + (net datain0 + (joined + (portRef (member Data 70)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)))) + (net raddr10 + (joined + (portRef (member RdAddress 0)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)) + (portRef D (instanceRef FF_1)))) + (net raddr9 + (joined + (portRef (member RdAddress 1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))) + (net raddr8 + (joined + (portRef (member RdAddress 2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))) + (net raddr7 + (joined + (portRef (member RdAddress 3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_0_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_1_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_2_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_3_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_4_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_5_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_6_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_0_7_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_0_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_1_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_2_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_3_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_4_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_5_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_6_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00_1_7_0)))))))) + (design pmi_ram_dpXbnonesadr7111204871112048p1395dc00 + (cellRef pmi_ram_dpXbnonesadr7111204871112048p1395dc00 + (libraryRef ORCLIB))) +) diff --git a/CPLD1/impl1/pmi_ram_dpXbnonesadr7411204874112048p1395f517.edn b/CPLD1/impl1/pmi_ram_dpXbnonesadr7411204874112048p1395f517.edn new file mode 100644 index 0000000..10aced1 --- /dev/null +++ b/CPLD1/impl1/pmi_ram_dpXbnonesadr7411204874112048p1395f517.edn @@ -0,0 +1,3411 @@ +(edif pmi_ram_dpXbnonesadr7411204874112048p1395f517 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 15 16 52 6) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 74 -num_rows 2048 -rdata_width 74 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr7411204874112048p1395f517 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction 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Q "Q(73:0)") 74) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7411204874112048p1395f517__PMIP__2048__74__74__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string 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CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7411204874112048p1395f517__PMIP__2048__74__74__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + 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+ (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7411204874112048p1395f517__PMIP__2048__74__74__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7411204874112048p1395f517__PMIP__2048__74__74__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7411204874112048p1395f517__PMIP__2048__74__74__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + 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"ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7411204874112048p1395f517__PMIP__2048__74__74__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7411204874112048p1395f517__PMIP__2048__74__74__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7411204874112048p1395f517__PMIP__2048__74__74__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7411204874112048p1395f517__PMIP__2048__74__74__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7411204874112048p1395f517__PMIP__2048__74__74__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_73 + (viewRef view1 + (cellRef MUX21))) + (instance mux_72 + (viewRef view1 + (cellRef MUX21))) + (instance mux_71 + (viewRef view1 + (cellRef MUX21))) + (instance mux_70 + (viewRef view1 + (cellRef MUX21))) + (instance mux_69 + (viewRef view1 + (cellRef MUX21))) + (instance mux_68 + (viewRef view1 + (cellRef MUX21))) + (instance mux_67 + (viewRef view1 + (cellRef MUX21))) + (instance mux_66 + (viewRef view1 + (cellRef MUX21))) + (instance mux_65 + (viewRef view1 + (cellRef MUX21))) + (instance mux_64 + (viewRef view1 + (cellRef MUX21))) + (instance mux_63 + (viewRef view1 + (cellRef MUX21))) + (instance mux_62 + (viewRef view1 + (cellRef MUX21))) + (instance mux_61 + (viewRef view1 + (cellRef MUX21))) + (instance mux_60 + (viewRef view1 + (cellRef MUX21))) + (instance mux_59 + (viewRef view1 + (cellRef MUX21))) + (instance mux_58 + (viewRef view1 + (cellRef MUX21))) + (instance mux_57 + (viewRef view1 + (cellRef MUX21))) + (instance mux_56 + (viewRef view1 + (cellRef MUX21))) + (instance mux_55 + (viewRef view1 + (cellRef MUX21))) + (instance mux_54 + (viewRef view1 + (cellRef MUX21))) + (instance mux_53 + (viewRef view1 + (cellRef MUX21))) + (instance mux_52 + (viewRef view1 + (cellRef MUX21))) + (instance mux_51 + (viewRef view1 + (cellRef MUX21))) + (instance mux_50 + (viewRef view1 + (cellRef MUX21))) + (instance mux_49 + (viewRef view1 + (cellRef MUX21))) + (instance mux_48 + (viewRef view1 + (cellRef MUX21))) + (instance mux_47 + (viewRef view1 + (cellRef MUX21))) + (instance mux_46 + (viewRef view1 + (cellRef MUX21))) + (instance mux_45 + (viewRef view1 + (cellRef MUX21))) + (instance mux_44 + (viewRef view1 + (cellRef MUX21))) + (instance mux_43 + (viewRef view1 + (cellRef MUX21))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef CSA2 (instanceRef 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FF_1)))) + (net raddr9 + (joined + (portRef (member RdAddress 1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))) + (net raddr8 + (joined + (portRef (member RdAddress 2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))) + (net raddr7 + (joined + (portRef (member RdAddress 3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_0_17)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_1_16)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_2_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_3_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_4_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_5_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_6_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_7_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_0_8_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_0_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_1_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_2_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_3_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_4_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_5_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_6_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_7_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7411204874112048p1395f517_1_8_0)))))))) + (design pmi_ram_dpXbnonesadr7411204874112048p1395f517 + (cellRef pmi_ram_dpXbnonesadr7411204874112048p1395f517 + (libraryRef ORCLIB))) +) diff --git a/CPLD1/impl1/pmi_ram_dpXbnonesadr81010248101024p1371af55.edn b/CPLD1/impl1/pmi_ram_dpXbnonesadr81010248101024p1371af55.edn new file mode 100644 index 0000000..71d0439 --- /dev/null +++ b/CPLD1/impl1/pmi_ram_dpXbnonesadr81010248101024p1371af55.edn @@ -0,0 +1,456 @@ +(edif pmi_ram_dpXbnonesadr81010248101024p1371af55 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 15 16 2 21) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 8 -num_rows 1024 -rdata_width 8 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr81010248101024p1371af55 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr81010248101024p1371af55 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(9:0)") 10) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(9:0)") 10) + (direction INPUT)) + (port (array (rename Data "Data(7:0)") 8) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(7:0)") 8) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr81010248101024p1371af55__PMIP__1024__8__8__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net dataout7 + (joined + (portRef (member Q 0)) + (portRef DOB7 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net dataout6 + (joined + (portRef (member Q 1)) + (portRef DOB6 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net dataout5 + (joined + (portRef (member Q 2)) + (portRef DOB5 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net dataout4 + (joined + (portRef (member Q 3)) + (portRef DOB4 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net dataout3 + (joined + (portRef (member Q 4)) + (portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net dataout2 + (joined + (portRef (member Q 5)) + (portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net dataout1 + (joined + (portRef (member Q 6)) + (portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net dataout0 + (joined + (portRef (member Q 7)) + (portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net WrClockEn + (joined + (portRef WrClockEn) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net clk + (joined + (portRef WrClock) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net Reset + (joined + (portRef Reset) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net RdClockEn + (joined + (portRef RdClockEn) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net rdclk + (joined + (portRef RdClock) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net wren + (joined + (portRef WE) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net datain7 + (joined + (portRef (member Data 0)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net datain6 + (joined + (portRef (member Data 1)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net datain5 + (joined + (portRef (member Data 2)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net datain4 + (joined + (portRef (member Data 3)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net datain3 + (joined + (portRef (member Data 4)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net datain2 + (joined + (portRef (member Data 5)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net datain1 + (joined + (portRef (member Data 6)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net datain0 + (joined + (portRef (member Data 7)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net raddr9 + (joined + (portRef (member RdAddress 0)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net raddr8 + (joined + (portRef (member RdAddress 1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net raddr7 + (joined + (portRef (member RdAddress 2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 0)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr81010248101024p1371af55_0_0_0)))))))) + (design pmi_ram_dpXbnonesadr81010248101024p1371af55 + (cellRef pmi_ram_dpXbnonesadr81010248101024p1371af55 + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/NewExtIns_CPLD2_impl1.areasrr b/CPLD2/impl1/NewExtIns_CPLD2_impl1.areasrr new file mode 100644 index 0000000..5141b8e --- /dev/null +++ b/CPLD2/impl1/NewExtIns_CPLD2_impl1.areasrr @@ -0,0 +1,162 @@ +---------------------------------------------------------------------- +Report for cell RelayConTop.verilog + +Register bits: 1275 of 6864 (19%) +PIC Latch: 0 +I/O cells: 187 + Cell usage: + cell count Res Usage(%) + CCU2D 59 100.0 + FD1P3AX 427 100.0 + FD1P3AY 3 100.0 + FD1P3BX 33 100.0 + FD1P3DX 347 100.0 + FD1P3IX 175 100.0 + FD1P3JX 1 100.0 + FD1S3AX 20 100.0 + FD1S3AY 1 100.0 + FD1S3BX 4 100.0 + FD1S3DX 87 100.0 + FD1S3IX 33 100.0 + FD1S3JX 1 100.0 + GSR 1 100.0 + IB 5 100.0 + IFS1P3IX 2 100.0 + IFS1P3JX 1 100.0 + INV 18 100.0 + L6MUX21 74 100.0 + OB 181 100.0 + OBZ 1 100.0 + OFS1P3DX 4 100.0 + OFS1P3IX 136 100.0 + ORCALUT4 1290 100.0 + PFUMX 104 100.0 + PUR 1 100.0 + VHI 15 100.0 + VLO 15 100.0 + jtagconn16 1 100.0 + pmi_distributed_dpram_4s_2s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 2 100.0 + pmi_ram_dp_Z4 1 100.0 +SUB MODULES + BUS_Con_uniq_1 1 100.0 + CPLD_Con_uniq_1 1 100.0 + Reg_file_uniq_1 1 100.0 + relaycontop_la0 1 100.0 + relaycontop_la0_trig 1 100.0 + reveal_coretop 1 100.0 + + TOTAL 3049 +---------------------------------------------------------------------- +Report for cell CPLD_Con_uniq_1.netlist + Instance path: CPLD_Con_2 + Cell usage: + cell count Res Usage(%) + CCU2D 9 15.3 + FD1P3IX 44 25.1 + FD1P3JX 1 100.0 + FD1S3AX 14 70.0 + FD1S3IX 23 69.7 + INV 1 5.6 + ORCALUT4 339 26.3 + VHI 1 6.7 + VLO 1 6.7 + + TOTAL 433 +---------------------------------------------------------------------- +Report for cell Reg_file_uniq_1.netlist + Instance path: CPLD_Reg_2 + Cell usage: + cell count Res Usage(%) + FD1P3AX 409 95.8 + FD1P3AY 3 100.0 + FD1S3AX 4 20.0 + FD1S3AY 1 100.0 + L6MUX21 72 97.3 + ORCALUT4 250 19.4 + PFUMX 97 93.3 + VHI 1 6.7 + VLO 1 6.7 + + TOTAL 838 +---------------------------------------------------------------------- +Report for cell BUS_Con_uniq_1.netlist + Instance path: BUS_Con_2 + Cell usage: + cell count Res Usage(%) + FD1P3IX 131 74.9 + FD1S3AX 2 10.0 + FD1S3IX 10 30.3 + FD1S3JX 1 100.0 + ORCALUT4 96 7.4 + VHI 1 6.7 + VLO 1 6.7 + + TOTAL 242 +---------------------------------------------------------------------- +Report for cell reveal_coretop.verilog + Instance path: RelayConTop_reveal_coretop_instance + Cell usage: + cell count Res Usage(%) + CCU2D 50 84.7 + FD1P3AX 18 4.2 + FD1P3BX 33 100.0 + FD1P3DX 347 100.0 + FD1S3BX 4 100.0 + FD1S3DX 87 100.0 + INV 16 88.9 + L6MUX21 2 2.7 + ORCALUT4 605 46.9 + PFUMX 7 6.7 + VHI 11 73.3 + VLO 11 73.3 + jtagconn16 1 100.0 + pmi_distributed_dpram_4s_2s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 2 100.0 + pmi_ram_dp_Z4 1 100.0 +SUB MODULES + relaycontop_la0 1 100.0 + relaycontop_la0_trig 1 100.0 + + TOTAL 1197 +---------------------------------------------------------------------- +Report for cell relaycontop_la0.netlist + Instance path: RelayConTop_reveal_coretop_instance.relaycontop_la0_inst_0 + Cell usage: + cell count Res Usage(%) + CCU2D 50 84.7 + FD1P3AX 18 4.2 + FD1P3BX 33 100.0 + FD1P3DX 347 100.0 + FD1S3BX 4 100.0 + FD1S3DX 87 100.0 + INV 16 88.9 + L6MUX21 2 2.7 + ORCALUT4 605 46.9 + PFUMX 7 6.7 + VHI 10 66.7 + VLO 10 66.7 + pmi_distributed_dpram_4s_2s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 2 100.0 + pmi_ram_dp_Z4 1 100.0 +SUB MODULES + relaycontop_la0_trig 1 100.0 + + TOTAL 1193 +---------------------------------------------------------------------- +Report for cell relaycontop_la0_trig.netlist + Instance path: RelayConTop_reveal_coretop_instance.relaycontop_la0_inst_0.trig_u + Cell usage: + cell count Res Usage(%) + CCU2D 18 30.5 + FD1P3AX 16 3.7 + FD1P3BX 1 3.0 + FD1P3DX 61 17.6 + FD1S3BX 4 100.0 + FD1S3DX 32 36.8 + INV 9 50.0 + L6MUX21 2 2.7 + ORCALUT4 193 15.0 + PFUMX 7 6.7 + VHI 7 46.7 + VLO 7 46.7 + pmi_distributed_dpram_4s_2s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 2 100.0 + + TOTAL 359 diff --git a/CPLD2/impl1/NewExtIns_CPLD2_impl1.bit b/CPLD2/impl1/NewExtIns_CPLD2_impl1.bit new file mode 100644 index 0000000..5a5daa8 Binary files /dev/null and b/CPLD2/impl1/NewExtIns_CPLD2_impl1.bit differ diff --git a/CPLD2/impl1/NewExtIns_CPLD2_impl1.hub b/CPLD2/impl1/NewExtIns_CPLD2_impl1.hub new file mode 100644 index 0000000..d8aa80f --- /dev/null +++ b/CPLD2/impl1/NewExtIns_CPLD2_impl1.hub @@ -0,0 +1 @@ +HUBID_00 REVEAL_0 diff --git a/CPLD2/impl1/NewExtIns_CPLD2_impl1.jed b/CPLD2/impl1/NewExtIns_CPLD2_impl1.jed new file mode 100644 index 0000000..e890d23 --- /dev/null +++ b/CPLD2/impl1/NewExtIns_CPLD2_impl1.jed @@ -0,0 +1,11472 @@ +* +NOTE Diamond (64-bit) 3.14.0.75.2 JEDEC Compatible Fuse File.* +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.* +NOTE All Rights Reserved.* +NOTE DATE CREATED: Tue May 26 15:52:57 2026* +NOTE DESIGN NAME: NewExtIns_CPLD2_impl1.ncd* +NOTE DEVICE NAME: LCMXO2-7000HC-4FPBGA484* +NOTE JEDEC FILE STATUS: Final Version 1.95* +NOTE PIN ASSIGNMENTS* +NOTE PINS o_miso : AA9 : out* +NOTE PINS o_rvalid : V15 : out* +NOTE PINS i_sys_clk : B9 : in* +NOTE PINS o_PMU_OC_4[31] : A3 : out* +NOTE PINS o_PMU_OC_4[30] : B3 : out* +NOTE PINS o_PMU_OC_4[29] : A2 : out* +NOTE PINS o_PMU_OC_4[28] : C11 : out* +NOTE PINS o_PMU_OC_4[27] : D3 : out* +NOTE PINS o_PMU_OC_4[26] : E2 : out* +NOTE PINS o_PMU_OC_4[25] : D1 : out* +NOTE PINS o_PMU_OC_4[24] : E1 : out* +NOTE PINS o_PMU_OC_4[23] : E15 : out* +NOTE PINS o_PMU_OC_4[22] : G12 : out* +NOTE PINS o_PMU_OC_4[21] : A16 : out* +NOTE PINS o_PMU_OC_4[20] : F12 : out* +NOTE PINS o_PMU_OC_4[19] : C16 : out* +NOTE PINS o_PMU_OC_4[18] : B11 : out* +NOTE PINS o_PMU_OC_4[17] : D12 : out* +NOTE PINS o_PMU_OC_4[16] : C8 : out* +NOTE PINS o_PMU_OC_4[15] : E11 : out* +NOTE PINS o_PMU_OC_4[14] : G11 : out* +NOTE PINS o_PMU_OC_4[13] : C5 : out* +NOTE PINS o_PMU_OC_4[12] : C4 : out* +NOTE PINS o_PMU_OC_4[11] : F1 : out* +NOTE PINS o_PMU_OC_4[10] : G3 : out* +NOTE PINS o_PMU_OC_4[9] : G2 : out* +NOTE PINS o_PMU_OC_4[8] : G1 : out* +NOTE PINS o_PMU_OC_4[7] : H21 : out* +NOTE PINS o_PMU_OC_4[6] : A10 : out* +NOTE PINS o_PMU_OC_4[5] : J21 : out* +NOTE PINS o_PMU_OC_4[4] : E14 : out* +NOTE PINS o_PMU_OC_4[3] : E12 : out* +NOTE PINS o_PMU_OC_4[2] : W14 : out* +NOTE PINS o_PMU_OC_4[1] : G22 : out* +NOTE PINS o_PMU_OC_4[0] : W15 : out* +NOTE PINS o_PMU_OC_3[31] : D21 : out* +NOTE PINS o_PMU_OC_3[30] : E20 : out* +NOTE PINS o_PMU_OC_3[29] : E22 : out* +NOTE PINS o_PMU_OC_3[28] : G21 : out* +NOTE PINS o_PMU_OC_3[27] : C15 : out* +NOTE PINS o_PMU_OC_3[26] : B15 : out* +NOTE PINS o_PMU_OC_3[25] : B14 : out* +NOTE PINS o_PMU_OC_3[24] : B13 : out* +NOTE PINS o_PMU_OC_3[23] : T21 : out* +NOTE PINS o_PMU_OC_3[22] : T22 : out* +NOTE PINS o_PMU_OC_3[21] : V22 : out* +NOTE PINS o_PMU_OC_3[20] : U22 : out* +NOTE PINS o_PMU_OC_3[19] : W22 : out* +NOTE PINS o_PMU_OC_3[18] : R19 : out* +NOTE PINS o_PMU_OC_3[17] : T19 : out* +NOTE PINS o_PMU_OC_3[16] : AB18 : out* +NOTE PINS o_PMU_OC_3[15] : B16 : out* +NOTE PINS o_PMU_OC_3[14] : A17 : out* +NOTE PINS o_PMU_OC_3[13] : C18 : out* +NOTE PINS o_PMU_OC_3[12] : B19 : out* +NOTE PINS o_PMU_OC_3[11] : A13 : out* +NOTE PINS o_PMU_OC_3[10] : B12 : out* +NOTE PINS o_PMU_OC_3[9] : A12 : out* +NOTE PINS o_PMU_OC_3[8] : A11 : out* +NOTE PINS o_PMU_OC_3[7] : R21 : out* +NOTE PINS o_PMU_OC_3[6] : R20 : out* +NOTE PINS o_PMU_OC_3[5] : P19 : out* +NOTE PINS o_PMU_OC_3[4] : N16 : out* +NOTE PINS o_PMU_OC_3[3] : U20 : out* +NOTE PINS o_PMU_OC_3[2] : W16 : out* +NOTE PINS o_PMU_OC_3[1] : AB21 : out* +NOTE PINS o_PMU_OC_3[0] : R18 : out* +NOTE PINS o_PMU_OC_2[31] : D11 : out* +NOTE PINS o_PMU_OC_2[30] : E10 : out* +NOTE PINS o_PMU_OC_2[29] : E9 : out* +NOTE PINS o_PMU_OC_2[28] : E8 : out* +NOTE PINS o_PMU_OC_2[27] : T6 : out* +NOTE PINS o_PMU_OC_2[26] : W5 : out* +NOTE PINS o_PMU_OC_2[25] : U5 : out* +NOTE PINS o_PMU_OC_2[24] : T7 : out* +NOTE PINS o_PMU_OC_2[23] : M16 : out* +NOTE PINS o_PMU_OC_2[22] : M17 : out* +NOTE PINS o_PMU_OC_2[21] : N20 : out* +NOTE PINS o_PMU_OC_2[20] : R22 : out* +NOTE PINS o_PMU_OC_2[19] : Y13 : out* +NOTE PINS o_PMU_OC_2[18] : P20 : out* +NOTE PINS o_PMU_OC_2[17] : M19 : out* +NOTE PINS o_PMU_OC_2[16] : B8 : out* +NOTE PINS o_PMU_OC_2[15] : H3 : out* +NOTE PINS o_PMU_OC_2[14] : H2 : out* +NOTE PINS o_PMU_OC_2[13] : H6 : out* +NOTE PINS o_PMU_OC_2[12] : H5 : out* +NOTE PINS o_PMU_OC_2[11] : B1 : out* +NOTE PINS o_PMU_OC_2[10] : C3 : out* +NOTE PINS o_PMU_OC_2[9] : C2 : out* +NOTE PINS o_PMU_OC_2[8] : C1 : out* +NOTE PINS o_PMU_OC_2[7] : B10 : out* +NOTE PINS o_PMU_OC_2[6] : M18 : out* +NOTE PINS o_PMU_OC_2[5] : P21 : out* +NOTE PINS o_PMU_OC_2[4] : N21 : out* +NOTE PINS o_PMU_OC_2[3] : F11 : out* +NOTE PINS o_PMU_OC_2[2] : Y16 : out* +NOTE PINS o_PMU_OC_2[1] : AB15 : out* +NOTE PINS o_PMU_OC_2[0] : N17 : out* +NOTE PINS o_PMU_OC_1[31] : U4 : out* +NOTE PINS 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+RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_4 +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0_COUT[9] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0_S0[0] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1 +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s_0_S1[5] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s_0_COUT[5] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0_S0[0] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2 +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s_0_S1[5] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s_0_COUT[5] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/VCC +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/GND +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[4] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/te_precnt_cry_0_S0[0] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/N_1 +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/te_precnt_s_0_S1[15] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/te_precnt_s_0_COUT[15] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/genblk1.te_tt_dist_ram/mem_0_0/DO2 +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/genblk1.te_tt_dist_ram/mem_0_0/DO3 +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/mem_0_0/DO2 +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/mem_0_0/DO3 +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0_S0[0] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_1 +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s_0_S1[15] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s_0_COUT[15] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[3] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu_0[3] +CPLD_Con_2/un1_delay_cnt_1_s_15_0_S1 +CPLD_Con_2/un1_delay_cnt_1_s_15_0_COUT +CPLD_Con_2/un1_delay_cnt_1_cry_0_0_S1 +CPLD_Con_2/un1_delay_cnt_1_cry_0_0_S0 +CPLD_Con_2/N_10 +[ END CLIPPED ] +[ START DESIGN PREFS ] +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.14.0.75.2 -- WARNING: Map write only section -- Tue May 26 15:49:45 2026 + +SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; +LOCATE COMP "i_sys_clk" SITE "B9" ; +LOCATE COMP "o_PMU_OC_4[31]" SITE "A3" ; +LOCATE COMP "o_PMU_OC_4[30]" SITE "B3" ; +LOCATE COMP "o_PMU_OC_4[29]" SITE "A2" ; +LOCATE COMP "o_PMU_OC_4[28]" SITE "C11" ; +LOCATE COMP "o_PMU_OC_4[27]" SITE "D3" ; +LOCATE COMP "o_PMU_OC_4[26]" SITE "E2" ; +LOCATE COMP "o_PMU_OC_4[25]" SITE "D1" ; +LOCATE COMP "o_PMU_OC_4[24]" SITE "E1" ; +LOCATE COMP "o_PMU_OC_4[15]" SITE "E11" ; +LOCATE COMP "o_PMU_OC_4[14]" SITE "G11" ; +LOCATE COMP "o_PMU_OC_4[13]" SITE "C5" ; +LOCATE COMP "o_PMU_OC_4[12]" SITE "C4" ; +LOCATE COMP "o_PMU_OC_4[11]" SITE "F1" ; +LOCATE COMP "o_PMU_OC_4[10]" SITE "G3" ; +LOCATE COMP "o_PMU_OC_4[9]" SITE "G2" ; +LOCATE COMP "o_PMU_OC_4[8]" SITE "G1" ; +LOCATE COMP "o_PMU_OC_3[31]" SITE "D21" ; +LOCATE COMP "o_PMU_OC_3[30]" SITE "E20" ; +LOCATE COMP "o_PMU_OC_3[29]" SITE "E22" ; +LOCATE COMP "o_PMU_OC_3[28]" SITE "G21" ; +LOCATE COMP "o_PMU_OC_3[27]" SITE "C15" ; +LOCATE COMP "o_PMU_OC_3[26]" SITE "B15" ; +LOCATE COMP "o_PMU_OC_3[25]" SITE "B14" ; +LOCATE COMP "o_PMU_OC_3[24]" SITE "B13" ; +LOCATE COMP "o_PMU_OC_3[15]" SITE "B16" ; +LOCATE COMP "o_PMU_OC_3[14]" SITE "A17" ; +LOCATE COMP "o_PMU_OC_3[13]" SITE "C18" ; +LOCATE COMP "o_PMU_OC_3[12]" SITE "B19" ; +LOCATE COMP "o_PMU_OC_3[11]" SITE "A13" ; +LOCATE COMP "o_PMU_OC_3[10]" SITE "B12" ; +LOCATE COMP "o_PMU_OC_3[9]" SITE "A12" ; +LOCATE COMP "o_PMU_OC_3[8]" SITE "A11" ; +LOCATE COMP "o_PMU_OC_2[31]" SITE "D11" ; +LOCATE COMP "o_PMU_OC_2[30]" SITE "E10" ; +LOCATE COMP "o_PMU_OC_2[29]" SITE "E9" ; +LOCATE COMP "o_PMU_OC_2[28]" SITE "E8" ; +LOCATE COMP "o_PMU_OC_2[27]" SITE "T6" ; +LOCATE COMP "o_PMU_OC_2[26]" SITE "W5" ; +LOCATE COMP "o_PMU_OC_2[25]" SITE "U5" ; +LOCATE COMP "o_PMU_OC_2[24]" SITE "T7" ; +LOCATE COMP "o_PMU_OC_2[15]" SITE "H3" ; +LOCATE COMP "o_PMU_OC_2[14]" SITE "H2" ; +LOCATE COMP "o_PMU_OC_2[13]" SITE "H6" ; +LOCATE COMP "o_PMU_OC_2[12]" SITE "H5" ; +LOCATE COMP "o_PMU_OC_2[11]" SITE "B1" ; +LOCATE COMP "o_PMU_OC_2[10]" SITE "C3" ; +LOCATE COMP "o_PMU_OC_2[9]" SITE "C2" ; +LOCATE COMP "o_PMU_OC_2[8]" SITE "C1" ; +LOCATE COMP "o_PMU_OC_1[31]" SITE "U4" ; +LOCATE COMP "o_PMU_OC_1[30]" SITE "P6" ; +LOCATE COMP "o_PMU_OC_1[29]" SITE "T5" ; +LOCATE COMP "o_PMU_OC_1[28]" SITE "R6" ; +LOCATE COMP "o_PMU_OC_1[27]" SITE "M4" ; +LOCATE COMP "o_PMU_OC_1[26]" SITE "P3" ; +LOCATE COMP "o_PMU_OC_1[25]" SITE "D15" ; +LOCATE COMP "o_PMU_OC_1[24]" SITE "N5" ; +LOCATE COMP "o_PMU_OC_1[15]" SITE "E17" ; +LOCATE COMP "o_PMU_OC_1[14]" SITE "D17" ; +LOCATE COMP "o_PMU_OC_1[13]" SITE "F17" ; +LOCATE COMP "o_PMU_OC_1[12]" SITE "C17" ; +LOCATE COMP "o_PMU_OC_1[11]" SITE "F13" ; +LOCATE COMP "o_PMU_OC_1[10]" SITE "C13" ; +LOCATE COMP "o_PMU_OC_1[9]" SITE "G13" ; +LOCATE COMP "o_PMU_OC_1[8]" SITE "D14" ; +LOCATE COMP "o_RC_T[25]" SITE "AA13" ; +LOCATE COMP "o_RC_T[24]" SITE "T13" ; +LOCATE COMP "o_RC_T[23]" SITE "U15" ; +LOCATE COMP "o_RC_T[22]" SITE "T15" ; +LOCATE COMP "o_RC_T[21]" SITE "Y17" ; +LOCATE COMP "o_RC_T[20]" SITE "W17" ; +LOCATE COMP "o_RC_T[19]" SITE "W19" ; +LOCATE COMP "o_RC_T[18]" SITE "AB20" ; +LOCATE COMP "o_RC_T[17]" SITE "AA19" ; +LOCATE COMP "o_RC_T[16]" SITE "Y18" ; +LOCATE COMP "o_RC_T[15]" SITE "AB17" ; +LOCATE COMP "o_RC_T[14]" SITE "V16" ; +LOCATE COMP "o_RC_T[13]" SITE "V14" ; +LOCATE COMP "o_RC_T[12]" SITE "V13" ; +LOCATE COMP "o_RC_T[11]" SITE "Y12" ; +LOCATE COMP "o_RC_T[10]" SITE "W12" ; +LOCATE COMP "o_RC_T[9]" SITE "V12" ; +LOCATE COMP "o_RC_T[8]" SITE "V8" ; +LOCATE COMP "o_RC_T[7]" SITE "AB13" ; +LOCATE COMP "o_RC_T[6]" SITE "AA12" ; +LOCATE COMP "o_RC_T[5]" SITE "AB11" ; +LOCATE COMP "o_RC_T[4]" SITE "AA11" ; +LOCATE COMP "o_RC_T[3]" SITE "AA10" ; +LOCATE COMP "o_RC_T[2]" SITE "AB10" ; +LOCATE COMP "o_RC_T[1]" SITE "Y10" ; +LOCATE COMP "o_RC_T[0]" SITE "AA8" ; +LOCATE COMP "o_RC_S[15]" SITE "AA7" ; +LOCATE COMP "o_RC_S[14]" SITE "AB7" ; +LOCATE COMP "o_RC_S[13]" SITE "Y7" ; +LOCATE COMP "o_RC_S[12]" SITE "Y6" ; +LOCATE COMP "o_RC_S[11]" SITE "AB6" ; +LOCATE COMP "o_RC_S[10]" SITE "AB5" ; +LOCATE COMP "o_RC_S[9]" SITE "W6" ; +LOCATE COMP "o_RC_S[8]" SITE "Y5" ; +LOCATE COMP "o_RC_S[7]" SITE "AA4" ; +LOCATE COMP "o_RC_S[6]" SITE "Y4" ; +LOCATE COMP "o_RC_S[5]" SITE "AB3" ; +LOCATE COMP "o_RC_S[4]" SITE "AA3" ; +LOCATE COMP "o_RC_S[3]" SITE "Y3" ; +LOCATE COMP "o_RC_S[2]" SITE "AB2" ; +LOCATE COMP "o_RC_S[1]" SITE "W9" ; +LOCATE COMP "o_RC_S[0]" SITE "T10" ; +LOCATE COMP "o_RC_F[7]" SITE "U10" ; +LOCATE COMP "o_RC_F[6]" SITE "W11" ; +LOCATE COMP "o_RC_F[5]" SITE "V11" ; +LOCATE COMP "o_RC_F[4]" SITE "U11" ; +LOCATE COMP "o_RC_F[3]" SITE "T11" ; +LOCATE COMP "o_RC_F[2]" SITE "T12" ; +LOCATE COMP "o_RC_F[1]" SITE "U12" ; +LOCATE COMP "o_RC_F[0]" SITE "U13" ; +LOCATE COMP "o_err" SITE "AB16" ; +LOCATE COMP "i_cs" SITE "Y15" ; +LOCATE COMP "i_mosi" SITE "AB12" ; +LOCATE COMP "i_sclk" SITE "AA16" ; +LOCATE COMP "i_rst_n" SITE "Y14" ; +USE PRIMARY NET "i_sys_clk_c" ; +SCHEMATIC END ; +[ END DESIGN PREFS ] diff --git a/CPLD2/impl1/NewExtIns_CPLD2_impl1_map.hrr b/CPLD2/impl1/NewExtIns_CPLD2_impl1_map.hrr new file mode 100644 index 0000000..72ae6ec --- /dev/null +++ b/CPLD2/impl1/NewExtIns_CPLD2_impl1_map.hrr @@ -0,0 +1,209 @@ +--------------------------------------------------- +Report for cell RelayConTop + Instance path: RelayConTop + Cell usage: + cell count Res Usage(%) + SLIC 760.00 100.0 + IOLGC 142.00 100.0 + LUT4 1344.00 100.0 + DISTRAM 6.00 100.0 + IOREG 142 100.0 + IOBUF 187 100.0 + PFUREG 1190 100.0 + RIPPLE 76 100.0 + EBR 10 100.0 +SUB MODULES + cell count SLC Usage(%) + xo2chub 1 3.2 + reveal_coretop 1 42.6 + Reg_file_uniq_1 1 28.8 + CPLD_Con_uniq_1 1 17.3 + BUS_Con_uniq_1 1 8.1 +--------------------------------------------------- +Report for cell CPLD_Con_uniq_1 + Instance path: RelayConTop/CPLD_Con_2 + Cell usage: + cell count Res Usage(%) + SLIC 131.50 17.3 + LUT4 340.00 25.3 + PFUREG 82 6.9 + RIPPLE 9 11.8 +--------------------------------------------------- +Report for cell Reg_file_uniq_1 + Instance path: RelayConTop/CPLD_Reg_2 + Cell usage: + cell count Res Usage(%) + SLIC 218.58 28.8 + LUT4 250.00 18.6 + PFUREG 417 35.0 +--------------------------------------------------- +Report for cell BUS_Con_uniq_1 + Instance path: RelayConTop/BUS_Con_2 + Cell usage: + cell count Res Usage(%) + SLIC 61.75 8.1 + LUT4 96.00 7.1 + PFUREG 144 12.1 +--------------------------------------------------- +Report for cell reveal_coretop + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance + Cell usage: + cell count Res Usage(%) + SLIC 323.42 42.6 + LUT4 645.00 48.0 + DISTRAM 4.00 66.7 + PFUREG 495 41.6 + RIPPLE 50 65.8 + EBR 10 100.0 +SUB MODULES + cell count SLC Usage(%) + relaycontop_la0 1 42.6 +--------------------------------------------------- +Report for cell relaycontop_la0 + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0 + Cell usage: + cell count Res Usage(%) + SLIC 323.42 42.6 + LUT4 645.00 48.0 + DISTRAM 4.00 66.7 + PFUREG 495 41.6 + RIPPLE 50 65.8 + EBR 10 100.0 +SUB MODULES + cell count SLC Usage(%) + rvl_tm_Z3 1 15.6 + rvl_jtag_int_42s_2s_0s_0s_6s_42s_42s 1 14.4 + relaycontop_la0_trig 1 12.5 +--------------------------------------------------- +Report for cell relaycontop_la0_trig + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u + Cell usage: + cell count Res Usage(%) + SLIC 95.13 12.5 + LUT4 189.00 14.1 + DISTRAM 4.00 66.7 + PFUREG 118 9.9 + RIPPLE 18 23.7 +SUB MODULES + cell count SLC Usage(%) + rvl_tu_1s_0s_0s_0s_1s_2 1 0.8 + rvl_tu_1s_0s_0s_0s_1s_1 1 0.8 + rvl_tcnt_2s_3s_1_0s 1 1.3 + rvl_te_Z1_0 1 4.0 + rvl_te_Z1_1 1 4.8 + rvl_decode_2s_2s 1 0.4 +--------------------------------------------------- +Report for cell rvl_decode_2s_2s + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u + Cell usage: + cell count Res Usage(%) + SLIC 3.10 0.4 + LUT4 12.50 0.9 +--------------------------------------------------- +Report for cell rvl_tu_1s_0s_0s_0s_1s_2 + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0 + Cell usage: + cell count Res Usage(%) + SLIC 6.08 0.8 + LUT4 11.00 0.8 + PFUREG 8 0.7 +--------------------------------------------------- +Report for cell rvl_tu_1s_0s_0s_0s_1s_1 + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_1 + Cell usage: + cell count Res Usage(%) + SLIC 6.18 0.8 + LUT4 12.00 0.9 + PFUREG 8 0.7 +--------------------------------------------------- +Report for cell rvl_te_Z1_1 + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0 + Cell usage: + cell count Res Usage(%) + SLIC 36.20 4.8 + LUT4 69.50 5.2 + DISTRAM 2.00 33.3 + PFUREG 53 4.5 + RIPPLE 9 11.8 +SUB MODULES + cell count SLC Usage(%) +pmi_distributed_dpramXbnoner224pb08036b 1 0.3 +--------------------------------------------------- +Report for cell pmi_distributed_dpramXbnoner224pb08036b + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram + Cell usage: + cell count Res Usage(%) + SLIC 2.25 0.3 + LUT4 1.00 0.1 + DISTRAM 2.00 33.3 + PFUREG 2 0.2 +--------------------------------------------------- +Report for cell rvl_te_Z1_0 + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1 + Cell usage: + cell count Res Usage(%) + SLIC 30.33 4.0 + LUT4 53.00 3.9 + DISTRAM 2.00 33.3 + PFUREG 36 3.0 + RIPPLE 9 11.8 +SUB MODULES + cell count SLC Usage(%) +pmi_distributed_dpramXbnoner224pb08036b_0 1 0.3 +--------------------------------------------------- +Report for cell pmi_distributed_dpramXbnoner224pb08036b_0 + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/genblk1.te_tt_dist_ram + Cell usage: + cell count Res Usage(%) + SLIC 2.25 0.3 + LUT4 1.00 0.1 + DISTRAM 2.00 33.3 + PFUREG 2 0.2 +--------------------------------------------------- +Report for cell rvl_tcnt_2s_3s_1_0s + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0 + Cell usage: + cell count Res Usage(%) + SLIC 9.73 1.3 + LUT4 22.00 1.6 + PFUREG 13 1.1 +--------------------------------------------------- +Report for cell rvl_jtag_int_42s_2s_0s_0s_6s_42s_42s + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u + Cell usage: + cell count Res Usage(%) + SLIC 109.27 14.4 + LUT4 249.50 18.6 + PFUREG 168 14.1 + RIPPLE 8 10.5 +--------------------------------------------------- +Report for cell rvl_tm_Z3 + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u + Cell usage: + cell count Res Usage(%) + SLIC 118.57 15.6 + LUT4 205.00 15.3 + PFUREG 209 17.6 + RIPPLE 24 31.6 + EBR 10 100.0 +SUB MODULES + cell count SLC Usage(%) +pmi_ram_dpXbnonesadr4211204842112048p1395c895 1 1.4 +--------------------------------------------------- +Report for cell pmi_ram_dpXbnonesadr4211204842112048p1395c895 + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem + Cell usage: + cell count Res Usage(%) + SLIC 11.00 1.4 + LUT4 42.00 3.1 + PFUREG 2 0.2 + EBR 10 100.0 +--------------------------------------------------- +Report for cell xo2chub + Instance path: RelayConTop/xo2chub + Cell usage: + cell count Res Usage(%) + SLIC 24.25 3.2 + LUT4 12.00 0.9 + PFUREG 51 4.3 + RIPPLE 17 22.4 diff --git a/CPLD2/impl1/NewExtIns_CPLD2_impl1_synplify.lpf b/CPLD2/impl1/NewExtIns_CPLD2_impl1_synplify.lpf new file mode 100644 index 0000000..23af319 --- /dev/null +++ b/CPLD2/impl1/NewExtIns_CPLD2_impl1_synplify.lpf @@ -0,0 +1,26 @@ +# +# Logical Preferences generated for Lattice by Synplify map202309lat, Build 191R. +# + +# Period Constraints +#FREQUENCY NET "RelayConTop_reveal_coretop_instance/jtck[0]" 200.0 MHz; +#FREQUENCY PORT "i_sys_clk" 200.0 MHz; + + +# Output Constraints + +# Input Constraints + +# Point-to-point Delay Constraints + + + +# Block Path Constraints +#BLOCK PATH FROM CLKNET "i_sys_clk_c" TO CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]"; +#BLOCK PATH FROM CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]" TO CLKNET "i_sys_clk_c"; +#BLOCK PATH FROM CLKNET "i_sys_clk_c" TO CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]"; +#BLOCK PATH FROM CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]" TO CLKNET "i_sys_clk_c"; + +BLOCK ASYNCPATHS; + +# End of generated Logical Preferences. diff --git a/CPLD2/impl1/NewExtIns_CPLD2_impl1_synplify_tmp2.lpf b/CPLD2/impl1/NewExtIns_CPLD2_impl1_synplify_tmp2.lpf new file mode 100644 index 0000000..e69de29 diff --git a/CPLD2/impl1/NewExtIns_CPLD2_impl1_synplify_tmp4.lpf b/CPLD2/impl1/NewExtIns_CPLD2_impl1_synplify_tmp4.lpf new file mode 100644 index 0000000..e69de29 diff --git a/CPLD2/impl1/NewExtIns_CPLD2_impl1_synplify_tmp8.lpf b/CPLD2/impl1/NewExtIns_CPLD2_impl1_synplify_tmp8.lpf new file mode 100644 index 0000000..e69de29 diff --git a/CPLD2/impl1/_cmd._cml b/CPLD2/impl1/_cmd._cml new file mode 100644 index 0000000..0c44226 --- /dev/null +++ b/CPLD2/impl1/_cmd._cml @@ -0,0 +1 @@ +-link -encrypt -top RelayConTop -osyn /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD2/impl1/synwork/NewExtIns_CPLD2_impl1_comp.srs /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD2/impl1/synwork/layer0.srs -jobname linker \ No newline at end of file diff --git a/CPLD2/impl1/impl1.xcf b/CPLD2/impl1/impl1.xcf new file mode 100644 index 0000000..b253682 --- /dev/null +++ b/CPLD2/impl1/impl1.xcf @@ -0,0 +1,52 @@ + + + + + + JTAG + + + 1 + Lattice + MachXO2 + LCMXO2-7000HC + 0x012bd043 + All + LCMXO2-7000HC + + 8 + 11111111 + 1 + 0 + + D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD2/impl1/NewExtIns_CPLD2_impl1.jed + 01/20/26 16:01:30 + 0x566E + FLASH Erase,Program,Verify + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB + EzUSB-0 + \\?\usb#vid_1134&pid_8001#9&2fe42d87&0&2# + + diff --git a/CPLD2/impl1/pmi_distributed_dpramXbnoner224pb08036b.edn b/CPLD2/impl1/pmi_distributed_dpramXbnoner224pb08036b.edn new file mode 100644 index 0000000..dba12b1 --- /dev/null +++ b/CPLD2/impl1/pmi_distributed_dpramXbnoner224pb08036b.edn @@ -0,0 +1,233 @@ +(edif pmi_distributed_dpramXbnoner224pb08036b + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 5 26 15 49 44) + (program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2")))) + (comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 4 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner224pb08036b -pmi ") + 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b/CPLD2/impl1/pmi_distributed_dpramXbnoner238pb0819f2_1.edn new file mode 100644 index 0000000..abc071a --- /dev/null +++ b/CPLD2/impl1/pmi_distributed_dpramXbnoner238pb0819f2_1.edn @@ -0,0 +1,239 @@ +(edif pmi_distributed_dpramXbnoner238pb0819f2_1 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 5 15 18 6 2) + (program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2")))) + (comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 8 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner238pb0819f2_1 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell ROM16X1A + (cellType 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(string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr100112048100112048p13b98964__PMIP__2048__100__100__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + 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(property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr100112048100112048p13b98964__PMIP__2048__100__100__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr100112048100112048p13b98964__PMIP__2048__100__100__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr100112048100112048p13b98964__PMIP__2048__100__100__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr100112048100112048p13b98964__PMIP__2048__100__100__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr100112048100112048p13b98964__PMIP__2048__100__100__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string 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REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr100112048100112048p13b98964__PMIP__2048__100__100__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10 + (viewRef view1 + (cellRef DP8KC)) + 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MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef DIB8 (instanceRef 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pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net raddr7 + (joined + (portRef (member RdAddress 3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))))))) + (design pmi_ram_dpXbnonesadr100112048100112048p13b98964 + (cellRef pmi_ram_dpXbnonesadr100112048100112048p13b98964 + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr101112048101112048p13b9937e.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr101112048101112048p13b9937e.edn new file mode 100644 index 0000000..c0f3c30 --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr101112048101112048p13b9937e.edn @@ -0,0 +1,4470 @@ +(edif pmi_ram_dpXbnonesadr101112048101112048p13b9937e + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 5 15 18 6 2) + (program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2")))) + (comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 101 -num_rows 2048 -rdata_width 101 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr101112048101112048p13b9937e -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr101112048101112048p13b9937e + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(100:0)") 101) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(100:0)") 101) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property 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+ (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance 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(instance mux_47 + (viewRef view1 + (cellRef MUX21))) + (instance mux_46 + (viewRef view1 + (cellRef MUX21))) + (instance mux_45 + (viewRef view1 + (cellRef MUX21))) + (instance mux_44 + (viewRef view1 + (cellRef MUX21))) + (instance mux_43 + (viewRef view1 + (cellRef MUX21))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef DIB0 (instanceRef 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(net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))))))) + (design pmi_ram_dpXbnonesadr101112048101112048p13b9937e + (cellRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b.edn new file mode 100644 index 0000000..065326a --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b.edn @@ -0,0 +1,4527 @@ +(edif pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 14 14 21 25) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 104 -num_rows 2048 -rdata_width 104 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view 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(cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_103 + (viewRef view1 + (cellRef MUX21))) + (instance mux_102 + (viewRef view1 + (cellRef MUX21))) + (instance mux_101 + (viewRef view1 + (cellRef MUX21))) + (instance mux_100 + (viewRef view1 + (cellRef MUX21))) + (instance mux_99 + (viewRef view1 + (cellRef MUX21))) + (instance mux_98 + (viewRef view1 + (cellRef MUX21))) + (instance mux_97 + (viewRef view1 + (cellRef MUX21))) + (instance mux_96 + (viewRef view1 + (cellRef MUX21))) + (instance mux_95 + (viewRef view1 + (cellRef MUX21))) + (instance mux_94 + (viewRef view1 + (cellRef MUX21))) + (instance mux_93 + (viewRef view1 + (cellRef MUX21))) + (instance mux_92 + (viewRef view1 + (cellRef MUX21))) + (instance mux_91 + (viewRef view1 + (cellRef MUX21))) + (instance mux_90 + (viewRef view1 + (cellRef MUX21))) + (instance mux_89 + (viewRef view1 + (cellRef MUX21))) + (instance mux_88 + (viewRef view1 + (cellRef MUX21))) + (instance mux_87 + (viewRef view1 + (cellRef MUX21))) + (instance mux_86 + (viewRef view1 + (cellRef MUX21))) + (instance mux_85 + (viewRef view1 + (cellRef MUX21))) + (instance mux_84 + (viewRef view1 + (cellRef MUX21))) + (instance mux_83 + (viewRef view1 + (cellRef MUX21))) + (instance mux_82 + (viewRef view1 + (cellRef MUX21))) + (instance mux_81 + (viewRef view1 + (cellRef MUX21))) + (instance mux_80 + (viewRef view1 + (cellRef MUX21))) + (instance mux_79 + (viewRef view1 + (cellRef MUX21))) + (instance mux_78 + (viewRef view1 + (cellRef MUX21))) + (instance mux_77 + (viewRef view1 + (cellRef MUX21))) + (instance mux_76 + (viewRef view1 + (cellRef MUX21))) + (instance mux_75 + (viewRef view1 + (cellRef MUX21))) + (instance mux_74 + (viewRef view1 + (cellRef MUX21))) + (instance mux_73 + (viewRef view1 + (cellRef MUX21))) + (instance mux_72 + (viewRef view1 + (cellRef MUX21))) + (instance mux_71 + (viewRef view1 + (cellRef MUX21))) + (instance mux_70 + (viewRef view1 + (cellRef MUX21))) + (instance mux_69 + (viewRef view1 + (cellRef MUX21))) + (instance mux_68 + (viewRef view1 + (cellRef MUX21))) + (instance mux_67 + (viewRef view1 + (cellRef MUX21))) + (instance mux_66 + (viewRef view1 + (cellRef MUX21))) + (instance mux_65 + (viewRef view1 + (cellRef MUX21))) + (instance mux_64 + (viewRef view1 + (cellRef MUX21))) + (instance mux_63 + (viewRef view1 + (cellRef MUX21))) + (instance mux_62 + (viewRef view1 + (cellRef MUX21))) + (instance mux_61 + (viewRef view1 + (cellRef MUX21))) + (instance mux_60 + (viewRef view1 + (cellRef MUX21))) + (instance mux_59 + (viewRef view1 + (cellRef MUX21))) + (instance mux_58 + (viewRef view1 + (cellRef MUX21))) + (instance mux_57 + (viewRef view1 + (cellRef MUX21))) + (instance mux_56 + (viewRef view1 + (cellRef MUX21))) + (instance mux_55 + (viewRef view1 + (cellRef MUX21))) + (instance mux_54 + (viewRef view1 + (cellRef MUX21))) + (instance mux_53 + (viewRef view1 + (cellRef MUX21))) + (instance mux_52 + (viewRef view1 + (cellRef MUX21))) + (instance mux_51 + (viewRef view1 + (cellRef MUX21))) + (instance mux_50 + (viewRef view1 + (cellRef MUX21))) + (instance mux_49 + (viewRef view1 + (cellRef MUX21))) + (instance mux_48 + (viewRef view1 + (cellRef MUX21))) + (instance mux_47 + (viewRef view1 + (cellRef MUX21))) + (instance mux_46 + (viewRef view1 + (cellRef MUX21))) + (instance mux_45 + (viewRef view1 + (cellRef MUX21))) + (instance mux_44 + (viewRef view1 + (cellRef MUX21))) + (instance mux_43 + (viewRef view1 + (cellRef MUX21))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef DIB6 (instanceRef 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pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef DIB6 (instanceRef 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(instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))))))) + (design pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b + (cellRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr105101024105101024p13b96f61.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr105101024105101024p13b96f61.edn new file mode 100644 index 0000000..083860c --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr105101024105101024p13b96f61.edn @@ -0,0 +1,2136 @@ +(edif pmi_ram_dpXbnonesadr105101024105101024p13b96f61 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 15 14 33 36) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 105 -num_rows 1024 -rdata_width 105 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr105101024105101024p13b96f61 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr105101024105101024p13b96f61 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(9:0)") 10) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(9:0)") 10) + (direction INPUT)) + (port (array (rename Data "Data(104:0)") 105) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(104:0)") 105) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr105101024105101024p13b96f61__PMIP__1024__105__105__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr105101024105101024p13b96f61__PMIP__1024__105__105__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr105101024105101024p13b96f61__PMIP__1024__105__105__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr105101024105101024p13b96f61__PMIP__1024__105__105__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr105101024105101024p13b96f61__PMIP__1024__105__105__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr105101024105101024p13b96f61__PMIP__1024__105__105__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr105101024105101024p13b96f61__PMIP__1024__105__105__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr105101024105101024p13b96f61__PMIP__1024__105__105__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr105101024105101024p13b96f61__PMIP__1024__105__105__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr105101024105101024p13b96f61__PMIP__1024__105__105__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr105101024105101024p13b96f61__PMIP__1024__105__105__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr105101024105101024p13b96f61__PMIP__1024__105__105__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef ADB2 (instanceRef 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pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)))) + (net WrClockEn + (joined + (portRef WrClockEn) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)))) + (net clk + (joined + (portRef WrClock) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef CLKA (instanceRef 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pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)))) + (net RdClockEn + (joined + (portRef RdClockEn) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef OCEB (instanceRef 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(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 0)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_0_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_1_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_2_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_3_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_4_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_5_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_6_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_7_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_8_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_9_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_10_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61_0_11_0)))))))) + (design pmi_ram_dpXbnonesadr105101024105101024p13b96f61 + (cellRef pmi_ram_dpXbnonesadr105101024105101024p13b96f61 + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr3411204834112048p1395d432.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr3411204834112048p1395d432.edn new file mode 100644 index 0000000..7af1353 --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr3411204834112048p1395d432.edn @@ -0,0 +1,1741 @@ +(edif pmi_ram_dpXbnonesadr3411204834112048p1395d432 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 14 17 10 39) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 34 -num_rows 2048 -rdata_width 34 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr3411204834112048p1395d432 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr3411204834112048p1395d432 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(33:0)") 34) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(33:0)") 34) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3411204834112048p1395d432__PMIP__2048__34__34__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3411204834112048p1395d432__PMIP__2048__34__34__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3411204834112048p1395d432__PMIP__2048__34__34__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3411204834112048p1395d432__PMIP__2048__34__34__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3411204834112048p1395d432__PMIP__2048__34__34__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3411204834112048p1395d432__PMIP__2048__34__34__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3411204834112048p1395d432__PMIP__2048__34__34__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3411204834112048p1395d432__PMIP__2048__34__34__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef CD (instanceRef FF_1)) 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pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef SP (instanceRef FF_1)) + (portRef SP (instanceRef FF_0)))) + (net rdclk + (joined + (portRef RdClock) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef CK (instanceRef FF_1)) + (portRef CK (instanceRef FF_0)))) + (net wren + (joined + (portRef WE) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef WEA (instanceRef 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pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)))) + (net datain25 + (joined + (portRef (member Data 8)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)))) + (net datain24 + (joined + (portRef (member Data 9)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)))) + (net datain23 + (joined + (portRef (member Data 10)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)))) + (net datain22 + (joined + (portRef (member Data 11)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)))) + (net datain21 + (joined + (portRef (member Data 12)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)))) + (net datain20 + (joined + (portRef (member Data 13)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)))) + (net datain19 + (joined + (portRef (member Data 14)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)))) + (net datain18 + (joined + (portRef (member Data 15)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)))) + (net datain17 + (joined + (portRef (member Data 16)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)))) + (net datain16 + (joined + (portRef (member Data 17)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)))) + (net datain15 + (joined + (portRef (member Data 18)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)))) + (net datain14 + (joined + (portRef (member Data 19)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)))) + (net datain13 + (joined + (portRef (member Data 20)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)))) + (net datain12 + (joined + (portRef (member Data 21)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)))) + (net datain11 + (joined + (portRef (member Data 22)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)))) + (net datain10 + (joined + (portRef (member Data 23)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)))) + (net datain9 + (joined + (portRef (member Data 24)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)))) + (net datain8 + (joined + (portRef (member Data 25)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)))) + (net datain7 + (joined + (portRef (member Data 26)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)))) + (net datain6 + (joined + (portRef (member Data 27)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)))) + (net datain5 + (joined + (portRef (member Data 28)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)))) + (net datain4 + (joined + (portRef (member Data 29)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)))) + (net datain3 + (joined + (portRef (member Data 30)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)))) + (net datain2 + (joined + (portRef (member Data 31)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)))) + (net datain1 + (joined + (portRef (member Data 32)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)))) + (net datain0 + (joined + (portRef (member Data 33)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)))) + (net raddr10 + (joined + (portRef (member RdAddress 0)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)) + (portRef D (instanceRef FF_1)))) + (net raddr9 + (joined + (portRef (member RdAddress 1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))) + (net raddr8 + (joined + (portRef (member RdAddress 2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))) + (net raddr7 + (joined + (portRef (member RdAddress 3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_0_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_1_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_2_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_0_3_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_0_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_1_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_2_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3411204834112048p1395d432_1_3_0)))))))) + (design pmi_ram_dpXbnonesadr3411204834112048p1395d432 + (cellRef pmi_ram_dpXbnonesadr3411204834112048p1395d432 + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr3811204838112048p1395f327.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr3811204838112048p1395f327.edn new file mode 100644 index 0000000..098463a --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr3811204838112048p1395f327.edn @@ -0,0 +1,1491 @@ +(edif pmi_ram_dpXbnonesadr3811204838112048p1395f327 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 5 25 11 22 52) + (program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2")))) + (comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 38 -num_rows 2048 -rdata_width 38 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr3811204838112048p1395f327 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr3811204838112048p1395f327 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(37:0)") 38) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(37:0)") 38) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) 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pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net Reset + (joined + (portRef Reset) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net RdClockEn + (joined + (portRef RdClockEn) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net rdclk + (joined + (portRef RdClock) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net wren + (joined + (portRef WE) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net datain37 + (joined + (portRef (member Data 0)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net datain36 + (joined + (portRef (member Data 1)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net datain35 + (joined + (portRef (member Data 2)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)))) + (net datain34 + (joined + (portRef (member Data 3)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)))) + (net datain33 + (joined + (portRef (member Data 4)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)))) + (net datain32 + (joined + (portRef (member Data 5)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)))) + (net datain31 + (joined + (portRef (member Data 6)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)))) + (net datain30 + (joined + (portRef (member Data 7)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)))) + (net datain29 + (joined + (portRef (member Data 8)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)))) + (net datain28 + (joined + (portRef (member Data 9)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)))) + (net datain27 + (joined + (portRef (member Data 10)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)))) + (net datain26 + (joined + (portRef (member Data 11)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)))) + (net datain25 + (joined + (portRef (member Data 12)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)))) + (net datain24 + (joined + (portRef (member Data 13)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)))) + (net datain23 + (joined + (portRef (member Data 14)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)))) + (net datain22 + (joined + (portRef (member Data 15)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)))) + (net datain21 + (joined + (portRef (member Data 16)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)))) + (net datain20 + (joined + (portRef (member Data 17)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)))) + (net datain19 + (joined + (portRef (member Data 18)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)))) + (net datain18 + (joined + (portRef (member Data 19)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)))) + (net datain17 + (joined + (portRef (member Data 20)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)))) + (net datain16 + (joined + (portRef (member Data 21)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)))) + (net datain15 + (joined + (portRef (member Data 22)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)))) + (net datain14 + (joined + (portRef (member Data 23)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)))) + (net datain13 + (joined + (portRef (member Data 24)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)))) + (net datain12 + (joined + (portRef (member Data 25)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)))) + (net datain11 + (joined + (portRef (member Data 26)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)))) + (net datain10 + (joined + (portRef (member Data 27)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)))) + (net datain9 + (joined + (portRef (member Data 28)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)))) + (net datain8 + (joined + (portRef (member Data 29)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)))) + (net datain7 + (joined + (portRef (member Data 30)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)))) + (net datain6 + (joined + (portRef (member Data 31)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)))) + (net datain5 + (joined + (portRef (member Data 32)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)))) + (net datain4 + (joined + (portRef (member Data 33)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)))) + (net datain3 + (joined + (portRef (member Data 34)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)))) + (net datain2 + (joined + (portRef (member Data 35)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)))) + (net datain1 + (joined + (portRef (member Data 36)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)))) + (net datain0 + (joined + (portRef (member Data 37)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)))) + (net raddr10 + (joined + (portRef (member RdAddress 0)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net raddr9 + (joined + (portRef (member RdAddress 1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net raddr8 + (joined + (portRef (member RdAddress 2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net raddr7 + (joined + (portRef (member RdAddress 3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0)))))))) + (design pmi_ram_dpXbnonesadr3811204838112048p1395f327 + (cellRef pmi_ram_dpXbnonesadr3811204838112048p1395f327 + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr4011204840112048p1395baf7.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr4011204840112048p1395baf7.edn new file mode 100644 index 0000000..d62e2c7 --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr4011204840112048p1395baf7.edn @@ -0,0 +1,1505 @@ +(edif pmi_ram_dpXbnonesadr4011204840112048p1395baf7 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 14 14 25 56) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 40 -num_rows 2048 -rdata_width 40 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr4011204840112048p1395baf7 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr4011204840112048p1395baf7 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(39:0)") 40) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(39:0)") 40) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_0_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4011204840112048p1395baf7__PMIP__2048__40__40__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property 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(string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_2_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4011204840112048p1395baf7__PMIP__2048__40__40__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_3_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + 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(property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_5_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4011204840112048p1395baf7__PMIP__2048__40__40__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property 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(property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_0_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_0_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_0_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_0_9)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_0_9)) + (portRef CSA0 (instanceRef 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pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_5_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_6_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_7_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_8_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_9_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_0_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_1_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_2_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_3_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_4_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_5_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_6_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_7_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_8_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_9_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_0_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_1_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_2_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_3_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_4_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_5_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_6_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_7_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_8_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_9_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_0_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_1_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_2_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_3_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_4_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_5_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_6_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_7_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_8_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_9_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_0_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_1_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_2_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_3_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_4_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_5_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_6_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_7_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_8_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_9_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_0_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_1_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_2_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_3_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_4_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_5_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_6_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_7_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_8_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_9_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_0_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_1_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_2_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_3_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_4_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_5_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_6_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_7_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_8_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_9_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_0_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_1_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_2_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_3_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_4_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_5_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_6_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_7_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_8_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_9_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_0_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_1_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_2_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_3_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_4_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_5_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_6_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_7_2)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_8_1)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7_0_9_0)))))))) + (design pmi_ram_dpXbnonesadr4011204840112048p1395baf7 + (cellRef pmi_ram_dpXbnonesadr4011204840112048p1395baf7 + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr4211204842112048p1395c895.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr4211204842112048p1395c895.edn new file mode 100644 index 0000000..32290bd --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr4211204842112048p1395c895.edn @@ -0,0 +1,2075 @@ +(edif pmi_ram_dpXbnonesadr4211204842112048p1395c895 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 5 26 15 49 45) + (program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2")))) + (comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 42 -num_rows 2048 -rdata_width 42 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr4211204842112048p1395c895 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr4211204842112048p1395c895 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(41:0)") 42) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(41:0)") 42) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4211204842112048p1395c895__PMIP__2048__42__42__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4211204842112048p1395c895__PMIP__2048__42__42__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4211204842112048p1395c895__PMIP__2048__42__42__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4211204842112048p1395c895__PMIP__2048__42__42__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4211204842112048p1395c895__PMIP__2048__42__42__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4211204842112048p1395c895__PMIP__2048__42__42__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4211204842112048p1395c895__PMIP__2048__42__42__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_2_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4211204842112048p1395c895__PMIP__2048__42__42__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_3_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4211204842112048p1395c895__PMIP__2048__42__42__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_4_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4211204842112048p1395c895__PMIP__2048__42__42__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_2_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_3_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_4_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_2_2)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_2_2)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_2_2)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_2_2)) + (portRef WEB (instanceRef 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pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_2_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_3_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_4_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_2_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_3_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_4_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_2_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_3_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_4_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_2_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_3_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_4_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_2_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_3_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_4_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_2_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_3_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_4_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_2_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_3_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_4_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_2_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_3_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_4_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_2_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_3_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_4_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_2_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_3_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_4_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_2_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_3_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_4_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_2_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_3_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_4_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_2_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_3_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_4_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_0_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_1_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_2_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_3_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_0_4_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_0_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_1_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_2_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_3_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4211204842112048p1395c895_1_4_0)))))))) + (design pmi_ram_dpXbnonesadr4211204842112048p1395c895 + (cellRef pmi_ram_dpXbnonesadr4211204842112048p1395c895 + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr4411204844112048p1395dab9.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr4411204844112048p1395dab9.edn new file mode 100644 index 0000000..afad3eb --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr4411204844112048p1395dab9.edn @@ -0,0 +1,2113 @@ +(edif pmi_ram_dpXbnonesadr4411204844112048p1395dab9 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 14 14 30 59) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 44 -num_rows 2048 -rdata_width 44 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr4411204844112048p1395dab9 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr4411204844112048p1395dab9 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(43:0)") 44) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(43:0)") 44) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4411204844112048p1395dab9__PMIP__2048__44__44__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4411204844112048p1395dab9__PMIP__2048__44__44__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4411204844112048p1395dab9__PMIP__2048__44__44__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4411204844112048p1395dab9__PMIP__2048__44__44__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4411204844112048p1395dab9__PMIP__2048__44__44__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4411204844112048p1395dab9__PMIP__2048__44__44__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4411204844112048p1395dab9__PMIP__2048__44__44__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4411204844112048p1395dab9__PMIP__2048__44__44__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4411204844112048p1395dab9__PMIP__2048__44__44__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4411204844112048p1395dab9__PMIP__2048__44__44__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_43 + (viewRef view1 + (cellRef MUX21))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef DIB0 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(instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef WEB 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(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)))) + (net raddr10 + (joined + (portRef (member RdAddress 0)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)) + (portRef D (instanceRef FF_1)))) + (net raddr9 + (joined + (portRef (member RdAddress 1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))) + (net raddr8 + (joined + (portRef (member RdAddress 2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))) + (net raddr7 + (joined + (portRef (member RdAddress 3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_0_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_1_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_2_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_3_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_0_4_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_0_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_1_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_2_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_3_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9_1_4_0)))))))) + (design pmi_ram_dpXbnonesadr4411204844112048p1395dab9 + (cellRef pmi_ram_dpXbnonesadr4411204844112048p1395dab9 + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr4511204845112048p1395e474.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr4511204845112048p1395e474.edn new file mode 100644 index 0000000..071fe44 --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr4511204845112048p1395e474.edn @@ -0,0 +1,2132 @@ +(edif pmi_ram_dpXbnonesadr4511204845112048p1395e474 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 15 10 46 58) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 45 -num_rows 2048 -rdata_width 45 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr4511204845112048p1395e474 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr4511204845112048p1395e474 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(44:0)") 45) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(44:0)") 45) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4511204845112048p1395e474__PMIP__2048__45__45__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4511204845112048p1395e474__PMIP__2048__45__45__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4511204845112048p1395e474__PMIP__2048__45__45__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4511204845112048p1395e474__PMIP__2048__45__45__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4511204845112048p1395e474__PMIP__2048__45__45__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4511204845112048p1395e474__PMIP__2048__45__45__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4511204845112048p1395e474__PMIP__2048__45__45__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4511204845112048p1395e474__PMIP__2048__45__45__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4511204845112048p1395e474__PMIP__2048__45__45__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4511204845112048p1395e474__PMIP__2048__45__45__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_44 + (viewRef view1 + (cellRef MUX21))) + (instance mux_43 + (viewRef view1 + (cellRef MUX21))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef DIB7 (instanceRef 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pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0)))))))) + (design pmi_ram_dpXbnonesadr4511204845112048p1395e474 + (cellRef pmi_ram_dpXbnonesadr4511204845112048p1395e474 + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr4611204846112048p1395ed3e.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr4611204846112048p1395ed3e.edn new file mode 100644 index 0000000..8ee5ff8 --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr4611204846112048p1395ed3e.edn @@ -0,0 +1,1729 @@ +(edif pmi_ram_dpXbnonesadr4611204846112048p1395ed3e + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 14 16 34 54) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 46 -num_rows 2048 -rdata_width 46 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr4611204846112048p1395ed3e -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr4611204846112048p1395ed3e + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(45:0)") 46) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(45:0)") 46) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_0_11 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4611204846112048p1395ed3e__PMIP__2048__46__46__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_1_10 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4611204846112048p1395ed3e__PMIP__2048__46__46__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_2_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4611204846112048p1395ed3e__PMIP__2048__46__46__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_3_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4611204846112048p1395ed3e__PMIP__2048__46__46__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4611204846112048p1395ed3e__PMIP__2048__46__46__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4611204846112048p1395ed3e__PMIP__2048__46__46__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4611204846112048p1395ed3e__PMIP__2048__46__46__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4611204846112048p1395ed3e__PMIP__2048__46__46__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + 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(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_3_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_3_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef DIB1 (instanceRef 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(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_2_9)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_2_9)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_3_8)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_3_8)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)))) + (net clk + (joined + (portRef WrClock) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_0_11)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_1_10)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_2_9)) + (portRef CLKA (instanceRef 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pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_0_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_1_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_2_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_3_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_0_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_1_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_2_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_3_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_0_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_1_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_2_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_3_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_0_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_1_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_2_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_3_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_0_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_1_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_2_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_3_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_0_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_1_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_2_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_3_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_0_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_1_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_2_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_3_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_0_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_1_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_2_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_3_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_0_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_1_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_2_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_3_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_0_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_1_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_2_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_3_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_0_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_1_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_2_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_3_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_0_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_1_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_2_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_3_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_0_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_1_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_2_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_3_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_0_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_1_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_2_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_3_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_0_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_1_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_2_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_3_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_4_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_5_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_6_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_7_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_8_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_9_2)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_10_1)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e_0_11_0)))))))) + (design pmi_ram_dpXbnonesadr4611204846112048p1395ed3e + (cellRef pmi_ram_dpXbnonesadr4611204846112048p1395ed3e + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr6711204867112048p139603f9.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr6711204867112048p139603f9.edn new file mode 100644 index 0000000..3333650 --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr6711204867112048p139603f9.edn @@ -0,0 +1,3096 @@ +(edif pmi_ram_dpXbnonesadr6711204867112048p139603f9 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 15 14 44 25) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 67 -num_rows 2048 -rdata_width 67 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr6711204867112048p139603f9 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction 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(port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell 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+ (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr6711204867112048p139603f9__PMIP__2048__67__67__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr6711204867112048p139603f9__PMIP__2048__67__67__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string 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pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_4_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr6711204867112048p139603f9__PMIP__2048__67__67__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_5_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string 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view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_1_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_2_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_3_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_4_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_5_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_6_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_7_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef DIB6 (instanceRef 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pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_1_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_2_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_3_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_4_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_5_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_6_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_7_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_1_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_2_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_3_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_4_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_5_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_6_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_7_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_1_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_2_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_3_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_4_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_5_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_6_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_7_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_1_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_2_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_3_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_4_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_5_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_6_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_7_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_1_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_2_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_3_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_4_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_5_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_6_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_7_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_1_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_2_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_3_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_4_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_5_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_6_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_7_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_1_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_2_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_3_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_4_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_5_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_6_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_7_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_1_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_2_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_3_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_4_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_5_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_6_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_7_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_1_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_2_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_3_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_4_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_5_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_6_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_7_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_1_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_2_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_3_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_4_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_5_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_6_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_7_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_1_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_2_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_3_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_4_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_5_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_6_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_7_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_1_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_2_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_3_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_4_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_5_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_6_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_7_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_0_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_1_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_2_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_3_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_4_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_5_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_6_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_0_7_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_0_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_1_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_2_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_3_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_4_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_5_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_6_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6711204867112048p139603f9_1_7_0)))))))) + (design pmi_ram_dpXbnonesadr6711204867112048p139603f9 + (cellRef pmi_ram_dpXbnonesadr6711204867112048p139603f9 + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr6811204868112048p13960e6d.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr6811204868112048p13960e6d.edn new file mode 100644 index 0000000..1d142c5 --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr6811204868112048p13960e6d.edn @@ -0,0 +1,3115 @@ +(edif pmi_ram_dpXbnonesadr6811204868112048p13960e6d + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 19 10 37 51) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 68 -num_rows 2048 -rdata_width 68 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr6811204868112048p13960e6d -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr6811204868112048p13960e6d + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(67:0)") 68) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(67:0)") 68) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr6811204868112048p13960e6d__PMIP__2048__68__68__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr6811204868112048p13960e6d__PMIP__2048__68__68__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr6811204868112048p13960e6d__PMIP__2048__68__68__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr6811204868112048p13960e6d__PMIP__2048__68__68__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr6811204868112048p13960e6d__PMIP__2048__68__68__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr6811204868112048p13960e6d__PMIP__2048__68__68__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr6811204868112048p13960e6d__PMIP__2048__68__68__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr6811204868112048p13960e6d__PMIP__2048__68__68__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr6811204868112048p13960e6d__PMIP__2048__68__68__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr6811204868112048p13960e6d__PMIP__2048__68__68__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr6811204868112048p13960e6d__PMIP__2048__68__68__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr6811204868112048p13960e6d__PMIP__2048__68__68__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr6811204868112048p13960e6d__PMIP__2048__68__68__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr6811204868112048p13960e6d__PMIP__2048__68__68__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr6811204868112048p13960e6d__PMIP__2048__68__68__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr6811204868112048p13960e6d__PMIP__2048__68__68__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_67 + (viewRef view1 + (cellRef MUX21))) + (instance mux_66 + (viewRef view1 + (cellRef MUX21))) + (instance mux_65 + (viewRef view1 + (cellRef MUX21))) + (instance mux_64 + (viewRef view1 + (cellRef MUX21))) + (instance mux_63 + (viewRef view1 + (cellRef MUX21))) + (instance mux_62 + (viewRef view1 + (cellRef MUX21))) + (instance mux_61 + (viewRef view1 + (cellRef MUX21))) + (instance mux_60 + (viewRef view1 + (cellRef MUX21))) + (instance mux_59 + (viewRef view1 + (cellRef MUX21))) + (instance mux_58 + (viewRef view1 + (cellRef MUX21))) + (instance mux_57 + (viewRef view1 + (cellRef MUX21))) + (instance mux_56 + (viewRef view1 + (cellRef MUX21))) + (instance mux_55 + (viewRef view1 + (cellRef MUX21))) + (instance mux_54 + (viewRef view1 + (cellRef MUX21))) + (instance mux_53 + (viewRef view1 + (cellRef MUX21))) + (instance mux_52 + (viewRef view1 + (cellRef MUX21))) + (instance mux_51 + (viewRef view1 + (cellRef MUX21))) + (instance mux_50 + (viewRef view1 + (cellRef MUX21))) + (instance mux_49 + (viewRef view1 + (cellRef MUX21))) + (instance mux_48 + (viewRef view1 + (cellRef MUX21))) + (instance mux_47 + (viewRef view1 + (cellRef MUX21))) + (instance mux_46 + (viewRef view1 + (cellRef MUX21))) + (instance mux_45 + (viewRef view1 + (cellRef MUX21))) + (instance mux_44 + (viewRef view1 + (cellRef MUX21))) + (instance mux_43 + (viewRef view1 + (cellRef MUX21))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)) + (portRef WEB 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(instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef RSTB 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(instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADB8 (instanceRef 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pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_0_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_1_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_2_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_3_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_4_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_5_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_6_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_0_7_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_0_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_1_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_2_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_3_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_4_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_5_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_6_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d_1_7_0)))))))) + (design pmi_ram_dpXbnonesadr6811204868112048p13960e6d + (cellRef pmi_ram_dpXbnonesadr6811204868112048p13960e6d + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr7011204870112048p1395d212.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr7011204870112048p1395d212.edn new file mode 100644 index 0000000..0f1c71c --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr7011204870112048p1395d212.edn @@ -0,0 +1,3153 @@ +(edif pmi_ram_dpXbnonesadr7011204870112048p1395d212 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 15 11 21 27) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 70 -num_rows 2048 -rdata_width 70 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr7011204870112048p1395d212 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr7011204870112048p1395d212 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(69:0)") 70) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(69:0)") 70) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7011204870112048p1395d212__PMIP__2048__70__70__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7011204870112048p1395d212__PMIP__2048__70__70__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7011204870112048p1395d212__PMIP__2048__70__70__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7011204870112048p1395d212__PMIP__2048__70__70__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7011204870112048p1395d212__PMIP__2048__70__70__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7011204870112048p1395d212__PMIP__2048__70__70__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7011204870112048p1395d212__PMIP__2048__70__70__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7011204870112048p1395d212__PMIP__2048__70__70__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7011204870112048p1395d212__PMIP__2048__70__70__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7011204870112048p1395d212__PMIP__2048__70__70__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7011204870112048p1395d212__PMIP__2048__70__70__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7011204870112048p1395d212__PMIP__2048__70__70__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7011204870112048p1395d212__PMIP__2048__70__70__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7011204870112048p1395d212__PMIP__2048__70__70__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7011204870112048p1395d212__PMIP__2048__70__70__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7011204870112048p1395d212__PMIP__2048__70__70__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_69 + (viewRef view1 + (cellRef MUX21))) + (instance mux_68 + (viewRef view1 + (cellRef MUX21))) + (instance mux_67 + (viewRef view1 + (cellRef MUX21))) + (instance mux_66 + (viewRef view1 + (cellRef MUX21))) + (instance mux_65 + (viewRef view1 + (cellRef MUX21))) + (instance mux_64 + (viewRef view1 + (cellRef MUX21))) + (instance mux_63 + (viewRef view1 + (cellRef MUX21))) + (instance mux_62 + (viewRef view1 + (cellRef MUX21))) + (instance mux_61 + (viewRef view1 + (cellRef MUX21))) + (instance mux_60 + (viewRef view1 + (cellRef MUX21))) + (instance mux_59 + (viewRef view1 + (cellRef MUX21))) + (instance mux_58 + (viewRef view1 + (cellRef MUX21))) + (instance mux_57 + (viewRef view1 + (cellRef MUX21))) + (instance mux_56 + (viewRef view1 + (cellRef MUX21))) + (instance mux_55 + (viewRef view1 + (cellRef MUX21))) + (instance mux_54 + (viewRef view1 + (cellRef MUX21))) + (instance mux_53 + (viewRef view1 + (cellRef MUX21))) + (instance mux_52 + (viewRef view1 + (cellRef MUX21))) + (instance mux_51 + (viewRef view1 + (cellRef MUX21))) + (instance mux_50 + (viewRef view1 + (cellRef MUX21))) + (instance mux_49 + (viewRef view1 + (cellRef MUX21))) + (instance mux_48 + (viewRef view1 + (cellRef MUX21))) + (instance mux_47 + (viewRef view1 + (cellRef MUX21))) + (instance mux_46 + (viewRef view1 + (cellRef MUX21))) + (instance mux_45 + (viewRef view1 + (cellRef MUX21))) + (instance mux_44 + (viewRef view1 + (cellRef MUX21))) + (instance mux_43 + (viewRef view1 + (cellRef MUX21))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef CSA1 (instanceRef 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pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))) + (net raddr8 + (joined + (portRef (member RdAddress 2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))) + (net raddr7 + (joined + (portRef (member RdAddress 3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_0_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_1_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_2_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_3_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_4_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_5_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_6_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_0_7_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_0_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_1_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_2_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_3_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_4_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_5_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_6_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7011204870112048p1395d212_1_7_0)))))))) + (design pmi_ram_dpXbnonesadr7011204870112048p1395d212 + (cellRef pmi_ram_dpXbnonesadr7011204870112048p1395d212 + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr7311204873112048p1395eb70.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr7311204873112048p1395eb70.edn new file mode 100644 index 0000000..6557fcd --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr7311204873112048p1395eb70.edn @@ -0,0 +1,3392 @@ +(edif pmi_ram_dpXbnonesadr7311204873112048p1395eb70 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 13 14 11 21) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 73 -num_rows 2048 -rdata_width 73 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr7311204873112048p1395eb70 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr7311204873112048p1395eb70 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(72:0)") 73) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(72:0)") 73) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7311204873112048p1395eb70__PMIP__2048__73__73__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7311204873112048p1395eb70__PMIP__2048__73__73__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7311204873112048p1395eb70__PMIP__2048__73__73__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7311204873112048p1395eb70__PMIP__2048__73__73__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7311204873112048p1395eb70__PMIP__2048__73__73__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string 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CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7311204873112048p1395eb70__PMIP__2048__73__73__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7311204873112048p1395eb70__PMIP__2048__73__73__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7311204873112048p1395eb70__PMIP__2048__73__73__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7311204873112048p1395eb70__PMIP__2048__73__73__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7311204873112048p1395eb70__PMIP__2048__73__73__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7311204873112048p1395eb70__PMIP__2048__73__73__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7311204873112048p1395eb70__PMIP__2048__73__73__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7311204873112048p1395eb70__PMIP__2048__73__73__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7311204873112048p1395eb70__PMIP__2048__73__73__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7311204873112048p1395eb70__PMIP__2048__73__73__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7311204873112048p1395eb70__PMIP__2048__73__73__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_72 + (viewRef view1 + (cellRef MUX21))) + (instance mux_71 + (viewRef view1 + (cellRef MUX21))) + (instance mux_70 + (viewRef view1 + (cellRef MUX21))) + (instance mux_69 + (viewRef view1 + (cellRef MUX21))) + (instance mux_68 + (viewRef view1 + (cellRef MUX21))) + (instance mux_67 + (viewRef view1 + (cellRef MUX21))) + (instance mux_66 + (viewRef view1 + (cellRef MUX21))) + (instance mux_65 + (viewRef view1 + (cellRef MUX21))) + (instance mux_64 + (viewRef view1 + (cellRef MUX21))) + (instance mux_63 + (viewRef view1 + (cellRef MUX21))) + (instance mux_62 + (viewRef view1 + (cellRef MUX21))) + (instance mux_61 + (viewRef view1 + (cellRef MUX21))) + (instance mux_60 + (viewRef view1 + (cellRef MUX21))) + (instance mux_59 + (viewRef view1 + (cellRef MUX21))) + (instance mux_58 + (viewRef view1 + (cellRef MUX21))) + (instance mux_57 + (viewRef view1 + (cellRef MUX21))) + (instance mux_56 + (viewRef view1 + (cellRef MUX21))) + (instance mux_55 + (viewRef view1 + (cellRef MUX21))) + (instance mux_54 + (viewRef view1 + (cellRef MUX21))) + (instance mux_53 + (viewRef view1 + (cellRef MUX21))) + (instance mux_52 + (viewRef view1 + (cellRef MUX21))) + (instance mux_51 + (viewRef view1 + (cellRef MUX21))) + (instance mux_50 + (viewRef view1 + (cellRef MUX21))) + (instance mux_49 + (viewRef view1 + (cellRef MUX21))) + (instance mux_48 + (viewRef view1 + (cellRef MUX21))) + (instance mux_47 + (viewRef view1 + (cellRef MUX21))) + (instance mux_46 + (viewRef view1 + (cellRef MUX21))) + (instance mux_45 + (viewRef view1 + (cellRef MUX21))) + (instance mux_44 + (viewRef view1 + (cellRef MUX21))) + (instance mux_43 + (viewRef view1 + (cellRef MUX21))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef CSB2 (instanceRef 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72)) + (portRef Z (instanceRef mux_72)))) + (net WrClockEn + (joined + (portRef WrClockEn) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef OCEA (instanceRef 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(instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net RdClockEn + (joined + (portRef RdClockEn) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef CEB (instanceRef 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(instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)) + (portRef SP (instanceRef FF_1)) + (portRef SP (instanceRef FF_0)))) + (net rdclk + (joined + (portRef RdClock) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef CLKB (instanceRef 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(portRef WEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef WEA 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(instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)) + (portRef D (instanceRef FF_1)))) + (net raddr9 + (joined + (portRef (member RdAddress 1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net raddr8 + (joined + (portRef (member RdAddress 2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net raddr7 + (joined + (portRef (member RdAddress 3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_0_17)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_1_16)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_2_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_3_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_4_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_5_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_6_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_7_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_0_8_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_0_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_1_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_2_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_3_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_4_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_5_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_6_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_7_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70_1_8_0)))))))) + (design pmi_ram_dpXbnonesadr7311204873112048p1395eb70 + (cellRef pmi_ram_dpXbnonesadr7311204873112048p1395eb70 + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr7511204875112048p1395fbe3.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr7511204875112048p1395fbe3.edn new file mode 100644 index 0000000..9ab5872 --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr7511204875112048p1395fbe3.edn @@ -0,0 +1,3430 @@ +(edif pmi_ram_dpXbnonesadr7511204875112048p1395fbe3 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 14 17 59 15) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 75 -num_rows 2048 -rdata_width 75 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr7511204875112048p1395fbe3 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr7511204875112048p1395fbe3 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(74:0)") 75) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(74:0)") 75) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7511204875112048p1395fbe3__PMIP__2048__75__75__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7511204875112048p1395fbe3__PMIP__2048__75__75__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7511204875112048p1395fbe3__PMIP__2048__75__75__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7511204875112048p1395fbe3__PMIP__2048__75__75__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7511204875112048p1395fbe3__PMIP__2048__75__75__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7511204875112048p1395fbe3__PMIP__2048__75__75__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7511204875112048p1395fbe3__PMIP__2048__75__75__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7511204875112048p1395fbe3__PMIP__2048__75__75__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7511204875112048p1395fbe3__PMIP__2048__75__75__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7511204875112048p1395fbe3__PMIP__2048__75__75__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7511204875112048p1395fbe3__PMIP__2048__75__75__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7511204875112048p1395fbe3__PMIP__2048__75__75__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7511204875112048p1395fbe3__PMIP__2048__75__75__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7511204875112048p1395fbe3__PMIP__2048__75__75__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_5_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7511204875112048p1395fbe3__PMIP__2048__75__75__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_6_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7511204875112048p1395fbe3__PMIP__2048__75__75__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_7_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7511204875112048p1395fbe3__PMIP__2048__75__75__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_8_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7511204875112048p1395fbe3__PMIP__2048__75__75__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_74 + (viewRef view1 + (cellRef MUX21))) + (instance mux_73 + (viewRef view1 + (cellRef MUX21))) + (instance mux_72 + (viewRef view1 + (cellRef MUX21))) + (instance mux_71 + (viewRef view1 + (cellRef MUX21))) + (instance mux_70 + (viewRef view1 + (cellRef MUX21))) + (instance mux_69 + (viewRef view1 + (cellRef MUX21))) + (instance mux_68 + (viewRef view1 + (cellRef MUX21))) + (instance mux_67 + (viewRef view1 + (cellRef MUX21))) + (instance mux_66 + (viewRef view1 + (cellRef MUX21))) + (instance mux_65 + (viewRef view1 + (cellRef MUX21))) + (instance mux_64 + (viewRef view1 + (cellRef MUX21))) + (instance mux_63 + (viewRef view1 + (cellRef MUX21))) + (instance mux_62 + (viewRef view1 + (cellRef MUX21))) + (instance mux_61 + (viewRef view1 + (cellRef MUX21))) + (instance mux_60 + (viewRef view1 + (cellRef MUX21))) + (instance mux_59 + (viewRef view1 + (cellRef MUX21))) + (instance mux_58 + (viewRef view1 + (cellRef MUX21))) + (instance mux_57 + (viewRef view1 + (cellRef MUX21))) + (instance mux_56 + (viewRef view1 + (cellRef MUX21))) + (instance mux_55 + (viewRef view1 + (cellRef MUX21))) + (instance mux_54 + (viewRef view1 + (cellRef MUX21))) + (instance mux_53 + (viewRef view1 + (cellRef MUX21))) + (instance mux_52 + (viewRef view1 + (cellRef MUX21))) + (instance mux_51 + (viewRef view1 + (cellRef MUX21))) + (instance mux_50 + (viewRef view1 + (cellRef MUX21))) + (instance mux_49 + (viewRef view1 + (cellRef MUX21))) + (instance mux_48 + (viewRef view1 + (cellRef MUX21))) + (instance mux_47 + (viewRef view1 + (cellRef MUX21))) + (instance mux_46 + (viewRef view1 + (cellRef MUX21))) + (instance mux_45 + (viewRef view1 + (cellRef MUX21))) + (instance mux_44 + (viewRef view1 + (cellRef MUX21))) + (instance mux_43 + (viewRef view1 + (cellRef MUX21))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_5_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_6_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_7_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_8_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef ADA2 (instanceRef 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(instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_5_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_6_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_7_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_8_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_5_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_6_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_7_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_8_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_5_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_6_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_7_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_8_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_5_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_6_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_7_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_8_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_5_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_6_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_7_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_8_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_5_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_6_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_7_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_8_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_5_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_6_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_7_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_8_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_5_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_6_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_7_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_8_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_5_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_6_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_7_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_8_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_5_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_6_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_7_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_8_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_5_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_6_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_7_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_8_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_5_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_6_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_7_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_8_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_5_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_6_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_7_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_8_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_5_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_6_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_7_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_8_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_5_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_6_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_7_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_8_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_5_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_6_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_7_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_8_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_0_17)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_1_16)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_2_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_3_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_4_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_5_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_6_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_7_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_0_8_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_0_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_1_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_2_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_3_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_4_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_5_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_6_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_7_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3_1_8_0)))))))) + (design pmi_ram_dpXbnonesadr7511204875112048p1395fbe3 + (cellRef pmi_ram_dpXbnonesadr7511204875112048p1395fbe3 + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr7611204876112048p139603f9.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr7611204876112048p139603f9.edn new file mode 100644 index 0000000..569d1b8 --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr7611204876112048p139603f9.edn @@ -0,0 +1,3449 @@ +(edif pmi_ram_dpXbnonesadr7611204876112048p139603f9 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 15 10 55 42) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 76 -num_rows 2048 -rdata_width 76 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr7611204876112048p139603f9 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr7611204876112048p139603f9 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(75:0)") 76) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(75:0)") 76) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7611204876112048p139603f9__PMIP__2048__76__76__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7611204876112048p139603f9__PMIP__2048__76__76__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7611204876112048p139603f9__PMIP__2048__76__76__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7611204876112048p139603f9__PMIP__2048__76__76__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7611204876112048p139603f9__PMIP__2048__76__76__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7611204876112048p139603f9__PMIP__2048__76__76__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7611204876112048p139603f9__PMIP__2048__76__76__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7611204876112048p139603f9__PMIP__2048__76__76__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string 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CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7611204876112048p139603f9__PMIP__2048__76__76__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7611204876112048p139603f9__PMIP__2048__76__76__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance 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(string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7611204876112048p139603f9__PMIP__2048__76__76__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) 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(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef CD (instanceRef FF_1)) + (portRef CD (instanceRef FF_0)))) + (net raddr10_ff + (joined + (portRef D (instanceRef FF_0)) + (portRef Q (instanceRef FF_1)))) + (net mdout1_1_0 + (joined + (portRef D1 (instanceRef mux_75)) + (portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)))) + (net mdout1_0_0 + (joined + (portRef D0 (instanceRef mux_75)) + (portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)))) + (net mdout1_1_1 + (joined + (portRef D1 (instanceRef mux_74)) + (portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)))) + (net mdout1_0_1 + (joined + (portRef D0 (instanceRef mux_74)) + (portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)))) + (net mdout1_1_2 + (joined + (portRef D1 (instanceRef mux_73)) + (portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)))) + (net mdout1_0_2 + (joined + (portRef D0 (instanceRef mux_73)) + (portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)))) + (net mdout1_1_3 + (joined + (portRef D1 (instanceRef mux_72)) + (portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)))) + (net mdout1_0_3 + (joined + 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pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net Reset + (joined + (portRef Reset) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net RdClockEn + (joined + (portRef RdClockEn) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef SP (instanceRef FF_1)) + (portRef SP (instanceRef FF_0)))) + (net rdclk + (joined + (portRef RdClock) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)) + (portRef CK (instanceRef FF_1)) + (portRef CK (instanceRef FF_0)))) + (net wren + (joined + (portRef WE) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net datain75 + (joined + (portRef (member Data 0)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net datain74 + (joined + (portRef (member Data 1)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net datain73 + (joined + (portRef (member Data 2)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net datain72 + (joined + (portRef (member Data 3)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net datain71 + (joined + (portRef (member Data 4)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)))) + (net datain70 + (joined + (portRef (member Data 5)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)))) + (net datain69 + (joined + (portRef (member Data 6)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)))) + (net datain68 + (joined + (portRef (member Data 7)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)))) + (net datain67 + (joined + (portRef (member Data 8)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)))) + (net datain66 + (joined + (portRef (member Data 9)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)))) + (net datain65 + (joined + (portRef (member Data 10)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)))) + (net datain64 + (joined + (portRef (member Data 11)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)))) + (net datain63 + (joined + (portRef (member Data 12)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)))) + (net datain62 + (joined + (portRef (member Data 13)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)))) + (net datain61 + (joined + (portRef (member Data 14)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)))) + (net datain60 + (joined + (portRef (member Data 15)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)))) + (net datain59 + (joined + (portRef (member Data 16)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)))) + (net datain58 + (joined + (portRef (member Data 17)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + 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(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net raddr8 + (joined + (portRef (member RdAddress 2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef 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+ (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net raddr7 + (joined + (portRef (member RdAddress 3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_0_17)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_1_16)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_2_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_3_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_4_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_5_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_6_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_7_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_0_8_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_0_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_1_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_2_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_3_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_4_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_5_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_6_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_7_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7611204876112048p139603f9_1_8_0)))))))) + (design pmi_ram_dpXbnonesadr7611204876112048p139603f9 + (cellRef pmi_ram_dpXbnonesadr7611204876112048p139603f9 + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr7711204877112048p13960d59.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr7711204877112048p13960d59.edn new file mode 100644 index 0000000..025bf33 --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr7711204877112048p13960d59.edn @@ -0,0 +1,3468 @@ +(edif pmi_ram_dpXbnonesadr7711204877112048p13960d59 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 14 17 54 30) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 77 -num_rows 2048 -rdata_width 77 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr7711204877112048p13960d59 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr7711204877112048p13960d59 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(76:0)") 77) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(76:0)") 77) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7711204877112048p13960d59__PMIP__2048__77__77__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7711204877112048p13960d59__PMIP__2048__77__77__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7711204877112048p13960d59__PMIP__2048__77__77__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7711204877112048p13960d59__PMIP__2048__77__77__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7711204877112048p13960d59__PMIP__2048__77__77__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7711204877112048p13960d59__PMIP__2048__77__77__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7711204877112048p13960d59__PMIP__2048__77__77__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7711204877112048p13960d59__PMIP__2048__77__77__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7711204877112048p13960d59__PMIP__2048__77__77__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7711204877112048p13960d59__PMIP__2048__77__77__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7711204877112048p13960d59__PMIP__2048__77__77__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7711204877112048p13960d59__PMIP__2048__77__77__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7711204877112048p13960d59__PMIP__2048__77__77__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7711204877112048p13960d59__PMIP__2048__77__77__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7711204877112048p13960d59__PMIP__2048__77__77__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7711204877112048p13960d59__PMIP__2048__77__77__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7711204877112048p13960d59__PMIP__2048__77__77__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr7711204877112048p13960d59__PMIP__2048__77__77__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_76 + (viewRef view1 + (cellRef MUX21))) + (instance mux_75 + (viewRef view1 + (cellRef MUX21))) + (instance mux_74 + (viewRef view1 + (cellRef MUX21))) + (instance mux_73 + (viewRef view1 + (cellRef MUX21))) + (instance mux_72 + (viewRef view1 + (cellRef MUX21))) + (instance mux_71 + (viewRef view1 + (cellRef MUX21))) + (instance mux_70 + (viewRef view1 + (cellRef MUX21))) + (instance mux_69 + (viewRef view1 + (cellRef MUX21))) + (instance mux_68 + (viewRef view1 + (cellRef MUX21))) + (instance mux_67 + (viewRef view1 + (cellRef MUX21))) + (instance mux_66 + (viewRef view1 + (cellRef MUX21))) + (instance mux_65 + (viewRef view1 + (cellRef MUX21))) + (instance mux_64 + (viewRef view1 + (cellRef MUX21))) + (instance mux_63 + (viewRef view1 + (cellRef MUX21))) + (instance mux_62 + (viewRef view1 + (cellRef MUX21))) + (instance mux_61 + (viewRef view1 + (cellRef MUX21))) + (instance mux_60 + (viewRef view1 + (cellRef MUX21))) + (instance mux_59 + (viewRef view1 + (cellRef MUX21))) + (instance mux_58 + (viewRef view1 + (cellRef MUX21))) + (instance mux_57 + (viewRef view1 + (cellRef MUX21))) + (instance mux_56 + (viewRef view1 + (cellRef MUX21))) + (instance mux_55 + (viewRef view1 + (cellRef MUX21))) + (instance mux_54 + (viewRef view1 + (cellRef MUX21))) + (instance mux_53 + (viewRef view1 + (cellRef MUX21))) + (instance mux_52 + (viewRef view1 + (cellRef MUX21))) + (instance mux_51 + (viewRef view1 + (cellRef MUX21))) + (instance mux_50 + (viewRef view1 + (cellRef MUX21))) + (instance mux_49 + (viewRef view1 + (cellRef MUX21))) + (instance mux_48 + (viewRef view1 + (cellRef MUX21))) + (instance mux_47 + (viewRef view1 + (cellRef MUX21))) + (instance mux_46 + (viewRef view1 + (cellRef MUX21))) + (instance mux_45 + (viewRef view1 + (cellRef MUX21))) + (instance mux_44 + (viewRef view1 + (cellRef MUX21))) + (instance mux_43 + (viewRef view1 + (cellRef MUX21))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef DIB2 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(instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))) + (net raddr8 + (joined + (portRef (member RdAddress 2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))) + (net raddr7 + (joined + (portRef (member RdAddress 3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_0_17)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_1_16)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_2_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_3_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_4_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_5_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_6_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_7_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_0_8_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_0_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_1_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_2_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_3_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_4_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_5_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_6_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_7_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr7711204877112048p13960d59_1_8_0)))))))) + (design pmi_ram_dpXbnonesadr7711204877112048p13960d59 + (cellRef pmi_ram_dpXbnonesadr7711204877112048p13960d59 + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr8111204881112048p1395e235.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr8111204881112048p1395e235.edn new file mode 100644 index 0000000..5270c24 --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr8111204881112048p1395e235.edn @@ -0,0 +1,3544 @@ +(edif pmi_ram_dpXbnonesadr8111204881112048p1395e235 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 14 17 46 9) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 81 -num_rows 2048 -rdata_width 81 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr8111204881112048p1395e235 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr8111204881112048p1395e235 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(80:0)") 81) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(80:0)") 81) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8111204881112048p1395e235__PMIP__2048__81__81__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8111204881112048p1395e235__PMIP__2048__81__81__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8111204881112048p1395e235__PMIP__2048__81__81__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8111204881112048p1395e235__PMIP__2048__81__81__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8111204881112048p1395e235__PMIP__2048__81__81__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8111204881112048p1395e235__PMIP__2048__81__81__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8111204881112048p1395e235__PMIP__2048__81__81__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8111204881112048p1395e235__PMIP__2048__81__81__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8111204881112048p1395e235__PMIP__2048__81__81__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8111204881112048p1395e235__PMIP__2048__81__81__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8111204881112048p1395e235__PMIP__2048__81__81__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8111204881112048p1395e235__PMIP__2048__81__81__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8111204881112048p1395e235__PMIP__2048__81__81__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8111204881112048p1395e235__PMIP__2048__81__81__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8111204881112048p1395e235__PMIP__2048__81__81__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8111204881112048p1395e235__PMIP__2048__81__81__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_7_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8111204881112048p1395e235__PMIP__2048__81__81__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_8_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8111204881112048p1395e235__PMIP__2048__81__81__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_80 + (viewRef view1 + (cellRef MUX21))) + (instance mux_79 + (viewRef view1 + (cellRef MUX21))) + (instance mux_78 + (viewRef view1 + (cellRef MUX21))) + (instance mux_77 + (viewRef view1 + (cellRef MUX21))) + (instance mux_76 + (viewRef view1 + (cellRef MUX21))) + (instance mux_75 + (viewRef view1 + (cellRef MUX21))) + (instance mux_74 + (viewRef view1 + (cellRef MUX21))) + (instance mux_73 + (viewRef view1 + (cellRef MUX21))) + (instance mux_72 + (viewRef view1 + (cellRef MUX21))) + (instance mux_71 + (viewRef view1 + (cellRef MUX21))) + (instance mux_70 + (viewRef view1 + (cellRef MUX21))) + (instance mux_69 + (viewRef view1 + (cellRef MUX21))) + (instance mux_68 + (viewRef view1 + (cellRef MUX21))) + (instance mux_67 + (viewRef view1 + (cellRef MUX21))) + (instance mux_66 + (viewRef view1 + (cellRef MUX21))) + (instance mux_65 + (viewRef view1 + (cellRef MUX21))) + (instance mux_64 + (viewRef view1 + (cellRef MUX21))) + (instance mux_63 + (viewRef view1 + (cellRef MUX21))) + (instance mux_62 + (viewRef view1 + (cellRef MUX21))) + (instance mux_61 + (viewRef view1 + (cellRef MUX21))) + (instance mux_60 + (viewRef view1 + (cellRef MUX21))) + (instance mux_59 + (viewRef view1 + (cellRef MUX21))) + (instance mux_58 + (viewRef view1 + (cellRef MUX21))) + (instance mux_57 + (viewRef view1 + (cellRef MUX21))) + (instance mux_56 + (viewRef view1 + (cellRef MUX21))) + (instance mux_55 + (viewRef view1 + (cellRef MUX21))) + (instance mux_54 + (viewRef view1 + (cellRef MUX21))) + (instance mux_53 + (viewRef view1 + (cellRef MUX21))) + (instance mux_52 + (viewRef view1 + (cellRef MUX21))) + (instance mux_51 + (viewRef view1 + (cellRef MUX21))) + (instance mux_50 + (viewRef view1 + (cellRef MUX21))) + (instance mux_49 + (viewRef view1 + (cellRef MUX21))) + (instance mux_48 + (viewRef view1 + (cellRef MUX21))) + (instance mux_47 + (viewRef view1 + (cellRef MUX21))) + (instance mux_46 + (viewRef view1 + (cellRef MUX21))) + (instance mux_45 + (viewRef view1 + (cellRef MUX21))) + (instance mux_44 + (viewRef view1 + (cellRef MUX21))) + (instance mux_43 + (viewRef view1 + (cellRef MUX21))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_7_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_8_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2)) + (portRef CSA2 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(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_7_1)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_8_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_7_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_8_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_7_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_8_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_7_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_8_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_7_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_8_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_7_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_8_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_7_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_8_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_7_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_8_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_7_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_8_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_7_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_8_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_7_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_8_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_7_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_8_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_7_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_8_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_7_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_8_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_7_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_8_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_7_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_8_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_7_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_8_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_7_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_8_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_0_17)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_1_16)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_2_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_3_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_4_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_5_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_6_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_7_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_0_8_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_0_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_1_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_2_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_3_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_4_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_5_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_6_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_7_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8111204881112048p1395e235_1_8_0)))))))) + (design pmi_ram_dpXbnonesadr8111204881112048p1395e235 + (cellRef pmi_ram_dpXbnonesadr8111204881112048p1395e235 + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr8211204882112048p1395ebf0.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr8211204882112048p1395ebf0.edn new file mode 100644 index 0000000..3095e0d --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr8211204882112048p1395ebf0.edn @@ -0,0 +1,3745 @@ +(edif pmi_ram_dpXbnonesadr8211204882112048p1395ebf0 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 15 14 27 23) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 82 -num_rows 2048 -rdata_width 82 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr8211204882112048p1395ebf0 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr8211204882112048p1395ebf0 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(81:0)") 82) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(81:0)") 82) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8211204882112048p1395ebf0__PMIP__2048__82__82__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8211204882112048p1395ebf0__PMIP__2048__82__82__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8211204882112048p1395ebf0__PMIP__2048__82__82__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8211204882112048p1395ebf0__PMIP__2048__82__82__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8211204882112048p1395ebf0__PMIP__2048__82__82__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8211204882112048p1395ebf0__PMIP__2048__82__82__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8211204882112048p1395ebf0__PMIP__2048__82__82__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8211204882112048p1395ebf0__PMIP__2048__82__82__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8211204882112048p1395ebf0__PMIP__2048__82__82__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8211204882112048p1395ebf0__PMIP__2048__82__82__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8211204882112048p1395ebf0__PMIP__2048__82__82__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance 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"pmi_ram_dpXbnonesadr8211204882112048p1395ebf0__PMIP__2048__82__82__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8211204882112048p1395ebf0__PMIP__2048__82__82__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + 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+ (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8211204882112048p1395ebf0__PMIP__2048__82__82__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + 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(instance mux_68 + (viewRef view1 + (cellRef MUX21))) + (instance mux_67 + (viewRef view1 + (cellRef MUX21))) + (instance mux_66 + (viewRef view1 + (cellRef MUX21))) + (instance mux_65 + (viewRef view1 + (cellRef MUX21))) + (instance mux_64 + (viewRef view1 + (cellRef MUX21))) + (instance mux_63 + (viewRef view1 + (cellRef MUX21))) + (instance mux_62 + (viewRef view1 + (cellRef MUX21))) + (instance mux_61 + (viewRef view1 + (cellRef MUX21))) + (instance mux_60 + (viewRef view1 + (cellRef MUX21))) + (instance mux_59 + (viewRef view1 + (cellRef MUX21))) + (instance mux_58 + (viewRef view1 + (cellRef MUX21))) + (instance mux_57 + (viewRef view1 + (cellRef MUX21))) + (instance mux_56 + (viewRef view1 + (cellRef MUX21))) + (instance mux_55 + (viewRef view1 + (cellRef MUX21))) + (instance mux_54 + (viewRef view1 + (cellRef MUX21))) + (instance mux_53 + (viewRef view1 + (cellRef MUX21))) + (instance mux_52 + (viewRef view1 + (cellRef MUX21))) + (instance mux_51 + (viewRef view1 + (cellRef MUX21))) + (instance mux_50 + (viewRef view1 + (cellRef MUX21))) + (instance mux_49 + (viewRef view1 + (cellRef MUX21))) + (instance mux_48 + (viewRef view1 + (cellRef MUX21))) + (instance mux_47 + (viewRef view1 + (cellRef MUX21))) + (instance mux_46 + (viewRef view1 + (cellRef MUX21))) + (instance mux_45 + (viewRef view1 + (cellRef MUX21))) + (instance mux_44 + (viewRef view1 + (cellRef MUX21))) + (instance mux_43 + (viewRef view1 + (cellRef MUX21))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef DIB1 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pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net Reset + (joined + (portRef Reset) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net RdClockEn + (joined + (portRef RdClockEn) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)) + (portRef SP (instanceRef FF_1)) + (portRef SP (instanceRef FF_0)))) + (net rdclk + (joined + (portRef RdClock) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)) + (portRef CK (instanceRef FF_1)) + (portRef CK (instanceRef FF_0)))) + (net wren + (joined + (portRef WE) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net datain81 + (joined + (portRef (member Data 0)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net datain80 + (joined + (portRef (member Data 1)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)))) + (net datain79 + (joined + (portRef (member Data 2)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)))) + (net datain78 + (joined + (portRef (member Data 3)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)))) + (net datain77 + (joined + (portRef (member Data 4)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)))) + (net datain76 + (joined + (portRef (member Data 5)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)))) + (net datain75 + (joined + (portRef (member Data 6)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)))) + (net datain74 + (joined + (portRef (member Data 7)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)))) + (net datain73 + (joined + (portRef (member Data 8)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)))) + (net datain72 + (joined + (portRef (member Data 9)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)))) + (net datain71 + (joined + (portRef (member Data 10)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)))) + (net datain70 + (joined + (portRef (member Data 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(instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net raddr8 + (joined + (portRef (member RdAddress 2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net raddr7 + (joined + (portRef (member RdAddress 3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_0_19)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_1_18)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_2_17)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_3_16)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_4_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_5_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_6_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_7_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_8_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_0_9_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_0_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_1_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_2_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_3_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_4_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_5_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_6_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_7_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_8_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0_1_9_0)))))))) + (design pmi_ram_dpXbnonesadr8211204882112048p1395ebf0 + (cellRef pmi_ram_dpXbnonesadr8211204882112048p1395ebf0 + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr8611204886112048p13960e6d.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr8611204886112048p13960e6d.edn new file mode 100644 index 0000000..07a1423 --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr8611204886112048p13960e6d.edn @@ -0,0 +1,3821 @@ +(edif pmi_ram_dpXbnonesadr8611204886112048p13960e6d + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 14 18 6 56) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 86 -num_rows 2048 -rdata_width 86 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr8611204886112048p13960e6d -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr8611204886112048p13960e6d + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(85:0)") 86) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(85:0)") 86) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8611204886112048p13960e6d__PMIP__2048__86__86__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8611204886112048p13960e6d__PMIP__2048__86__86__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8611204886112048p13960e6d__PMIP__2048__86__86__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8611204886112048p13960e6d__PMIP__2048__86__86__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8611204886112048p13960e6d__PMIP__2048__86__86__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8611204886112048p13960e6d__PMIP__2048__86__86__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8611204886112048p13960e6d__PMIP__2048__86__86__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8611204886112048p13960e6d__PMIP__2048__86__86__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string 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(instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)) + 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ADB10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_0_19)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_1_18)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_2_17)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_3_16)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_4_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_5_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_6_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_7_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_8_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_0_9_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_0_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_1_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_2_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_3_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_4_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_5_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_6_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_7_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_8_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d_1_9_0)))))))) + (design pmi_ram_dpXbnonesadr8611204886112048p13960e6d + (cellRef pmi_ram_dpXbnonesadr8611204886112048p13960e6d + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr8711204887112048p139613de.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr8711204887112048p139613de.edn new file mode 100644 index 0000000..952406d --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr8711204887112048p139613de.edn @@ -0,0 +1,3840 @@ +(edif pmi_ram_dpXbnonesadr8711204887112048p139613de + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 15 10 31 55) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 87 -num_rows 2048 -rdata_width 87 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr8711204887112048p139613de -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr8711204887112048p139613de + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(86:0)") 87) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(86:0)") 87) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8711204887112048p139613de__PMIP__2048__87__87__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8711204887112048p139613de__PMIP__2048__87__87__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8711204887112048p139613de__PMIP__2048__87__87__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8711204887112048p139613de__PMIP__2048__87__87__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8711204887112048p139613de__PMIP__2048__87__87__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8711204887112048p139613de__PMIP__2048__87__87__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8711204887112048p139613de__PMIP__2048__87__87__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8711204887112048p139613de__PMIP__2048__87__87__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8711204887112048p139613de__PMIP__2048__87__87__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8711204887112048p139613de__PMIP__2048__87__87__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8711204887112048p139613de__PMIP__2048__87__87__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8711204887112048p139613de__PMIP__2048__87__87__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8711204887112048p139613de__PMIP__2048__87__87__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8711204887112048p139613de__PMIP__2048__87__87__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8711204887112048p139613de__PMIP__2048__87__87__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8711204887112048p139613de__PMIP__2048__87__87__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8711204887112048p139613de__PMIP__2048__87__87__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8711204887112048p139613de__PMIP__2048__87__87__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8711204887112048p139613de__PMIP__2048__87__87__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8711204887112048p139613de__PMIP__2048__87__87__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_86 + (viewRef view1 + (cellRef MUX21))) + (instance mux_85 + (viewRef view1 + (cellRef MUX21))) + (instance mux_84 + (viewRef view1 + (cellRef MUX21))) + (instance mux_83 + (viewRef view1 + (cellRef MUX21))) + (instance mux_82 + (viewRef view1 + (cellRef MUX21))) + (instance mux_81 + (viewRef view1 + (cellRef MUX21))) + (instance mux_80 + (viewRef view1 + (cellRef MUX21))) + (instance mux_79 + (viewRef view1 + (cellRef MUX21))) + (instance mux_78 + (viewRef view1 + (cellRef MUX21))) + (instance mux_77 + (viewRef view1 + (cellRef MUX21))) + (instance mux_76 + (viewRef view1 + (cellRef MUX21))) + (instance mux_75 + (viewRef view1 + (cellRef MUX21))) + (instance mux_74 + (viewRef view1 + (cellRef MUX21))) + (instance mux_73 + (viewRef view1 + (cellRef MUX21))) + (instance mux_72 + (viewRef view1 + (cellRef MUX21))) + (instance mux_71 + (viewRef view1 + (cellRef MUX21))) + (instance mux_70 + (viewRef view1 + (cellRef MUX21))) + (instance mux_69 + (viewRef view1 + (cellRef MUX21))) + (instance mux_68 + (viewRef view1 + (cellRef MUX21))) + (instance mux_67 + (viewRef view1 + (cellRef MUX21))) + (instance mux_66 + (viewRef view1 + (cellRef MUX21))) + (instance mux_65 + (viewRef view1 + (cellRef MUX21))) + (instance mux_64 + (viewRef view1 + (cellRef MUX21))) + (instance mux_63 + (viewRef view1 + (cellRef MUX21))) + (instance mux_62 + (viewRef view1 + (cellRef MUX21))) + (instance mux_61 + (viewRef view1 + (cellRef MUX21))) + (instance mux_60 + (viewRef view1 + (cellRef MUX21))) + (instance mux_59 + (viewRef view1 + (cellRef MUX21))) + (instance mux_58 + (viewRef view1 + (cellRef MUX21))) + (instance mux_57 + (viewRef view1 + (cellRef MUX21))) + (instance mux_56 + (viewRef view1 + (cellRef MUX21))) + (instance mux_55 + (viewRef view1 + (cellRef MUX21))) + (instance mux_54 + (viewRef view1 + (cellRef MUX21))) + (instance mux_53 + (viewRef view1 + (cellRef MUX21))) + (instance mux_52 + (viewRef view1 + (cellRef MUX21))) + (instance mux_51 + (viewRef view1 + (cellRef MUX21))) + (instance mux_50 + (viewRef view1 + (cellRef MUX21))) + (instance mux_49 + (viewRef view1 + (cellRef MUX21))) + (instance mux_48 + (viewRef view1 + (cellRef MUX21))) + (instance mux_47 + (viewRef view1 + (cellRef MUX21))) + (instance mux_46 + (viewRef view1 + (cellRef MUX21))) + (instance mux_45 + (viewRef view1 + (cellRef MUX21))) + (instance mux_44 + (viewRef view1 + (cellRef MUX21))) + (instance mux_43 + (viewRef view1 + (cellRef MUX21))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef DIB3 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(instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net clk + (joined + (portRef WrClock) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net Reset + (joined + (portRef Reset) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net RdClockEn + (joined + (portRef RdClockEn) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)) + (portRef SP (instanceRef FF_1)) + (portRef SP (instanceRef FF_0)))) + (net rdclk + (joined + (portRef RdClock) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)) + (portRef CK (instanceRef FF_1)) + (portRef CK (instanceRef FF_0)))) + (net wren + (joined + (portRef WE) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef WEA (instanceRef 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82)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)))) + (net datain3 + (joined + (portRef (member Data 83)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)))) + (net datain2 + (joined + (portRef (member Data 84)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)))) + (net datain1 + (joined + (portRef (member Data 85)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)))) + (net datain0 + (joined + (portRef (member Data 86)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)))) + (net raddr10 + (joined + (portRef (member RdAddress 0)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)) + (portRef D (instanceRef FF_1)))) + (net raddr9 + (joined + (portRef (member RdAddress 1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net raddr8 + (joined + (portRef (member RdAddress 2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net raddr7 + (joined + (portRef (member RdAddress 3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_0_19)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_1_18)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_2_17)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_3_16)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_4_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_5_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_6_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_7_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_8_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_0_9_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_0_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_1_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_2_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_3_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_4_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_5_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_6_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_7_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_8_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8711204887112048p139613de_1_9_0)))))))) + (design pmi_ram_dpXbnonesadr8711204887112048p139613de + (cellRef pmi_ram_dpXbnonesadr8711204887112048p139613de + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr8811204888112048p13961f15.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr8811204888112048p13961f15.edn new file mode 100644 index 0000000..faaff99 --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr8811204888112048p13961f15.edn @@ -0,0 +1,3859 @@ +(edif pmi_ram_dpXbnonesadr8811204888112048p13961f15 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 15 11 28 30) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 88 -num_rows 2048 -rdata_width 88 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr8811204888112048p13961f15 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr8811204888112048p13961f15 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(87:0)") 88) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(87:0)") 88) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8811204888112048p13961f15__PMIP__2048__88__88__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8811204888112048p13961f15__PMIP__2048__88__88__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8811204888112048p13961f15__PMIP__2048__88__88__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8811204888112048p13961f15__PMIP__2048__88__88__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8811204888112048p13961f15__PMIP__2048__88__88__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8811204888112048p13961f15__PMIP__2048__88__88__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8811204888112048p13961f15__PMIP__2048__88__88__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr8811204888112048p13961f15__PMIP__2048__88__88__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string 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(instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)) + 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(instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)))) + (net raddr7 + (joined + (portRef (member RdAddress 3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADB10 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pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_0_19)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_1_18)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_2_17)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_3_16)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_4_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_5_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_6_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_7_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_8_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_0_9_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_0_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_1_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_2_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_3_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_4_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_5_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_6_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_7_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_8_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr8811204888112048p13961f15_1_9_0)))))))) + (design pmi_ram_dpXbnonesadr8811204888112048p13961f15 + (cellRef pmi_ram_dpXbnonesadr8811204888112048p13961f15 + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr9011204890112048p1395e512.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr9011204890112048p1395e512.edn new file mode 100644 index 0000000..ca52b81 --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr9011204890112048p1395e512.edn @@ -0,0 +1,3897 @@ +(edif pmi_ram_dpXbnonesadr9011204890112048p1395e512 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 14 18 31 23) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 90 -num_rows 2048 -rdata_width 90 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr9011204890112048p1395e512 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr9011204890112048p1395e512 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(89:0)") 90) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(89:0)") 90) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9011204890112048p1395e512__PMIP__2048__90__90__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9011204890112048p1395e512__PMIP__2048__90__90__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9011204890112048p1395e512__PMIP__2048__90__90__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9011204890112048p1395e512__PMIP__2048__90__90__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9011204890112048p1395e512__PMIP__2048__90__90__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9011204890112048p1395e512__PMIP__2048__90__90__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9011204890112048p1395e512__PMIP__2048__90__90__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9011204890112048p1395e512__PMIP__2048__90__90__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9011204890112048p1395e512__PMIP__2048__90__90__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9011204890112048p1395e512__PMIP__2048__90__90__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9011204890112048p1395e512__PMIP__2048__90__90__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9011204890112048p1395e512__PMIP__2048__90__90__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9011204890112048p1395e512__PMIP__2048__90__90__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9011204890112048p1395e512__PMIP__2048__90__90__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9011204890112048p1395e512__PMIP__2048__90__90__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9011204890112048p1395e512__PMIP__2048__90__90__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9011204890112048p1395e512__PMIP__2048__90__90__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9011204890112048p1395e512__PMIP__2048__90__90__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9011204890112048p1395e512__PMIP__2048__90__90__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9011204890112048p1395e512__PMIP__2048__90__90__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_89 + (viewRef view1 + (cellRef MUX21))) + (instance mux_88 + (viewRef view1 + (cellRef MUX21))) + (instance mux_87 + (viewRef view1 + (cellRef MUX21))) + (instance mux_86 + (viewRef view1 + (cellRef MUX21))) + (instance mux_85 + (viewRef view1 + (cellRef MUX21))) + (instance mux_84 + (viewRef view1 + (cellRef MUX21))) + (instance mux_83 + (viewRef view1 + (cellRef MUX21))) + (instance mux_82 + (viewRef view1 + (cellRef MUX21))) + (instance mux_81 + (viewRef view1 + (cellRef MUX21))) + (instance mux_80 + (viewRef view1 + (cellRef MUX21))) + (instance mux_79 + (viewRef view1 + (cellRef MUX21))) + (instance mux_78 + (viewRef view1 + (cellRef MUX21))) + (instance mux_77 + (viewRef view1 + (cellRef MUX21))) + (instance mux_76 + (viewRef view1 + (cellRef MUX21))) + (instance mux_75 + (viewRef view1 + (cellRef MUX21))) + (instance mux_74 + (viewRef view1 + (cellRef MUX21))) + (instance mux_73 + (viewRef view1 + (cellRef MUX21))) + (instance mux_72 + (viewRef view1 + (cellRef MUX21))) + (instance mux_71 + (viewRef view1 + (cellRef MUX21))) + (instance mux_70 + (viewRef view1 + (cellRef MUX21))) + (instance mux_69 + (viewRef view1 + (cellRef MUX21))) + (instance mux_68 + (viewRef view1 + (cellRef MUX21))) + (instance mux_67 + (viewRef view1 + (cellRef MUX21))) + (instance mux_66 + (viewRef view1 + (cellRef MUX21))) + (instance mux_65 + (viewRef view1 + (cellRef MUX21))) + (instance mux_64 + (viewRef view1 + (cellRef MUX21))) + (instance mux_63 + (viewRef view1 + (cellRef MUX21))) + (instance mux_62 + (viewRef view1 + (cellRef MUX21))) + (instance mux_61 + (viewRef view1 + (cellRef MUX21))) + (instance mux_60 + (viewRef view1 + (cellRef MUX21))) + (instance mux_59 + (viewRef view1 + (cellRef MUX21))) + (instance mux_58 + (viewRef view1 + (cellRef MUX21))) + (instance mux_57 + (viewRef view1 + (cellRef MUX21))) + (instance mux_56 + (viewRef view1 + (cellRef MUX21))) + (instance mux_55 + (viewRef view1 + (cellRef MUX21))) + (instance mux_54 + (viewRef view1 + (cellRef MUX21))) + (instance mux_53 + (viewRef view1 + (cellRef MUX21))) + (instance mux_52 + (viewRef view1 + (cellRef MUX21))) + (instance mux_51 + (viewRef view1 + (cellRef MUX21))) + (instance mux_50 + (viewRef view1 + (cellRef MUX21))) + (instance mux_49 + (viewRef view1 + (cellRef MUX21))) + (instance mux_48 + (viewRef view1 + (cellRef MUX21))) + (instance mux_47 + (viewRef view1 + (cellRef MUX21))) + (instance mux_46 + (viewRef view1 + (cellRef MUX21))) + (instance mux_45 + (viewRef view1 + (cellRef MUX21))) + (instance mux_44 + (viewRef view1 + (cellRef MUX21))) + (instance mux_43 + (viewRef view1 + (cellRef MUX21))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef ADA2 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pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef CEA 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(instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)))) + (net clk + (joined + (portRef WrClock) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef CLKA (instanceRef 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pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef RSTA 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RSTA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)))) + (net RdClockEn + (joined + (portRef RdClockEn) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)) + (portRef SP (instanceRef FF_1)) + (portRef SP (instanceRef FF_0)))) + (net rdclk + (joined + (portRef RdClock) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef CLKB (instanceRef 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pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_0_19)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_1_18)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_2_17)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_3_16)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_4_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_5_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_6_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_7_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_8_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_0_9_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_0_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_1_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_2_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_3_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_4_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_5_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_6_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_7_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_8_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9011204890112048p1395e512_1_9_0)))))))) + (design pmi_ram_dpXbnonesadr9011204890112048p1395e512 + (cellRef pmi_ram_dpXbnonesadr9011204890112048p1395e512 + (libraryRef ORCLIB))) +) diff --git a/CPLD2/impl1/pmi_ram_dpXbnonesadr9211204892112048p1395f582.edn b/CPLD2/impl1/pmi_ram_dpXbnonesadr9211204892112048p1395f582.edn new file mode 100644 index 0000000..643f1d6 --- /dev/null +++ b/CPLD2/impl1/pmi_ram_dpXbnonesadr9211204892112048p1395f582.edn @@ -0,0 +1,4117 @@ +(edif pmi_ram_dpXbnonesadr9211204892112048p1395f582 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 15 14 14 5) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 92 -num_rows 2048 -rdata_width 92 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr9211204892112048p1395f582 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr9211204892112048p1395f582 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(91:0)") 92) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(91:0)") 92) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr9211204892112048p1395f582__PMIP__2048__92__92__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_91 + (viewRef view1 + (cellRef MUX21))) + (instance mux_90 + (viewRef view1 + (cellRef MUX21))) + (instance mux_89 + (viewRef view1 + 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(viewRef view1 + (cellRef MUX21))) + (instance mux_52 + (viewRef view1 + (cellRef MUX21))) + (instance mux_51 + (viewRef view1 + (cellRef MUX21))) + (instance mux_50 + (viewRef view1 + (cellRef MUX21))) + (instance mux_49 + (viewRef view1 + (cellRef MUX21))) + (instance mux_48 + (viewRef view1 + (cellRef MUX21))) + (instance mux_47 + (viewRef view1 + (cellRef MUX21))) + (instance mux_46 + (viewRef view1 + (cellRef MUX21))) + (instance mux_45 + (viewRef view1 + (cellRef MUX21))) + (instance mux_44 + (viewRef view1 + (cellRef MUX21))) + (instance mux_43 + (viewRef view1 + (cellRef MUX21))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef DIB4 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ADB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)) + (portRef CD (instanceRef FF_1)) + (portRef CD (instanceRef FF_0)))) + (net raddr10_ff + (joined + (portRef D (instanceRef FF_0)) + (portRef Q (instanceRef FF_1)))) + (net mdout1_1_0 + (joined + (portRef D1 (instanceRef mux_91)) + (portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)))) + (net mdout1_0_0 + (joined + (portRef D0 (instanceRef mux_91)) + (portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)))) + (net mdout1_1_1 + (joined + (portRef D1 (instanceRef mux_90)) + (portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)))) + (net mdout1_0_1 + (joined + (portRef D0 (instanceRef mux_90)) + (portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)))) + (net mdout1_1_2 + (joined + (portRef D1 (instanceRef mux_89)) + (portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)))) + (net mdout1_0_2 + (joined + (portRef D0 (instanceRef mux_89)) + (portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)))) + (net mdout1_1_3 + (joined + (portRef D1 (instanceRef mux_88)) + (portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)))) + (net mdout1_0_3 + (joined + (portRef D0 (instanceRef mux_88)) + (portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)))) + (net mdout1_1_4 + (joined + (portRef D1 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RSTA (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)))) + (net RdClockEn + (joined + (portRef RdClockEn) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef OCEB (instanceRef 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+ (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_0_21)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_1_20)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_2_19)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_3_18)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_4_17)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_5_16)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_6_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_7_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_8_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_9_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_0_10_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_0_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_1_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_2_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_3_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_4_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_5_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_6_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_7_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_8_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_9_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr9211204892112048p1395f582_1_10_0)))))))) + (design pmi_ram_dpXbnonesadr9211204892112048p1395f582 + (cellRef pmi_ram_dpXbnonesadr9211204892112048p1395f582 + (libraryRef ORCLIB))) +) diff --git a/CPLD3/impl1/NewExtIns_CPLD3_impl1.areasrr b/CPLD3/impl1/NewExtIns_CPLD3_impl1.areasrr new file mode 100644 index 0000000..3deea2c --- /dev/null +++ b/CPLD3/impl1/NewExtIns_CPLD3_impl1.areasrr @@ -0,0 +1,158 @@ +---------------------------------------------------------------------- +Report for cell RelayConTop.verilog + +Register bits: 1206 of 6864 (18%) +PIC Latch: 0 +I/O cells: 14 + Cell usage: + cell count Res Usage(%) + CCU2D 41 100.0 + FD1P3AX 424 100.0 + FD1P3AY 2 100.0 + FD1P3BX 32 100.0 + FD1P3DX 437 100.0 + FD1P3IX 133 100.0 + FD1P3JX 1 100.0 + FD1S3AX 6 100.0 + FD1S3AY 1 100.0 + FD1S3BX 3 100.0 + FD1S3DX 140 100.0 + FD1S3IX 16 100.0 + FD1S3JX 1 100.0 + GSR 1 100.0 + IB 5 100.0 + IFS1P3IX 3 100.0 + IFS1P3JX 1 100.0 + INV 13 100.0 + L6MUX21 73 100.0 + OB 8 100.0 + OBZ 1 100.0 + OFS1P3DX 2 100.0 + OFS1P3JX 4 100.0 + ORCALUT4 1035 100.0 + PFUMX 102 100.0 + PUR 1 100.0 + VHI 13 100.0 + VLO 13 100.0 + jtagconn16 1 100.0 + pmi_distributed_dpram_2s_1s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 1 100.0 + pmi_ram_dp_Z4 1 100.0 +SUB MODULES + BUS_Con_uniq_1 1 100.0 + CPLD_Con_uniq_1 1 100.0 + Reg_file_uniq_1 1 100.0 + relaycontop_la0 1 100.0 + relaycontop_la0_trig 1 100.0 + reveal_coretop 1 100.0 + + TOTAL 2521 +---------------------------------------------------------------------- +Report for cell CPLD_Con_uniq_1.netlist + Instance path: CPLD_Con_3 + Cell usage: + cell count Res Usage(%) + FD1P3IX 8 6.0 + FD1P3JX 1 100.0 + FD1S3IX 6 37.5 + ORCALUT4 34 3.3 + VHI 1 7.7 + VLO 1 7.7 + + TOTAL 51 +---------------------------------------------------------------------- +Report for cell Reg_file_uniq_1.netlist + Instance path: CPLD_Reg_3 + Cell usage: + cell count Res Usage(%) + FD1P3AX 406 95.8 + FD1P3AY 2 100.0 + FD1S3AX 4 66.7 + FD1S3AY 1 100.0 + L6MUX21 72 98.6 + ORCALUT4 243 23.5 + PFUMX 96 94.1 + VHI 1 7.7 + VLO 1 7.7 + + TOTAL 826 +---------------------------------------------------------------------- +Report for cell BUS_Con_uniq_1.netlist + Instance path: Bus_Con_3 + Cell usage: + cell count Res Usage(%) + FD1P3IX 125 94.0 + FD1S3AX 2 33.3 + FD1S3IX 10 62.5 + FD1S3JX 1 100.0 + ORCALUT4 100 9.7 + VHI 1 7.7 + VLO 1 7.7 + + TOTAL 240 +---------------------------------------------------------------------- +Report for cell reveal_coretop.verilog + Instance path: RelayConTop_reveal_coretop_instance + Cell usage: + cell count Res Usage(%) + CCU2D 41 100.0 + FD1P3AX 18 4.2 + FD1P3BX 32 100.0 + FD1P3DX 437 100.0 + FD1S3BX 3 100.0 + FD1S3DX 140 100.0 + INV 12 92.3 + L6MUX21 1 1.4 + ORCALUT4 658 63.6 + PFUMX 6 5.9 + VHI 9 69.2 + VLO 9 69.2 + jtagconn16 1 100.0 + pmi_distributed_dpram_2s_1s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 1 100.0 + pmi_ram_dp_Z4 1 100.0 +SUB MODULES + relaycontop_la0 1 100.0 + relaycontop_la0_trig 1 100.0 + + TOTAL 1371 +---------------------------------------------------------------------- +Report for cell relaycontop_la0.netlist + Instance path: RelayConTop_reveal_coretop_instance.relaycontop_la0_inst_0 + Cell usage: + cell count Res Usage(%) + CCU2D 41 100.0 + FD1P3AX 18 4.2 + FD1P3BX 32 100.0 + FD1P3DX 437 100.0 + FD1S3BX 3 100.0 + FD1S3DX 140 100.0 + INV 12 92.3 + L6MUX21 1 1.4 + ORCALUT4 658 63.6 + PFUMX 6 5.9 + VHI 8 61.5 + VLO 8 61.5 + pmi_distributed_dpram_2s_1s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 1 100.0 + pmi_ram_dp_Z4 1 100.0 +SUB MODULES + relaycontop_la0_trig 1 100.0 + + TOTAL 1367 +---------------------------------------------------------------------- +Report for cell relaycontop_la0_trig.netlist + Instance path: RelayConTop_reveal_coretop_instance.relaycontop_la0_inst_0.trig_u + Cell usage: + cell count Res Usage(%) + CCU2D 9 22.0 + FD1P3AX 16 3.8 + FD1P3DX 29 6.6 + FD1S3BX 3 100.0 + FD1S3DX 22 15.7 + INV 5 38.5 + L6MUX21 1 1.4 + ORCALUT4 119 11.5 + PFUMX 3 2.9 + VHI 5 38.5 + VLO 5 38.5 + pmi_distributed_dpram_2s_1s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 1 100.0 + + TOTAL 218 diff --git a/CPLD3/impl1/NewExtIns_CPLD3_impl1.bit b/CPLD3/impl1/NewExtIns_CPLD3_impl1.bit new file mode 100644 index 0000000..5e6f975 Binary files /dev/null and b/CPLD3/impl1/NewExtIns_CPLD3_impl1.bit differ diff --git a/CPLD3/impl1/NewExtIns_CPLD3_impl1.hub b/CPLD3/impl1/NewExtIns_CPLD3_impl1.hub new file mode 100644 index 0000000..d8aa80f --- /dev/null +++ b/CPLD3/impl1/NewExtIns_CPLD3_impl1.hub @@ -0,0 +1 @@ +HUBID_00 REVEAL_0 diff --git a/CPLD3/impl1/NewExtIns_CPLD3_impl1.jed b/CPLD3/impl1/NewExtIns_CPLD3_impl1.jed new file mode 100644 index 0000000..7ad8497 --- /dev/null +++ b/CPLD3/impl1/NewExtIns_CPLD3_impl1.jed @@ -0,0 +1,11299 @@ +* +NOTE Diamond (64-bit) 3.14.0.75.2 JEDEC Compatible Fuse File.* +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.* +NOTE All Rights Reserved.* +NOTE DATE CREATED: Tue May 26 15:55:28 2026* +NOTE DESIGN NAME: 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+RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/dec0_wre3 RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_en +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2.CN jtaghub16_jtck +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jrstn_i jtaghub16_jrstn +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w.CN jtaghub16_jtck +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jrstn_i jtaghub16_jrstn +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/jtck_i jtaghub16_jtck +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/jrstn_i jtaghub16_jrstn +xo2chub/cdn.CN jtaghub16_jtck +xo2chub/jrstn_i jtaghub16_jrstn +[ END MERGED ] +[ START CLIPPED ] +xo2chub/GND +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/popfeedthru_unused +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/scuba_vlo +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/scuba_vhi +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren_jtck +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/VCC +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_te[2] +xo2chub/VCC +xo2chub/bit_count_cry_0_COUT[3] +xo2chub/rom_rd_addr_cry_0_S0[0] +xo2chub/N_2 +xo2chub/rom_rd_addr_s_0_S1[7] +xo2chub/rom_rd_addr_s_0_COUT[7] +xo2chub/jtdo2_int_prm_16_0_0_S1 +xo2chub/jtdo2_int_prm_16_0_0_S0 +xo2chub/N_3 +xo2chub/er2_tdo[14] +xo2chub/er2_tdo[15] +xo2chub/jtdo2_int_prm_15_0_0_S1 +xo2chub/jtdo2_int_prm_15_0_0_S0 +xo2chub/er2_tdo[12] +xo2chub/er2_tdo[13] +xo2chub/jtdo2_int_prm_13_0_0_S1 +xo2chub/jtdo2_int_prm_13_0_0_S0 +xo2chub/er2_tdo[10] +xo2chub/er2_tdo[11] +xo2chub/jtdo2_int_prm_11_0_0_S1 +xo2chub/jtdo2_int_prm_11_0_0_S0 +xo2chub/er2_tdo[8] +xo2chub/er2_tdo[9] +xo2chub/jtdo2_int_prm_9_0_0_S1 +xo2chub/jtdo2_int_prm_9_0_0_S0 +xo2chub/er2_tdo[6] +xo2chub/er2_tdo[7] +xo2chub/jtdo2_int_prm_7_0_0_S1 +xo2chub/jtdo2_int_prm_7_0_0_S0 +xo2chub/er2_tdo[4] +xo2chub/er2_tdo[5] +xo2chub/jtdo2_int_prm_5_0_0_S1 +xo2chub/jtdo2_int_prm_5_0_0_S0 +xo2chub/er2_tdo[2] +xo2chub/er2_tdo[3] +xo2chub/jtdo2_int_prm_3_0_0_S1 +xo2chub/jtdo2_int_prm_3_0_0_S0 +xo2chub/er2_tdo[1] +xo2chub/jtdo2_int_prm_1_0_0_S0 +xo2chub/jtdo2_int_prm_1_0_0_COUT +xo2chub/ip_enable[15] +xo2chub/genblk7.un1_jtagf_u_1 +xo2chub/genblk7.un1_jtagf_u +xo2chub/tdoa +xo2chub/tdia +xo2chub/tmsa +xo2chub/tcka +xo2chub/cdn +xo2chub/bit_count_cry_0_S0[0] +xo2chub/N_1 +VCC +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/VCC +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/GND +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0_COUT[9] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0_S0[0] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_2 +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0_COUT[9] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0_S0[0] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_3 +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0_COUT[9] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0_S0[0] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_4 +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0_COUT[9] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0_S0[0] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_1 +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0_S0[0] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1 +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s_0_S1[5] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s_0_COUT[5] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0_S0[0] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2 +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0_COUT[5] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/VCC +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/GND +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[4] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0_S0[0] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_1 +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s_0_S1[15] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s_0_COUT[15] +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/mem_0_0/DO2 +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/mem_0_0/DO3 +RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[3] +[ END CLIPPED ] +[ START DESIGN PREFS ] +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.14.0.75.2 -- WARNING: Map write only section -- Tue May 26 15:55:16 2026 + +SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; +LOCATE COMP "o_miso" SITE "AA14" ; +LOCATE COMP "i_sys_clk" SITE "B9" ; +LOCATE COMP "o_err" SITE "AB16" ; +LOCATE COMP "o_PMU_RC[3]" SITE "P18" ; +LOCATE COMP "o_PMU_RC[2]" SITE "P19" ; +LOCATE COMP "o_PMU_RC[1]" SITE "N18" ; +LOCATE COMP "o_PMU_RC[0]" SITE "V2" ; +LOCATE COMP "i_cs" SITE "AB11" ; +LOCATE COMP "i_mosi" SITE "AB12" ; +LOCATE COMP "i_sclk" SITE "AA10" ; +LOCATE COMP "i_rst_n" SITE "Y14" ; +SCHEMATIC END ; +[ END DESIGN PREFS ] diff --git a/CPLD3/impl1/NewExtIns_CPLD3_impl1_map.hrr b/CPLD3/impl1/NewExtIns_CPLD3_impl1_map.hrr new file mode 100644 index 0000000..8c7167c --- /dev/null +++ b/CPLD3/impl1/NewExtIns_CPLD3_impl1_map.hrr @@ -0,0 +1,176 @@ +--------------------------------------------------- +Report for cell RelayConTop + Instance path: RelayConTop + Cell usage: + cell count Res Usage(%) + SLIC 746.00 100.0 + IOLGC 9.00 100.0 + LUT4 1154.00 100.0 + DISTRAM 3.00 100.0 + IOREG 9 100.0 + IOBUF 14 100.0 + PFUREG 1252 100.0 + RIPPLE 58 100.0 + EBR 24 100.0 +SUB MODULES + cell count SLC Usage(%) + xo2chub 1 4.5 + reveal_coretop 1 56.7 + Reg_file_uniq_1 1 28.6 + CPLD_Con_uniq_1 1 1.8 + BUS_Con_uniq_1 1 8.3 +--------------------------------------------------- +Report for cell CPLD_Con_uniq_1 + Instance path: RelayConTop/CPLD_Con_3 + Cell usage: + cell count Res Usage(%) + SLIC 13.42 1.8 + LUT4 34.00 2.9 + PFUREG 15 1.2 +--------------------------------------------------- +Report for cell Reg_file_uniq_1 + Instance path: RelayConTop/CPLD_Reg_3 + Cell usage: + cell count Res Usage(%) + SLIC 213.53 28.6 + LUT4 243.00 21.1 + PFUREG 413 33.0 +--------------------------------------------------- +Report for cell BUS_Con_uniq_1 + Instance path: RelayConTop/Bus_Con_3 + Cell usage: + cell count Res Usage(%) + SLIC 61.75 8.3 + LUT4 100.00 8.7 + PFUREG 138 11.0 +--------------------------------------------------- +Report for cell reveal_coretop + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance + Cell usage: + cell count Res Usage(%) + SLIC 423.22 56.7 + LUT4 763.00 66.1 + DISTRAM 2.00 66.7 + PFUREG 634 50.6 + RIPPLE 41 70.7 + EBR 24 100.0 +SUB MODULES + cell count SLC Usage(%) + relaycontop_la0 1 56.7 +--------------------------------------------------- +Report for cell relaycontop_la0 + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0 + Cell usage: + cell count Res Usage(%) + SLIC 423.22 56.7 + LUT4 763.00 66.1 + DISTRAM 2.00 66.7 + PFUREG 634 50.6 + RIPPLE 41 70.7 + EBR 24 100.0 +SUB MODULES + cell count SLC Usage(%) + rvl_tm_Z3 1 26.6 +rvl_jtag_int_104s_1s_0s_0s_7s_104s_104s 1 21.3 + relaycontop_la0_trig 1 8.7 +--------------------------------------------------- +Report for cell relaycontop_la0_trig + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u + Cell usage: + cell count Res Usage(%) + SLIC 65.10 8.7 + LUT4 118.00 10.2 + DISTRAM 2.00 66.7 + PFUREG 72 5.8 + RIPPLE 9 15.5 +SUB MODULES + cell count SLC Usage(%) + rvl_tu_1s_0s_0s_0s_1s 1 1.3 + rvl_te_Z1 1 5.6 + rvl_tcnt_1s_3s_1_0s 1 1.4 + rvl_decode_1s_1s 1 0.3 +--------------------------------------------------- +Report for cell rvl_decode_1s_1s + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u + Cell usage: + cell count Res Usage(%) + SLIC 2.23 0.3 + LUT4 8.50 0.7 +--------------------------------------------------- +Report for cell rvl_tu_1s_0s_0s_0s_1s + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0 + Cell usage: + cell count Res Usage(%) + SLIC 9.62 1.3 + LUT4 13.00 1.1 + PFUREG 8 0.6 +--------------------------------------------------- +Report for cell rvl_te_Z1 + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0 + Cell usage: + cell count Res Usage(%) + SLIC 41.70 5.6 + LUT4 65.50 5.7 + DISTRAM 2.00 66.7 + PFUREG 52 4.2 + RIPPLE 9 15.5 +SUB MODULES + cell count SLC Usage(%) +pmi_distributed_dpramXbnoner212pb07f9c9 1 0.3 +--------------------------------------------------- +Report for cell pmi_distributed_dpramXbnoner212pb07f9c9 + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram + Cell usage: + cell count Res Usage(%) + SLIC 2.50 0.3 + LUT4 1.00 0.1 + DISTRAM 2.00 66.7 + PFUREG 2 0.2 +--------------------------------------------------- +Report for cell rvl_tcnt_1s_3s_1_0s + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0 + Cell usage: + cell count Res Usage(%) + SLIC 10.32 1.4 + LUT4 27.00 2.3 + PFUREG 12 1.0 +--------------------------------------------------- +Report for cell rvl_jtag_int_104s_1s_0s_0s_7s_104s_104s + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u + Cell usage: + cell count Res Usage(%) + SLIC 159.08 21.3 + LUT4 373.50 32.4 + PFUREG 229 18.3 + RIPPLE 8 13.8 +--------------------------------------------------- +Report for cell rvl_tm_Z3 + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u + Cell usage: + cell count Res Usage(%) + SLIC 198.58 26.6 + LUT4 270.00 23.4 + PFUREG 333 26.6 + RIPPLE 24 41.4 + EBR 24 100.0 +SUB MODULES + cell count SLC Usage(%) +pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b 1 3.6 +--------------------------------------------------- +Report for cell pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b + Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem + Cell usage: + cell count Res Usage(%) + SLIC 26.50 3.6 + LUT4 104.00 9.0 + PFUREG 2 0.2 + EBR 24 100.0 +--------------------------------------------------- +Report for cell xo2chub + Instance path: RelayConTop/xo2chub + Cell usage: + cell count Res Usage(%) + SLIC 33.50 4.5 + LUT4 12.00 1.0 + PFUREG 51 4.1 + RIPPLE 17 29.3 diff --git a/CPLD3/impl1/NewExtIns_CPLD3_impl1_synplify.lpf b/CPLD3/impl1/NewExtIns_CPLD3_impl1_synplify.lpf new file mode 100644 index 0000000..23af319 --- /dev/null +++ b/CPLD3/impl1/NewExtIns_CPLD3_impl1_synplify.lpf @@ -0,0 +1,26 @@ +# +# Logical Preferences generated for Lattice by Synplify map202309lat, Build 191R. +# + +# Period Constraints +#FREQUENCY NET "RelayConTop_reveal_coretop_instance/jtck[0]" 200.0 MHz; +#FREQUENCY PORT "i_sys_clk" 200.0 MHz; + + +# Output Constraints + +# Input Constraints + +# Point-to-point Delay Constraints + + + +# Block Path Constraints +#BLOCK PATH FROM CLKNET "i_sys_clk_c" TO CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]"; +#BLOCK PATH FROM CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]" TO CLKNET "i_sys_clk_c"; +#BLOCK PATH FROM CLKNET "i_sys_clk_c" TO CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]"; +#BLOCK PATH FROM CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]" TO CLKNET "i_sys_clk_c"; + +BLOCK ASYNCPATHS; + +# End of generated Logical Preferences. diff --git a/CPLD3/impl1/NewExtIns_CPLD3_impl1_synplify_tmp2.lpf b/CPLD3/impl1/NewExtIns_CPLD3_impl1_synplify_tmp2.lpf new file mode 100644 index 0000000..e69de29 diff --git a/CPLD3/impl1/NewExtIns_CPLD3_impl1_synplify_tmp4.lpf b/CPLD3/impl1/NewExtIns_CPLD3_impl1_synplify_tmp4.lpf new file mode 100644 index 0000000..e69de29 diff --git a/CPLD3/impl1/NewExtIns_CPLD3_impl1_synplify_tmp8.lpf b/CPLD3/impl1/NewExtIns_CPLD3_impl1_synplify_tmp8.lpf new file mode 100644 index 0000000..e69de29 diff --git a/CPLD3/impl1/_cmd._cml b/CPLD3/impl1/_cmd._cml new file mode 100644 index 0000000..1c4dad2 --- /dev/null +++ b/CPLD3/impl1/_cmd._cml @@ -0,0 +1 @@ +-link -encrypt -top RelayConTop -osyn /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD3/impl1/synwork/NewExtIns_CPLD3_impl1_comp.srs /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD3/impl1/synwork/layer0.srs -jobname linker \ No newline at end of file diff --git a/CPLD3/impl1/impl1.xcf b/CPLD3/impl1/impl1.xcf new file mode 100644 index 0000000..46f365d --- /dev/null +++ b/CPLD3/impl1/impl1.xcf @@ -0,0 +1,52 @@ + + + + + + JTAG + + + 1 + Lattice + MachXO2 + LCMXO2-7000HC + 0x012bd043 + All + LCMXO2-7000HC + + 8 + 11111111 + 1 + 0 + + D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD3/impl1/NewExtIns_CPLD3_impl1.jed + 01/19/26 18:24:04 + 0x4480 + FLASH Erase,Program,Verify + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB + EzUSB-0 + \\?\usb#vid_1134&pid_8001#9&2fe42d87&0&2# + + diff --git a/CPLD3/impl1/pmi_distributed_dpramXbnoner212pb07f9c9.edn b/CPLD3/impl1/pmi_distributed_dpramXbnoner212pb07f9c9.edn new file mode 100644 index 0000000..d47a57a --- /dev/null +++ b/CPLD3/impl1/pmi_distributed_dpramXbnoner212pb07f9c9.edn @@ -0,0 +1,227 @@ +(edif pmi_distributed_dpramXbnoner212pb07f9c9 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 5 26 15 55 16) + (program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2")))) + (comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 2 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner212pb07f9c9 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell ROM16X1A + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port AD3 + (direction INPUT)) + (port AD2 + (direction INPUT)) + (port AD1 + (direction INPUT)) + (port AD0 + (direction INPUT)) + (port DO0 + (direction OUTPUT))))) + (cell DPR16X4C + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DI0 + (direction INPUT)) + (port DI1 + (direction INPUT)) + (port DI2 + (direction INPUT)) + (port DI3 + (direction INPUT)) + (port WCK + (direction INPUT)) + (port WRE + (direction INPUT)) + (port RAD0 + (direction INPUT)) + (port RAD1 + (direction INPUT)) + (port RAD2 + (direction INPUT)) + (port RAD3 + (direction INPUT)) + (port WAD0 + (direction INPUT)) + (port WAD1 + (direction INPUT)) + (port WAD2 + (direction INPUT)) + (port WAD3 + (direction INPUT)) + (port DO0 + (direction OUTPUT)) + (port DO1 + (direction OUTPUT)) + (port DO2 + (direction OUTPUT)) + (port DO3 + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell pmi_distributed_dpramXbnoner212pb07f9c9 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(0:0)") 1) + (direction INPUT)) + (port (array (rename Data "Data(1:0)") 2) + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WE + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(0:0)") 1) + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port (array (rename Q "Q(1:0)") 2) + (direction OUTPUT))) + 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mux_64 + (viewRef view1 + (cellRef MUX21))) + (instance mux_63 + (viewRef view1 + (cellRef MUX21))) + (instance mux_62 + (viewRef view1 + (cellRef MUX21))) + (instance mux_61 + (viewRef view1 + (cellRef MUX21))) + (instance mux_60 + (viewRef view1 + (cellRef MUX21))) + (instance mux_59 + (viewRef view1 + (cellRef MUX21))) + (instance mux_58 + (viewRef view1 + (cellRef MUX21))) + (instance mux_57 + (viewRef view1 + (cellRef MUX21))) + (instance mux_56 + (viewRef view1 + (cellRef MUX21))) + (instance mux_55 + (viewRef view1 + (cellRef MUX21))) + (instance mux_54 + (viewRef view1 + (cellRef MUX21))) + (instance mux_53 + (viewRef view1 + (cellRef MUX21))) + (instance mux_52 + (viewRef view1 + (cellRef MUX21))) + (instance mux_51 + (viewRef view1 + (cellRef MUX21))) + (instance mux_50 + (viewRef view1 + (cellRef MUX21))) + (instance mux_49 + (viewRef view1 + (cellRef MUX21))) + (instance mux_48 + (viewRef view1 + (cellRef MUX21))) + (instance mux_47 + (viewRef view1 + (cellRef MUX21))) + (instance mux_46 + (viewRef view1 + (cellRef MUX21))) + (instance mux_45 + (viewRef view1 + (cellRef MUX21))) + (instance mux_44 + (viewRef view1 + (cellRef MUX21))) + (instance mux_43 + (viewRef view1 + (cellRef MUX21))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef CSA1 (instanceRef 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DIB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB1 (instanceRef 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(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef DIB7 (instanceRef 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(portRef WEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef DIB3 (instanceRef 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pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net RdClockEn + (joined + (portRef RdClockEn) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef CEB (instanceRef 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(portRef CEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef OCEB (instanceRef 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pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)) + (portRef D (instanceRef FF_1)))) + (net raddr9 + (joined + (portRef (member RdAddress 1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net raddr8 + (joined + (portRef (member RdAddress 2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net raddr7 + (joined + (portRef (member RdAddress 3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_0_23)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_1_22)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_2_21)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_3_20)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_4_19)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_5_18)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_6_17)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_7_16)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_8_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_9_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_10_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_0_11_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_0_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_1_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_2_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_3_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_4_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_5_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_6_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_7_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_8_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_9_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_10_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr100112048100112048p13b98964_1_11_0)))))))) + (design pmi_ram_dpXbnonesadr100112048100112048p13b98964 + (cellRef pmi_ram_dpXbnonesadr100112048100112048p13b98964 + (libraryRef ORCLIB))) +) diff --git a/CPLD3/impl1/pmi_ram_dpXbnonesadr101112048101112048p13b9937e.edn b/CPLD3/impl1/pmi_ram_dpXbnonesadr101112048101112048p13b9937e.edn new file mode 100644 index 0000000..81ed3d5 --- /dev/null +++ b/CPLD3/impl1/pmi_ram_dpXbnonesadr101112048101112048p13b9937e.edn @@ -0,0 +1,4470 @@ +(edif pmi_ram_dpXbnonesadr101112048101112048p13b9937e + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 13 14 5 26) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 101 -num_rows 2048 -rdata_width 101 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr101112048101112048p13b9937e -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr101112048101112048p13b9937e + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(100:0)") 101) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(100:0)") 101) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr101112048101112048p13b9937e__PMIP__2048__101__101__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string 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FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_100 + (viewRef view1 + (cellRef MUX21))) + (instance mux_99 + (viewRef view1 + (cellRef MUX21))) + (instance mux_98 + (viewRef view1 + (cellRef MUX21))) + (instance mux_97 + (viewRef view1 + (cellRef MUX21))) + (instance mux_96 + (viewRef view1 + (cellRef MUX21))) + (instance mux_95 + (viewRef view1 + (cellRef MUX21))) + (instance mux_94 + (viewRef view1 + (cellRef MUX21))) + (instance mux_93 + (viewRef view1 + (cellRef MUX21))) + (instance mux_92 + (viewRef view1 + (cellRef MUX21))) + (instance mux_91 + (viewRef view1 + (cellRef MUX21))) + (instance mux_90 + (viewRef view1 + (cellRef MUX21))) + (instance mux_89 + (viewRef view1 + (cellRef MUX21))) + (instance mux_88 + (viewRef view1 + (cellRef MUX21))) + (instance mux_87 + (viewRef view1 + (cellRef MUX21))) + (instance mux_86 + (viewRef view1 + (cellRef MUX21))) + (instance mux_85 + (viewRef view1 + (cellRef MUX21))) + (instance mux_84 + (viewRef view1 + (cellRef MUX21))) + (instance mux_83 + (viewRef view1 + (cellRef MUX21))) + (instance mux_82 + (viewRef view1 + (cellRef MUX21))) + (instance mux_81 + (viewRef view1 + (cellRef MUX21))) + (instance mux_80 + (viewRef view1 + (cellRef MUX21))) + (instance mux_79 + (viewRef view1 + (cellRef MUX21))) + (instance mux_78 + (viewRef view1 + (cellRef MUX21))) + (instance mux_77 + (viewRef view1 + (cellRef MUX21))) + (instance mux_76 + (viewRef view1 + (cellRef MUX21))) + (instance mux_75 + (viewRef view1 + (cellRef MUX21))) + (instance mux_74 + (viewRef view1 + (cellRef MUX21))) + (instance mux_73 + (viewRef view1 + (cellRef MUX21))) + (instance mux_72 + (viewRef view1 + (cellRef MUX21))) + (instance mux_71 + (viewRef view1 + (cellRef MUX21))) + (instance mux_70 + (viewRef view1 + (cellRef MUX21))) + (instance mux_69 + (viewRef view1 + (cellRef MUX21))) + (instance mux_68 + (viewRef view1 + (cellRef MUX21))) + (instance mux_67 + (viewRef view1 + (cellRef MUX21))) + (instance mux_66 + (viewRef view1 + (cellRef MUX21))) + (instance mux_65 + (viewRef view1 + (cellRef MUX21))) + (instance mux_64 + (viewRef view1 + (cellRef MUX21))) + (instance mux_63 + (viewRef view1 + (cellRef MUX21))) + (instance mux_62 + (viewRef view1 + (cellRef MUX21))) + (instance mux_61 + (viewRef view1 + (cellRef MUX21))) + (instance mux_60 + (viewRef view1 + (cellRef MUX21))) + (instance mux_59 + (viewRef view1 + (cellRef MUX21))) + (instance mux_58 + (viewRef view1 + (cellRef MUX21))) + (instance mux_57 + (viewRef view1 + (cellRef MUX21))) + (instance mux_56 + (viewRef view1 + (cellRef MUX21))) + (instance mux_55 + (viewRef view1 + (cellRef MUX21))) + (instance mux_54 + (viewRef view1 + (cellRef MUX21))) + (instance mux_53 + (viewRef view1 + (cellRef MUX21))) + (instance mux_52 + (viewRef view1 + (cellRef MUX21))) + (instance mux_51 + (viewRef view1 + (cellRef MUX21))) + (instance mux_50 + (viewRef view1 + (cellRef MUX21))) + (instance mux_49 + (viewRef view1 + (cellRef MUX21))) + (instance mux_48 + (viewRef view1 + (cellRef MUX21))) + (instance mux_47 + (viewRef view1 + (cellRef MUX21))) + (instance mux_46 + (viewRef view1 + (cellRef MUX21))) + (instance mux_45 + (viewRef view1 + (cellRef MUX21))) + (instance mux_44 + (viewRef view1 + (cellRef MUX21))) + (instance mux_43 + (viewRef view1 + (cellRef MUX21))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef CSB2 (instanceRef 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pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)) + (portRef CSA2 (instanceRef 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pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net RdClockEn + (joined + (portRef RdClockEn) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)) + (portRef SP (instanceRef FF_1)) + (portRef SP (instanceRef FF_0)))) + (net rdclk + (joined + (portRef RdClock) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)) + (portRef CK (instanceRef FF_1)) + (portRef CK (instanceRef FF_0)))) + (net wren + (joined + (portRef WE) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef WEA (instanceRef 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WEA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net datain100 + (joined + (portRef (member Data 0)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net datain99 + (joined + (portRef (member Data 1)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net datain98 + (joined + (portRef (member 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pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_0_23)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_1_22)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_2_21)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_3_20)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_4_19)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_5_18)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_6_17)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_7_16)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_8_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_9_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_10_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_0_11_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_0_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_1_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_2_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_3_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_4_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_5_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_6_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_7_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_8_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_9_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_10_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e_1_11_0)))))))) + (design pmi_ram_dpXbnonesadr101112048101112048p13b9937e + (cellRef pmi_ram_dpXbnonesadr101112048101112048p13b9937e + (libraryRef ORCLIB))) +) diff --git a/CPLD3/impl1/pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b.edn b/CPLD3/impl1/pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b.edn new file mode 100644 index 0000000..64cbda3 --- /dev/null +++ b/CPLD3/impl1/pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b.edn @@ -0,0 +1,4527 @@ +(edif pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 5 26 15 55 16) + (program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2")))) + (comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 104 -num_rows 2048 -rdata_width 104 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(103:0)") 104) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(103:0)") 104) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string 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+ (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4 + (viewRef view1 + (cellRef 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(property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b__PMIP__2048__104__104__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_103 + (viewRef view1 + (cellRef MUX21))) + (instance mux_102 + (viewRef view1 + (cellRef MUX21))) + (instance mux_101 + (viewRef view1 + (cellRef MUX21))) + (instance mux_100 + (viewRef view1 + (cellRef MUX21))) + (instance mux_99 + (viewRef view1 + (cellRef MUX21))) + (instance mux_98 + (viewRef view1 + (cellRef MUX21))) + (instance mux_97 + (viewRef view1 + (cellRef MUX21))) + (instance mux_96 + (viewRef view1 + (cellRef MUX21))) + (instance mux_95 + (viewRef view1 + (cellRef MUX21))) + (instance mux_94 + (viewRef view1 + (cellRef MUX21))) + (instance mux_93 + (viewRef view1 + (cellRef MUX21))) + (instance mux_92 + (viewRef view1 + (cellRef MUX21))) + (instance mux_91 + (viewRef view1 + (cellRef MUX21))) + (instance mux_90 + (viewRef view1 + (cellRef MUX21))) + (instance mux_89 + (viewRef view1 + (cellRef MUX21))) + (instance mux_88 + (viewRef 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(instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef WEB (instanceRef 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(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef DIB2 (instanceRef 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ADB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef CSA2 (instanceRef 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pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net RdClockEn + (joined + (portRef RdClockEn) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)) + (portRef SP (instanceRef FF_1)) + (portRef SP (instanceRef FF_0)))) + (net rdclk + (joined + (portRef RdClock) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)) + (portRef CK (instanceRef FF_1)) + (portRef CK (instanceRef FF_0)))) + (net wren + (joined + (portRef WE) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net datain103 + (joined + (portRef (member Data 0)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net datain102 + (joined + (portRef (member Data 1)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net datain101 + (joined + (portRef (member Data 2)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net datain100 + (joined + (portRef (member Data 3)) + (portRef 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(instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADB6 (instanceRef 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pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADB4 (instanceRef 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(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_0_23)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_1_22)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_2_21)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_3_20)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_4_19)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_5_18)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_6_17)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_7_16)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_8_15)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_9_14)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_10_13)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_0_11_12)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_0_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_1_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_2_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_3_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_4_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_5_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_6_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_7_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_8_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_9_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_10_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b_1_11_0)))))))) + (design pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b + (cellRef pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b + (libraryRef ORCLIB))) +) diff --git a/CPLD3/impl1/pmi_ram_dpXbnonesadr11120481112048p1371b9e1.edn b/CPLD3/impl1/pmi_ram_dpXbnonesadr11120481112048p1371b9e1.edn new file mode 100644 index 0000000..2821193 --- /dev/null +++ b/CPLD3/impl1/pmi_ram_dpXbnonesadr11120481112048p1371b9e1.edn @@ -0,0 +1,413 @@ +(edif pmi_ram_dpXbnonesadr11120481112048p1371b9e1 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 5 22 15 39 37) + (program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2")))) + (comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 1 -num_rows 2048 -rdata_width 1 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr11120481112048p1371b9e1 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr11120481112048p1371b9e1 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(0:0)") 1) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(0:0)") 1) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr11120481112048p1371b9e1__PMIP__2048__1__1__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net dataout0 + (joined + (portRef (member Q 0)) + (portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net WrClockEn + (joined + (portRef WrClockEn) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net clk + (joined + (portRef WrClock) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net Reset + (joined + (portRef Reset) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net RdClockEn + (joined + (portRef RdClockEn) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net rdclk + (joined + (portRef RdClock) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net wren + (joined + (portRef WE) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net datain0 + (joined + (portRef (member Data 0)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net raddr10 + (joined + (portRef (member RdAddress 0)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net raddr9 + (joined + (portRef (member RdAddress 1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net raddr8 + (joined + (portRef (member RdAddress 2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net raddr7 + (joined + (portRef (member RdAddress 3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1_0_0_0)))))))) + (design pmi_ram_dpXbnonesadr11120481112048p1371b9e1 + (cellRef pmi_ram_dpXbnonesadr11120481112048p1371b9e1 + (libraryRef ORCLIB))) +) diff --git a/CPLD3/impl1/pmi_ram_dpXbnonesadr1211204812112048p1395b04f.edn b/CPLD3/impl1/pmi_ram_dpXbnonesadr1211204812112048p1395b04f.edn new file mode 100644 index 0000000..c138126 --- /dev/null +++ b/CPLD3/impl1/pmi_ram_dpXbnonesadr1211204812112048p1395b04f.edn @@ -0,0 +1,672 @@ +(edif pmi_ram_dpXbnonesadr1211204812112048p1395b04f + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 19 16 42 24) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 12 -num_rows 2048 -rdata_width 12 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr1211204812112048p1395b04f -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr1211204812112048p1395b04f + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(11:0)") 12) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(11:0)") 12) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr1211204812112048p1395b04f__PMIP__2048__12__12__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr1211204812112048p1395b04f__PMIP__2048__12__12__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr1211204812112048p1395b04f__PMIP__2048__12__12__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net dataout11 + (joined + (portRef (member Q 0)) + (portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net dataout10 + (joined + (portRef (member Q 1)) + (portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net dataout9 + (joined + (portRef (member Q 2)) + (portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net dataout8 + (joined + (portRef (member Q 3)) + (portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net dataout7 + (joined + (portRef (member Q 4)) + (portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)))) + (net dataout6 + (joined + (portRef (member Q 5)) + (portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)))) + (net dataout5 + (joined + (portRef (member Q 6)) + (portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)))) + (net dataout4 + (joined + (portRef (member Q 7)) + (portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)))) + (net dataout3 + (joined + (portRef (member Q 8)) + (portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)))) + (net dataout2 + (joined + (portRef (member Q 9)) + (portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)))) + (net dataout1 + (joined + (portRef (member Q 10)) + (portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)))) + (net dataout0 + (joined + (portRef (member Q 11)) + (portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)))) + (net WrClockEn + (joined + (portRef WrClockEn) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net clk + (joined + (portRef WrClock) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net Reset + (joined + (portRef Reset) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net RdClockEn + (joined + (portRef RdClockEn) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net rdclk + (joined + (portRef RdClock) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net wren + (joined + (portRef WE) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net datain11 + (joined + (portRef (member Data 0)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net datain10 + (joined + (portRef (member Data 1)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net datain9 + (joined + (portRef (member Data 2)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net datain8 + (joined + (portRef (member Data 3)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net datain7 + (joined + (portRef (member Data 4)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)))) + (net datain6 + (joined + (portRef (member Data 5)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)))) + (net datain5 + (joined + (portRef (member Data 6)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)))) + (net datain4 + (joined + (portRef (member Data 7)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)))) + (net datain3 + (joined + (portRef (member Data 8)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)))) + (net datain2 + (joined + (portRef (member Data 9)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)))) + (net datain1 + (joined + (portRef (member Data 10)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)))) + (net datain0 + (joined + (portRef (member Data 11)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)))) + (net raddr10 + (joined + (portRef (member RdAddress 0)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net raddr9 + (joined + (portRef (member RdAddress 1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net raddr8 + (joined + (portRef (member RdAddress 2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net raddr7 + (joined + (portRef (member RdAddress 3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_0_2)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_1_1)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f_0_2_0)))))))) + (design pmi_ram_dpXbnonesadr1211204812112048p1395b04f + (cellRef pmi_ram_dpXbnonesadr1211204812112048p1395b04f + (libraryRef ORCLIB))) +) diff --git a/CPLD3/impl1/pmi_ram_dpXbnonesadr41120484112048p1371d0a0.edn b/CPLD3/impl1/pmi_ram_dpXbnonesadr41120484112048p1371d0a0.edn new file mode 100644 index 0000000..feec6a7 --- /dev/null +++ b/CPLD3/impl1/pmi_ram_dpXbnonesadr41120484112048p1371d0a0.edn @@ -0,0 +1,434 @@ +(edif pmi_ram_dpXbnonesadr41120484112048p1371d0a0 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 5 15 18 14 2) + (program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2")))) + (comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 4 -num_rows 2048 -rdata_width 4 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr41120484112048p1371d0a0 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction 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OUTPUT))))) + (cell pmi_ram_dpXbnonesadr41120484112048p1371d0a0 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(3:0)") 4) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(3:0)") 4) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr41120484112048p1371d0a0__PMIP__2048__4__4__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0)) + (portRef CSA1 (instanceRef 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(portRef CEB (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0)))) + (net rdclk + (joined + (portRef RdClock) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0)))) + (net wren + (joined + (portRef WE) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0)))) + (net datain3 + (joined + (portRef (member Data 0)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0)))) + (net datain2 + (joined + (portRef (member Data 1)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0)))) + (net datain1 + (joined + (portRef (member Data 2)) + (portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0)))) + (net datain0 + (joined + (portRef (member Data 3)) + (portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr41120484112048p1371d0a0_0_0_0)))) + (net raddr10 + (joined + (portRef (member RdAddress 0)) + (portRef ADB12 (instanceRef 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pmi_ram_dpXbnonesadr4311204843112048p1395d432 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction 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(port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(42:0)") 43) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4311204843112048p1395d432__PMIP__2048__43__43__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4311204843112048p1395d432__PMIP__2048__43__43__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4311204843112048p1395d432__PMIP__2048__43__43__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4311204843112048p1395d432__PMIP__2048__43__43__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4311204843112048p1395d432__PMIP__2048__43__43__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4311204843112048p1395d432__PMIP__2048__43__43__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4311204843112048p1395d432__PMIP__2048__43__43__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4311204843112048p1395d432__PMIP__2048__43__43__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4311204843112048p1395d432__PMIP__2048__43__43__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4311204843112048p1395d432__PMIP__2048__43__43__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef DIB4 (instanceRef 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pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_0_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_1_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_2_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_3_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_0_4_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_0_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_1_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_2_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_3_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4311204843112048p1395d432_1_4_0)))))))) + (design pmi_ram_dpXbnonesadr4311204843112048p1395d432 + (cellRef pmi_ram_dpXbnonesadr4311204843112048p1395d432 + (libraryRef ORCLIB))) +) diff --git a/CPLD3/impl1/pmi_ram_dpXbnonesadr4511204845112048p1395e474.edn b/CPLD3/impl1/pmi_ram_dpXbnonesadr4511204845112048p1395e474.edn new file mode 100644 index 0000000..7c38be8 --- /dev/null +++ b/CPLD3/impl1/pmi_ram_dpXbnonesadr4511204845112048p1395e474.edn @@ -0,0 +1,2132 @@ +(edif pmi_ram_dpXbnonesadr4511204845112048p1395e474 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 19 17 16 54) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 45 -num_rows 2048 -rdata_width 45 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr4511204845112048p1395e474 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr4511204845112048p1395e474 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(44:0)") 45) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(44:0)") 45) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4511204845112048p1395e474__PMIP__2048__45__45__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4511204845112048p1395e474__PMIP__2048__45__45__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4511204845112048p1395e474__PMIP__2048__45__45__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4511204845112048p1395e474__PMIP__2048__45__45__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4511204845112048p1395e474__PMIP__2048__45__45__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4511204845112048p1395e474__PMIP__2048__45__45__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4511204845112048p1395e474__PMIP__2048__45__45__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4511204845112048p1395e474__PMIP__2048__45__45__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4511204845112048p1395e474__PMIP__2048__45__45__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4511204845112048p1395e474__PMIP__2048__45__45__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_44 + (viewRef view1 + (cellRef MUX21))) + (instance mux_43 + (viewRef view1 + (cellRef MUX21))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + 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MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef DIB7 (instanceRef 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pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_0_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_1_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_2_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_3_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_0_4_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_0_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_1_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_2_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_3_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4511204845112048p1395e474_1_4_0)))))))) + (design pmi_ram_dpXbnonesadr4511204845112048p1395e474 + (cellRef pmi_ram_dpXbnonesadr4511204845112048p1395e474 + (libraryRef ORCLIB))) +) diff --git a/CPLD3/impl1/pmi_ram_dpXbnonesadr4911204849112048p1396061b.edn b/CPLD3/impl1/pmi_ram_dpXbnonesadr4911204849112048p1396061b.edn new file mode 100644 index 0000000..623374c --- /dev/null +++ b/CPLD3/impl1/pmi_ram_dpXbnonesadr4911204849112048p1396061b.edn @@ -0,0 +1,2390 @@ +(edif pmi_ram_dpXbnonesadr4911204849112048p1396061b + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 19 17 32 24) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 49 -num_rows 2048 -rdata_width 49 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr4911204849112048p1396061b -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr4911204849112048p1396061b + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(48:0)") 49) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(48:0)") 49) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4911204849112048p1396061b__PMIP__2048__49__49__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4911204849112048p1396061b__PMIP__2048__49__49__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4911204849112048p1396061b__PMIP__2048__49__49__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4911204849112048p1396061b__PMIP__2048__49__49__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4911204849112048p1396061b__PMIP__2048__49__49__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4911204849112048p1396061b__PMIP__2048__49__49__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4911204849112048p1396061b__PMIP__2048__49__49__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4911204849112048p1396061b__PMIP__2048__49__49__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4911204849112048p1396061b__PMIP__2048__49__49__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4911204849112048p1396061b__PMIP__2048__49__49__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4911204849112048p1396061b__PMIP__2048__49__49__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr4911204849112048p1396061b__PMIP__2048__49__49__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_48 + (viewRef view1 + (cellRef MUX21))) + (instance mux_47 + (viewRef view1 + (cellRef MUX21))) + (instance mux_46 + (viewRef view1 + (cellRef MUX21))) + (instance mux_45 + (viewRef view1 + (cellRef MUX21))) + (instance mux_44 + (viewRef view1 + (cellRef MUX21))) + (instance mux_43 + (viewRef view1 + (cellRef MUX21))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + 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pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)) + (portRef D (instanceRef FF_1)))) + (net raddr9 + (joined + (portRef (member RdAddress 1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))) + (net raddr8 + (joined + (portRef (member RdAddress 2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))) + (net raddr7 + (joined + (portRef (member RdAddress 3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_0_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_1_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_2_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_3_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_4_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_0_5_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_0_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_1_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_2_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_3_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_4_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr4911204849112048p1396061b_1_5_0)))))))) + (design pmi_ram_dpXbnonesadr4911204849112048p1396061b + (cellRef pmi_ram_dpXbnonesadr4911204849112048p1396061b + (libraryRef ORCLIB))) +) diff --git a/CPLD3/impl1/pmi_ram_dpXbnonesadr5011204850112048p1395c280.edn b/CPLD3/impl1/pmi_ram_dpXbnonesadr5011204850112048p1395c280.edn new file mode 100644 index 0000000..39ca4ee --- /dev/null +++ b/CPLD3/impl1/pmi_ram_dpXbnonesadr5011204850112048p1395c280.edn @@ -0,0 +1,2409 @@ +(edif pmi_ram_dpXbnonesadr5011204850112048p1395c280 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 5 14 11 40 52) + (program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2")))) + (comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 50 -num_rows 2048 -rdata_width 50 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr5011204850112048p1395c280 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell MUX21 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port SD + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr5011204850112048p1395c280 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(49:0)") 50) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(49:0)") 50) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr5011204850112048p1395c280__PMIP__2048__50__50__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr5011204850112048p1395c280__PMIP__2048__50__50__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr5011204850112048p1395c280__PMIP__2048__50__50__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr5011204850112048p1395c280__PMIP__2048__50__50__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr5011204850112048p1395c280__PMIP__2048__50__50__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr5011204850112048p1395c280__PMIP__2048__50__50__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr5011204850112048p1395c280__PMIP__2048__50__50__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr5011204850112048p1395c280__PMIP__2048__50__50__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr5011204850112048p1395c280__PMIP__2048__50__50__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_3_2 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr5011204850112048p1395c280__PMIP__2048__50__50__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_4_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr5011204850112048p1395c280__PMIP__2048__50__50__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_5_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr5011204850112048p1395c280__PMIP__2048__50__50__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance FF_0 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance mux_49 + (viewRef view1 + (cellRef MUX21))) + (instance mux_48 + (viewRef view1 + (cellRef MUX21))) + (instance mux_47 + (viewRef view1 + (cellRef MUX21))) + (instance mux_46 + (viewRef view1 + (cellRef MUX21))) + (instance mux_45 + (viewRef view1 + (cellRef MUX21))) + (instance mux_44 + (viewRef view1 + (cellRef MUX21))) + (instance mux_43 + (viewRef view1 + (cellRef MUX21))) + (instance mux_42 + (viewRef view1 + (cellRef MUX21))) + (instance mux_41 + (viewRef view1 + (cellRef MUX21))) + (instance mux_40 + (viewRef view1 + (cellRef MUX21))) + (instance mux_39 + (viewRef view1 + (cellRef MUX21))) + (instance mux_38 + (viewRef view1 + (cellRef MUX21))) + (instance mux_37 + (viewRef view1 + (cellRef MUX21))) + (instance mux_36 + (viewRef view1 + (cellRef MUX21))) + (instance mux_35 + (viewRef view1 + (cellRef MUX21))) + (instance mux_34 + (viewRef view1 + (cellRef MUX21))) + (instance mux_33 + (viewRef view1 + (cellRef MUX21))) + (instance mux_32 + (viewRef view1 + (cellRef MUX21))) + (instance mux_31 + (viewRef view1 + (cellRef MUX21))) + (instance mux_30 + (viewRef view1 + (cellRef MUX21))) + (instance mux_29 + (viewRef view1 + (cellRef MUX21))) + (instance mux_28 + (viewRef view1 + (cellRef MUX21))) + (instance mux_27 + (viewRef view1 + (cellRef MUX21))) + (instance mux_26 + (viewRef view1 + (cellRef MUX21))) + (instance mux_25 + (viewRef view1 + (cellRef MUX21))) + (instance mux_24 + (viewRef view1 + (cellRef MUX21))) + (instance mux_23 + (viewRef view1 + (cellRef MUX21))) + (instance mux_22 + (viewRef view1 + (cellRef MUX21))) + (instance mux_21 + (viewRef view1 + (cellRef MUX21))) + (instance mux_20 + (viewRef view1 + (cellRef MUX21))) + (instance mux_19 + (viewRef view1 + (cellRef MUX21))) + (instance mux_18 + (viewRef view1 + (cellRef MUX21))) + (instance mux_17 + (viewRef view1 + (cellRef MUX21))) + (instance mux_16 + (viewRef view1 + (cellRef MUX21))) + (instance mux_15 + (viewRef view1 + (cellRef MUX21))) + (instance mux_14 + (viewRef view1 + (cellRef MUX21))) + (instance mux_13 + (viewRef view1 + (cellRef MUX21))) + (instance mux_12 + (viewRef view1 + (cellRef MUX21))) + (instance mux_11 + (viewRef view1 + (cellRef MUX21))) + (instance mux_10 + (viewRef view1 + (cellRef MUX21))) + (instance mux_9 + (viewRef view1 + (cellRef MUX21))) + (instance mux_8 + (viewRef view1 + (cellRef MUX21))) + (instance mux_7 + (viewRef view1 + (cellRef MUX21))) + (instance mux_6 + (viewRef view1 + (cellRef MUX21))) + (instance mux_5 + (viewRef view1 + (cellRef MUX21))) + (instance mux_4 + (viewRef view1 + (cellRef MUX21))) + (instance mux_3 + (viewRef view1 + (cellRef MUX21))) + (instance mux_2 + (viewRef view1 + (cellRef MUX21))) + (instance mux_1 + (viewRef view1 + (cellRef MUX21))) + (instance mux_0 + (viewRef view1 + (cellRef MUX21))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_3_2)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_4_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_5_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef CSB1 (instanceRef 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pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef ADB1 (instanceRef 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pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef DIB6 (instanceRef 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(portRef (member RdAddress 8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_3_2)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_4_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_5_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_3_2)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_4_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_5_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_3_2)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_4_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_5_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_3_2)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_4_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_5_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_3_2)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_4_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_5_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_3_2)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_4_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_5_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_3_2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_4_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_5_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_3_2)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_4_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_5_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_3_2)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_4_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_5_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_3_2)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_4_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_5_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_3_2)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_4_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_5_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_3_2)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_4_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_5_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_3_2)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_4_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_5_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_0_11)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_1_10)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_2_9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_3_8)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_4_7)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_0_5_6)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_0_5)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_1_4)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_2_3)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_3_2)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_4_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr5011204850112048p1395c280_1_5_0)))))))) + (design pmi_ram_dpXbnonesadr5011204850112048p1395c280 + (cellRef pmi_ram_dpXbnonesadr5011204850112048p1395c280 + (libraryRef ORCLIB))) +) diff --git a/CPLD3/impl1/pmi_ram_dpXbnonesadr81120488112048p1371f311.edn b/CPLD3/impl1/pmi_ram_dpXbnonesadr81120488112048p1371f311.edn new file mode 100644 index 0000000..efeaa01 --- /dev/null +++ b/CPLD3/impl1/pmi_ram_dpXbnonesadr81120488112048p1371f311.edn @@ -0,0 +1,553 @@ +(edif pmi_ram_dpXbnonesadr81120488112048p1371f311 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2026 1 19 16 35 48) + (program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2")))) + (comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 8 -num_rows 2048 -rdata_width 8 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr81120488112048p1371f311 -pmi ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP8KC + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell pmi_ram_dpXbnonesadr81120488112048p1371f311 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename WrAddress "WrAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename RdAddress "RdAddress(10:0)") 11) + (direction INPUT)) + (port (array (rename Data "Data(7:0)") 8) + (direction INPUT)) + (port WE + (direction INPUT)) + (port RdClock + (direction INPUT)) + (port RdClockEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port WrClock + (direction INPUT)) + (port WrClockEn + (direction INPUT)) + (port (array (rename Q "Q(7:0)") 8) + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr81120488112048p1371f311__PMIP__2048__8__8__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0 + (viewRef view1 + (cellRef DP8KC)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "ASYNC")) + (property MEM_LPC_FILE + (string "pmi_ram_dpXbnonesadr81120488112048p1371f311__PMIP__2048__8__8__-1B")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "4")) + (property DATA_WIDTH_A + (string "4"))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef DIB6 (instanceRef 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pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)) + (portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)) + (portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)) + (portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)) + (portRef WEB (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)) + (portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)) + (portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)) + (portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)) + (portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)) + (portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)) + (portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)) + (portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)) + (portRef DIA7 (instanceRef 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(net dataout6 + (joined + (portRef (member Q 1)) + (portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net dataout5 + (joined + (portRef (member Q 2)) + (portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net dataout4 + (joined + (portRef (member Q 3)) + (portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net dataout3 + (joined + (portRef (member Q 4)) + (portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)))) + (net dataout2 + (joined + (portRef (member Q 5)) + (portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)))) + (net dataout1 + (joined + (portRef (member Q 6)) + (portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)))) + (net dataout0 + (joined + (portRef (member Q 7)) + (portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)))) + (net WrClockEn + (joined + (portRef WrClockEn) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef OCEA (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)) + (portRef CEA (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net clk + (joined + (portRef WrClock) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef CLKA (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net Reset + (joined + (portRef Reset) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef RSTB (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)) + (portRef RSTA (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net RdClockEn + (joined + (portRef RdClockEn) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef OCEB (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)) + (portRef CEB (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net rdclk + (joined + (portRef RdClock) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef CLKB (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net wren + (joined + (portRef WE) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef WEA (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net datain7 + (joined + (portRef (member Data 0)) + (portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net datain6 + (joined + (portRef (member Data 1)) + (portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net datain5 + (joined + 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pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net raddr9 + (joined + (portRef (member RdAddress 1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net raddr8 + (joined + (portRef (member RdAddress 2)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net raddr7 + (joined + (portRef (member RdAddress 3)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net raddr6 + (joined + (portRef (member RdAddress 4)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net raddr5 + (joined + (portRef (member RdAddress 5)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net raddr4 + (joined + (portRef (member RdAddress 6)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net raddr3 + (joined + (portRef (member RdAddress 7)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net raddr2 + (joined + (portRef (member RdAddress 8)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net raddr1 + (joined + (portRef (member RdAddress 9)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net raddr0 + (joined + (portRef (member RdAddress 10)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net waddr10 + (joined + (portRef (member WrAddress 0)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net waddr9 + (joined + (portRef (member WrAddress 1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net waddr8 + (joined + (portRef (member WrAddress 2)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net waddr7 + (joined + (portRef (member WrAddress 3)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net waddr6 + (joined + (portRef (member WrAddress 4)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net waddr5 + (joined + (portRef (member WrAddress 5)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net waddr4 + (joined + (portRef (member WrAddress 6)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net waddr3 + (joined + (portRef (member WrAddress 7)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net waddr2 + (joined + (portRef (member WrAddress 8)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net waddr1 + (joined + (portRef (member WrAddress 9)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))) + (net waddr0 + (joined + (portRef (member WrAddress 10)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_0_1)) + (portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr81120488112048p1371f311_0_1_0)))))))) + (design pmi_ram_dpXbnonesadr81120488112048p1371f311 + (cellRef pmi_ram_dpXbnonesadr81120488112048p1371f311 + (libraryRef ORCLIB))) +)