1492 lines
85 KiB
Clojure
1492 lines
85 KiB
Clojure
(edif pmi_ram_dpXbnonesadr3811204838112048p1395f327
|
|
(edifVersion 2 0 0)
|
|
(edifLevel 0)
|
|
(keywordMap (keywordLevel 0))
|
|
(status
|
|
(written
|
|
(timestamp 2026 1 19 12 38 13)
|
|
(program "SCUBA" (version "Diamond (64-bit) 3.13.0.56.2"))))
|
|
(comment "C:/lscc/diamond/3.13/ispfpga/bin/nt64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -data_width 38 -num_rows 2048 -rdata_width 38 -read_reg1 outreg -gsr DISABLED -reset_rel async -memformat bin -cascade -1 -n pmi_ram_dpXbnonesadr3811204838112048p1395f327 -pmi ")
|
|
(library ORCLIB
|
|
(edifLevel 0)
|
|
(technology
|
|
(numberDefinition))
|
|
(cell VHI
|
|
(cellType GENERIC)
|
|
(view view1
|
|
(viewType NETLIST)
|
|
(interface
|
|
(port Z
|
|
(direction OUTPUT)))))
|
|
(cell VLO
|
|
(cellType GENERIC)
|
|
(view view1
|
|
(viewType NETLIST)
|
|
(interface
|
|
(port Z
|
|
(direction OUTPUT)))))
|
|
(cell DP8KC
|
|
(cellType GENERIC)
|
|
(view view1
|
|
(viewType NETLIST)
|
|
(interface
|
|
(port DIA8
|
|
(direction INPUT))
|
|
(port DIA7
|
|
(direction INPUT))
|
|
(port DIA6
|
|
(direction INPUT))
|
|
(port DIA5
|
|
(direction INPUT))
|
|
(port DIA4
|
|
(direction INPUT))
|
|
(port DIA3
|
|
(direction INPUT))
|
|
(port DIA2
|
|
(direction INPUT))
|
|
(port DIA1
|
|
(direction INPUT))
|
|
(port DIA0
|
|
(direction INPUT))
|
|
(port ADA12
|
|
(direction INPUT))
|
|
(port ADA11
|
|
(direction INPUT))
|
|
(port ADA10
|
|
(direction INPUT))
|
|
(port ADA9
|
|
(direction INPUT))
|
|
(port ADA8
|
|
(direction INPUT))
|
|
(port ADA7
|
|
(direction INPUT))
|
|
(port ADA6
|
|
(direction INPUT))
|
|
(port ADA5
|
|
(direction INPUT))
|
|
(port ADA4
|
|
(direction INPUT))
|
|
(port ADA3
|
|
(direction INPUT))
|
|
(port ADA2
|
|
(direction INPUT))
|
|
(port ADA1
|
|
(direction INPUT))
|
|
(port ADA0
|
|
(direction INPUT))
|
|
(port CEA
|
|
(direction INPUT))
|
|
(port OCEA
|
|
(direction INPUT))
|
|
(port CLKA
|
|
(direction INPUT))
|
|
(port WEA
|
|
(direction INPUT))
|
|
(port CSA2
|
|
(direction INPUT))
|
|
(port CSA1
|
|
(direction INPUT))
|
|
(port CSA0
|
|
(direction INPUT))
|
|
(port RSTA
|
|
(direction INPUT))
|
|
(port DIB8
|
|
(direction INPUT))
|
|
(port DIB7
|
|
(direction INPUT))
|
|
(port DIB6
|
|
(direction INPUT))
|
|
(port DIB5
|
|
(direction INPUT))
|
|
(port DIB4
|
|
(direction INPUT))
|
|
(port DIB3
|
|
(direction INPUT))
|
|
(port DIB2
|
|
(direction INPUT))
|
|
(port DIB1
|
|
(direction INPUT))
|
|
(port DIB0
|
|
(direction INPUT))
|
|
(port ADB12
|
|
(direction INPUT))
|
|
(port ADB11
|
|
(direction INPUT))
|
|
(port ADB10
|
|
(direction INPUT))
|
|
(port ADB9
|
|
(direction INPUT))
|
|
(port ADB8
|
|
(direction INPUT))
|
|
(port ADB7
|
|
(direction INPUT))
|
|
(port ADB6
|
|
(direction INPUT))
|
|
(port ADB5
|
|
(direction INPUT))
|
|
(port ADB4
|
|
(direction INPUT))
|
|
(port ADB3
|
|
(direction INPUT))
|
|
(port ADB2
|
|
(direction INPUT))
|
|
(port ADB1
|
|
(direction INPUT))
|
|
(port ADB0
|
|
(direction INPUT))
|
|
(port CEB
|
|
(direction INPUT))
|
|
(port OCEB
|
|
(direction INPUT))
|
|
(port CLKB
|
|
(direction INPUT))
|
|
(port WEB
|
|
(direction INPUT))
|
|
(port CSB2
|
|
(direction INPUT))
|
|
(port CSB1
|
|
(direction INPUT))
|
|
(port CSB0
|
|
(direction INPUT))
|
|
(port RSTB
|
|
(direction INPUT))
|
|
(port DOA8
|
|
(direction OUTPUT))
|
|
(port DOA7
|
|
(direction OUTPUT))
|
|
(port DOA6
|
|
(direction OUTPUT))
|
|
(port DOA5
|
|
(direction OUTPUT))
|
|
(port DOA4
|
|
(direction OUTPUT))
|
|
(port DOA3
|
|
(direction OUTPUT))
|
|
(port DOA2
|
|
(direction OUTPUT))
|
|
(port DOA1
|
|
(direction OUTPUT))
|
|
(port DOA0
|
|
(direction OUTPUT))
|
|
(port DOB8
|
|
(direction OUTPUT))
|
|
(port DOB7
|
|
(direction OUTPUT))
|
|
(port DOB6
|
|
(direction OUTPUT))
|
|
(port DOB5
|
|
(direction OUTPUT))
|
|
(port DOB4
|
|
(direction OUTPUT))
|
|
(port DOB3
|
|
(direction OUTPUT))
|
|
(port DOB2
|
|
(direction OUTPUT))
|
|
(port DOB1
|
|
(direction OUTPUT))
|
|
(port DOB0
|
|
(direction OUTPUT)))))
|
|
(cell pmi_ram_dpXbnonesadr3811204838112048p1395f327
|
|
(cellType GENERIC)
|
|
(view view1
|
|
(viewType NETLIST)
|
|
(interface
|
|
(port (array (rename WrAddress "WrAddress(10:0)") 11)
|
|
(direction INPUT))
|
|
(port (array (rename RdAddress "RdAddress(10:0)") 11)
|
|
(direction INPUT))
|
|
(port (array (rename Data "Data(37:0)") 38)
|
|
(direction INPUT))
|
|
(port WE
|
|
(direction INPUT))
|
|
(port RdClock
|
|
(direction INPUT))
|
|
(port RdClockEn
|
|
(direction INPUT))
|
|
(port Reset
|
|
(direction INPUT))
|
|
(port WrClock
|
|
(direction INPUT))
|
|
(port WrClockEn
|
|
(direction INPUT))
|
|
(port (array (rename Q "Q(37:0)") 38)
|
|
(direction OUTPUT)))
|
|
(property NGD_DRC_MASK (integer 1))
|
|
(contents
|
|
(instance scuba_vhi_inst
|
|
(viewRef view1
|
|
(cellRef VHI)))
|
|
(instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9
|
|
(viewRef view1
|
|
(cellRef DP8KC))
|
|
(property INIT_DATA
|
|
(string "STATIC"))
|
|
(property ASYNC_RESET_RELEASE
|
|
(string "ASYNC"))
|
|
(property MEM_LPC_FILE
|
|
(string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B"))
|
|
(property MEM_INIT_FILE
|
|
(string ""))
|
|
(property CSDECODE_B
|
|
(string "0b000"))
|
|
(property CSDECODE_A
|
|
(string "0b000"))
|
|
(property WRITEMODE_B
|
|
(string "NORMAL"))
|
|
(property WRITEMODE_A
|
|
(string "NORMAL"))
|
|
(property GSR
|
|
(string "ENABLED"))
|
|
(property RESETMODE
|
|
(string "ASYNC"))
|
|
(property REGMODE_B
|
|
(string "OUTREG"))
|
|
(property REGMODE_A
|
|
(string "OUTREG"))
|
|
(property DATA_WIDTH_B
|
|
(string "4"))
|
|
(property DATA_WIDTH_A
|
|
(string "4")))
|
|
(instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8
|
|
(viewRef view1
|
|
(cellRef DP8KC))
|
|
(property INIT_DATA
|
|
(string "STATIC"))
|
|
(property ASYNC_RESET_RELEASE
|
|
(string "ASYNC"))
|
|
(property MEM_LPC_FILE
|
|
(string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B"))
|
|
(property MEM_INIT_FILE
|
|
(string ""))
|
|
(property CSDECODE_B
|
|
(string "0b000"))
|
|
(property CSDECODE_A
|
|
(string "0b000"))
|
|
(property WRITEMODE_B
|
|
(string "NORMAL"))
|
|
(property WRITEMODE_A
|
|
(string "NORMAL"))
|
|
(property GSR
|
|
(string "ENABLED"))
|
|
(property RESETMODE
|
|
(string "ASYNC"))
|
|
(property REGMODE_B
|
|
(string "OUTREG"))
|
|
(property REGMODE_A
|
|
(string "OUTREG"))
|
|
(property DATA_WIDTH_B
|
|
(string "4"))
|
|
(property DATA_WIDTH_A
|
|
(string "4")))
|
|
(instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7
|
|
(viewRef view1
|
|
(cellRef DP8KC))
|
|
(property INIT_DATA
|
|
(string "STATIC"))
|
|
(property ASYNC_RESET_RELEASE
|
|
(string "ASYNC"))
|
|
(property MEM_LPC_FILE
|
|
(string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B"))
|
|
(property MEM_INIT_FILE
|
|
(string ""))
|
|
(property CSDECODE_B
|
|
(string "0b000"))
|
|
(property CSDECODE_A
|
|
(string "0b000"))
|
|
(property WRITEMODE_B
|
|
(string "NORMAL"))
|
|
(property WRITEMODE_A
|
|
(string "NORMAL"))
|
|
(property GSR
|
|
(string "ENABLED"))
|
|
(property RESETMODE
|
|
(string "ASYNC"))
|
|
(property REGMODE_B
|
|
(string "OUTREG"))
|
|
(property REGMODE_A
|
|
(string "OUTREG"))
|
|
(property DATA_WIDTH_B
|
|
(string "4"))
|
|
(property DATA_WIDTH_A
|
|
(string "4")))
|
|
(instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6
|
|
(viewRef view1
|
|
(cellRef DP8KC))
|
|
(property INIT_DATA
|
|
(string "STATIC"))
|
|
(property ASYNC_RESET_RELEASE
|
|
(string "ASYNC"))
|
|
(property MEM_LPC_FILE
|
|
(string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B"))
|
|
(property MEM_INIT_FILE
|
|
(string ""))
|
|
(property CSDECODE_B
|
|
(string "0b000"))
|
|
(property CSDECODE_A
|
|
(string "0b000"))
|
|
(property WRITEMODE_B
|
|
(string "NORMAL"))
|
|
(property WRITEMODE_A
|
|
(string "NORMAL"))
|
|
(property GSR
|
|
(string "ENABLED"))
|
|
(property RESETMODE
|
|
(string "ASYNC"))
|
|
(property REGMODE_B
|
|
(string "OUTREG"))
|
|
(property REGMODE_A
|
|
(string "OUTREG"))
|
|
(property DATA_WIDTH_B
|
|
(string "4"))
|
|
(property DATA_WIDTH_A
|
|
(string "4")))
|
|
(instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5
|
|
(viewRef view1
|
|
(cellRef DP8KC))
|
|
(property INIT_DATA
|
|
(string "STATIC"))
|
|
(property ASYNC_RESET_RELEASE
|
|
(string "ASYNC"))
|
|
(property MEM_LPC_FILE
|
|
(string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B"))
|
|
(property MEM_INIT_FILE
|
|
(string ""))
|
|
(property CSDECODE_B
|
|
(string "0b000"))
|
|
(property CSDECODE_A
|
|
(string "0b000"))
|
|
(property WRITEMODE_B
|
|
(string "NORMAL"))
|
|
(property WRITEMODE_A
|
|
(string "NORMAL"))
|
|
(property GSR
|
|
(string "ENABLED"))
|
|
(property RESETMODE
|
|
(string "ASYNC"))
|
|
(property REGMODE_B
|
|
(string "OUTREG"))
|
|
(property REGMODE_A
|
|
(string "OUTREG"))
|
|
(property DATA_WIDTH_B
|
|
(string "4"))
|
|
(property DATA_WIDTH_A
|
|
(string "4")))
|
|
(instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4
|
|
(viewRef view1
|
|
(cellRef DP8KC))
|
|
(property INIT_DATA
|
|
(string "STATIC"))
|
|
(property ASYNC_RESET_RELEASE
|
|
(string "ASYNC"))
|
|
(property MEM_LPC_FILE
|
|
(string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B"))
|
|
(property MEM_INIT_FILE
|
|
(string ""))
|
|
(property CSDECODE_B
|
|
(string "0b000"))
|
|
(property CSDECODE_A
|
|
(string "0b000"))
|
|
(property WRITEMODE_B
|
|
(string "NORMAL"))
|
|
(property WRITEMODE_A
|
|
(string "NORMAL"))
|
|
(property GSR
|
|
(string "ENABLED"))
|
|
(property RESETMODE
|
|
(string "ASYNC"))
|
|
(property REGMODE_B
|
|
(string "OUTREG"))
|
|
(property REGMODE_A
|
|
(string "OUTREG"))
|
|
(property DATA_WIDTH_B
|
|
(string "4"))
|
|
(property DATA_WIDTH_A
|
|
(string "4")))
|
|
(instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3
|
|
(viewRef view1
|
|
(cellRef DP8KC))
|
|
(property INIT_DATA
|
|
(string "STATIC"))
|
|
(property ASYNC_RESET_RELEASE
|
|
(string "ASYNC"))
|
|
(property MEM_LPC_FILE
|
|
(string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B"))
|
|
(property MEM_INIT_FILE
|
|
(string ""))
|
|
(property CSDECODE_B
|
|
(string "0b000"))
|
|
(property CSDECODE_A
|
|
(string "0b000"))
|
|
(property WRITEMODE_B
|
|
(string "NORMAL"))
|
|
(property WRITEMODE_A
|
|
(string "NORMAL"))
|
|
(property GSR
|
|
(string "ENABLED"))
|
|
(property RESETMODE
|
|
(string "ASYNC"))
|
|
(property REGMODE_B
|
|
(string "OUTREG"))
|
|
(property REGMODE_A
|
|
(string "OUTREG"))
|
|
(property DATA_WIDTH_B
|
|
(string "4"))
|
|
(property DATA_WIDTH_A
|
|
(string "4")))
|
|
(instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2
|
|
(viewRef view1
|
|
(cellRef DP8KC))
|
|
(property INIT_DATA
|
|
(string "STATIC"))
|
|
(property ASYNC_RESET_RELEASE
|
|
(string "ASYNC"))
|
|
(property MEM_LPC_FILE
|
|
(string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B"))
|
|
(property MEM_INIT_FILE
|
|
(string ""))
|
|
(property CSDECODE_B
|
|
(string "0b000"))
|
|
(property CSDECODE_A
|
|
(string "0b000"))
|
|
(property WRITEMODE_B
|
|
(string "NORMAL"))
|
|
(property WRITEMODE_A
|
|
(string "NORMAL"))
|
|
(property GSR
|
|
(string "ENABLED"))
|
|
(property RESETMODE
|
|
(string "ASYNC"))
|
|
(property REGMODE_B
|
|
(string "OUTREG"))
|
|
(property REGMODE_A
|
|
(string "OUTREG"))
|
|
(property DATA_WIDTH_B
|
|
(string "4"))
|
|
(property DATA_WIDTH_A
|
|
(string "4")))
|
|
(instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1
|
|
(viewRef view1
|
|
(cellRef DP8KC))
|
|
(property INIT_DATA
|
|
(string "STATIC"))
|
|
(property ASYNC_RESET_RELEASE
|
|
(string "ASYNC"))
|
|
(property MEM_LPC_FILE
|
|
(string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B"))
|
|
(property MEM_INIT_FILE
|
|
(string ""))
|
|
(property CSDECODE_B
|
|
(string "0b000"))
|
|
(property CSDECODE_A
|
|
(string "0b000"))
|
|
(property WRITEMODE_B
|
|
(string "NORMAL"))
|
|
(property WRITEMODE_A
|
|
(string "NORMAL"))
|
|
(property GSR
|
|
(string "ENABLED"))
|
|
(property RESETMODE
|
|
(string "ASYNC"))
|
|
(property REGMODE_B
|
|
(string "OUTREG"))
|
|
(property REGMODE_A
|
|
(string "OUTREG"))
|
|
(property DATA_WIDTH_B
|
|
(string "4"))
|
|
(property DATA_WIDTH_A
|
|
(string "4")))
|
|
(instance scuba_vlo_inst
|
|
(viewRef view1
|
|
(cellRef VLO)))
|
|
(instance pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0
|
|
(viewRef view1
|
|
(cellRef DP8KC))
|
|
(property INIT_DATA
|
|
(string "STATIC"))
|
|
(property ASYNC_RESET_RELEASE
|
|
(string "ASYNC"))
|
|
(property MEM_LPC_FILE
|
|
(string "pmi_ram_dpXbnonesadr3811204838112048p1395f327__PMIP__2048__38__38__-1B"))
|
|
(property MEM_INIT_FILE
|
|
(string ""))
|
|
(property CSDECODE_B
|
|
(string "0b000"))
|
|
(property CSDECODE_A
|
|
(string "0b000"))
|
|
(property WRITEMODE_B
|
|
(string "NORMAL"))
|
|
(property WRITEMODE_A
|
|
(string "NORMAL"))
|
|
(property GSR
|
|
(string "ENABLED"))
|
|
(property RESETMODE
|
|
(string "ASYNC"))
|
|
(property REGMODE_B
|
|
(string "OUTREG"))
|
|
(property REGMODE_A
|
|
(string "OUTREG"))
|
|
(property DATA_WIDTH_B
|
|
(string "4"))
|
|
(property DATA_WIDTH_A
|
|
(string "4")))
|
|
(net scuba_vhi
|
|
(joined
|
|
(portRef Z (instanceRef scuba_vhi_inst))))
|
|
(net scuba_vlo
|
|
(joined
|
|
(portRef Z (instanceRef scuba_vlo_inst))
|
|
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef CSB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef CSA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef CSB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef CSA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef CSB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef CSA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef WEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef ADB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef ADA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef ADB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef ADA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef DIB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef DIA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef DIB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef DIA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef DIB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef DIA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef DIB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef DIA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef DIB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef DIA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef DIB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef DIB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef DIB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef DIB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net dataout37
|
|
(joined
|
|
(portRef (member Q 0))
|
|
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net dataout36
|
|
(joined
|
|
(portRef (member Q 1))
|
|
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net dataout35
|
|
(joined
|
|
(portRef (member Q 2))
|
|
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))))
|
|
(net dataout34
|
|
(joined
|
|
(portRef (member Q 3))
|
|
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))))
|
|
(net dataout33
|
|
(joined
|
|
(portRef (member Q 4))
|
|
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))))
|
|
(net dataout32
|
|
(joined
|
|
(portRef (member Q 5))
|
|
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))))
|
|
(net dataout31
|
|
(joined
|
|
(portRef (member Q 6))
|
|
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))))
|
|
(net dataout30
|
|
(joined
|
|
(portRef (member Q 7))
|
|
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))))
|
|
(net dataout29
|
|
(joined
|
|
(portRef (member Q 8))
|
|
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))))
|
|
(net dataout28
|
|
(joined
|
|
(portRef (member Q 9))
|
|
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))))
|
|
(net dataout27
|
|
(joined
|
|
(portRef (member Q 10))
|
|
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))))
|
|
(net dataout26
|
|
(joined
|
|
(portRef (member Q 11))
|
|
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))))
|
|
(net dataout25
|
|
(joined
|
|
(portRef (member Q 12))
|
|
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))))
|
|
(net dataout24
|
|
(joined
|
|
(portRef (member Q 13))
|
|
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))))
|
|
(net dataout23
|
|
(joined
|
|
(portRef (member Q 14))
|
|
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))))
|
|
(net dataout22
|
|
(joined
|
|
(portRef (member Q 15))
|
|
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))))
|
|
(net dataout21
|
|
(joined
|
|
(portRef (member Q 16))
|
|
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))))
|
|
(net dataout20
|
|
(joined
|
|
(portRef (member Q 17))
|
|
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))))
|
|
(net dataout19
|
|
(joined
|
|
(portRef (member Q 18))
|
|
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))))
|
|
(net dataout18
|
|
(joined
|
|
(portRef (member Q 19))
|
|
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))))
|
|
(net dataout17
|
|
(joined
|
|
(portRef (member Q 20))
|
|
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))))
|
|
(net dataout16
|
|
(joined
|
|
(portRef (member Q 21))
|
|
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))))
|
|
(net dataout15
|
|
(joined
|
|
(portRef (member Q 22))
|
|
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))))
|
|
(net dataout14
|
|
(joined
|
|
(portRef (member Q 23))
|
|
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))))
|
|
(net dataout13
|
|
(joined
|
|
(portRef (member Q 24))
|
|
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))))
|
|
(net dataout12
|
|
(joined
|
|
(portRef (member Q 25))
|
|
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))))
|
|
(net dataout11
|
|
(joined
|
|
(portRef (member Q 26))
|
|
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))))
|
|
(net dataout10
|
|
(joined
|
|
(portRef (member Q 27))
|
|
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))))
|
|
(net dataout9
|
|
(joined
|
|
(portRef (member Q 28))
|
|
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))))
|
|
(net dataout8
|
|
(joined
|
|
(portRef (member Q 29))
|
|
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))))
|
|
(net dataout7
|
|
(joined
|
|
(portRef (member Q 30))
|
|
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))))
|
|
(net dataout6
|
|
(joined
|
|
(portRef (member Q 31))
|
|
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))))
|
|
(net dataout5
|
|
(joined
|
|
(portRef (member Q 32))
|
|
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))))
|
|
(net dataout4
|
|
(joined
|
|
(portRef (member Q 33))
|
|
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))))
|
|
(net dataout3
|
|
(joined
|
|
(portRef (member Q 34))
|
|
(portRef DOB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))))
|
|
(net dataout2
|
|
(joined
|
|
(portRef (member Q 35))
|
|
(portRef DOB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))))
|
|
(net dataout1
|
|
(joined
|
|
(portRef (member Q 36))
|
|
(portRef DOB1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))))
|
|
(net dataout0
|
|
(joined
|
|
(portRef (member Q 37))
|
|
(portRef DOB0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))))
|
|
(net WrClockEn
|
|
(joined
|
|
(portRef WrClockEn)
|
|
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef OCEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef CEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net clk
|
|
(joined
|
|
(portRef WrClock)
|
|
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef CLKA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net Reset
|
|
(joined
|
|
(portRef Reset)
|
|
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef RSTB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef RSTA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net RdClockEn
|
|
(joined
|
|
(portRef RdClockEn)
|
|
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef OCEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))
|
|
(portRef CEB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net rdclk
|
|
(joined
|
|
(portRef RdClock)
|
|
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef CLKB (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net wren
|
|
(joined
|
|
(portRef WE)
|
|
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef WEA (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net datain37
|
|
(joined
|
|
(portRef (member Data 0))
|
|
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net datain36
|
|
(joined
|
|
(portRef (member Data 1))
|
|
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net datain35
|
|
(joined
|
|
(portRef (member Data 2))
|
|
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))))
|
|
(net datain34
|
|
(joined
|
|
(portRef (member Data 3))
|
|
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))))
|
|
(net datain33
|
|
(joined
|
|
(portRef (member Data 4))
|
|
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))))
|
|
(net datain32
|
|
(joined
|
|
(portRef (member Data 5))
|
|
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))))
|
|
(net datain31
|
|
(joined
|
|
(portRef (member Data 6))
|
|
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))))
|
|
(net datain30
|
|
(joined
|
|
(portRef (member Data 7))
|
|
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))))
|
|
(net datain29
|
|
(joined
|
|
(portRef (member Data 8))
|
|
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))))
|
|
(net datain28
|
|
(joined
|
|
(portRef (member Data 9))
|
|
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))))
|
|
(net datain27
|
|
(joined
|
|
(portRef (member Data 10))
|
|
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))))
|
|
(net datain26
|
|
(joined
|
|
(portRef (member Data 11))
|
|
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))))
|
|
(net datain25
|
|
(joined
|
|
(portRef (member Data 12))
|
|
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))))
|
|
(net datain24
|
|
(joined
|
|
(portRef (member Data 13))
|
|
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))))
|
|
(net datain23
|
|
(joined
|
|
(portRef (member Data 14))
|
|
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))))
|
|
(net datain22
|
|
(joined
|
|
(portRef (member Data 15))
|
|
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))))
|
|
(net datain21
|
|
(joined
|
|
(portRef (member Data 16))
|
|
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))))
|
|
(net datain20
|
|
(joined
|
|
(portRef (member Data 17))
|
|
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))))
|
|
(net datain19
|
|
(joined
|
|
(portRef (member Data 18))
|
|
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))))
|
|
(net datain18
|
|
(joined
|
|
(portRef (member Data 19))
|
|
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))))
|
|
(net datain17
|
|
(joined
|
|
(portRef (member Data 20))
|
|
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))))
|
|
(net datain16
|
|
(joined
|
|
(portRef (member Data 21))
|
|
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))))
|
|
(net datain15
|
|
(joined
|
|
(portRef (member Data 22))
|
|
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))))
|
|
(net datain14
|
|
(joined
|
|
(portRef (member Data 23))
|
|
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))))
|
|
(net datain13
|
|
(joined
|
|
(portRef (member Data 24))
|
|
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))))
|
|
(net datain12
|
|
(joined
|
|
(portRef (member Data 25))
|
|
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))))
|
|
(net datain11
|
|
(joined
|
|
(portRef (member Data 26))
|
|
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))))
|
|
(net datain10
|
|
(joined
|
|
(portRef (member Data 27))
|
|
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))))
|
|
(net datain9
|
|
(joined
|
|
(portRef (member Data 28))
|
|
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))))
|
|
(net datain8
|
|
(joined
|
|
(portRef (member Data 29))
|
|
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))))
|
|
(net datain7
|
|
(joined
|
|
(portRef (member Data 30))
|
|
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))))
|
|
(net datain6
|
|
(joined
|
|
(portRef (member Data 31))
|
|
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))))
|
|
(net datain5
|
|
(joined
|
|
(portRef (member Data 32))
|
|
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))))
|
|
(net datain4
|
|
(joined
|
|
(portRef (member Data 33))
|
|
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))))
|
|
(net datain3
|
|
(joined
|
|
(portRef (member Data 34))
|
|
(portRef DIA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))))
|
|
(net datain2
|
|
(joined
|
|
(portRef (member Data 35))
|
|
(portRef DIA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))))
|
|
(net datain1
|
|
(joined
|
|
(portRef (member Data 36))
|
|
(portRef DIA1 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))))
|
|
(net datain0
|
|
(joined
|
|
(portRef (member Data 37))
|
|
(portRef DIA0 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))))
|
|
(net raddr10
|
|
(joined
|
|
(portRef (member RdAddress 0))
|
|
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADB12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net raddr9
|
|
(joined
|
|
(portRef (member RdAddress 1))
|
|
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADB11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net raddr8
|
|
(joined
|
|
(portRef (member RdAddress 2))
|
|
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADB10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net raddr7
|
|
(joined
|
|
(portRef (member RdAddress 3))
|
|
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADB9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net raddr6
|
|
(joined
|
|
(portRef (member RdAddress 4))
|
|
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADB8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net raddr5
|
|
(joined
|
|
(portRef (member RdAddress 5))
|
|
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADB7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net raddr4
|
|
(joined
|
|
(portRef (member RdAddress 6))
|
|
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADB6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net raddr3
|
|
(joined
|
|
(portRef (member RdAddress 7))
|
|
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADB5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net raddr2
|
|
(joined
|
|
(portRef (member RdAddress 8))
|
|
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADB4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net raddr1
|
|
(joined
|
|
(portRef (member RdAddress 9))
|
|
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADB3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net raddr0
|
|
(joined
|
|
(portRef (member RdAddress 10))
|
|
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADB2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net waddr10
|
|
(joined
|
|
(portRef (member WrAddress 0))
|
|
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADA12 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net waddr9
|
|
(joined
|
|
(portRef (member WrAddress 1))
|
|
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADA11 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net waddr8
|
|
(joined
|
|
(portRef (member WrAddress 2))
|
|
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADA10 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net waddr7
|
|
(joined
|
|
(portRef (member WrAddress 3))
|
|
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADA9 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net waddr6
|
|
(joined
|
|
(portRef (member WrAddress 4))
|
|
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADA8 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net waddr5
|
|
(joined
|
|
(portRef (member WrAddress 5))
|
|
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADA7 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net waddr4
|
|
(joined
|
|
(portRef (member WrAddress 6))
|
|
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADA6 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net waddr3
|
|
(joined
|
|
(portRef (member WrAddress 7))
|
|
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADA5 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net waddr2
|
|
(joined
|
|
(portRef (member WrAddress 8))
|
|
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADA4 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net waddr1
|
|
(joined
|
|
(portRef (member WrAddress 9))
|
|
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADA3 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))
|
|
(net waddr0
|
|
(joined
|
|
(portRef (member WrAddress 10))
|
|
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_0_9))
|
|
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_1_8))
|
|
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_2_7))
|
|
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_3_6))
|
|
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_4_5))
|
|
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_5_4))
|
|
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_6_3))
|
|
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_7_2))
|
|
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_8_1))
|
|
(portRef ADA2 (instanceRef pmi_ram_dpXbnonesadr3811204838112048p1395f327_0_9_0))))))))
|
|
(design pmi_ram_dpXbnonesadr3811204838112048p1395f327
|
|
(cellRef pmi_ram_dpXbnonesadr3811204838112048p1395f327
|
|
(libraryRef ORCLIB)))
|
|
)
|