yuysh/NewInstrCalBoard_CPLD
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CPLD1 debug logic too large, delete some signals

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yuysh
2026-05-28 10:29:27 +08:00
parent bf6769d814
commit 8de946787c
3 changed files with 4 additions and 41 deletions
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CPLD1/debug.rvl
+2 -21
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@@ -1,7 +1,7 @@
<Project ModBy="Inserter" SigType="0" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/debug.rvl" Date="2026-05-26">
<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/debug.rvl" Date="2026-05-28">
<IP Version="1_6_042617"/>
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD1"/>
<Core InsertDataset="0" Insert="1" Reveal_sig="695532518" Name="RelayConTop_LA0" ID="0">
<Core InsertDataset="0" Insert="1" Reveal_sig="695772961" Name="RelayConTop_LA0" ID="0">
<Setting>
<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
@@ -15,25 +15,6 @@
<Sig Type="SIG" Name="BUS_Con_1/i_cs"/>
<Sig Type="SIG" Name="BUS_Con_1/i_mosi"/>
<Sig Type="SIG" Name="BUS_Con_1/i_sclk"/>
<Bus Name="o_DMM_EN">
<Sig Type="SIG" Name="o_DMM_EN:0"/>
<Sig Type="SIG" Name="o_DMM_EN:1"/>
<Sig Type="SIG" Name="o_DMM_EN:2"/>
<Sig Type="SIG" Name="o_DMM_EN:3"/>
<Sig Type="SIG" Name="o_DMM_EN:4"/>
<Sig Type="SIG" Name="o_DMM_EN:5"/>
<Sig Type="SIG" Name="o_DMM_EN:6"/>
<Sig Type="SIG" Name="o_DMM_EN:7"/>
<Sig Type="SIG" Name="o_DMM_EN:8"/>
<Sig Type="SIG" Name="o_DMM_EN:9"/>
<Sig Type="SIG" Name="o_DMM_EN:10"/>
<Sig Type="SIG" Name="o_DMM_EN:11"/>
<Sig Type="SIG" Name="o_DMM_EN:12"/>
<Sig Type="SIG" Name="o_DMM_EN:13"/>
<Sig Type="SIG" Name="o_DMM_EN:14"/>
<Sig Type="SIG" Name="o_DMM_EN:15"/>
</Bus>
<Sig Type="SIG" Name="o_IO_RC1"/>
<Sig Type="SIG" Name="BUS_Con_1/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_1/err_flag"/>
<Sig Type="SIG" Name="CPLD_Reg_1/err_flag"/>