yuysh/NewInstrCalBoard_CPLD
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NewInstrCalBoard_CPLD/CPLD1/debug.rvl
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<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/debug.rvl" Date="2026-05-28">
<IP Version="1_6_042617"/>
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD1"/>
<Core InsertDataset="0" Insert="1" Reveal_sig="695772961" Name="RelayConTop_LA0" ID="0">
<Setting>
<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
<Capture Mode="0" MinSamplesPerTrig="8"/>
<Event CntEnable="0" MaxEventCnt="8"/>
<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_RelayConTop_LA0_net"/>
<DistRAM Disable="0"/>
</Setting>
<Dataset Name="Base">
<Trace>
<Sig Type="SIG" Name="BUS_Con_1/i_cs"/>
<Sig Type="SIG" Name="BUS_Con_1/i_mosi"/>
<Sig Type="SIG" Name="BUS_Con_1/i_sclk"/>
<Sig Type="SIG" Name="BUS_Con_1/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_1/err_flag"/>
<Sig Type="SIG" Name="CPLD_Reg_1/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_con_exec"/>
<Bus Name="CPLD_Con_1/i_DC_Con1">
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:0"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:1"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:2"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:3"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:4"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:5"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:6"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:7"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:8"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:9"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:10"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:11"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:12"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:13"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:14"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:15"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:16"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:17"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:18"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:19"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:20"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:21"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:22"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:23"/>
</Bus>
<Bus Name="CPLD_Con_1/i_DC_Con2">
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:0"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:1"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:2"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:3"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:4"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:5"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:6"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:7"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:8"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:9"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:10"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:11"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:12"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:13"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:14"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:15"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:16"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:17"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:18"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:19"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:20"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:21"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:22"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:23"/>
</Bus>
<Bus Name="CPLD_Con_1/i_DC_Con3">
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:0"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:1"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:2"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:3"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:4"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:5"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:6"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:7"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:8"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:9"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:10"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:11"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:12"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:13"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:14"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:15"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:16"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:17"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:18"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:19"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:20"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:21"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:22"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:23"/>
</Bus>
<Bus Name="CPLD_Con_1/i_DC_Con4">
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:0"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:1"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:2"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:3"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:4"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:5"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:6"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:7"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:8"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:9"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:10"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:11"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:12"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:13"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:14"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:15"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:16"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:17"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:18"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:19"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:20"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:21"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:22"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:23"/>
</Bus>
</Trace>
<Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="i_cs,"/>
<TU Serialbits="0" Type="0" ID="2" Sig="i_sclk,"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
</Trigger>
</Dataset>
</Core>
</Project>
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