From 8de946787c9803ae39148cb0028b3b3b476461fa Mon Sep 17 00:00:00 2001
From: yuysh <yuyang.shen@manlink.cn>
Date: Thu, 28 May 2026 10:29:27 +0800
Subject: [PATCH] CPLD1 debug logic too large, delete some signals

---
 CPLD1/NewExtIns_CPLD1.lpf |  1 +
 CPLD1/debug.rvl           | 23 ++---------------------
 CPLD1/debug.rvs           | 21 +--------------------
 3 files changed, 4 insertions(+), 41 deletions(-)

diff --git a/CPLD1/NewExtIns_CPLD1.lpf b/CPLD1/NewExtIns_CPLD1.lpf
index 4b8a16c..2f8649d 100644
--- a/CPLD1/NewExtIns_CPLD1.lpf
+++ b/CPLD1/NewExtIns_CPLD1.lpf
@@ -1,3 +1,4 @@
+rvl_alias "i_sys_clk" "i_sys_clk";
 RVL_ALIAS "i_sys_clk" "i_sys_clk"; 
 RVL_ALIAS "i_sys_clk" "i_sys_clk"; 
 RVL_ALIAS "i_sys_clk" "i_sys_clk"; 
diff --git a/CPLD1/debug.rvl b/CPLD1/debug.rvl
index 28c5395..b2fd312 100644
--- a/CPLD1/debug.rvl
+++ b/CPLD1/debug.rvl
@@ -1,7 +1,7 @@
-<Project ModBy="Inserter" SigType="0" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/debug.rvl" Date="2026-05-26">
+<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/debug.rvl" Date="2026-05-28">
     <IP Version="1_6_042617"/>
     <Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD1"/>
-    <Core InsertDataset="0" Insert="1" Reveal_sig="695532518" Name="RelayConTop_LA0" ID="0">
+    <Core InsertDataset="0" Insert="1" Reveal_sig="695772961" Name="RelayConTop_LA0" ID="0">
         <Setting>
             <Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
             <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
@@ -15,25 +15,6 @@
                 <Sig Type="SIG" Name="BUS_Con_1/i_cs"/>
                 <Sig Type="SIG" Name="BUS_Con_1/i_mosi"/>
                 <Sig Type="SIG" Name="BUS_Con_1/i_sclk"/>
-                <Bus Name="o_DMM_EN">
-                    <Sig Type="SIG" Name="o_DMM_EN:0"/>
-                    <Sig Type="SIG" Name="o_DMM_EN:1"/>
-                    <Sig Type="SIG" Name="o_DMM_EN:2"/>
-                    <Sig Type="SIG" Name="o_DMM_EN:3"/>
-                    <Sig Type="SIG" Name="o_DMM_EN:4"/>
-                    <Sig Type="SIG" Name="o_DMM_EN:5"/>
-                    <Sig Type="SIG" Name="o_DMM_EN:6"/>
-                    <Sig Type="SIG" Name="o_DMM_EN:7"/>
-                    <Sig Type="SIG" Name="o_DMM_EN:8"/>
-                    <Sig Type="SIG" Name="o_DMM_EN:9"/>
-                    <Sig Type="SIG" Name="o_DMM_EN:10"/>
-                    <Sig Type="SIG" Name="o_DMM_EN:11"/>
-                    <Sig Type="SIG" Name="o_DMM_EN:12"/>
-                    <Sig Type="SIG" Name="o_DMM_EN:13"/>
-                    <Sig Type="SIG" Name="o_DMM_EN:14"/>
-                    <Sig Type="SIG" Name="o_DMM_EN:15"/>
-                </Bus>
-                <Sig Type="SIG" Name="o_IO_RC1"/>
                 <Sig Type="SIG" Name="BUS_Con_1/err_flag"/>
                 <Sig Type="SIG" Name="CPLD_Con_1/err_flag"/>
                 <Sig Type="SIG" Name="CPLD_Reg_1/err_flag"/>
diff --git a/CPLD1/debug.rvs b/CPLD1/debug.rvs
index 865652e..fe0163f 100644
--- a/CPLD1/debug.rvs
+++ b/CPLD1/debug.rvs
@@ -1,4 +1,4 @@
-<Project ModBy="Inserter" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/debug.rvl" Date="2026-05-26">
+<Project ModBy="Inserter" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/debug.rvl" Date="2026-05-28">
     <Core Name="RelayConTop_LA0">
         <Setting>
             <Capture SamplesPerTrig="2048" NumTrigsCap="1"/>
@@ -10,25 +10,6 @@
                 <Sig Name="BUS_Con_1/i_cs"/>
                 <Sig Name="BUS_Con_1/i_mosi"/>
                 <Sig Name="BUS_Con_1/i_sclk"/>
-                <Bus Name="o_DMM_EN" Radix="0">
-                    <Sig Name="o_DMM_EN:0"/>
-                    <Sig Name="o_DMM_EN:1"/>
-                    <Sig Name="o_DMM_EN:2"/>
-                    <Sig Name="o_DMM_EN:3"/>
-                    <Sig Name="o_DMM_EN:4"/>
-                    <Sig Name="o_DMM_EN:5"/>
-                    <Sig Name="o_DMM_EN:6"/>
-                    <Sig Name="o_DMM_EN:7"/>
-                    <Sig Name="o_DMM_EN:8"/>
-                    <Sig Name="o_DMM_EN:9"/>
-                    <Sig Name="o_DMM_EN:10"/>
-                    <Sig Name="o_DMM_EN:11"/>
-                    <Sig Name="o_DMM_EN:12"/>
-                    <Sig Name="o_DMM_EN:13"/>
-                    <Sig Name="o_DMM_EN:14"/>
-                    <Sig Name="o_DMM_EN:15"/>
-                </Bus>
-                <Sig Name="o_IO_RC1"/>
                 <Sig Name="BUS_Con_1/err_flag"/>
                 <Sig Name="CPLD_Con_1/err_flag"/>
                 <Sig Name="CPLD_Reg_1/err_flag"/>