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yuysh
2026-05-29 16:32:58 +08:00
parent 611945be04
commit 3e722a7f15
24 changed files with 17150 additions and 20488 deletions
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CPLD1/CPLD1_Debug.rva
+64 -54
View File
@@ -26,65 +26,75 @@
<LACoreCount>1</LACoreCount>
<WinUI CoreIndex="0">
<TraceSigTreeData>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_cs" NodeType="0" PortIndex="0"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_mosi" NodeType="0" PortIndex="1"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/i_sclk" NodeType="0" PortIndex="2"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/exec_flag" NodeType="0" PortIndex="3"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/i_con_exec" NodeType="0" PortIndex="4"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/slot_exec_flag" NodeType="1" PortIndex="5">
<TraceSignal IsHidden="false" Name="i_rst_n" NodeType="0" PortIndex="0"/>
<TraceSignal IsHidden="false" Name="BUS_Con_1/err_flag" NodeType="0" PortIndex="1"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/err_flag" NodeType="0" PortIndex="2"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_1/err_flag" NodeType="0" PortIndex="3"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_con_exec" NodeType="0" PortIndex="4"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1" NodeType="1" PortIndex="5">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/slot_exec_flag:0" NodeType="2" PortIndex="5"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/slot_exec_flag:1" NodeType="2" PortIndex="6"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/slot_exec_flag:2" NodeType="2" PortIndex="7"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/slot_exec_flag:3" NodeType="2" PortIndex="8"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x01" NodeType="1" PortIndex="9">
<BusRadix Radix="0"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:0" NodeType="2" PortIndex="5"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:1" NodeType="2" PortIndex="6"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:2" NodeType="2" PortIndex="7"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:3" NodeType="2" PortIndex="8"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:4" NodeType="2" PortIndex="9"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:5" NodeType="2" PortIndex="10"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:6" NodeType="2" PortIndex="11"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:7" NodeType="2" PortIndex="12"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:8" NodeType="2" PortIndex="13"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:9" NodeType="2" PortIndex="14"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:10" NodeType="2" PortIndex="15"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:11" NodeType="2" PortIndex="16"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:12" NodeType="2" PortIndex="17"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:13" NodeType="2" PortIndex="18"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:14" NodeType="2" PortIndex="19"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:15" NodeType="2" PortIndex="20"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:16" NodeType="2" PortIndex="21"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:17" NodeType="2" PortIndex="22"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:18" NodeType="2" PortIndex="23"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:19" NodeType="2" PortIndex="24"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:20" NodeType="2" PortIndex="25"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:21" NodeType="2" PortIndex="26"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:22" NodeType="2" PortIndex="27"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_1/i_DC_Con1:23" NodeType="2" PortIndex="28"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1" NodeType="1" PortIndex="29">
<BusRadix Radix="3"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x01:0" NodeType="2" PortIndex="9"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x01:1" NodeType="2" PortIndex="10"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x01:2" NodeType="2" PortIndex="11"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x01:3" NodeType="2" PortIndex="12"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x17" NodeType="1" PortIndex="13">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x17:0" NodeType="2" PortIndex="13"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x17:1" NodeType="2" PortIndex="14"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x17:2" NodeType="2" PortIndex="15"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/OC_x17:3" NodeType="2" PortIndex="16"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN" NodeType="1" PortIndex="17">
<BusRadix Radix="0"/>
<IsExpanded Expand="true"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="o_DMM_EN:0" NodeType="2" PortIndex="17"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:1" NodeType="2" PortIndex="18"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:2" NodeType="2" PortIndex="19"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:3" NodeType="2" PortIndex="20"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:4" NodeType="2" PortIndex="21"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:5" NodeType="2" PortIndex="22"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:6" NodeType="2" PortIndex="23"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:7" NodeType="2" PortIndex="24"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:8" NodeType="2" PortIndex="25"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:9" NodeType="2" PortIndex="26"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:10" NodeType="2" PortIndex="27"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:11" NodeType="2" PortIndex="28"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:12" NodeType="2" PortIndex="29"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:13" NodeType="2" PortIndex="30"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:14" NodeType="2" PortIndex="31"/>
<TraceSignal IsHidden="false" Name="o_DMM_EN:15" NodeType="2" PortIndex="32"/>
<TraceSignal IsHidden="false" Name="o_IO_RC1" NodeType="0" PortIndex="33"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx" NodeType="1" PortIndex="34">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx:0" NodeType="2" PortIndex="34"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx:1" NodeType="2" PortIndex="35"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx:2" NodeType="2" PortIndex="36"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx:3" NodeType="2" PortIndex="37"/>
<TraceSignal IsHidden="false" Name="CPLD_Freq_Con_1/RC_Tx:4" NodeType="2" PortIndex="38"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:0" NodeType="2" PortIndex="29"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:1" NodeType="2" PortIndex="30"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:2" NodeType="2" PortIndex="31"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:3" NodeType="2" PortIndex="32"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:4" NodeType="2" PortIndex="33"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:5" NodeType="2" PortIndex="34"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:6" NodeType="2" PortIndex="35"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:7" NodeType="2" PortIndex="36"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:8" NodeType="2" PortIndex="37"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:9" NodeType="2" PortIndex="38"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:10" NodeType="2" PortIndex="39"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:11" NodeType="2" PortIndex="40"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:12" NodeType="2" PortIndex="41"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:13" NodeType="2" PortIndex="42"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:14" NodeType="2" PortIndex="43"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:15" NodeType="2" PortIndex="44"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:16" NodeType="2" PortIndex="45"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:17" NodeType="2" PortIndex="46"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:18" NodeType="2" PortIndex="47"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:19" NodeType="2" PortIndex="48"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:20" NodeType="2" PortIndex="49"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:21" NodeType="2" PortIndex="50"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:22" NodeType="2" PortIndex="51"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:23" NodeType="2" PortIndex="52"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:24" NodeType="2" PortIndex="53"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:25" NodeType="2" PortIndex="54"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:26" NodeType="2" PortIndex="55"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:27" NodeType="2" PortIndex="56"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:28" NodeType="2" PortIndex="57"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:29" NodeType="2" PortIndex="58"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:30" NodeType="2" PortIndex="59"/>
<TraceSignal IsHidden="false" Name="PMU_OC_1:31" NodeType="2" PortIndex="60"/>
</TraceSigTreeData>
<TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/>
<CoreRun Run="true"/>
CPLD1/CPLD1_Debug.svf
-5798
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CPLD1/CPLD1_Debug.trc
+2051 -2051
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CPLD1/NewExtIns_CPLD1.ldf
+4 -4
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@@ -24,15 +24,15 @@
<Source name="CPLD1_Debug.rva" type="Reveal Analyzer Project File" type_short="RVA">
<Options/>
</Source>
<Source name="NewExtIns_CPLD1.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
<Source name="debug.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
<Source name="debug.rvl" type="Reveal" type_short="Reveal">
<Options/>
</Source>
<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
<Source name="NewExtIns_CPLD1.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
<Source name="tb_RelayConTop/tb_RelayConTop.spf" type="Simulation Project File" type_short="SPF">
<Options/>
</Source>
CPLD1/debug.rvl
+38 -84
View File
@@ -1,7 +1,7 @@
<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/debug.rvl" Date="2026-05-28">
<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/debug.rvl" Date="2026-05-29">
<IP Version="1_6_042617"/>
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD1"/>
<Core InsertDataset="0" Insert="1" Reveal_sig="695772961" Name="RelayConTop_LA0" ID="0">
<Core InsertDataset="0" Insert="1" Reveal_sig="695925353" Name="RelayConTop_LA0" ID="0">
<Setting>
<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
@@ -12,9 +12,7 @@
</Setting>
<Dataset Name="Base">
<Trace>
<Sig Type="SIG" Name="BUS_Con_1/i_cs"/>
<Sig Type="SIG" Name="BUS_Con_1/i_mosi"/>
<Sig Type="SIG" Name="BUS_Con_1/i_sclk"/>
<Sig Type="SIG" Name="i_rst_n"/>
<Sig Type="SIG" Name="BUS_Con_1/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_1/err_flag"/>
<Sig Type="SIG" Name="CPLD_Reg_1/err_flag"/>
@@ -45,88 +43,44 @@
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:22"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:23"/>
</Bus>
<Bus Name="CPLD_Con_1/i_DC_Con2">
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:0"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:1"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:2"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:3"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:4"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:5"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:6"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:7"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:8"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:9"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:10"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:11"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:12"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:13"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:14"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:15"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:16"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:17"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:18"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:19"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:20"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:21"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:22"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con2:23"/>
</Bus>
<Bus Name="CPLD_Con_1/i_DC_Con3">
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:0"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:1"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:2"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:3"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:4"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:5"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:6"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:7"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:8"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:9"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:10"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:11"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:12"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:13"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:14"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:15"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:16"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:17"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:18"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:19"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:20"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:21"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:22"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con3:23"/>
</Bus>
<Bus Name="CPLD_Con_1/i_DC_Con4">
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:0"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:1"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:2"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:3"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:4"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:5"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:6"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:7"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:8"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:9"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:10"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:11"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:12"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:13"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:14"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:15"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:16"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:17"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:18"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:19"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:20"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:21"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:22"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con4:23"/>
<Bus Name="PMU_OC_1">
<Sig Type="SIG" Name="PMU_OC_1:0"/>
<Sig Type="SIG" Name="PMU_OC_1:1"/>
<Sig Type="SIG" Name="PMU_OC_1:2"/>
<Sig Type="SIG" Name="PMU_OC_1:3"/>
<Sig Type="SIG" Name="PMU_OC_1:4"/>
<Sig Type="SIG" Name="PMU_OC_1:5"/>
<Sig Type="SIG" Name="PMU_OC_1:6"/>
<Sig Type="SIG" Name="PMU_OC_1:7"/>
<Sig Type="SIG" Name="PMU_OC_1:8"/>
<Sig Type="SIG" Name="PMU_OC_1:9"/>
<Sig Type="SIG" Name="PMU_OC_1:10"/>
<Sig Type="SIG" Name="PMU_OC_1:11"/>
<Sig Type="SIG" Name="PMU_OC_1:12"/>
<Sig Type="SIG" Name="PMU_OC_1:13"/>
<Sig Type="SIG" Name="PMU_OC_1:14"/>
<Sig Type="SIG" Name="PMU_OC_1:15"/>
<Sig Type="SIG" Name="PMU_OC_1:16"/>
<Sig Type="SIG" Name="PMU_OC_1:17"/>
<Sig Type="SIG" Name="PMU_OC_1:18"/>
<Sig Type="SIG" Name="PMU_OC_1:19"/>
<Sig Type="SIG" Name="PMU_OC_1:20"/>
<Sig Type="SIG" Name="PMU_OC_1:21"/>
<Sig Type="SIG" Name="PMU_OC_1:22"/>
<Sig Type="SIG" Name="PMU_OC_1:23"/>
<Sig Type="SIG" Name="PMU_OC_1:24"/>
<Sig Type="SIG" Name="PMU_OC_1:25"/>
<Sig Type="SIG" Name="PMU_OC_1:26"/>
<Sig Type="SIG" Name="PMU_OC_1:27"/>
<Sig Type="SIG" Name="PMU_OC_1:28"/>
<Sig Type="SIG" Name="PMU_OC_1:29"/>
<Sig Type="SIG" Name="PMU_OC_1:30"/>
<Sig Type="SIG" Name="PMU_OC_1:31"/>
</Bus>
</Trace>
<Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="i_cs,"/>
<TU Serialbits="0" Type="0" ID="2" Sig="i_sclk,"/>
<TU Serialbits="0" Type="0" ID="1" Sig="i_rst_n,"/>
<TU Serialbits="0" Type="0" ID="2" Sig="CPLD_Con_1/i_con_exec,"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
</Trigger>
CPLD1/debug.rvs
+83 -129
View File
@@ -1,130 +1,84 @@
<Project ModBy="Inserter" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/debug.rvl" Date="2026-05-28">
<Core Name="RelayConTop_LA0">
<Setting>
<Capture SamplesPerTrig="2048" NumTrigsCap="1"/>
<Event EventCnt="0" CntEnableRun="0"/>
<TrigSetting PreTrgSamples="" AND_ALL="0" PostTrgSamples="" TURadix="0"/>
</Setting>
<Dataset Name="Base">
<Trace>
<Sig Name="BUS_Con_1/i_cs"/>
<Sig Name="BUS_Con_1/i_mosi"/>
<Sig Name="BUS_Con_1/i_sclk"/>
<Sig Name="BUS_Con_1/err_flag"/>
<Sig Name="CPLD_Con_1/err_flag"/>
<Sig Name="CPLD_Reg_1/err_flag"/>
<Sig Name="CPLD_Con_1/i_con_exec"/>
<Bus Name="CPLD_Con_1/i_DC_Con1" Radix="0">
<Sig Name="CPLD_Con_1/i_DC_Con1:0"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:1"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:2"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:3"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:4"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:5"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:6"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:7"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:8"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:9"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:10"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:11"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:12"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:13"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:14"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:15"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:16"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:17"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:18"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:19"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:20"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:21"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:22"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:23"/>
</Bus>
<Bus Name="CPLD_Con_1/i_DC_Con2" Radix="0">
<Sig Name="CPLD_Con_1/i_DC_Con2:0"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:1"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:2"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:3"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:4"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:5"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:6"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:7"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:8"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:9"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:10"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:11"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:12"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:13"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:14"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:15"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:16"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:17"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:18"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:19"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:20"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:21"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:22"/>
<Sig Name="CPLD_Con_1/i_DC_Con2:23"/>
</Bus>
<Bus Name="CPLD_Con_1/i_DC_Con3" Radix="0">
<Sig Name="CPLD_Con_1/i_DC_Con3:0"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:1"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:2"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:3"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:4"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:5"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:6"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:7"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:8"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:9"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:10"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:11"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:12"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:13"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:14"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:15"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:16"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:17"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:18"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:19"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:20"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:21"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:22"/>
<Sig Name="CPLD_Con_1/i_DC_Con3:23"/>
</Bus>
<Bus Name="CPLD_Con_1/i_DC_Con4" Radix="0">
<Sig Name="CPLD_Con_1/i_DC_Con4:0"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:1"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:2"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:3"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:4"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:5"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:6"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:7"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:8"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:9"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:10"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:11"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:12"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:13"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:14"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:15"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:16"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:17"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:18"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:19"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:20"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:21"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:22"/>
<Sig Name="CPLD_Con_1/i_DC_Con4:23"/>
</Bus>
</Trace>
<Trigger>
<TU Operator="7" Name="TU1" ID="1" Value="0" Radix="0"/>
<TU Operator="6" Name="TU2" ID="2" Value="0" Radix="0"/>
<TE Enable="1" Expression="TU1" Name="TE1" ID="1"/>
<TE Enable="1" Expression="TU2" Name="TE2" ID="2"/>
</Trigger>
</Dataset>
</Core>
<Project ModBy="Analyzer" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/debug.rvs" Date="2026-05-29">
<Core Name="RelayConTop_LA0">
<Setting>
<Capture SamplesPerTrig="2048" NumTrigsCap="1"/>
<Event EventCnt="0" CntEnableRun="0"/>
<TrigSetting PreTrgSamples="" AND_ALL="0" PostTrgSamples="" TURadix="0"/>
</Setting>
<Dataset Name="Base">
<Trace>
<Sig Name="i_rst_n"/>
<Sig Name="BUS_Con_1/err_flag"/>
<Sig Name="CPLD_Con_1/err_flag"/>
<Sig Name="CPLD_Reg_1/err_flag"/>
<Sig Name="CPLD_Con_1/i_con_exec"/>
<Bus Name="CPLD_Con_1/i_DC_Con1" Radix="0">
<Sig Name="CPLD_Con_1/i_DC_Con1:0"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:1"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:2"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:3"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:4"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:5"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:6"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:7"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:8"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:9"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:10"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:11"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:12"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:13"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:14"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:15"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:16"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:17"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:18"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:19"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:20"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:21"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:22"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:23"/>
</Bus>
<Bus Name="PMU_OC_1" Radix="0">
<Sig Name="PMU_OC_1:0"/>
<Sig Name="PMU_OC_1:1"/>
<Sig Name="PMU_OC_1:2"/>
<Sig Name="PMU_OC_1:3"/>
<Sig Name="PMU_OC_1:4"/>
<Sig Name="PMU_OC_1:5"/>
<Sig Name="PMU_OC_1:6"/>
<Sig Name="PMU_OC_1:7"/>
<Sig Name="PMU_OC_1:8"/>
<Sig Name="PMU_OC_1:9"/>
<Sig Name="PMU_OC_1:10"/>
<Sig Name="PMU_OC_1:11"/>
<Sig Name="PMU_OC_1:12"/>
<Sig Name="PMU_OC_1:13"/>
<Sig Name="PMU_OC_1:14"/>
<Sig Name="PMU_OC_1:15"/>
<Sig Name="PMU_OC_1:16"/>
<Sig Name="PMU_OC_1:17"/>
<Sig Name="PMU_OC_1:18"/>
<Sig Name="PMU_OC_1:19"/>
<Sig Name="PMU_OC_1:20"/>
<Sig Name="PMU_OC_1:21"/>
<Sig Name="PMU_OC_1:22"/>
<Sig Name="PMU_OC_1:23"/>
<Sig Name="PMU_OC_1:24"/>
<Sig Name="PMU_OC_1:25"/>
<Sig Name="PMU_OC_1:26"/>
<Sig Name="PMU_OC_1:27"/>
<Sig Name="PMU_OC_1:28"/>
<Sig Name="PMU_OC_1:29"/>
<Sig Name="PMU_OC_1:30"/>
<Sig Name="PMU_OC_1:31"/>
</Bus>
</Trace>
<Trigger>
<TU Operator="7" Name="TU2" ID="1" Value="0" Radix="0"/>
<TU Operator="6" Name="TU3" ID="2" Value="0" Radix="0"/>
<TE Enable="1" Expression="TU2" Name="TE2" ID="1"/>
<TE Enable="1" Expression="TU3" Name="TE3" ID="2"/>
</Trigger>
</Dataset>
</Core>
</Project>
CPLD1/impl1/NewExtIns_CPLD1_impl1.bit
BIN
View File
Binary file not shown.
CPLD1/impl1/NewExtIns_CPLD1_impl1.jed
+3592 -3592
View File
File diff suppressed because it is too large Load Diff
CPLD1/impl1/impl1.xcf
+4 -4
View File
@@ -19,9 +19,9 @@
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
<File>D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/impl1/NewExtIns_CPLD1_impl1.jed</File>
<FileTime>01/19/26 12:45:04</FileTime>
<JedecChecksum>0x75FB</JedecChecksum>
<File>C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/impl1/NewExtIns_CPLD1_impl1.jed</File>
<FileTime>05/29/26 15:43:40</FileTime>
<JedecChecksum>0x092E</JedecChecksum>
<Operation>FLASH Erase,Program,Verify</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
@@ -47,6 +47,6 @@
<CableOptions>
<CableName>USB</CableName>
<PortAdd>EzUSB-0</PortAdd>
<USBID>\\?\usb#vid_1134&amp;amp;pid_8001#9&amp;amp;2fe42d87&amp;amp;0&amp;amp;2#</USBID>
<USBID>\\?\usb#vid_1134&amp;amp;pid_8001#6&amp;amp;ca080be&amp;amp;0&amp;amp;3#</USBID>
</CableOptions>
</ispXCF>
CPLD2/debug.rvl
+107 -39
View File
@@ -1,7 +1,7 @@
<Project ModBy="Inserter" SigType="0" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD2/debug.rvl" Date="2026-05-26">
<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD2/debug.rvl" Date="2026-05-29">
<IP Version="1_6_042617"/>
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD2"/>
<Core InsertDataset="0" Insert="1" Reveal_sig="695532641" Name="RelayConTop_LA0" ID="0">
<Core InsertDataset="0" Insert="1" Reveal_sig="695926902" Name="RelayConTop_LA0" ID="0">
<Setting>
<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
@@ -16,46 +16,114 @@
<Sig Type="SIG" Name="BUS_Con_2/i_cs"/>
<Sig Type="SIG" Name="BUS_Con_2/i_sclk"/>
<Sig Type="SIG" Name="BUS_Con_2/i_mosi"/>
<Sig Type="SIG" Name="BUS_Con_2/i_reg_busy"/>
<Sig Type="SIG" Name="CPLD_Reg_2/o_exec"/>
<Bus Name="RC_T">
<Sig Type="SIG" Name="RC_T:0"/>
<Sig Type="SIG" Name="RC_T:1"/>
<Sig Type="SIG" Name="RC_T:2"/>
<Sig Type="SIG" Name="RC_T:3"/>
<Sig Type="SIG" Name="RC_T:4"/>
<Sig Type="SIG" Name="RC_T:5"/>
<Sig Type="SIG" Name="RC_T:6"/>
<Sig Type="SIG" Name="RC_T:7"/>
<Sig Type="SIG" Name="RC_T:8"/>
<Sig Type="SIG" Name="RC_T:9"/>
<Sig Type="SIG" Name="RC_T:10"/>
<Sig Type="SIG" Name="RC_T:11"/>
<Sig Type="SIG" Name="RC_T:12"/>
<Sig Type="SIG" Name="RC_T:13"/>
<Sig Type="SIG" Name="RC_T:14"/>
<Sig Type="SIG" Name="RC_T:15"/>
<Sig Type="SIG" Name="RC_T:16"/>
<Sig Type="SIG" Name="RC_T:17"/>
<Sig Type="SIG" Name="RC_T:18"/>
<Sig Type="SIG" Name="RC_T:19"/>
<Sig Type="SIG" Name="RC_T:20"/>
<Sig Type="SIG" Name="RC_T:21"/>
<Sig Type="SIG" Name="RC_T:22"/>
<Sig Type="SIG" Name="RC_T:23"/>
<Sig Type="SIG" Name="RC_T:24"/>
<Sig Type="SIG" Name="RC_T:25"/>
<Sig Type="SIG" Name="RC_T:26"/>
<Sig Type="SIG" Name="RC_T:27"/>
<Sig Type="SIG" Name="RC_T:28"/>
<Sig Type="SIG" Name="RC_T:29"/>
<Sig Type="SIG" Name="RC_T:30"/>
<Sig Type="SIG" Name="RC_T:31"/>
</Bus>
<Sig Type="SIG" Name="CPLD_Con_2/i_con_exec"/>
<Sig Type="SIG" Name="BUS_Con_2/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_2/err_flag"/>
<Sig Type="SIG" Name="CPLD_Reg_2/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_2/i_con_exec"/>
<Bus Name="DC_Con1">
<Sig Type="SIG" Name="DC_Con1:0"/>
<Sig Type="SIG" Name="DC_Con1:1"/>
<Sig Type="SIG" Name="DC_Con1:2"/>
<Sig Type="SIG" Name="DC_Con1:3"/>
<Sig Type="SIG" Name="DC_Con1:4"/>
<Sig Type="SIG" Name="DC_Con1:5"/>
<Sig Type="SIG" Name="DC_Con1:6"/>
<Sig Type="SIG" Name="DC_Con1:7"/>
<Sig Type="SIG" Name="DC_Con1:8"/>
<Sig Type="SIG" Name="DC_Con1:9"/>
<Sig Type="SIG" Name="DC_Con1:10"/>
<Sig Type="SIG" Name="DC_Con1:11"/>
<Sig Type="SIG" Name="DC_Con1:12"/>
<Sig Type="SIG" Name="DC_Con1:13"/>
<Sig Type="SIG" Name="DC_Con1:14"/>
<Sig Type="SIG" Name="DC_Con1:15"/>
<Sig Type="SIG" Name="DC_Con1:16"/>
<Sig Type="SIG" Name="DC_Con1:17"/>
<Sig Type="SIG" Name="DC_Con1:18"/>
<Sig Type="SIG" Name="DC_Con1:19"/>
<Sig Type="SIG" Name="DC_Con1:20"/>
<Sig Type="SIG" Name="DC_Con1:21"/>
<Sig Type="SIG" Name="DC_Con1:22"/>
<Sig Type="SIG" Name="DC_Con1:23"/>
</Bus>
<Bus Name="DC_Con2">
<Sig Type="SIG" Name="DC_Con2:0"/>
<Sig Type="SIG" Name="DC_Con2:1"/>
<Sig Type="SIG" Name="DC_Con2:2"/>
<Sig Type="SIG" Name="DC_Con2:3"/>
<Sig Type="SIG" Name="DC_Con2:4"/>
<Sig Type="SIG" Name="DC_Con2:5"/>
<Sig Type="SIG" Name="DC_Con2:6"/>
<Sig Type="SIG" Name="DC_Con2:7"/>
<Sig Type="SIG" Name="DC_Con2:8"/>
<Sig Type="SIG" Name="DC_Con2:9"/>
<Sig Type="SIG" Name="DC_Con2:10"/>
<Sig Type="SIG" Name="DC_Con2:11"/>
<Sig Type="SIG" Name="DC_Con2:12"/>
<Sig Type="SIG" Name="DC_Con2:13"/>
<Sig Type="SIG" Name="DC_Con2:14"/>
<Sig Type="SIG" Name="DC_Con2:15"/>
<Sig Type="SIG" Name="DC_Con2:16"/>
<Sig Type="SIG" Name="DC_Con2:17"/>
<Sig Type="SIG" Name="DC_Con2:18"/>
<Sig Type="SIG" Name="DC_Con2:19"/>
<Sig Type="SIG" Name="DC_Con2:20"/>
<Sig Type="SIG" Name="DC_Con2:21"/>
<Sig Type="SIG" Name="DC_Con2:22"/>
<Sig Type="SIG" Name="DC_Con2:23"/>
</Bus>
<Bus Name="DC_Con3">
<Sig Type="SIG" Name="DC_Con3:0"/>
<Sig Type="SIG" Name="DC_Con3:1"/>
<Sig Type="SIG" Name="DC_Con3:2"/>
<Sig Type="SIG" Name="DC_Con3:3"/>
<Sig Type="SIG" Name="DC_Con3:4"/>
<Sig Type="SIG" Name="DC_Con3:5"/>
<Sig Type="SIG" Name="DC_Con3:6"/>
<Sig Type="SIG" Name="DC_Con3:7"/>
<Sig Type="SIG" Name="DC_Con3:8"/>
<Sig Type="SIG" Name="DC_Con3:9"/>
<Sig Type="SIG" Name="DC_Con3:10"/>
<Sig Type="SIG" Name="DC_Con3:11"/>
<Sig Type="SIG" Name="DC_Con3:12"/>
<Sig Type="SIG" Name="DC_Con3:13"/>
<Sig Type="SIG" Name="DC_Con3:14"/>
<Sig Type="SIG" Name="DC_Con3:15"/>
<Sig Type="SIG" Name="DC_Con3:16"/>
<Sig Type="SIG" Name="DC_Con3:17"/>
<Sig Type="SIG" Name="DC_Con3:18"/>
<Sig Type="SIG" Name="DC_Con3:19"/>
<Sig Type="SIG" Name="DC_Con3:20"/>
<Sig Type="SIG" Name="DC_Con3:21"/>
<Sig Type="SIG" Name="DC_Con3:22"/>
<Sig Type="SIG" Name="DC_Con3:23"/>
</Bus>
<Bus Name="DC_Con4">
<Sig Type="SIG" Name="DC_Con4:0"/>
<Sig Type="SIG" Name="DC_Con4:1"/>
<Sig Type="SIG" Name="DC_Con4:2"/>
<Sig Type="SIG" Name="DC_Con4:3"/>
<Sig Type="SIG" Name="DC_Con4:4"/>
<Sig Type="SIG" Name="DC_Con4:5"/>
<Sig Type="SIG" Name="DC_Con4:6"/>
<Sig Type="SIG" Name="DC_Con4:7"/>
<Sig Type="SIG" Name="DC_Con4:8"/>
<Sig Type="SIG" Name="DC_Con4:9"/>
<Sig Type="SIG" Name="DC_Con4:10"/>
<Sig Type="SIG" Name="DC_Con4:11"/>
<Sig Type="SIG" Name="DC_Con4:12"/>
<Sig Type="SIG" Name="DC_Con4:13"/>
<Sig Type="SIG" Name="DC_Con4:14"/>
<Sig Type="SIG" Name="DC_Con4:15"/>
<Sig Type="SIG" Name="DC_Con4:16"/>
<Sig Type="SIG" Name="DC_Con4:17"/>
<Sig Type="SIG" Name="DC_Con4:18"/>
<Sig Type="SIG" Name="DC_Con4:19"/>
<Sig Type="SIG" Name="DC_Con4:20"/>
<Sig Type="SIG" Name="DC_Con4:21"/>
<Sig Type="SIG" Name="DC_Con4:22"/>
<Sig Type="SIG" Name="DC_Con4:23"/>
</Bus>
</Trace>
<Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="i_cs,"/>
CPLD2/debug.rvs
+107 -39
View File
@@ -1,4 +1,4 @@
<Project ModBy="Inserter" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD2/debug.rvl" Date="2026-05-26">
<Project ModBy="Inserter" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD2/debug.rvl" Date="2026-05-29">
<Core Name="RelayConTop_LA0">
<Setting>
<Capture SamplesPerTrig="2048" NumTrigsCap="1"/>
@@ -11,50 +11,118 @@
<Sig Name="BUS_Con_2/i_cs"/>
<Sig Name="BUS_Con_2/i_sclk"/>
<Sig Name="BUS_Con_2/i_mosi"/>
<Sig Name="BUS_Con_2/i_reg_busy"/>
<Sig Name="CPLD_Reg_2/o_exec"/>
<Bus Name="RC_T" Radix="0">
<Sig Name="RC_T:0"/>
<Sig Name="RC_T:1"/>
<Sig Name="RC_T:2"/>
<Sig Name="RC_T:3"/>
<Sig Name="RC_T:4"/>
<Sig Name="RC_T:5"/>
<Sig Name="RC_T:6"/>
<Sig Name="RC_T:7"/>
<Sig Name="RC_T:8"/>
<Sig Name="RC_T:9"/>
<Sig Name="RC_T:10"/>
<Sig Name="RC_T:11"/>
<Sig Name="RC_T:12"/>
<Sig Name="RC_T:13"/>
<Sig Name="RC_T:14"/>
<Sig Name="RC_T:15"/>
<Sig Name="RC_T:16"/>
<Sig Name="RC_T:17"/>
<Sig Name="RC_T:18"/>
<Sig Name="RC_T:19"/>
<Sig Name="RC_T:20"/>
<Sig Name="RC_T:21"/>
<Sig Name="RC_T:22"/>
<Sig Name="RC_T:23"/>
<Sig Name="RC_T:24"/>
<Sig Name="RC_T:25"/>
<Sig Name="RC_T:26"/>
<Sig Name="RC_T:27"/>
<Sig Name="RC_T:28"/>
<Sig Name="RC_T:29"/>
<Sig Name="RC_T:30"/>
<Sig Name="RC_T:31"/>
</Bus>
<Sig Name="CPLD_Con_2/i_con_exec"/>
<Sig Name="BUS_Con_2/err_flag"/>
<Sig Name="CPLD_Con_2/err_flag"/>
<Sig Name="CPLD_Reg_2/err_flag"/>
<Sig Name="CPLD_Con_2/i_con_exec"/>
<Bus Name="DC_Con1" Radix="0">
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<Bus Name="DC_Con4" Radix="0">
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<Trigger>
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CPLD2/impl1/NewExtIns_CPLD2_impl1.bit
BIN
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CPLD2/impl1/NewExtIns_CPLD2_impl1.jed
+3552 -3552
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CPLD2/impl1/NewExtIns_CPLD2_impl1_synplify.lpf
+1 -1
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@@ -1,5 +1,5 @@
#
# Logical Preferences generated for Lattice by Synplify map202309lat, Build 191R.
# Logical Preferences generated for Lattice by Synplify map202303lat, Build 132R.
#
# Period Constraints
CPLD2/untitled.svf
+76 -120
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CPLD3/CPLD3_Debug.rva
+107 -57
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@@ -27,75 +27,125 @@
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CPLD3/CPLD3_Debug.svf
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CPLD3/CPLD3_Debug.trc
+2051 -2051
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CPLD3/debug.rvl
+5 -4
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@@ -1,7 +1,7 @@
<Project ModBy="Inserter" SigType="0" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD3/debug.rvl" Date="2026-05-26">
<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/debug.rvl" Date="2026-05-29">
<IP Version="1_6_042617"/>
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD3"/>
<Core InsertDataset="0" Insert="1" Reveal_sig="695532996" Name="RelayConTop_LA0" ID="0">
<Core InsertDataset="0" Insert="1" Reveal_sig="695927056" Name="RelayConTop_LA0" ID="0">
<Setting>
<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
@@ -12,9 +12,9 @@
</Setting>
<Dataset Name="Base">
<Trace>
<Sig Type="SIG" Name="Bus_Con_3/i_sclk"/>
<Sig Type="SIG" Name="i_rst_n"/>
<Sig Type="SIG" Name="Bus_Con_3/i_cs"/>
<Sig Type="SIG" Name="Bus_Con_3/i_sclk"/>
<Sig Type="SIG" Name="Bus_Con_3/i_mosi"/>
<Sig Type="SIG" Name="Bus_Con_3/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_3/err_flag"/>
@@ -126,7 +126,8 @@
</Bus>
</Trace>
<Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="con_exec,"/>
<TU Serialbits="0" Type="0" ID="1" Sig="i_cs,"/>
<TU Serialbits="0" Type="0" ID="2" Sig="i_rst_n,"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
</Trigger>
</Dataset>
CPLD3/debug.rvs
+129 -128
View File
@@ -1,129 +1,130 @@
<Project ModBy="Inserter" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD3/debug.rvl" Date="2026-05-26">
<Core Name="RelayConTop_LA0">
<Setting>
<Capture SamplesPerTrig="2048" NumTrigsCap="1"/>
<Event EventCnt="0" CntEnableRun="0"/>
<TrigSetting PreTrgSamples="" AND_ALL="0" PostTrgSamples="" TURadix="0"/>
</Setting>
<Dataset Name="Base">
<Trace>
<Sig Name="Bus_Con_3/i_sclk"/>
<Sig Name="i_rst_n"/>
<Sig Name="Bus_Con_3/i_cs"/>
<Sig Name="Bus_Con_3/i_mosi"/>
<Sig Name="Bus_Con_3/err_flag"/>
<Sig Name="CPLD_Con_3/err_flag"/>
<Sig Name="CPLD_Reg_3/err_flag"/>
<Sig Name="CPLD_Con_3/i_con_exec"/>
<Bus Name="CPLD_Con_3/i_DC_Con1" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con1:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con2" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con2:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con3" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con3:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con4" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con4:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:23"/>
</Bus>
</Trace>
<Trigger>
<TU Operator="6" Name="TU1" ID="1" Value="0" Radix="0"/>
<TE Enable="1" Expression="TU1" Name="TE1" ID="1"/>
</Trigger>
</Dataset>
</Core>
<Project ModBy="Analyzer" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/debug.rvs" Date="2026-05-29">
<Core Name="RelayConTop_LA0">
<Setting>
<Capture SamplesPerTrig="2048" NumTrigsCap="1"/>
<Event EventCnt="0" CntEnableRun="0"/>
<TrigSetting PreTrgSamples="" AND_ALL="0" PostTrgSamples="" TURadix="0"/>
</Setting>
<Dataset Name="Base">
<Trace>
<Sig Name="i_rst_n"/>
<Sig Name="Bus_Con_3/i_cs"/>
<Sig Name="Bus_Con_3/i_sclk"/>
<Sig Name="Bus_Con_3/i_mosi"/>
<Sig Name="Bus_Con_3/err_flag"/>
<Sig Name="CPLD_Con_3/err_flag"/>
<Sig Name="CPLD_Reg_3/err_flag"/>
<Sig Name="CPLD_Con_3/i_con_exec"/>
<Bus Name="CPLD_Con_3/i_DC_Con1" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con1:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con2" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con2:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con3" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con3:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con4" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con4:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:23"/>
</Bus>
</Trace>
<Trigger>
<TU Operator="7" Name="TU1" ID="1" Value="0" Radix="0"/>
<TU Operator="7" Name="TU2" ID="2" Value="0" Radix="0"/>
<TE Enable="1" Expression="TU1" Name="TE1" ID="1"/>
</Trigger>
</Dataset>
</Core>
</Project>
CPLD3/impl1/NewExtIns_CPLD3_impl1.bit
BIN
View File
Binary file not shown.
CPLD3/impl1/NewExtIns_CPLD3_impl1.jed
+2776 -2776
View File
File diff suppressed because it is too large Load Diff
CPLD3/impl1/NewExtIns_CPLD3_impl1_synplify.lpf
+1 -1
View File
@@ -1,5 +1,5 @@
#
# Logical Preferences generated for Lattice by Synplify map202309lat, Build 191R.
# Logical Preferences generated for Lattice by Synplify map202303lat, Build 132R.
#
# Period Constraints
CPLD3/impl1/impl1.xcf
+4 -4
View File
@@ -19,9 +19,9 @@
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
<File>D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD3/impl1/NewExtIns_CPLD3_impl1.jed</File>
<FileTime>01/19/26 18:24:04</FileTime>
<JedecChecksum>0x4480</JedecChecksum>
<File>C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/impl1/NewExtIns_CPLD3_impl1.jed</File>
<FileTime>05/29/26 16:05:22</FileTime>
<JedecChecksum>0xA758</JedecChecksum>
<Operation>FLASH Erase,Program,Verify</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
@@ -47,6 +47,6 @@
<CableOptions>
<CableName>USB</CableName>
<PortAdd>EzUSB-0</PortAdd>
<USBID>\\?\usb#vid_1134&amp;amp;pid_8001#9&amp;amp;2fe42d87&amp;amp;0&amp;amp;2#</USBID>
<USBID>\\?\usb#vid_1134&amp;amp;pid_8001#6&amp;amp;ca080be&amp;amp;0&amp;amp;3#</USBID>
</CableOptions>
</ispXCF>