90 lines
5.1 KiB
Plaintext
90 lines
5.1 KiB
Plaintext
<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/debug.rvl" Date="2026-05-29">
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<IP Version="1_6_042617"/>
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<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD1"/>
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<Core InsertDataset="0" Insert="1" Reveal_sig="695925353" Name="RelayConTop_LA0" ID="0">
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<Setting>
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<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
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<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
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<Capture Mode="0" MinSamplesPerTrig="8"/>
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<Event CntEnable="0" MaxEventCnt="8"/>
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<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_RelayConTop_LA0_net"/>
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<DistRAM Disable="0"/>
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</Setting>
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<Dataset Name="Base">
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<Trace>
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<Sig Type="SIG" Name="i_rst_n"/>
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<Sig Type="SIG" Name="BUS_Con_1/err_flag"/>
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<Sig Type="SIG" Name="CPLD_Con_1/err_flag"/>
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<Sig Type="SIG" Name="CPLD_Reg_1/err_flag"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_con_exec"/>
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<Bus Name="CPLD_Con_1/i_DC_Con1">
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:0"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:1"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:2"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:3"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:4"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:5"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:6"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:7"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:8"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:9"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:10"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:11"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:12"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:13"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:14"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:15"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:16"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:17"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:18"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:19"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:20"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:21"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:22"/>
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<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:23"/>
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</Bus>
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<Bus Name="PMU_OC_1">
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<Sig Type="SIG" Name="PMU_OC_1:0"/>
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<Sig Type="SIG" Name="PMU_OC_1:1"/>
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<Sig Type="SIG" Name="PMU_OC_1:2"/>
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<Sig Type="SIG" Name="PMU_OC_1:3"/>
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<Sig Type="SIG" Name="PMU_OC_1:4"/>
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<Sig Type="SIG" Name="PMU_OC_1:5"/>
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<Sig Type="SIG" Name="PMU_OC_1:6"/>
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<Sig Type="SIG" Name="PMU_OC_1:7"/>
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<Sig Type="SIG" Name="PMU_OC_1:8"/>
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<Sig Type="SIG" Name="PMU_OC_1:9"/>
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<Sig Type="SIG" Name="PMU_OC_1:10"/>
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<Sig Type="SIG" Name="PMU_OC_1:11"/>
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<Sig Type="SIG" Name="PMU_OC_1:12"/>
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<Sig Type="SIG" Name="PMU_OC_1:13"/>
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<Sig Type="SIG" Name="PMU_OC_1:14"/>
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<Sig Type="SIG" Name="PMU_OC_1:15"/>
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<Sig Type="SIG" Name="PMU_OC_1:16"/>
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<Sig Type="SIG" Name="PMU_OC_1:17"/>
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<Sig Type="SIG" Name="PMU_OC_1:18"/>
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<Sig Type="SIG" Name="PMU_OC_1:19"/>
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<Sig Type="SIG" Name="PMU_OC_1:20"/>
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<Sig Type="SIG" Name="PMU_OC_1:21"/>
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<Sig Type="SIG" Name="PMU_OC_1:22"/>
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<Sig Type="SIG" Name="PMU_OC_1:23"/>
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<Sig Type="SIG" Name="PMU_OC_1:24"/>
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<Sig Type="SIG" Name="PMU_OC_1:25"/>
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<Sig Type="SIG" Name="PMU_OC_1:26"/>
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<Sig Type="SIG" Name="PMU_OC_1:27"/>
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<Sig Type="SIG" Name="PMU_OC_1:28"/>
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<Sig Type="SIG" Name="PMU_OC_1:29"/>
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<Sig Type="SIG" Name="PMU_OC_1:30"/>
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<Sig Type="SIG" Name="PMU_OC_1:31"/>
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</Bus>
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</Trace>
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<Trigger>
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<TU Serialbits="0" Type="0" ID="1" Sig="i_rst_n,"/>
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<TU Serialbits="0" Type="0" ID="2" Sig="CPLD_Con_1/i_con_exec,"/>
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<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
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<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
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</Trigger>
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</Dataset>
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</Core>
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</Project>
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