39 lines
1.7 KiB
XML
39 lines
1.7 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<BaliProject version="3.2" title="NewExtIns_CPLD2" device="LCMXO2-7000HC-4FG484C" default_implementation="impl1">
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<Options/>
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<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
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<Options def_top="RelayConTop" top="RelayConTop"/>
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<Source name="RelayConTop.v" type="Verilog" type_short="Verilog">
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<Options top_module="RelayConTop"/>
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</Source>
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<Source name="BUS_Con.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="Reg_file.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="tb_RelayConTop.sv" type="Verilog" type_short="Verilog" syn_sim="SimOnly">
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<Options VerilogStandard="System Verilog"/>
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</Source>
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<Source name="CPLD_Con.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="NewExtIns_CPLD2.lpf" type="Logic Preference" type_short="LPF">
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<Options/>
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</Source>
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<Source name="debug.rvl" type="Reveal" type_short="Reveal">
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<Options/>
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</Source>
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<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
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<Options/>
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</Source>
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<Source name="tb_RelayConTop/tb_RelayConTop.spf" type="Simulation Project File" type_short="SPF">
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<Options/>
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</Source>
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<Source name="untitled.rva" type="Reveal Analyzer Project File" type_short="RVA">
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<Options/>
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</Source>
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</Implementation>
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<Strategy name="Strategy1" file="NewExtInsRelay1.sty"/>
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</BaliProject>
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