Jeremy Shen 3b268f6583 Migrate to Vitis2023.2 version

2026-05-26 17:02:52 +08:00

1.Docs

PMU DC Control Output & bug fix

2026-05-20 18:21:42 +08:00

2.FW

Migrate to Vitis2023.2 version

2026-05-26 17:02:52 +08:00

3.FW_Docs

Add Zynq project files

2026-05-25 18:12:01 +08:00

scripts

Add testbenches

2026-05-25 09:29:23 +08:00

.gitignore

Add *.metadata/ to ignore items

2026-05-25 18:11:36 +08:00

install.sh

Add Zynq test prj

2026-05-15 16:13:10 +08:00

S

Description

新仪表校准板仓库

113 MiB

Languages

C 87.6%

Makefile 4.8%

Verilog 1.8%

VHDL 1.6%

Assembly 1.5%

Other 2.6%