Add Zynq test prj
This commit is contained in:
Jeremy Shen
@@ -10,6 +10,7 @@ Thumbs.db
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*~
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*.bak
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*.tmp
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*lock*
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# ===========================
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# OpenCode
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@@ -118,6 +119,9 @@ usage_statistics_webtalk.*
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*.tcl.old
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*.tcl.bak
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*cache
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*gen
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# 工具生成目录
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/impl/
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/_diamond/
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@@ -0,0 +1,8 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2018.3 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
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<labtools version="1" minor="0">
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<HWSession Dir="hw_1" File="hw.xml"/>
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</labtools>
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Load Diff
@@ -0,0 +1,639 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<wave_config>
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<wave_state>
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</wave_state>
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<db_ref_list>
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<db_ref path="D:/WORK/ManLin/Verify/FPGA/Zynq/Z035/NewExtInst_Debug/NewExtInst_Debug.hw/hw_1/wave/hw_ila_data_1/hw_ila_data_1.wdb" id="1">
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<top_modules>
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</top_modules>
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</db_ref>
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</db_ref_list>
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<zoom_setting>
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<ZoomStartTime time="0fs"></ZoomStartTime>
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<ZoomEndTime time="1024001fs"></ZoomEndTime>
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<Cursor1Time time="1024000fs"></Cursor1Time>
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</zoom_setting>
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<column_width_setting>
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<NameColumnWidth column_width="417"></NameColumnWidth>
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<ValueColumnWidth column_width="155"></ValueColumnWidth>
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</column_width_setting>
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<WVObjectSize size="77" />
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<wave_markers>
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</wave_markers>
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<wvobject fp_name="EMIO_0_tri_i_0" type="logic">
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<obj_property name="DisplayName">FullPathName</obj_property>
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||||
<obj_property name="ElementShortName">EMIO_0_tri_i_0</obj_property>
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||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_0</obj_property>
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<obj_property name="Radix">HEXRADIX</obj_property>
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<obj_property name="LABELRADIX">true</obj_property>
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||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
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</wvobject>
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<wvobject fp_name="EMIO_0_tri_i_1" type="logic">
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<obj_property name="DisplayName">FullPathName</obj_property>
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<obj_property name="ElementShortName">EMIO_0_tri_i_1</obj_property>
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<obj_property name="ObjectShortName">EMIO_0_tri_i_1</obj_property>
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||||
<obj_property name="Radix">HEXRADIX</obj_property>
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<obj_property name="LABELRADIX">true</obj_property>
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<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
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</wvobject>
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<wvobject fp_name="EMIO_0_tri_i_2" type="logic">
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<obj_property name="DisplayName">FullPathName</obj_property>
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<obj_property name="ElementShortName">EMIO_0_tri_i_2</obj_property>
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<obj_property name="ObjectShortName">EMIO_0_tri_i_2</obj_property>
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||||
<obj_property name="Radix">HEXRADIX</obj_property>
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||||
<obj_property name="LABELRADIX">true</obj_property>
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||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
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</wvobject>
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<wvobject fp_name="EMIO_0_tri_i_3" type="logic">
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<obj_property name="DisplayName">FullPathName</obj_property>
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||||
<obj_property name="ElementShortName">EMIO_0_tri_i_3</obj_property>
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||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_3</obj_property>
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<obj_property name="Radix">HEXRADIX</obj_property>
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<obj_property name="LABELRADIX">true</obj_property>
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<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
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</wvobject>
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||||
<wvobject fp_name="EMIO_0_tri_i_4" type="logic">
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<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_4</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_4</obj_property>
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||||
<obj_property name="Radix">HEXRADIX</obj_property>
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||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_5" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_5</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_5</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_6" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_6</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_6</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
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||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
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||||
<wvobject fp_name="EMIO_0_tri_i_7" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_7</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_7</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_8" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_8</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_8</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_9" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_9</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_9</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_10" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_10</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_10</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_11" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_11</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_11</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_12" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_12</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_12</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_13" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_13</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_13</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_14" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_14</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_14</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_15" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_15</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_15</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_16" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_16</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_16</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_17" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_17</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_17</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_18" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_18</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_18</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_19" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_19</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_19</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_20" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_20</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_20</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_21" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_21</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_21</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_22" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_22</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_22</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_23" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_23</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_23</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_24" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_24</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_24</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_25" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_25</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_25</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_26" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_26</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_26</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_27" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_27</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_27</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_28" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_28</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_28</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_29" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_29</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_29</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_30" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_30</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_30</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_31" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_31</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_31</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_i_32" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_i_32</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_i_32</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
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<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
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</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_0" type="logic">
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<obj_property name="DisplayName">FullPathName</obj_property>
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<obj_property name="ElementShortName">EMIO_0_tri_o_0</obj_property>
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<obj_property name="ObjectShortName">EMIO_0_tri_o_0</obj_property>
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<obj_property name="Radix">HEXRADIX</obj_property>
|
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<obj_property name="LABELRADIX">true</obj_property>
|
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<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
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</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_1" type="logic">
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||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
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<obj_property name="ElementShortName">EMIO_0_tri_o_1</obj_property>
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<obj_property name="ObjectShortName">EMIO_0_tri_o_1</obj_property>
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<obj_property name="Radix">HEXRADIX</obj_property>
|
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<obj_property name="LABELRADIX">true</obj_property>
|
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<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
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</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_2" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
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<obj_property name="ElementShortName">EMIO_0_tri_o_2</obj_property>
|
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<obj_property name="ObjectShortName">EMIO_0_tri_o_2</obj_property>
|
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<obj_property name="Radix">HEXRADIX</obj_property>
|
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<obj_property name="LABELRADIX">true</obj_property>
|
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<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
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</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_3" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_3</obj_property>
|
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<obj_property name="ObjectShortName">EMIO_0_tri_o_3</obj_property>
|
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<obj_property name="Radix">HEXRADIX</obj_property>
|
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<obj_property name="LABELRADIX">true</obj_property>
|
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<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
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</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_4" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
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<obj_property name="ElementShortName">EMIO_0_tri_o_4</obj_property>
|
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<obj_property name="ObjectShortName">EMIO_0_tri_o_4</obj_property>
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<obj_property name="Radix">HEXRADIX</obj_property>
|
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<obj_property name="LABELRADIX">true</obj_property>
|
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<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
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</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_5" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
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<obj_property name="ElementShortName">EMIO_0_tri_o_5</obj_property>
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<obj_property name="ObjectShortName">EMIO_0_tri_o_5</obj_property>
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<obj_property name="Radix">HEXRADIX</obj_property>
|
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<obj_property name="LABELRADIX">true</obj_property>
|
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<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
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</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_6" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
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<obj_property name="ElementShortName">EMIO_0_tri_o_6</obj_property>
|
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<obj_property name="ObjectShortName">EMIO_0_tri_o_6</obj_property>
|
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<obj_property name="Radix">HEXRADIX</obj_property>
|
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<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_7" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_7</obj_property>
|
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<obj_property name="ObjectShortName">EMIO_0_tri_o_7</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
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<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_8" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_8</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_o_8</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
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</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_9" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_9</obj_property>
|
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<obj_property name="ObjectShortName">EMIO_0_tri_o_9</obj_property>
|
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<obj_property name="Radix">HEXRADIX</obj_property>
|
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<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
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</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_10" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_10</obj_property>
|
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<obj_property name="ObjectShortName">EMIO_0_tri_o_10</obj_property>
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<obj_property name="Radix">HEXRADIX</obj_property>
|
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<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
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</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_11" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_11</obj_property>
|
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<obj_property name="ObjectShortName">EMIO_0_tri_o_11</obj_property>
|
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<obj_property name="Radix">HEXRADIX</obj_property>
|
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<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
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</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_12" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
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<obj_property name="ElementShortName">EMIO_0_tri_o_12</obj_property>
|
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<obj_property name="ObjectShortName">EMIO_0_tri_o_12</obj_property>
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<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
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</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_13" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
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<obj_property name="ElementShortName">EMIO_0_tri_o_13</obj_property>
|
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<obj_property name="ObjectShortName">EMIO_0_tri_o_13</obj_property>
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<obj_property name="Radix">HEXRADIX</obj_property>
|
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<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_14" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_14</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_o_14</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_15" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_15</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_o_15</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_16" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_16</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_o_16</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_17" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_17</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_o_17</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_18" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_18</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_o_18</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_19" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_19</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_o_19</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_20" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_20</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_o_20</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_21" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_21</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_o_21</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_22" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_22</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_o_22</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_23" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_23</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_o_23</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_24" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_24</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_o_24</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_25" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_25</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_o_25</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_26" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_26</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_o_26</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
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|
||||
<wvobject fp_name="EMIO_0_tri_o_27" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_27</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_o_27</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
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<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
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</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_28" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_28</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_o_28</obj_property>
|
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<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
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</wvobject>
|
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<wvobject fp_name="EMIO_0_tri_o_29" type="logic">
|
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<obj_property name="DisplayName">FullPathName</obj_property>
|
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<obj_property name="ElementShortName">EMIO_0_tri_o_29</obj_property>
|
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<obj_property name="ObjectShortName">EMIO_0_tri_o_29</obj_property>
|
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<obj_property name="Radix">HEXRADIX</obj_property>
|
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<obj_property name="LABELRADIX">true</obj_property>
|
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<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_30" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_30</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_o_30</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
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<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_31" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_31</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_o_31</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
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<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_o_32" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_o_32</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_o_32</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_t_0" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_t_0</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_t_0</obj_property>
|
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<obj_property name="Radix">HEXRADIX</obj_property>
|
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<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_t_1" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_t_1</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_t_1</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_t_2" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_t_2</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_t_2</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
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<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_t_3" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
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<obj_property name="ElementShortName">EMIO_0_tri_t_3</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_t_3</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_t_4" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_t_4</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_t_4</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_t_5" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_t_5</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_t_5</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_t_6" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_t_6</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_t_6</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_t_7" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_t_7</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_t_7</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_t_8" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_t_8</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_t_8</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_t_9" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_t_9</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_t_9</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="EMIO_0_tri_t_10" type="logic">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">EMIO_0_tri_t_10</obj_property>
|
||||
<obj_property name="ObjectShortName">EMIO_0_tri_t_10</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
@@ -0,0 +1,5 @@
|
||||
1768374503
|
||||
0
|
||||
2
|
||||
0
|
||||
a8afe58f-132c-49c9-917f-ca0fff35ca74
|
||||
@@ -0,0 +1 @@
|
||||
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
|
||||
+165
@@ -0,0 +1,165 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:user:SPI_Con:1.0
|
||||
// IP Revision: 3
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module NewExtInst_TOP_SPI_Con_0_0 (
|
||||
i_miso,
|
||||
o_sclk,
|
||||
o_cs,
|
||||
o_mosi,
|
||||
s00_axi_aclk,
|
||||
s00_axi_aresetn,
|
||||
s00_axi_awaddr,
|
||||
s00_axi_awprot,
|
||||
s00_axi_awvalid,
|
||||
s00_axi_awready,
|
||||
s00_axi_wdata,
|
||||
s00_axi_wstrb,
|
||||
s00_axi_wvalid,
|
||||
s00_axi_wready,
|
||||
s00_axi_bresp,
|
||||
s00_axi_bvalid,
|
||||
s00_axi_bready,
|
||||
s00_axi_araddr,
|
||||
s00_axi_arprot,
|
||||
s00_axi_arvalid,
|
||||
s00_axi_arready,
|
||||
s00_axi_rdata,
|
||||
s00_axi_rresp,
|
||||
s00_axi_rvalid,
|
||||
s00_axi_rready
|
||||
);
|
||||
|
||||
input wire i_miso;
|
||||
output wire o_sclk;
|
||||
output wire o_cs;
|
||||
output wire o_mosi;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *)
|
||||
input wire s00_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *)
|
||||
input wire s00_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
|
||||
input wire [6 : 0] s00_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
|
||||
input wire [2 : 0] s00_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
|
||||
input wire s00_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
|
||||
output wire s00_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
|
||||
input wire [31 : 0] s00_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
|
||||
input wire [3 : 0] s00_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
|
||||
input wire s00_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
|
||||
output wire s00_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
|
||||
output wire [1 : 0] s00_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
|
||||
output wire s00_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
|
||||
input wire s00_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
|
||||
input wire [6 : 0] s00_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
|
||||
input wire [2 : 0] s00_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
|
||||
input wire s00_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
|
||||
output wire s00_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
|
||||
output wire [31 : 0] s00_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
|
||||
output wire [1 : 0] s00_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
|
||||
output wire s00_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 32, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 7, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM\
|
||||
_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
|
||||
input wire s00_axi_rready;
|
||||
|
||||
SPI_Con_v1_0 #(
|
||||
.C_S00_AXI_DATA_WIDTH(32), // Width of S_AXI data bus
|
||||
.C_S00_AXI_ADDR_WIDTH(7) // Width of S_AXI address bus
|
||||
) inst (
|
||||
.i_miso(i_miso),
|
||||
.o_sclk(o_sclk),
|
||||
.o_cs(o_cs),
|
||||
.o_mosi(o_mosi),
|
||||
.s00_axi_aclk(s00_axi_aclk),
|
||||
.s00_axi_aresetn(s00_axi_aresetn),
|
||||
.s00_axi_awaddr(s00_axi_awaddr),
|
||||
.s00_axi_awprot(s00_axi_awprot),
|
||||
.s00_axi_awvalid(s00_axi_awvalid),
|
||||
.s00_axi_awready(s00_axi_awready),
|
||||
.s00_axi_wdata(s00_axi_wdata),
|
||||
.s00_axi_wstrb(s00_axi_wstrb),
|
||||
.s00_axi_wvalid(s00_axi_wvalid),
|
||||
.s00_axi_wready(s00_axi_wready),
|
||||
.s00_axi_bresp(s00_axi_bresp),
|
||||
.s00_axi_bvalid(s00_axi_bvalid),
|
||||
.s00_axi_bready(s00_axi_bready),
|
||||
.s00_axi_araddr(s00_axi_araddr),
|
||||
.s00_axi_arprot(s00_axi_arprot),
|
||||
.s00_axi_arvalid(s00_axi_arvalid),
|
||||
.s00_axi_arready(s00_axi_arready),
|
||||
.s00_axi_rdata(s00_axi_rdata),
|
||||
.s00_axi_rresp(s00_axi_rresp),
|
||||
.s00_axi_rvalid(s00_axi_rvalid),
|
||||
.s00_axi_rready(s00_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+165
@@ -0,0 +1,165 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:user:SPI_Con:1.0
|
||||
// IP Revision: 3
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module NewExtInst_TOP_SPI_Con_0_1 (
|
||||
i_miso,
|
||||
o_sclk,
|
||||
o_cs,
|
||||
o_mosi,
|
||||
s00_axi_aclk,
|
||||
s00_axi_aresetn,
|
||||
s00_axi_awaddr,
|
||||
s00_axi_awprot,
|
||||
s00_axi_awvalid,
|
||||
s00_axi_awready,
|
||||
s00_axi_wdata,
|
||||
s00_axi_wstrb,
|
||||
s00_axi_wvalid,
|
||||
s00_axi_wready,
|
||||
s00_axi_bresp,
|
||||
s00_axi_bvalid,
|
||||
s00_axi_bready,
|
||||
s00_axi_araddr,
|
||||
s00_axi_arprot,
|
||||
s00_axi_arvalid,
|
||||
s00_axi_arready,
|
||||
s00_axi_rdata,
|
||||
s00_axi_rresp,
|
||||
s00_axi_rvalid,
|
||||
s00_axi_rready
|
||||
);
|
||||
|
||||
input wire i_miso;
|
||||
output wire o_sclk;
|
||||
output wire o_cs;
|
||||
output wire o_mosi;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *)
|
||||
input wire s00_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *)
|
||||
input wire s00_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
|
||||
input wire [6 : 0] s00_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
|
||||
input wire [2 : 0] s00_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
|
||||
input wire s00_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
|
||||
output wire s00_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
|
||||
input wire [31 : 0] s00_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
|
||||
input wire [3 : 0] s00_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
|
||||
input wire s00_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
|
||||
output wire s00_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
|
||||
output wire [1 : 0] s00_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
|
||||
output wire s00_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
|
||||
input wire s00_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
|
||||
input wire [6 : 0] s00_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
|
||||
input wire [2 : 0] s00_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
|
||||
input wire s00_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
|
||||
output wire s00_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
|
||||
output wire [31 : 0] s00_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
|
||||
output wire [1 : 0] s00_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
|
||||
output wire s00_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 32, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 7, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM\
|
||||
_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
|
||||
input wire s00_axi_rready;
|
||||
|
||||
SPI_Con_v1_0 #(
|
||||
.C_S00_AXI_DATA_WIDTH(32), // Width of S_AXI data bus
|
||||
.C_S00_AXI_ADDR_WIDTH(7) // Width of S_AXI address bus
|
||||
) inst (
|
||||
.i_miso(i_miso),
|
||||
.o_sclk(o_sclk),
|
||||
.o_cs(o_cs),
|
||||
.o_mosi(o_mosi),
|
||||
.s00_axi_aclk(s00_axi_aclk),
|
||||
.s00_axi_aresetn(s00_axi_aresetn),
|
||||
.s00_axi_awaddr(s00_axi_awaddr),
|
||||
.s00_axi_awprot(s00_axi_awprot),
|
||||
.s00_axi_awvalid(s00_axi_awvalid),
|
||||
.s00_axi_awready(s00_axi_awready),
|
||||
.s00_axi_wdata(s00_axi_wdata),
|
||||
.s00_axi_wstrb(s00_axi_wstrb),
|
||||
.s00_axi_wvalid(s00_axi_wvalid),
|
||||
.s00_axi_wready(s00_axi_wready),
|
||||
.s00_axi_bresp(s00_axi_bresp),
|
||||
.s00_axi_bvalid(s00_axi_bvalid),
|
||||
.s00_axi_bready(s00_axi_bready),
|
||||
.s00_axi_araddr(s00_axi_araddr),
|
||||
.s00_axi_arprot(s00_axi_arprot),
|
||||
.s00_axi_arvalid(s00_axi_arvalid),
|
||||
.s00_axi_arready(s00_axi_arready),
|
||||
.s00_axi_rdata(s00_axi_rdata),
|
||||
.s00_axi_rresp(s00_axi_rresp),
|
||||
.s00_axi_rvalid(s00_axi_rvalid),
|
||||
.s00_axi_rready(s00_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+165
@@ -0,0 +1,165 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:user:SPI_Con:1.0
|
||||
// IP Revision: 3
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module NewExtInst_TOP_SPI_Con_0_2 (
|
||||
i_miso,
|
||||
o_sclk,
|
||||
o_cs,
|
||||
o_mosi,
|
||||
s00_axi_aclk,
|
||||
s00_axi_aresetn,
|
||||
s00_axi_awaddr,
|
||||
s00_axi_awprot,
|
||||
s00_axi_awvalid,
|
||||
s00_axi_awready,
|
||||
s00_axi_wdata,
|
||||
s00_axi_wstrb,
|
||||
s00_axi_wvalid,
|
||||
s00_axi_wready,
|
||||
s00_axi_bresp,
|
||||
s00_axi_bvalid,
|
||||
s00_axi_bready,
|
||||
s00_axi_araddr,
|
||||
s00_axi_arprot,
|
||||
s00_axi_arvalid,
|
||||
s00_axi_arready,
|
||||
s00_axi_rdata,
|
||||
s00_axi_rresp,
|
||||
s00_axi_rvalid,
|
||||
s00_axi_rready
|
||||
);
|
||||
|
||||
input wire i_miso;
|
||||
output wire o_sclk;
|
||||
output wire o_cs;
|
||||
output wire o_mosi;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *)
|
||||
input wire s00_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *)
|
||||
input wire s00_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
|
||||
input wire [6 : 0] s00_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
|
||||
input wire [2 : 0] s00_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
|
||||
input wire s00_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
|
||||
output wire s00_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
|
||||
input wire [31 : 0] s00_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
|
||||
input wire [3 : 0] s00_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
|
||||
input wire s00_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
|
||||
output wire s00_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
|
||||
output wire [1 : 0] s00_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
|
||||
output wire s00_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
|
||||
input wire s00_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
|
||||
input wire [6 : 0] s00_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
|
||||
input wire [2 : 0] s00_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
|
||||
input wire s00_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
|
||||
output wire s00_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
|
||||
output wire [31 : 0] s00_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
|
||||
output wire [1 : 0] s00_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
|
||||
output wire s00_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 32, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 7, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM\
|
||||
_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
|
||||
input wire s00_axi_rready;
|
||||
|
||||
SPI_Con_v1_0 #(
|
||||
.C_S00_AXI_DATA_WIDTH(32), // Width of S_AXI data bus
|
||||
.C_S00_AXI_ADDR_WIDTH(7) // Width of S_AXI address bus
|
||||
) inst (
|
||||
.i_miso(i_miso),
|
||||
.o_sclk(o_sclk),
|
||||
.o_cs(o_cs),
|
||||
.o_mosi(o_mosi),
|
||||
.s00_axi_aclk(s00_axi_aclk),
|
||||
.s00_axi_aresetn(s00_axi_aresetn),
|
||||
.s00_axi_awaddr(s00_axi_awaddr),
|
||||
.s00_axi_awprot(s00_axi_awprot),
|
||||
.s00_axi_awvalid(s00_axi_awvalid),
|
||||
.s00_axi_awready(s00_axi_awready),
|
||||
.s00_axi_wdata(s00_axi_wdata),
|
||||
.s00_axi_wstrb(s00_axi_wstrb),
|
||||
.s00_axi_wvalid(s00_axi_wvalid),
|
||||
.s00_axi_wready(s00_axi_wready),
|
||||
.s00_axi_bresp(s00_axi_bresp),
|
||||
.s00_axi_bvalid(s00_axi_bvalid),
|
||||
.s00_axi_bready(s00_axi_bready),
|
||||
.s00_axi_araddr(s00_axi_araddr),
|
||||
.s00_axi_arprot(s00_axi_arprot),
|
||||
.s00_axi_arvalid(s00_axi_arvalid),
|
||||
.s00_axi_arready(s00_axi_arready),
|
||||
.s00_axi_rdata(s00_axi_rdata),
|
||||
.s00_axi_rresp(s00_axi_rresp),
|
||||
.s00_axi_rvalid(s00_axi_rvalid),
|
||||
.s00_axi_rready(s00_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+12770
File diff suppressed because it is too large
Load Diff
+14896
File diff suppressed because it is too large
Load Diff
+354
@@ -0,0 +1,354 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
|
||||
// IP Revision: 29
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module NewExtInst_TOP_auto_pc_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awprot,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_araddr,
|
||||
m_axi_arprot,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [11 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [3 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [1 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
|
||||
input wire [11 : 0] s_axi_wid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [11 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [11 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [3 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [1 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [11 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, \
|
||||
RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4\
|
||||
, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
axi_protocol_converter_v2_1_29_axi_protocol_converter #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_M_AXI_PROTOCOL(2),
|
||||
.C_S_AXI_PROTOCOL(1),
|
||||
.C_IGNORE_ID(0),
|
||||
.C_AXI_ID_WIDTH(12),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(32),
|
||||
.C_AXI_SUPPORTS_WRITE(1),
|
||||
.C_AXI_SUPPORTS_READ(1),
|
||||
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_TRANSLATION_MODE(2)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(4'H0),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(s_axi_wid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(4'H0),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(12'H000),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(1'H0),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(12'H000),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1'H0),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+89
@@ -0,0 +1,89 @@
|
||||
|
||||
// file: NewExtInst_TOP_clk_wiz_0_0.v
|
||||
// (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1__100.00000______0.000______50.0______226.965____237.727
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary__________25.000____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "NewExtInst_TOP_clk_wiz_0_0,clk_wiz_v6_0_13_0_0,{component_name=NewExtInst_TOP_clk_wiz_0_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=40.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
|
||||
|
||||
module NewExtInst_TOP_clk_wiz_0_0
|
||||
(
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
// Status and control signals
|
||||
input reset,
|
||||
output locked,
|
||||
// Clock in ports
|
||||
input clk_in1
|
||||
);
|
||||
|
||||
NewExtInst_TOP_clk_wiz_0_0_clk_wiz inst
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(clk_out1),
|
||||
// Status and control signals
|
||||
.reset(reset),
|
||||
.locked(locked),
|
||||
// Clock in ports
|
||||
.clk_in1(clk_in1)
|
||||
);
|
||||
|
||||
endmodule
|
||||
+201
@@ -0,0 +1,201 @@
|
||||
|
||||
// file: NewExtInst_TOP_clk_wiz_0_0.v
|
||||
// (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1__100.00000______0.000______50.0______226.965____237.727
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary__________25.000____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module NewExtInst_TOP_clk_wiz_0_0_clk_wiz
|
||||
|
||||
(// Clock in ports
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
// Status and control signals
|
||||
input reset,
|
||||
output locked,
|
||||
input clk_in1
|
||||
);
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
wire clk_in1_NewExtInst_TOP_clk_wiz_0_0;
|
||||
wire clk_in2_NewExtInst_TOP_clk_wiz_0_0;
|
||||
IBUF clkin1_ibufg
|
||||
(.O (clk_in1_NewExtInst_TOP_clk_wiz_0_0),
|
||||
.I (clk_in1));
|
||||
|
||||
|
||||
|
||||
|
||||
// Clocking PRIMITIVE
|
||||
//------------------------------------
|
||||
|
||||
// Instantiation of the MMCM PRIMITIVE
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
|
||||
wire clk_out1_NewExtInst_TOP_clk_wiz_0_0;
|
||||
wire clk_out2_NewExtInst_TOP_clk_wiz_0_0;
|
||||
wire clk_out3_NewExtInst_TOP_clk_wiz_0_0;
|
||||
wire clk_out4_NewExtInst_TOP_clk_wiz_0_0;
|
||||
wire clk_out5_NewExtInst_TOP_clk_wiz_0_0;
|
||||
wire clk_out6_NewExtInst_TOP_clk_wiz_0_0;
|
||||
wire clk_out7_NewExtInst_TOP_clk_wiz_0_0;
|
||||
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire psdone_unused;
|
||||
wire locked_int;
|
||||
wire clkfbout_NewExtInst_TOP_clk_wiz_0_0;
|
||||
wire clkfbout_buf_NewExtInst_TOP_clk_wiz_0_0;
|
||||
wire clkfboutb_unused;
|
||||
wire clkout0b_unused;
|
||||
wire clkout1_unused;
|
||||
wire clkout1b_unused;
|
||||
wire clkout2_unused;
|
||||
wire clkout2b_unused;
|
||||
wire clkout3_unused;
|
||||
wire clkout3b_unused;
|
||||
wire clkout4_unused;
|
||||
wire clkout5_unused;
|
||||
wire clkout6_unused;
|
||||
wire clkfbstopped_unused;
|
||||
wire clkinstopped_unused;
|
||||
wire reset_high;
|
||||
|
||||
MMCME2_ADV
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.CLKOUT4_CASCADE ("FALSE"),
|
||||
.COMPENSATION ("ZHOLD"),
|
||||
.STARTUP_WAIT ("FALSE"),
|
||||
.DIVCLK_DIVIDE (1),
|
||||
.CLKFBOUT_MULT_F (40.000),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKFBOUT_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT0_DIVIDE_F (10.000),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKOUT0_USE_FINE_PS ("FALSE"),
|
||||
.CLKIN1_PERIOD (40.000))
|
||||
mmcm_adv_inst
|
||||
// Output clocks
|
||||
(
|
||||
.CLKFBOUT (clkfbout_NewExtInst_TOP_clk_wiz_0_0),
|
||||
.CLKFBOUTB (clkfboutb_unused),
|
||||
.CLKOUT0 (clk_out1_NewExtInst_TOP_clk_wiz_0_0),
|
||||
.CLKOUT0B (clkout0b_unused),
|
||||
.CLKOUT1 (clkout1_unused),
|
||||
.CLKOUT1B (clkout1b_unused),
|
||||
.CLKOUT2 (clkout2_unused),
|
||||
.CLKOUT2B (clkout2b_unused),
|
||||
.CLKOUT3 (clkout3_unused),
|
||||
.CLKOUT3B (clkout3b_unused),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
.CLKOUT5 (clkout5_unused),
|
||||
.CLKOUT6 (clkout6_unused),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout_buf_NewExtInst_TOP_clk_wiz_0_0),
|
||||
.CLKIN1 (clk_in1_NewExtInst_TOP_clk_wiz_0_0),
|
||||
.CLKIN2 (1'b0),
|
||||
// Tied to always select the primary input clock
|
||||
.CLKINSEL (1'b1),
|
||||
// Ports for dynamic reconfiguration
|
||||
.DADDR (7'h0),
|
||||
.DCLK (1'b0),
|
||||
.DEN (1'b0),
|
||||
.DI (16'h0),
|
||||
.DO (do_unused),
|
||||
.DRDY (drdy_unused),
|
||||
.DWE (1'b0),
|
||||
// Ports for dynamic phase shift
|
||||
.PSCLK (1'b0),
|
||||
.PSEN (1'b0),
|
||||
.PSINCDEC (1'b0),
|
||||
.PSDONE (psdone_unused),
|
||||
// Other control and status signals
|
||||
.LOCKED (locked_int),
|
||||
.CLKINSTOPPED (clkinstopped_unused),
|
||||
.CLKFBSTOPPED (clkfbstopped_unused),
|
||||
.PWRDWN (1'b0),
|
||||
.RST (reset_high));
|
||||
assign reset_high = reset;
|
||||
|
||||
assign locked = locked_int;
|
||||
// Clock Monitor clock assigning
|
||||
//--------------------------------------
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
|
||||
BUFG clkf_buf
|
||||
(.O (clkfbout_buf_NewExtInst_TOP_clk_wiz_0_0),
|
||||
.I (clkfbout_NewExtInst_TOP_clk_wiz_0_0));
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (clk_out1),
|
||||
.I (clk_out1_NewExtInst_TOP_clk_wiz_0_0));
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+258
@@ -0,0 +1,258 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
// Date : Fri May 15 15:26:59 2026
|
||||
// Host : mkb running 64-bit unknown
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.v
|
||||
// Design : NewExtInst_TOP_clk_wiz_0_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7z035ffg676-2
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* NotValidForBitStream *)
|
||||
module NewExtInst_TOP_clk_wiz_0_0
|
||||
(clk_out1,
|
||||
reset,
|
||||
locked,
|
||||
clk_in1);
|
||||
output clk_out1;
|
||||
input reset;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
|
||||
(* IBUF_LOW_PWR *) wire clk_in1;
|
||||
wire clk_out1;
|
||||
wire locked;
|
||||
wire reset;
|
||||
|
||||
NewExtInst_TOP_clk_wiz_0_0_clk_wiz inst
|
||||
(.clk_in1(clk_in1),
|
||||
.clk_out1(clk_out1),
|
||||
.locked(locked),
|
||||
.reset(reset));
|
||||
endmodule
|
||||
|
||||
module NewExtInst_TOP_clk_wiz_0_0_clk_wiz
|
||||
(clk_out1,
|
||||
reset,
|
||||
locked,
|
||||
clk_in1);
|
||||
output clk_out1;
|
||||
input reset;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
|
||||
wire clk_in1;
|
||||
wire clk_in1_NewExtInst_TOP_clk_wiz_0_0;
|
||||
wire clk_out1;
|
||||
wire clk_out1_NewExtInst_TOP_clk_wiz_0_0;
|
||||
wire clkfbout_NewExtInst_TOP_clk_wiz_0_0;
|
||||
wire clkfbout_buf_NewExtInst_TOP_clk_wiz_0_0;
|
||||
wire locked;
|
||||
wire reset;
|
||||
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
|
||||
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
|
||||
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
|
||||
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkf_buf
|
||||
(.I(clkfbout_NewExtInst_TOP_clk_wiz_0_0),
|
||||
.O(clkfbout_buf_NewExtInst_TOP_clk_wiz_0_0));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
IBUF #(
|
||||
.IOSTANDARD("DEFAULT"))
|
||||
clkin1_ibufg
|
||||
(.I(clk_in1),
|
||||
.O(clk_in1_NewExtInst_TOP_clk_wiz_0_0));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkout1_buf
|
||||
(.I(clk_out1_NewExtInst_TOP_clk_wiz_0_0),
|
||||
.O(clk_out1));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
MMCME2_ADV #(
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
.CLKFBOUT_MULT_F(40.000000),
|
||||
.CLKFBOUT_PHASE(0.000000),
|
||||
.CLKFBOUT_USE_FINE_PS("FALSE"),
|
||||
.CLKIN1_PERIOD(40.000000),
|
||||
.CLKIN2_PERIOD(0.000000),
|
||||
.CLKOUT0_DIVIDE_F(10.000000),
|
||||
.CLKOUT0_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT0_PHASE(0.000000),
|
||||
.CLKOUT0_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT1_PHASE(0.000000),
|
||||
.CLKOUT1_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT2_PHASE(0.000000),
|
||||
.CLKOUT2_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT3_PHASE(0.000000),
|
||||
.CLKOUT3_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT4_PHASE(0.000000),
|
||||
.CLKOUT4_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT5_PHASE(0.000000),
|
||||
.CLKOUT5_USE_FINE_PS("FALSE"),
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT6_PHASE(0.000000),
|
||||
.CLKOUT6_USE_FINE_PS("FALSE"),
|
||||
.COMPENSATION("ZHOLD"),
|
||||
.DIVCLK_DIVIDE(1),
|
||||
.IS_CLKINSEL_INVERTED(1'b0),
|
||||
.IS_PSEN_INVERTED(1'b0),
|
||||
.IS_PSINCDEC_INVERTED(1'b0),
|
||||
.IS_PWRDWN_INVERTED(1'b0),
|
||||
.IS_RST_INVERTED(1'b0),
|
||||
.REF_JITTER1(0.010000),
|
||||
.REF_JITTER2(0.010000),
|
||||
.SS_EN("FALSE"),
|
||||
.SS_MODE("CENTER_HIGH"),
|
||||
.SS_MOD_PERIOD(10000),
|
||||
.STARTUP_WAIT("FALSE"))
|
||||
mmcm_adv_inst
|
||||
(.CLKFBIN(clkfbout_buf_NewExtInst_TOP_clk_wiz_0_0),
|
||||
.CLKFBOUT(clkfbout_NewExtInst_TOP_clk_wiz_0_0),
|
||||
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
|
||||
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
|
||||
.CLKIN1(clk_in1_NewExtInst_TOP_clk_wiz_0_0),
|
||||
.CLKIN2(1'b0),
|
||||
.CLKINSEL(1'b1),
|
||||
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
|
||||
.CLKOUT0(clk_out1_NewExtInst_TOP_clk_wiz_0_0),
|
||||
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
|
||||
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
|
||||
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
|
||||
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
|
||||
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
|
||||
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
|
||||
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
|
||||
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
|
||||
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
|
||||
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
|
||||
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DCLK(1'b0),
|
||||
.DEN(1'b0),
|
||||
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
|
||||
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
|
||||
.DWE(1'b0),
|
||||
.LOCKED(locked),
|
||||
.PSCLK(1'b0),
|
||||
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
|
||||
.PSEN(1'b0),
|
||||
.PSINCDEC(1'b0),
|
||||
.PWRDWN(1'b0),
|
||||
.RST(reset));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+189
@@ -0,0 +1,189 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
-- Date : Fri May 15 15:26:59 2026
|
||||
-- Host : mkb running 64-bit unknown
|
||||
-- Command : write_vhdl -force -mode funcsim
|
||||
-- /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.vhdl
|
||||
-- Design : NewExtInst_TOP_clk_wiz_0_0
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7z035ffg676-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity NewExtInst_TOP_clk_wiz_0_0_clk_wiz is
|
||||
port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
reset : in STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1 : in STD_LOGIC
|
||||
);
|
||||
end NewExtInst_TOP_clk_wiz_0_0_clk_wiz;
|
||||
|
||||
architecture STRUCTURE of NewExtInst_TOP_clk_wiz_0_0_clk_wiz is
|
||||
signal clk_in1_NewExtInst_TOP_clk_wiz_0_0 : STD_LOGIC;
|
||||
signal clk_out1_NewExtInst_TOP_clk_wiz_0_0 : STD_LOGIC;
|
||||
signal clkfbout_NewExtInst_TOP_clk_wiz_0_0 : STD_LOGIC;
|
||||
signal clkfbout_buf_NewExtInst_TOP_clk_wiz_0_0 : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
attribute BOX_TYPE : string;
|
||||
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE : string;
|
||||
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
|
||||
attribute IBUF_DELAY_VALUE : string;
|
||||
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
|
||||
attribute IFD_DELAY_VALUE : string;
|
||||
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
|
||||
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
|
||||
begin
|
||||
clkf_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clkfbout_NewExtInst_TOP_clk_wiz_0_0,
|
||||
O => clkfbout_buf_NewExtInst_TOP_clk_wiz_0_0
|
||||
);
|
||||
clkin1_ibufg: unisim.vcomponents.IBUF
|
||||
generic map(
|
||||
IOSTANDARD => "DEFAULT"
|
||||
)
|
||||
port map (
|
||||
I => clk_in1,
|
||||
O => clk_in1_NewExtInst_TOP_clk_wiz_0_0
|
||||
);
|
||||
clkout1_buf: unisim.vcomponents.BUFG
|
||||
port map (
|
||||
I => clk_out1_NewExtInst_TOP_clk_wiz_0_0,
|
||||
O => clk_out1
|
||||
);
|
||||
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
|
||||
generic map(
|
||||
BANDWIDTH => "OPTIMIZED",
|
||||
CLKFBOUT_MULT_F => 40.000000,
|
||||
CLKFBOUT_PHASE => 0.000000,
|
||||
CLKFBOUT_USE_FINE_PS => false,
|
||||
CLKIN1_PERIOD => 40.000000,
|
||||
CLKIN2_PERIOD => 0.000000,
|
||||
CLKOUT0_DIVIDE_F => 10.000000,
|
||||
CLKOUT0_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT0_PHASE => 0.000000,
|
||||
CLKOUT0_USE_FINE_PS => false,
|
||||
CLKOUT1_DIVIDE => 1,
|
||||
CLKOUT1_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT1_PHASE => 0.000000,
|
||||
CLKOUT1_USE_FINE_PS => false,
|
||||
CLKOUT2_DIVIDE => 1,
|
||||
CLKOUT2_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT2_PHASE => 0.000000,
|
||||
CLKOUT2_USE_FINE_PS => false,
|
||||
CLKOUT3_DIVIDE => 1,
|
||||
CLKOUT3_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT3_PHASE => 0.000000,
|
||||
CLKOUT3_USE_FINE_PS => false,
|
||||
CLKOUT4_CASCADE => false,
|
||||
CLKOUT4_DIVIDE => 1,
|
||||
CLKOUT4_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT4_PHASE => 0.000000,
|
||||
CLKOUT4_USE_FINE_PS => false,
|
||||
CLKOUT5_DIVIDE => 1,
|
||||
CLKOUT5_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT5_PHASE => 0.000000,
|
||||
CLKOUT5_USE_FINE_PS => false,
|
||||
CLKOUT6_DIVIDE => 1,
|
||||
CLKOUT6_DUTY_CYCLE => 0.500000,
|
||||
CLKOUT6_PHASE => 0.000000,
|
||||
CLKOUT6_USE_FINE_PS => false,
|
||||
COMPENSATION => "ZHOLD",
|
||||
DIVCLK_DIVIDE => 1,
|
||||
IS_CLKINSEL_INVERTED => '0',
|
||||
IS_PSEN_INVERTED => '0',
|
||||
IS_PSINCDEC_INVERTED => '0',
|
||||
IS_PWRDWN_INVERTED => '0',
|
||||
IS_RST_INVERTED => '0',
|
||||
REF_JITTER1 => 0.010000,
|
||||
REF_JITTER2 => 0.010000,
|
||||
SS_EN => "FALSE",
|
||||
SS_MODE => "CENTER_HIGH",
|
||||
SS_MOD_PERIOD => 10000,
|
||||
STARTUP_WAIT => false
|
||||
)
|
||||
port map (
|
||||
CLKFBIN => clkfbout_buf_NewExtInst_TOP_clk_wiz_0_0,
|
||||
CLKFBOUT => clkfbout_NewExtInst_TOP_clk_wiz_0_0,
|
||||
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
|
||||
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
|
||||
CLKIN1 => clk_in1_NewExtInst_TOP_clk_wiz_0_0,
|
||||
CLKIN2 => '0',
|
||||
CLKINSEL => '1',
|
||||
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
|
||||
CLKOUT0 => clk_out1_NewExtInst_TOP_clk_wiz_0_0,
|
||||
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
|
||||
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
|
||||
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
|
||||
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
|
||||
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
|
||||
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
|
||||
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
|
||||
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
|
||||
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
|
||||
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
|
||||
DADDR(6 downto 0) => B"0000000",
|
||||
DCLK => '0',
|
||||
DEN => '0',
|
||||
DI(15 downto 0) => B"0000000000000000",
|
||||
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
|
||||
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
|
||||
DWE => '0',
|
||||
LOCKED => locked,
|
||||
PSCLK => '0',
|
||||
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
|
||||
PSEN => '0',
|
||||
PSINCDEC => '0',
|
||||
PWRDWN => '0',
|
||||
RST => reset
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity NewExtInst_TOP_clk_wiz_0_0 is
|
||||
port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
reset : in STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1 : in STD_LOGIC
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of NewExtInst_TOP_clk_wiz_0_0 : entity is true;
|
||||
end NewExtInst_TOP_clk_wiz_0_0;
|
||||
|
||||
architecture STRUCTURE of NewExtInst_TOP_clk_wiz_0_0 is
|
||||
begin
|
||||
inst: entity work.NewExtInst_TOP_clk_wiz_0_0_clk_wiz
|
||||
port map (
|
||||
clk_in1 => clk_in1,
|
||||
clk_out1 => clk_out1,
|
||||
locked => locked,
|
||||
reset => reset
|
||||
);
|
||||
end STRUCTURE;
|
||||
+985
@@ -0,0 +1,985 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
// Date : Fri May 15 15:26:59 2026
|
||||
// Host : mkb running 64-bit unknown
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.v
|
||||
// Design : NewExtInst_TOP_proc_sys_reset_0_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7z035ffg676-2
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "NewExtInst_TOP_proc_sys_reset_0_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2023.2" *)
|
||||
(* NotValidForBitStream *)
|
||||
module NewExtInst_TOP_proc_sys_reset_0_0
|
||||
(slowest_sync_clk,
|
||||
ext_reset_in,
|
||||
aux_reset_in,
|
||||
mb_debug_sys_rst,
|
||||
dcm_locked,
|
||||
mb_reset,
|
||||
bus_struct_reset,
|
||||
peripheral_reset,
|
||||
interconnect_aresetn,
|
||||
peripheral_aresetn);
|
||||
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 25000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN NewExtInst_TOP_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input slowest_sync_clk;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input ext_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aux_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) output mb_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]bus_struct_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]interconnect_aresetn;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_aresetn;
|
||||
|
||||
wire aux_reset_in;
|
||||
wire [0:0]bus_struct_reset;
|
||||
wire dcm_locked;
|
||||
wire ext_reset_in;
|
||||
wire [0:0]interconnect_aresetn;
|
||||
wire mb_debug_sys_rst;
|
||||
wire mb_reset;
|
||||
wire [0:0]peripheral_aresetn;
|
||||
wire [0:0]peripheral_reset;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* C_AUX_RESET_HIGH = "1'b0" *)
|
||||
(* C_AUX_RST_WIDTH = "4" *)
|
||||
(* C_EXT_RESET_HIGH = "1'b0" *)
|
||||
(* C_EXT_RST_WIDTH = "4" *)
|
||||
(* C_FAMILY = "zynq" *)
|
||||
(* C_NUM_BUS_RST = "1" *)
|
||||
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
|
||||
(* C_NUM_PERP_ARESETN = "1" *)
|
||||
(* C_NUM_PERP_RST = "1" *)
|
||||
NewExtInst_TOP_proc_sys_reset_0_0_proc_sys_reset U0
|
||||
(.aux_reset_in(aux_reset_in),
|
||||
.bus_struct_reset(bus_struct_reset),
|
||||
.dcm_locked(dcm_locked),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.interconnect_aresetn(interconnect_aresetn),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.mb_reset(mb_reset),
|
||||
.peripheral_aresetn(peripheral_aresetn),
|
||||
.peripheral_reset(peripheral_reset),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "cdc_sync" *)
|
||||
module NewExtInst_TOP_proc_sys_reset_0_0_cdc_sync
|
||||
(lpf_asr_reg,
|
||||
scndry_out,
|
||||
lpf_asr,
|
||||
p_1_in,
|
||||
p_2_in,
|
||||
asr_lpf,
|
||||
aux_reset_in,
|
||||
slowest_sync_clk);
|
||||
output lpf_asr_reg;
|
||||
output scndry_out;
|
||||
input lpf_asr;
|
||||
input p_1_in;
|
||||
input p_2_in;
|
||||
input [0:0]asr_lpf;
|
||||
input aux_reset_in;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
|
||||
wire Q;
|
||||
wire asr_d1;
|
||||
wire [0:0]asr_lpf;
|
||||
wire aux_reset_in;
|
||||
wire lpf_asr;
|
||||
wire lpf_asr_reg;
|
||||
wire p_1_in;
|
||||
wire p_2_in;
|
||||
wire scndry_out;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(asr_d1),
|
||||
.Q(Q),
|
||||
.R(1'b0));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
|
||||
(.I0(aux_reset_in),
|
||||
.O(asr_d1));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Q),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.Q(scndry_out),
|
||||
.R(1'b0));
|
||||
LUT5 #(
|
||||
.INIT(32'hEAAAAAA8))
|
||||
lpf_asr_i_1
|
||||
(.I0(lpf_asr),
|
||||
.I1(p_1_in),
|
||||
.I2(p_2_in),
|
||||
.I3(scndry_out),
|
||||
.I4(asr_lpf),
|
||||
.O(lpf_asr_reg));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "cdc_sync" *)
|
||||
module NewExtInst_TOP_proc_sys_reset_0_0_cdc_sync_0
|
||||
(lpf_exr_reg,
|
||||
scndry_out,
|
||||
lpf_exr,
|
||||
p_1_in4_in,
|
||||
p_2_in3_in,
|
||||
exr_lpf,
|
||||
mb_debug_sys_rst,
|
||||
ext_reset_in,
|
||||
slowest_sync_clk);
|
||||
output lpf_exr_reg;
|
||||
output scndry_out;
|
||||
input lpf_exr;
|
||||
input p_1_in4_in;
|
||||
input p_2_in3_in;
|
||||
input [0:0]exr_lpf;
|
||||
input mb_debug_sys_rst;
|
||||
input ext_reset_in;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
|
||||
wire Q;
|
||||
wire exr_d1;
|
||||
wire [0:0]exr_lpf;
|
||||
wire ext_reset_in;
|
||||
wire lpf_exr;
|
||||
wire lpf_exr_reg;
|
||||
wire mb_debug_sys_rst;
|
||||
wire p_1_in4_in;
|
||||
wire p_2_in3_in;
|
||||
wire scndry_out;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(exr_d1),
|
||||
.Q(Q),
|
||||
.R(1'b0));
|
||||
LUT2 #(
|
||||
.INIT(4'hB))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
|
||||
(.I0(mb_debug_sys_rst),
|
||||
.I1(ext_reset_in),
|
||||
.O(exr_d1));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Q),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.Q(scndry_out),
|
||||
.R(1'b0));
|
||||
LUT5 #(
|
||||
.INIT(32'hEAAAAAA8))
|
||||
lpf_exr_i_1
|
||||
(.I0(lpf_exr),
|
||||
.I1(p_1_in4_in),
|
||||
.I2(p_2_in3_in),
|
||||
.I3(scndry_out),
|
||||
.I4(exr_lpf),
|
||||
.O(lpf_exr_reg));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "lpf" *)
|
||||
module NewExtInst_TOP_proc_sys_reset_0_0_lpf
|
||||
(lpf_int,
|
||||
slowest_sync_clk,
|
||||
dcm_locked,
|
||||
mb_debug_sys_rst,
|
||||
ext_reset_in,
|
||||
aux_reset_in);
|
||||
output lpf_int;
|
||||
input slowest_sync_clk;
|
||||
input dcm_locked;
|
||||
input mb_debug_sys_rst;
|
||||
input ext_reset_in;
|
||||
input aux_reset_in;
|
||||
|
||||
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
|
||||
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
|
||||
wire Q;
|
||||
wire [0:0]asr_lpf;
|
||||
wire aux_reset_in;
|
||||
wire dcm_locked;
|
||||
wire [0:0]exr_lpf;
|
||||
wire ext_reset_in;
|
||||
wire lpf_asr;
|
||||
wire lpf_exr;
|
||||
wire lpf_int;
|
||||
wire lpf_int0__0;
|
||||
wire mb_debug_sys_rst;
|
||||
wire p_1_in;
|
||||
wire p_1_in4_in;
|
||||
wire p_2_in;
|
||||
wire p_2_in3_in;
|
||||
wire p_3_in1_in;
|
||||
wire p_3_in6_in;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
NewExtInst_TOP_proc_sys_reset_0_0_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX
|
||||
(.asr_lpf(asr_lpf),
|
||||
.aux_reset_in(aux_reset_in),
|
||||
.lpf_asr(lpf_asr),
|
||||
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
|
||||
.p_1_in(p_1_in),
|
||||
.p_2_in(p_2_in),
|
||||
.scndry_out(p_3_in1_in),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
NewExtInst_TOP_proc_sys_reset_0_0_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT
|
||||
(.exr_lpf(exr_lpf),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.lpf_exr(lpf_exr),
|
||||
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.p_1_in4_in(p_1_in4_in),
|
||||
.p_2_in3_in(p_2_in3_in),
|
||||
.scndry_out(p_3_in6_in),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[1].asr_lpf_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_in1_in),
|
||||
.Q(p_2_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[2].asr_lpf_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_2_in),
|
||||
.Q(p_1_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[3].asr_lpf_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_1_in),
|
||||
.Q(asr_lpf),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[1].exr_lpf_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_in6_in),
|
||||
.Q(p_2_in3_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[2].exr_lpf_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_2_in3_in),
|
||||
.Q(p_1_in4_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[3].exr_lpf_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_1_in4_in),
|
||||
.Q(exr_lpf),
|
||||
.R(1'b0));
|
||||
(* XILINX_LEGACY_PRIM = "SRL16" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
(* srl_name = "U0/\\EXT_LPF/POR_SRL_I " *)
|
||||
SRL16E #(
|
||||
.INIT(16'hFFFF))
|
||||
POR_SRL_I
|
||||
(.A0(1'b1),
|
||||
.A1(1'b1),
|
||||
.A2(1'b1),
|
||||
.A3(1'b1),
|
||||
.CE(1'b1),
|
||||
.CLK(slowest_sync_clk),
|
||||
.D(1'b0),
|
||||
.Q(Q));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_asr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
|
||||
.Q(lpf_asr),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_exr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
|
||||
.Q(lpf_exr),
|
||||
.R(1'b0));
|
||||
LUT4 #(
|
||||
.INIT(16'hFFFD))
|
||||
lpf_int0
|
||||
(.I0(dcm_locked),
|
||||
.I1(lpf_exr),
|
||||
.I2(lpf_asr),
|
||||
.I3(Q),
|
||||
.O(lpf_int0__0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_int_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(lpf_int0__0),
|
||||
.Q(lpf_int),
|
||||
.R(1'b0));
|
||||
endmodule
|
||||
|
||||
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
|
||||
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
|
||||
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
|
||||
(* ORIG_REF_NAME = "proc_sys_reset" *)
|
||||
module NewExtInst_TOP_proc_sys_reset_0_0_proc_sys_reset
|
||||
(slowest_sync_clk,
|
||||
ext_reset_in,
|
||||
aux_reset_in,
|
||||
mb_debug_sys_rst,
|
||||
dcm_locked,
|
||||
mb_reset,
|
||||
bus_struct_reset,
|
||||
peripheral_reset,
|
||||
interconnect_aresetn,
|
||||
peripheral_aresetn);
|
||||
input slowest_sync_clk;
|
||||
input ext_reset_in;
|
||||
input aux_reset_in;
|
||||
input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
output mb_reset;
|
||||
output [0:0]bus_struct_reset;
|
||||
output [0:0]peripheral_reset;
|
||||
output [0:0]interconnect_aresetn;
|
||||
output [0:0]peripheral_aresetn;
|
||||
|
||||
wire Bsr_out;
|
||||
wire MB_out;
|
||||
wire Pr_out;
|
||||
wire SEQ_n_3;
|
||||
wire SEQ_n_4;
|
||||
wire aux_reset_in;
|
||||
wire [0:0]bus_struct_reset;
|
||||
wire dcm_locked;
|
||||
wire ext_reset_in;
|
||||
wire [0:0]interconnect_aresetn;
|
||||
wire lpf_int;
|
||||
wire mb_debug_sys_rst;
|
||||
wire mb_reset;
|
||||
wire [0:0]peripheral_aresetn;
|
||||
wire [0:0]peripheral_reset;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(SEQ_n_3),
|
||||
.Q(interconnect_aresetn),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(SEQ_n_4),
|
||||
.Q(peripheral_aresetn),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\BSR_OUT_DFF[0].FDRE_BSR
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Bsr_out),
|
||||
.Q(bus_struct_reset),
|
||||
.R(1'b0));
|
||||
NewExtInst_TOP_proc_sys_reset_0_0_lpf EXT_LPF
|
||||
(.aux_reset_in(aux_reset_in),
|
||||
.dcm_locked(dcm_locked),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.lpf_int(lpf_int),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
FDRE_inst
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(MB_out),
|
||||
.Q(mb_reset),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\PR_OUT_DFF[0].FDRE_PER
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Pr_out),
|
||||
.Q(peripheral_reset),
|
||||
.R(1'b0));
|
||||
NewExtInst_TOP_proc_sys_reset_0_0_sequence_psr SEQ
|
||||
(.Bsr_out(Bsr_out),
|
||||
.MB_out(MB_out),
|
||||
.Pr_out(Pr_out),
|
||||
.bsr_reg_0(SEQ_n_3),
|
||||
.lpf_int(lpf_int),
|
||||
.pr_reg_0(SEQ_n_4),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "sequence_psr" *)
|
||||
module NewExtInst_TOP_proc_sys_reset_0_0_sequence_psr
|
||||
(MB_out,
|
||||
Bsr_out,
|
||||
Pr_out,
|
||||
bsr_reg_0,
|
||||
pr_reg_0,
|
||||
lpf_int,
|
||||
slowest_sync_clk);
|
||||
output MB_out;
|
||||
output Bsr_out;
|
||||
output Pr_out;
|
||||
output bsr_reg_0;
|
||||
output pr_reg_0;
|
||||
input lpf_int;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire Bsr_out;
|
||||
wire Core_i_1_n_0;
|
||||
wire MB_out;
|
||||
wire Pr_out;
|
||||
wire \bsr_dec_reg_n_0_[0] ;
|
||||
wire \bsr_dec_reg_n_0_[2] ;
|
||||
wire bsr_i_1_n_0;
|
||||
wire bsr_reg_0;
|
||||
wire \core_dec[0]_i_1_n_0 ;
|
||||
wire \core_dec[2]_i_1_n_0 ;
|
||||
wire \core_dec_reg_n_0_[0] ;
|
||||
wire \core_dec_reg_n_0_[1] ;
|
||||
wire from_sys_i_1_n_0;
|
||||
wire lpf_int;
|
||||
wire p_0_in;
|
||||
wire [2:0]p_3_out;
|
||||
wire [2:0]p_5_out;
|
||||
wire pr_dec0__0;
|
||||
wire \pr_dec_reg_n_0_[0] ;
|
||||
wire \pr_dec_reg_n_0_[2] ;
|
||||
wire pr_i_1_n_0;
|
||||
wire pr_reg_0;
|
||||
wire seq_clr;
|
||||
wire [5:0]seq_cnt;
|
||||
wire seq_cnt_en;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1
|
||||
(.I0(Bsr_out),
|
||||
.O(bsr_reg_0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair5" *)
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1
|
||||
(.I0(Pr_out),
|
||||
.O(pr_reg_0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
Core_i_1
|
||||
(.I0(MB_out),
|
||||
.I1(p_0_in),
|
||||
.O(Core_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
Core_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Core_i_1_n_0),
|
||||
.Q(MB_out),
|
||||
.S(lpf_int));
|
||||
NewExtInst_TOP_proc_sys_reset_0_0_upcnt_n SEQ_COUNTER
|
||||
(.Q(seq_cnt),
|
||||
.seq_clr(seq_clr),
|
||||
.seq_cnt_en(seq_cnt_en),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h0090))
|
||||
\bsr_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[4]),
|
||||
.I2(seq_cnt[3]),
|
||||
.I3(seq_cnt[5]),
|
||||
.O(p_5_out[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair6" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\bsr_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\bsr_dec_reg_n_0_[0] ),
|
||||
.O(p_5_out[2]));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\bsr_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_5_out[0]),
|
||||
.Q(\bsr_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\bsr_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_5_out[2]),
|
||||
.Q(\bsr_dec_reg_n_0_[2] ),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
bsr_i_1
|
||||
(.I0(Bsr_out),
|
||||
.I1(\bsr_dec_reg_n_0_[2] ),
|
||||
.O(bsr_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
bsr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(bsr_i_1_n_0),
|
||||
.Q(Bsr_out),
|
||||
.S(lpf_int));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h9000))
|
||||
\core_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[4]),
|
||||
.I2(seq_cnt[3]),
|
||||
.I3(seq_cnt[5]),
|
||||
.O(\core_dec[0]_i_1_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair6" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\core_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\core_dec_reg_n_0_[0] ),
|
||||
.O(\core_dec[2]_i_1_n_0 ));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\core_dec[0]_i_1_n_0 ),
|
||||
.Q(\core_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(pr_dec0__0),
|
||||
.Q(\core_dec_reg_n_0_[1] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\core_dec[2]_i_1_n_0 ),
|
||||
.Q(p_0_in),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
from_sys_i_1
|
||||
(.I0(MB_out),
|
||||
.I1(seq_cnt_en),
|
||||
.O(from_sys_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b0))
|
||||
from_sys_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(from_sys_i_1_n_0),
|
||||
.Q(seq_cnt_en),
|
||||
.S(lpf_int));
|
||||
LUT4 #(
|
||||
.INIT(16'h0018))
|
||||
pr_dec0
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[0]),
|
||||
.I2(seq_cnt[2]),
|
||||
.I3(seq_cnt[1]),
|
||||
.O(pr_dec0__0));
|
||||
LUT4 #(
|
||||
.INIT(16'h0480))
|
||||
\pr_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[3]),
|
||||
.I2(seq_cnt[5]),
|
||||
.I3(seq_cnt[4]),
|
||||
.O(p_3_out[0]));
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\pr_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\pr_dec_reg_n_0_[0] ),
|
||||
.O(p_3_out[2]));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\pr_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_out[0]),
|
||||
.Q(\pr_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\pr_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_out[2]),
|
||||
.Q(\pr_dec_reg_n_0_[2] ),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair5" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
pr_i_1
|
||||
(.I0(Pr_out),
|
||||
.I1(\pr_dec_reg_n_0_[2] ),
|
||||
.O(pr_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
pr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(pr_i_1_n_0),
|
||||
.Q(Pr_out),
|
||||
.S(lpf_int));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
seq_clr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(1'b1),
|
||||
.Q(seq_clr),
|
||||
.R(lpf_int));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "upcnt_n" *)
|
||||
module NewExtInst_TOP_proc_sys_reset_0_0_upcnt_n
|
||||
(Q,
|
||||
seq_clr,
|
||||
seq_cnt_en,
|
||||
slowest_sync_clk);
|
||||
output [5:0]Q;
|
||||
input seq_clr;
|
||||
input seq_cnt_en;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire [5:0]Q;
|
||||
wire clear;
|
||||
wire [5:0]q_int0;
|
||||
wire seq_clr;
|
||||
wire seq_cnt_en;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\q_int[0]_i_1
|
||||
(.I0(Q[0]),
|
||||
.O(q_int0[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\q_int[1]_i_1
|
||||
(.I0(Q[0]),
|
||||
.I1(Q[1]),
|
||||
.O(q_int0[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT3 #(
|
||||
.INIT(8'h78))
|
||||
\q_int[2]_i_1
|
||||
(.I0(Q[0]),
|
||||
.I1(Q[1]),
|
||||
.I2(Q[2]),
|
||||
.O(q_int0[2]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h7F80))
|
||||
\q_int[3]_i_1
|
||||
(.I0(Q[1]),
|
||||
.I1(Q[0]),
|
||||
.I2(Q[2]),
|
||||
.I3(Q[3]),
|
||||
.O(q_int0[3]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT5 #(
|
||||
.INIT(32'h7FFF8000))
|
||||
\q_int[4]_i_1
|
||||
(.I0(Q[2]),
|
||||
.I1(Q[0]),
|
||||
.I2(Q[1]),
|
||||
.I3(Q[3]),
|
||||
.I4(Q[4]),
|
||||
.O(q_int0[4]));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\q_int[5]_i_1
|
||||
(.I0(seq_clr),
|
||||
.O(clear));
|
||||
LUT6 #(
|
||||
.INIT(64'h7FFFFFFF80000000))
|
||||
\q_int[5]_i_2
|
||||
(.I0(Q[3]),
|
||||
.I1(Q[1]),
|
||||
.I2(Q[0]),
|
||||
.I3(Q[2]),
|
||||
.I4(Q[4]),
|
||||
.I5(Q[5]),
|
||||
.O(q_int0[5]));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[0]),
|
||||
.Q(Q[0]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[1]),
|
||||
.Q(Q[1]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[2]),
|
||||
.Q(Q[2]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[3]),
|
||||
.Q(Q[3]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[4]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[4]),
|
||||
.Q(Q[4]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[5]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[5]),
|
||||
.Q(Q[5]),
|
||||
.R(clear));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+1135
File diff suppressed because it is too large
Load Diff
+147
@@ -0,0 +1,147 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
|
||||
-- IP Revision: 14
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY proc_sys_reset_v5_0_14;
|
||||
USE proc_sys_reset_v5_0_14.proc_sys_reset;
|
||||
|
||||
ENTITY NewExtInst_TOP_proc_sys_reset_0_0 IS
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END NewExtInst_TOP_proc_sys_reset_0_0;
|
||||
|
||||
ARCHITECTURE NewExtInst_TOP_proc_sys_reset_0_0_arch OF NewExtInst_TOP_proc_sys_reset_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF NewExtInst_TOP_proc_sys_reset_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT proc_sys_reset IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_EXT_RST_WIDTH : INTEGER;
|
||||
C_AUX_RST_WIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : STD_LOGIC;
|
||||
C_AUX_RESET_HIGH : STD_LOGIC;
|
||||
C_NUM_BUS_RST : INTEGER;
|
||||
C_NUM_PERP_RST : INTEGER;
|
||||
C_NUM_INTERCONNECT_ARESETN : INTEGER;
|
||||
C_NUM_PERP_ARESETN : INTEGER
|
||||
);
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 25000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN NewExtInst_TOP_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_EXT_RST_WIDTH => 4,
|
||||
C_AUX_RST_WIDTH => 4,
|
||||
C_EXT_RESET_HIGH => '0',
|
||||
C_AUX_RESET_HIGH => '0',
|
||||
C_NUM_BUS_RST => 1,
|
||||
C_NUM_PERP_RST => 1,
|
||||
C_NUM_INTERCONNECT_ARESETN => 1,
|
||||
C_NUM_PERP_ARESETN => 1
|
||||
)
|
||||
PORT MAP (
|
||||
slowest_sync_clk => slowest_sync_clk,
|
||||
ext_reset_in => ext_reset_in,
|
||||
aux_reset_in => aux_reset_in,
|
||||
mb_debug_sys_rst => mb_debug_sys_rst,
|
||||
dcm_locked => dcm_locked,
|
||||
mb_reset => mb_reset,
|
||||
bus_struct_reset => bus_struct_reset,
|
||||
peripheral_reset => peripheral_reset,
|
||||
interconnect_aresetn => interconnect_aresetn,
|
||||
peripheral_aresetn => peripheral_aresetn
|
||||
);
|
||||
END NewExtInst_TOP_proc_sys_reset_0_0_arch;
|
||||
+6425
File diff suppressed because it is too large
Load Diff
+6952
File diff suppressed because it is too large
Load Diff
+584
@@ -0,0 +1,584 @@
|
||||
|
||||
|
||||
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module NewExtInst_TOP_processing_system7_0_0 (
|
||||
M_AXI_GP0_ARVALID,
|
||||
M_AXI_GP0_AWVALID,
|
||||
M_AXI_GP0_BREADY,
|
||||
M_AXI_GP0_RREADY,
|
||||
M_AXI_GP0_WLAST,
|
||||
M_AXI_GP0_WVALID,
|
||||
M_AXI_GP0_ARID,
|
||||
M_AXI_GP0_AWID,
|
||||
M_AXI_GP0_WID,
|
||||
M_AXI_GP0_ARBURST,
|
||||
M_AXI_GP0_ARLOCK,
|
||||
M_AXI_GP0_ARSIZE,
|
||||
M_AXI_GP0_AWBURST,
|
||||
M_AXI_GP0_AWLOCK,
|
||||
M_AXI_GP0_AWSIZE,
|
||||
M_AXI_GP0_ARPROT,
|
||||
M_AXI_GP0_AWPROT,
|
||||
M_AXI_GP0_ARADDR,
|
||||
M_AXI_GP0_AWADDR,
|
||||
M_AXI_GP0_WDATA,
|
||||
M_AXI_GP0_ARCACHE,
|
||||
M_AXI_GP0_ARLEN,
|
||||
M_AXI_GP0_ARQOS,
|
||||
M_AXI_GP0_AWCACHE,
|
||||
M_AXI_GP0_AWLEN,
|
||||
M_AXI_GP0_AWQOS,
|
||||
M_AXI_GP0_WSTRB,
|
||||
M_AXI_GP0_ACLK,
|
||||
M_AXI_GP0_ARREADY,
|
||||
M_AXI_GP0_AWREADY,
|
||||
M_AXI_GP0_BVALID,
|
||||
M_AXI_GP0_RLAST,
|
||||
M_AXI_GP0_RVALID,
|
||||
M_AXI_GP0_WREADY,
|
||||
M_AXI_GP0_BID,
|
||||
M_AXI_GP0_RID,
|
||||
M_AXI_GP0_BRESP,
|
||||
M_AXI_GP0_RRESP,
|
||||
M_AXI_GP0_RDATA,
|
||||
FCLK_CLK0,
|
||||
FCLK_CLK1,
|
||||
FCLK_CLK2,
|
||||
FCLK_CLK3,
|
||||
FCLK_RESET0_N,
|
||||
MIO,
|
||||
DDR_CAS_n,
|
||||
DDR_CKE,
|
||||
DDR_Clk_n,
|
||||
DDR_Clk,
|
||||
DDR_CS_n,
|
||||
DDR_DRSTB,
|
||||
DDR_ODT,
|
||||
DDR_RAS_n,
|
||||
DDR_WEB,
|
||||
DDR_BankAddr,
|
||||
DDR_Addr,
|
||||
DDR_VRN,
|
||||
DDR_VRP,
|
||||
DDR_DM,
|
||||
DDR_DQ,
|
||||
DDR_DQS_n,
|
||||
DDR_DQS,
|
||||
PS_SRSTB,
|
||||
PS_CLK,
|
||||
PS_PORB
|
||||
);
|
||||
output M_AXI_GP0_ARVALID;
|
||||
output M_AXI_GP0_AWVALID;
|
||||
output M_AXI_GP0_BREADY;
|
||||
output M_AXI_GP0_RREADY;
|
||||
output M_AXI_GP0_WLAST;
|
||||
output M_AXI_GP0_WVALID;
|
||||
output [11 : 0] M_AXI_GP0_ARID;
|
||||
output [11 : 0] M_AXI_GP0_AWID;
|
||||
output [11 : 0] M_AXI_GP0_WID;
|
||||
output [1 : 0] M_AXI_GP0_ARBURST;
|
||||
output [1 : 0] M_AXI_GP0_ARLOCK;
|
||||
output [2 : 0] M_AXI_GP0_ARSIZE;
|
||||
output [1 : 0] M_AXI_GP0_AWBURST;
|
||||
output [1 : 0] M_AXI_GP0_AWLOCK;
|
||||
output [2 : 0] M_AXI_GP0_AWSIZE;
|
||||
output [2 : 0] M_AXI_GP0_ARPROT;
|
||||
output [2 : 0] M_AXI_GP0_AWPROT;
|
||||
output [31 : 0] M_AXI_GP0_ARADDR;
|
||||
output [31 : 0] M_AXI_GP0_AWADDR;
|
||||
output [31 : 0] M_AXI_GP0_WDATA;
|
||||
output [3 : 0] M_AXI_GP0_ARCACHE;
|
||||
output [3 : 0] M_AXI_GP0_ARLEN;
|
||||
output [3 : 0] M_AXI_GP0_ARQOS;
|
||||
output [3 : 0] M_AXI_GP0_AWCACHE;
|
||||
output [3 : 0] M_AXI_GP0_AWLEN;
|
||||
output [3 : 0] M_AXI_GP0_AWQOS;
|
||||
output [3 : 0] M_AXI_GP0_WSTRB;
|
||||
input M_AXI_GP0_ACLK;
|
||||
input M_AXI_GP0_ARREADY;
|
||||
input M_AXI_GP0_AWREADY;
|
||||
input M_AXI_GP0_BVALID;
|
||||
input M_AXI_GP0_RLAST;
|
||||
input M_AXI_GP0_RVALID;
|
||||
input M_AXI_GP0_WREADY;
|
||||
input [11 : 0] M_AXI_GP0_BID;
|
||||
input [11 : 0] M_AXI_GP0_RID;
|
||||
input [1 : 0] M_AXI_GP0_BRESP;
|
||||
input [1 : 0] M_AXI_GP0_RRESP;
|
||||
input [31 : 0] M_AXI_GP0_RDATA;
|
||||
output FCLK_CLK0;
|
||||
output FCLK_CLK1;
|
||||
output FCLK_CLK2;
|
||||
output FCLK_CLK3;
|
||||
output FCLK_RESET0_N;
|
||||
input [53 : 0] MIO;
|
||||
input DDR_CAS_n;
|
||||
input DDR_CKE;
|
||||
input DDR_Clk_n;
|
||||
input DDR_Clk;
|
||||
input DDR_CS_n;
|
||||
input DDR_DRSTB;
|
||||
input DDR_ODT;
|
||||
input DDR_RAS_n;
|
||||
input DDR_WEB;
|
||||
input [2 : 0] DDR_BankAddr;
|
||||
input [14 : 0] DDR_Addr;
|
||||
input DDR_VRN;
|
||||
input DDR_VRP;
|
||||
input [3 : 0] DDR_DM;
|
||||
input [31 : 0] DDR_DQ;
|
||||
input [3 : 0] DDR_DQS_n;
|
||||
input [3 : 0] DDR_DQS;
|
||||
input PS_SRSTB;
|
||||
input PS_CLK;
|
||||
input PS_PORB;
|
||||
|
||||
processing_system7_vip_v1_0_17 #(
|
||||
.C_USE_M_AXI_GP0(1),
|
||||
.C_USE_M_AXI_GP1(0),
|
||||
.C_USE_S_AXI_ACP(0),
|
||||
.C_USE_S_AXI_GP0(0),
|
||||
.C_USE_S_AXI_GP1(0),
|
||||
.C_USE_S_AXI_HP0(0),
|
||||
.C_USE_S_AXI_HP1(0),
|
||||
.C_USE_S_AXI_HP2(0),
|
||||
.C_USE_S_AXI_HP3(0),
|
||||
.C_S_AXI_HP0_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP1_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP2_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP3_DATA_WIDTH(64),
|
||||
.C_HIGH_OCM_EN(0),
|
||||
.C_FCLK_CLK0_FREQ(25.0),
|
||||
.C_FCLK_CLK1_FREQ(50.0),
|
||||
.C_FCLK_CLK2_FREQ(100.0),
|
||||
.C_FCLK_CLK3_FREQ(200.0),
|
||||
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
|
||||
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
|
||||
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
|
||||
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
|
||||
) inst (
|
||||
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
|
||||
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
|
||||
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
|
||||
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
|
||||
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
|
||||
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
|
||||
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
|
||||
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
|
||||
.M_AXI_GP0_WID(M_AXI_GP0_WID),
|
||||
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
|
||||
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
|
||||
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
|
||||
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
|
||||
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
|
||||
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
|
||||
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
|
||||
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
|
||||
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
|
||||
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
|
||||
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
|
||||
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
|
||||
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
|
||||
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
|
||||
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
|
||||
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
|
||||
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
|
||||
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
|
||||
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
|
||||
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
|
||||
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
|
||||
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
|
||||
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
|
||||
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
|
||||
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
|
||||
.M_AXI_GP0_BID(M_AXI_GP0_BID),
|
||||
.M_AXI_GP0_RID(M_AXI_GP0_RID),
|
||||
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
|
||||
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
|
||||
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
|
||||
.M_AXI_GP1_ARVALID(),
|
||||
.M_AXI_GP1_AWVALID(),
|
||||
.M_AXI_GP1_BREADY(),
|
||||
.M_AXI_GP1_RREADY(),
|
||||
.M_AXI_GP1_WLAST(),
|
||||
.M_AXI_GP1_WVALID(),
|
||||
.M_AXI_GP1_ARID(),
|
||||
.M_AXI_GP1_AWID(),
|
||||
.M_AXI_GP1_WID(),
|
||||
.M_AXI_GP1_ARBURST(),
|
||||
.M_AXI_GP1_ARLOCK(),
|
||||
.M_AXI_GP1_ARSIZE(),
|
||||
.M_AXI_GP1_AWBURST(),
|
||||
.M_AXI_GP1_AWLOCK(),
|
||||
.M_AXI_GP1_AWSIZE(),
|
||||
.M_AXI_GP1_ARPROT(),
|
||||
.M_AXI_GP1_AWPROT(),
|
||||
.M_AXI_GP1_ARADDR(),
|
||||
.M_AXI_GP1_AWADDR(),
|
||||
.M_AXI_GP1_WDATA(),
|
||||
.M_AXI_GP1_ARCACHE(),
|
||||
.M_AXI_GP1_ARLEN(),
|
||||
.M_AXI_GP1_ARQOS(),
|
||||
.M_AXI_GP1_AWCACHE(),
|
||||
.M_AXI_GP1_AWLEN(),
|
||||
.M_AXI_GP1_AWQOS(),
|
||||
.M_AXI_GP1_WSTRB(),
|
||||
.M_AXI_GP1_ACLK(1'B0),
|
||||
.M_AXI_GP1_ARREADY(1'B0),
|
||||
.M_AXI_GP1_AWREADY(1'B0),
|
||||
.M_AXI_GP1_BVALID(1'B0),
|
||||
.M_AXI_GP1_RLAST(1'B0),
|
||||
.M_AXI_GP1_RVALID(1'B0),
|
||||
.M_AXI_GP1_WREADY(1'B0),
|
||||
.M_AXI_GP1_BID(12'B0),
|
||||
.M_AXI_GP1_RID(12'B0),
|
||||
.M_AXI_GP1_BRESP(2'B0),
|
||||
.M_AXI_GP1_RRESP(2'B0),
|
||||
.M_AXI_GP1_RDATA(32'B0),
|
||||
.S_AXI_GP0_ARREADY(),
|
||||
.S_AXI_GP0_AWREADY(),
|
||||
.S_AXI_GP0_BVALID(),
|
||||
.S_AXI_GP0_RLAST(),
|
||||
.S_AXI_GP0_RVALID(),
|
||||
.S_AXI_GP0_WREADY(),
|
||||
.S_AXI_GP0_BRESP(),
|
||||
.S_AXI_GP0_RRESP(),
|
||||
.S_AXI_GP0_RDATA(),
|
||||
.S_AXI_GP0_BID(),
|
||||
.S_AXI_GP0_RID(),
|
||||
.S_AXI_GP0_ACLK(1'B0),
|
||||
.S_AXI_GP0_ARVALID(1'B0),
|
||||
.S_AXI_GP0_AWVALID(1'B0),
|
||||
.S_AXI_GP0_BREADY(1'B0),
|
||||
.S_AXI_GP0_RREADY(1'B0),
|
||||
.S_AXI_GP0_WLAST(1'B0),
|
||||
.S_AXI_GP0_WVALID(1'B0),
|
||||
.S_AXI_GP0_ARBURST(2'B0),
|
||||
.S_AXI_GP0_ARLOCK(2'B0),
|
||||
.S_AXI_GP0_ARSIZE(3'B0),
|
||||
.S_AXI_GP0_AWBURST(2'B0),
|
||||
.S_AXI_GP0_AWLOCK(2'B0),
|
||||
.S_AXI_GP0_AWSIZE(3'B0),
|
||||
.S_AXI_GP0_ARPROT(3'B0),
|
||||
.S_AXI_GP0_AWPROT(3'B0),
|
||||
.S_AXI_GP0_ARADDR(32'B0),
|
||||
.S_AXI_GP0_AWADDR(32'B0),
|
||||
.S_AXI_GP0_WDATA(32'B0),
|
||||
.S_AXI_GP0_ARCACHE(4'B0),
|
||||
.S_AXI_GP0_ARLEN(4'B0),
|
||||
.S_AXI_GP0_ARQOS(4'B0),
|
||||
.S_AXI_GP0_AWCACHE(4'B0),
|
||||
.S_AXI_GP0_AWLEN(4'B0),
|
||||
.S_AXI_GP0_AWQOS(4'B0),
|
||||
.S_AXI_GP0_WSTRB(4'B0),
|
||||
.S_AXI_GP0_ARID(6'B0),
|
||||
.S_AXI_GP0_AWID(6'B0),
|
||||
.S_AXI_GP0_WID(6'B0),
|
||||
.S_AXI_GP1_ARREADY(),
|
||||
.S_AXI_GP1_AWREADY(),
|
||||
.S_AXI_GP1_BVALID(),
|
||||
.S_AXI_GP1_RLAST(),
|
||||
.S_AXI_GP1_RVALID(),
|
||||
.S_AXI_GP1_WREADY(),
|
||||
.S_AXI_GP1_BRESP(),
|
||||
.S_AXI_GP1_RRESP(),
|
||||
.S_AXI_GP1_RDATA(),
|
||||
.S_AXI_GP1_BID(),
|
||||
.S_AXI_GP1_RID(),
|
||||
.S_AXI_GP1_ACLK(1'B0),
|
||||
.S_AXI_GP1_ARVALID(1'B0),
|
||||
.S_AXI_GP1_AWVALID(1'B0),
|
||||
.S_AXI_GP1_BREADY(1'B0),
|
||||
.S_AXI_GP1_RREADY(1'B0),
|
||||
.S_AXI_GP1_WLAST(1'B0),
|
||||
.S_AXI_GP1_WVALID(1'B0),
|
||||
.S_AXI_GP1_ARBURST(2'B0),
|
||||
.S_AXI_GP1_ARLOCK(2'B0),
|
||||
.S_AXI_GP1_ARSIZE(3'B0),
|
||||
.S_AXI_GP1_AWBURST(2'B0),
|
||||
.S_AXI_GP1_AWLOCK(2'B0),
|
||||
.S_AXI_GP1_AWSIZE(3'B0),
|
||||
.S_AXI_GP1_ARPROT(3'B0),
|
||||
.S_AXI_GP1_AWPROT(3'B0),
|
||||
.S_AXI_GP1_ARADDR(32'B0),
|
||||
.S_AXI_GP1_AWADDR(32'B0),
|
||||
.S_AXI_GP1_WDATA(32'B0),
|
||||
.S_AXI_GP1_ARCACHE(4'B0),
|
||||
.S_AXI_GP1_ARLEN(4'B0),
|
||||
.S_AXI_GP1_ARQOS(4'B0),
|
||||
.S_AXI_GP1_AWCACHE(4'B0),
|
||||
.S_AXI_GP1_AWLEN(4'B0),
|
||||
.S_AXI_GP1_AWQOS(4'B0),
|
||||
.S_AXI_GP1_WSTRB(4'B0),
|
||||
.S_AXI_GP1_ARID(6'B0),
|
||||
.S_AXI_GP1_AWID(6'B0),
|
||||
.S_AXI_GP1_WID(6'B0),
|
||||
.S_AXI_ACP_ARREADY(),
|
||||
.S_AXI_ACP_AWREADY(),
|
||||
.S_AXI_ACP_BVALID(),
|
||||
.S_AXI_ACP_RLAST(),
|
||||
.S_AXI_ACP_RVALID(),
|
||||
.S_AXI_ACP_WREADY(),
|
||||
.S_AXI_ACP_BRESP(),
|
||||
.S_AXI_ACP_RRESP(),
|
||||
.S_AXI_ACP_BID(),
|
||||
.S_AXI_ACP_RID(),
|
||||
.S_AXI_ACP_RDATA(),
|
||||
.S_AXI_ACP_ACLK(1'B0),
|
||||
.S_AXI_ACP_ARVALID(1'B0),
|
||||
.S_AXI_ACP_AWVALID(1'B0),
|
||||
.S_AXI_ACP_BREADY(1'B0),
|
||||
.S_AXI_ACP_RREADY(1'B0),
|
||||
.S_AXI_ACP_WLAST(1'B0),
|
||||
.S_AXI_ACP_WVALID(1'B0),
|
||||
.S_AXI_ACP_ARID(3'B0),
|
||||
.S_AXI_ACP_ARPROT(3'B0),
|
||||
.S_AXI_ACP_AWID(3'B0),
|
||||
.S_AXI_ACP_AWPROT(3'B0),
|
||||
.S_AXI_ACP_WID(3'B0),
|
||||
.S_AXI_ACP_ARADDR(32'B0),
|
||||
.S_AXI_ACP_AWADDR(32'B0),
|
||||
.S_AXI_ACP_ARCACHE(4'B0),
|
||||
.S_AXI_ACP_ARLEN(4'B0),
|
||||
.S_AXI_ACP_ARQOS(4'B0),
|
||||
.S_AXI_ACP_AWCACHE(4'B0),
|
||||
.S_AXI_ACP_AWLEN(4'B0),
|
||||
.S_AXI_ACP_AWQOS(4'B0),
|
||||
.S_AXI_ACP_ARBURST(2'B0),
|
||||
.S_AXI_ACP_ARLOCK(2'B0),
|
||||
.S_AXI_ACP_ARSIZE(3'B0),
|
||||
.S_AXI_ACP_AWBURST(2'B0),
|
||||
.S_AXI_ACP_AWLOCK(2'B0),
|
||||
.S_AXI_ACP_AWSIZE(3'B0),
|
||||
.S_AXI_ACP_ARUSER(5'B0),
|
||||
.S_AXI_ACP_AWUSER(5'B0),
|
||||
.S_AXI_ACP_WDATA(64'B0),
|
||||
.S_AXI_ACP_WSTRB(8'B0),
|
||||
.S_AXI_HP0_ARREADY(),
|
||||
.S_AXI_HP0_AWREADY(),
|
||||
.S_AXI_HP0_BVALID(),
|
||||
.S_AXI_HP0_RLAST(),
|
||||
.S_AXI_HP0_RVALID(),
|
||||
.S_AXI_HP0_WREADY(),
|
||||
.S_AXI_HP0_BRESP(),
|
||||
.S_AXI_HP0_RRESP(),
|
||||
.S_AXI_HP0_BID(),
|
||||
.S_AXI_HP0_RID(),
|
||||
.S_AXI_HP0_RDATA(),
|
||||
.S_AXI_HP0_ACLK(1'B0),
|
||||
.S_AXI_HP0_ARVALID(1'B0),
|
||||
.S_AXI_HP0_AWVALID(1'B0),
|
||||
.S_AXI_HP0_BREADY(1'B0),
|
||||
.S_AXI_HP0_RREADY(1'B0),
|
||||
.S_AXI_HP0_WLAST(1'B0),
|
||||
.S_AXI_HP0_WVALID(1'B0),
|
||||
.S_AXI_HP0_ARBURST(2'B0),
|
||||
.S_AXI_HP0_ARLOCK(2'B0),
|
||||
.S_AXI_HP0_ARSIZE(3'B0),
|
||||
.S_AXI_HP0_AWBURST(2'B0),
|
||||
.S_AXI_HP0_AWLOCK(2'B0),
|
||||
.S_AXI_HP0_AWSIZE(3'B0),
|
||||
.S_AXI_HP0_ARPROT(3'B0),
|
||||
.S_AXI_HP0_AWPROT(3'B0),
|
||||
.S_AXI_HP0_ARADDR(32'B0),
|
||||
.S_AXI_HP0_AWADDR(32'B0),
|
||||
.S_AXI_HP0_ARCACHE(4'B0),
|
||||
.S_AXI_HP0_ARLEN(4'B0),
|
||||
.S_AXI_HP0_ARQOS(4'B0),
|
||||
.S_AXI_HP0_AWCACHE(4'B0),
|
||||
.S_AXI_HP0_AWLEN(4'B0),
|
||||
.S_AXI_HP0_AWQOS(4'B0),
|
||||
.S_AXI_HP0_ARID(6'B0),
|
||||
.S_AXI_HP0_AWID(6'B0),
|
||||
.S_AXI_HP0_WID(6'B0),
|
||||
.S_AXI_HP0_WDATA(64'B0),
|
||||
.S_AXI_HP0_WSTRB(8'B0),
|
||||
.S_AXI_HP1_ARREADY(),
|
||||
.S_AXI_HP1_AWREADY(),
|
||||
.S_AXI_HP1_BVALID(),
|
||||
.S_AXI_HP1_RLAST(),
|
||||
.S_AXI_HP1_RVALID(),
|
||||
.S_AXI_HP1_WREADY(),
|
||||
.S_AXI_HP1_BRESP(),
|
||||
.S_AXI_HP1_RRESP(),
|
||||
.S_AXI_HP1_BID(),
|
||||
.S_AXI_HP1_RID(),
|
||||
.S_AXI_HP1_RDATA(),
|
||||
.S_AXI_HP1_ACLK(1'B0),
|
||||
.S_AXI_HP1_ARVALID(1'B0),
|
||||
.S_AXI_HP1_AWVALID(1'B0),
|
||||
.S_AXI_HP1_BREADY(1'B0),
|
||||
.S_AXI_HP1_RREADY(1'B0),
|
||||
.S_AXI_HP1_WLAST(1'B0),
|
||||
.S_AXI_HP1_WVALID(1'B0),
|
||||
.S_AXI_HP1_ARBURST(2'B0),
|
||||
.S_AXI_HP1_ARLOCK(2'B0),
|
||||
.S_AXI_HP1_ARSIZE(3'B0),
|
||||
.S_AXI_HP1_AWBURST(2'B0),
|
||||
.S_AXI_HP1_AWLOCK(2'B0),
|
||||
.S_AXI_HP1_AWSIZE(3'B0),
|
||||
.S_AXI_HP1_ARPROT(3'B0),
|
||||
.S_AXI_HP1_AWPROT(3'B0),
|
||||
.S_AXI_HP1_ARADDR(32'B0),
|
||||
.S_AXI_HP1_AWADDR(32'B0),
|
||||
.S_AXI_HP1_ARCACHE(4'B0),
|
||||
.S_AXI_HP1_ARLEN(4'B0),
|
||||
.S_AXI_HP1_ARQOS(4'B0),
|
||||
.S_AXI_HP1_AWCACHE(4'B0),
|
||||
.S_AXI_HP1_AWLEN(4'B0),
|
||||
.S_AXI_HP1_AWQOS(4'B0),
|
||||
.S_AXI_HP1_ARID(6'B0),
|
||||
.S_AXI_HP1_AWID(6'B0),
|
||||
.S_AXI_HP1_WID(6'B0),
|
||||
.S_AXI_HP1_WDATA(64'B0),
|
||||
.S_AXI_HP1_WSTRB(8'B0),
|
||||
.S_AXI_HP2_ARREADY(),
|
||||
.S_AXI_HP2_AWREADY(),
|
||||
.S_AXI_HP2_BVALID(),
|
||||
.S_AXI_HP2_RLAST(),
|
||||
.S_AXI_HP2_RVALID(),
|
||||
.S_AXI_HP2_WREADY(),
|
||||
.S_AXI_HP2_BRESP(),
|
||||
.S_AXI_HP2_RRESP(),
|
||||
.S_AXI_HP2_BID(),
|
||||
.S_AXI_HP2_RID(),
|
||||
.S_AXI_HP2_RDATA(),
|
||||
.S_AXI_HP2_ACLK(1'B0),
|
||||
.S_AXI_HP2_ARVALID(1'B0),
|
||||
.S_AXI_HP2_AWVALID(1'B0),
|
||||
.S_AXI_HP2_BREADY(1'B0),
|
||||
.S_AXI_HP2_RREADY(1'B0),
|
||||
.S_AXI_HP2_WLAST(1'B0),
|
||||
.S_AXI_HP2_WVALID(1'B0),
|
||||
.S_AXI_HP2_ARBURST(2'B0),
|
||||
.S_AXI_HP2_ARLOCK(2'B0),
|
||||
.S_AXI_HP2_ARSIZE(3'B0),
|
||||
.S_AXI_HP2_AWBURST(2'B0),
|
||||
.S_AXI_HP2_AWLOCK(2'B0),
|
||||
.S_AXI_HP2_AWSIZE(3'B0),
|
||||
.S_AXI_HP2_ARPROT(3'B0),
|
||||
.S_AXI_HP2_AWPROT(3'B0),
|
||||
.S_AXI_HP2_ARADDR(32'B0),
|
||||
.S_AXI_HP2_AWADDR(32'B0),
|
||||
.S_AXI_HP2_ARCACHE(4'B0),
|
||||
.S_AXI_HP2_ARLEN(4'B0),
|
||||
.S_AXI_HP2_ARQOS(4'B0),
|
||||
.S_AXI_HP2_AWCACHE(4'B0),
|
||||
.S_AXI_HP2_AWLEN(4'B0),
|
||||
.S_AXI_HP2_AWQOS(4'B0),
|
||||
.S_AXI_HP2_ARID(6'B0),
|
||||
.S_AXI_HP2_AWID(6'B0),
|
||||
.S_AXI_HP2_WID(6'B0),
|
||||
.S_AXI_HP2_WDATA(64'B0),
|
||||
.S_AXI_HP2_WSTRB(8'B0),
|
||||
.S_AXI_HP3_ARREADY(),
|
||||
.S_AXI_HP3_AWREADY(),
|
||||
.S_AXI_HP3_BVALID(),
|
||||
.S_AXI_HP3_RLAST(),
|
||||
.S_AXI_HP3_RVALID(),
|
||||
.S_AXI_HP3_WREADY(),
|
||||
.S_AXI_HP3_BRESP(),
|
||||
.S_AXI_HP3_RRESP(),
|
||||
.S_AXI_HP3_BID(),
|
||||
.S_AXI_HP3_RID(),
|
||||
.S_AXI_HP3_RDATA(),
|
||||
.S_AXI_HP3_ACLK(1'B0),
|
||||
.S_AXI_HP3_ARVALID(1'B0),
|
||||
.S_AXI_HP3_AWVALID(1'B0),
|
||||
.S_AXI_HP3_BREADY(1'B0),
|
||||
.S_AXI_HP3_RREADY(1'B0),
|
||||
.S_AXI_HP3_WLAST(1'B0),
|
||||
.S_AXI_HP3_WVALID(1'B0),
|
||||
.S_AXI_HP3_ARBURST(2'B0),
|
||||
.S_AXI_HP3_ARLOCK(2'B0),
|
||||
.S_AXI_HP3_ARSIZE(3'B0),
|
||||
.S_AXI_HP3_AWBURST(2'B0),
|
||||
.S_AXI_HP3_AWLOCK(2'B0),
|
||||
.S_AXI_HP3_AWSIZE(3'B0),
|
||||
.S_AXI_HP3_ARPROT(3'B0),
|
||||
.S_AXI_HP3_AWPROT(3'B0),
|
||||
.S_AXI_HP3_ARADDR(32'B0),
|
||||
.S_AXI_HP3_AWADDR(32'B0),
|
||||
.S_AXI_HP3_ARCACHE(4'B0),
|
||||
.S_AXI_HP3_ARLEN(4'B0),
|
||||
.S_AXI_HP3_ARQOS(4'B0),
|
||||
.S_AXI_HP3_AWCACHE(4'B0),
|
||||
.S_AXI_HP3_AWLEN(4'B0),
|
||||
.S_AXI_HP3_AWQOS(4'B0),
|
||||
.S_AXI_HP3_ARID(6'B0),
|
||||
.S_AXI_HP3_AWID(6'B0),
|
||||
.S_AXI_HP3_WID(6'B0),
|
||||
.S_AXI_HP3_WDATA(64'B0),
|
||||
.S_AXI_HP3_WSTRB(8'B0),
|
||||
.FCLK_CLK0(FCLK_CLK0),
|
||||
|
||||
.FCLK_CLK1(FCLK_CLK1),
|
||||
|
||||
.FCLK_CLK2(FCLK_CLK2),
|
||||
|
||||
.FCLK_CLK3(FCLK_CLK3),
|
||||
.FCLK_RESET0_N(FCLK_RESET0_N),
|
||||
.FCLK_RESET1_N(),
|
||||
.FCLK_RESET2_N(),
|
||||
.FCLK_RESET3_N(),
|
||||
.IRQ_F2P(IRQ_F2P),
|
||||
.PS_SRSTB(PS_SRSTB),
|
||||
.PS_CLK(PS_CLK),
|
||||
.PS_PORB(PS_PORB)
|
||||
);
|
||||
endmodule
|
||||
+985
@@ -0,0 +1,985 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
// Date : Fri May 15 15:26:59 2026
|
||||
// Host : mkb running 64-bit unknown
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.v
|
||||
// Design : NewExtInst_TOP_rst_clk_wiz_0_100M_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7z035ffg676-2
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "NewExtInst_TOP_rst_clk_wiz_0_100M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2023.2" *)
|
||||
(* NotValidForBitStream *)
|
||||
module NewExtInst_TOP_rst_clk_wiz_0_100M_0
|
||||
(slowest_sync_clk,
|
||||
ext_reset_in,
|
||||
aux_reset_in,
|
||||
mb_debug_sys_rst,
|
||||
dcm_locked,
|
||||
mb_reset,
|
||||
bus_struct_reset,
|
||||
peripheral_reset,
|
||||
interconnect_aresetn,
|
||||
peripheral_aresetn);
|
||||
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *) input slowest_sync_clk;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input ext_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aux_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) output mb_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]bus_struct_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]interconnect_aresetn;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_aresetn;
|
||||
|
||||
wire aux_reset_in;
|
||||
wire [0:0]bus_struct_reset;
|
||||
wire dcm_locked;
|
||||
wire ext_reset_in;
|
||||
wire [0:0]interconnect_aresetn;
|
||||
wire mb_debug_sys_rst;
|
||||
wire mb_reset;
|
||||
wire [0:0]peripheral_aresetn;
|
||||
wire [0:0]peripheral_reset;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* C_AUX_RESET_HIGH = "1'b0" *)
|
||||
(* C_AUX_RST_WIDTH = "4" *)
|
||||
(* C_EXT_RESET_HIGH = "1'b1" *)
|
||||
(* C_EXT_RST_WIDTH = "4" *)
|
||||
(* C_FAMILY = "zynq" *)
|
||||
(* C_NUM_BUS_RST = "1" *)
|
||||
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
|
||||
(* C_NUM_PERP_ARESETN = "1" *)
|
||||
(* C_NUM_PERP_RST = "1" *)
|
||||
NewExtInst_TOP_rst_clk_wiz_0_100M_0_proc_sys_reset U0
|
||||
(.aux_reset_in(aux_reset_in),
|
||||
.bus_struct_reset(bus_struct_reset),
|
||||
.dcm_locked(dcm_locked),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.interconnect_aresetn(interconnect_aresetn),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.mb_reset(mb_reset),
|
||||
.peripheral_aresetn(peripheral_aresetn),
|
||||
.peripheral_reset(peripheral_reset),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "cdc_sync" *)
|
||||
module NewExtInst_TOP_rst_clk_wiz_0_100M_0_cdc_sync
|
||||
(lpf_exr_reg,
|
||||
scndry_out,
|
||||
lpf_exr,
|
||||
p_1_in4_in,
|
||||
p_2_in3_in,
|
||||
exr_lpf,
|
||||
ext_reset_in,
|
||||
mb_debug_sys_rst,
|
||||
slowest_sync_clk);
|
||||
output lpf_exr_reg;
|
||||
output scndry_out;
|
||||
input lpf_exr;
|
||||
input p_1_in4_in;
|
||||
input p_2_in3_in;
|
||||
input [0:0]exr_lpf;
|
||||
input ext_reset_in;
|
||||
input mb_debug_sys_rst;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
|
||||
wire Q;
|
||||
wire exr_d1;
|
||||
wire [0:0]exr_lpf;
|
||||
wire ext_reset_in;
|
||||
wire lpf_exr;
|
||||
wire lpf_exr_reg;
|
||||
wire mb_debug_sys_rst;
|
||||
wire p_1_in4_in;
|
||||
wire p_2_in3_in;
|
||||
wire scndry_out;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(exr_d1),
|
||||
.Q(Q),
|
||||
.R(1'b0));
|
||||
LUT2 #(
|
||||
.INIT(4'hE))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
|
||||
(.I0(ext_reset_in),
|
||||
.I1(mb_debug_sys_rst),
|
||||
.O(exr_d1));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Q),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.Q(scndry_out),
|
||||
.R(1'b0));
|
||||
LUT5 #(
|
||||
.INIT(32'hEAAAAAA8))
|
||||
lpf_exr_i_1
|
||||
(.I0(lpf_exr),
|
||||
.I1(p_1_in4_in),
|
||||
.I2(p_2_in3_in),
|
||||
.I3(scndry_out),
|
||||
.I4(exr_lpf),
|
||||
.O(lpf_exr_reg));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "cdc_sync" *)
|
||||
module NewExtInst_TOP_rst_clk_wiz_0_100M_0_cdc_sync_0
|
||||
(lpf_asr_reg,
|
||||
scndry_out,
|
||||
lpf_asr,
|
||||
p_1_in,
|
||||
p_2_in,
|
||||
asr_lpf,
|
||||
aux_reset_in,
|
||||
slowest_sync_clk);
|
||||
output lpf_asr_reg;
|
||||
output scndry_out;
|
||||
input lpf_asr;
|
||||
input p_1_in;
|
||||
input p_2_in;
|
||||
input [0:0]asr_lpf;
|
||||
input aux_reset_in;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
|
||||
wire Q;
|
||||
wire asr_d1;
|
||||
wire [0:0]asr_lpf;
|
||||
wire aux_reset_in;
|
||||
wire lpf_asr;
|
||||
wire lpf_asr_reg;
|
||||
wire p_1_in;
|
||||
wire p_2_in;
|
||||
wire scndry_out;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(asr_d1),
|
||||
.Q(Q),
|
||||
.R(1'b0));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
|
||||
(.I0(aux_reset_in),
|
||||
.O(asr_d1));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Q),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.Q(scndry_out),
|
||||
.R(1'b0));
|
||||
LUT5 #(
|
||||
.INIT(32'hEAAAAAA8))
|
||||
lpf_asr_i_1
|
||||
(.I0(lpf_asr),
|
||||
.I1(p_1_in),
|
||||
.I2(p_2_in),
|
||||
.I3(scndry_out),
|
||||
.I4(asr_lpf),
|
||||
.O(lpf_asr_reg));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "lpf" *)
|
||||
module NewExtInst_TOP_rst_clk_wiz_0_100M_0_lpf
|
||||
(lpf_int,
|
||||
slowest_sync_clk,
|
||||
dcm_locked,
|
||||
ext_reset_in,
|
||||
mb_debug_sys_rst,
|
||||
aux_reset_in);
|
||||
output lpf_int;
|
||||
input slowest_sync_clk;
|
||||
input dcm_locked;
|
||||
input ext_reset_in;
|
||||
input mb_debug_sys_rst;
|
||||
input aux_reset_in;
|
||||
|
||||
wire \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0 ;
|
||||
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
|
||||
wire Q;
|
||||
wire [0:0]asr_lpf;
|
||||
wire aux_reset_in;
|
||||
wire dcm_locked;
|
||||
wire [0:0]exr_lpf;
|
||||
wire ext_reset_in;
|
||||
wire lpf_asr;
|
||||
wire lpf_exr;
|
||||
wire lpf_int;
|
||||
wire lpf_int0__0;
|
||||
wire mb_debug_sys_rst;
|
||||
wire p_1_in;
|
||||
wire p_1_in4_in;
|
||||
wire p_2_in;
|
||||
wire p_2_in3_in;
|
||||
wire p_3_in1_in;
|
||||
wire p_3_in6_in;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
NewExtInst_TOP_rst_clk_wiz_0_100M_0_cdc_sync \ACTIVE_HIGH_EXT.ACT_HI_EXT
|
||||
(.exr_lpf(exr_lpf),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.lpf_exr(lpf_exr),
|
||||
.lpf_exr_reg(\ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0 ),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.p_1_in4_in(p_1_in4_in),
|
||||
.p_2_in3_in(p_2_in3_in),
|
||||
.scndry_out(p_3_in6_in),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
NewExtInst_TOP_rst_clk_wiz_0_100M_0_cdc_sync_0 \ACTIVE_LOW_AUX.ACT_LO_AUX
|
||||
(.asr_lpf(asr_lpf),
|
||||
.aux_reset_in(aux_reset_in),
|
||||
.lpf_asr(lpf_asr),
|
||||
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
|
||||
.p_1_in(p_1_in),
|
||||
.p_2_in(p_2_in),
|
||||
.scndry_out(p_3_in1_in),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[1].asr_lpf_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_in1_in),
|
||||
.Q(p_2_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[2].asr_lpf_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_2_in),
|
||||
.Q(p_1_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[3].asr_lpf_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_1_in),
|
||||
.Q(asr_lpf),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[1].exr_lpf_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_in6_in),
|
||||
.Q(p_2_in3_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[2].exr_lpf_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_2_in3_in),
|
||||
.Q(p_1_in4_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[3].exr_lpf_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_1_in4_in),
|
||||
.Q(exr_lpf),
|
||||
.R(1'b0));
|
||||
(* XILINX_LEGACY_PRIM = "SRL16" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
(* srl_name = "U0/\\EXT_LPF/POR_SRL_I " *)
|
||||
SRL16E #(
|
||||
.INIT(16'hFFFF))
|
||||
POR_SRL_I
|
||||
(.A0(1'b1),
|
||||
.A1(1'b1),
|
||||
.A2(1'b1),
|
||||
.A3(1'b1),
|
||||
.CE(1'b1),
|
||||
.CLK(slowest_sync_clk),
|
||||
.D(1'b0),
|
||||
.Q(Q));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_asr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
|
||||
.Q(lpf_asr),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_exr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0 ),
|
||||
.Q(lpf_exr),
|
||||
.R(1'b0));
|
||||
LUT4 #(
|
||||
.INIT(16'hFFFD))
|
||||
lpf_int0
|
||||
(.I0(dcm_locked),
|
||||
.I1(lpf_exr),
|
||||
.I2(lpf_asr),
|
||||
.I3(Q),
|
||||
.O(lpf_int0__0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_int_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(lpf_int0__0),
|
||||
.Q(lpf_int),
|
||||
.R(1'b0));
|
||||
endmodule
|
||||
|
||||
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b1" *)
|
||||
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
|
||||
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
|
||||
(* ORIG_REF_NAME = "proc_sys_reset" *)
|
||||
module NewExtInst_TOP_rst_clk_wiz_0_100M_0_proc_sys_reset
|
||||
(slowest_sync_clk,
|
||||
ext_reset_in,
|
||||
aux_reset_in,
|
||||
mb_debug_sys_rst,
|
||||
dcm_locked,
|
||||
mb_reset,
|
||||
bus_struct_reset,
|
||||
peripheral_reset,
|
||||
interconnect_aresetn,
|
||||
peripheral_aresetn);
|
||||
input slowest_sync_clk;
|
||||
input ext_reset_in;
|
||||
input aux_reset_in;
|
||||
input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
output mb_reset;
|
||||
output [0:0]bus_struct_reset;
|
||||
output [0:0]peripheral_reset;
|
||||
output [0:0]interconnect_aresetn;
|
||||
output [0:0]peripheral_aresetn;
|
||||
|
||||
wire Bsr_out;
|
||||
wire MB_out;
|
||||
wire Pr_out;
|
||||
wire SEQ_n_3;
|
||||
wire SEQ_n_4;
|
||||
wire aux_reset_in;
|
||||
wire [0:0]bus_struct_reset;
|
||||
wire dcm_locked;
|
||||
wire ext_reset_in;
|
||||
wire [0:0]interconnect_aresetn;
|
||||
wire lpf_int;
|
||||
wire mb_debug_sys_rst;
|
||||
wire mb_reset;
|
||||
wire [0:0]peripheral_aresetn;
|
||||
wire [0:0]peripheral_reset;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(SEQ_n_3),
|
||||
.Q(interconnect_aresetn),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(SEQ_n_4),
|
||||
.Q(peripheral_aresetn),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\BSR_OUT_DFF[0].FDRE_BSR
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Bsr_out),
|
||||
.Q(bus_struct_reset),
|
||||
.R(1'b0));
|
||||
NewExtInst_TOP_rst_clk_wiz_0_100M_0_lpf EXT_LPF
|
||||
(.aux_reset_in(aux_reset_in),
|
||||
.dcm_locked(dcm_locked),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.lpf_int(lpf_int),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
FDRE_inst
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(MB_out),
|
||||
.Q(mb_reset),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\PR_OUT_DFF[0].FDRE_PER
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Pr_out),
|
||||
.Q(peripheral_reset),
|
||||
.R(1'b0));
|
||||
NewExtInst_TOP_rst_clk_wiz_0_100M_0_sequence_psr SEQ
|
||||
(.Bsr_out(Bsr_out),
|
||||
.MB_out(MB_out),
|
||||
.Pr_out(Pr_out),
|
||||
.bsr_reg_0(SEQ_n_3),
|
||||
.lpf_int(lpf_int),
|
||||
.pr_reg_0(SEQ_n_4),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "sequence_psr" *)
|
||||
module NewExtInst_TOP_rst_clk_wiz_0_100M_0_sequence_psr
|
||||
(MB_out,
|
||||
Bsr_out,
|
||||
Pr_out,
|
||||
bsr_reg_0,
|
||||
pr_reg_0,
|
||||
lpf_int,
|
||||
slowest_sync_clk);
|
||||
output MB_out;
|
||||
output Bsr_out;
|
||||
output Pr_out;
|
||||
output bsr_reg_0;
|
||||
output pr_reg_0;
|
||||
input lpf_int;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire Bsr_out;
|
||||
wire Core_i_1_n_0;
|
||||
wire MB_out;
|
||||
wire Pr_out;
|
||||
wire \bsr_dec_reg_n_0_[0] ;
|
||||
wire \bsr_dec_reg_n_0_[2] ;
|
||||
wire bsr_i_1_n_0;
|
||||
wire bsr_reg_0;
|
||||
wire \core_dec[0]_i_1_n_0 ;
|
||||
wire \core_dec[2]_i_1_n_0 ;
|
||||
wire \core_dec_reg_n_0_[0] ;
|
||||
wire \core_dec_reg_n_0_[1] ;
|
||||
wire from_sys_i_1_n_0;
|
||||
wire lpf_int;
|
||||
wire p_0_in;
|
||||
wire [2:0]p_3_out;
|
||||
wire [2:0]p_5_out;
|
||||
wire pr_dec0__0;
|
||||
wire \pr_dec_reg_n_0_[0] ;
|
||||
wire \pr_dec_reg_n_0_[2] ;
|
||||
wire pr_i_1_n_0;
|
||||
wire pr_reg_0;
|
||||
wire seq_clr;
|
||||
wire [5:0]seq_cnt;
|
||||
wire seq_cnt_en;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1
|
||||
(.I0(Bsr_out),
|
||||
.O(bsr_reg_0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair5" *)
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1
|
||||
(.I0(Pr_out),
|
||||
.O(pr_reg_0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
Core_i_1
|
||||
(.I0(MB_out),
|
||||
.I1(p_0_in),
|
||||
.O(Core_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
Core_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Core_i_1_n_0),
|
||||
.Q(MB_out),
|
||||
.S(lpf_int));
|
||||
NewExtInst_TOP_rst_clk_wiz_0_100M_0_upcnt_n SEQ_COUNTER
|
||||
(.Q(seq_cnt),
|
||||
.seq_clr(seq_clr),
|
||||
.seq_cnt_en(seq_cnt_en),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h0090))
|
||||
\bsr_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[4]),
|
||||
.I2(seq_cnt[3]),
|
||||
.I3(seq_cnt[5]),
|
||||
.O(p_5_out[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair6" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\bsr_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\bsr_dec_reg_n_0_[0] ),
|
||||
.O(p_5_out[2]));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\bsr_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_5_out[0]),
|
||||
.Q(\bsr_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\bsr_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_5_out[2]),
|
||||
.Q(\bsr_dec_reg_n_0_[2] ),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
bsr_i_1
|
||||
(.I0(Bsr_out),
|
||||
.I1(\bsr_dec_reg_n_0_[2] ),
|
||||
.O(bsr_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
bsr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(bsr_i_1_n_0),
|
||||
.Q(Bsr_out),
|
||||
.S(lpf_int));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h9000))
|
||||
\core_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[4]),
|
||||
.I2(seq_cnt[3]),
|
||||
.I3(seq_cnt[5]),
|
||||
.O(\core_dec[0]_i_1_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair6" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\core_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\core_dec_reg_n_0_[0] ),
|
||||
.O(\core_dec[2]_i_1_n_0 ));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\core_dec[0]_i_1_n_0 ),
|
||||
.Q(\core_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(pr_dec0__0),
|
||||
.Q(\core_dec_reg_n_0_[1] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\core_dec[2]_i_1_n_0 ),
|
||||
.Q(p_0_in),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
from_sys_i_1
|
||||
(.I0(MB_out),
|
||||
.I1(seq_cnt_en),
|
||||
.O(from_sys_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b0))
|
||||
from_sys_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(from_sys_i_1_n_0),
|
||||
.Q(seq_cnt_en),
|
||||
.S(lpf_int));
|
||||
LUT4 #(
|
||||
.INIT(16'h0018))
|
||||
pr_dec0
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[0]),
|
||||
.I2(seq_cnt[2]),
|
||||
.I3(seq_cnt[1]),
|
||||
.O(pr_dec0__0));
|
||||
LUT4 #(
|
||||
.INIT(16'h0480))
|
||||
\pr_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[3]),
|
||||
.I2(seq_cnt[5]),
|
||||
.I3(seq_cnt[4]),
|
||||
.O(p_3_out[0]));
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\pr_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\pr_dec_reg_n_0_[0] ),
|
||||
.O(p_3_out[2]));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\pr_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_out[0]),
|
||||
.Q(\pr_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\pr_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_out[2]),
|
||||
.Q(\pr_dec_reg_n_0_[2] ),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair5" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
pr_i_1
|
||||
(.I0(Pr_out),
|
||||
.I1(\pr_dec_reg_n_0_[2] ),
|
||||
.O(pr_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
pr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(pr_i_1_n_0),
|
||||
.Q(Pr_out),
|
||||
.S(lpf_int));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
seq_clr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(1'b1),
|
||||
.Q(seq_clr),
|
||||
.R(lpf_int));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "upcnt_n" *)
|
||||
module NewExtInst_TOP_rst_clk_wiz_0_100M_0_upcnt_n
|
||||
(Q,
|
||||
seq_clr,
|
||||
seq_cnt_en,
|
||||
slowest_sync_clk);
|
||||
output [5:0]Q;
|
||||
input seq_clr;
|
||||
input seq_cnt_en;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire [5:0]Q;
|
||||
wire clear;
|
||||
wire [5:0]q_int0;
|
||||
wire seq_clr;
|
||||
wire seq_cnt_en;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\q_int[0]_i_1
|
||||
(.I0(Q[0]),
|
||||
.O(q_int0[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\q_int[1]_i_1
|
||||
(.I0(Q[0]),
|
||||
.I1(Q[1]),
|
||||
.O(q_int0[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT3 #(
|
||||
.INIT(8'h78))
|
||||
\q_int[2]_i_1
|
||||
(.I0(Q[0]),
|
||||
.I1(Q[1]),
|
||||
.I2(Q[2]),
|
||||
.O(q_int0[2]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h7F80))
|
||||
\q_int[3]_i_1
|
||||
(.I0(Q[1]),
|
||||
.I1(Q[0]),
|
||||
.I2(Q[2]),
|
||||
.I3(Q[3]),
|
||||
.O(q_int0[3]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT5 #(
|
||||
.INIT(32'h7FFF8000))
|
||||
\q_int[4]_i_1
|
||||
(.I0(Q[2]),
|
||||
.I1(Q[0]),
|
||||
.I2(Q[1]),
|
||||
.I3(Q[3]),
|
||||
.I4(Q[4]),
|
||||
.O(q_int0[4]));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\q_int[5]_i_1
|
||||
(.I0(seq_clr),
|
||||
.O(clear));
|
||||
LUT6 #(
|
||||
.INIT(64'h7FFFFFFF80000000))
|
||||
\q_int[5]_i_2
|
||||
(.I0(Q[3]),
|
||||
.I1(Q[1]),
|
||||
.I2(Q[0]),
|
||||
.I3(Q[2]),
|
||||
.I4(Q[4]),
|
||||
.I5(Q[5]),
|
||||
.O(q_int0[5]));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[0]),
|
||||
.Q(Q[0]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[1]),
|
||||
.Q(Q[1]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[2]),
|
||||
.Q(Q[2]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[3]),
|
||||
.Q(Q[3]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[4]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[4]),
|
||||
.Q(Q[4]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[5]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[5]),
|
||||
.Q(Q[5]),
|
||||
.R(clear));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+1135
File diff suppressed because it is too large
Load Diff
+147
@@ -0,0 +1,147 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
|
||||
-- IP Revision: 14
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY proc_sys_reset_v5_0_14;
|
||||
USE proc_sys_reset_v5_0_14.proc_sys_reset;
|
||||
|
||||
ENTITY NewExtInst_TOP_rst_clk_wiz_0_100M_0 IS
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END NewExtInst_TOP_rst_clk_wiz_0_100M_0;
|
||||
|
||||
ARCHITECTURE NewExtInst_TOP_rst_clk_wiz_0_100M_0_arch OF NewExtInst_TOP_rst_clk_wiz_0_100M_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF NewExtInst_TOP_rst_clk_wiz_0_100M_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT proc_sys_reset IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_EXT_RST_WIDTH : INTEGER;
|
||||
C_AUX_RST_WIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : STD_LOGIC;
|
||||
C_AUX_RESET_HIGH : STD_LOGIC;
|
||||
C_NUM_BUS_RST : INTEGER;
|
||||
C_NUM_PERP_RST : INTEGER;
|
||||
C_NUM_INTERCONNECT_ARESETN : INTEGER;
|
||||
C_NUM_PERP_ARESETN : INTEGER
|
||||
);
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_EXT_RST_WIDTH => 4,
|
||||
C_AUX_RST_WIDTH => 4,
|
||||
C_EXT_RESET_HIGH => '1',
|
||||
C_AUX_RESET_HIGH => '0',
|
||||
C_NUM_BUS_RST => 1,
|
||||
C_NUM_PERP_RST => 1,
|
||||
C_NUM_INTERCONNECT_ARESETN => 1,
|
||||
C_NUM_PERP_ARESETN => 1
|
||||
)
|
||||
PORT MAP (
|
||||
slowest_sync_clk => slowest_sync_clk,
|
||||
ext_reset_in => ext_reset_in,
|
||||
aux_reset_in => aux_reset_in,
|
||||
mb_debug_sys_rst => mb_debug_sys_rst,
|
||||
dcm_locked => dcm_locked,
|
||||
mb_reset => mb_reset,
|
||||
bus_struct_reset => bus_struct_reset,
|
||||
peripheral_reset => peripheral_reset,
|
||||
interconnect_aresetn => interconnect_aresetn,
|
||||
peripheral_aresetn => peripheral_aresetn
|
||||
);
|
||||
END NewExtInst_TOP_rst_clk_wiz_0_100M_0_arch;
|
||||
+3926
File diff suppressed because it is too large
Load Diff
+4465
File diff suppressed because it is too large
Load Diff
+310
@@ -0,0 +1,310 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
|
||||
// IP Revision: 30
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module NewExtInst_TOP_xbar_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awaddr,
|
||||
s_axi_awprot,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_araddr,
|
||||
s_axi_arprot,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awprot,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_araddr,
|
||||
m_axi_arprot,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
|
||||
input wire [0 : 0] s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
|
||||
output wire [0 : 0] s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
|
||||
input wire [0 : 0] s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
|
||||
output wire [0 : 0] s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
|
||||
output wire [0 : 0] s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
|
||||
input wire [0 : 0] s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
|
||||
input wire [0 : 0] s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
|
||||
output wire [0 : 0] s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
|
||||
output wire [0 : 0] s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 4, NUM_WRITE_THREADS\
|
||||
4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
|
||||
input wire [0 : 0] s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]" *)
|
||||
output wire [95 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]" *)
|
||||
output wire [8 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]" *)
|
||||
output wire [2 : 0] m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]" *)
|
||||
input wire [2 : 0] m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]" *)
|
||||
output wire [95 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]" *)
|
||||
output wire [11 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]" *)
|
||||
output wire [2 : 0] m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]" *)
|
||||
input wire [2 : 0] m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]" *)
|
||||
input wire [5 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]" *)
|
||||
input wire [2 : 0] m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]" *)
|
||||
output wire [2 : 0] m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]" *)
|
||||
output wire [95 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]" *)
|
||||
output wire [8 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]" *)
|
||||
output wire [2 : 0] m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]" *)
|
||||
input wire [2 : 0] m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]" *)
|
||||
input wire [95 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]" *)
|
||||
input wire [5 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]" *)
|
||||
input wire [2 : 0] m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS\
|
||||
1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_D\
|
||||
OMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING \
|
||||
2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]" *)
|
||||
output wire [2 : 0] m_axi_rready;
|
||||
|
||||
axi_crossbar_v2_1_30_axi_crossbar #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_NUM_SLAVE_SLOTS(1),
|
||||
.C_NUM_MASTER_SLOTS(3),
|
||||
.C_AXI_ID_WIDTH(1),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(32),
|
||||
.C_AXI_PROTOCOL(2),
|
||||
.C_NUM_ADDR_RANGES(1),
|
||||
.C_M_AXI_BASE_ADDR(192'H0000000043c200000000000043c100000000000043c00000),
|
||||
.C_M_AXI_ADDR_WIDTH(96'H000000100000001000000010),
|
||||
.C_S_AXI_BASE_ID(32'H00000000),
|
||||
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
|
||||
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_M_AXI_WRITE_CONNECTIVITY(96'H000000010000000100000001),
|
||||
.C_M_AXI_READ_CONNECTIVITY(96'H000000010000000100000001),
|
||||
.C_R_REGISTER(1),
|
||||
.C_S_AXI_SINGLE_THREAD(32'H00000001),
|
||||
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
|
||||
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
|
||||
.C_M_AXI_WRITE_ISSUING(96'H000000010000000100000001),
|
||||
.C_M_AXI_READ_ISSUING(96'H000000010000000100000001),
|
||||
.C_S_AXI_ARB_PRIORITY(32'H00000000),
|
||||
.C_M_AXI_SECURE(96'H000000000000000000000000),
|
||||
.C_CONNECTIVITY_MODE(0)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(1'H0),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(8'H00),
|
||||
.s_axi_awsize(3'H0),
|
||||
.s_axi_awburst(2'H0),
|
||||
.s_axi_awlock(1'H0),
|
||||
.s_axi_awcache(4'H0),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(4'H0),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(1'H0),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(1'H1),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(1'H0),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(8'H00),
|
||||
.s_axi_arsize(3'H0),
|
||||
.s_axi_arburst(2'H0),
|
||||
.s_axi_arlock(1'H0),
|
||||
.s_axi_arcache(4'H0),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arqos(4'H0),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(3'H0),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(3'H0),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(3'H0),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(3'H7),
|
||||
.m_axi_ruser(3'H0),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+128
@@ -0,0 +1,128 @@
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
module SPI_Con_v1_0 #
|
||||
(
|
||||
// Users to add parameters here
|
||||
|
||||
// User parameters ends
|
||||
// Do not modify the parameters beyond this line
|
||||
|
||||
|
||||
// Parameters of Axi Slave Bus Interface S00_AXI
|
||||
parameter integer C_S00_AXI_DATA_WIDTH = 32,
|
||||
parameter integer C_S00_AXI_ADDR_WIDTH = 7
|
||||
)
|
||||
(
|
||||
// Users to add ports here
|
||||
input wire i_miso,
|
||||
output wire o_sclk,
|
||||
output wire o_cs,
|
||||
output wire o_mosi,
|
||||
|
||||
|
||||
// User ports ends
|
||||
// Do not modify the ports beyond this line
|
||||
|
||||
|
||||
// Ports of Axi Slave Bus Interface S00_AXI
|
||||
input wire s00_axi_aclk,
|
||||
input wire s00_axi_aresetn,
|
||||
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
|
||||
input wire [2 : 0] s00_axi_awprot,
|
||||
input wire s00_axi_awvalid,
|
||||
output wire s00_axi_awready,
|
||||
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
|
||||
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
|
||||
input wire s00_axi_wvalid,
|
||||
output wire s00_axi_wready,
|
||||
output wire [1 : 0] s00_axi_bresp,
|
||||
output wire s00_axi_bvalid,
|
||||
input wire s00_axi_bready,
|
||||
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
|
||||
input wire [2 : 0] s00_axi_arprot,
|
||||
input wire s00_axi_arvalid,
|
||||
output wire s00_axi_arready,
|
||||
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
|
||||
output wire [1 : 0] s00_axi_rresp,
|
||||
output wire s00_axi_rvalid,
|
||||
input wire s00_axi_rready
|
||||
);
|
||||
// Public Reg
|
||||
reg [6:0]spi_addr ;
|
||||
reg [23:0]spi_data;
|
||||
reg w_req;
|
||||
reg r_req;
|
||||
reg spi_done;
|
||||
|
||||
|
||||
// Instantiation of Axi Bus Interface S00_AXI
|
||||
// This inst will handle actul AXI commiuncation and register read/write
|
||||
SPI_Con_v1_0_S00_AXI # (
|
||||
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
|
||||
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
|
||||
) SPI_Con_v1_0_S00_AXI_inst (
|
||||
.S_AXI_ACLK(s00_axi_aclk),
|
||||
.S_AXI_ARESETN(s00_axi_aresetn),
|
||||
.S_AXI_AWADDR(s00_axi_awaddr),
|
||||
.S_AXI_AWPROT(s00_axi_awprot),
|
||||
.S_AXI_AWVALID(s00_axi_awvalid),
|
||||
.S_AXI_AWREADY(s00_axi_awready),
|
||||
.S_AXI_WDATA(s00_axi_wdata),
|
||||
.S_AXI_WSTRB(s00_axi_wstrb),
|
||||
.S_AXI_WVALID(s00_axi_wvalid),
|
||||
.S_AXI_WREADY(s00_axi_wready),
|
||||
.S_AXI_BRESP(s00_axi_bresp),
|
||||
.S_AXI_BVALID(s00_axi_bvalid),
|
||||
.S_AXI_BREADY(s00_axi_bready),
|
||||
.S_AXI_ARADDR(s00_axi_araddr),
|
||||
.S_AXI_ARPROT(s00_axi_arprot),
|
||||
.S_AXI_ARVALID(s00_axi_arvalid),
|
||||
.S_AXI_ARREADY(s00_axi_arready),
|
||||
.S_AXI_RDATA(s00_axi_rdata),
|
||||
.S_AXI_RRESP(s00_axi_rresp),
|
||||
.S_AXI_RVALID(s00_axi_rvalid),
|
||||
.S_AXI_RREADY(s00_axi_rready),
|
||||
.i_spi_data(spi_data),
|
||||
.i_spi_done(spi_done),
|
||||
.o_wreq(w_req),
|
||||
.o_spi_addr(spi_addr),
|
||||
.o_rreq(r_req)
|
||||
);
|
||||
|
||||
// Add user logic here
|
||||
//SPI Reg
|
||||
reg mosi_reg;
|
||||
reg miso_reg;
|
||||
reg sclk_reg;
|
||||
reg cs_reg;
|
||||
|
||||
//Flag reg
|
||||
reg busy_flag;
|
||||
|
||||
|
||||
always @(posedge s00_axi_aclk) begin
|
||||
if (s00_axi_aresetn == 1'b0) begin
|
||||
mosi_reg <= 1'b0;
|
||||
miso_reg <= 1'b0;
|
||||
sclk_reg <= 1'b0;
|
||||
cs_reg <= 1'b1;
|
||||
spi_done <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
if ((w_req == 1'b1) | (r_req == 1'b1)) begin
|
||||
spi_done <= 1'b0;
|
||||
|
||||
end
|
||||
else begin
|
||||
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign o_cs = cs_reg;
|
||||
assign o_sclk = sclk_reg;
|
||||
assign o_mosi = mosi_reg;
|
||||
// User logic ends
|
||||
|
||||
endmodule
|
||||
+716
@@ -0,0 +1,716 @@
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
module SPI_Con_v1_0_S00_AXI #
|
||||
(
|
||||
// Users to add parameters here
|
||||
|
||||
// User parameters ends
|
||||
// Do not modify the parameters beyond this line
|
||||
|
||||
// Width of S_AXI data bus
|
||||
parameter integer C_S_AXI_DATA_WIDTH = 32,
|
||||
// Width of S_AXI address bus
|
||||
parameter integer C_S_AXI_ADDR_WIDTH = 7
|
||||
)
|
||||
(
|
||||
// Users to add ports here
|
||||
input wire i_spi_data,
|
||||
input wire i_spi_done,
|
||||
output wire o_wreq,
|
||||
output wire o_spi_addr,
|
||||
output wire o_rreq,
|
||||
// User ports ends
|
||||
// Do not modify the ports beyond this line
|
||||
|
||||
// Global Clock Signal
|
||||
input wire S_AXI_ACLK,
|
||||
// Global Reset Signal. This Signal is Active LOW
|
||||
input wire S_AXI_ARESETN,
|
||||
// Write address (issued by master, acceped by Slave)
|
||||
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
|
||||
// Write channel Protection type. This signal indicates the
|
||||
// privilege and security level of the transaction, and whether
|
||||
// the transaction is a data access or an instruction access.
|
||||
input wire [2 : 0] S_AXI_AWPROT,
|
||||
// Write address valid. This signal indicates that the master signaling
|
||||
// valid write address and control information.
|
||||
input wire S_AXI_AWVALID,
|
||||
// Write address ready. This signal indicates that the slave is ready
|
||||
// to accept an address and associated control signals.
|
||||
output wire S_AXI_AWREADY,
|
||||
// Write data (issued by master, acceped by Slave)
|
||||
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
|
||||
// Write strobes. This signal indicates which byte lanes hold
|
||||
// valid data. There is one write strobe bit for each eight
|
||||
// bits of the write data bus.
|
||||
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
|
||||
// Write valid. This signal indicates that valid write
|
||||
// data and strobes are available.
|
||||
input wire S_AXI_WVALID,
|
||||
// Write ready. This signal indicates that the slave
|
||||
// can accept the write data.
|
||||
output wire S_AXI_WREADY,
|
||||
// Write response. This signal indicates the status
|
||||
// of the write transaction.
|
||||
output wire [1 : 0] S_AXI_BRESP,
|
||||
// Write response valid. This signal indicates that the channel
|
||||
// is signaling a valid write response.
|
||||
output wire S_AXI_BVALID,
|
||||
// Response ready. This signal indicates that the master
|
||||
// can accept a write response.
|
||||
input wire S_AXI_BREADY,
|
||||
// Read address (issued by master, acceped by Slave)
|
||||
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
|
||||
// Protection type. This signal indicates the privilege
|
||||
// and security level of the transaction, and whether the
|
||||
// transaction is a data access or an instruction access.
|
||||
input wire [2 : 0] S_AXI_ARPROT,
|
||||
// Read address valid. This signal indicates that the channel
|
||||
// is signaling valid read address and control information.
|
||||
input wire S_AXI_ARVALID,
|
||||
// Read address ready. This signal indicates that the slave is
|
||||
// ready to accept an address and associated control signals.
|
||||
output wire S_AXI_ARREADY,
|
||||
// Read data (issued by slave)
|
||||
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
|
||||
// Read response. This signal indicates the status of the
|
||||
// read transfer.
|
||||
output wire [1 : 0] S_AXI_RRESP,
|
||||
// Read valid. This signal indicates that the channel is
|
||||
// signaling the required read data.
|
||||
output wire S_AXI_RVALID,
|
||||
// Read ready. This signal indicates that the master can
|
||||
// accept the read data and response information.
|
||||
input wire S_AXI_RREADY
|
||||
);
|
||||
|
||||
// AXI4LITE signals
|
||||
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
|
||||
reg axi_awready;
|
||||
reg axi_wready;
|
||||
reg [1 : 0] axi_bresp;
|
||||
reg axi_bvalid;
|
||||
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
|
||||
reg axi_arready;
|
||||
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
|
||||
reg [1 : 0] axi_rresp;
|
||||
reg axi_rvalid;
|
||||
|
||||
// Example-specific design signals
|
||||
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
|
||||
// ADDR_LSB is used for addressing 32/64 bit registers/memories
|
||||
// ADDR_LSB = 2 for 32 bits (n downto 2)
|
||||
// ADDR_LSB = 3 for 64 bits (n downto 3)
|
||||
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
|
||||
localparam integer OPT_MEM_ADDR_BITS = 4;
|
||||
//----------------------------------------------
|
||||
//-- Signals for user logic register space example
|
||||
//------------------------------------------------
|
||||
//-- Number of Slave Registers 32
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg12;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg24;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg25;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg26;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31;
|
||||
wire slv_reg_rden;
|
||||
wire slv_reg_wren;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
|
||||
integer byte_index;
|
||||
reg aw_en;
|
||||
|
||||
// I/O Connections assignments
|
||||
|
||||
assign S_AXI_AWREADY = axi_awready;
|
||||
assign S_AXI_WREADY = axi_wready;
|
||||
assign S_AXI_BRESP = axi_bresp;
|
||||
assign S_AXI_BVALID = axi_bvalid;
|
||||
assign S_AXI_ARREADY = axi_arready;
|
||||
assign S_AXI_RDATA = axi_rdata;
|
||||
assign S_AXI_RRESP = axi_rresp;
|
||||
assign S_AXI_RVALID = axi_rvalid;
|
||||
// Implement axi_awready generation
|
||||
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
|
||||
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
|
||||
// de-asserted when reset is low.
|
||||
|
||||
always @( posedge S_AXI_ACLK )
|
||||
begin
|
||||
if ( S_AXI_ARESETN == 1'b0 )
|
||||
begin
|
||||
axi_awready <= 1'b0;
|
||||
aw_en <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
|
||||
begin
|
||||
// slave is ready to accept write address when
|
||||
// there is a valid write address and write data
|
||||
// on the write address and data bus. This design
|
||||
// expects no outstanding transactions.
|
||||
axi_awready <= 1'b1;
|
||||
aw_en <= 1'b0;
|
||||
end
|
||||
else if (S_AXI_BREADY && axi_bvalid)
|
||||
begin
|
||||
aw_en <= 1'b1;
|
||||
axi_awready <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
axi_awready <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Implement axi_awaddr latching
|
||||
// This process is used to latch the address when both
|
||||
// S_AXI_AWVALID and S_AXI_WVALID are valid.
|
||||
|
||||
always @( posedge S_AXI_ACLK )
|
||||
begin
|
||||
if ( S_AXI_ARESETN == 1'b0 )
|
||||
begin
|
||||
axi_awaddr <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
|
||||
begin
|
||||
// Write Address latching
|
||||
axi_awaddr <= S_AXI_AWADDR;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Implement axi_wready generation
|
||||
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
|
||||
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
|
||||
// de-asserted when reset is low.
|
||||
|
||||
always @( posedge S_AXI_ACLK )
|
||||
begin
|
||||
if ( S_AXI_ARESETN == 1'b0 )
|
||||
begin
|
||||
axi_wready <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
|
||||
begin
|
||||
// slave is ready to accept write data when
|
||||
// there is a valid write address and write data
|
||||
// on the write address and data bus. This design
|
||||
// expects no outstanding transactions.
|
||||
axi_wready <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
axi_wready <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Implement memory mapped register select and write logic generation
|
||||
// The write data is accepted and written to memory mapped registers when
|
||||
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
|
||||
// select byte enables of slave registers while writing.
|
||||
// These registers are cleared when reset (active low) is applied.
|
||||
// Slave register write enable is asserted when valid address and data are available
|
||||
// and the slave is ready to accept the write address and write data.
|
||||
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
|
||||
|
||||
always @( posedge S_AXI_ACLK )
|
||||
begin
|
||||
if ( S_AXI_ARESETN == 1'b0 )
|
||||
begin
|
||||
slv_reg0 <= 0;
|
||||
slv_reg1 <= 0;
|
||||
slv_reg2 <= 0;
|
||||
slv_reg3 <= 0;
|
||||
slv_reg4 <= 0;
|
||||
slv_reg5 <= 0;
|
||||
slv_reg6 <= 0;
|
||||
slv_reg7 <= 0;
|
||||
slv_reg8 <= 0;
|
||||
slv_reg9 <= 0;
|
||||
slv_reg10 <= 0;
|
||||
slv_reg11 <= 0;
|
||||
slv_reg12 <= 0;
|
||||
slv_reg13 <= 0;
|
||||
slv_reg14 <= 0;
|
||||
slv_reg15 <= 0;
|
||||
slv_reg16 <= 0;
|
||||
slv_reg17 <= 0;
|
||||
slv_reg18 <= 0;
|
||||
slv_reg19 <= 0;
|
||||
slv_reg20 <= 0;
|
||||
slv_reg21 <= 0;
|
||||
slv_reg22 <= 0;
|
||||
slv_reg23 <= 0;
|
||||
slv_reg24 <= 0;
|
||||
slv_reg25 <= 0;
|
||||
slv_reg26 <= 0;
|
||||
slv_reg27 <= 0;
|
||||
slv_reg28 <= 0;
|
||||
slv_reg29 <= 0;
|
||||
slv_reg30 <= 0;
|
||||
slv_reg31 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (slv_reg_wren)
|
||||
begin
|
||||
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
|
||||
5'h00:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 0
|
||||
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h01:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 1
|
||||
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h02:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 2
|
||||
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h03:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 3
|
||||
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h04:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 4
|
||||
slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h05:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 5
|
||||
slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h06:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 6
|
||||
slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h07:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 7
|
||||
slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h08:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 8
|
||||
slv_reg8[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h09:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 9
|
||||
slv_reg9[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h0A:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 10
|
||||
slv_reg10[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h0B:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 11
|
||||
slv_reg11[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h0C:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 12
|
||||
slv_reg12[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h0D:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 13
|
||||
slv_reg13[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h0E:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 14
|
||||
slv_reg14[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h0F:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 15
|
||||
slv_reg15[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h10:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 16
|
||||
slv_reg16[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h11:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 17
|
||||
slv_reg17[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h12:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 18
|
||||
slv_reg18[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h13:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 19
|
||||
slv_reg19[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h14:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 20
|
||||
slv_reg20[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h15:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 21
|
||||
slv_reg21[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h16:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 22
|
||||
slv_reg22[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h17:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 23
|
||||
slv_reg23[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h18:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 24
|
||||
slv_reg24[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h19:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 25
|
||||
slv_reg25[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h1A:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 26
|
||||
slv_reg26[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h1B:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 27
|
||||
slv_reg27[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h1C:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 28
|
||||
slv_reg28[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h1D:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 29
|
||||
slv_reg29[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h1E:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 30
|
||||
slv_reg30[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
5'h1F:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 31
|
||||
slv_reg31[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
default : begin
|
||||
slv_reg0 <= slv_reg0;
|
||||
slv_reg1 <= slv_reg1;
|
||||
slv_reg2 <= slv_reg2;
|
||||
slv_reg3 <= slv_reg3;
|
||||
slv_reg4 <= slv_reg4;
|
||||
slv_reg5 <= slv_reg5;
|
||||
slv_reg6 <= slv_reg6;
|
||||
slv_reg7 <= slv_reg7;
|
||||
slv_reg8 <= slv_reg8;
|
||||
slv_reg9 <= slv_reg9;
|
||||
slv_reg10 <= slv_reg10;
|
||||
slv_reg11 <= slv_reg11;
|
||||
slv_reg12 <= slv_reg12;
|
||||
slv_reg13 <= slv_reg13;
|
||||
slv_reg14 <= slv_reg14;
|
||||
slv_reg15 <= slv_reg15;
|
||||
slv_reg16 <= slv_reg16;
|
||||
slv_reg17 <= slv_reg17;
|
||||
slv_reg18 <= slv_reg18;
|
||||
slv_reg19 <= slv_reg19;
|
||||
slv_reg20 <= slv_reg20;
|
||||
slv_reg21 <= slv_reg21;
|
||||
slv_reg22 <= slv_reg22;
|
||||
slv_reg23 <= slv_reg23;
|
||||
slv_reg24 <= slv_reg24;
|
||||
slv_reg25 <= slv_reg25;
|
||||
slv_reg26 <= slv_reg26;
|
||||
slv_reg27 <= slv_reg27;
|
||||
slv_reg28 <= slv_reg28;
|
||||
slv_reg29 <= slv_reg29;
|
||||
slv_reg30 <= slv_reg30;
|
||||
slv_reg31 <= slv_reg31;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Implement write response logic generation
|
||||
// The write response and response valid signals are asserted by the slave
|
||||
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
|
||||
// This marks the acceptance of address and indicates the status of
|
||||
// write transaction.
|
||||
|
||||
always @( posedge S_AXI_ACLK )
|
||||
begin
|
||||
if ( S_AXI_ARESETN == 1'b0 )
|
||||
begin
|
||||
axi_bvalid <= 0;
|
||||
axi_bresp <= 2'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
|
||||
begin
|
||||
// indicates a valid write response is available
|
||||
axi_bvalid <= 1'b1;
|
||||
axi_bresp <= 2'b0; // 'OKAY' response
|
||||
end // work error responses in future
|
||||
else
|
||||
begin
|
||||
if (S_AXI_BREADY && axi_bvalid)
|
||||
//check if bready is asserted while bvalid is high)
|
||||
//(there is a possibility that bready is always asserted high)
|
||||
begin
|
||||
axi_bvalid <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Implement axi_arready generation
|
||||
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
|
||||
// S_AXI_ARVALID is asserted. axi_awready is
|
||||
// de-asserted when reset (active low) is asserted.
|
||||
// The read address is also latched when S_AXI_ARVALID is
|
||||
// asserted. axi_araddr is reset to zero on reset assertion.
|
||||
|
||||
always @( posedge S_AXI_ACLK )
|
||||
begin
|
||||
if ( S_AXI_ARESETN == 1'b0 )
|
||||
begin
|
||||
axi_arready <= 1'b0;
|
||||
axi_araddr <= 32'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (~axi_arready && S_AXI_ARVALID)
|
||||
begin
|
||||
// indicates that the slave has acceped the valid read address
|
||||
axi_arready <= 1'b1;
|
||||
// Read address latching
|
||||
axi_araddr <= S_AXI_ARADDR;
|
||||
end
|
||||
else
|
||||
begin
|
||||
axi_arready <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Implement axi_arvalid generation
|
||||
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
|
||||
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
|
||||
// data are available on the axi_rdata bus at this instance. The
|
||||
// assertion of axi_rvalid marks the validity of read data on the
|
||||
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
|
||||
// is deasserted on reset (active low). axi_rresp and axi_rdata are
|
||||
// cleared to zero on reset (active low).
|
||||
always @( posedge S_AXI_ACLK )
|
||||
begin
|
||||
if ( S_AXI_ARESETN == 1'b0 )
|
||||
begin
|
||||
axi_rvalid <= 0;
|
||||
axi_rresp <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
|
||||
begin
|
||||
// Valid read data is available at the read data bus
|
||||
axi_rvalid <= 1'b1;
|
||||
axi_rresp <= 2'b0; // 'OKAY' response
|
||||
end
|
||||
else if (axi_rvalid && S_AXI_RREADY)
|
||||
begin
|
||||
// Read data is accepted by the master
|
||||
axi_rvalid <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Implement memory mapped register select and read logic generation
|
||||
// Slave register read enable is asserted when valid address is available
|
||||
// and the slave is ready to accept the read address.
|
||||
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
|
||||
always @(*)
|
||||
begin
|
||||
// Address decoding for reading registers
|
||||
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
|
||||
5'h00 : reg_data_out <= slv_reg0;
|
||||
5'h01 : reg_data_out <= slv_reg1;
|
||||
5'h02 : reg_data_out <= slv_reg2;
|
||||
5'h03 : reg_data_out <= slv_reg3;
|
||||
5'h04 : reg_data_out <= slv_reg4;
|
||||
5'h05 : reg_data_out <= slv_reg5;
|
||||
5'h06 : reg_data_out <= slv_reg6;
|
||||
5'h07 : reg_data_out <= slv_reg7;
|
||||
5'h08 : reg_data_out <= slv_reg8;
|
||||
5'h09 : reg_data_out <= slv_reg9;
|
||||
5'h0A : reg_data_out <= slv_reg10;
|
||||
5'h0B : reg_data_out <= slv_reg11;
|
||||
5'h0C : reg_data_out <= slv_reg12;
|
||||
5'h0D : reg_data_out <= slv_reg13;
|
||||
5'h0E : reg_data_out <= slv_reg14;
|
||||
5'h0F : reg_data_out <= slv_reg15;
|
||||
5'h10 : reg_data_out <= slv_reg16;
|
||||
5'h11 : reg_data_out <= slv_reg17;
|
||||
5'h12 : reg_data_out <= slv_reg18;
|
||||
5'h13 : reg_data_out <= slv_reg19;
|
||||
5'h14 : reg_data_out <= slv_reg20;
|
||||
5'h15 : reg_data_out <= slv_reg21;
|
||||
5'h16 : reg_data_out <= slv_reg22;
|
||||
5'h17 : reg_data_out <= slv_reg23;
|
||||
5'h18 : reg_data_out <= slv_reg24;
|
||||
5'h19 : reg_data_out <= slv_reg25;
|
||||
5'h1A : reg_data_out <= slv_reg26;
|
||||
5'h1B : reg_data_out <= slv_reg27;
|
||||
5'h1C : reg_data_out <= slv_reg28;
|
||||
5'h1D : reg_data_out <= slv_reg29;
|
||||
5'h1E : reg_data_out <= slv_reg30;
|
||||
5'h1F : reg_data_out <= slv_reg31;
|
||||
default : reg_data_out <= 0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// Output register or memory read data
|
||||
always @( posedge S_AXI_ACLK )
|
||||
begin
|
||||
if ( S_AXI_ARESETN == 1'b0 )
|
||||
begin
|
||||
axi_rdata <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
// When there is a valid read address (S_AXI_ARVALID) with
|
||||
// acceptance of read address by the slave (axi_arready),
|
||||
// output the read dada
|
||||
if (slv_reg_rden)
|
||||
begin
|
||||
axi_rdata <= reg_data_out; // register read data
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Add user logic here
|
||||
|
||||
// User logic ends
|
||||
|
||||
endmodule
|
||||
+656
@@ -0,0 +1,656 @@
|
||||
{
|
||||
"version": "1.0",
|
||||
"modules": {
|
||||
"NewExtInst_TOP": {
|
||||
"proto_instances": {
|
||||
"/SPI_Con_0/S00_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "s00_axi_aclk"},
|
||||
"ARADDR": { "actual": "s00_axi_araddr[6:0]"},
|
||||
"ARESETN": { "actual": "s00_axi_aresetn"},
|
||||
"ARPROT": { "actual": "s00_axi_arprot[2:0]"},
|
||||
"ARREADY": { "actual": "s00_axi_arready"},
|
||||
"ARVALID": { "actual": "s00_axi_arvalid"},
|
||||
"AWADDR": { "actual": "s00_axi_awaddr[6:0]"},
|
||||
"AWPROT": { "actual": "s00_axi_awprot[2:0]"},
|
||||
"AWREADY": { "actual": "s00_axi_awready"},
|
||||
"AWVALID": { "actual": "s00_axi_awvalid"},
|
||||
"BREADY": { "actual": "s00_axi_bready"},
|
||||
"BRESP": { "actual": "s00_axi_bresp[1:0]"},
|
||||
"BVALID": { "actual": "s00_axi_bvalid"},
|
||||
"RDATA": { "actual": "s00_axi_rdata[31:0]"},
|
||||
"RREADY": { "actual": "s00_axi_rready"},
|
||||
"RRESP": { "actual": "s00_axi_rresp[1:0]"},
|
||||
"RVALID": { "actual": "s00_axi_rvalid"},
|
||||
"WDATA": { "actual": "s00_axi_wdata[31:0]"},
|
||||
"WREADY": { "actual": "s00_axi_wready"},
|
||||
"WSTRB": { "actual": "s00_axi_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "s00_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/SPI_Con_1/S00_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "s00_axi_aclk"},
|
||||
"ARADDR": { "actual": "s00_axi_araddr[6:0]"},
|
||||
"ARESETN": { "actual": "s00_axi_aresetn"},
|
||||
"ARPROT": { "actual": "s00_axi_arprot[2:0]"},
|
||||
"ARREADY": { "actual": "s00_axi_arready"},
|
||||
"ARVALID": { "actual": "s00_axi_arvalid"},
|
||||
"AWADDR": { "actual": "s00_axi_awaddr[6:0]"},
|
||||
"AWPROT": { "actual": "s00_axi_awprot[2:0]"},
|
||||
"AWREADY": { "actual": "s00_axi_awready"},
|
||||
"AWVALID": { "actual": "s00_axi_awvalid"},
|
||||
"BREADY": { "actual": "s00_axi_bready"},
|
||||
"BRESP": { "actual": "s00_axi_bresp[1:0]"},
|
||||
"BVALID": { "actual": "s00_axi_bvalid"},
|
||||
"RDATA": { "actual": "s00_axi_rdata[31:0]"},
|
||||
"RREADY": { "actual": "s00_axi_rready"},
|
||||
"RRESP": { "actual": "s00_axi_rresp[1:0]"},
|
||||
"RVALID": { "actual": "s00_axi_rvalid"},
|
||||
"WDATA": { "actual": "s00_axi_wdata[31:0]"},
|
||||
"WREADY": { "actual": "s00_axi_wready"},
|
||||
"WSTRB": { "actual": "s00_axi_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "s00_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/SPI_Con_2/S00_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "s00_axi_aclk"},
|
||||
"ARADDR": { "actual": "s00_axi_araddr[6:0]"},
|
||||
"ARESETN": { "actual": "s00_axi_aresetn"},
|
||||
"ARPROT": { "actual": "s00_axi_arprot[2:0]"},
|
||||
"ARREADY": { "actual": "s00_axi_arready"},
|
||||
"ARVALID": { "actual": "s00_axi_arvalid"},
|
||||
"AWADDR": { "actual": "s00_axi_awaddr[6:0]"},
|
||||
"AWPROT": { "actual": "s00_axi_awprot[2:0]"},
|
||||
"AWREADY": { "actual": "s00_axi_awready"},
|
||||
"AWVALID": { "actual": "s00_axi_awvalid"},
|
||||
"BREADY": { "actual": "s00_axi_bready"},
|
||||
"BRESP": { "actual": "s00_axi_bresp[1:0]"},
|
||||
"BVALID": { "actual": "s00_axi_bvalid"},
|
||||
"RDATA": { "actual": "s00_axi_rdata[31:0]"},
|
||||
"RREADY": { "actual": "s00_axi_rready"},
|
||||
"RRESP": { "actual": "s00_axi_rresp[1:0]"},
|
||||
"RVALID": { "actual": "s00_axi_rvalid"},
|
||||
"WDATA": { "actual": "s00_axi_wdata[31:0]"},
|
||||
"WREADY": { "actual": "s00_axi_wready"},
|
||||
"WSTRB": { "actual": "s00_axi_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "s00_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/processing_system7_0/M_AXI_GP0": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "M_AXI_GP0_ACLK"},
|
||||
"ARADDR": { "actual": "M_AXI_GP0_ARADDR[31:0]"},
|
||||
"ARBURST": { "actual": "M_AXI_GP0_ARBURST[1:0]"},
|
||||
"ARCACHE": { "actual": "M_AXI_GP0_ARCACHE[3:0]"},
|
||||
"ARID": { "actual": "M_AXI_GP0_ARID[11:0]"},
|
||||
"ARLEN": { "actual": "M_AXI_GP0_ARLEN[3:0]"},
|
||||
"ARLOCK": { "actual": "M_AXI_GP0_ARLOCK[1:0]"},
|
||||
"ARPROT": { "actual": "M_AXI_GP0_ARPROT[2:0]"},
|
||||
"ARQOS": { "actual": "M_AXI_GP0_ARQOS[3:0]"},
|
||||
"ARREADY": { "actual": "M_AXI_GP0_ARREADY"},
|
||||
"ARSIZE": { "actual": "M_AXI_GP0_ARSIZE[2:0]"},
|
||||
"ARVALID": { "actual": "M_AXI_GP0_ARVALID"},
|
||||
"AWADDR": { "actual": "M_AXI_GP0_AWADDR[31:0]"},
|
||||
"AWBURST": { "actual": "M_AXI_GP0_AWBURST[1:0]"},
|
||||
"AWCACHE": { "actual": "M_AXI_GP0_AWCACHE[3:0]"},
|
||||
"AWID": { "actual": "M_AXI_GP0_AWID[11:0]"},
|
||||
"AWLEN": { "actual": "M_AXI_GP0_AWLEN[3:0]"},
|
||||
"AWLOCK": { "actual": "M_AXI_GP0_AWLOCK[1:0]"},
|
||||
"AWPROT": { "actual": "M_AXI_GP0_AWPROT[2:0]"},
|
||||
"AWQOS": { "actual": "M_AXI_GP0_AWQOS[3:0]"},
|
||||
"AWREADY": { "actual": "M_AXI_GP0_AWREADY"},
|
||||
"AWSIZE": { "actual": "M_AXI_GP0_AWSIZE[2:0]"},
|
||||
"AWVALID": { "actual": "M_AXI_GP0_AWVALID"},
|
||||
"BID": { "actual": "M_AXI_GP0_BID[11:0]"},
|
||||
"BREADY": { "actual": "M_AXI_GP0_BREADY"},
|
||||
"BRESP": { "actual": "M_AXI_GP0_BRESP[1:0]"},
|
||||
"BVALID": { "actual": "M_AXI_GP0_BVALID"},
|
||||
"RDATA": { "actual": "M_AXI_GP0_RDATA[31:0]"},
|
||||
"RID": { "actual": "M_AXI_GP0_RID[11:0]"},
|
||||
"RLAST": { "actual": "M_AXI_GP0_RLAST"},
|
||||
"RREADY": { "actual": "M_AXI_GP0_RREADY"},
|
||||
"RRESP": { "actual": "M_AXI_GP0_RRESP[1:0]"},
|
||||
"RVALID": { "actual": "M_AXI_GP0_RVALID"},
|
||||
"WDATA": { "actual": "M_AXI_GP0_WDATA[31:0]"},
|
||||
"WID": { "actual": "M_AXI_GP0_WID[11:0]"},
|
||||
"WLAST": { "actual": "M_AXI_GP0_WLAST"},
|
||||
"WREADY": { "actual": "M_AXI_GP0_WREADY"},
|
||||
"WSTRB": { "actual": "M_AXI_GP0_WSTRB[3:0]"},
|
||||
"WVALID": { "actual": "M_AXI_GP0_WVALID"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/M00_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "M00_ACLK"},
|
||||
"ARADDR": { "actual": "M00_AXI_araddr[31:0]"},
|
||||
"ARESETN": { "actual": "ARESETN"},
|
||||
"ARPROT": { "actual": "M00_AXI_arprot[2:0]"},
|
||||
"ARREADY": { "actual": "M00_AXI_arready[0:0]"},
|
||||
"ARVALID": { "actual": "M00_AXI_arvalid[0:0]"},
|
||||
"AWADDR": { "actual": "M00_AXI_awaddr[31:0]"},
|
||||
"AWPROT": { "actual": "M00_AXI_awprot[2:0]"},
|
||||
"AWREADY": { "actual": "M00_AXI_awready[0:0]"},
|
||||
"AWVALID": { "actual": "M00_AXI_awvalid[0:0]"},
|
||||
"BREADY": { "actual": "M00_AXI_bready[0:0]"},
|
||||
"BRESP": { "actual": "M00_AXI_bresp[1:0]"},
|
||||
"BVALID": { "actual": "M00_AXI_bvalid[0:0]"},
|
||||
"RDATA": { "actual": "M00_AXI_rdata[31:0]"},
|
||||
"RREADY": { "actual": "M00_AXI_rready[0:0]"},
|
||||
"RRESP": { "actual": "M00_AXI_rresp[1:0]"},
|
||||
"RVALID": { "actual": "M00_AXI_rvalid[0:0]"},
|
||||
"WDATA": { "actual": "M00_AXI_wdata[31:0]"},
|
||||
"WREADY": { "actual": "M00_AXI_wready[0:0]"},
|
||||
"WSTRB": { "actual": "M00_AXI_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "M00_AXI_wvalid[0:0]"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/M01_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "M01_ACLK"},
|
||||
"ARADDR": { "actual": "M01_AXI_araddr[63:32]"},
|
||||
"ARESETN": { "actual": "ARESETN"},
|
||||
"ARPROT": { "actual": "M01_AXI_arprot[5:3]"},
|
||||
"ARREADY": { "actual": "M01_AXI_arready[1:1]"},
|
||||
"ARVALID": { "actual": "M01_AXI_arvalid[1:1]"},
|
||||
"AWADDR": { "actual": "M01_AXI_awaddr[63:32]"},
|
||||
"AWPROT": { "actual": "M01_AXI_awprot[5:3]"},
|
||||
"AWREADY": { "actual": "M01_AXI_awready[1:1]"},
|
||||
"AWVALID": { "actual": "M01_AXI_awvalid[1:1]"},
|
||||
"BREADY": { "actual": "M01_AXI_bready[1:1]"},
|
||||
"BRESP": { "actual": "M01_AXI_bresp[3:2]"},
|
||||
"BVALID": { "actual": "M01_AXI_bvalid[1:1]"},
|
||||
"RDATA": { "actual": "M01_AXI_rdata[63:32]"},
|
||||
"RREADY": { "actual": "M01_AXI_rready[1:1]"},
|
||||
"RRESP": { "actual": "M01_AXI_rresp[3:2]"},
|
||||
"RVALID": { "actual": "M01_AXI_rvalid[1:1]"},
|
||||
"WDATA": { "actual": "M01_AXI_wdata[63:32]"},
|
||||
"WREADY": { "actual": "M01_AXI_wready[1:1]"},
|
||||
"WSTRB": { "actual": "M01_AXI_wstrb[7:4]"},
|
||||
"WVALID": { "actual": "M01_AXI_wvalid[1:1]"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/M02_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "M02_ACLK"},
|
||||
"ARADDR": { "actual": "M02_AXI_araddr[95:64]"},
|
||||
"ARESETN": { "actual": "ARESETN"},
|
||||
"ARPROT": { "actual": "M02_AXI_arprot[8:6]"},
|
||||
"ARREADY": { "actual": "M02_AXI_arready[2:2]"},
|
||||
"ARVALID": { "actual": "M02_AXI_arvalid[2:2]"},
|
||||
"AWADDR": { "actual": "M02_AXI_awaddr[95:64]"},
|
||||
"AWPROT": { "actual": "M02_AXI_awprot[8:6]"},
|
||||
"AWREADY": { "actual": "M02_AXI_awready[2:2]"},
|
||||
"AWVALID": { "actual": "M02_AXI_awvalid[2:2]"},
|
||||
"BREADY": { "actual": "M02_AXI_bready[2:2]"},
|
||||
"BRESP": { "actual": "M02_AXI_bresp[5:4]"},
|
||||
"BVALID": { "actual": "M02_AXI_bvalid[2:2]"},
|
||||
"RDATA": { "actual": "M02_AXI_rdata[95:64]"},
|
||||
"RREADY": { "actual": "M02_AXI_rready[2:2]"},
|
||||
"RRESP": { "actual": "M02_AXI_rresp[5:4]"},
|
||||
"RVALID": { "actual": "M02_AXI_rvalid[2:2]"},
|
||||
"WDATA": { "actual": "M02_AXI_wdata[95:64]"},
|
||||
"WREADY": { "actual": "M02_AXI_wready[2:2]"},
|
||||
"WSTRB": { "actual": "M02_AXI_wstrb[11:8]"},
|
||||
"WVALID": { "actual": "M02_AXI_wvalid[2:2]"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/S00_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "S00_ACLK"},
|
||||
"ARADDR": { "actual": "S00_AXI_araddr[31:0]"},
|
||||
"ARBURST": { "actual": "S00_AXI_arburst[1:0]"},
|
||||
"ARCACHE": { "actual": "S00_AXI_arcache[3:0]"},
|
||||
"ARESETN": { "actual": "ARESETN"},
|
||||
"ARID": { "actual": "S00_AXI_arid[11:0]"},
|
||||
"ARLEN": { "actual": "S00_AXI_arlen[7:0]"},
|
||||
"ARLOCK": { "actual": "S00_AXI_arlock[0:0]"},
|
||||
"ARPROT": { "actual": "S00_AXI_arprot[2:0]"},
|
||||
"ARQOS": { "actual": "S00_AXI_arqos[3:0]"},
|
||||
"ARREADY": { "actual": "S00_AXI_arready"},
|
||||
"ARSIZE": { "actual": "S00_AXI_arsize[2:0]"},
|
||||
"ARVALID": { "actual": "S00_AXI_arvalid"},
|
||||
"AWADDR": { "actual": "S00_AXI_awaddr[31:0]"},
|
||||
"AWBURST": { "actual": "S00_AXI_awburst[1:0]"},
|
||||
"AWCACHE": { "actual": "S00_AXI_awcache[3:0]"},
|
||||
"AWID": { "actual": "S00_AXI_awid[11:0]"},
|
||||
"AWLEN": { "actual": "S00_AXI_awlen[7:0]"},
|
||||
"AWLOCK": { "actual": "S00_AXI_awlock[0:0]"},
|
||||
"AWPROT": { "actual": "S00_AXI_awprot[2:0]"},
|
||||
"AWQOS": { "actual": "S00_AXI_awqos[3:0]"},
|
||||
"AWREADY": { "actual": "S00_AXI_awready"},
|
||||
"AWSIZE": { "actual": "S00_AXI_awsize[2:0]"},
|
||||
"AWVALID": { "actual": "S00_AXI_awvalid"},
|
||||
"BID": { "actual": "S00_AXI_bid[11:0]"},
|
||||
"BREADY": { "actual": "S00_AXI_bready"},
|
||||
"BRESP": { "actual": "S00_AXI_bresp[1:0]"},
|
||||
"BVALID": { "actual": "S00_AXI_bvalid"},
|
||||
"RDATA": { "actual": "S00_AXI_rdata[31:0]"},
|
||||
"RID": { "actual": "S00_AXI_rid[11:0]"},
|
||||
"RLAST": { "actual": "S00_AXI_rlast"},
|
||||
"RREADY": { "actual": "S00_AXI_rready"},
|
||||
"RRESP": { "actual": "S00_AXI_rresp[1:0]"},
|
||||
"RVALID": { "actual": "S00_AXI_rvalid"},
|
||||
"WDATA": { "actual": "S00_AXI_wdata[31:0]"},
|
||||
"WID": { "actual": "S00_AXI_wid[11:0]"},
|
||||
"WLAST": { "actual": "S00_AXI_wlast"},
|
||||
"WREADY": { "actual": "S00_AXI_wready"},
|
||||
"WSTRB": { "actual": "S00_AXI_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "S00_AXI_wvalid"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/m00_couplers/M_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "M_ACLK"},
|
||||
"ARADDR": { "actual": "M_AXI_araddr[31:0]"},
|
||||
"ARESETN": { "actual": "M_ARESETN"},
|
||||
"ARPROT": { "actual": "M_AXI_arprot[2:0]"},
|
||||
"ARREADY": { "actual": "M_AXI_arready[0:0]"},
|
||||
"ARVALID": { "actual": "M_AXI_arvalid[0:0]"},
|
||||
"AWADDR": { "actual": "M_AXI_awaddr[31:0]"},
|
||||
"AWPROT": { "actual": "M_AXI_awprot[2:0]"},
|
||||
"AWREADY": { "actual": "M_AXI_awready[0:0]"},
|
||||
"AWVALID": { "actual": "M_AXI_awvalid[0:0]"},
|
||||
"BREADY": { "actual": "M_AXI_bready[0:0]"},
|
||||
"BRESP": { "actual": "M_AXI_bresp[1:0]"},
|
||||
"BVALID": { "actual": "M_AXI_bvalid[0:0]"},
|
||||
"RDATA": { "actual": "M_AXI_rdata[31:0]"},
|
||||
"RREADY": { "actual": "M_AXI_rready[0:0]"},
|
||||
"RRESP": { "actual": "M_AXI_rresp[1:0]"},
|
||||
"RVALID": { "actual": "M_AXI_rvalid[0:0]"},
|
||||
"WDATA": { "actual": "M_AXI_wdata[31:0]"},
|
||||
"WREADY": { "actual": "M_AXI_wready[0:0]"},
|
||||
"WSTRB": { "actual": "M_AXI_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "M_AXI_wvalid[0:0]"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/m00_couplers/S_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "S_ACLK"},
|
||||
"ARADDR": { "actual": "S_AXI_araddr[31:0]"},
|
||||
"ARESETN": { "actual": "S_ARESETN"},
|
||||
"ARPROT": { "actual": "S_AXI_arprot[2:0]"},
|
||||
"ARREADY": { "actual": "S_AXI_arready[0:0]"},
|
||||
"ARVALID": { "actual": "S_AXI_arvalid[0:0]"},
|
||||
"AWADDR": { "actual": "S_AXI_awaddr[31:0]"},
|
||||
"AWPROT": { "actual": "S_AXI_awprot[2:0]"},
|
||||
"AWREADY": { "actual": "S_AXI_awready[0:0]"},
|
||||
"AWVALID": { "actual": "S_AXI_awvalid[0:0]"},
|
||||
"BREADY": { "actual": "S_AXI_bready[0:0]"},
|
||||
"BRESP": { "actual": "S_AXI_bresp[1:0]"},
|
||||
"BVALID": { "actual": "S_AXI_bvalid[0:0]"},
|
||||
"RDATA": { "actual": "S_AXI_rdata[31:0]"},
|
||||
"RREADY": { "actual": "S_AXI_rready[0:0]"},
|
||||
"RRESP": { "actual": "S_AXI_rresp[1:0]"},
|
||||
"RVALID": { "actual": "S_AXI_rvalid[0:0]"},
|
||||
"WDATA": { "actual": "S_AXI_wdata[31:0]"},
|
||||
"WREADY": { "actual": "S_AXI_wready[0:0]"},
|
||||
"WSTRB": { "actual": "S_AXI_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "S_AXI_wvalid[0:0]"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/m01_couplers/M_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "M_ACLK"},
|
||||
"ARADDR": { "actual": "M_AXI_araddr[63:32]"},
|
||||
"ARESETN": { "actual": "M_ARESETN"},
|
||||
"ARPROT": { "actual": "M_AXI_arprot[5:3]"},
|
||||
"ARREADY": { "actual": "M_AXI_arready[1:1]"},
|
||||
"ARVALID": { "actual": "M_AXI_arvalid[1:1]"},
|
||||
"AWADDR": { "actual": "M_AXI_awaddr[63:32]"},
|
||||
"AWPROT": { "actual": "M_AXI_awprot[5:3]"},
|
||||
"AWREADY": { "actual": "M_AXI_awready[1:1]"},
|
||||
"AWVALID": { "actual": "M_AXI_awvalid[1:1]"},
|
||||
"BREADY": { "actual": "M_AXI_bready[1:1]"},
|
||||
"BRESP": { "actual": "M_AXI_bresp[3:2]"},
|
||||
"BVALID": { "actual": "M_AXI_bvalid[1:1]"},
|
||||
"RDATA": { "actual": "M_AXI_rdata[63:32]"},
|
||||
"RREADY": { "actual": "M_AXI_rready[1:1]"},
|
||||
"RRESP": { "actual": "M_AXI_rresp[3:2]"},
|
||||
"RVALID": { "actual": "M_AXI_rvalid[1:1]"},
|
||||
"WDATA": { "actual": "M_AXI_wdata[63:32]"},
|
||||
"WREADY": { "actual": "M_AXI_wready[1:1]"},
|
||||
"WSTRB": { "actual": "M_AXI_wstrb[7:4]"},
|
||||
"WVALID": { "actual": "M_AXI_wvalid[1:1]"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/m01_couplers/S_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "S_ACLK"},
|
||||
"ARADDR": { "actual": "S_AXI_araddr[63:32]"},
|
||||
"ARESETN": { "actual": "S_ARESETN"},
|
||||
"ARPROT": { "actual": "S_AXI_arprot[5:3]"},
|
||||
"ARREADY": { "actual": "S_AXI_arready[1:1]"},
|
||||
"ARVALID": { "actual": "S_AXI_arvalid[1:1]"},
|
||||
"AWADDR": { "actual": "S_AXI_awaddr[63:32]"},
|
||||
"AWPROT": { "actual": "S_AXI_awprot[5:3]"},
|
||||
"AWREADY": { "actual": "S_AXI_awready[1:1]"},
|
||||
"AWVALID": { "actual": "S_AXI_awvalid[1:1]"},
|
||||
"BREADY": { "actual": "S_AXI_bready[1:1]"},
|
||||
"BRESP": { "actual": "S_AXI_bresp[3:2]"},
|
||||
"BVALID": { "actual": "S_AXI_bvalid[1:1]"},
|
||||
"RDATA": { "actual": "S_AXI_rdata[63:32]"},
|
||||
"RREADY": { "actual": "S_AXI_rready[1:1]"},
|
||||
"RRESP": { "actual": "S_AXI_rresp[3:2]"},
|
||||
"RVALID": { "actual": "S_AXI_rvalid[1:1]"},
|
||||
"WDATA": { "actual": "S_AXI_wdata[63:32]"},
|
||||
"WREADY": { "actual": "S_AXI_wready[1:1]"},
|
||||
"WSTRB": { "actual": "S_AXI_wstrb[7:4]"},
|
||||
"WVALID": { "actual": "S_AXI_wvalid[1:1]"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/m02_couplers/M_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "M_ACLK"},
|
||||
"ARADDR": { "actual": "M_AXI_araddr[95:64]"},
|
||||
"ARESETN": { "actual": "M_ARESETN"},
|
||||
"ARPROT": { "actual": "M_AXI_arprot[8:6]"},
|
||||
"ARREADY": { "actual": "M_AXI_arready[2:2]"},
|
||||
"ARVALID": { "actual": "M_AXI_arvalid[2:2]"},
|
||||
"AWADDR": { "actual": "M_AXI_awaddr[95:64]"},
|
||||
"AWPROT": { "actual": "M_AXI_awprot[8:6]"},
|
||||
"AWREADY": { "actual": "M_AXI_awready[2:2]"},
|
||||
"AWVALID": { "actual": "M_AXI_awvalid[2:2]"},
|
||||
"BREADY": { "actual": "M_AXI_bready[2:2]"},
|
||||
"BRESP": { "actual": "M_AXI_bresp[5:4]"},
|
||||
"BVALID": { "actual": "M_AXI_bvalid[2:2]"},
|
||||
"RDATA": { "actual": "M_AXI_rdata[95:64]"},
|
||||
"RREADY": { "actual": "M_AXI_rready[2:2]"},
|
||||
"RRESP": { "actual": "M_AXI_rresp[5:4]"},
|
||||
"RVALID": { "actual": "M_AXI_rvalid[2:2]"},
|
||||
"WDATA": { "actual": "M_AXI_wdata[95:64]"},
|
||||
"WREADY": { "actual": "M_AXI_wready[2:2]"},
|
||||
"WSTRB": { "actual": "M_AXI_wstrb[11:8]"},
|
||||
"WVALID": { "actual": "M_AXI_wvalid[2:2]"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/m02_couplers/S_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "S_ACLK"},
|
||||
"ARADDR": { "actual": "S_AXI_araddr[95:64]"},
|
||||
"ARESETN": { "actual": "S_ARESETN"},
|
||||
"ARPROT": { "actual": "S_AXI_arprot[8:6]"},
|
||||
"ARREADY": { "actual": "S_AXI_arready[2:2]"},
|
||||
"ARVALID": { "actual": "S_AXI_arvalid[2:2]"},
|
||||
"AWADDR": { "actual": "S_AXI_awaddr[95:64]"},
|
||||
"AWPROT": { "actual": "S_AXI_awprot[8:6]"},
|
||||
"AWREADY": { "actual": "S_AXI_awready[2:2]"},
|
||||
"AWVALID": { "actual": "S_AXI_awvalid[2:2]"},
|
||||
"BREADY": { "actual": "S_AXI_bready[2:2]"},
|
||||
"BRESP": { "actual": "S_AXI_bresp[5:4]"},
|
||||
"BVALID": { "actual": "S_AXI_bvalid[2:2]"},
|
||||
"RDATA": { "actual": "S_AXI_rdata[95:64]"},
|
||||
"RREADY": { "actual": "S_AXI_rready[2:2]"},
|
||||
"RRESP": { "actual": "S_AXI_rresp[5:4]"},
|
||||
"RVALID": { "actual": "S_AXI_rvalid[2:2]"},
|
||||
"WDATA": { "actual": "S_AXI_wdata[95:64]"},
|
||||
"WREADY": { "actual": "S_AXI_wready[2:2]"},
|
||||
"WSTRB": { "actual": "S_AXI_wstrb[11:8]"},
|
||||
"WVALID": { "actual": "S_AXI_wvalid[2:2]"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/s00_couplers/M_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "M_ACLK"},
|
||||
"ARADDR": { "actual": "M_AXI_araddr[31:0]"},
|
||||
"ARESETN": { "actual": "M_ARESETN"},
|
||||
"ARPROT": { "actual": "M_AXI_arprot[2:0]"},
|
||||
"ARREADY": { "actual": "M_AXI_arready"},
|
||||
"ARVALID": { "actual": "M_AXI_arvalid"},
|
||||
"AWADDR": { "actual": "M_AXI_awaddr[31:0]"},
|
||||
"AWPROT": { "actual": "M_AXI_awprot[2:0]"},
|
||||
"AWREADY": { "actual": "M_AXI_awready"},
|
||||
"AWVALID": { "actual": "M_AXI_awvalid"},
|
||||
"BREADY": { "actual": "M_AXI_bready"},
|
||||
"BRESP": { "actual": "M_AXI_bresp[1:0]"},
|
||||
"BVALID": { "actual": "M_AXI_bvalid"},
|
||||
"RDATA": { "actual": "M_AXI_rdata[31:0]"},
|
||||
"RREADY": { "actual": "M_AXI_rready"},
|
||||
"RRESP": { "actual": "M_AXI_rresp[1:0]"},
|
||||
"RVALID": { "actual": "M_AXI_rvalid"},
|
||||
"WDATA": { "actual": "M_AXI_wdata[31:0]"},
|
||||
"WREADY": { "actual": "M_AXI_wready"},
|
||||
"WSTRB": { "actual": "M_AXI_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "M_AXI_wvalid"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/s00_couplers/S_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "S_ACLK"},
|
||||
"ARADDR": { "actual": "S_AXI_araddr[31:0]"},
|
||||
"ARBURST": { "actual": "S_AXI_arburst[1:0]"},
|
||||
"ARCACHE": { "actual": "S_AXI_arcache[3:0]"},
|
||||
"ARESETN": { "actual": "S_ARESETN"},
|
||||
"ARID": { "actual": "S_AXI_arid[11:0]"},
|
||||
"ARLEN": { "actual": "S_AXI_arlen[7:0]"},
|
||||
"ARLOCK": { "actual": "S_AXI_arlock[0:0]"},
|
||||
"ARPROT": { "actual": "S_AXI_arprot[2:0]"},
|
||||
"ARQOS": { "actual": "S_AXI_arqos[3:0]"},
|
||||
"ARREADY": { "actual": "S_AXI_arready"},
|
||||
"ARSIZE": { "actual": "S_AXI_arsize[2:0]"},
|
||||
"ARVALID": { "actual": "S_AXI_arvalid"},
|
||||
"AWADDR": { "actual": "S_AXI_awaddr[31:0]"},
|
||||
"AWBURST": { "actual": "S_AXI_awburst[1:0]"},
|
||||
"AWCACHE": { "actual": "S_AXI_awcache[3:0]"},
|
||||
"AWID": { "actual": "S_AXI_awid[11:0]"},
|
||||
"AWLEN": { "actual": "S_AXI_awlen[7:0]"},
|
||||
"AWLOCK": { "actual": "S_AXI_awlock[0:0]"},
|
||||
"AWPROT": { "actual": "S_AXI_awprot[2:0]"},
|
||||
"AWQOS": { "actual": "S_AXI_awqos[3:0]"},
|
||||
"AWREADY": { "actual": "S_AXI_awready"},
|
||||
"AWSIZE": { "actual": "S_AXI_awsize[2:0]"},
|
||||
"AWVALID": { "actual": "S_AXI_awvalid"},
|
||||
"BID": { "actual": "S_AXI_bid[11:0]"},
|
||||
"BREADY": { "actual": "S_AXI_bready"},
|
||||
"BRESP": { "actual": "S_AXI_bresp[1:0]"},
|
||||
"BVALID": { "actual": "S_AXI_bvalid"},
|
||||
"RDATA": { "actual": "S_AXI_rdata[31:0]"},
|
||||
"RID": { "actual": "S_AXI_rid[11:0]"},
|
||||
"RLAST": { "actual": "S_AXI_rlast"},
|
||||
"RREADY": { "actual": "S_AXI_rready"},
|
||||
"RRESP": { "actual": "S_AXI_rresp[1:0]"},
|
||||
"RVALID": { "actual": "S_AXI_rvalid"},
|
||||
"WDATA": { "actual": "S_AXI_wdata[31:0]"},
|
||||
"WID": { "actual": "S_AXI_wid[11:0]"},
|
||||
"WLAST": { "actual": "S_AXI_wlast"},
|
||||
"WREADY": { "actual": "S_AXI_wready"},
|
||||
"WSTRB": { "actual": "S_AXI_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "S_AXI_wvalid"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/s00_couplers/auto_pc/M_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "m_axi_araddr[31:0]"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARPROT": { "actual": "m_axi_arprot[2:0]"},
|
||||
"ARREADY": { "actual": "m_axi_arready"},
|
||||
"ARVALID": { "actual": "m_axi_arvalid"},
|
||||
"AWADDR": { "actual": "m_axi_awaddr[31:0]"},
|
||||
"AWPROT": { "actual": "m_axi_awprot[2:0]"},
|
||||
"AWREADY": { "actual": "m_axi_awready"},
|
||||
"AWVALID": { "actual": "m_axi_awvalid"},
|
||||
"BREADY": { "actual": "m_axi_bready"},
|
||||
"BRESP": { "actual": "m_axi_bresp[1:0]"},
|
||||
"BVALID": { "actual": "m_axi_bvalid"},
|
||||
"RDATA": { "actual": "m_axi_rdata[31:0]"},
|
||||
"RREADY": { "actual": "m_axi_rready"},
|
||||
"RRESP": { "actual": "m_axi_rresp[1:0]"},
|
||||
"RVALID": { "actual": "m_axi_rvalid"},
|
||||
"WDATA": { "actual": "m_axi_wdata[31:0]"},
|
||||
"WREADY": { "actual": "m_axi_wready"},
|
||||
"WSTRB": { "actual": "m_axi_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "m_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/s00_couplers/auto_pc/S_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "s_axi_araddr[31:0]"},
|
||||
"ARBURST": { "actual": "s_axi_arburst[1:0]"},
|
||||
"ARCACHE": { "actual": "s_axi_arcache[3:0]"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARID": { "actual": "s_axi_arid[11:0]"},
|
||||
"ARLEN": { "actual": "s_axi_arlen[3:0]"},
|
||||
"ARLOCK": { "actual": "s_axi_arlock[1:0]"},
|
||||
"ARPROT": { "actual": "s_axi_arprot[2:0]"},
|
||||
"ARQOS": { "actual": "s_axi_arqos[3:0]"},
|
||||
"ARREADY": { "actual": "s_axi_arready"},
|
||||
"ARSIZE": { "actual": "s_axi_arsize[2:0]"},
|
||||
"ARVALID": { "actual": "s_axi_arvalid"},
|
||||
"AWADDR": { "actual": "s_axi_awaddr[31:0]"},
|
||||
"AWBURST": { "actual": "s_axi_awburst[1:0]"},
|
||||
"AWCACHE": { "actual": "s_axi_awcache[3:0]"},
|
||||
"AWID": { "actual": "s_axi_awid[11:0]"},
|
||||
"AWLEN": { "actual": "s_axi_awlen[3:0]"},
|
||||
"AWLOCK": { "actual": "s_axi_awlock[1:0]"},
|
||||
"AWPROT": { "actual": "s_axi_awprot[2:0]"},
|
||||
"AWQOS": { "actual": "s_axi_awqos[3:0]"},
|
||||
"AWREADY": { "actual": "s_axi_awready"},
|
||||
"AWSIZE": { "actual": "s_axi_awsize[2:0]"},
|
||||
"AWVALID": { "actual": "s_axi_awvalid"},
|
||||
"BID": { "actual": "s_axi_bid[11:0]"},
|
||||
"BREADY": { "actual": "s_axi_bready"},
|
||||
"BRESP": { "actual": "s_axi_bresp[1:0]"},
|
||||
"BVALID": { "actual": "s_axi_bvalid"},
|
||||
"RDATA": { "actual": "s_axi_rdata[31:0]"},
|
||||
"RID": { "actual": "s_axi_rid[11:0]"},
|
||||
"RLAST": { "actual": "s_axi_rlast"},
|
||||
"RREADY": { "actual": "s_axi_rready"},
|
||||
"RRESP": { "actual": "s_axi_rresp[1:0]"},
|
||||
"RVALID": { "actual": "s_axi_rvalid"},
|
||||
"WDATA": { "actual": "s_axi_wdata[31:0]"},
|
||||
"WID": { "actual": "s_axi_wid[11:0]"},
|
||||
"WLAST": { "actual": "s_axi_wlast"},
|
||||
"WREADY": { "actual": "s_axi_wready"},
|
||||
"WSTRB": { "actual": "s_axi_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "s_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/xbar/M00_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "m_axi_araddr[31:0]"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARPROT": { "actual": "m_axi_arprot[2:0]"},
|
||||
"ARREADY": { "actual": "m_axi_arready[0:0]"},
|
||||
"ARVALID": { "actual": "m_axi_arvalid[0:0]"},
|
||||
"AWADDR": { "actual": "m_axi_awaddr[31:0]"},
|
||||
"AWPROT": { "actual": "m_axi_awprot[2:0]"},
|
||||
"AWREADY": { "actual": "m_axi_awready[0:0]"},
|
||||
"AWVALID": { "actual": "m_axi_awvalid[0:0]"},
|
||||
"BREADY": { "actual": "m_axi_bready[0:0]"},
|
||||
"BRESP": { "actual": "m_axi_bresp[1:0]"},
|
||||
"BVALID": { "actual": "m_axi_bvalid[0:0]"},
|
||||
"RDATA": { "actual": "m_axi_rdata[31:0]"},
|
||||
"RREADY": { "actual": "m_axi_rready[0:0]"},
|
||||
"RRESP": { "actual": "m_axi_rresp[1:0]"},
|
||||
"RVALID": { "actual": "m_axi_rvalid[0:0]"},
|
||||
"WDATA": { "actual": "m_axi_wdata[31:0]"},
|
||||
"WREADY": { "actual": "m_axi_wready[0:0]"},
|
||||
"WSTRB": { "actual": "m_axi_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "m_axi_wvalid[0:0]"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/xbar/M01_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "m_axi_araddr[63:32]"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARPROT": { "actual": "m_axi_arprot[5:3]"},
|
||||
"ARREADY": { "actual": "m_axi_arready[1:1]"},
|
||||
"ARVALID": { "actual": "m_axi_arvalid[1:1]"},
|
||||
"AWADDR": { "actual": "m_axi_awaddr[63:32]"},
|
||||
"AWPROT": { "actual": "m_axi_awprot[5:3]"},
|
||||
"AWREADY": { "actual": "m_axi_awready[1:1]"},
|
||||
"AWVALID": { "actual": "m_axi_awvalid[1:1]"},
|
||||
"BREADY": { "actual": "m_axi_bready[1:1]"},
|
||||
"BRESP": { "actual": "m_axi_bresp[3:2]"},
|
||||
"BVALID": { "actual": "m_axi_bvalid[1:1]"},
|
||||
"RDATA": { "actual": "m_axi_rdata[63:32]"},
|
||||
"RREADY": { "actual": "m_axi_rready[1:1]"},
|
||||
"RRESP": { "actual": "m_axi_rresp[3:2]"},
|
||||
"RVALID": { "actual": "m_axi_rvalid[1:1]"},
|
||||
"WDATA": { "actual": "m_axi_wdata[63:32]"},
|
||||
"WREADY": { "actual": "m_axi_wready[1:1]"},
|
||||
"WSTRB": { "actual": "m_axi_wstrb[7:4]"},
|
||||
"WVALID": { "actual": "m_axi_wvalid[1:1]"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/xbar/M02_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "m_axi_araddr[95:64]"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARPROT": { "actual": "m_axi_arprot[8:6]"},
|
||||
"ARREADY": { "actual": "m_axi_arready[2:2]"},
|
||||
"ARVALID": { "actual": "m_axi_arvalid[2:2]"},
|
||||
"AWADDR": { "actual": "m_axi_awaddr[95:64]"},
|
||||
"AWPROT": { "actual": "m_axi_awprot[8:6]"},
|
||||
"AWREADY": { "actual": "m_axi_awready[2:2]"},
|
||||
"AWVALID": { "actual": "m_axi_awvalid[2:2]"},
|
||||
"BREADY": { "actual": "m_axi_bready[2:2]"},
|
||||
"BRESP": { "actual": "m_axi_bresp[5:4]"},
|
||||
"BVALID": { "actual": "m_axi_bvalid[2:2]"},
|
||||
"RDATA": { "actual": "m_axi_rdata[95:64]"},
|
||||
"RREADY": { "actual": "m_axi_rready[2:2]"},
|
||||
"RRESP": { "actual": "m_axi_rresp[5:4]"},
|
||||
"RVALID": { "actual": "m_axi_rvalid[2:2]"},
|
||||
"WDATA": { "actual": "m_axi_wdata[95:64]"},
|
||||
"WREADY": { "actual": "m_axi_wready[2:2]"},
|
||||
"WSTRB": { "actual": "m_axi_wstrb[11:8]"},
|
||||
"WVALID": { "actual": "m_axi_wvalid[2:2]"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/xbar/S00_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "s_axi_araddr[31:0]"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARPROT": { "actual": "s_axi_arprot[2:0]"},
|
||||
"ARREADY": { "actual": "s_axi_arready[0:0]"},
|
||||
"ARVALID": { "actual": "s_axi_arvalid[0:0]"},
|
||||
"AWADDR": { "actual": "s_axi_awaddr[31:0]"},
|
||||
"AWPROT": { "actual": "s_axi_awprot[2:0]"},
|
||||
"AWREADY": { "actual": "s_axi_awready[0:0]"},
|
||||
"AWVALID": { "actual": "s_axi_awvalid[0:0]"},
|
||||
"BREADY": { "actual": "s_axi_bready[0:0]"},
|
||||
"BRESP": { "actual": "s_axi_bresp[1:0]"},
|
||||
"BVALID": { "actual": "s_axi_bvalid[0:0]"},
|
||||
"RDATA": { "actual": "s_axi_rdata[31:0]"},
|
||||
"RREADY": { "actual": "s_axi_rready[0:0]"},
|
||||
"RRESP": { "actual": "s_axi_rresp[1:0]"},
|
||||
"RVALID": { "actual": "s_axi_rvalid[0:0]"},
|
||||
"WDATA": { "actual": "s_axi_wdata[31:0]"},
|
||||
"WREADY": { "actual": "s_axi_wready[0:0]"},
|
||||
"WSTRB": { "actual": "s_axi_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "s_axi_wvalid[0:0]"}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+1955
File diff suppressed because it is too large
Load Diff
+26
@@ -0,0 +1,26 @@
|
||||
COMPILER=
|
||||
ARCHIVER=
|
||||
CP=cp
|
||||
COMPILER_FLAGS=
|
||||
EXTRA_COMPILER_FLAGS=
|
||||
LIB=libxil.a
|
||||
|
||||
RELEASEDIR=../../../lib
|
||||
INCLUDEDIR=../../../include
|
||||
INCLUDES=-I./. -I${INCLUDEDIR}
|
||||
|
||||
INCLUDEFILES=*.h
|
||||
LIBSOURCES=*.c
|
||||
OUTS = *.o
|
||||
|
||||
libs:
|
||||
echo "Compiling SPI_Con..."
|
||||
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
|
||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
||||
make clean
|
||||
|
||||
include:
|
||||
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
|
||||
|
||||
clean:
|
||||
rm -rf ${OUTS}
|
||||
+272
@@ -0,0 +1,272 @@
|
||||
{
|
||||
"graphjs": {
|
||||
"version": "1.0",
|
||||
"keys": [
|
||||
{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
"type": "int",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VT",
|
||||
"name": "vert_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BA",
|
||||
"name": "base_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HA",
|
||||
"name": "high_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BP",
|
||||
"name": "base_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HP",
|
||||
"name": "high_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MX",
|
||||
"name": "master_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MI",
|
||||
"name": "master_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MS",
|
||||
"name": "master_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MV",
|
||||
"name": "master_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SX",
|
||||
"name": "slave_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SI",
|
||||
"name": "slave_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MM",
|
||||
"name": "slave_memmap",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SS",
|
||||
"name": "slave_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SV",
|
||||
"name": "slave_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TM",
|
||||
"name": "memory_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TU",
|
||||
"name": "usage_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "LT",
|
||||
"name": "lock_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BT",
|
||||
"name": "boot_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
|
||||
"type": "int",
|
||||
"for": "edge"
|
||||
}
|
||||
],
|
||||
"vertice_type_order": [
|
||||
{
|
||||
"abrv": "BC",
|
||||
"desc": "Block Container"
|
||||
},
|
||||
{
|
||||
"abrv": "PR",
|
||||
"desc": "Parital Reference"
|
||||
},
|
||||
{
|
||||
"abrv": "VR",
|
||||
"desc": "Variant"
|
||||
},
|
||||
{
|
||||
"abrv": "PM",
|
||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
},
|
||||
{
|
||||
"abrv": "AC",
|
||||
"desc": "Assignment Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "ACE",
|
||||
"desc": "Excluded Assign Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "APX",
|
||||
"desc": "Boundary Aperture"
|
||||
},
|
||||
{
|
||||
"abrv": "CIP",
|
||||
"desc": "High level Processing System"
|
||||
}
|
||||
],
|
||||
"vertices": {
|
||||
"V0": {
|
||||
"VM": "NewExtInst_TOP",
|
||||
"VT": "BC"
|
||||
},
|
||||
"V1": {
|
||||
"VH": "2",
|
||||
"VM": "NewExtInst_TOP",
|
||||
"VT": "VR"
|
||||
},
|
||||
"V2": {
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
},
|
||||
"V3": {
|
||||
"VT": "AC",
|
||||
"BA": "0x43C00000",
|
||||
"HA": "0x43C0FFFF",
|
||||
"BP": "C_S00_AXI_BASEADDR",
|
||||
"HP": "C_S00_AXI_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_SPI_Con_0_S00_AXI_reg",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/SPI_Con_0",
|
||||
"SI": "S00_AXI",
|
||||
"SS": "S00_AXI_reg",
|
||||
"SV": "xilinx.com:user:SPI_Con:1.0",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
},
|
||||
"V4": {
|
||||
"VT": "AC",
|
||||
"BA": "0x43C10000",
|
||||
"HA": "0x43C1FFFF",
|
||||
"BP": "C_S00_AXI_BASEADDR",
|
||||
"HP": "C_S00_AXI_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_SPI_Con_1_S00_AXI_reg",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/SPI_Con_1",
|
||||
"SI": "S00_AXI",
|
||||
"SS": "S00_AXI_reg",
|
||||
"SV": "xilinx.com:user:SPI_Con:1.0",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
},
|
||||
"V5": {
|
||||
"VT": "AC",
|
||||
"BA": "0x43C20000",
|
||||
"HA": "0x43C2FFFF",
|
||||
"BP": "C_S00_AXI_BASEADDR",
|
||||
"HP": "C_S00_AXI_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_SPI_Con_2_S00_AXI_reg",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/SPI_Con_2",
|
||||
"SI": "S00_AXI",
|
||||
"SS": "S00_AXI_reg",
|
||||
"SV": "xilinx.com:user:SPI_Con:1.0",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
},
|
||||
{
|
||||
"src": "V3",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V4",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V5",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
+107
@@ -0,0 +1,107 @@
|
||||
|
||||
#ifndef SPI_CON_H
|
||||
#define SPI_CON_H
|
||||
|
||||
|
||||
/****************** Include Files ********************/
|
||||
#include "xil_types.h"
|
||||
#include "xstatus.h"
|
||||
|
||||
#define SPI_CON_S00_AXI_SLV_REG0_OFFSET 0
|
||||
#define SPI_CON_S00_AXI_SLV_REG1_OFFSET 4
|
||||
#define SPI_CON_S00_AXI_SLV_REG2_OFFSET 8
|
||||
#define SPI_CON_S00_AXI_SLV_REG3_OFFSET 12
|
||||
#define SPI_CON_S00_AXI_SLV_REG4_OFFSET 16
|
||||
#define SPI_CON_S00_AXI_SLV_REG5_OFFSET 20
|
||||
#define SPI_CON_S00_AXI_SLV_REG6_OFFSET 24
|
||||
#define SPI_CON_S00_AXI_SLV_REG7_OFFSET 28
|
||||
#define SPI_CON_S00_AXI_SLV_REG8_OFFSET 32
|
||||
#define SPI_CON_S00_AXI_SLV_REG9_OFFSET 36
|
||||
#define SPI_CON_S00_AXI_SLV_REG10_OFFSET 40
|
||||
#define SPI_CON_S00_AXI_SLV_REG11_OFFSET 44
|
||||
#define SPI_CON_S00_AXI_SLV_REG12_OFFSET 48
|
||||
#define SPI_CON_S00_AXI_SLV_REG13_OFFSET 52
|
||||
#define SPI_CON_S00_AXI_SLV_REG14_OFFSET 56
|
||||
#define SPI_CON_S00_AXI_SLV_REG15_OFFSET 60
|
||||
#define SPI_CON_S00_AXI_SLV_REG16_OFFSET 64
|
||||
#define SPI_CON_S00_AXI_SLV_REG17_OFFSET 68
|
||||
#define SPI_CON_S00_AXI_SLV_REG18_OFFSET 72
|
||||
#define SPI_CON_S00_AXI_SLV_REG19_OFFSET 76
|
||||
#define SPI_CON_S00_AXI_SLV_REG20_OFFSET 80
|
||||
#define SPI_CON_S00_AXI_SLV_REG21_OFFSET 84
|
||||
#define SPI_CON_S00_AXI_SLV_REG22_OFFSET 88
|
||||
#define SPI_CON_S00_AXI_SLV_REG23_OFFSET 92
|
||||
#define SPI_CON_S00_AXI_SLV_REG24_OFFSET 96
|
||||
#define SPI_CON_S00_AXI_SLV_REG25_OFFSET 100
|
||||
#define SPI_CON_S00_AXI_SLV_REG26_OFFSET 104
|
||||
#define SPI_CON_S00_AXI_SLV_REG27_OFFSET 108
|
||||
#define SPI_CON_S00_AXI_SLV_REG28_OFFSET 112
|
||||
#define SPI_CON_S00_AXI_SLV_REG29_OFFSET 116
|
||||
#define SPI_CON_S00_AXI_SLV_REG30_OFFSET 120
|
||||
#define SPI_CON_S00_AXI_SLV_REG31_OFFSET 124
|
||||
|
||||
|
||||
/**************************** Type Definitions *****************************/
|
||||
/**
|
||||
*
|
||||
* Write a value to a SPI_CON register. A 32 bit write is performed.
|
||||
* If the component is implemented in a smaller width, only the least
|
||||
* significant data is written.
|
||||
*
|
||||
* @param BaseAddress is the base address of the SPI_CONdevice.
|
||||
* @param RegOffset is the register offset from the base to write to.
|
||||
* @param Data is the data written to the register.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void SPI_CON_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
|
||||
*
|
||||
*/
|
||||
#define SPI_CON_mWriteReg(BaseAddress, RegOffset, Data) \
|
||||
Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
|
||||
|
||||
/**
|
||||
*
|
||||
* Read a value from a SPI_CON register. A 32 bit read is performed.
|
||||
* If the component is implemented in a smaller width, only the least
|
||||
* significant data is read from the register. The most significant data
|
||||
* will be read as 0.
|
||||
*
|
||||
* @param BaseAddress is the base address of the SPI_CON device.
|
||||
* @param RegOffset is the register offset from the base to write to.
|
||||
*
|
||||
* @return Data is the data from the register.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* u32 SPI_CON_mReadReg(u32 BaseAddress, unsigned RegOffset)
|
||||
*
|
||||
*/
|
||||
#define SPI_CON_mReadReg(BaseAddress, RegOffset) \
|
||||
Xil_In32((BaseAddress) + (RegOffset))
|
||||
|
||||
/************************** Function Prototypes ****************************/
|
||||
/**
|
||||
*
|
||||
* Run a self-test on the driver/device. Note this may be a destructive test if
|
||||
* resets of the device are performed.
|
||||
*
|
||||
* If the hardware system is not built correctly, this function may never
|
||||
* return to the caller.
|
||||
*
|
||||
* @param baseaddr_p is the base address of the SPI_CON instance to be worked on.
|
||||
*
|
||||
* @return
|
||||
*
|
||||
* - XST_SUCCESS if all self-test code passed
|
||||
* - XST_FAILURE if any self-test code failed
|
||||
*
|
||||
* @note Caching must be turned off for this function to work.
|
||||
* @note Self test may fail if data memory and device are not on the same bus.
|
||||
*
|
||||
*/
|
||||
XStatus SPI_CON_Reg_SelfTest(void * baseaddr_p);
|
||||
|
||||
#endif // SPI_CON_H
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
|
||||
|
||||
OPTION psf_version = 2.1;
|
||||
|
||||
BEGIN DRIVER SPI_Con
|
||||
OPTION supported_peripherals = (SPI_Con);
|
||||
OPTION copyfiles = all;
|
||||
OPTION VERSION = 1.0;
|
||||
OPTION NAME = SPI_Con;
|
||||
END DRIVER
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
|
||||
|
||||
proc generate {drv_handle} {
|
||||
xdefine_include_file $drv_handle "xparameters.h" "SPI_Con" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
|
||||
}
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
+117
@@ -0,0 +1,117 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158730
|
||||
#define QSPI_FREQ 142857132
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 100000000
|
||||
#define UART_FREQ 100000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 25000000
|
||||
#define FPGA1_FREQ 50000000
|
||||
#define FPGA2_FREQ 100000000
|
||||
#define FPGA3_FREQ 200000000
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
+125613
File diff suppressed because it is too large
Load Diff
+781
@@ -0,0 +1,781 @@
|
||||
proc ps7_pll_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000701
|
||||
mask_write 0XF8000150 0x00003F33 0x00000A03
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A02
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00500800
|
||||
mask_write 0XF8000180 0x03F03F30 0x00400500
|
||||
mask_write 0XF8000190 0x03F03F30 0x00200500
|
||||
mask_write 0XF80001A0 0x03F03F30 0x00100500
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_3_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x0007FFFF 0x00001082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
|
||||
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00000003 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x0003F03F 0x0003C008
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x00010000 0x00000000
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x00000200 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000080
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000703FF 0x000003FF
|
||||
mask_write 0XF800620C 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006210 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006214 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF5 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000260
|
||||
mask_write 0XF8000B70 0x00000001 0x00000001
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003F01 0x00001601
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000724 0x00003F01 0x00001601
|
||||
mask_write 0XF8000728 0x00003FFF 0x00001680
|
||||
mask_write 0XF800072C 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000730 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000734 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000738 0x00003FFF 0x00001680
|
||||
mask_write 0XF800073C 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001202
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001203
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001203
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001203
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B8 0x00003F01 0x00001201
|
||||
mask_write 0XF80007BC 0x00003F01 0x00001201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000012E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000012E1
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F002E
|
||||
mask_write 0XF8000834 0x003F003F 0x00090000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x000003FF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_3_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000701
|
||||
mask_write 0XF8000150 0x00003F33 0x00000A03
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A02
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00500800
|
||||
mask_write 0XF8000180 0x03F03F30 0x00400500
|
||||
mask_write 0XF8000190 0x03F03F30 0x00200500
|
||||
mask_write 0XF80001A0 0x03F03F30 0x00100500
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_2_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000080
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000260
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003F01 0x00001601
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000724 0x00003F01 0x00001601
|
||||
mask_write 0XF8000728 0x00003FFF 0x00001680
|
||||
mask_write 0XF800072C 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000730 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000734 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000738 0x00003FFF 0x00001680
|
||||
mask_write 0XF800073C 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001202
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001203
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001203
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001203
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B8 0x00003F01 0x00001201
|
||||
mask_write 0XF80007BC 0x00003F01 0x00001201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000012E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000012E1
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F002E
|
||||
mask_write 0XF8000834 0x003F003F 0x00090000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x00000FFF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_2_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000701
|
||||
mask_write 0XF8000150 0x00003F33 0x00000A03
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A02
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00500800
|
||||
mask_write 0XF8000180 0x03F03F30 0x00400500
|
||||
mask_write 0XF8000190 0x03F03F30 0x00200500
|
||||
mask_write 0XF80001A0 0x03F03F30 0x00100500
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_1_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000080
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x000073FF 0x00000260
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003F01 0x00001601
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000724 0x00003F01 0x00001601
|
||||
mask_write 0XF8000728 0x00003FFF 0x00001680
|
||||
mask_write 0XF800072C 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000730 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000734 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000738 0x00003FFF 0x00001680
|
||||
mask_write 0XF800073C 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001202
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001203
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001203
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001203
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B8 0x00003F01 0x00001201
|
||||
mask_write 0XF80007BC 0x00003F01 0x00001201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000012E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000012E1
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F002E
|
||||
mask_write 0XF8000834 0x003F003F 0x00090000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x00000FFF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_1_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
set PCW_SILICON_VER_1_0 "0x0"
|
||||
set PCW_SILICON_VER_2_0 "0x1"
|
||||
set PCW_SILICON_VER_3_0 "0x2"
|
||||
set APU_FREQ 666666666
|
||||
|
||||
|
||||
|
||||
proc mask_poll { addr mask } {
|
||||
set count 1
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
while { $maskedval == 0 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
set count [ expr { $count + 1 } ]
|
||||
if { $count == 100000000 } {
|
||||
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
|
||||
break
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
proc mask_delay { addr val } {
|
||||
set delay [ get_number_of_cycles_for_delay $val ]
|
||||
perf_reset_and_start_timer
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
while { $maskedval == 1 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
}
|
||||
perf_reset_clock
|
||||
}
|
||||
|
||||
proc ps_version { } {
|
||||
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
|
||||
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
|
||||
return $mask_sil_ver;
|
||||
}
|
||||
|
||||
proc ps7_post_config {} {
|
||||
set saved_mode [configparams force-mem-accesses]
|
||||
configparams force-mem-accesses 1
|
||||
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_post_config_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_post_config_2_0
|
||||
} else {
|
||||
ps7_post_config_3_0
|
||||
}
|
||||
configparams force-mem-accesses $saved_mode
|
||||
}
|
||||
|
||||
proc ps7_debug {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_debug_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_debug_2_0
|
||||
} else {
|
||||
ps7_debug_3_0
|
||||
}
|
||||
}
|
||||
proc ps7_init {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_mio_init_data_1_0
|
||||
ps7_pll_init_data_1_0
|
||||
ps7_clock_init_data_1_0
|
||||
ps7_ddr_init_data_1_0
|
||||
ps7_peripherals_init_data_1_0
|
||||
#puts "PCW Silicon Version : 1.0"
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_mio_init_data_2_0
|
||||
ps7_pll_init_data_2_0
|
||||
ps7_clock_init_data_2_0
|
||||
ps7_ddr_init_data_2_0
|
||||
ps7_peripherals_init_data_2_0
|
||||
#puts "PCW Silicon Version : 2.0"
|
||||
} else {
|
||||
ps7_mio_init_data_3_0
|
||||
ps7_pll_init_data_3_0
|
||||
ps7_clock_init_data_3_0
|
||||
ps7_ddr_init_data_3_0
|
||||
ps7_peripherals_init_data_3_0
|
||||
#puts "PCW Silicon Version : 3.0"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# For delay calculation using global timer
|
||||
|
||||
# start timer
|
||||
proc perf_start_clock { } {
|
||||
|
||||
#writing SCU_GLOBAL_TIMER_CONTROL register
|
||||
|
||||
mask_write 0xF8F00208 0x00000109 0x00000009
|
||||
}
|
||||
|
||||
# stop timer and reset timer count regs
|
||||
proc perf_reset_clock { } {
|
||||
perf_disable_clock
|
||||
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
|
||||
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
# Compute mask for given delay in miliseconds
|
||||
proc get_number_of_cycles_for_delay { delay } {
|
||||
|
||||
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
|
||||
variable APU_FREQ
|
||||
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
|
||||
}
|
||||
|
||||
|
||||
# stop timer
|
||||
proc perf_disable_clock {} {
|
||||
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
proc perf_reset_and_start_timer {} {
|
||||
perf_reset_clock
|
||||
perf_start_clock
|
||||
}
|
||||
|
||||
|
||||
+131
@@ -0,0 +1,131 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010-2020 <Xilinx Inc.>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, see <http://www.gnu.org/licenses/>
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init_gpl.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158730
|
||||
#define QSPI_FREQ 142857132
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 100000000
|
||||
#define UART_FREQ 100000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 25000000
|
||||
#define FPGA1_FREQ 50000000
|
||||
#define FPGA2_FREQ 100000000
|
||||
#define FPGA3_FREQ 200000000
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
+106
@@ -0,0 +1,106 @@
|
||||
/*
|
||||
* Xilinx SystemC/TLM-2.0 Zynq Wrapper.
|
||||
*
|
||||
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
|
||||
*
|
||||
* Copyright (c) 2016, Xilinx Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define SC_INCLUDE_DYNAMIC_PROCESSES
|
||||
|
||||
#include <inttypes.h>
|
||||
|
||||
#include "tlm_utils/simple_initiator_socket.h"
|
||||
#include "tlm_utils/simple_target_socket.h"
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace std;
|
||||
|
||||
#include "xilinx-zynq.h"
|
||||
#include <sys/types.h>
|
||||
|
||||
//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr,
|
||||
// Iremoteport_tlm_sync *sync)
|
||||
// : remoteport_tlm(name, -1, sk_descr, sync),
|
||||
xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr)
|
||||
: remoteport_tlm(name, -1, sk_descr),
|
||||
rp_m_axi_gp0("rp_m_axi_gp0"),
|
||||
rp_m_axi_gp1("rp_m_axi_gp1"),
|
||||
rp_s_axi_gp0("rp_s_axi_gp0"),
|
||||
rp_s_axi_gp1("rp_s_axi_gp1"),
|
||||
rp_s_axi_hp0("rp_s_axi_hp0"),
|
||||
rp_s_axi_hp1("rp_s_axi_hp1"),
|
||||
rp_s_axi_hp2("rp_s_axi_hp2"),
|
||||
rp_s_axi_hp3("rp_s_axi_hp3"),
|
||||
rp_s_axi_acp("rp_s_axi_acp"),
|
||||
rp_wires_in("wires_in", 20, 0),
|
||||
rp_wires_out("wires_out", 0, 17),
|
||||
rp_irq_out("irq_out", 0, 28),
|
||||
pl2ps_irq("pl2ps_irq", 20),
|
||||
ps2pl_irq("ps2pl_irq", 28),
|
||||
ps2pl_rst("ps2pl_rst", 17)
|
||||
{
|
||||
int i;
|
||||
|
||||
m_axi_gp[0] = &rp_m_axi_gp0.sk;
|
||||
m_axi_gp[1] = &rp_m_axi_gp1.sk;
|
||||
|
||||
s_axi_gp[0] = &rp_s_axi_gp0.sk;
|
||||
s_axi_gp[1] = &rp_s_axi_gp1.sk;
|
||||
|
||||
s_axi_hp[0] = &rp_s_axi_hp0.sk;
|
||||
s_axi_hp[1] = &rp_s_axi_hp1.sk;
|
||||
s_axi_hp[2] = &rp_s_axi_hp2.sk;
|
||||
s_axi_hp[3] = &rp_s_axi_hp3.sk;
|
||||
s_axi_acp = &rp_s_axi_acp.sk;
|
||||
|
||||
/* PL to PS Interrupt signals. */
|
||||
for (i = 0; i < 20; i++) {
|
||||
rp_wires_in.wires_in[i](pl2ps_irq[i]);
|
||||
}
|
||||
|
||||
/* PS to PL Interrupt signals. */
|
||||
for (i = 0; i < 28; i++) {
|
||||
rp_irq_out.wires_out[i](ps2pl_irq[i]);
|
||||
}
|
||||
|
||||
/* PS to PL resets. */
|
||||
for (i = 0; i < 17; i++) {
|
||||
rp_wires_out.wires_out[i](ps2pl_rst[i]);
|
||||
}
|
||||
|
||||
register_dev(0, &rp_s_axi_gp0);
|
||||
register_dev(1, &rp_s_axi_gp1);
|
||||
|
||||
register_dev(2, &rp_s_axi_hp0);
|
||||
register_dev(3, &rp_s_axi_hp1);
|
||||
register_dev(4, &rp_s_axi_hp2);
|
||||
register_dev(5, &rp_s_axi_hp3);
|
||||
|
||||
register_dev(6, &rp_s_axi_acp);
|
||||
|
||||
register_dev(7, &rp_m_axi_gp0);
|
||||
register_dev(8, &rp_m_axi_gp1);
|
||||
register_dev(9, &rp_wires_in);
|
||||
register_dev(10, &rp_wires_out);
|
||||
register_dev(11, &rp_irq_out);
|
||||
}
|
||||
Executable
+26
@@ -0,0 +1,26 @@
|
||||
COMPILER=
|
||||
ARCHIVER=
|
||||
CP=cp
|
||||
COMPILER_FLAGS=
|
||||
EXTRA_COMPILER_FLAGS=
|
||||
LIB=libxil.a
|
||||
|
||||
RELEASEDIR=../../../lib
|
||||
INCLUDEDIR=../../../include
|
||||
INCLUDES=-I./. -I${INCLUDEDIR}
|
||||
|
||||
INCLUDEFILES=*.h
|
||||
LIBSOURCES=*.c
|
||||
OUTS = *.o
|
||||
|
||||
libs:
|
||||
echo "Compiling SPI_Con..."
|
||||
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
|
||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
||||
make clean
|
||||
|
||||
include:
|
||||
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
|
||||
|
||||
clean:
|
||||
rm -rf ${OUTS}
|
||||
+272
@@ -0,0 +1,272 @@
|
||||
{
|
||||
"graphjs": {
|
||||
"version": "1.0",
|
||||
"keys": [
|
||||
{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
"type": "int",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VT",
|
||||
"name": "vert_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BA",
|
||||
"name": "base_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HA",
|
||||
"name": "high_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BP",
|
||||
"name": "base_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HP",
|
||||
"name": "high_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MX",
|
||||
"name": "master_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MI",
|
||||
"name": "master_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MS",
|
||||
"name": "master_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MV",
|
||||
"name": "master_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SX",
|
||||
"name": "slave_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SI",
|
||||
"name": "slave_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MM",
|
||||
"name": "slave_memmap",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SS",
|
||||
"name": "slave_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SV",
|
||||
"name": "slave_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TM",
|
||||
"name": "memory_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TU",
|
||||
"name": "usage_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "LT",
|
||||
"name": "lock_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BT",
|
||||
"name": "boot_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
|
||||
"type": "int",
|
||||
"for": "edge"
|
||||
}
|
||||
],
|
||||
"vertice_type_order": [
|
||||
{
|
||||
"abrv": "BC",
|
||||
"desc": "Block Container"
|
||||
},
|
||||
{
|
||||
"abrv": "PR",
|
||||
"desc": "Parital Reference"
|
||||
},
|
||||
{
|
||||
"abrv": "VR",
|
||||
"desc": "Variant"
|
||||
},
|
||||
{
|
||||
"abrv": "PM",
|
||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
},
|
||||
{
|
||||
"abrv": "AC",
|
||||
"desc": "Assignment Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "ACE",
|
||||
"desc": "Excluded Assign Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "APX",
|
||||
"desc": "Boundary Aperture"
|
||||
},
|
||||
{
|
||||
"abrv": "CIP",
|
||||
"desc": "High level Processing System"
|
||||
}
|
||||
],
|
||||
"vertices": {
|
||||
"V0": {
|
||||
"VM": "NewExtInst_TOP",
|
||||
"VT": "BC"
|
||||
},
|
||||
"V1": {
|
||||
"VH": "2",
|
||||
"VM": "NewExtInst_TOP",
|
||||
"VT": "VR"
|
||||
},
|
||||
"V2": {
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
},
|
||||
"V3": {
|
||||
"VT": "AC",
|
||||
"BA": "0x43C00000",
|
||||
"HA": "0x43C0FFFF",
|
||||
"BP": "C_S00_AXI_BASEADDR",
|
||||
"HP": "C_S00_AXI_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_SPI_Con_0_S00_AXI_reg",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/SPI_Con_0",
|
||||
"SI": "S00_AXI",
|
||||
"SS": "S00_AXI_reg",
|
||||
"SV": "xilinx.com:user:SPI_Con:1.0",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
},
|
||||
"V4": {
|
||||
"VT": "AC",
|
||||
"BA": "0x43C10000",
|
||||
"HA": "0x43C1FFFF",
|
||||
"BP": "C_S00_AXI_BASEADDR",
|
||||
"HP": "C_S00_AXI_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_SPI_Con_1_S00_AXI_reg",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/SPI_Con_1",
|
||||
"SI": "S00_AXI",
|
||||
"SS": "S00_AXI_reg",
|
||||
"SV": "xilinx.com:user:SPI_Con:1.0",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
},
|
||||
"V5": {
|
||||
"VT": "AC",
|
||||
"BA": "0x43C20000",
|
||||
"HA": "0x43C2FFFF",
|
||||
"BP": "C_S00_AXI_BASEADDR",
|
||||
"HP": "C_S00_AXI_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_SPI_Con_2_S00_AXI_reg",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/SPI_Con_2",
|
||||
"SI": "S00_AXI",
|
||||
"SS": "S00_AXI_reg",
|
||||
"SV": "xilinx.com:user:SPI_Con:1.0",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
},
|
||||
{
|
||||
"src": "V3",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V4",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V5",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
+258
@@ -0,0 +1,258 @@
|
||||
#!/usr/bin/env bash
|
||||
#**********************************************************************************************************
|
||||
# Vivado (TM) v2023.2 (64-bit)
|
||||
#
|
||||
# Script generated by Vivado on Fri May 15 15:32:22 CST 2026
|
||||
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
|
||||
#
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
# Filename : NewExtInst_TOP.sh
|
||||
# Simulator : Aldec Active-HDL Simulator
|
||||
# Description : Simulation script generated by export_simulation Tcl command
|
||||
# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
|
||||
# design. The script will copy the library mapping file from the compiled library directory,
|
||||
# create design library directories and library mappings in the mapping file.
|
||||
#
|
||||
# Usage : NewExtInst_TOP.sh
|
||||
# NewExtInst_TOP.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
|
||||
# NewExtInst_TOP.sh [-reset_run]
|
||||
# NewExtInst_TOP.sh [-reset_log]
|
||||
# NewExtInst_TOP.sh [-help]
|
||||
#
|
||||
# * The -noclean_files switch is deprecated and will not peform any function (by default, the
|
||||
# simulator generated files will not be removed unless -reset_run switch is used)
|
||||
#
|
||||
# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library
|
||||
# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
|
||||
# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
|
||||
# switch with the directory path where the library is created while generating the script
|
||||
# with export_simulation.
|
||||
#
|
||||
# Alternatively, you can set the library path by setting the following project property:-
|
||||
#
|
||||
# set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
|
||||
#
|
||||
# You can also point to the simulation library by either setting the 'lib_map_path' global
|
||||
# variable in this script or specify it with the '-lib_map_path' switch while executing this
|
||||
# script (type 'NewExtInst_TOP.sh -help' for more information).
|
||||
#
|
||||
# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
|
||||
# generated script, but if design is targetted for system simulation containing SystemC/C++/C
|
||||
# sources, then the library path MUST be specified upfront when calling export_simulation.
|
||||
#
|
||||
# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#**********************************************************************************************************
|
||||
|
||||
# script info
|
||||
echo -e "NewExtInst_TOP.sh - Script generated by export_simulation (Vivado v2023.2 (64-bit)-id)\n"
|
||||
|
||||
# main steps
|
||||
run()
|
||||
{
|
||||
check_args $*
|
||||
setup
|
||||
if [[ ($b_step == 1) ]]; then
|
||||
case $step in
|
||||
"compile" )
|
||||
init_lib
|
||||
compile
|
||||
;;
|
||||
"simulate" )
|
||||
simulate
|
||||
;;
|
||||
* )
|
||||
echo -e "ERROR: Invalid or missing step '$step' (type \"./NewExtInst_TOP.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
esac
|
||||
else
|
||||
init_lib
|
||||
compile
|
||||
simulate
|
||||
fi
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
runvsimsa -do "do {compile.do}" 2>&1 | tee -a compile.log
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
runvsimsa -l simulate.log -do "do {simulate.do}"
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
# delete previous files for a clean rerun
|
||||
if [[ ($b_reset_run == 1) ]]; then
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
fi
|
||||
|
||||
# delete previous log files
|
||||
if [[ ($b_reset_log == 1) ]]; then
|
||||
reset_log
|
||||
echo -e "INFO: Simulation run log files deleted.\n"
|
||||
exit 0
|
||||
fi
|
||||
|
||||
# add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# simulator index file/library directory processing
|
||||
init_lib()
|
||||
{
|
||||
if [[ ($b_keep_index == 1) ]]; then
|
||||
# keep previous design library mappings
|
||||
true
|
||||
else
|
||||
# map simulator index file
|
||||
map_setup_file
|
||||
fi
|
||||
}
|
||||
|
||||
# map library.cfg file
|
||||
map_setup_file()
|
||||
{
|
||||
file="library.cfg"
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
if [[ -e $src_file ]]; then
|
||||
vmap -link $lib_map_path
|
||||
fi
|
||||
fi
|
||||
}
|
||||
|
||||
# delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# delete generated log files from the previous run
|
||||
reset_log()
|
||||
{
|
||||
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# check switch argument value
|
||||
check_arg_value()
|
||||
{
|
||||
if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "simulate")) ]];then
|
||||
echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./NewExtInst_TOP.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
}
|
||||
|
||||
# check command line arguments
|
||||
check_args()
|
||||
{
|
||||
arg_count=$#
|
||||
if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
|
||||
usage
|
||||
fi
|
||||
while [[ "$#" -gt 0 ]]; do
|
||||
case $1 in
|
||||
-step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
|
||||
-lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
|
||||
-gen_bypass) b_gen_bypass=1 ;;
|
||||
-reset_run) b_reset_run=1 ;;
|
||||
-reset_log) b_reset_log=1 ;;
|
||||
-keep_index) b_keep_index=1 ;;
|
||||
-noclean_files) b_noclean_files=1 ;;
|
||||
-help|-h) ;;
|
||||
*) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
|
||||
esac
|
||||
shift
|
||||
done
|
||||
|
||||
# -reset_run is not applicable with other switches
|
||||
if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
|
||||
echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
# -reset_log is not applicable with other switches
|
||||
if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
|
||||
echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
# -keep_index is not applicable with other switches
|
||||
if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
|
||||
echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
# -noclean_files is not applicable with other switches
|
||||
if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
|
||||
echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
}
|
||||
|
||||
# script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: NewExtInst_TOP.sh [-help]\n\
|
||||
Usage: NewExtInst_TOP.sh [-step]\n\
|
||||
Usage: NewExtInst_TOP.sh [-lib_map_path]\n\
|
||||
Usage: NewExtInst_TOP.sh [-reset_run]\n\
|
||||
Usage: NewExtInst_TOP.sh [-reset_log]\n\
|
||||
Usage: NewExtInst_TOP.sh [-keep_index]\n\
|
||||
Usage: NewExtInst_TOP.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-step <name>] -- Execute specified step (compile, simulate)\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
|
||||
file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
|
||||
NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
|
||||
NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
|
||||
[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
|
||||
[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
|
||||
echo -e $msg
|
||||
exit 0
|
||||
}
|
||||
|
||||
# initialize globals
|
||||
step=""
|
||||
lib_map_path=""
|
||||
b_step=0
|
||||
b_lib_map_path=0
|
||||
b_gen_bypass=0
|
||||
b_reset_run=0
|
||||
b_reset_log=0
|
||||
b_keep_index=0
|
||||
b_noclean_files=0
|
||||
|
||||
# launch script
|
||||
run $*
|
||||
+50
@@ -0,0 +1,50 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2023.2 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and how to fetch design source file details
|
||||
# from the file_info.txt file.
|
||||
#
|
||||
# Generated by export_simulation on Fri May 15 15:32:22 CST 2026
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. Steps to run the generated simulation script
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./NewExtInst_TOP.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first calls the 'check_args' function, the purpose of which
|
||||
is to verify the generated script arguments and print error if incorrect switch
|
||||
is specified. The 'run' function then calls the 'setup' function, the purpose of
|
||||
which is to specify custom or initialization commands. The function also executes
|
||||
following sub-functions:-
|
||||
'reset_run' if -reset_run switch is specified.
|
||||
'reset_log' if -reset_log switch is specified.
|
||||
|
||||
The purpose of 'reset_run' function' is to delete the simulator generated design
|
||||
data from the previous run and the purpose of 'reset_log' function' is to delete
|
||||
the simulator generated log files.
|
||||
|
||||
The 'run' function then calls the 'init_lib' function, the purpose of which is to
|
||||
create design library mappings and directories. This function is called before the
|
||||
'compile' step. By default, if '-step' switch is specified with the script then the
|
||||
script will execute that specfic step, else it will execute all steps applicable
|
||||
for the target simulator.
|
||||
|
||||
For more information on the script, please type './NewExtInst_TOP.sh -help'
|
||||
|
||||
2. Design source file information
|
||||
|
||||
export_simulation generates a 'file_info.txt' file that contains design file information
|
||||
based on the compile order when export_simulation was executed from Vivado. The file
|
||||
contains information about the file name, type, library it is compiled into, whether
|
||||
it is part of the IP, associated library, file path information in a comma separated
|
||||
format. This file can be parsed to extract the required information for generating a
|
||||
custom script or can be read from verification test infra.
|
||||
|
||||
Executable
+107
@@ -0,0 +1,107 @@
|
||||
|
||||
#ifndef SPI_CON_H
|
||||
#define SPI_CON_H
|
||||
|
||||
|
||||
/****************** Include Files ********************/
|
||||
#include "xil_types.h"
|
||||
#include "xstatus.h"
|
||||
|
||||
#define SPI_CON_S00_AXI_SLV_REG0_OFFSET 0
|
||||
#define SPI_CON_S00_AXI_SLV_REG1_OFFSET 4
|
||||
#define SPI_CON_S00_AXI_SLV_REG2_OFFSET 8
|
||||
#define SPI_CON_S00_AXI_SLV_REG3_OFFSET 12
|
||||
#define SPI_CON_S00_AXI_SLV_REG4_OFFSET 16
|
||||
#define SPI_CON_S00_AXI_SLV_REG5_OFFSET 20
|
||||
#define SPI_CON_S00_AXI_SLV_REG6_OFFSET 24
|
||||
#define SPI_CON_S00_AXI_SLV_REG7_OFFSET 28
|
||||
#define SPI_CON_S00_AXI_SLV_REG8_OFFSET 32
|
||||
#define SPI_CON_S00_AXI_SLV_REG9_OFFSET 36
|
||||
#define SPI_CON_S00_AXI_SLV_REG10_OFFSET 40
|
||||
#define SPI_CON_S00_AXI_SLV_REG11_OFFSET 44
|
||||
#define SPI_CON_S00_AXI_SLV_REG12_OFFSET 48
|
||||
#define SPI_CON_S00_AXI_SLV_REG13_OFFSET 52
|
||||
#define SPI_CON_S00_AXI_SLV_REG14_OFFSET 56
|
||||
#define SPI_CON_S00_AXI_SLV_REG15_OFFSET 60
|
||||
#define SPI_CON_S00_AXI_SLV_REG16_OFFSET 64
|
||||
#define SPI_CON_S00_AXI_SLV_REG17_OFFSET 68
|
||||
#define SPI_CON_S00_AXI_SLV_REG18_OFFSET 72
|
||||
#define SPI_CON_S00_AXI_SLV_REG19_OFFSET 76
|
||||
#define SPI_CON_S00_AXI_SLV_REG20_OFFSET 80
|
||||
#define SPI_CON_S00_AXI_SLV_REG21_OFFSET 84
|
||||
#define SPI_CON_S00_AXI_SLV_REG22_OFFSET 88
|
||||
#define SPI_CON_S00_AXI_SLV_REG23_OFFSET 92
|
||||
#define SPI_CON_S00_AXI_SLV_REG24_OFFSET 96
|
||||
#define SPI_CON_S00_AXI_SLV_REG25_OFFSET 100
|
||||
#define SPI_CON_S00_AXI_SLV_REG26_OFFSET 104
|
||||
#define SPI_CON_S00_AXI_SLV_REG27_OFFSET 108
|
||||
#define SPI_CON_S00_AXI_SLV_REG28_OFFSET 112
|
||||
#define SPI_CON_S00_AXI_SLV_REG29_OFFSET 116
|
||||
#define SPI_CON_S00_AXI_SLV_REG30_OFFSET 120
|
||||
#define SPI_CON_S00_AXI_SLV_REG31_OFFSET 124
|
||||
|
||||
|
||||
/**************************** Type Definitions *****************************/
|
||||
/**
|
||||
*
|
||||
* Write a value to a SPI_CON register. A 32 bit write is performed.
|
||||
* If the component is implemented in a smaller width, only the least
|
||||
* significant data is written.
|
||||
*
|
||||
* @param BaseAddress is the base address of the SPI_CONdevice.
|
||||
* @param RegOffset is the register offset from the base to write to.
|
||||
* @param Data is the data written to the register.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void SPI_CON_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
|
||||
*
|
||||
*/
|
||||
#define SPI_CON_mWriteReg(BaseAddress, RegOffset, Data) \
|
||||
Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
|
||||
|
||||
/**
|
||||
*
|
||||
* Read a value from a SPI_CON register. A 32 bit read is performed.
|
||||
* If the component is implemented in a smaller width, only the least
|
||||
* significant data is read from the register. The most significant data
|
||||
* will be read as 0.
|
||||
*
|
||||
* @param BaseAddress is the base address of the SPI_CON device.
|
||||
* @param RegOffset is the register offset from the base to write to.
|
||||
*
|
||||
* @return Data is the data from the register.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* u32 SPI_CON_mReadReg(u32 BaseAddress, unsigned RegOffset)
|
||||
*
|
||||
*/
|
||||
#define SPI_CON_mReadReg(BaseAddress, RegOffset) \
|
||||
Xil_In32((BaseAddress) + (RegOffset))
|
||||
|
||||
/************************** Function Prototypes ****************************/
|
||||
/**
|
||||
*
|
||||
* Run a self-test on the driver/device. Note this may be a destructive test if
|
||||
* resets of the device are performed.
|
||||
*
|
||||
* If the hardware system is not built correctly, this function may never
|
||||
* return to the caller.
|
||||
*
|
||||
* @param baseaddr_p is the base address of the SPI_CON instance to be worked on.
|
||||
*
|
||||
* @return
|
||||
*
|
||||
* - XST_SUCCESS if all self-test code passed
|
||||
* - XST_FAILURE if any self-test code failed
|
||||
*
|
||||
* @note Caching must be turned off for this function to work.
|
||||
* @note Self test may fail if data memory and device are not on the same bus.
|
||||
*
|
||||
*/
|
||||
XStatus SPI_CON_Reg_SelfTest(void * baseaddr_p);
|
||||
|
||||
#endif // SPI_CON_H
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
|
||||
|
||||
OPTION psf_version = 2.1;
|
||||
|
||||
BEGIN DRIVER SPI_Con
|
||||
OPTION supported_peripherals = (SPI_Con);
|
||||
OPTION copyfiles = all;
|
||||
OPTION VERSION = 1.0;
|
||||
OPTION NAME = SPI_Con;
|
||||
END DRIVER
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
|
||||
|
||||
proc generate {drv_handle} {
|
||||
xdefine_include_file $drv_handle "xparameters.h" "SPI_Con" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
|
||||
}
|
||||
+39
@@ -0,0 +1,39 @@
|
||||
axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
xpm_cdc.sv,systemverilog,xpm,../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
xpm_memory.sv,systemverilog,xpm,../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_15,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/5753/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_17,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/sim/NewExtInst_TOP_processing_system7_0_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_clk_wiz_0_0_clk_wiz.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_clk_wiz.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_clk_wiz_0_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_14,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_proc_sys_reset_0_0.vhd,vhdl,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/sim/NewExtInst_TOP_proc_sys_reset_0_0.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
SPI_Con_v1_0_S00_AXI.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
SPI_Con_v1_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_SPI_Con_0_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/sim/NewExtInst_TOP_SPI_Con_0_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_SPI_Con_0_1.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/sim/NewExtInst_TOP_SPI_Con_0_1.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_SPI_Con_0_2.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/sim/NewExtInst_TOP_SPI_Con_0_2.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
generic_baseblocks_v2_1_vl_rfs.v,verilog,generic_baseblocks_v2_1_1,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_register_slice_v2_1_vl_rfs.v,verilog,axi_register_slice_v2_1_29,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_9,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/simulation/fifo_generator_vlog_beh.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_9,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_9,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_data_fifo_v2_1_vl_rfs.v,verilog,axi_data_fifo_v2_1_28,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_crossbar_v2_1_vl_rfs.v,verilog,axi_crossbar_v2_1_30,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_xbar_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/sim/NewExtInst_TOP_xbar_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd,vhdl,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/sim/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_29,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/sim/NewExtInst_TOP_auto_pc_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/sim/NewExtInst_TOP.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
+84
@@ -0,0 +1,84 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/libps7.dll
Executable
+47
@@ -0,0 +1,47 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
Executable
+47
@@ -0,0 +1,47 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/activehdl/ps7_init.h
Executable
+117
@@ -0,0 +1,117 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158730
|
||||
#define QSPI_FREQ 142857132
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 100000000
|
||||
#define UART_FREQ 100000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 25000000
|
||||
#define FPGA1_FREQ 50000000
|
||||
#define FPGA2_FREQ 100000000
|
||||
#define FPGA3_FREQ 200000000
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
+125613
File diff suppressed because it is too large
Load Diff
+781
@@ -0,0 +1,781 @@
|
||||
proc ps7_pll_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000701
|
||||
mask_write 0XF8000150 0x00003F33 0x00000A03
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A02
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00500800
|
||||
mask_write 0XF8000180 0x03F03F30 0x00400500
|
||||
mask_write 0XF8000190 0x03F03F30 0x00200500
|
||||
mask_write 0XF80001A0 0x03F03F30 0x00100500
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_3_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x0007FFFF 0x00001082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
|
||||
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00000003 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x0003F03F 0x0003C008
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x00010000 0x00000000
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x00000200 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000080
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000703FF 0x000003FF
|
||||
mask_write 0XF800620C 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006210 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006214 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF5 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000260
|
||||
mask_write 0XF8000B70 0x00000001 0x00000001
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003F01 0x00001601
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000724 0x00003F01 0x00001601
|
||||
mask_write 0XF8000728 0x00003FFF 0x00001680
|
||||
mask_write 0XF800072C 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000730 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000734 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000738 0x00003FFF 0x00001680
|
||||
mask_write 0XF800073C 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001202
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001203
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001203
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001203
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B8 0x00003F01 0x00001201
|
||||
mask_write 0XF80007BC 0x00003F01 0x00001201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000012E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000012E1
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F002E
|
||||
mask_write 0XF8000834 0x003F003F 0x00090000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x000003FF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_3_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000701
|
||||
mask_write 0XF8000150 0x00003F33 0x00000A03
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A02
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00500800
|
||||
mask_write 0XF8000180 0x03F03F30 0x00400500
|
||||
mask_write 0XF8000190 0x03F03F30 0x00200500
|
||||
mask_write 0XF80001A0 0x03F03F30 0x00100500
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_2_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000080
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000260
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003F01 0x00001601
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000724 0x00003F01 0x00001601
|
||||
mask_write 0XF8000728 0x00003FFF 0x00001680
|
||||
mask_write 0XF800072C 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000730 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000734 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000738 0x00003FFF 0x00001680
|
||||
mask_write 0XF800073C 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001202
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001203
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001203
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001203
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B8 0x00003F01 0x00001201
|
||||
mask_write 0XF80007BC 0x00003F01 0x00001201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000012E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000012E1
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F002E
|
||||
mask_write 0XF8000834 0x003F003F 0x00090000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x00000FFF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_2_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000701
|
||||
mask_write 0XF8000150 0x00003F33 0x00000A03
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A02
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00500800
|
||||
mask_write 0XF8000180 0x03F03F30 0x00400500
|
||||
mask_write 0XF8000190 0x03F03F30 0x00200500
|
||||
mask_write 0XF80001A0 0x03F03F30 0x00100500
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_1_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000080
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x000073FF 0x00000260
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003F01 0x00001601
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000724 0x00003F01 0x00001601
|
||||
mask_write 0XF8000728 0x00003FFF 0x00001680
|
||||
mask_write 0XF800072C 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000730 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000734 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000738 0x00003FFF 0x00001680
|
||||
mask_write 0XF800073C 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001202
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001203
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001203
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001203
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B8 0x00003F01 0x00001201
|
||||
mask_write 0XF80007BC 0x00003F01 0x00001201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000012E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000012E1
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F002E
|
||||
mask_write 0XF8000834 0x003F003F 0x00090000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x00000FFF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_1_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
set PCW_SILICON_VER_1_0 "0x0"
|
||||
set PCW_SILICON_VER_2_0 "0x1"
|
||||
set PCW_SILICON_VER_3_0 "0x2"
|
||||
set APU_FREQ 666666666
|
||||
|
||||
|
||||
|
||||
proc mask_poll { addr mask } {
|
||||
set count 1
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
while { $maskedval == 0 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
set count [ expr { $count + 1 } ]
|
||||
if { $count == 100000000 } {
|
||||
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
|
||||
break
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
proc mask_delay { addr val } {
|
||||
set delay [ get_number_of_cycles_for_delay $val ]
|
||||
perf_reset_and_start_timer
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
while { $maskedval == 1 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
}
|
||||
perf_reset_clock
|
||||
}
|
||||
|
||||
proc ps_version { } {
|
||||
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
|
||||
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
|
||||
return $mask_sil_ver;
|
||||
}
|
||||
|
||||
proc ps7_post_config {} {
|
||||
set saved_mode [configparams force-mem-accesses]
|
||||
configparams force-mem-accesses 1
|
||||
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_post_config_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_post_config_2_0
|
||||
} else {
|
||||
ps7_post_config_3_0
|
||||
}
|
||||
configparams force-mem-accesses $saved_mode
|
||||
}
|
||||
|
||||
proc ps7_debug {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_debug_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_debug_2_0
|
||||
} else {
|
||||
ps7_debug_3_0
|
||||
}
|
||||
}
|
||||
proc ps7_init {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_mio_init_data_1_0
|
||||
ps7_pll_init_data_1_0
|
||||
ps7_clock_init_data_1_0
|
||||
ps7_ddr_init_data_1_0
|
||||
ps7_peripherals_init_data_1_0
|
||||
#puts "PCW Silicon Version : 1.0"
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_mio_init_data_2_0
|
||||
ps7_pll_init_data_2_0
|
||||
ps7_clock_init_data_2_0
|
||||
ps7_ddr_init_data_2_0
|
||||
ps7_peripherals_init_data_2_0
|
||||
#puts "PCW Silicon Version : 2.0"
|
||||
} else {
|
||||
ps7_mio_init_data_3_0
|
||||
ps7_pll_init_data_3_0
|
||||
ps7_clock_init_data_3_0
|
||||
ps7_ddr_init_data_3_0
|
||||
ps7_peripherals_init_data_3_0
|
||||
#puts "PCW Silicon Version : 3.0"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# For delay calculation using global timer
|
||||
|
||||
# start timer
|
||||
proc perf_start_clock { } {
|
||||
|
||||
#writing SCU_GLOBAL_TIMER_CONTROL register
|
||||
|
||||
mask_write 0xF8F00208 0x00000109 0x00000009
|
||||
}
|
||||
|
||||
# stop timer and reset timer count regs
|
||||
proc perf_reset_clock { } {
|
||||
perf_disable_clock
|
||||
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
|
||||
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
# Compute mask for given delay in miliseconds
|
||||
proc get_number_of_cycles_for_delay { delay } {
|
||||
|
||||
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
|
||||
variable APU_FREQ
|
||||
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
|
||||
}
|
||||
|
||||
|
||||
# stop timer
|
||||
proc perf_disable_clock {} {
|
||||
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
proc perf_reset_and_start_timer {} {
|
||||
perf_reset_clock
|
||||
perf_start_clock
|
||||
}
|
||||
|
||||
|
||||
+131
@@ -0,0 +1,131 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010-2020 <Xilinx Inc.>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, see <http://www.gnu.org/licenses/>
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init_gpl.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158730
|
||||
#define QSPI_FREQ 142857132
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 100000000
|
||||
#define UART_FREQ 100000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 25000000
|
||||
#define FPGA1_FREQ 50000000
|
||||
#define FPGA2_FREQ 100000000
|
||||
#define FPGA3_FREQ 200000000
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
+106
@@ -0,0 +1,106 @@
|
||||
/*
|
||||
* Xilinx SystemC/TLM-2.0 Zynq Wrapper.
|
||||
*
|
||||
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
|
||||
*
|
||||
* Copyright (c) 2016, Xilinx Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define SC_INCLUDE_DYNAMIC_PROCESSES
|
||||
|
||||
#include <inttypes.h>
|
||||
|
||||
#include "tlm_utils/simple_initiator_socket.h"
|
||||
#include "tlm_utils/simple_target_socket.h"
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace std;
|
||||
|
||||
#include "xilinx-zynq.h"
|
||||
#include <sys/types.h>
|
||||
|
||||
//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr,
|
||||
// Iremoteport_tlm_sync *sync)
|
||||
// : remoteport_tlm(name, -1, sk_descr, sync),
|
||||
xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr)
|
||||
: remoteport_tlm(name, -1, sk_descr),
|
||||
rp_m_axi_gp0("rp_m_axi_gp0"),
|
||||
rp_m_axi_gp1("rp_m_axi_gp1"),
|
||||
rp_s_axi_gp0("rp_s_axi_gp0"),
|
||||
rp_s_axi_gp1("rp_s_axi_gp1"),
|
||||
rp_s_axi_hp0("rp_s_axi_hp0"),
|
||||
rp_s_axi_hp1("rp_s_axi_hp1"),
|
||||
rp_s_axi_hp2("rp_s_axi_hp2"),
|
||||
rp_s_axi_hp3("rp_s_axi_hp3"),
|
||||
rp_s_axi_acp("rp_s_axi_acp"),
|
||||
rp_wires_in("wires_in", 20, 0),
|
||||
rp_wires_out("wires_out", 0, 17),
|
||||
rp_irq_out("irq_out", 0, 28),
|
||||
pl2ps_irq("pl2ps_irq", 20),
|
||||
ps2pl_irq("ps2pl_irq", 28),
|
||||
ps2pl_rst("ps2pl_rst", 17)
|
||||
{
|
||||
int i;
|
||||
|
||||
m_axi_gp[0] = &rp_m_axi_gp0.sk;
|
||||
m_axi_gp[1] = &rp_m_axi_gp1.sk;
|
||||
|
||||
s_axi_gp[0] = &rp_s_axi_gp0.sk;
|
||||
s_axi_gp[1] = &rp_s_axi_gp1.sk;
|
||||
|
||||
s_axi_hp[0] = &rp_s_axi_hp0.sk;
|
||||
s_axi_hp[1] = &rp_s_axi_hp1.sk;
|
||||
s_axi_hp[2] = &rp_s_axi_hp2.sk;
|
||||
s_axi_hp[3] = &rp_s_axi_hp3.sk;
|
||||
s_axi_acp = &rp_s_axi_acp.sk;
|
||||
|
||||
/* PL to PS Interrupt signals. */
|
||||
for (i = 0; i < 20; i++) {
|
||||
rp_wires_in.wires_in[i](pl2ps_irq[i]);
|
||||
}
|
||||
|
||||
/* PS to PL Interrupt signals. */
|
||||
for (i = 0; i < 28; i++) {
|
||||
rp_irq_out.wires_out[i](ps2pl_irq[i]);
|
||||
}
|
||||
|
||||
/* PS to PL resets. */
|
||||
for (i = 0; i < 17; i++) {
|
||||
rp_wires_out.wires_out[i](ps2pl_rst[i]);
|
||||
}
|
||||
|
||||
register_dev(0, &rp_s_axi_gp0);
|
||||
register_dev(1, &rp_s_axi_gp1);
|
||||
|
||||
register_dev(2, &rp_s_axi_hp0);
|
||||
register_dev(3, &rp_s_axi_hp1);
|
||||
register_dev(4, &rp_s_axi_hp2);
|
||||
register_dev(5, &rp_s_axi_hp3);
|
||||
|
||||
register_dev(6, &rp_s_axi_acp);
|
||||
|
||||
register_dev(7, &rp_m_axi_gp0);
|
||||
register_dev(8, &rp_m_axi_gp1);
|
||||
register_dev(9, &rp_wires_in);
|
||||
register_dev(10, &rp_wires_out);
|
||||
register_dev(11, &rp_irq_out);
|
||||
}
|
||||
Executable
+26
@@ -0,0 +1,26 @@
|
||||
COMPILER=
|
||||
ARCHIVER=
|
||||
CP=cp
|
||||
COMPILER_FLAGS=
|
||||
EXTRA_COMPILER_FLAGS=
|
||||
LIB=libxil.a
|
||||
|
||||
RELEASEDIR=../../../lib
|
||||
INCLUDEDIR=../../../include
|
||||
INCLUDES=-I./. -I${INCLUDEDIR}
|
||||
|
||||
INCLUDEFILES=*.h
|
||||
LIBSOURCES=*.c
|
||||
OUTS = *.o
|
||||
|
||||
libs:
|
||||
echo "Compiling SPI_Con..."
|
||||
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
|
||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
||||
make clean
|
||||
|
||||
include:
|
||||
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
|
||||
|
||||
clean:
|
||||
rm -rf ${OUTS}
|
||||
+272
@@ -0,0 +1,272 @@
|
||||
{
|
||||
"graphjs": {
|
||||
"version": "1.0",
|
||||
"keys": [
|
||||
{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
"type": "int",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VT",
|
||||
"name": "vert_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BA",
|
||||
"name": "base_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HA",
|
||||
"name": "high_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BP",
|
||||
"name": "base_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HP",
|
||||
"name": "high_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MX",
|
||||
"name": "master_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MI",
|
||||
"name": "master_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MS",
|
||||
"name": "master_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MV",
|
||||
"name": "master_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SX",
|
||||
"name": "slave_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SI",
|
||||
"name": "slave_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MM",
|
||||
"name": "slave_memmap",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SS",
|
||||
"name": "slave_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SV",
|
||||
"name": "slave_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TM",
|
||||
"name": "memory_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TU",
|
||||
"name": "usage_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "LT",
|
||||
"name": "lock_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BT",
|
||||
"name": "boot_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
|
||||
"type": "int",
|
||||
"for": "edge"
|
||||
}
|
||||
],
|
||||
"vertice_type_order": [
|
||||
{
|
||||
"abrv": "BC",
|
||||
"desc": "Block Container"
|
||||
},
|
||||
{
|
||||
"abrv": "PR",
|
||||
"desc": "Parital Reference"
|
||||
},
|
||||
{
|
||||
"abrv": "VR",
|
||||
"desc": "Variant"
|
||||
},
|
||||
{
|
||||
"abrv": "PM",
|
||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
},
|
||||
{
|
||||
"abrv": "AC",
|
||||
"desc": "Assignment Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "ACE",
|
||||
"desc": "Excluded Assign Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "APX",
|
||||
"desc": "Boundary Aperture"
|
||||
},
|
||||
{
|
||||
"abrv": "CIP",
|
||||
"desc": "High level Processing System"
|
||||
}
|
||||
],
|
||||
"vertices": {
|
||||
"V0": {
|
||||
"VM": "NewExtInst_TOP",
|
||||
"VT": "BC"
|
||||
},
|
||||
"V1": {
|
||||
"VH": "2",
|
||||
"VM": "NewExtInst_TOP",
|
||||
"VT": "VR"
|
||||
},
|
||||
"V2": {
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
},
|
||||
"V3": {
|
||||
"VT": "AC",
|
||||
"BA": "0x43C00000",
|
||||
"HA": "0x43C0FFFF",
|
||||
"BP": "C_S00_AXI_BASEADDR",
|
||||
"HP": "C_S00_AXI_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_SPI_Con_0_S00_AXI_reg",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/SPI_Con_0",
|
||||
"SI": "S00_AXI",
|
||||
"SS": "S00_AXI_reg",
|
||||
"SV": "xilinx.com:user:SPI_Con:1.0",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
},
|
||||
"V4": {
|
||||
"VT": "AC",
|
||||
"BA": "0x43C10000",
|
||||
"HA": "0x43C1FFFF",
|
||||
"BP": "C_S00_AXI_BASEADDR",
|
||||
"HP": "C_S00_AXI_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_SPI_Con_1_S00_AXI_reg",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/SPI_Con_1",
|
||||
"SI": "S00_AXI",
|
||||
"SS": "S00_AXI_reg",
|
||||
"SV": "xilinx.com:user:SPI_Con:1.0",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
},
|
||||
"V5": {
|
||||
"VT": "AC",
|
||||
"BA": "0x43C20000",
|
||||
"HA": "0x43C2FFFF",
|
||||
"BP": "C_S00_AXI_BASEADDR",
|
||||
"HP": "C_S00_AXI_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_SPI_Con_2_S00_AXI_reg",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/SPI_Con_2",
|
||||
"SI": "S00_AXI",
|
||||
"SS": "S00_AXI_reg",
|
||||
"SV": "xilinx.com:user:SPI_Con:1.0",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
},
|
||||
{
|
||||
"src": "V3",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V4",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V5",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
+287
@@ -0,0 +1,287 @@
|
||||
#!/usr/bin/env bash
|
||||
#**********************************************************************************************************
|
||||
# Vivado (TM) v2023.2 (64-bit)
|
||||
#
|
||||
# Script generated by Vivado on Fri May 15 15:32:22 CST 2026
|
||||
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
|
||||
#
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
# Filename : NewExtInst_TOP.sh
|
||||
# Simulator : Siemens ModelSim Simulator
|
||||
# Description : Simulation script generated by export_simulation Tcl command
|
||||
# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
|
||||
# design. The script will copy the library mapping file from the compiled library directory,
|
||||
# create design library directories and library mappings in the mapping file.
|
||||
#
|
||||
# Usage : NewExtInst_TOP.sh
|
||||
# NewExtInst_TOP.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
|
||||
# NewExtInst_TOP.sh [-reset_run]
|
||||
# NewExtInst_TOP.sh [-reset_log]
|
||||
# NewExtInst_TOP.sh [-help]
|
||||
#
|
||||
# * The -noclean_files switch is deprecated and will not peform any function (by default, the
|
||||
# simulator generated files will not be removed unless -reset_run switch is used)
|
||||
#
|
||||
# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library
|
||||
# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
|
||||
# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
|
||||
# switch with the directory path where the library is created while generating the script
|
||||
# with export_simulation.
|
||||
#
|
||||
# Alternatively, you can set the library path by setting the following project property:-
|
||||
#
|
||||
# set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
|
||||
#
|
||||
# You can also point to the simulation library by either setting the 'lib_map_path' global
|
||||
# variable in this script or specify it with the '-lib_map_path' switch while executing this
|
||||
# script (type 'NewExtInst_TOP.sh -help' for more information).
|
||||
#
|
||||
# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
|
||||
# generated script, but if design is targetted for system simulation containing SystemC/C++/C
|
||||
# sources, then the library path MUST be specified upfront when calling export_simulation.
|
||||
#
|
||||
# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#**********************************************************************************************************
|
||||
|
||||
# catch pipeline exit status
|
||||
set -Eeuo pipefail
|
||||
|
||||
# script info
|
||||
echo -e "NewExtInst_TOP.sh - Script generated by export_simulation (Vivado v2023.2 (64-bit)-id)\n"
|
||||
|
||||
# main steps
|
||||
run()
|
||||
{
|
||||
check_args $*
|
||||
setup
|
||||
if [[ ($b_step == 1) ]]; then
|
||||
case $step in
|
||||
"compile" )
|
||||
init_lib
|
||||
compile
|
||||
;;
|
||||
"simulate" )
|
||||
simulate
|
||||
;;
|
||||
* )
|
||||
echo -e "ERROR: Invalid or missing step '$step' (type \"./NewExtInst_TOP.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
esac
|
||||
else
|
||||
init_lib
|
||||
compile
|
||||
simulate
|
||||
fi
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
vsim -c -do "do {simulate.do}" -l simulate.log
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
# delete previous files for a clean rerun
|
||||
if [[ ($b_reset_run == 1) ]]; then
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
fi
|
||||
|
||||
# delete previous log files
|
||||
if [[ ($b_reset_log == 1) ]]; then
|
||||
reset_log
|
||||
echo -e "INFO: Simulation run log files deleted.\n"
|
||||
exit 0
|
||||
fi
|
||||
|
||||
# add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# simulator index file/library directory processing
|
||||
init_lib()
|
||||
{
|
||||
if [[ ($b_keep_index == 1) ]]; then
|
||||
# keep previous simulator index file
|
||||
true
|
||||
else
|
||||
# copy simulator index file to current directory
|
||||
copy_setup_file
|
||||
fi
|
||||
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
ref_lib_dir=$lib_map_path
|
||||
fi
|
||||
|
||||
if [[ ($b_keep_index == 1) ]]; then
|
||||
# do not recreate design library directories
|
||||
true
|
||||
else
|
||||
# create design library directories
|
||||
create_lib_dir
|
||||
fi
|
||||
}
|
||||
|
||||
# copy modelsim.ini file
|
||||
copy_setup_file()
|
||||
{
|
||||
file="modelsim.ini"
|
||||
if [[ ($lib_map_path == "") ]]; then
|
||||
lib_map_path="/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/compile_simlib/modelsim"
|
||||
fi
|
||||
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
if [[ -e $src_file ]]; then
|
||||
cp $src_file .
|
||||
fi
|
||||
fi
|
||||
}
|
||||
|
||||
# create design library directory
|
||||
create_lib_dir()
|
||||
{
|
||||
lib_dir="modelsim_lib"
|
||||
if [[ -e $lib_dir ]]; then
|
||||
rm -rf $lib_dir
|
||||
fi
|
||||
mkdir $lib_dir
|
||||
}
|
||||
|
||||
# delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# delete generated log files from the previous run
|
||||
reset_log()
|
||||
{
|
||||
files_to_remove=(compile.log elaborate.log simulate.log)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# check switch argument value
|
||||
check_arg_value()
|
||||
{
|
||||
if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "simulate")) ]];then
|
||||
echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./NewExtInst_TOP.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
}
|
||||
|
||||
# check command line arguments
|
||||
check_args()
|
||||
{
|
||||
arg_count=$#
|
||||
if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
|
||||
usage
|
||||
fi
|
||||
while [[ "$#" -gt 0 ]]; do
|
||||
case $1 in
|
||||
-step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
|
||||
-lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
|
||||
-gen_bypass) b_gen_bypass=1 ;;
|
||||
-reset_run) b_reset_run=1 ;;
|
||||
-reset_log) b_reset_log=1 ;;
|
||||
-keep_index) b_keep_index=1 ;;
|
||||
-noclean_files) b_noclean_files=1 ;;
|
||||
-help|-h) ;;
|
||||
*) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
|
||||
esac
|
||||
shift
|
||||
done
|
||||
|
||||
# -reset_run is not applicable with other switches
|
||||
if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
|
||||
echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
# -reset_log is not applicable with other switches
|
||||
if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
|
||||
echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
# -keep_index is not applicable with other switches
|
||||
if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
|
||||
echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
# -noclean_files is not applicable with other switches
|
||||
if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
|
||||
echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
}
|
||||
|
||||
# script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: NewExtInst_TOP.sh [-help]\n\
|
||||
Usage: NewExtInst_TOP.sh [-step]\n\
|
||||
Usage: NewExtInst_TOP.sh [-lib_map_path]\n\
|
||||
Usage: NewExtInst_TOP.sh [-reset_run]\n\
|
||||
Usage: NewExtInst_TOP.sh [-reset_log]\n\
|
||||
Usage: NewExtInst_TOP.sh [-keep_index]\n\
|
||||
Usage: NewExtInst_TOP.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-step <name>] -- Execute specified step (compile, simulate)\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
|
||||
file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
|
||||
NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
|
||||
NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
|
||||
[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
|
||||
[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
|
||||
echo -e $msg
|
||||
exit 0
|
||||
}
|
||||
|
||||
# initialize globals
|
||||
step=""
|
||||
lib_map_path=""
|
||||
b_step=0
|
||||
b_lib_map_path=0
|
||||
b_gen_bypass=0
|
||||
b_reset_run=0
|
||||
b_reset_log=0
|
||||
b_keep_index=0
|
||||
b_noclean_files=0
|
||||
|
||||
# launch script
|
||||
run $*
|
||||
+50
@@ -0,0 +1,50 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2023.2 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and how to fetch design source file details
|
||||
# from the file_info.txt file.
|
||||
#
|
||||
# Generated by export_simulation on Fri May 15 15:32:22 CST 2026
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. Steps to run the generated simulation script
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./NewExtInst_TOP.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first calls the 'check_args' function, the purpose of which
|
||||
is to verify the generated script arguments and print error if incorrect switch
|
||||
is specified. The 'run' function then calls the 'setup' function, the purpose of
|
||||
which is to specify custom or initialization commands. The function also executes
|
||||
following sub-functions:-
|
||||
'reset_run' if -reset_run switch is specified.
|
||||
'reset_log' if -reset_log switch is specified.
|
||||
|
||||
The purpose of 'reset_run' function' is to delete the simulator generated design
|
||||
data from the previous run and the purpose of 'reset_log' function' is to delete
|
||||
the simulator generated log files.
|
||||
|
||||
The 'run' function then calls the 'init_lib' function, the purpose of which is to
|
||||
create design library mappings and directories. This function is called before the
|
||||
'compile' step. By default, if '-step' switch is specified with the script then the
|
||||
script will execute that specfic step, else it will execute all steps applicable
|
||||
for the target simulator.
|
||||
|
||||
For more information on the script, please type './NewExtInst_TOP.sh -help'
|
||||
|
||||
2. Design source file information
|
||||
|
||||
export_simulation generates a 'file_info.txt' file that contains design file information
|
||||
based on the compile order when export_simulation was executed from Vivado. The file
|
||||
contains information about the file name, type, library it is compiled into, whether
|
||||
it is part of the IP, associated library, file path information in a comma separated
|
||||
format. This file can be parsed to extract the required information for generating a
|
||||
custom script or can be read from verification test infra.
|
||||
|
||||
Executable
+107
@@ -0,0 +1,107 @@
|
||||
|
||||
#ifndef SPI_CON_H
|
||||
#define SPI_CON_H
|
||||
|
||||
|
||||
/****************** Include Files ********************/
|
||||
#include "xil_types.h"
|
||||
#include "xstatus.h"
|
||||
|
||||
#define SPI_CON_S00_AXI_SLV_REG0_OFFSET 0
|
||||
#define SPI_CON_S00_AXI_SLV_REG1_OFFSET 4
|
||||
#define SPI_CON_S00_AXI_SLV_REG2_OFFSET 8
|
||||
#define SPI_CON_S00_AXI_SLV_REG3_OFFSET 12
|
||||
#define SPI_CON_S00_AXI_SLV_REG4_OFFSET 16
|
||||
#define SPI_CON_S00_AXI_SLV_REG5_OFFSET 20
|
||||
#define SPI_CON_S00_AXI_SLV_REG6_OFFSET 24
|
||||
#define SPI_CON_S00_AXI_SLV_REG7_OFFSET 28
|
||||
#define SPI_CON_S00_AXI_SLV_REG8_OFFSET 32
|
||||
#define SPI_CON_S00_AXI_SLV_REG9_OFFSET 36
|
||||
#define SPI_CON_S00_AXI_SLV_REG10_OFFSET 40
|
||||
#define SPI_CON_S00_AXI_SLV_REG11_OFFSET 44
|
||||
#define SPI_CON_S00_AXI_SLV_REG12_OFFSET 48
|
||||
#define SPI_CON_S00_AXI_SLV_REG13_OFFSET 52
|
||||
#define SPI_CON_S00_AXI_SLV_REG14_OFFSET 56
|
||||
#define SPI_CON_S00_AXI_SLV_REG15_OFFSET 60
|
||||
#define SPI_CON_S00_AXI_SLV_REG16_OFFSET 64
|
||||
#define SPI_CON_S00_AXI_SLV_REG17_OFFSET 68
|
||||
#define SPI_CON_S00_AXI_SLV_REG18_OFFSET 72
|
||||
#define SPI_CON_S00_AXI_SLV_REG19_OFFSET 76
|
||||
#define SPI_CON_S00_AXI_SLV_REG20_OFFSET 80
|
||||
#define SPI_CON_S00_AXI_SLV_REG21_OFFSET 84
|
||||
#define SPI_CON_S00_AXI_SLV_REG22_OFFSET 88
|
||||
#define SPI_CON_S00_AXI_SLV_REG23_OFFSET 92
|
||||
#define SPI_CON_S00_AXI_SLV_REG24_OFFSET 96
|
||||
#define SPI_CON_S00_AXI_SLV_REG25_OFFSET 100
|
||||
#define SPI_CON_S00_AXI_SLV_REG26_OFFSET 104
|
||||
#define SPI_CON_S00_AXI_SLV_REG27_OFFSET 108
|
||||
#define SPI_CON_S00_AXI_SLV_REG28_OFFSET 112
|
||||
#define SPI_CON_S00_AXI_SLV_REG29_OFFSET 116
|
||||
#define SPI_CON_S00_AXI_SLV_REG30_OFFSET 120
|
||||
#define SPI_CON_S00_AXI_SLV_REG31_OFFSET 124
|
||||
|
||||
|
||||
/**************************** Type Definitions *****************************/
|
||||
/**
|
||||
*
|
||||
* Write a value to a SPI_CON register. A 32 bit write is performed.
|
||||
* If the component is implemented in a smaller width, only the least
|
||||
* significant data is written.
|
||||
*
|
||||
* @param BaseAddress is the base address of the SPI_CONdevice.
|
||||
* @param RegOffset is the register offset from the base to write to.
|
||||
* @param Data is the data written to the register.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void SPI_CON_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
|
||||
*
|
||||
*/
|
||||
#define SPI_CON_mWriteReg(BaseAddress, RegOffset, Data) \
|
||||
Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
|
||||
|
||||
/**
|
||||
*
|
||||
* Read a value from a SPI_CON register. A 32 bit read is performed.
|
||||
* If the component is implemented in a smaller width, only the least
|
||||
* significant data is read from the register. The most significant data
|
||||
* will be read as 0.
|
||||
*
|
||||
* @param BaseAddress is the base address of the SPI_CON device.
|
||||
* @param RegOffset is the register offset from the base to write to.
|
||||
*
|
||||
* @return Data is the data from the register.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* u32 SPI_CON_mReadReg(u32 BaseAddress, unsigned RegOffset)
|
||||
*
|
||||
*/
|
||||
#define SPI_CON_mReadReg(BaseAddress, RegOffset) \
|
||||
Xil_In32((BaseAddress) + (RegOffset))
|
||||
|
||||
/************************** Function Prototypes ****************************/
|
||||
/**
|
||||
*
|
||||
* Run a self-test on the driver/device. Note this may be a destructive test if
|
||||
* resets of the device are performed.
|
||||
*
|
||||
* If the hardware system is not built correctly, this function may never
|
||||
* return to the caller.
|
||||
*
|
||||
* @param baseaddr_p is the base address of the SPI_CON instance to be worked on.
|
||||
*
|
||||
* @return
|
||||
*
|
||||
* - XST_SUCCESS if all self-test code passed
|
||||
* - XST_FAILURE if any self-test code failed
|
||||
*
|
||||
* @note Caching must be turned off for this function to work.
|
||||
* @note Self test may fail if data memory and device are not on the same bus.
|
||||
*
|
||||
*/
|
||||
XStatus SPI_CON_Reg_SelfTest(void * baseaddr_p);
|
||||
|
||||
#endif // SPI_CON_H
|
||||
2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/SPI_Con.mdd
Executable
+10
@@ -0,0 +1,10 @@
|
||||
|
||||
|
||||
OPTION psf_version = 2.1;
|
||||
|
||||
BEGIN DRIVER SPI_Con
|
||||
OPTION supported_peripherals = (SPI_Con);
|
||||
OPTION copyfiles = all;
|
||||
OPTION VERSION = 1.0;
|
||||
OPTION NAME = SPI_Con;
|
||||
END DRIVER
|
||||
2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/sim_scripts/NewExtInst_TOP/modelsim/SPI_Con.tcl
Executable
+5
@@ -0,0 +1,5 @@
|
||||
|
||||
|
||||
proc generate {drv_handle} {
|
||||
xdefine_include_file $drv_handle "xparameters.h" "SPI_Con" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
|
||||
}
|
||||
+39
@@ -0,0 +1,39 @@
|
||||
axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
xpm_cdc.sv,systemverilog,xpm,../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
xpm_memory.sv,systemverilog,xpm,../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_15,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/5753/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_17,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/sim/NewExtInst_TOP_processing_system7_0_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_clk_wiz_0_0_clk_wiz.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_clk_wiz.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_clk_wiz_0_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_14,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_proc_sys_reset_0_0.vhd,vhdl,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/sim/NewExtInst_TOP_proc_sys_reset_0_0.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
SPI_Con_v1_0_S00_AXI.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
SPI_Con_v1_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_SPI_Con_0_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/sim/NewExtInst_TOP_SPI_Con_0_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_SPI_Con_0_1.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/sim/NewExtInst_TOP_SPI_Con_0_1.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_SPI_Con_0_2.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/sim/NewExtInst_TOP_SPI_Con_0_2.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
generic_baseblocks_v2_1_vl_rfs.v,verilog,generic_baseblocks_v2_1_1,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_register_slice_v2_1_vl_rfs.v,verilog,axi_register_slice_v2_1_29,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_9,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/simulation/fifo_generator_vlog_beh.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_9,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_9,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_data_fifo_v2_1_vl_rfs.v,verilog,axi_data_fifo_v2_1_28,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_crossbar_v2_1_vl_rfs.v,verilog,axi_crossbar_v2_1_30,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_xbar_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/sim/NewExtInst_TOP_xbar_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd,vhdl,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/sim/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_29,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/sim/NewExtInst_TOP_auto_pc_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/sim/NewExtInst_TOP.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
+84
@@ -0,0 +1,84 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
Executable
+47
@@ -0,0 +1,47 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
Executable
+47
@@ -0,0 +1,47 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
Executable
+117
@@ -0,0 +1,117 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158730
|
||||
#define QSPI_FREQ 142857132
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 100000000
|
||||
#define UART_FREQ 100000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 25000000
|
||||
#define FPGA1_FREQ 50000000
|
||||
#define FPGA2_FREQ 100000000
|
||||
#define FPGA3_FREQ 200000000
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
+125613
File diff suppressed because it is too large
Load Diff
+781
@@ -0,0 +1,781 @@
|
||||
proc ps7_pll_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000701
|
||||
mask_write 0XF8000150 0x00003F33 0x00000A03
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A02
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00500800
|
||||
mask_write 0XF8000180 0x03F03F30 0x00400500
|
||||
mask_write 0XF8000190 0x03F03F30 0x00200500
|
||||
mask_write 0XF80001A0 0x03F03F30 0x00100500
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_3_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x0007FFFF 0x00001082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
|
||||
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00000003 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x0003F03F 0x0003C008
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x00010000 0x00000000
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x00000200 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000080
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000703FF 0x000003FF
|
||||
mask_write 0XF800620C 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006210 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006214 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF5 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000260
|
||||
mask_write 0XF8000B70 0x00000001 0x00000001
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003F01 0x00001601
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000724 0x00003F01 0x00001601
|
||||
mask_write 0XF8000728 0x00003FFF 0x00001680
|
||||
mask_write 0XF800072C 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000730 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000734 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000738 0x00003FFF 0x00001680
|
||||
mask_write 0XF800073C 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001202
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001203
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001203
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001203
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B8 0x00003F01 0x00001201
|
||||
mask_write 0XF80007BC 0x00003F01 0x00001201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000012E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000012E1
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F002E
|
||||
mask_write 0XF8000834 0x003F003F 0x00090000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x000003FF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_3_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000701
|
||||
mask_write 0XF8000150 0x00003F33 0x00000A03
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A02
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00500800
|
||||
mask_write 0XF8000180 0x03F03F30 0x00400500
|
||||
mask_write 0XF8000190 0x03F03F30 0x00200500
|
||||
mask_write 0XF80001A0 0x03F03F30 0x00100500
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_2_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000080
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000260
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003F01 0x00001601
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000724 0x00003F01 0x00001601
|
||||
mask_write 0XF8000728 0x00003FFF 0x00001680
|
||||
mask_write 0XF800072C 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000730 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000734 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000738 0x00003FFF 0x00001680
|
||||
mask_write 0XF800073C 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001202
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001203
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001203
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001203
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B8 0x00003F01 0x00001201
|
||||
mask_write 0XF80007BC 0x00003F01 0x00001201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000012E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000012E1
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F002E
|
||||
mask_write 0XF8000834 0x003F003F 0x00090000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x00000FFF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_2_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000701
|
||||
mask_write 0XF8000150 0x00003F33 0x00000A03
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A02
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00500800
|
||||
mask_write 0XF8000180 0x03F03F30 0x00400500
|
||||
mask_write 0XF8000190 0x03F03F30 0x00200500
|
||||
mask_write 0XF80001A0 0x03F03F30 0x00100500
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01EC0C4D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_1_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000080
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x000073FF 0x00000260
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003F01 0x00001601
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000724 0x00003F01 0x00001601
|
||||
mask_write 0XF8000728 0x00003FFF 0x00001680
|
||||
mask_write 0XF800072C 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000730 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000734 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000738 0x00003FFF 0x00001680
|
||||
mask_write 0XF800073C 0x00003FFF 0x00001680
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001202
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001203
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001203
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001203
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B8 0x00003F01 0x00001201
|
||||
mask_write 0XF80007BC 0x00003F01 0x00001201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000012E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000012E1
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F002E
|
||||
mask_write 0XF8000834 0x003F003F 0x00090000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x00000FFF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_1_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
set PCW_SILICON_VER_1_0 "0x0"
|
||||
set PCW_SILICON_VER_2_0 "0x1"
|
||||
set PCW_SILICON_VER_3_0 "0x2"
|
||||
set APU_FREQ 666666666
|
||||
|
||||
|
||||
|
||||
proc mask_poll { addr mask } {
|
||||
set count 1
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
while { $maskedval == 0 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
set count [ expr { $count + 1 } ]
|
||||
if { $count == 100000000 } {
|
||||
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
|
||||
break
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
proc mask_delay { addr val } {
|
||||
set delay [ get_number_of_cycles_for_delay $val ]
|
||||
perf_reset_and_start_timer
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
while { $maskedval == 1 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
}
|
||||
perf_reset_clock
|
||||
}
|
||||
|
||||
proc ps_version { } {
|
||||
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
|
||||
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
|
||||
return $mask_sil_ver;
|
||||
}
|
||||
|
||||
proc ps7_post_config {} {
|
||||
set saved_mode [configparams force-mem-accesses]
|
||||
configparams force-mem-accesses 1
|
||||
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_post_config_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_post_config_2_0
|
||||
} else {
|
||||
ps7_post_config_3_0
|
||||
}
|
||||
configparams force-mem-accesses $saved_mode
|
||||
}
|
||||
|
||||
proc ps7_debug {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_debug_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_debug_2_0
|
||||
} else {
|
||||
ps7_debug_3_0
|
||||
}
|
||||
}
|
||||
proc ps7_init {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_mio_init_data_1_0
|
||||
ps7_pll_init_data_1_0
|
||||
ps7_clock_init_data_1_0
|
||||
ps7_ddr_init_data_1_0
|
||||
ps7_peripherals_init_data_1_0
|
||||
#puts "PCW Silicon Version : 1.0"
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_mio_init_data_2_0
|
||||
ps7_pll_init_data_2_0
|
||||
ps7_clock_init_data_2_0
|
||||
ps7_ddr_init_data_2_0
|
||||
ps7_peripherals_init_data_2_0
|
||||
#puts "PCW Silicon Version : 2.0"
|
||||
} else {
|
||||
ps7_mio_init_data_3_0
|
||||
ps7_pll_init_data_3_0
|
||||
ps7_clock_init_data_3_0
|
||||
ps7_ddr_init_data_3_0
|
||||
ps7_peripherals_init_data_3_0
|
||||
#puts "PCW Silicon Version : 3.0"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# For delay calculation using global timer
|
||||
|
||||
# start timer
|
||||
proc perf_start_clock { } {
|
||||
|
||||
#writing SCU_GLOBAL_TIMER_CONTROL register
|
||||
|
||||
mask_write 0xF8F00208 0x00000109 0x00000009
|
||||
}
|
||||
|
||||
# stop timer and reset timer count regs
|
||||
proc perf_reset_clock { } {
|
||||
perf_disable_clock
|
||||
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
|
||||
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
# Compute mask for given delay in miliseconds
|
||||
proc get_number_of_cycles_for_delay { delay } {
|
||||
|
||||
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
|
||||
variable APU_FREQ
|
||||
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
|
||||
}
|
||||
|
||||
|
||||
# stop timer
|
||||
proc perf_disable_clock {} {
|
||||
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
proc perf_reset_and_start_timer {} {
|
||||
perf_reset_clock
|
||||
perf_start_clock
|
||||
}
|
||||
|
||||
|
||||
+131
@@ -0,0 +1,131 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010-2020 <Xilinx Inc.>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, see <http://www.gnu.org/licenses/>
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init_gpl.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158730
|
||||
#define QSPI_FREQ 142857132
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 100000000
|
||||
#define UART_FREQ 100000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 25000000
|
||||
#define FPGA1_FREQ 50000000
|
||||
#define FPGA2_FREQ 100000000
|
||||
#define FPGA3_FREQ 200000000
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
+106
@@ -0,0 +1,106 @@
|
||||
/*
|
||||
* Xilinx SystemC/TLM-2.0 Zynq Wrapper.
|
||||
*
|
||||
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
|
||||
*
|
||||
* Copyright (c) 2016, Xilinx Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define SC_INCLUDE_DYNAMIC_PROCESSES
|
||||
|
||||
#include <inttypes.h>
|
||||
|
||||
#include "tlm_utils/simple_initiator_socket.h"
|
||||
#include "tlm_utils/simple_target_socket.h"
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace std;
|
||||
|
||||
#include "xilinx-zynq.h"
|
||||
#include <sys/types.h>
|
||||
|
||||
//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr,
|
||||
// Iremoteport_tlm_sync *sync)
|
||||
// : remoteport_tlm(name, -1, sk_descr, sync),
|
||||
xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr)
|
||||
: remoteport_tlm(name, -1, sk_descr),
|
||||
rp_m_axi_gp0("rp_m_axi_gp0"),
|
||||
rp_m_axi_gp1("rp_m_axi_gp1"),
|
||||
rp_s_axi_gp0("rp_s_axi_gp0"),
|
||||
rp_s_axi_gp1("rp_s_axi_gp1"),
|
||||
rp_s_axi_hp0("rp_s_axi_hp0"),
|
||||
rp_s_axi_hp1("rp_s_axi_hp1"),
|
||||
rp_s_axi_hp2("rp_s_axi_hp2"),
|
||||
rp_s_axi_hp3("rp_s_axi_hp3"),
|
||||
rp_s_axi_acp("rp_s_axi_acp"),
|
||||
rp_wires_in("wires_in", 20, 0),
|
||||
rp_wires_out("wires_out", 0, 17),
|
||||
rp_irq_out("irq_out", 0, 28),
|
||||
pl2ps_irq("pl2ps_irq", 20),
|
||||
ps2pl_irq("ps2pl_irq", 28),
|
||||
ps2pl_rst("ps2pl_rst", 17)
|
||||
{
|
||||
int i;
|
||||
|
||||
m_axi_gp[0] = &rp_m_axi_gp0.sk;
|
||||
m_axi_gp[1] = &rp_m_axi_gp1.sk;
|
||||
|
||||
s_axi_gp[0] = &rp_s_axi_gp0.sk;
|
||||
s_axi_gp[1] = &rp_s_axi_gp1.sk;
|
||||
|
||||
s_axi_hp[0] = &rp_s_axi_hp0.sk;
|
||||
s_axi_hp[1] = &rp_s_axi_hp1.sk;
|
||||
s_axi_hp[2] = &rp_s_axi_hp2.sk;
|
||||
s_axi_hp[3] = &rp_s_axi_hp3.sk;
|
||||
s_axi_acp = &rp_s_axi_acp.sk;
|
||||
|
||||
/* PL to PS Interrupt signals. */
|
||||
for (i = 0; i < 20; i++) {
|
||||
rp_wires_in.wires_in[i](pl2ps_irq[i]);
|
||||
}
|
||||
|
||||
/* PS to PL Interrupt signals. */
|
||||
for (i = 0; i < 28; i++) {
|
||||
rp_irq_out.wires_out[i](ps2pl_irq[i]);
|
||||
}
|
||||
|
||||
/* PS to PL resets. */
|
||||
for (i = 0; i < 17; i++) {
|
||||
rp_wires_out.wires_out[i](ps2pl_rst[i]);
|
||||
}
|
||||
|
||||
register_dev(0, &rp_s_axi_gp0);
|
||||
register_dev(1, &rp_s_axi_gp1);
|
||||
|
||||
register_dev(2, &rp_s_axi_hp0);
|
||||
register_dev(3, &rp_s_axi_hp1);
|
||||
register_dev(4, &rp_s_axi_hp2);
|
||||
register_dev(5, &rp_s_axi_hp3);
|
||||
|
||||
register_dev(6, &rp_s_axi_acp);
|
||||
|
||||
register_dev(7, &rp_m_axi_gp0);
|
||||
register_dev(8, &rp_m_axi_gp1);
|
||||
register_dev(9, &rp_wires_in);
|
||||
register_dev(10, &rp_wires_out);
|
||||
register_dev(11, &rp_irq_out);
|
||||
}
|
||||
Executable
+26
@@ -0,0 +1,26 @@
|
||||
COMPILER=
|
||||
ARCHIVER=
|
||||
CP=cp
|
||||
COMPILER_FLAGS=
|
||||
EXTRA_COMPILER_FLAGS=
|
||||
LIB=libxil.a
|
||||
|
||||
RELEASEDIR=../../../lib
|
||||
INCLUDEDIR=../../../include
|
||||
INCLUDES=-I./. -I${INCLUDEDIR}
|
||||
|
||||
INCLUDEFILES=*.h
|
||||
LIBSOURCES=*.c
|
||||
OUTS = *.o
|
||||
|
||||
libs:
|
||||
echo "Compiling SPI_Con..."
|
||||
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
|
||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
||||
make clean
|
||||
|
||||
include:
|
||||
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
|
||||
|
||||
clean:
|
||||
rm -rf ${OUTS}
|
||||
+272
@@ -0,0 +1,272 @@
|
||||
{
|
||||
"graphjs": {
|
||||
"version": "1.0",
|
||||
"keys": [
|
||||
{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
"type": "int",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VT",
|
||||
"name": "vert_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BA",
|
||||
"name": "base_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HA",
|
||||
"name": "high_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BP",
|
||||
"name": "base_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HP",
|
||||
"name": "high_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MX",
|
||||
"name": "master_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MI",
|
||||
"name": "master_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MS",
|
||||
"name": "master_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MV",
|
||||
"name": "master_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SX",
|
||||
"name": "slave_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SI",
|
||||
"name": "slave_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MM",
|
||||
"name": "slave_memmap",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SS",
|
||||
"name": "slave_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SV",
|
||||
"name": "slave_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TM",
|
||||
"name": "memory_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TU",
|
||||
"name": "usage_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "LT",
|
||||
"name": "lock_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BT",
|
||||
"name": "boot_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
|
||||
"type": "int",
|
||||
"for": "edge"
|
||||
}
|
||||
],
|
||||
"vertice_type_order": [
|
||||
{
|
||||
"abrv": "BC",
|
||||
"desc": "Block Container"
|
||||
},
|
||||
{
|
||||
"abrv": "PR",
|
||||
"desc": "Parital Reference"
|
||||
},
|
||||
{
|
||||
"abrv": "VR",
|
||||
"desc": "Variant"
|
||||
},
|
||||
{
|
||||
"abrv": "PM",
|
||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
},
|
||||
{
|
||||
"abrv": "AC",
|
||||
"desc": "Assignment Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "ACE",
|
||||
"desc": "Excluded Assign Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "APX",
|
||||
"desc": "Boundary Aperture"
|
||||
},
|
||||
{
|
||||
"abrv": "CIP",
|
||||
"desc": "High level Processing System"
|
||||
}
|
||||
],
|
||||
"vertices": {
|
||||
"V0": {
|
||||
"VM": "NewExtInst_TOP",
|
||||
"VT": "BC"
|
||||
},
|
||||
"V1": {
|
||||
"VH": "2",
|
||||
"VM": "NewExtInst_TOP",
|
||||
"VT": "VR"
|
||||
},
|
||||
"V2": {
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
},
|
||||
"V3": {
|
||||
"VT": "AC",
|
||||
"BA": "0x43C00000",
|
||||
"HA": "0x43C0FFFF",
|
||||
"BP": "C_S00_AXI_BASEADDR",
|
||||
"HP": "C_S00_AXI_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_SPI_Con_0_S00_AXI_reg",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/SPI_Con_0",
|
||||
"SI": "S00_AXI",
|
||||
"SS": "S00_AXI_reg",
|
||||
"SV": "xilinx.com:user:SPI_Con:1.0",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
},
|
||||
"V4": {
|
||||
"VT": "AC",
|
||||
"BA": "0x43C10000",
|
||||
"HA": "0x43C1FFFF",
|
||||
"BP": "C_S00_AXI_BASEADDR",
|
||||
"HP": "C_S00_AXI_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_SPI_Con_1_S00_AXI_reg",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/SPI_Con_1",
|
||||
"SI": "S00_AXI",
|
||||
"SS": "S00_AXI_reg",
|
||||
"SV": "xilinx.com:user:SPI_Con:1.0",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
},
|
||||
"V5": {
|
||||
"VT": "AC",
|
||||
"BA": "0x43C20000",
|
||||
"HA": "0x43C2FFFF",
|
||||
"BP": "C_S00_AXI_BASEADDR",
|
||||
"HP": "C_S00_AXI_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_SPI_Con_2_S00_AXI_reg",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/SPI_Con_2",
|
||||
"SI": "S00_AXI",
|
||||
"SS": "S00_AXI_reg",
|
||||
"SV": "xilinx.com:user:SPI_Con:1.0",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
},
|
||||
{
|
||||
"src": "V3",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V4",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
},
|
||||
{
|
||||
"src": "V5",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
+297
@@ -0,0 +1,297 @@
|
||||
#!/usr/bin/env bash
|
||||
#**********************************************************************************************************
|
||||
# Vivado (TM) v2023.2 (64-bit)
|
||||
#
|
||||
# Script generated by Vivado on Fri May 15 15:32:22 CST 2026
|
||||
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
|
||||
#
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
# Filename : NewExtInst_TOP.sh
|
||||
# Simulator : Siemens Questa Advanced Simulator
|
||||
# Description : Simulation script generated by export_simulation Tcl command
|
||||
# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
|
||||
# design. The script will copy the library mapping file from the compiled library directory,
|
||||
# create design library directories and library mappings in the mapping file.
|
||||
#
|
||||
# Usage : NewExtInst_TOP.sh
|
||||
# NewExtInst_TOP.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
|
||||
# NewExtInst_TOP.sh [-reset_run]
|
||||
# NewExtInst_TOP.sh [-reset_log]
|
||||
# NewExtInst_TOP.sh [-help]
|
||||
#
|
||||
# * The -noclean_files switch is deprecated and will not peform any function (by default, the
|
||||
# simulator generated files will not be removed unless -reset_run switch is used)
|
||||
#
|
||||
# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library
|
||||
# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
|
||||
# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
|
||||
# switch with the directory path where the library is created while generating the script
|
||||
# with export_simulation.
|
||||
#
|
||||
# Alternatively, you can set the library path by setting the following project property:-
|
||||
#
|
||||
# set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
|
||||
#
|
||||
# You can also point to the simulation library by either setting the 'lib_map_path' global
|
||||
# variable in this script or specify it with the '-lib_map_path' switch while executing this
|
||||
# script (type 'NewExtInst_TOP.sh -help' for more information).
|
||||
#
|
||||
# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
|
||||
# generated script, but if design is targetted for system simulation containing SystemC/C++/C
|
||||
# sources, then the library path MUST be specified upfront when calling export_simulation.
|
||||
#
|
||||
# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#**********************************************************************************************************
|
||||
|
||||
# catch pipeline exit status
|
||||
set -Eeuo pipefail
|
||||
|
||||
# script info
|
||||
echo -e "NewExtInst_TOP.sh - Script generated by export_simulation (Vivado v2023.2 (64-bit)-id)\n"
|
||||
|
||||
# main steps
|
||||
run()
|
||||
{
|
||||
check_args $*
|
||||
setup
|
||||
if [[ ($b_step == 1) ]]; then
|
||||
case $step in
|
||||
"compile" )
|
||||
init_lib
|
||||
compile
|
||||
;;
|
||||
"elaborate" )
|
||||
elaborate
|
||||
;;
|
||||
"simulate" )
|
||||
simulate
|
||||
;;
|
||||
* )
|
||||
echo -e "ERROR: Invalid or missing step '$step' (type \"./NewExtInst_TOP.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
esac
|
||||
else
|
||||
init_lib
|
||||
compile
|
||||
elaborate
|
||||
simulate
|
||||
fi
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
}
|
||||
|
||||
# RUN_STEP: <elaborate>
|
||||
elaborate()
|
||||
{
|
||||
source elaborate.do 2>&1 | tee elaborate.log
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
vsim -64 -c -do "do {simulate.do}" -l simulate.log
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
# delete previous files for a clean rerun
|
||||
if [[ ($b_reset_run == 1) ]]; then
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
fi
|
||||
|
||||
# delete previous log files
|
||||
if [[ ($b_reset_log == 1) ]]; then
|
||||
reset_log
|
||||
echo -e "INFO: Simulation run log files deleted.\n"
|
||||
exit 0
|
||||
fi
|
||||
|
||||
# add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# simulator index file/library directory processing
|
||||
init_lib()
|
||||
{
|
||||
if [[ ($b_keep_index == 1) ]]; then
|
||||
# keep previous simulator index file
|
||||
true
|
||||
else
|
||||
# copy simulator index file to current directory
|
||||
copy_setup_file
|
||||
fi
|
||||
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
ref_lib_dir=$lib_map_path
|
||||
fi
|
||||
|
||||
if [[ ($b_keep_index == 1) ]]; then
|
||||
# do not recreate design library directories
|
||||
true
|
||||
else
|
||||
# create design library directories
|
||||
create_lib_dir
|
||||
fi
|
||||
}
|
||||
|
||||
# copy modelsim.ini file
|
||||
copy_setup_file()
|
||||
{
|
||||
file="modelsim.ini"
|
||||
if [[ ($lib_map_path == "") ]]; then
|
||||
lib_map_path="/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/compile_simlib/questa"
|
||||
fi
|
||||
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
if [[ -e $src_file ]]; then
|
||||
cp $src_file .
|
||||
fi
|
||||
fi
|
||||
}
|
||||
|
||||
# create design library directory
|
||||
create_lib_dir()
|
||||
{
|
||||
lib_dir="questa_lib"
|
||||
if [[ -e $lib_dir ]]; then
|
||||
rm -rf $lib_dir
|
||||
fi
|
||||
mkdir $lib_dir
|
||||
}
|
||||
|
||||
# delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# delete generated log files from the previous run
|
||||
reset_log()
|
||||
{
|
||||
files_to_remove=(compile.log elaborate.log simulate.log)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# check switch argument value
|
||||
check_arg_value()
|
||||
{
|
||||
if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then
|
||||
echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./NewExtInst_TOP.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
}
|
||||
|
||||
# check command line arguments
|
||||
check_args()
|
||||
{
|
||||
arg_count=$#
|
||||
if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
|
||||
usage
|
||||
fi
|
||||
while [[ "$#" -gt 0 ]]; do
|
||||
case $1 in
|
||||
-step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
|
||||
-lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
|
||||
-gen_bypass) b_gen_bypass=1 ;;
|
||||
-reset_run) b_reset_run=1 ;;
|
||||
-reset_log) b_reset_log=1 ;;
|
||||
-keep_index) b_keep_index=1 ;;
|
||||
-noclean_files) b_noclean_files=1 ;;
|
||||
-help|-h) ;;
|
||||
*) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
|
||||
esac
|
||||
shift
|
||||
done
|
||||
|
||||
# -reset_run is not applicable with other switches
|
||||
if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
|
||||
echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
# -reset_log is not applicable with other switches
|
||||
if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
|
||||
echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
# -keep_index is not applicable with other switches
|
||||
if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
|
||||
echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
# -noclean_files is not applicable with other switches
|
||||
if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
|
||||
echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
}
|
||||
|
||||
# script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: NewExtInst_TOP.sh [-help]\n\
|
||||
Usage: NewExtInst_TOP.sh [-step]\n\
|
||||
Usage: NewExtInst_TOP.sh [-lib_map_path]\n\
|
||||
Usage: NewExtInst_TOP.sh [-reset_run]\n\
|
||||
Usage: NewExtInst_TOP.sh [-reset_log]\n\
|
||||
Usage: NewExtInst_TOP.sh [-keep_index]\n\
|
||||
Usage: NewExtInst_TOP.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-step <name>] -- Execute specified step (compile, elaborate, simulate)\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
|
||||
file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
|
||||
NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
|
||||
NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
|
||||
[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
|
||||
[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
|
||||
echo -e $msg
|
||||
exit 0
|
||||
}
|
||||
|
||||
# initialize globals
|
||||
step=""
|
||||
lib_map_path=""
|
||||
b_step=0
|
||||
b_lib_map_path=0
|
||||
b_gen_bypass=0
|
||||
b_reset_run=0
|
||||
b_reset_log=0
|
||||
b_keep_index=0
|
||||
b_noclean_files=0
|
||||
|
||||
# launch script
|
||||
run $*
|
||||
+50
@@ -0,0 +1,50 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2023.2 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and how to fetch design source file details
|
||||
# from the file_info.txt file.
|
||||
#
|
||||
# Generated by export_simulation on Fri May 15 15:32:22 CST 2026
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. Steps to run the generated simulation script
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./NewExtInst_TOP.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first calls the 'check_args' function, the purpose of which
|
||||
is to verify the generated script arguments and print error if incorrect switch
|
||||
is specified. The 'run' function then calls the 'setup' function, the purpose of
|
||||
which is to specify custom or initialization commands. The function also executes
|
||||
following sub-functions:-
|
||||
'reset_run' if -reset_run switch is specified.
|
||||
'reset_log' if -reset_log switch is specified.
|
||||
|
||||
The purpose of 'reset_run' function' is to delete the simulator generated design
|
||||
data from the previous run and the purpose of 'reset_log' function' is to delete
|
||||
the simulator generated log files.
|
||||
|
||||
The 'run' function then calls the 'init_lib' function, the purpose of which is to
|
||||
create design library mappings and directories. This function is called before the
|
||||
'compile' step. By default, if '-step' switch is specified with the script then the
|
||||
script will execute that specfic step, else it will execute all steps applicable
|
||||
for the target simulator.
|
||||
|
||||
For more information on the script, please type './NewExtInst_TOP.sh -help'
|
||||
|
||||
2. Design source file information
|
||||
|
||||
export_simulation generates a 'file_info.txt' file that contains design file information
|
||||
based on the compile order when export_simulation was executed from Vivado. The file
|
||||
contains information about the file name, type, library it is compiled into, whether
|
||||
it is part of the IP, associated library, file path information in a comma separated
|
||||
format. This file can be parsed to extract the required information for generating a
|
||||
custom script or can be read from verification test infra.
|
||||
|
||||
Executable
+107
@@ -0,0 +1,107 @@
|
||||
|
||||
#ifndef SPI_CON_H
|
||||
#define SPI_CON_H
|
||||
|
||||
|
||||
/****************** Include Files ********************/
|
||||
#include "xil_types.h"
|
||||
#include "xstatus.h"
|
||||
|
||||
#define SPI_CON_S00_AXI_SLV_REG0_OFFSET 0
|
||||
#define SPI_CON_S00_AXI_SLV_REG1_OFFSET 4
|
||||
#define SPI_CON_S00_AXI_SLV_REG2_OFFSET 8
|
||||
#define SPI_CON_S00_AXI_SLV_REG3_OFFSET 12
|
||||
#define SPI_CON_S00_AXI_SLV_REG4_OFFSET 16
|
||||
#define SPI_CON_S00_AXI_SLV_REG5_OFFSET 20
|
||||
#define SPI_CON_S00_AXI_SLV_REG6_OFFSET 24
|
||||
#define SPI_CON_S00_AXI_SLV_REG7_OFFSET 28
|
||||
#define SPI_CON_S00_AXI_SLV_REG8_OFFSET 32
|
||||
#define SPI_CON_S00_AXI_SLV_REG9_OFFSET 36
|
||||
#define SPI_CON_S00_AXI_SLV_REG10_OFFSET 40
|
||||
#define SPI_CON_S00_AXI_SLV_REG11_OFFSET 44
|
||||
#define SPI_CON_S00_AXI_SLV_REG12_OFFSET 48
|
||||
#define SPI_CON_S00_AXI_SLV_REG13_OFFSET 52
|
||||
#define SPI_CON_S00_AXI_SLV_REG14_OFFSET 56
|
||||
#define SPI_CON_S00_AXI_SLV_REG15_OFFSET 60
|
||||
#define SPI_CON_S00_AXI_SLV_REG16_OFFSET 64
|
||||
#define SPI_CON_S00_AXI_SLV_REG17_OFFSET 68
|
||||
#define SPI_CON_S00_AXI_SLV_REG18_OFFSET 72
|
||||
#define SPI_CON_S00_AXI_SLV_REG19_OFFSET 76
|
||||
#define SPI_CON_S00_AXI_SLV_REG20_OFFSET 80
|
||||
#define SPI_CON_S00_AXI_SLV_REG21_OFFSET 84
|
||||
#define SPI_CON_S00_AXI_SLV_REG22_OFFSET 88
|
||||
#define SPI_CON_S00_AXI_SLV_REG23_OFFSET 92
|
||||
#define SPI_CON_S00_AXI_SLV_REG24_OFFSET 96
|
||||
#define SPI_CON_S00_AXI_SLV_REG25_OFFSET 100
|
||||
#define SPI_CON_S00_AXI_SLV_REG26_OFFSET 104
|
||||
#define SPI_CON_S00_AXI_SLV_REG27_OFFSET 108
|
||||
#define SPI_CON_S00_AXI_SLV_REG28_OFFSET 112
|
||||
#define SPI_CON_S00_AXI_SLV_REG29_OFFSET 116
|
||||
#define SPI_CON_S00_AXI_SLV_REG30_OFFSET 120
|
||||
#define SPI_CON_S00_AXI_SLV_REG31_OFFSET 124
|
||||
|
||||
|
||||
/**************************** Type Definitions *****************************/
|
||||
/**
|
||||
*
|
||||
* Write a value to a SPI_CON register. A 32 bit write is performed.
|
||||
* If the component is implemented in a smaller width, only the least
|
||||
* significant data is written.
|
||||
*
|
||||
* @param BaseAddress is the base address of the SPI_CONdevice.
|
||||
* @param RegOffset is the register offset from the base to write to.
|
||||
* @param Data is the data written to the register.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void SPI_CON_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
|
||||
*
|
||||
*/
|
||||
#define SPI_CON_mWriteReg(BaseAddress, RegOffset, Data) \
|
||||
Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
|
||||
|
||||
/**
|
||||
*
|
||||
* Read a value from a SPI_CON register. A 32 bit read is performed.
|
||||
* If the component is implemented in a smaller width, only the least
|
||||
* significant data is read from the register. The most significant data
|
||||
* will be read as 0.
|
||||
*
|
||||
* @param BaseAddress is the base address of the SPI_CON device.
|
||||
* @param RegOffset is the register offset from the base to write to.
|
||||
*
|
||||
* @return Data is the data from the register.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* u32 SPI_CON_mReadReg(u32 BaseAddress, unsigned RegOffset)
|
||||
*
|
||||
*/
|
||||
#define SPI_CON_mReadReg(BaseAddress, RegOffset) \
|
||||
Xil_In32((BaseAddress) + (RegOffset))
|
||||
|
||||
/************************** Function Prototypes ****************************/
|
||||
/**
|
||||
*
|
||||
* Run a self-test on the driver/device. Note this may be a destructive test if
|
||||
* resets of the device are performed.
|
||||
*
|
||||
* If the hardware system is not built correctly, this function may never
|
||||
* return to the caller.
|
||||
*
|
||||
* @param baseaddr_p is the base address of the SPI_CON instance to be worked on.
|
||||
*
|
||||
* @return
|
||||
*
|
||||
* - XST_SUCCESS if all self-test code passed
|
||||
* - XST_FAILURE if any self-test code failed
|
||||
*
|
||||
* @note Caching must be turned off for this function to work.
|
||||
* @note Self test may fail if data memory and device are not on the same bus.
|
||||
*
|
||||
*/
|
||||
XStatus SPI_CON_Reg_SelfTest(void * baseaddr_p);
|
||||
|
||||
#endif // SPI_CON_H
|
||||
Executable
+10
@@ -0,0 +1,10 @@
|
||||
|
||||
|
||||
OPTION psf_version = 2.1;
|
||||
|
||||
BEGIN DRIVER SPI_Con
|
||||
OPTION supported_peripherals = (SPI_Con);
|
||||
OPTION copyfiles = all;
|
||||
OPTION VERSION = 1.0;
|
||||
OPTION NAME = SPI_Con;
|
||||
END DRIVER
|
||||
Executable
+5
@@ -0,0 +1,5 @@
|
||||
|
||||
|
||||
proc generate {drv_handle} {
|
||||
xdefine_include_file $drv_handle "xparameters.h" "SPI_Con" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
|
||||
}
|
||||
+39
@@ -0,0 +1,39 @@
|
||||
axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
xpm_cdc.sv,systemverilog,xpm,../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
xpm_memory.sv,systemverilog,xpm,../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_15,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/5753/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_17,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/sim/NewExtInst_TOP_processing_system7_0_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_clk_wiz_0_0_clk_wiz.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_clk_wiz.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_clk_wiz_0_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_14,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_proc_sys_reset_0_0.vhd,vhdl,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/sim/NewExtInst_TOP_proc_sys_reset_0_0.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
SPI_Con_v1_0_S00_AXI.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
SPI_Con_v1_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_SPI_Con_0_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/sim/NewExtInst_TOP_SPI_Con_0_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_SPI_Con_0_1.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/sim/NewExtInst_TOP_SPI_Con_0_1.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_SPI_Con_0_2.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/sim/NewExtInst_TOP_SPI_Con_0_2.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
generic_baseblocks_v2_1_vl_rfs.v,verilog,generic_baseblocks_v2_1_1,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_register_slice_v2_1_vl_rfs.v,verilog,axi_register_slice_v2_1_29,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_9,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/simulation/fifo_generator_vlog_beh.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_9,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_9,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_data_fifo_v2_1_vl_rfs.v,verilog,axi_data_fifo_v2_1_28,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_crossbar_v2_1_vl_rfs.v,verilog,axi_crossbar_v2_1_30,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_xbar_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/sim/NewExtInst_TOP_xbar_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd,vhdl,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/sim/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_29,../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/sim/NewExtInst_TOP_auto_pc_0.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
NewExtInst_TOP.v,verilog,xil_defaultlib,../../../bd/NewExtInst_TOP/sim/NewExtInst_TOP.v,incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl"incdir="../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
+84
@@ -0,0 +1,84 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
Executable
+47
@@ -0,0 +1,47 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
Executable
+47
@@ -0,0 +1,47 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
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