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11 Commits
c5df01f33d .. CPLD
Author SHA1 Message Date
Jeremy Shen 3b268f6583 Migrate to Vitis2023.2 version 2026-05-26 17:02:52 +08:00
Jeremy Shen 2dca3709ef CPLD bug fixes 2026-05-25 18:13:03 +08:00
Jeremy Shen 74cd2ae192 Add Zynq project files 2026-05-25 18:12:01 +08:00
Jeremy Shen e61e9d48ad Add *.metadata/ to ignore items 2026-05-25 18:11:36 +08:00
Jeremy Shen 63e1fdcdf1 Add testbenches 2026-05-25 09:29:23 +08:00
Jeremy Shen 99ef0f0e6e CPLD3 implementation 2026-05-22 16:59:29 +08:00
Jeremy Shen 7f43729caf Bug fix & CPLD2 PMU implementation 2026-05-21 17:15:14 +08:00
Jeremy Shen 13611d20a0 Increase the version of CPLD1 2026-05-21 11:33:20 +08:00
Jeremy Shen 7096f94f47 PMU DC Control Output & bug fix 2026-05-20 18:21:42 +08:00
Jeremy Shen 248a54b777 Add PMU DC Control part 2026-05-20 10:05:48 +08:00
Jeremy Shen 79d5a810dc Add dc function (05-18) 2026-05-19 14:34:14 +08:00
5532 changed files with 1685528 additions and 1543 deletions
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.gitignore
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@@ -115,6 +115,7 @@ work/
*.gen/ *.gen/
*.tmp/ *.tmp/
*.data/ *.data/
*.metadata/
# Vivado 独立目录 # Vivado 独立目录
.Xil/ .Xil/
1.Docs/NewCalBoard_DIG_SYY.md
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# NewCalBoard_DIG_SYY
> Extracted from `NewCalBoard_DIG_SYY.xlsx`
- **File size:** 38,819 bytes (37.9 KB)
- **Total sheets:** 6
## Sheet Summary
| # | Sheet Name | Rows | Columns | Merged Cells | Data Rows |
|---|-----------|------|---------|-------------|----------|
| 1 | Notes | 6 | 3 | 0 | 5 |
| 2 | CPLD_REG | 35 | 42 | 39 | 12 |
| 3 | ARM_CPLD | 36 | 7 | 0 | 34 |
| 4 | Freq_CPLD | 57 | 8 | 0 | 57 |
| 5 | Freq_Output | 20 | 18 | 19 | 17 |
| 6 | PMU_CH_Sel | 133 | 26 | 98 | 129 |
---
## Sheet: `Notes`
- **Dimensions:** 6 rows x 3 columns
- **Merged cell ranges:** 0
| SCLK_S03定义错误 | | |
|---|---|---|---|---|
| Zynq与CPLD互连线冲突 | 1_B5_31 | TPL241A & 5522 |
| | 2_B2_35 | ARM & ULN |
| | 2_B2_38 | ARM & ULN |
| | 3_B2_56 | ARM & ADG |
---
## Sheet: `CPLD_REG`
- **Dimensions:** 35 rows x 42 columns
- **Merged cell ranges:** 39
| Addr[7:0] | | | | Data[23:0] | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MSB | | | LSB | MSB(bit23) | | | | | | | | | | | | bit11 | | bit9 | | | | | | | | bit1 | LSB(bit0) | | | | | | | | | | | | | | |
| W(1)/R(0) | 0 (IDENT) | | | CPLD3 | CPLD2 | CPLD1 | Reserved | | | | | | | | | Major Version | | | | Minor Version | | | | Reversion | | | | | | | | | | | | | | | | | |
| W(1)/R(0) | 1 (STATE) | | | RDY | Reserved | | | | | | | | | | | | | | | | | | | | | | EXEC | Level1(MSB) | | Level2 | | | | Level3(LSB) | | | | | | | |
| W(1)/R(0) | 2 (Freq_Slot1) | | | Per Relay_Control (1 to Switch/0 to Not Switch) | | | | | | | | | | | | | | Channel_Number | | | | | | | | | Slot_EN(1 to EN) | RC_F1 | RC_F2 | RC_S1 | RC_S2 | RC_S3 | RC_S4 | RC_T1 | RC_T2 | RC_T3 | RC_T4 | RC_T5 | RC_T6 | RC_T7 | RC_T8 |
| W(1)/R(0) | 3 (Freq_Slot2) | | | Per Relay_Control (1 to Switch/0 to Not Switch) | | | | | | | | | | | | | | Channel_Number | | | | | | | | | Slot_EN(1 to EN) | RC_F3 | RC_F4 | RC_S5 | RC_S6 | RC_S7 | RC_S8 | RC_T9 | RC_T10 | RC_T11 | RC_T12 | RC_T13 | RC_T14 | RC_T15 | RC_T16 |
| W(1)/R(0) | 4 (Freq_Slot3) | | | Per Relay_Control (1 to Switch/0 to Not Switch) | | | | | | | | | | | | | | Channel_Number | | | | | | | | | Slot_EN(1 to EN) | RC_F5 | RC_F6 | RC_S9 | RC_S10 | RC_S11 | RC_S12 | RC_T17 | RC_T18 | RC_T19 | RC_T20 | RC_T21 | RC_T22 | RC_T23 | RC_T24 |
| W(1)/R(0) | 5 (Freq_Slot4) | | | Per Relay_Control (1 to Switch/0 to Not Switch) | | | | | | | | | | | | | | Channel_Number | | | | | | | | | Slot_EN(1 to EN) | RC_F7 | RC_F8 | RC_S13 | RC_S14 | RC_S15 | RC_S16 | RC_T25 | RC_T26 | RC_T27 | RC_T28 | RC_T29 | RC_T30 | RC_T31 | RC_T32 |
| W(1)/R(0) | 6 (DC_Slot1) | | | PMU(0)/DPS(1) | V(0)/I(1) | Rload_Sel | | | | | Reserved | | | | | | | Channel_Number | | | | | | | | | Slot_EN(1 to EN) | | | | | | | | | | | | | | |
| W(1)/R(1) | 7 (DC_Slot2) | | | PMU(0)/DPS(1) | V(0)/I(1) | Rload_Sel | | | | | Reserved | | | | | | | Channel_Number | | | | | | | | | Slot_EN(1 to EN) | | | | | | | | | | | | | | |
| W(1)/R(2) | 8 (DC_Slot3) | | | PMU(0)/DPS(1) | V(0)/I(1) | Rload_Sel | | | | | Reserved | | | | | | | Channel_Number | | | | | | | | | Slot_EN(1 to EN) | | | | | | | | | | | | | | |
| W(1)/R(3) | 9 (DC_Slot4) | | | PMU(0)/DPS(1) | V(0)/I(1) | Rload_Sel | | | | | Reserved | | | | | | | Channel_Number | | | | | | | | | Slot_EN(1 to EN) | | | | | | | | | | | | | | |
---
## Sheet: `ARM_CPLD`
- **Dimensions:** 36 rows x 7 columns
- **Merged cell ranges:** 0
| SIG | ARM | DIR(Zynq) | CPLD | | | |
|---|---|---|---|---|---|---|---|---|
| RVAILD | B13_L15P_AF19 | | 1_B2_56 | AA16 | | OPTIONAL |
| CLK | B13_L9P_AB21 | | 1_B2_35 | AA10 | | |
| ERR | B13_L16N_AE21 | | 1_B2_55 | AB16 | | |
| MOSI | B13_L19N_Y20 | | 1_B2_39 | AB12 | | |
| WREADY | B13_L16P_AE20 | | 1_B2_54 | Y15 | | |
| RST_N | B13_L18N_AF18 | | 1_B2_47 | Y14 | | |
| RREADY | B13_L17P_AD18 | | 1_B2_48 | AB15 | | |
| WVAILD | B13_L17N_AD19 | | 1_B2_53 | AA15 | | |
| MISO | B13_L18P_AE18 | | 1_B2_44 | AA14 | | |
| CS | B13_L19P_W20 | | 1_B2_38 | AB11 | | |
| | B13_L10P_AA22 | | 1_XO2_CLK2_0 | AA9 | | |
| ERR | B13_L1P_AA25 | | 2_B2_55 | AB16 | | |
| CLK | B13_L1N_AB25 | | 2_B2_56 | AA16 | | |
| CS | B13_L11P_AD23 | | 2_B2_54 | Y15 | | |
| WVAILD | B13_L11N_AD24 | | 2_B2_53 | AA15 | | |
| RST_N | B13_L12P_AC23 | | 2_B2_47 | Y14 | | |
| MOSI | B13_L13P_AD20 | | 2_B2_39 | AB12 | | |
| RVAILD | B13_L12N_AC24 | | 2_B2_48 | AB15 | | |
| RREADY | B13_L14P_AC21 | | 2_B2_35 | AA10 | 2_B2_35同时连到ARM & ULN | |
| MISO | B13_L13N_AD21 | | 2_B2_44 | AA14 | | |
| WREADY | B13_L14N_AC22 | | 2_B2_38 | AB11 | 2_B2_38同时连到ARM & ULN | |
| | B13_L15N_AF20 | | 2_XO2_CLK2_0 | AA9 | | |
| ERR | B12_L10P_AE13 | | 3_B2_55 | AB16 | | |
| RVAILD | B12_L10N_AF13 | | 3_B2_56 | AA16 | 3_B2_56同时连到ARM & ADG | |
| WREADY | B12_L9P_AE11 | | 3_B2_54 | Y15 | | |
| WVAILD | B12_L9N_AF10 | | 3_B2_53 | AA15 | | |
| RST_N | B12_L8P_AE12 | | 3_B2_47 | Y14 | | |
| MOSI | B12_L8N_AF12 | | 3_B2_39 | AB12 | | |
| RREADY | B12_L7P_AE10 | | 3_B2_48 | AB15 | | |
| CLK | B12_L7N_AD10 | | 3_B2_35 | AA10 | | |
| MISO | B12_L6P_AA13 | | 3_B2_44 | AA14 | | |
| CS | B12_L6N_AA12 | | 3_B2_38 | AB11 | | |
| | B12_L5P_W13 | | 3_XO2_CLK2_0 | AA9 | | |
---
## Sheet: `Freq_CPLD`
- **Dimensions:** 57 rows x 8 columns
- **Merged cell ranges:** 0
| Level | Relay | CPLD | CPLD_Pin | Channel | Slot | | |
|---|---|---|---|---|---|---|---|---|---|
| #1 | RC_F1 | 2_B2_58 | U13 | 1-4&65-68||5-8&69-72 | 1 | | |
| | RC_F2 | 2_B2_46 | U12 | 129-132&193-196||133-136&197-200 | 1 | | |
| | RC_F3 | 2_B2_45 | T12 | 1-4&65-68||5-8&69-72 | 2 | | |
| | RC_F4 | 2_B2_34 | T11 | 129-132&193-196||133-136&197-200 | 2 | | |
| | RC_F5 | 2_B2_33 | U11 | 1-4&65-68||5-8&69-72 | 3 | | |
| | RC_F6 | 2_B2_29 | V11 | 129-132&193-196||133-136&197-200 | 3 | | |
| | RC_F7 | 2_B2_30 | W11 | 1-4&65-68||5-8&69-72 | 4 | | |
| | RC_F8 | 2_B2_27 | U10 | 129-132&193-196||133-136&197-200 | 4 | | |
| #2 | RC_S1 | 2_B2_28 | T10 | 1-2&5-6||3-4&7-8 | 1 | | |
| | RC_S2 | 2_B2_24 | W9 | 65-66&69-70||67-68&71-72 | 1 | | |
| | RC_S3 | 2_B2_11 | AB2 | 129-130&133-134||131-132&135-136 | 1 | | |
| | RC_S4 | 2_B2_01 | Y3 | 193-194&197-198||195-196&199-200 | 1 | | |
| | RC_S5 | 2_B2_02 | AA3 | 1-2&5-6||3-4&7-8 | 2 | | |
| | RC_S6 | 2_B2_12 | AB3 | 65-66&69-70||67-68&71-72 | 2 | | |
| | RC_S7 | 2_B2_06 | Y4 | 129-130&133-134||131-132&135-136 | 2 | | |
| | RC_S8 | 2_B2_13 | AA4 | 193-194&197-198||195-196&199-200 | 2 | | |
| | RC_S9 | 2_B2_14 | Y5 | 1-2&5-6||3-4&7-8 | 3 | | |
| | RC_S10 | 2_B2_15 | W6 | 65-66&69-70||67-68&71-72 | 3 | | |
| | RC_S11 | 2_B2_19 | AB5 | 129-130&133-134||131-132&135-136 | 3 | | |
| | RC_S12 | 2_B2_21 | AB6 | 193-194&197-198||195-196&199-200 | 3 | | |
| | RC_S13 | 2_B2_20 | Y6 | 1-2&5-6||3-4&7-8 | 4 | | |
| | RC_S14 | 2_B2_22 | Y7 | 65-66&69-70||67-68&71-72 | 4 | | |
| | RC_S15 | 2_B2_26 | AB7 | 129-130&133-134||131-132&135-136 | 4 | | |
| | RC_S16 | 2_B2_25 | AA7 | 193-194&197-198||195-196&199-200 | 4 | | |
| #3 | RC_T1 | 2_B2_32 | AA8 | 1&3||2&4 | 1 | | |
| | RC_T2 | 2_B2_84 | Y10 | 5&7||6&8 | 1 | | |
| | RC_T3 | 2_B2_36 | AB10 | 65&67||66&68 | 1 | | |
| | RC_T4 | 2_B2_35 | AA10 | 69&71||70&72 | 1 | | |
| | RC_T5 | 2_B2_37 | AA11 | 129&131||130&132 | 1 | | |
| | RC_T6 | 2_B2_38 | AB11 | 133&135||134&136 | 1 | | |
| | RC_T7 | 2_B2_40 | AA12 | 193&195||194&196 | 1 | | |
| | RC_T8 | 2_B2_41 | AB13 | 192&199||198&200 | 1 | | |
| | RC_T9 | 2_B2_17 | AA13 | 1&3||2&4 | 2 | | |
| | RC_T10 | 2_B2_50 | V12 | 5&7||6&8 | 2 | | |
| | RC_T11 | 2_B2_49 | W12 | 65&67||66&68 | 2 | | |
| | RC_T12 | 2_B2_51 | Y12 | 69&71||70&72 | 2 | | |
| | RC_T13 | 2_B2_52 | V13 | 129&131||130&132 | 2 | | |
| | RC_T14 | 2_B2_62 | V14 | 133&135||134&136 | 2 | | |
| | RC_T15 | 2_B2_73 | V16 | 193&195||194&196 | 2 | | |
| | RC_T16 | 2_B2_60 | AB17 | 192&199||198&200 | 2 | | |
| | RC_T17 | 2_B2_69 | Y18 | 1&3||2&4 | 3 | | 65&67||66&68 |
| | RC_T18 | 2_B2_70 | AA19 | 5&7||6&8 | 3 | | 69&71||70&72 |
| | RC_T19 | 2_B2_71 | AB20 | 65&67||66&68 | 3 | | 1&3||2&4 |
| | RC_T20 | 2_B2_80 | W19 | 69&71||70&72 | 3 | | 5&7||6&8 |
| | RC_T21 | 2_B2_68 | W17 | 129&131||130&132 | 3 | | 193&195||194&196 |
| | RC_T22 | 2_B2_63 | Y17 | 133&135||134&136 | 3 | | 192&199||198&200 |
| | RC_T23 | 2_B2_77 | T15 | 193&195||194&196 | 3 | | 129&131||130&132 |
| | RC_T24 | 2_B2_74 | U15 | 192&199||198&200 | 3 | | 133&135||134&136 |
| | RC_T25 | 2_B2_57 | T13 | 1&3||2&4 | 4 | | |
| | RC_T26 | 2_B2_42 | AA13 | 5&7||6&8 | 4 | | |
| | RC_T27 | 1_B2_58 | U13 | 65&67||66&68 | 4 | | |
| | RC_T28 | 1_B2_46 | U12 | 69&71||70&72 | 4 | | |
| | RC_T29 | 1_B2_45 | T12 | 129&131||130&132 | 4 | | |
| | RC_T30 | 1_B2_34 | T11 | 133&135||134&136 | 4 | | |
| | RC_T31 | 1_B2_33 | U11 | 193&195||194&196 | 4 | | |
| | RC_T32 | 1_B2_29 | V11 | 192&199||198&200 | 4 | | |
---
## Sheet: `Freq_Output`
- **Dimensions:** 20 rows x 18 columns
- **Merged cell ranges:** 19
| Slot | Relay_Out | Channel_Range | DUT_Port | DUT_EN | CPLD_Pin | | | DMM_EN | CPLD_Pin | | OUTPUT_Port | | Freq_BNC | CPLD_Pin | | | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | CAL_1.01 | 001-008 | D1_1 | OC_1.01 | 1_B1_35 | M19 | S_DMM_1 | OC_DMM0 | 1_B0_38 | F17 | DMM1 | 1_CAL | IO_RC1 | 1_B0_23 | F10 | | CTRL_SIG |
| | CAL_1.09 | 065-072 | D1_3 | OC_1.09 | 2_B0_59 | D14 | S_DMM_2 | OC_DMM1 | 1_B0_37 | E17 | | | | | | | CPLD1 |
| | CAL_1.17 | 129-136 | D1_5 | OC_1.17 | 1_B2_15 | W6 | S_DMM_3 | OC_DMM2 | 1_B0_52 | D17 | | | | | | | CPLD2 |
| | CAL_1.25 | 193-200 | D1_7 | OC_1.25 | 2_B3_04 | N5 | S_DMM_4 | OC_DMM3 | 1_B0_55 | C17 | | | | | | | CPLD3 |
| 2 | CAL_2.01 | 001-008 | D1_9 | OC_2.01 | 1_B0_45 | E16 | S_DMM_5 | OC_DMM4 | 1_B2_36 | AB10 | DMM2 | 2_CAL | IO_RC1 | 1_B0_23 | F10 | | |
| | CAL_2.09 | 065-072 | D1_11 | OC_2.09 | 2_B5_10 | C1 | S_DMM_6 | OC_DMM5 | 1_B2_37 | AA11 | | | PMU_RC1 | 3_B3_10 | V2 | | |
| | CAL_2.17 | 129-136 | D1_13 | OC_2.17 | 1_B0_58 | A17 | S_DMM_7 | OC_DMM6 | 1_B2_40 | AA12 | | | PMU_RC2 | 3_B1_38 | N18 | | |
| | CAL_2.25 | 193-200 | D1_15 | OC_2.25 | 2_B3_26 | T7 | S_DMM_8 | OC_DMM7 | 1_B2_41 | AB13 | | | | | | | |
| 3 | CAL_3.09 | 065-072 | D1_19 | OC_3.09 | 2_B0_34 | A11 | S_DMM_9 | OC_DMM8 | 1_B0_53 | D15 | DMM3 | 3_CAL | IO_RC1 | 1_B0_23 | F10 | | |
| | CAL_3.01 | 001-008 | D1_17 | OC_3.01 | 1_B3_03 | M3 | S_DMM_10 | OC_DMM9 | 1_B0_59 | D14 | | | PMU_RC1 | 3_B3_10 | V2 | | |
| | CAL_3.25 | 193-200 | D1_23 | OC_3.25 | 2_B0_76 | B13 | S_DMM_12 | OC_DMM12 | 1_B0_72 | F12 | | | PMU_RC3 | 3_B1_63 | P19 | | |
| | CAL_3.17 | 129-136 | D1_21 | OC_3.17 | 1_B0_17 | E8 | S_DMM_11 | OC_DMM11 | 1_B0_69 | C13 | | | | | | | |
| 4 | CAL_4.01 | 001-008 | D1_25 | OC_4.01 | 1_B0_75 | A13 | S_DMM_13 | OC_DMM12 | 1_B2_49 | W12 | DMM4 | 4_CAL | IO_RC1 | 1_B0_23 | F10 | | |
| | CAL_4.09 | 065-072 | D1_27 | OC_4.09 | 2_B5_22 | G1 | S_DMM_14 | OC_DMM13 | 1_B2_50 | V12 | | | PMU_RC1 | 3_B3_10 | V2 | | |
| | CAL_4.17 | 129-136 | D1_29 | OC_4.17 | 1_B0_68 | C15 | S_DMM_15 | OC_DMM14 | 1_B2_51 | Y12 | | | PMU_RC4 | 3_B1_64 | P18 | | |
| | CAL_4.25 | 193-200 | D1_31 | OC_4.25 | 2_B5_31 | E1 | S_DMM_16 | OC_DMM15 | 1_B2_52 | V13 | | | | | | | |
---
## Sheet: `PMU_CH_Sel`
- **Dimensions:** 133 rows x 26 columns
- **Merged cell ranges:** 98
| Slot | Relay_Out | Channel_Range | DUT_Port | DUT_EN | CPLD_Pin | | | DMM_EN | CPLD_Pin | | OUTPUT_Port | | DMM_SW | CPLD_Pin | | Resistor | Load_SW | CPLD_Pin | | VP/AP_SW | CPLD_Pin | | DMM_N | CPLD_Pin | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | CAL_1.01 | 001-008 | D1_1 | OC_1.01 | 1_B1_35 | M19 | S_DMM_1 | OC_DMM1 | 1_B0_38 | F17 | DMM1 | 1_CAL | PMU_RC1 | 3_B3_10 | V2 | 1Ω | RC_RL1 | 1_B4_14 | M6 | RC_VpK | 1_B4_08 | L7 | RC_LOF1 | 1_B5_32 | F3 |
| | CAL_1.02 | 009-016 | D2_1 | OC_1.02 | 1_B1_77 | R16 | | | | | | | | | | 5Ω | RC_RL2 | 1_B4_17 | M4 | RC_ApK | 1_B3_12 | P6 | RC_LOF2 | 1_B5_30 | H4 |
| | CAL_1.03 | 017-024 | D3_1 | OC_1.03 | 1_B1_31 | N20 | | | | | | | | | | 10Ω | RC_RL3 | 1_B0_35 | B10 | | | | RC_LOS1 | 1_B5_16 | G4 |
| | CAL_1.04 | 025-032 | D4_1 | OC_1.04 | 1_B1_69 | P20 | | | | | | | | | | 100Ω | RC_RL4 | 1_B4_15 | P3 | | | | RC_LOS2 | 1_B4_07 | L6 |
| | CAL_1.05 | 033-040 | D1_2 | OC_1.05 | 1_B1_10 | G19 | | | | | | | | | | 150Ω | RC_RL5 | 1_B5_04 | F5 | | | | | | |
| | CAL_1.06 | 041-048 | D2_2 | OC_1.06 | 1_B1_16 | J19 | | | | | | | | | | 499Ω | RC_RL6 | 1_B0_24 | G10 | | | | | | |
| | CAL_1.07 | 049-056 | D3_2 | OC_1.07 | 1_B1_04 | H16 | | | | | | | | | | 1kΩ | RC_RL7 | 1_B5_03 | F6 | | | | | | |
| | CAL_1.08 | 057-064 | D4_2 | OC_1.08 | 1_B1_13 | J17 | | | | | | | | | | 4.99kΩ | RC_RL8 | 1_B0_27 | C8 | | | | | | |
| | CAL_1.09 | 065-072 | D1_3 | OC_1.09 | 2_B0_59 | D14 | S_DMM_2 | OC_DMM2 | 1_B0_37 | E17 | | | | | | 10kΩ | RC_RL9 | 1_B0_21 | B7 | | | CPLD1 | CPLD2 | CPLD3 | |
| | CAL_1.10 | 073-080 | D2_3 | OC_1.10 | 2_B0_61 | G13 | | | | | | | | | | 49.9kΩ | RC_RL10 | 1_B0_09 | F8 | | | | | | |
| | CAL_1.11 | 081-088 | D3_3 | OC_1.11 | 2_B0_69 | C13 | | | | | | | | | | 100kΩ | RC_RL11 | 1_B0_14 | C5 | | | | | | |
| | CAL_1.12 | 089-096 | D4_3 | OC_1.12 | 2_B0_62 | F13 | | | | | | | | | | 402kΩ | RC_RL12 | 1_B0_08 | A3 | | | | | | |
| | CAL_1.13 | 097-104 | D1_4 | OC_1.13 | 2_B0_55 | C17 | | | | | | | | | | 1MΩ | RC_RL13 | 1_B0_33 | B11 | | | | | | |
| | CAL_1.14 | 105-112 | D2_4 | OC_1.14 | 2_B0_38 | F17 | | | | | | | | | | 1.5MΩ | RC_RL14 | 1_B0_15 | A5 | | | | | | |
| | CAL_1.15 | 113-120 | D3_4 | OC_1.15 | 2_B0_52 | D17 | | | | | | | | | | 2MΩ | RC_RL15 | 1_B0_13 | B4 | | | | | | |
| | CAL_1.16 | 121-128 | D4_4 | OC_1.16 | 2_B0_37 | E17 | | | | | | | | | | 4.99MΩ | RC_RL16 | 1_B0_31 | F11 | | | | | | |
| | CAL_1.17 | 129-136 | D1_5 | OC_1.17 | 1_B2_15 | W6 | S_DMM_3 | OC_DMM3 | 1_B0_52 | D17 | | | | | | 10MΩ | RC_RL17 | 1_B0_20 | D9 | | | | | | |
| | CAL_1.18 | 137-144 | D2_5 | OC_1.18 | 1_B2_25 | AA7 | | | | | | | | | | REV | RC_RL18 | 1_B3_04 | N5 | | | | | | |
| | CAL_1.19 | 145-152 | D3_5 | OC_1.19 | 1_B2_21 | AB6 | | | | | | | | | | | | | | | | | | | |
| | CAL_1.20 | 153-160 | D4_5 | OC_1.20 | 1_B2_22 | Y7 | | | | | | | | | | | | | | | | | | | |
| | CAL_1.21 | 161-168 | D1_6 | OC_1.21 | 1_B3_20 | V4 | | | | | | | | | | | | | | | | | | | |
| | CAL_1.22 | 169-176 | D2_6 | OC_1.22 | 1_B3_18 | R6 | | | | | | | | | | | | | | | | | | | |
| | CAL_1.23 | 177-184 | D3_6 | OC_1.23 | 1_B3_14 | U4 | | | | | | | | | | | | | | | | | | | |
| | CAL_1.24 | 185-192 | D4_6 | OC_1.24 | 1_B3_17 | T5 | | | | | | | | | | | | | | | | | | | |
| | CAL_1.25 | 193-200 | D1_7 | OC_1.25 | 2_B3_04 | N5 | S_DMM_4 | OC_DMM4 | 1_B0_55 | C17 | | | | | | | | | | | | | | | |
| | CAL_1.26 | 201-208 | D2_7 | OC_1.26 | 2_B0_53 | D15 | | | | | | | | | | | | | | | | | | | |
| | CAL_1.27 | 209-216 | D3_7 | OC_1.27 | 2_B4_15 | P3 | | | | | | | | | | | | | | | | | | | |
| | CAL_1.28 | 217-224 | D4_7 | OC_1.28 | 2_B4_17 | M4 | | | | | | | | | | | | | | | | | | | |
| | CAL_1.29 | 225-232 | D1_8 | OC_1.29 | 2_B3_18 | R6 | | | | | | | | | | | | | | | | | | | |
| | CAL_1.30 | 233-240 | D2_8 | OC_1.30 | 2_B3_17 | T5 | | | | | | | | | | | | | | | | | | | |
| | CAL_1.31 | 241-248 | D3_8 | OC_1.31 | 2_B3_12 | P6 | | | | | | | | | | | | | | | | | | | |
| | CAL_1.32 | 249-256 | D4_8 | OC_1.32 | 2_B3_14 | U4 | | | | | | | | | | | | | | | | | | | |
| 2 | CAL_2.01 | 001-008 | D1_9 | OC_2.01 | 1_B0_45 | E16 | S_DMM_5 | OC_DMM5 | 1_B2_36 | AB10 | DMM2 | 2_CAL | PMU_RC2 | 3_B1_38 | N18 | | | | | | | | | | |
| | CAL_2.02 | 009-016 | D2_9 | OC_2.02 | 1_B0_44 | F16 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.03 | 017-024 | D3_9 | OC_2.03 | 1_B0_51 | D16 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.04 | 025-032 | D4_9 | OC_2.04 | 1_B0_43 | G15 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.05 | 033-040 | D1_10 | OC_2.05 | 1_B1_06 | C22 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.06 | 041-048 | D2_10 | OC_2.06 | 1_B1_48 | D20 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.07 | 049-056 | D3_10 | OC_2.07 | 1_B1_49 | D21 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.08 | 057-064 | D4_10 | OC_2.08 | 1_B1_12 | D22 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.09 | 065-072 | D1_11 | OC_2.09 | 2_B5_10 | C1 | S_DMM_6 | OC_DMM6 | 1_B2_37 | AA11 | | | | | | | | | | | | | | | |
| | CAL_2.10 | 073-080 | D2_11 | OC_2.10 | 2_B5_02 | C2 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.11 | 081-088 | D3_11 | OC_2.11 | 2_B5_01 | C3 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.12 | 089-096 | D4_11 | OC_2.12 | 2_B5_09 | B1 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.13 | 097-104 | D1_12 | OC_2.13 | 2_B5_29 | H5 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.14 | 105-112 | D2_12 | OC_2.14 | 2_B5_11 | H6 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.15 | 113-120 | D3_12 | OC_2.15 | 2_B5_26 | H2 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.16 | 121-128 | D4_12 | OC_2.16 | 2_B5_25 | H3 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.17 | 129-136 | D1_13 | OC_2.17 | 1_B0_58 | A17 | S_DMM_7 | OC_DMM7 | 1_B2_40 | AA12 | | | | | | | | | | | | | | | |
| | CAL_2.18 | 137-144 | D2_13 | OC_2.18 | 1_B0_56 | A18 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.19 | 145-152 | D3_13 | OC_2.19 | 1_B0_49 | C18 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.20 | 153-160 | D4_13 | OC_2.20 | 1_B0_42 | D18 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.21 | 161-168 | D1_14 | OC_2.21 | 1_B0_61 | G13 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.22 | 169-176 | D2_14 | OC_2.22 | 1_B0_46 | F15 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.23 | 177-184 | D3_14 | OC_2.23 | 1_B0_62 | F13 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.24 | 185-192 | D4_14 | OC_2.24 | 1_B0_71 | G12 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.25 | 193-200 | D1_15 | OC_2.25 | 2_B3_26 | T7 | S_DMM_8 | OC_DMM8 | 1_B2_41 | AB13 | | | | | | | | | | | | | | | |
| | CAL_2.26 | 201-208 | D2_15 | OC_2.26 | 2_B3_25 | U5 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.27 | 209-216 | D3_15 | OC_2.27 | 2_B2_05 | W5 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.28 | 217-224 | D4_15 | OC_2.28 | 2_B3_22 | T6 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.29 | 225-232 | D1_16 | OC_2.29 | 2_B0_17 | E8 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.30 | 233-240 | D2_16 | OC_2.30 | 2_B0_19 | E9 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.31 | 241-248 | D3_16 | OC_2.31 | 2_B0_25 | E10 | | | | | | | | | | | | | | | | | | | |
| | CAL_2.32 | 249-256 | D4_16 | OC_2.32 | 2_B0_30 | D11 | | | | | | | | | | | | | | | | | | | |
| 3 | CAL_3.01 | 001-008 | D1_17 | OC_3.01 | 1_B3_03 | M3 | S_DMM_10 | OC_DMM10 | 1_B0_59 | D14 | DMM3 | 3_CAL | PMU_RC3 | 3_B1_63 | P19 | | | | | | | | | | |
| | CAL_3.02 | 009-016 | D2_17 | OC_3.02 | 1_B4_16 | R1 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.03 | 017-024 | D3_17 | OC_3.03 | 1_B4_20 | N2 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.04 | 025-032 | D4_17 | OC_3.04 | 1_B4_19 | N1 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.05 | 033-040 | D1_18 | OC_3.05 | 1_B1_09 | F19 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.06 | 041-048 | D2_18 | OC_3.06 | 1_B1_47 | E19 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.07 | 049-056 | D3_18 | OC_3.07 | 1_B0_40 | C20 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.08 | 057-064 | D4_18 | OC_3.08 | 1_B0_39 | B20 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.09 | 065-072 | D1_19 | OC_3.09 | 2_B0_34 | A11 | S_DMM_9 | OC_DMM9 | 1_B0_53 | D15 | | | | | | | | | | | | | | | |
| | CAL_3.10 | 073-080 | D2_19 | OC_3.10 | 2_B0_73 | A12 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.11 | 081-088 | D3_19 | OC_3.11 | 2_B0_74 | B12 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.12 | 089-096 | D4_19 | OC_3.12 | 2_B0_75 | A13 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.13 | 097-104 | D1_20 | OC_3.13 | 2_B0_50 | B19 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.14 | 105-112 | D2_20 | OC_3.14 | 2_B0_49 | C18 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.15 | 113-120 | D3_20 | OC_3.15 | 2_B0_58 | A17 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.16 | 121-128 | D4_20 | OC_3.16 | 2_B0_64 | B16 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.17 | 129-136 | D1_21 | OC_3.17 | 1_B0_17 | E8 | S_DMM_11 | OC_DMM11 | 1_B0_69 | C13 | | | | | | | | | | | | | | | |
| | CAL_3.18 | 137-144 | D2_21 | OC_3.18 | 1_B0_19 | E9 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.19 | 145-152 | D3_21 | OC_3.19 | 1_B0_25 | E10 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.20 | 153-160 | D4_21 | OC_3.20 | 1_B0_30 | D11 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.21 | 161-168 | D1_22 | OC_3.21 | 1_B0_10 | E7 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.22 | 169-176 | D2_22 | OC_3.22 | 1_B0_12 | D7 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.23 | 177-184 | D3_22 | OC_3.23 | 1_B0_18 | D8 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.24 | 185-192 | D4_22 | OC_3.24 | 1_B0_28 | B8 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.25 | 193-200 | D1_23 | OC_3.25 | 2_B0_76 | B13 | S_DMM_12 | OC_DMM12 | 1_B0_72 | F12 | | | | | | | | | | | | | | | |
| | CAL_3.26 | 201-208 | D2_23 | OC_3.26 | 2_B0_70 | B14 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.27 | 209-216 | D3_23 | OC_3.27 | 2_B0_67 | B15 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.28 | 217-224 | D4_23 | OC_3.28 | 2_B0_68 | C15 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.29 | 225-232 | D1_24 | OC_3.29 | 2_B1_17 | G21 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.30 | 233-240 | D2_24 | OC_3.30 | 2_B1_51 | E22 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.31 | 241-248 | D3_24 | OC_3.31 | 2_B1_50 | E20 | | | | | | | | | | | | | | | | | | | |
| | CAL_3.32 | 249-256 | D4_24 | OC_3.32 | 2_B1_49 | D21 | | | | | | | | | | | | | | | | | | | |
| 4 | CAL_4.01 | 001-008 | D1_25 | OC_4.01 | 1_B0_75 | A13 | S_DMM_13 | OC_DMM13 | 1_B2_49 | W12 | DMM4 | 4_CAL | PMU_RC4 | 3_B1_63 | P18 | | | | | | | | | | |
| | CAL_4.02 | 009-016 | D2_25 | OC_4.02 | 1_B0_76 | B13 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.03 | 017-024 | D3_25 | OC_4.03 | 1_B0_70 | B14 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.04 | 025-032 | D4_25 | OC_4.04 | 1_B0_67 | B15 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.05 | 033-040 | D1_26 | OC_4.05 | 1_B0_50 | B19 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.06 | 041-048 | D2_26 | OC_4.06 | 1_B0_65 | D12 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.07 | 049-056 | D3_26 | OC_4.07 | 1_B0_60 | E14 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.08 | 057-064 | D4_26 | OC_4.08 | 1_B0_54 | E15 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.09 | 065-072 | D1_27 | OC_4.09 | 2_B5_22 | G1 | S_DMM_14 | OC_DMM14 | 1_B2_50 | V12 | | | | | | | | | | | | | | | |
| | CAL_4.10 | 073-080 | D2_27 | OC_4.10 | 2_B5_21 | G2 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.11 | 081-088 | D3_27 | OC_4.11 | 2_B5_18 | G3 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.12 | 089-096 | D4_27 | OC_4.12 | 2_B5_17 | F1 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.13 | 097-104 | D1_27 | OC_4.13 | 2_B0_04 | C4 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.14 | 105-112 | D2_27 | OC_4.14 | 2_B0_14 | C5 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.15 | 113-120 | D3_27 | OC_4.15 | 2_B0_32 | G11 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.16 | 121-128 | D4_27 | OC_4.16 | 2_B0_29 | E11 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.17 | 129-136 | D1_29 | OC_4.17 | 1_B0_68 | C15 | S_DMM_15 | OC_DMM15 | 1_B2_51 | Y12 | | | | | | | | | | | | | | | |
| | CAL_4.18 | 137-144 | D2_29 | OC_4.18 | 1_B0_63 | A16 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.19 | 145-152 | D3_29 | OC_4.19 | 1_B0_64 | B16 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.20 | 153-160 | D4_29 | OC_4.20 | 1_B0_57 | C16 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.21 | 161-168 | D1_30 | OC_4.21 | 1_B0_66 | E12 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.22 | 169-176 | D1_30 | OC_4.22 | 1_B0_48 | A21 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.23 | 177-184 | D1_30 | OC_4.23 | 1_B1_05 | B22 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.24 | 185-192 | D1_30 | OC_4.24 | 1_B1_46 | C21 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.25 | 193-200 | D1_31 | OC_4.25 | 2_B5_31 | E1 | S_DMM_16 | OC_DMM16 | 1_B2_52 | V13 | | | | | | | | | | | | | | | |
| | CAL_4.26 | 201-208 | D1_29 | OC_4.26 | 2_B5_14 | D1 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.27 | 209-216 | D1_29 | OC_4.27 | 2_B5_13 | E2 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.28 | 217-224 | D1_29 | OC_4.28 | 2_B5_06 | D3 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.29 | 225-232 | D1_29 | OC_4.29 | 2_B0_26 | C11 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.30 | 233-240 | D1_29 | OC_4.30 | 2_B0_07 | A2 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.31 | 241-248 | D1_29 | OC_4.31 | 2_B0_01 | B3 | | | | | | | | | | | | | | | | | | | |
| | CAL_4.32 | 249-256 | D1_29 | OC_4.32 | 2_B0_08 | A3 | | | | | | | | | | | | | | | | | | | |
---
1.Docs/NewCalBoard_DIG_SYY.xlsx
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2.FW/CPLD1/.run_manager.ini
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[Runmanager] [Runmanager]
Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\x3\x30\0\0\x1!\0\0\x4\x11\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0) Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\x3\x30\0\0\x1!\0\0\x4\r\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
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2.FW/CPLD1/.spreadsheet_view.ini
+39 -39
View File
@@ -6,40 +6,40 @@ sig_sort_ascending=true
active_Sheet=Port Assignments active_Sheet=Port Assignments
[Port%20Assignments] [Port%20Assignments]
Name="202,0" Name="207,0"
Group%20By="111,1" Group%20By="118,1"
Pin="62,2" Pin="71,2"
BANK="85,3" BANK="91,3"
BANK_VCC="125,4" BANK_VCC="129,4"
VREF="81,5" VREF="85,5"
IO_TYPE="216,6" IO_TYPE="111,6"
PULLMODE="127,7" PULLMODE="133,7"
DRIVE="86,8" DRIVE="92,8"
SLEWRATE="126,9" SLEWRATE="129,9"
CLAMP="95,10" CLAMP="99,10"
OPENDRAIN="133,11" OPENDRAIN="139,11"
DIFFRESISTOR="155,12" DIFFRESISTOR="160,12"
DIFFDRIVE="122,13" DIFFDRIVE="127,13"
HYSTERESIS="140,14" HYSTERESIS="143,14"
Outload%20%28pF%29="133,15" Outload%20%28pF%29="144,15"
MaxSkew="111,16" MaxSkew="120,16"
Clock%20Load%20Only="165,17" Clock%20Load%20Only="172,17"
SwitchingID="129,18" SwitchingID="141,18"
Ground%20plane%20PCB%20noise%20%28mV%29="267,19" Ground%20plane%20PCB%20noise%20%28mV%29="274,19"
Power%20plane%20PCB%20noise%20%28mV%29="257,20" Power%20plane%20PCB%20noise%20%28mV%29="266,20"
SSO%20Allowance%28%25%29="181,21" SSO%20Allowance%28%25%29="189,21"
sort_columns="Name,Ascending" sort_columns="Name,Ascending"
[Pin%20Assignments] [Pin%20Assignments]
Pin="102,0" Pin="111,0"
Pad%20Name="116,1" Pad%20Name="126,1"
Dual%20Function="144,2" Dual%20Function="157,2"
Polarity="97,3" Polarity="108,3"
BANK="0,4" BANK="0,4"
BANK_VCC="125,5" BANK_VCC="129,5"
IO_TYPE="105,6" IO_TYPE="111,6"
Signal%20Name="134,7" Signal%20Name="144,7"
Signal%20Type="127,8" Signal%20Type="137,8"
sort_columns="Pin,Ascending" sort_columns="Pin,Ascending"
[Clock%20Resource] [Clock%20Resource]
@@ -48,8 +48,8 @@ Clock%20Name="215,ELLIPSIS"
Selection="100,ELLIPSIS" Selection="100,ELLIPSIS"
[Global%20Preferences] [Global%20Preferences]
Preference%20Name="234,ELLIPSIS" Preference%20Name="230,ELLIPSIS"
Preference%20Value="227,ELLIPSIS" Preference%20Value="232,ELLIPSIS"
[Cell%20Mapping] [Cell%20Mapping]
Type="100,ELLIPSIS" Type="100,ELLIPSIS"
@@ -63,14 +63,14 @@ Name="100,ELLIPSIS"
Prioritize="100,ELLIPSIS" Prioritize="100,ELLIPSIS"
[Timing%20Preferences] [Timing%20Preferences]
Preference%20Name="140,ELLIPSIS" Preference%20Name="146,ELLIPSIS"
Preference%20Value="138,ELLIPSIS" Preference%20Value="143,ELLIPSIS"
Preference%20Unit="128,ELLIPSIS" Preference%20Unit="133,ELLIPSIS"
[Group] [Group]
Group%20Type\Name="147,ELLIPSIS" Group%20Type\Name="153,ELLIPSIS"
Value="51,ELLIPSIS" Value="53,ELLIPSIS"
[Misc%20Preferences] [Misc%20Preferences]
Preference%20Name="140,ELLIPSIS" Preference%20Name="146,ELLIPSIS"
Preference%20Value="138,ELLIPSIS" Preference%20Value="143,ELLIPSIS"
2.FW/CPLD1/BUS_Con.v
+1 -3
View File
@@ -152,8 +152,6 @@ module BUS_Con (
// --- 4. Register Control FSM --- // --- 4. Register Control FSM ---
always @(posedge i_sys_clk) begin always @(posedge i_sys_clk) begin
if (!i_rst_n) begin if (!i_rst_n) begin
state <= IDLE; state <= IDLE;
@@ -210,6 +208,6 @@ module BUS_Con (
assign o_wready = (state == IDLE); assign o_wready = (state == IDLE);
// Pass through unused signal or hook it up if needed // Pass through unused signal or hook it up if needed
assign o_rvalid = 1'b0; assign o_rvalid = i_rvalid;
endmodule endmodule
2.FW/CPLD1/CPLD_Con.v
+287 -101
View File
@@ -2,16 +2,40 @@ module CPLD_Con (
input i_sys_clk, input i_sys_clk,
input i_rst_n, input i_rst_n,
input i_con_exec, input i_con_exec,
// Freq Relay Control
input [23:0]i_freq_relay1, input [23:0]i_freq_relay1,
input [23:0]i_freq_relay2, input [23:0]i_freq_relay2,
input [23:0]i_freq_relay3, input [23:0]i_freq_relay3,
input [23:0]i_freq_relay4, input [23:0]i_freq_relay4,
output o_con_done,
// DC related Control
input [23:0]i_DC_Con1,
input [23:0]i_DC_Con2,
input [23:0]i_DC_Con3,
input [23:0]i_DC_Con4,
//Output RELAYs
output [3:0]o_OC_x01, output [3:0]o_OC_x01,
output [3:0]o_OC_x17, output [3:0]o_OC_x17,
output [18:0]o_DMM_EN, output [18:0]o_DMM_EN,
output o_IO_RC1, output o_IO_RC1,
output [4:0]o_RC_Tx, output [5:0]o_RC_Tx,
output [31:0]o_PMU_OC_1 ,
output [31:0]o_PMU_OC_2 ,
output [31:0]o_PMU_OC_3 ,
output [31:0]o_PMU_OC_4 ,
// DMM Mode Sel
output o_RC_VSel,
output o_RC_ISel,
// Output RLoad Sel
output [17:0]o_RC_RLSel,
// FLAGs
output o_con_done,
output o_err output o_err
); );
@@ -20,13 +44,26 @@ module CPLD_Con (
reg [3:0]OC_x17 ; reg [3:0]OC_x17 ;
reg [18:0]DMM_en ; reg [18:0]DMM_en ;
reg[4:0]RC_Tx; reg[5:0]RC_Tx;
reg io_RC; reg io_RC;
reg RC_VISel;
reg [17:0]RC_RLSel ;
reg [31:0]PMU_OC_1 ;
reg [31:0]PMU_OC_2 ;
reg [31:0]PMU_OC_3 ;
reg [31:0]PMU_OC_4 ;
//Condition Tester
reg [15:0]en_t ;
reg freq_t;
reg dc_t;
//Flags //Flags
reg exec_flag; reg exec_flag;
reg err_flag; reg err_flag;
reg [3:0]slot_exec_flag; reg [3:0]freq_slot_flag;
reg [3:0]dc_slot_flag ;
reg done_flag; reg done_flag;
//Counter //Counter
@@ -46,130 +83,269 @@ module CPLD_Con (
end end
end end
//Function Identify
always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin
en_t <= 'd0;
freq_t <= 'd0;
dc_t <= 'd0;
end
else begin
en_t <= (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) + (i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0] );
freq_t <= i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0];
dc_t <= i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0];
end
end
// Main Controller Function
always @(posedge i_sys_clk) begin always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin if (i_rst_n == 1'b0) begin
exec_flag <= 1'b0; exec_flag <= 1'b0;
err_flag <= 1'b0; err_flag <= 1'b0;
slot_exec_flag <= 'd0;
OC_x01 <= 'd0; freq_slot_flag <= 'd0;
OC_x17 <= 'd0; dc_slot_flag <= 'd0;
io_RC <= 'd0;
OC_x01 <= 'd0;
OC_x17 <= 'd0;
DMM_en <= 'd0;
RC_VISel <='d0;
RC_RLSel <='d0;
PMU_OC_1 <= 'd0 ;
PMU_OC_2 <= 'd0 ;
PMU_OC_3 <= 'd0 ;
PMU_OC_4 <= 'd0 ;
done_flag <= 'd1; done_flag <= 'd1;
end end
else begin else begin
if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin
exec_flag <= 1'b1;
done_flag <= 1'b0;
//To DO: More Sanity Check? //To DO: More Sanity Check?
if (i_freq_relay1[0] && i_freq_relay2[0] && i_freq_relay3[0] && i_freq_relay4[0]) begin if (en_t > 'd1) begin //Only ONE Enable bit should be set!
err_flag <= 1'b1; err_flag <= 1'b1;
end end
else begin else begin
slot_exec_flag[0] <= i_freq_relay1[0]; exec_flag <= 1'b1;
slot_exec_flag[1] <= i_freq_relay2[0]; done_flag <= 1'b0;
slot_exec_flag[2] <= i_freq_relay3[0]; err_flag <= 1'b0;
slot_exec_flag[3] <= i_freq_relay4[0]; freq_slot_flag[0] <= i_freq_relay1[0];
RC_Tx <= i_freq_relay4[14:10]; freq_slot_flag[1] <= i_freq_relay2[0];
freq_slot_flag[2] <= i_freq_relay3[0];
freq_slot_flag[3] <= i_freq_relay4[0];
RC_Tx <= i_freq_relay4[17:12]; //Special Relay for slot4
dc_slot_flag[0] <= i_DC_Con1[0];
dc_slot_flag[1] <= i_DC_Con2[0];
dc_slot_flag[2] <= i_DC_Con3[0];
dc_slot_flag[3] <= i_DC_Con4[0];
end end
end end
else if (exec_flag == 1'b1) begin else if (exec_flag == 1'b1) begin
io_RC <= i_freq_relay1[0] || i_freq_relay2[0] || i_freq_relay3[0] || i_freq_relay4[0]; if (freq_t == 1'b1) begin
case (slot_exec_flag) io_RC <= i_freq_relay1[0] || i_freq_relay2[0] || i_freq_relay3[0] || i_freq_relay4[0];
4'b0001: begin case (freq_slot_flag)
if (i_freq_relay1[9:1] < 9) begin 4'b0001: begin
OC_x01 <= 4'b0001; if (i_freq_relay1[9:1] < 9) begin
OC_x17 <= 'd0; OC_x01 <= 4'b0001;
DMM_en <= 19'b000_0000_0000_0000_0001; OC_x17 <= 'd0;
DMM_en <= 19'b000_0000_0000_0000_0001;
end
else if (i_freq_relay1[9:1] < 73) begin
DMM_en <= 19'b000_0000_0000_0000_0010;
OC_x01 <= 'd0;
OC_x17 <= 'd0;
end
else if (i_freq_relay1[9:1] < 137) begin
OC_x17 <= 4'b0001;
OC_x01 <= 'd0;
DMM_en <= 19'b000_0000_0000_0000_0100;
end
else begin
DMM_en <= 19'b000_0000_0000_0000_1000;
OC_x01 <= 'd0;
OC_x17 <= 'd0;
end
end end
else if (i_freq_relay1[9:1] < 73) begin 4'b0010: begin
DMM_en <= 19'b000_0000_0000_0000_0010; if (i_freq_relay2[9:1] < 9) begin
OC_x01 <= 'd0; OC_x01 <= 4'b0010;
OC_x17 <= 'd0; OC_x17 <= 'd0;
DMM_en <= 19'b000_0000_0000_0001_0000;
end
else if (i_freq_relay2[9:1] < 73) begin
DMM_en <= 19'b000_0000_0000_0010_0000;
OC_x01 <= 'd0;
OC_x17 <= 'd0;
end
else if (i_freq_relay2[9:1] < 137) begin
OC_x17 <= 4'b0010;
OC_x01 <= 'd0;
DMM_en <= 19'b000_0000_0000_0100_0000;
end
else begin
OC_x01 <= 'd0;
OC_x17 <= 'd0;
DMM_en <= 19'b000_0000_0000_1000_0000;
end
end end
else if (i_freq_relay1[9:1] < 137) begin 4'b0100: begin
OC_x17 <= 4'b0001; if (i_freq_relay3[9:1] < 9) begin
OC_x01 <= 'd0; OC_x01 <= 'b0100;
DMM_en <= 19'b000_0000_0000_0000_0100; OC_x17 <= 'd0;
DMM_en <= 19'b000_0000_0001_0000_0000;
end
else if ((i_freq_relay3[9:1] > 64)& (i_freq_relay3[9:1] < 73)) begin
OC_x01 <= 4'b0000;
OC_x17 <= 'd0;
DMM_en <= 19'b000_0000_0010_0000_0000;
end
else if (i_freq_relay3[9:1] < 137) begin
DMM_en <= 19'b000_0000_0100_0000_0000;
OC_x01 <= 'd0;
OC_x17 <= 'b0100;
end
else if (i_freq_relay3[9:1] < 201) begin
OC_x17 <= 4'd0;
OC_x01 <= 'd0;
DMM_en <= 16'b000_0000_1000_0000_0000;
end
end end
else begin 4'b1000: begin
DMM_en <= 19'b000_0000_0000_0000_1000; if (i_freq_relay4[9:1] < 9) begin
OC_x01 <= 'd0; OC_x01 <= 4'b1000;
OC_x17 <= 'd0; OC_x17 <= 'd0;
DMM_en <= 19'b000_0001_0000_0000_0000;
end
else if (i_freq_relay4[9:1] < 72) begin
DMM_en <= 19'b000_0010_0000_0000_0000;
OC_x01 <= 'd0;
OC_x17 <= 'd0;
end
else if (i_freq_relay4[9:1] < 137) begin
OC_x17 <= 4'b1000;
OC_x01 <= 'd0;
DMM_en <= 19'b000_0100_0000_0000_0000;
end
else begin
OC_x01 <= 'd0;
OC_x17 <= 'd0;
DMM_en <= 19'b000_1000_0000_0000_0000;
end
end end
end default: begin // You Should NOT be HERE
4'b0010: begin
if (i_freq_relay2[9:1] < 9) begin
OC_x01 <= 4'b0010;
OC_x17 <= 'd0;
DMM_en <= 19'b000_0000_0000_0001_0000;
end
else if (i_freq_relay2[9:1] < 73) begin
DMM_en <= 19'b000_0000_0000_0010_0000;
OC_x01 <= 'd0;
OC_x17 <= 'd0;
end
else if (i_freq_relay2[9:1] < 137) begin
OC_x17 <= 4'b0010;
OC_x01 <= 'd0;
DMM_en <= 19'b000_0000_0000_0100_0000;
end
else begin
OC_x01 <= 'd0;
OC_x17 <= 'd0;
DMM_en <= 19'b000_0000_0000_1000_0000;
end
end
4'b0100: begin
if (i_freq_relay3[9:1] < 9) begin
OC_x01 <= 'b0100;
OC_x17 <= 'd0;
DMM_en <= 19'b000_0000_0001_0000_0000;
end
else if ((i_freq_relay3[9:1] > 64)& (i_freq_relay3[9:1] < 73)) begin
OC_x01 <= 4'b0000; OC_x01 <= 4'b0000;
OC_x17 <= 'd0; OC_x17 <= 4'b0000;
DMM_en <= 19'b000_0000_0010_0000_0000; DMM_en <= 'd0;
end end
else if (i_freq_relay3[9:1] < 137) begin endcase
DMM_en <= 19'b000_0000_0100_0000_0000; end
OC_x01 <= 'd0; else if (dc_t == 1'b1) begin
OC_x17 <= 'b0100; case (dc_slot_flag)
4'b0001: begin
if (i_DC_Con1[22] == 1'b1) begin
RC_VISel <= 1'b1; //Select Current
end
else begin
RC_VISel <= 1'b0; //Select Voltage
end
//Sanity Check
if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18) || (i_DC_Con1[9:1] < 1) || (i_DC_Con1[9:1] > 256)) begin
err_flag <= 1'b1;
end
else begin
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con1[21:17] - 1);
if (i_DC_Con1[23] == 1'b0) begin //Select PMU
PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con1[9:1]/8);
DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con1[9:1]/8);
end
else if (i_DC_Con1[23] == 1'b1) begin //Select DPS
end
end
end end
else if (i_freq_relay3[9:1] < 201) begin 4'b0010: begin
OC_x17 <= 4'd0; if (i_DC_Con2[22] == 1'b1) begin
OC_x01 <= 'd0; RC_VISel <= 1'b1; //Select Current
DMM_en <= 16'b000_0000_1000_0000_0000; end
else begin
RC_VISel <= 1'b0; //Select Voltage
end
//Sanity Check
if ((i_DC_Con2[21:17] < 1) || (i_DC_Con2[21:17] > 18) || (i_DC_Con2[9:1] < 1) || (i_DC_Con2[9:1] > 256)) begin
err_flag <= 1'b1;
end
else begin
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con2[21:17] - 1);
if (i_DC_Con2[23] == 1'b0) begin //Select PMU
PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con2[9:1]/8);
DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con2[9:1]/8);
end
else if (i_DC_Con2[23] == 1'b1) begin //Select DPS
end
end
end end
end 4'b0100:begin
4'b1000: begin if (i_DC_Con3[22] == 1'b1) begin
if (i_freq_relay4[9:1] < 9) begin RC_VISel <= 1'b1; //Select Current
OC_x01 <= 4'b1000; end
OC_x17 <= 'd0; else begin
DMM_en <= 19'b000_0001_0000_0000_0000; RC_VISel <= 1'b0; //Select Voltage
end
//Sanity Check
if ((i_DC_Con3[21:17] < 1) || (i_DC_Con3[21:17] > 18) || (i_DC_Con3[9:1] < 1) || (i_DC_Con3[9:1] > 256)) begin
err_flag <= 1'b1;
end
else begin
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con3[21:17] - 1);
if (i_DC_Con3[23] == 1'b0) begin //Select PMU
PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con3[9:1]/8);
DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con3[9:1]/8);
end
else if (i_DC_Con3[23] == 1'b1) begin //Select DPS
end
end
end end
else if (i_freq_relay4[9:1] < 72) begin 4'b1000:begin
DMM_en <= 19'b000_0010_0000_0000_0000; if (i_DC_Con4[22] == 1'b1) begin
OC_x01 <= 'd0; RC_VISel <= 1'b1; //Select Current
OC_x17 <= 'd0; end
else begin
RC_VISel <= 1'b0; //Select Voltage
end
//Sanity Check
if ((i_DC_Con4[21:17] < 1) || (i_DC_Con4[21:17] > 18) || (i_DC_Con4[9:1] < 1) || (i_DC_Con4[9:1] > 256)) begin
err_flag <= 1'b1;
end
else begin
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con4[21:17] - 1);
if (i_DC_Con4[23] == 1'b0) begin //Select PMU
PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con4[9:1]/8);
DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con4[9:1]/8);
end
else if (i_DC_Con4[23] == 1'b1) begin //Select DPS
end
end
end end
else if (i_freq_relay4[9:1] < 137) begin default:begin // You Should NOT be HERE
OC_x17 <= 4'b1000; RC_VISel <='d0;
OC_x01 <= 'd0; RC_RLSel <='d0;
DMM_en <= 19'b000_0100_0000_0000_0000;
PMU_OC_1 <= 'd0 ;
PMU_OC_2 <= 'd0 ;
PMU_OC_3 <= 'd0 ;
PMU_OC_4 <= 'd0 ;
DMM_en <= 'd0;
end end
else begin endcase
OC_x01 <= 'd0; end
OC_x17 <= 'd0;
DMM_en <= 19'b000_1000_0000_0000_0000;
end
end
default: begin
OC_x01 <= 4'b0000;
OC_x17 <= 4'b0000;
DMM_en <= 'd0;
end
endcase
done_flag <= 1'b1; done_flag <= 1'b1;
end end
end end
@@ -186,5 +362,15 @@ module CPLD_Con (
assign o_err = err_flag; assign o_err = err_flag;
assign o_RC_Tx = RC_Tx; assign o_RC_Tx = RC_Tx;
assign o_RC_ISel = (RC_VISel==1'b1)?1:0;
assign o_RC_VSel = (RC_VISel==1'b1)?0:1;
assign o_RC_RLSel = RC_RLSel;
assign o_PMU_OC_1 = PMU_OC_1;
assign o_PMU_OC_2 = PMU_OC_2;
assign o_PMU_OC_3 = PMU_OC_3;
assign o_PMU_OC_4 = PMU_OC_4;
endmodule endmodule
2.FW/CPLD1/NewExtIns_CPLD1.lpf
+258 -192
View File
@@ -18,7 +18,6 @@ IOBUF PORT "i_mosi" IO_TYPE=LVCMOS33 ;
IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 ;
IOBUF PORT "i_sclk" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_sclk" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ; IOBUF PORT "o_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ;
IOBUF PORT "o_rvaild" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "i_sys_clk" DRIVE=NA IO_TYPE=LVCMOS33 SLEWRATE=NA PULLMODE=DOWN ; IOBUF PORT "i_sys_clk" DRIVE=NA IO_TYPE=LVCMOS33 SLEWRATE=NA PULLMODE=DOWN ;
IOBUF PORT "o_err" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_err" IO_TYPE=LVCMOS33 ;
@@ -54,194 +53,261 @@ LOCATE COMP "o_DMM_EN[15]" SITE "V13" ;
LOCATE COMP "o_IO_RC1" SITE "F10" ; LOCATE COMP "o_IO_RC1" SITE "F10" ;
IOBUF PORT "o_IO_RC1" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_IO_RC1" IO_TYPE=LVCMOS33 ;
BLOCK JTAGPATHS ; BLOCK JTAGPATHS ;
LOCATE COMP "o_OC_1[0]" SITE "M19" ; LOCATE COMP "o_PMU_OC_1[0]" SITE "M19" ;
LOCATE COMP "o_OC_1[1]" SITE "R16" ; LOCATE COMP "o_PMU_OC_1[1]" SITE "R16" ;
LOCATE COMP "o_OC_1[2]" SITE "N20" ; LOCATE COMP "o_PMU_OC_1[2]" SITE "N20" ;
LOCATE COMP "o_OC_1[3]" SITE "P20" ; LOCATE COMP "o_PMU_OC_1[3]" SITE "P20" ;
LOCATE COMP "o_OC_1[4]" SITE "G19" ; LOCATE COMP "o_PMU_OC_1[4]" SITE "G19" ;
LOCATE COMP "o_OC_1[5]" SITE "J19" ; LOCATE COMP "o_PMU_OC_1[5]" SITE "J19" ;
LOCATE COMP "o_OC_1[6]" SITE "H16" ; LOCATE COMP "o_PMU_OC_1[6]" SITE "H16" ;
LOCATE COMP "o_OC_1[7]" SITE "J17" ; LOCATE COMP "o_PMU_OC_1[7]" SITE "J17" ;
LOCATE COMP "o_OC_1[16]" SITE "W6" ; LOCATE COMP "o_PMU_OC_1[16]" SITE "W6" ;
LOCATE COMP "o_OC_1[17]" SITE "AA7" ; LOCATE COMP "o_PMU_OC_1[17]" SITE "AA7" ;
LOCATE COMP "o_OC_1[18]" SITE "AB6" ; LOCATE COMP "o_PMU_OC_1[18]" SITE "AB6" ;
LOCATE COMP "o_OC_1[19]" SITE "Y7" ; LOCATE COMP "o_PMU_OC_1[19]" SITE "Y7" ;
LOCATE COMP "o_OC_1[20]" SITE "V4" ; LOCATE COMP "o_PMU_OC_1[20]" SITE "V4" ;
LOCATE COMP "o_OC_1[21]" SITE "R6" ; LOCATE COMP "o_PMU_OC_1[21]" SITE "R6" ;
LOCATE COMP "o_OC_1[22]" SITE "U4" ; LOCATE COMP "o_PMU_OC_1[22]" SITE "U4" ;
LOCATE COMP "o_OC_1[23]" SITE "T5" ; LOCATE COMP "o_PMU_OC_1[23]" SITE "T5" ;
LOCATE COMP "o_OC_2[0]" SITE "E16" ; LOCATE COMP "o_PMU_OC_2[0]" SITE "E16" ;
LOCATE COMP "o_OC_2[1]" SITE "F16" ; LOCATE COMP "o_PMU_OC_2[1]" SITE "F16" ;
LOCATE COMP "o_OC_2[2]" SITE "D16" ; LOCATE COMP "o_PMU_OC_2[2]" SITE "D16" ;
LOCATE COMP "o_OC_2[3]" SITE "G15" ; LOCATE COMP "o_PMU_OC_2[3]" SITE "G15" ;
LOCATE COMP "o_OC_2[4]" SITE "C22" ; LOCATE COMP "o_PMU_OC_2[4]" SITE "C22" ;
LOCATE COMP "o_OC_2[5]" SITE "D20" ; LOCATE COMP "o_PMU_OC_2[5]" SITE "D20" ;
LOCATE COMP "o_OC_2[6]" SITE "D21" ; LOCATE COMP "o_PMU_OC_2[6]" SITE "D21" ;
LOCATE COMP "o_OC_2[7]" SITE "D22" ; LOCATE COMP "o_PMU_OC_2[7]" SITE "D22" ;
LOCATE COMP "o_OC_2[16]" SITE "A17" ; LOCATE COMP "o_PMU_OC_2[16]" SITE "A17" ;
LOCATE COMP "o_OC_2[17]" SITE "A18" ; LOCATE COMP "o_PMU_OC_2[17]" SITE "A18" ;
LOCATE COMP "o_OC_2[18]" SITE "C18" ; LOCATE COMP "o_PMU_OC_2[18]" SITE "C18" ;
LOCATE COMP "o_OC_2[19]" SITE "D18" ; LOCATE COMP "o_PMU_OC_2[19]" SITE "D18" ;
LOCATE COMP "o_OC_2[20]" SITE "G13" ; LOCATE COMP "o_PMU_OC_2[20]" SITE "G13" ;
LOCATE COMP "o_OC_2[21]" SITE "F15" ; LOCATE COMP "o_PMU_OC_2[21]" SITE "F15" ;
LOCATE COMP "o_OC_2[22]" SITE "F13" ; LOCATE COMP "o_PMU_OC_2[22]" SITE "F13" ;
LOCATE COMP "o_OC_2[23]" SITE "G12" ; LOCATE COMP "o_PMU_OC_2[23]" SITE "G12" ;
LOCATE COMP "o_OC_3[0]" SITE "M3" ; LOCATE COMP "o_PMU_OC_3[0]" SITE "M3" ;
LOCATE COMP "o_OC_3[1]" SITE "R1" ; LOCATE COMP "o_PMU_OC_3[1]" SITE "R1" ;
LOCATE COMP "o_OC_3[2]" SITE "N2" ; LOCATE COMP "o_PMU_OC_3[2]" SITE "N2" ;
LOCATE COMP "o_OC_3[3]" SITE "N1" ; LOCATE COMP "o_PMU_OC_3[3]" SITE "N1" ;
LOCATE COMP "o_OC_3[4]" SITE "F19" ; LOCATE COMP "o_PMU_OC_3[4]" SITE "F19" ;
LOCATE COMP "o_OC_3[5]" SITE "E19" ; LOCATE COMP "o_PMU_OC_3[5]" SITE "E19" ;
LOCATE COMP "o_OC_3[7]" SITE "B20" ; LOCATE COMP "o_PMU_OC_3[7]" SITE "B20" ;
LOCATE COMP "o_OC_3[6]" SITE "C20" ; LOCATE COMP "o_PMU_OC_3[6]" SITE "C20" ;
LOCATE COMP "o_OC_3[16]" SITE "E8" ; LOCATE COMP "o_PMU_OC_3[16]" SITE "E8" ;
LOCATE COMP "o_OC_3[17]" SITE "E9" ; LOCATE COMP "o_PMU_OC_3[17]" SITE "E9" ;
LOCATE COMP "o_OC_3[18]" SITE "E10" ; LOCATE COMP "o_PMU_OC_3[18]" SITE "E10" ;
LOCATE COMP "o_OC_3[19]" SITE "D11" ; LOCATE COMP "o_PMU_OC_3[19]" SITE "D11" ;
LOCATE COMP "o_OC_3[20]" SITE "E7" ; LOCATE COMP "o_PMU_OC_3[20]" SITE "E7" ;
LOCATE COMP "o_OC_3[21]" SITE "D8" ; LOCATE COMP "o_PMU_OC_3[21]" SITE "D8" ;
LOCATE COMP "o_OC_3[22]" SITE "B8" ; LOCATE COMP "o_PMU_OC_3[22]" SITE "B8" ;
LOCATE COMP "o_OC_4[0]" SITE "A13" ; LOCATE COMP "o_PMU_OC_4[0]" SITE "A13" ;
LOCATE COMP "o_OC_4[1]" SITE "B13" ; LOCATE COMP "o_PMU_OC_4[1]" SITE "B13" ;
LOCATE COMP "o_OC_4[2]" SITE "B14" ; LOCATE COMP "o_PMU_OC_4[2]" SITE "B14" ;
LOCATE COMP "o_OC_4[3]" SITE "B15" ; LOCATE COMP "o_PMU_OC_4[3]" SITE "B15" ;
LOCATE COMP "o_OC_4[4]" SITE "B19" ; LOCATE COMP "o_PMU_OC_4[4]" SITE "B19" ;
LOCATE COMP "o_OC_4[5]" SITE "D12" ; LOCATE COMP "o_PMU_OC_4[5]" SITE "D12" ;
LOCATE COMP "o_OC_4[6]" SITE "E14" ; LOCATE COMP "o_PMU_OC_4[6]" SITE "E14" ;
LOCATE COMP "o_OC_4[7]" SITE "E15" ; LOCATE COMP "o_PMU_OC_4[7]" SITE "E15" ;
LOCATE COMP "o_OC_4[16]" SITE "C15" ; LOCATE COMP "o_PMU_OC_4[16]" SITE "C15" ;
LOCATE COMP "o_OC_4[17]" SITE "A16" ; LOCATE COMP "o_PMU_OC_4[17]" SITE "A16" ;
LOCATE COMP "o_OC_4[18]" SITE "B16" ; LOCATE COMP "o_PMU_OC_4[18]" SITE "B16" ;
LOCATE COMP "o_OC_4[19]" SITE "C16" ; LOCATE COMP "o_PMU_OC_4[19]" SITE "C16" ;
LOCATE COMP "o_OC_4[20]" SITE "E12" ; LOCATE COMP "o_PMU_OC_4[20]" SITE "E12" ;
LOCATE COMP "o_OC_4[21]" SITE "A21" ; LOCATE COMP "o_PMU_OC_4[21]" SITE "A21" ;
LOCATE COMP "o_OC_4[22]" SITE "B22" ; LOCATE COMP "o_PMU_OC_4[22]" SITE "B22" ;
LOCATE COMP "o_OC_4[23]" SITE "C21" ; LOCATE COMP "o_PMU_OC_4[23]" SITE "C21" ;
IOBUF PORT "o_OC_1[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ; IOBUF PORT "o_PMU_OC_1[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ;
IOBUF PORT "o_OC_1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[0]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_OC_1[0]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_OC_1[16]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_OC_1[16]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_OC_2[0]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_OC_2[0]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_OC_2[16]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_OC_2[16]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_OC_3[0]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_OC_3[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[16]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_OC_3[16]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_OC_4[0]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_OC_4[0]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_OC_4[16]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_OC_4[16]" IO_TYPE=LVCMOS33 ;
LOCATE COMP "o_RC_RLSel[1]" SITE "M4" ;
LOCATE COMP "o_RC_RLSel[2]" SITE "B10" ;
LOCATE COMP "o_RC_RLSel[3]" SITE "P3" ;
LOCATE COMP "o_RC_RLSel[4]" SITE "F5" ;
LOCATE COMP "o_RC_RLSel[5]" SITE "G10" ;
LOCATE COMP "o_RC_RLSel[6]" SITE "F6" ;
LOCATE COMP "o_RC_RLSel[7]" SITE "C8" ;
LOCATE COMP "o_RC_RLSel[8]" SITE "B7" ;
LOCATE COMP "o_RC_RLSel[9]" SITE "F8" ;
LOCATE COMP "o_RC_RLSel[10]" SITE "C5" ;
LOCATE COMP "o_RC_RLSel[11]" SITE "A3" ;
LOCATE COMP "o_RC_RLSel[12]" SITE "B11" ;
LOCATE COMP "o_RC_RLSel[13]" SITE "A5" ;
LOCATE COMP "o_RC_RLSel[14]" SITE "B4" ;
LOCATE COMP "o_RC_RLSel[15]" SITE "F11" ;
LOCATE COMP "o_RC_RLSel[16]" SITE "D9" ;
LOCATE COMP "o_RC_RLSel[17]" SITE "N5" ;
IOBUF PORT "o_RC_RLSel[0]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[1]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[2]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[3]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[4]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[5]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[6]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[7]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[8]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[9]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[10]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[11]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[12]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[13]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[14]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[15]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[16]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_RLSel[17]" IO_TYPE=LVCMOS33 ;
LOCATE COMP "o_RC_LOF[0]" SITE "F3" ;
LOCATE COMP "o_RC_LOF[1]" SITE "H4" ;
LOCATE COMP "o_RC_LOS[0]" SITE "G4" ;
LOCATE COMP "o_RC_LOS[1]" SITE "L6" ;
LOCATE COMP "o_RC_RLSel[0]" SITE "M6" ;
IOBUF PORT "o_RC_LOF[0]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_LOF[1]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_LOS[0]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_LOS[1]" IO_TYPE=LVCMOS33 ;
LOCATE COMP "o_RC_ISel" SITE "P6" ;
LOCATE COMP "o_RC_VSel" SITE "L7" ;
IOBUF PORT "o_RC_VSel" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_ISel" IO_TYPE=LVCMOS33 ;
LOCATE COMP "o_DMM_EN[16]" SITE "W11" ;
IOBUF PORT "o_DMM_EN[16]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DMM_EN[17]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_DMM_EN[18]" IO_TYPE=LVCMOS33 ;
LOCATE COMP "o_DMM_EN[17]" SITE "U10" ;
LOCATE COMP "o_DMM_EN[18]" SITE "T10" ;
LOCATE COMP "o_RC_T27" SITE "U13" ;
IOBUF PORT "o_RC_T27" IO_TYPE=LVCMOS33 ;
LOCATE COMP "o_RC_T28" SITE "U12" ;
LOCATE COMP "o_RC_T29" SITE "T12" ;
LOCATE COMP "o_RC_T30" SITE "T11" ;
LOCATE COMP "o_RC_T31" SITE "U11" ;
LOCATE COMP "o_RC_T32" SITE "V11" ;
IOBUF PORT "o_RC_T28" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_T29" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_T30" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_T31" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_RC_T32" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_con_done" IO_TYPE=LVCMOS33 ;
2.FW/CPLD1/Reg_file.v
+14 -2
View File
@@ -18,16 +18,24 @@ module Reg_file (
output o_exec, output o_exec,
// Direct Register Outputs // Direct Register Outputs
//Freq Regs
output [23:0] o_freq1, output [23:0] o_freq1,
output [23:0] o_freq2, output [23:0] o_freq2,
output [23:0] o_freq3, output [23:0] o_freq3,
output [23:0] o_freq4 output [23:0] o_freq4,
//DC Regs
output [23:0] o_DC1,
output [23:0] o_DC2,
output [23:0] o_DC3,
output [23:0] o_DC4
); );
// --- Parameters --- // --- Parameters ---
localparam REG_COUNT = 16; localparam REG_COUNT = 16;
localparam [23:0] localparam [23:0]
IDENT = 24'h200000 || 12'b0001_0000_0000, //CPLD1==1,version=1.0.0 IDENT = 24'h200000 | 12'b0001_0001_0000, //CPLD1==1,version=1.1.0
STATE_INIT = 24'h800000; STATE_INIT = 24'h800000;
// State Machine Definition // State Machine Definition
@@ -163,5 +171,9 @@ module Reg_file (
assign o_freq2 = regtable[3]; assign o_freq2 = regtable[3];
assign o_freq3 = regtable[4]; assign o_freq3 = regtable[4];
assign o_freq4 = regtable[5]; assign o_freq4 = regtable[5];
assign o_DC1 = regtable[6];
assign o_DC2 = regtable[7];
assign o_DC3 = regtable[8];
assign o_DC4 = regtable[9];
endmodule endmodule
2.FW/CPLD1/RelayConTop.v
+83 -21
View File
@@ -6,7 +6,7 @@ module RelayConTop (
input i_mosi, input i_mosi,
input i_cs, input i_cs,
output o_miso, output o_miso,
output o_rvalid, //output o_rvalid,
input i_rready, input i_rready,
input i_wvalid, input i_wvalid,
output o_wready, output o_wready,
@@ -19,15 +19,24 @@ module RelayConTop (
output o_RC_T29, output o_RC_T29,
output o_RC_T30, output o_RC_T30,
output o_RC_T31, output o_RC_T31,
output [31:0]o_OC_1, output o_RC_T32,
output [31:0]o_OC_2,
output [31:0]o_OC_3, output [17:0]o_RC_RLSel,
output [31:0]o_OC_4 output o_RC_VSel,
output o_RC_ISel,
output [1:0]o_RC_LOF, //Strange DMM_N port relay
output [1:0]o_RC_LOS,
output [31:0]o_PMU_OC_1,
output [31:0]o_PMU_OC_2,
output [31:0]o_PMU_OC_3,
output [31:0]o_PMU_OC_4
); );
wire [3:0]OC_x01; wire [3:0]OC_x01;
wire [3:0]OC_x17; wire [3:0]OC_x17;
wire [4:0]RC_Tx; wire [5:0]RC_Tx;
wire [18:0]DMM_EN; wire [18:0]DMM_EN;
wire IO_RC1; wire IO_RC1;
@@ -49,6 +58,27 @@ module RelayConTop (
wire [23:0]freq2_relay ; wire [23:0]freq2_relay ;
wire [23:0]freq3_relay ; wire [23:0]freq3_relay ;
wire [23:0]freq4_relay ; wire [23:0]freq4_relay ;
//DC Control Reg output
wire [23:0]DC_Con1 ;
wire [23:0]DC_Con2 ;
wire [23:0]DC_Con3 ;
wire [23:0]DC_Con4 ;
//PMU OC Control
wire [31:0]PMU_OC_1 ;
wire [31:0]PMU_OC_2 ;
wire [31:0]PMU_OC_3 ;
wire [31:0]PMU_OC_4 ;
//RL Control
wire [17:0]RC_RLSel ;
//DMM V Select
wire RC_VSel;
//DMM I Select
wire RC_ISel;
wire con_rvalid; wire con_rvalid;
wire con_done; wire con_done;
@@ -63,7 +93,7 @@ module RelayConTop (
.i_wvalid(i_wvalid), .i_wvalid(i_wvalid),
.i_reg_busy(reg_busy), .i_reg_busy(reg_busy),
.i_rdata(r_data), .i_rdata(r_data),
.o_cmd_valid(cmd_vaild), .o_cmd_valid(cmd_valid),
.o_wr(wr_flag), .o_wr(wr_flag),
.o_miso(o_miso), .o_miso(o_miso),
.o_rvalid(o_rvalid), .o_rvalid(o_rvalid),
@@ -76,7 +106,7 @@ module RelayConTop (
Reg_file CPLD_Reg_1( Reg_file CPLD_Reg_1(
.i_sys_clk(i_sys_clk), .i_sys_clk(i_sys_clk),
.i_rst_n(i_rst_n), .i_rst_n(i_rst_n),
.i_wr_req(cmd_vaild), .i_wr_req(cmd_valid),
.i_wr(wr_flag), .i_wr(wr_flag),
.i_addr(reg_addr), .i_addr(reg_addr),
.i_wdata(w_data), .i_wdata(w_data),
@@ -85,6 +115,10 @@ module RelayConTop (
.o_freq2(freq2_relay), //Freq_Slot2 .o_freq2(freq2_relay), //Freq_Slot2
.o_freq3(freq3_relay), //Freq_Slot3 .o_freq3(freq3_relay), //Freq_Slot3
.o_freq4(freq4_relay), //Freq_Slot4 .o_freq4(freq4_relay), //Freq_Slot4
.o_DC1(DC_Con1),
.o_DC2(DC_Con2),
.o_DC3(DC_Con3),
.o_DC4(DC_Con4),
.o_rvalid(con_rvalid), .o_rvalid(con_rvalid),
.o_rdata(r_data), .o_rdata(r_data),
.o_exec(con_exec), //Exec cmd .o_exec(con_exec), //Exec cmd
@@ -100,39 +134,67 @@ module RelayConTop (
.i_freq_relay2(freq2_relay), .i_freq_relay2(freq2_relay),
.i_freq_relay3(freq3_relay), .i_freq_relay3(freq3_relay),
.i_freq_relay4(freq4_relay), .i_freq_relay4(freq4_relay),
.i_DC_Con1(DC_Con1),
.i_DC_Con2(DC_Con2),
.i_DC_Con3(DC_Con3),
.i_DC_Con4(DC_Con4),
.o_con_done(con_done), .o_con_done(con_done),
.o_OC_x01(OC_x01), .o_OC_x01(OC_x01),
.o_OC_x17(OC_x17), .o_OC_x17(OC_x17),
.o_RC_Tx(RC_Tx), .o_RC_Tx(RC_Tx),
.o_DMM_EN(DMM_EN), .o_DMM_EN(DMM_EN),
.o_PMU_OC_1(PMU_OC_1),
.o_PMU_OC_2(PMU_OC_2),
.o_PMU_OC_3(PMU_OC_3),
.o_PMU_OC_4(PMU_OC_4),
.o_RC_VSel(RC_VSel),
.o_RC_ISel(RC_ISel),
.o_RC_RLSel(RC_RLSel),
.o_IO_RC1(IO_RC1), .o_IO_RC1(IO_RC1),
.o_err(cpld_err_flag) .o_err(cpld_err_flag)
); );
assign o_con_done = con_done; assign o_con_done = con_done;
//assign o_OC_x01 = OC_x01; //assign o_OC_x01 = OC_x01;
assign o_OC_1[0] = OC_x01[0]; assign o_PMU_OC_1[0] = OC_x01[0];
assign o_OC_2[0] = OC_x01[1]; assign o_PMU_OC_2[0] = OC_x01[1];
assign o_OC_3[0] = OC_x01[2]; assign o_PMU_OC_3[0] = OC_x01[2];
assign o_OC_4[0] = OC_x01[3]; assign o_PMU_OC_4[0] = OC_x01[3];
//assign o_OC_x17 = OC_x17; //assign o_OC_x17 = OC_x17;
assign o_OC_1[16] = OC_x17[0]; assign o_PMU_OC_1[16] = OC_x17[0];
assign o_OC_2[16] = OC_x17[1]; assign o_PMU_OC_2[16] = OC_x17[1];
assign o_OC_3[16] = OC_x17[2]; assign o_PMU_OC_3[16] = OC_x17[2];
assign o_OC_4[16] = OC_x17[3]; assign o_PMU_OC_4[16] = OC_x17[3];
assign o_PMU_OC_1[15:1] = PMU_OC_1[15:1];
assign o_PMU_OC_1[31:17] = PMU_OC_1[31:17];
assign o_PMU_OC_2[15:1] = PMU_OC_2[15:1];
assign o_PMU_OC_2[31:17] = PMU_OC_2[31:17];
assign o_PMU_OC_3[15:1] = PMU_OC_3[15:1];
assign o_PMU_OC_3[31:17] = PMU_OC_3[31:17];
assign o_PMU_OC_4[15:1] = PMU_OC_4[15:1];
assign o_PMU_OC_4[31:17] = PMU_OC_4[31:17];
assign o_DMM_EN = DMM_EN; assign o_DMM_EN = DMM_EN;
assign o_IO_RC1 = IO_RC1; assign o_IO_RC1 = IO_RC1;
assign o_RC_T27 = RC_Tx[4]; assign o_RC_T27 = RC_Tx[5];
assign o_RC_T28 = RC_Tx[3]; assign o_RC_T28 = RC_Tx[4];
assign o_RC_T29 = RC_Tx[2]; assign o_RC_T29 = RC_Tx[3];
assign o_RC_T30 = RC_Tx[1]; assign o_RC_T30 = RC_Tx[2];
assign o_RC_T31 = RC_Tx[0]; assign o_RC_T31 = RC_Tx[1];
assign o_RC_T32 = RC_Tx[0];
assign o_RC_RLSel = RC_RLSel;
assign o_RC_VSel = RC_VSel;
assign o_RC_ISel = RC_ISel;
assign o_RC_LOF = (RC_VSel == 1'b1)?2'b01:2'b10; //if Measure V then close RC_LOF[0]
assign o_RC_LOS = (RC_VSel == 1'b1)?2'b01:2'b10;
assign o_err = bus_err_flag || reg_err_flag ||cpld_err_flag; assign o_err = bus_err_flag || reg_err_flag ||cpld_err_flag;
2.FW/CPLD1/tb_RelayConTop.sv
+874 -270
View File
File diff suppressed because it is too large Load Diff
2.FW/CPLD1/tb_RelayConTop/source_files.lst
+2 -5
View File
@@ -1,5 +1,2 @@
"D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/CPLD_Freq_Con.v=work," "/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/tb_RelayConTop.sv=work,System Verilog"
"D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/Reg_file.v=work," "/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/RelayConTop_tf.v=work,Verilog 2001"
"D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/BUS_Con.v=work,"
"D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/RelayConTop.v=work,"
"D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/tb_RelayConTop.sv=work,"
2.FW/CPLD2/.run_manager.ini
+1 -1
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@@ -1,5 +1,5 @@
[Runmanager] [Runmanager]
Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1!\0\0\0\xe1\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0) Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1!\0\0\0\xdd\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\x6/\0\0\x2\x81\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\x6/\0\0\x2\x81\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x6+\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x4\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4L\0\0\0\v\0\0\0\0\0\0\x1\xbc\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0) headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x6+\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x4\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4L\0\0\0\v\0\0\0\0\0\0\x1\xbc\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
2.FW/CPLD2/.spreadsheet_view.ini
+3 -3
View File
@@ -3,10 +3,10 @@ pin_sort_type=0
pin_sort_ascending=true pin_sort_ascending=true
sig_sort_type=0 sig_sort_type=0
sig_sort_ascending=true sig_sort_ascending=true
active_Sheet=Global Preferences active_Sheet=Port Assignments
[Port%20Assignments] [Port%20Assignments]
Name="176,0" Name="216,0"
Group%20By="118,1" Group%20By="118,1"
Pin="71,2" Pin="71,2"
BANK="91,3" BANK="91,3"
@@ -65,7 +65,7 @@ Prioritize="100,ELLIPSIS"
[Timing%20Preferences] [Timing%20Preferences]
Preference%20Name="146,ELLIPSIS" Preference%20Name="146,ELLIPSIS"
Preference%20Value="143,ELLIPSIS" Preference%20Value="143,ELLIPSIS"
Preference%20Unit="1122,ELLIPSIS" Preference%20Unit="133,ELLIPSIS"
[Group] [Group]
Group%20Type\Name="153,ELLIPSIS" Group%20Type\Name="153,ELLIPSIS"
2.FW/CPLD2/BUS_Con.v
+17 -17
View File
@@ -9,14 +9,14 @@ module BUS_Con (
output o_miso, // <-- MISO Logic added here output o_miso, // <-- MISO Logic added here
// Local Interface // Local Interface
output o_rvaild, // (Typo in original: o_rvalid) output o_rvalid, // (Typo in original: o_rvalid)
input i_rvaild, // Valid signal from Backend (Data is ready) input i_rvalid, // Valid signal from Backend (Data is ready)
input i_wvaild, input i_wvalid,
output o_wready, output o_wready,
input i_reg_busy, input i_reg_busy,
input [23:0] i_rdata, // Data from Backend to send to Master input [23:0] i_rdata, // Data from Backend to send to Master
output o_wr, output o_wr,
output o_cmd_vaild, output o_cmd_valid,
output [23:0] o_data, output [23:0] o_data,
output [6:0] o_addr, output [6:0] o_addr,
output o_err output o_err
@@ -61,19 +61,19 @@ module BUS_Con (
reg err_flag; reg err_flag;
reg [1:0] state; reg [1:0] state;
// //
reg [31:0] tx_buffer; // Holds data waiting for the next CS Low reg [31:0] tx_buffer; // Holds data waiting for the next CS Low
reg [31:0] miso_shift; // The actual shifter reg [31:0] miso_shift; // The actual shifter
// Output Registers // Output Registers
reg [6:0] addr_out; reg [6:0] addr_out;
reg [23:0] data_out; reg [23:0] data_out;
reg wr_out; reg wr_out;
reg cmd_valid_out; reg cmd_valid_out;
// //
localparam IDLE = 2'b00; localparam IDLE = 2'b00;
localparam CMD_SENT = 2'b01; localparam CMD_SENT = 2'b01;
localparam WAIT_BUSY = 2'b10; localparam WAIT_BUSY = 2'b10;
localparam DONE = 2'b11; localparam DONE = 2'b11;
always @(posedge i_sys_clk) begin always @(posedge i_sys_clk) begin
@@ -122,7 +122,7 @@ module BUS_Con (
end else begin end else begin
// If backend provides valid read data, store it. // If backend provides valid read data, store it.
// We pad the top 8 bits with Zeros (or you can put status flags here) // We pad the top 8 bits with Zeros (or you can put status flags here)
if (i_rvaild) begin if (i_rvalid) begin
tx_buffer <= {8'h00, i_rdata}; tx_buffer <= {8'h00, i_rdata};
end end
end end
@@ -205,11 +205,11 @@ module BUS_Con (
assign o_addr = addr_out; assign o_addr = addr_out;
assign o_data = data_out; assign o_data = data_out;
assign o_wr = wr_out; assign o_wr = wr_out;
assign o_cmd_vaild = cmd_valid_out; assign o_cmd_valid = cmd_valid_out;
assign o_err = err_flag; assign o_err = err_flag;
assign o_wready = (state == IDLE); assign o_wready = (state == IDLE);
// Pass through unused signal or hook it up if needed // Pass through unused signal or hook it up if needed
assign o_rvaild = 1'b0; assign o_rvalid = i_rvalid;
endmodule endmodule
2.FW/CPLD2/CPLD_Con.v
+232 -95
View File
@@ -2,32 +2,61 @@ module CPLD_Con (
input i_sys_clk, input i_sys_clk,
input i_rst_n, input i_rst_n,
input i_con_exec, input i_con_exec,
// Freq Relay Control
input [23:0]i_freq_relay1, input [23:0]i_freq_relay1,
input [23:0]i_freq_relay2, input [23:0]i_freq_relay2,
input [23:0]i_freq_relay3, input [23:0]i_freq_relay3,
input [23:0]i_freq_relay4, input [23:0]i_freq_relay4,
output o_con_done,
// DC related Control
input [23:0]i_DC_Con1,
input [23:0]i_DC_Con2,
input [23:0]i_DC_Con3,
input [23:0]i_DC_Con4,
//Output RELAYs
output [7:0]o_RC_F, //Ref: Schematic output [7:0]o_RC_F, //Ref: Schematic
output [15:0]o_RC_S, output [15:0]o_RC_S,
output [31:0]o_RC_T, output [31:0]o_RC_T,
output [3:0] o_OC_x09, output [3:0] o_OC_x09,
output [3:0] o_OC_x25 output [3:0] o_OC_x25,
output [31:0]o_PMU_OC_1 ,
output [31:0]o_PMU_OC_2 ,
output [31:0]o_PMU_OC_3 ,
output [31:0]o_PMU_OC_4,
//Output FLAGs
output o_err,
output o_con_done
); );
//Output Relay Reg //Output Relay Reg
reg [3:0] OC_x09; reg [3:0] OC_x09;
reg [3:0] OC_x25; reg [3:0] OC_x25;
//Condition Tester
reg [15:0]en_t ;
reg freq_t;
reg dc_t;
//Relay Reg //Relay Reg
reg [7:0]relay_l1; reg [7:0]relay_l1;
reg [15:0]relay_l2 ; reg [15:0]relay_l2 ;
reg [31:0]relay_l3 ; reg [31:0]relay_l3 ;
reg [31:0]PMU_OC_1 ;
reg [31:0]PMU_OC_2 ;
reg [31:0]PMU_OC_3 ;
reg [31:0]PMU_OC_4 ;
//Flags //Flags
reg exec_done_flag; reg exec_done_flag;
reg exec_flag; reg exec_flag;
reg [3:0]slot_exec_flag; reg [3:0]freq_slot_flag;
reg [3:0]dc_slot_flag ;
reg err_flag; reg err_flag;
//Counter //Counter
@@ -52,6 +81,21 @@ module CPLD_Con (
end end
end end
//Function Identify
always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin
en_t <= 'd0;
freq_t <= 'd0;
dc_t <= 'd0;
end
else begin
en_t <= (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) + (i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0] );
freq_t <= i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0];
dc_t <= i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0];
end
end
// Main Controller Function
always @(posedge i_sys_clk) begin always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin if (i_rst_n == 1'b0) begin
relay_l1 <= 'd0; relay_l1 <= 'd0;
@@ -59,125 +103,211 @@ module CPLD_Con (
relay_l3 <= 'd0; relay_l3 <= 'd0;
exec_flag <= 1'b0; exec_flag <= 1'b0;
exec_done_flag <= 1'b1; exec_done_flag <= 1'b1;
slot_exec_flag <= 'd0; freq_slot_flag <= 'd0;
PMU_OC_1 <= 'd0;
PMU_OC_2 <= 'd0;
PMU_OC_3 <= 'd0;
PMU_OC_4 <= 'd0;
dc_slot_flag<='d0;
err_flag <= 'd0; err_flag <= 'd0;
end end
else begin else begin
if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin
exec_done_flag <= 'd0;
exec_flag <= 1'b1;
//To DO: More Sanity Check? //To DO: More Sanity Check?
// Add the bits together. Verilog handles the width expansion automatically for the comparison. if (en_t > 'd1) begin //Only ONE Enable bit should be set!
if ( (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) > 2'd1 ) begin
err_flag <= 1'b1; err_flag <= 1'b1;
end end
else begin else begin
slot_exec_flag[0] <= i_freq_relay1[0]; exec_done_flag <= 'd0;
slot_exec_flag[1] <= i_freq_relay2[0]; exec_flag <= 1'b1;
slot_exec_flag[2] <= i_freq_relay3[0];
slot_exec_flag[3] <= i_freq_relay4[0]; freq_slot_flag[0] <= i_freq_relay1[0];
freq_slot_flag[1] <= i_freq_relay2[0];
freq_slot_flag[2] <= i_freq_relay3[0];
freq_slot_flag[3] <= i_freq_relay4[0];
dc_slot_flag[0] <= i_DC_Con1[0];
dc_slot_flag[1] <= i_DC_Con2[0];
dc_slot_flag[2] <= i_DC_Con3[0];
dc_slot_flag[3] <= i_DC_Con4[0];
end end
end end
else if (exec_flag == 1'b1) begin else if (exec_flag == 1'b1) begin
//Output Relay //Output Relay
case (slot_exec_flag) if (freq_t == 1'b1) begin
4'b0001: begin case (freq_slot_flag)
relay_l1 <= {'d0,i_freq_relay1[22],i_freq_relay1[23]}; 4'b0001: begin
if (delay_cnt == 'd500) begin relay_l1 <= {'d0,i_freq_relay1[22],i_freq_relay1[23]};
relay_l2 <= {'d0,i_freq_relay1[18],i_freq_relay1[19],i_freq_relay1[20],i_freq_relay1[21]}; if (delay_cnt == 'd500) begin
relay_l2 <= {'d0,i_freq_relay1[18],i_freq_relay1[19],i_freq_relay1[20],i_freq_relay1[21]};
end
else if (delay_cnt == 'd1000) begin
relay_l3 <= {'d0,i_freq_relay1[10],i_freq_relay1[11],i_freq_relay1[12],i_freq_relay1[13],i_freq_relay1[14],i_freq_relay1[15],i_freq_relay1[16],i_freq_relay1[17]};
end
else if (delay_cnt == 'd1080) begin
exec_flag <= 'd0;
exec_done_flag <= 1'b1;
end
if ((freq_relay1 > 64) & (freq_relay1 < 73)) begin
OC_x09 <= 4'b0001;
end
else if ((freq_relay1 > 192) & (freq_relay1 < 201)) begin
OC_x25 <= 4'b0001;
end
else begin
OC_x09 <= 'd0;
OC_x25 <= 'd0;
end
end end
else if (delay_cnt == 'd1000) begin 4'b0010: begin
relay_l3 <= {'d0,i_freq_relay1[10],i_freq_relay1[11],i_freq_relay1[12],i_freq_relay1[13],i_freq_relay1[14],i_freq_relay1[15],i_freq_relay1[16],i_freq_relay1[17]}; relay_l1 <= {4'd0,i_freq_relay2[22],i_freq_relay2[23],2'd0};
if (delay_cnt == 'd500) begin
relay_l2 <= {8'd0,i_freq_relay2[18],i_freq_relay2[19],i_freq_relay2[20],i_freq_relay2[21],4'd0};
end
else if (delay_cnt == 'd1000) begin
relay_l3 <= {16'd0,i_freq_relay2[10],i_freq_relay2[11],i_freq_relay2[12],i_freq_relay2[13],i_freq_relay2[14],i_freq_relay2[15],i_freq_relay2[16],i_freq_relay2[17],8'd0};
end
else if (delay_cnt == 'd1080) begin
exec_flag <= 'd0;
exec_done_flag <= 1'b1;
end
if ((freq_relay2 > 64) & (freq_relay2 < 73)) begin
OC_x09 <= 4'b0010;
end
else if ((freq_relay2 > 192) & (freq_relay2 < 201)) begin
OC_x25 <= 4'b0010;
end
else begin
OC_x09 <= 'd0;
OC_x25 <= 'd0;
end
end end
else if (delay_cnt == 'd1080) begin 4'b0100: begin
relay_l1 <= {2'd0,i_freq_relay3[22],i_freq_relay3[23],4'd0};
if (delay_cnt == 'd500) begin
relay_l2 <= {4'd0,i_freq_relay3[18],i_freq_relay3[19],i_freq_relay3[20],i_freq_relay3[21],8'd0};
end
else if (delay_cnt == 'd1000) begin
relay_l3 <= {8'd0,i_freq_relay3[12],i_freq_relay3[13],i_freq_relay3[10],i_freq_relay3[11],i_freq_relay3[16],i_freq_relay3[17],i_freq_relay3[14],i_freq_relay3[15],16'd0};
end
else if (delay_cnt == 'd1080) begin
exec_flag <= 'd0;
exec_done_flag <= 1'b1;
end
if ((freq_relay3 > 64) &(freq_relay3 <73)) begin
OC_x09 <= 4'b0100;
end
else if ((freq_relay3 > 192) & (freq_relay3 < 201)) begin
OC_x25 <= 4'b0100;
end
else begin
OC_x09 <= 'd0;
OC_x25 <= 'd0;
end
end
4'b1000: begin
relay_l1 <= {i_freq_relay4[22],i_freq_relay4[23],6'd0};
if (delay_cnt == 'd500) begin
relay_l2 <= {i_freq_relay4[18],i_freq_relay4[19],i_freq_relay4[20],i_freq_relay4[21],12'd0};
end
else if (delay_cnt == 'd1000) begin
relay_l3 <= {i_freq_relay4[10],i_freq_relay4[11],i_freq_relay4[12],i_freq_relay4[13],i_freq_relay4[14],i_freq_relay4[15],i_freq_relay4[16],i_freq_relay4[17],24'd0};
end
else if (delay_cnt == 'd1080) begin
exec_flag <= 'd0;
exec_done_flag <= 1'b1;
end
if ((freq_relay4 > 64) & (freq_relay4 < 73)) begin
OC_x09 <= 4'b1000;
end
else if ((freq_relay4 > 192) & (freq_relay4 < 201)) begin
OC_x25 <= 4'b1000;
end
else begin
OC_x09 <= 'd0;
OC_x25 <= 'd0;
end
end
default: begin
OC_x09 <= 4'b0000;
OC_x25 <= 4'b0000;
end
endcase
end
else if (dc_t == 1'b1) begin
case (dc_slot_flag)
4'b0001: begin
//Sanity Check
if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18) || (i_DC_Con1[9:1] < 1) || (i_DC_Con1[9:1] > 256)) begin
err_flag <= 1'b1;
end
else begin
if (i_DC_Con1[23] == 1'b0) begin //Select PMU
PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con1[9:1]/8);
end
else if (i_DC_Con1[23] == 1'b1) begin //Select DPS
end
end
exec_flag <= 'd0; exec_flag <= 'd0;
exec_done_flag <= 1'b1; exec_done_flag <= 1'b1;
end end
if ((freq_relay1 > 64) & (freq_relay1 < 73)) begin 4'b0010: begin
OC_x09 <= 4'b0001; //Sanity Check
end if ((i_DC_Con2[21:17] < 1) || (i_DC_Con2[21:17] > 18) || (i_DC_Con2[9:1] < 1) || (i_DC_Con2[9:1] > 256)) begin
else if ((freq_relay1 > 192) & (freq_relay1 < 201)) begin err_flag <= 1'b1;
OC_x25 <= 4'b0001; end
end else begin
else begin if (i_DC_Con2[23] == 1'b0) begin //Select PMU
OC_x09 <= 'd0; PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con2[9:1]/8);
OC_x25 <= 'd0; end
end else if (i_DC_Con2[23] == 1'b1) begin //Select DPS
end
4'b0010: begin end
relay_l1 <= {4'd0,i_freq_relay2[22],i_freq_relay2[23],2'd0}; end
if (delay_cnt == 'd500) begin
relay_l2 <= {8'd0,i_freq_relay2[18],i_freq_relay2[19],i_freq_relay2[20],i_freq_relay2[21],4'd0};
end
else if (delay_cnt == 'd1000) begin
relay_l3 <= {16'd0,i_freq_relay2[10],i_freq_relay2[11],i_freq_relay2[12],i_freq_relay2[13],i_freq_relay2[14],i_freq_relay2[15],i_freq_relay2[16],i_freq_relay2[17],8'd0};
end
else if (delay_cnt == 'd1080) begin
exec_flag <= 'd0; exec_flag <= 'd0;
exec_done_flag <= 1'b1; exec_done_flag <= 1'b1;
end end
if ((freq_relay2 > 64) & (freq_relay2 < 73)) begin 4'b0100:begin
OC_x09 <= 4'b0010; //Sanity Check
end if ((i_DC_Con3[21:17] < 1) || (i_DC_Con3[21:17] > 18) || (i_DC_Con3[9:1] < 1) || (i_DC_Con3[9:1] > 256)) begin
else if ((freq_relay2 > 192) & (freq_relay2 < 201)) begin err_flag <= 1'b1;
OC_x25 <= 4'b0010; end
end else begin
else begin if (i_DC_Con3[23] == 1'b0) begin //Select PMU
OC_x09 <= 'd0; PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con3[9:1]/8);
OC_x25 <= 'd0; end
end else if (i_DC_Con3[23] == 1'b1) begin //Select DPS
end
4'b0100: begin end
relay_l1 <= {2'd0,i_freq_relay3[22],i_freq_relay3[23],4'd0}; end
if (delay_cnt == 'd500) begin
relay_l2 <= {4'd0,i_freq_relay3[18],i_freq_relay3[19],i_freq_relay3[20],i_freq_relay3[21],8'd0};
end
else if (delay_cnt == 'd1000) begin
relay_l3 <= {8'd0,i_freq_relay3[12],i_freq_relay3[13],i_freq_relay3[10],i_freq_relay3[11],i_freq_relay3[16],i_freq_relay3[17],i_freq_relay3[14],i_freq_relay3[15],16'd0};
end
else if (delay_cnt == 'd1080) begin
exec_flag <= 'd0; exec_flag <= 'd0;
exec_done_flag <= 1'b1; exec_done_flag <= 1'b1;
end end
if ((freq_relay3 > 64) &(freq_relay3 <73)) begin 4'b1000:begin
OC_x09 <= 4'b0100; //Sanity Check
end if ((i_DC_Con4[21:17] < 1) || (i_DC_Con4[21:17] > 18) || (i_DC_Con4[9:1] < 1) || (i_DC_Con4[9:1] > 256)) begin
else if ((freq_relay3 > 192) & (freq_relay3 < 201)) begin err_flag <= 1'b1;
OC_x25 <= 4'b0100; end
end else begin
else begin if (i_DC_Con4[23] == 1'b0) begin //Select PMU
OC_x09 <= 'd0; PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con4[9:1]/8);
OC_x25 <= 'd0; end
end else if (i_DC_Con4[23] == 1'b1) begin //Select DPS
end
4'b1000: begin end
relay_l1 <= {i_freq_relay4[22],i_freq_relay4[23],6'd0}; end
if (delay_cnt == 'd500) begin
relay_l2 <= {i_freq_relay4[18],i_freq_relay4[19],i_freq_relay4[20],i_freq_relay4[21],12'd0};
end
else if (delay_cnt == 'd1000) begin
relay_l3 <= {i_freq_relay4[10],i_freq_relay4[11],i_freq_relay4[12],i_freq_relay4[13],i_freq_relay4[14],i_freq_relay4[15],i_freq_relay4[16],i_freq_relay4[17],24'd0};
end
else if (delay_cnt == 'd1080) begin
exec_flag <= 'd0; exec_flag <= 'd0;
exec_done_flag <= 1'b1; exec_done_flag <= 1'b1;
end end
if ((freq_relay4 > 64) & (freq_relay4 < 73)) begin default:begin // You Should NOT be HERE
OC_x09 <= 4'b1000; PMU_OC_1 <= 'd0 ;
PMU_OC_2 <= 'd0 ;
PMU_OC_3 <= 'd0 ;
PMU_OC_4 <= 'd0 ;
end end
else if ((freq_relay4 > 192) & (freq_relay4 < 201)) begin endcase
OC_x25 <= 4'b1000; end
end
else begin
OC_x09 <= 'd0;
OC_x25 <= 'd0;
end
end
default: begin
OC_x09 <= 4'b0000;
OC_x25 <= 4'b0000;
end
endcase
end end
end end
end end
@@ -189,4 +319,11 @@ module CPLD_Con (
assign o_OC_x09 = OC_x09; assign o_OC_x09 = OC_x09;
assign o_OC_x25 = OC_x25; assign o_OC_x25 = OC_x25;
assign o_PMU_OC_1 = PMU_OC_1;
assign o_PMU_OC_2 = PMU_OC_2;
assign o_PMU_OC_3 = PMU_OC_3;
assign o_PMU_OC_4 = PMU_OC_4;
assign o_err = err_flag;
endmodule endmodule
2.FW/CPLD2/NewExtIns_CPLD2.ldf
+1 -1
View File
@@ -2,7 +2,7 @@
<BaliProject version="3.2" title="NewExtIns_CPLD2" device="LCMXO2-7000HC-4FG484C" default_implementation="impl1"> <BaliProject version="3.2" title="NewExtIns_CPLD2" device="LCMXO2-7000HC-4FG484C" default_implementation="impl1">
<Options/> <Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1"> <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
<Options def_top="RelayConTop"/> <Options def_top="RelayConTop" top="RelayConTop"/>
<Source name="RelayConTop.v" type="Verilog" type_short="Verilog"> <Source name="RelayConTop.v" type="Verilog" type_short="Verilog">
<Options top_module="RelayConTop"/> <Options top_module="RelayConTop"/>
</Source> </Source>
2.FW/CPLD2/NewExtIns_CPLD2.lpf
+200 -198
View File
@@ -4,6 +4,7 @@ RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk";
BLOCK RESETPATHS ; BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ; BLOCK ASYNCPATHS ;
LOCATE COMP "i_sys_clk" SITE "B9" ; LOCATE COMP "i_sys_clk" SITE "B9" ;
@@ -11,12 +12,12 @@ LOCATE COMP "i_rst_n" SITE "Y14" ;
LOCATE COMP "i_sclk" SITE "AA16" ; LOCATE COMP "i_sclk" SITE "AA16" ;
LOCATE COMP "i_cs" SITE "Y15" ; LOCATE COMP "i_cs" SITE "Y15" ;
LOCATE COMP "i_mosi" SITE "AB12" ; LOCATE COMP "i_mosi" SITE "AB12" ;
//LOCATE COMP "o_RC_T[26]" SITE "U13" ; //LOCATE COMP "o_RC_T[26]" SITE "U13" ;
//LOCATE COMP "o_RC_T[27]" SITE "U12" ; //LOCATE COMP "o_RC_T[27]" SITE "U12" ;
//LOCATE COMP "o_RC_T[28]" SITE "T12" ; //LOCATE COMP "o_RC_T[28]" SITE "T12" ;
//LOCATE COMP "o_RC_T[29]" SITE "T11" ; //LOCATE COMP "o_RC_T[29]" SITE "T11" ;
//LOCATE COMP "o_RC_T[30]" SITE "U11" ; //LOCATE COMP "o_RC_T[30]" SITE "U11" ;
//LOCATE COMP "o_RC_T[31]" SITE "V11" ; //LOCATE COMP "o_RC_T[31]" SITE "V11" ;
IOBUF PORT "i_cs" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_cs" IO_TYPE=LVCMOS33 ;
IOBUF PORT "i_mosi" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_mosi" IO_TYPE=LVCMOS33 ;
IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 ;
@@ -127,196 +128,197 @@ LOCATE COMP "o_RC_T[23]" SITE "U15" ;
LOCATE COMP "o_RC_T[24]" SITE "T13" ; LOCATE COMP "o_RC_T[24]" SITE "T13" ;
LOCATE COMP "o_RC_T[25]" SITE "AA13" ; LOCATE COMP "o_RC_T[25]" SITE "AA13" ;
LOCATE COMP "o_err" SITE "AB16" ; LOCATE COMP "o_err" SITE "AB16" ;
IOBUF PORT "o_OC_1[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[8]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_OC_1[8]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_OC_2[8]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_OC_2[8]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_OC_3[8]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_OC_3[8]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_OC_4[8]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_OC_4[8]" IO_TYPE=LVCMOS33 ;
LOCATE COMP "o_OC_1[8]" SITE "D14" ; LOCATE COMP "o_PMU_OC_1[8]" SITE "D14" ;
LOCATE COMP "o_OC_1[9]" SITE "G13" ; LOCATE COMP "o_PMU_OC_1[9]" SITE "G13" ;
LOCATE COMP "o_OC_1[10]" SITE "C13" ; LOCATE COMP "o_PMU_OC_1[10]" SITE "C13" ;
LOCATE COMP "o_OC_1[11]" SITE "F13" ; LOCATE COMP "o_PMU_OC_1[11]" SITE "F13" ;
LOCATE COMP "o_OC_1[12]" SITE "C17" ; LOCATE COMP "o_PMU_OC_1[12]" SITE "C17" ;
LOCATE COMP "o_OC_1[13]" SITE "F17" ; LOCATE COMP "o_PMU_OC_1[13]" SITE "F17" ;
LOCATE COMP "o_OC_1[14]" SITE "D17" ; LOCATE COMP "o_PMU_OC_1[14]" SITE "D17" ;
LOCATE COMP "o_OC_1[15]" SITE "E17" ; LOCATE COMP "o_PMU_OC_1[15]" SITE "E17" ;
LOCATE COMP "o_OC_1[24]" SITE "N5" ; LOCATE COMP "o_PMU_OC_1[24]" SITE "N5" ;
LOCATE COMP "o_OC_1[25]" SITE "D15" ; LOCATE COMP "o_PMU_OC_1[25]" SITE "D15" ;
LOCATE COMP "o_OC_1[26]" SITE "P3" ; LOCATE COMP "o_PMU_OC_1[26]" SITE "P3" ;
LOCATE COMP "o_OC_1[27]" SITE "M4" ; LOCATE COMP "o_PMU_OC_1[27]" SITE "M4" ;
LOCATE COMP "o_OC_1[28]" SITE "R6" ; LOCATE COMP "o_PMU_OC_1[28]" SITE "R6" ;
LOCATE COMP "o_OC_1[29]" SITE "T5" ; LOCATE COMP "o_PMU_OC_1[29]" SITE "T5" ;
LOCATE COMP "o_OC_1[30]" SITE "P6" ; LOCATE COMP "o_PMU_OC_1[30]" SITE "P6" ;
LOCATE COMP "o_OC_1[31]" SITE "U4" ; LOCATE COMP "o_PMU_OC_1[31]" SITE "U4" ;
LOCATE COMP "o_OC_2[8]" SITE "C1" ; LOCATE COMP "o_PMU_OC_2[8]" SITE "C1" ;
LOCATE COMP "o_OC_2[9]" SITE "C2" ; LOCATE COMP "o_PMU_OC_2[9]" SITE "C2" ;
LOCATE COMP "o_OC_2[10]" SITE "C3" ; LOCATE COMP "o_PMU_OC_2[10]" SITE "C3" ;
LOCATE COMP "o_OC_2[11]" SITE "B1" ; LOCATE COMP "o_PMU_OC_2[11]" SITE "B1" ;
LOCATE COMP "o_OC_2[12]" SITE "H5" ; LOCATE COMP "o_PMU_OC_2[12]" SITE "H5" ;
LOCATE COMP "o_OC_2[13]" SITE "H6" ; LOCATE COMP "o_PMU_OC_2[13]" SITE "H6" ;
LOCATE COMP "o_OC_2[14]" SITE "H2" ; LOCATE COMP "o_PMU_OC_2[14]" SITE "H2" ;
LOCATE COMP "o_OC_2[15]" SITE "H3" ; LOCATE COMP "o_PMU_OC_2[15]" SITE "H3" ;
LOCATE COMP "o_OC_2[24]" SITE "T7" ; LOCATE COMP "o_PMU_OC_2[24]" SITE "T7" ;
LOCATE COMP "o_OC_2[25]" SITE "U5" ; LOCATE COMP "o_PMU_OC_2[25]" SITE "U5" ;
LOCATE COMP "o_OC_2[26]" SITE "W5" ; LOCATE COMP "o_PMU_OC_2[26]" SITE "W5" ;
LOCATE COMP "o_OC_2[27]" SITE "T6" ; LOCATE COMP "o_PMU_OC_2[27]" SITE "T6" ;
LOCATE COMP "o_OC_2[28]" SITE "E8" ; LOCATE COMP "o_PMU_OC_2[28]" SITE "E8" ;
LOCATE COMP "o_OC_2[29]" SITE "E9" ; LOCATE COMP "o_PMU_OC_2[29]" SITE "E9" ;
LOCATE COMP "o_OC_2[30]" SITE "E10" ; LOCATE COMP "o_PMU_OC_2[30]" SITE "E10" ;
LOCATE COMP "o_OC_2[31]" SITE "D11" ; LOCATE COMP "o_PMU_OC_2[31]" SITE "D11" ;
LOCATE COMP "o_OC_3[8]" SITE "A11" ; LOCATE COMP "o_PMU_OC_3[8]" SITE "A11" ;
LOCATE COMP "o_OC_3[9]" SITE "A12" ; LOCATE COMP "o_PMU_OC_3[9]" SITE "A12" ;
LOCATE COMP "o_OC_3[10]" SITE "B12" ; LOCATE COMP "o_PMU_OC_3[10]" SITE "B12" ;
LOCATE COMP "o_OC_3[11]" SITE "A13" ; LOCATE COMP "o_PMU_OC_3[11]" SITE "A13" ;
LOCATE COMP "o_OC_3[12]" SITE "B19" ; LOCATE COMP "o_PMU_OC_3[12]" SITE "B19" ;
LOCATE COMP "o_OC_3[13]" SITE "C18" ; LOCATE COMP "o_PMU_OC_3[13]" SITE "C18" ;
LOCATE COMP "o_OC_3[14]" SITE "A17" ; LOCATE COMP "o_PMU_OC_3[14]" SITE "A17" ;
LOCATE COMP "o_OC_3[15]" SITE "B16" ; LOCATE COMP "o_PMU_OC_3[15]" SITE "B16" ;
LOCATE COMP "o_OC_3[24]" SITE "B13" ; LOCATE COMP "o_PMU_OC_3[24]" SITE "B13" ;
LOCATE COMP "o_OC_3[25]" SITE "B14" ; LOCATE COMP "o_PMU_OC_3[25]" SITE "B14" ;
LOCATE COMP "o_OC_3[26]" SITE "B15" ; LOCATE COMP "o_PMU_OC_3[26]" SITE "B15" ;
LOCATE COMP "o_OC_3[27]" SITE "C15" ; LOCATE COMP "o_PMU_OC_3[27]" SITE "C15" ;
LOCATE COMP "o_OC_3[28]" SITE "G21" ; LOCATE COMP "o_PMU_OC_3[28]" SITE "G21" ;
LOCATE COMP "o_OC_3[29]" SITE "E22" ; LOCATE COMP "o_PMU_OC_3[29]" SITE "E22" ;
LOCATE COMP "o_OC_3[30]" SITE "E20" ; LOCATE COMP "o_PMU_OC_3[30]" SITE "E20" ;
LOCATE COMP "o_OC_3[31]" SITE "D21" ; LOCATE COMP "o_PMU_OC_3[31]" SITE "D21" ;
LOCATE COMP "o_OC_4[8]" SITE "G1" ; LOCATE COMP "o_PMU_OC_4[8]" SITE "G1" ;
LOCATE COMP "o_OC_4[9]" SITE "G2" ; LOCATE COMP "o_PMU_OC_4[9]" SITE "G2" ;
LOCATE COMP "o_OC_4[10]" SITE "G3" ; LOCATE COMP "o_PMU_OC_4[10]" SITE "G3" ;
LOCATE COMP "o_OC_4[11]" SITE "F1" ; LOCATE COMP "o_PMU_OC_4[11]" SITE "F1" ;
LOCATE COMP "o_OC_4[12]" SITE "C4" ; LOCATE COMP "o_PMU_OC_4[12]" SITE "C4" ;
LOCATE COMP "o_OC_4[13]" SITE "C5" ; LOCATE COMP "o_PMU_OC_4[13]" SITE "C5" ;
LOCATE COMP "o_OC_4[14]" SITE "G11" ; LOCATE COMP "o_PMU_OC_4[14]" SITE "G11" ;
LOCATE COMP "o_OC_4[15]" SITE "E11" ; LOCATE COMP "o_PMU_OC_4[15]" SITE "E11" ;
LOCATE COMP "o_OC_4[24]" SITE "E1" ; LOCATE COMP "o_PMU_OC_4[24]" SITE "E1" ;
LOCATE COMP "o_OC_4[25]" SITE "D1" ; LOCATE COMP "o_PMU_OC_4[25]" SITE "D1" ;
LOCATE COMP "o_OC_4[26]" SITE "E2" ; LOCATE COMP "o_PMU_OC_4[26]" SITE "E2" ;
LOCATE COMP "o_OC_4[27]" SITE "D3" ; LOCATE COMP "o_PMU_OC_4[27]" SITE "D3" ;
LOCATE COMP "o_OC_4[28]" SITE "C11" ; LOCATE COMP "o_PMU_OC_4[28]" SITE "C11" ;
LOCATE COMP "o_OC_4[29]" SITE "A2" ; LOCATE COMP "o_PMU_OC_4[29]" SITE "A2" ;
LOCATE COMP "o_OC_4[30]" SITE "B3" ; LOCATE COMP "o_PMU_OC_4[30]" SITE "B3" ;
LOCATE COMP "o_OC_4[31]" SITE "A3" ; LOCATE COMP "o_PMU_OC_4[31]" SITE "A3" ;
USE PRIMARY NET "i_sys_clk_c" ; USE PRIMARY NET "i_sys_clk_c" ;
IOBUF PORT "o_rvalid" IO_TYPE=LVCMOS33 ;
2.FW/CPLD2/Reg_file.v
+13 -2
View File
@@ -21,13 +21,19 @@ module Reg_file (
output [23:0] o_freq1, output [23:0] o_freq1,
output [23:0] o_freq2, output [23:0] o_freq2,
output [23:0] o_freq3, output [23:0] o_freq3,
output [23:0] o_freq4 output [23:0] o_freq4,
//DC Regs
output [23:0] o_DC1,
output [23:0] o_DC2,
output [23:0] o_DC3,
output [23:0] o_DC4
); );
// --- Parameters --- // --- Parameters ---
localparam REG_COUNT = 16; localparam REG_COUNT = 16;
localparam [23:0] localparam [23:0]
IDENT = 24'h400000|| 12'b0001_0000_0000, //CPLD2==1,version=1.0.0 IDENT = 24'h400000 | 12'b0001_0001_0000, //CPLD2==1,version=1.1.0
STATE_INIT = 24'h800000; STATE_INIT = 24'h800000;
// State Machine Definition // State Machine Definition
@@ -163,5 +169,10 @@ module Reg_file (
assign o_freq2 = regtable[3]; assign o_freq2 = regtable[3];
assign o_freq3 = regtable[4]; assign o_freq3 = regtable[4];
assign o_freq4 = regtable[5]; assign o_freq4 = regtable[5];
assign o_DC1 = regtable[6];
assign o_DC2 = regtable[7];
assign o_DC3 = regtable[8];
assign o_DC4 = regtable[9];
endmodule endmodule
2.FW/CPLD2/RelayConTop.v
+66 -17
View File
@@ -8,7 +8,7 @@ module RelayConTop (
output o_miso, output o_miso,
output o_rvalid, output o_rvalid,
input i_rready, input i_rready,
input i_wvaild, input i_wvalid,
output o_wready, output o_wready,
output o_err, output o_err,
output [7:0]o_RC_F, //Ref: Schematic output [7:0]o_RC_F, //Ref: Schematic
@@ -16,10 +16,10 @@ module RelayConTop (
output [25:0]o_RC_T, //Actually ONLY 25 pin(rest is on CPLD1) output [25:0]o_RC_T, //Actually ONLY 25 pin(rest is on CPLD1)
//output [3:0] o_OC_x09, //output [3:0] o_OC_x09,
//output [3:0] o_OC_x25, //output [3:0] o_OC_x25,
output [31:0]o_OC_1, output [31:0]o_PMU_OC_1 ,
output [31:0]o_OC_2, output [31:0]o_PMU_OC_2 ,
output [31:0]o_OC_3, output [31:0]o_PMU_OC_3 ,
output [31:0]o_OC_4 output [31:0]o_PMU_OC_4
); );
wire [7:0] RC_F; wire [7:0] RC_F;
@@ -37,30 +37,44 @@ module RelayConTop (
wire wr_flag; //1=write,0=read wire wr_flag; //1=write,0=read
wire bus_err_flag; wire bus_err_flag;
wire reg_err_flag; wire reg_err_flag;
wire cpld_err_flag;
wire con_exec; wire con_exec;
wire [23:0]freq1_relay ; wire [23:0]freq1_relay ;
wire [23:0]freq2_relay ; wire [23:0]freq2_relay ;
wire [23:0]freq3_relay ; wire [23:0]freq3_relay ;
wire [23:0]freq4_relay ; wire [23:0]freq4_relay ;
//DC Control Reg output
wire [23:0]DC_Con1 ;
wire [23:0]DC_Con2 ;
wire [23:0]DC_Con3 ;
wire [23:0]DC_Con4 ;
//PMU OC Control
wire [31:0]PMU_OC_1 ;
wire [31:0]PMU_OC_2 ;
wire [31:0]PMU_OC_3 ;
wire [31:0]PMU_OC_4 ;
wire con_rvalid; wire con_rvalid;
wire con_done; wire con_done;
BUS_Con BUS_Con_2( BUS_Con BUS_Con_2(
.i_sys_clk(i_sys_clk), .i_sys_clk(i_sys_clk),
.i_rst_n(i_rst_n), .i_rst_n(i_rst_n),
.i_sclk(i_sclk), .i_sclk(i_sclk),
.i_mosi(i_mosi), .i_mosi(i_mosi),
.i_cs(i_cs), .i_cs(i_cs),
.i_rvaild(con_rvaild), .i_rvalid(con_rvalid),
.i_wvaild(i_wvaild), .i_wvalid(i_wvalid),
.i_reg_busy(reg_busy), .i_reg_busy(reg_busy),
.i_rdata(r_data), .i_rdata(r_data),
.o_cmd_vaild(cmd_valid), .o_cmd_valid(cmd_valid),
.o_wr(wr_flag), .o_wr(wr_flag),
.o_miso(o_miso), .o_miso(o_miso),
.o_rvaild(o_rvalid), .o_rvalid(o_rvalid),
.o_wready(o_wready), .o_wready(o_wready),
.o_data(w_data), .o_data(w_data),
.o_addr(reg_addr), .o_addr(reg_addr),
@@ -79,6 +93,10 @@ module RelayConTop (
.o_freq2(freq2_relay), //Freq_Slot2 .o_freq2(freq2_relay), //Freq_Slot2
.o_freq3(freq3_relay), //Freq_Slot3 .o_freq3(freq3_relay), //Freq_Slot3
.o_freq4(freq4_relay), //Freq_Slot4 .o_freq4(freq4_relay), //Freq_Slot4
.o_DC1(DC_Con1),
.o_DC2(DC_Con2),
.o_DC3(DC_Con3),
.o_DC4(DC_Con4),
.o_rvalid(con_rvalid), .o_rvalid(con_rvalid),
.o_rdata(r_data), .o_rdata(r_data),
.o_exec(con_exec), //Exec cmd .o_exec(con_exec), //Exec cmd
@@ -94,12 +112,21 @@ module RelayConTop (
.i_freq_relay2(freq2_relay), .i_freq_relay2(freq2_relay),
.i_freq_relay3(freq3_relay), .i_freq_relay3(freq3_relay),
.i_freq_relay4(freq4_relay), .i_freq_relay4(freq4_relay),
.i_DC_Con1(DC_Con1),
.i_DC_Con2(DC_Con2),
.i_DC_Con3(DC_Con3),
.i_DC_Con4(DC_Con4),
.o_PMU_OC_1(PMU_OC_1),
.o_PMU_OC_2(PMU_OC_2),
.o_PMU_OC_3(PMU_OC_3),
.o_PMU_OC_4(PMU_OC_4),
.o_con_done(con_done), .o_con_done(con_done),
.o_RC_F(RC_F), .o_RC_F(RC_F),
.o_RC_S(RC_S), .o_RC_S(RC_S),
.o_RC_T(RC_T), .o_RC_T(RC_T),
.o_OC_x09(OC_x09), .o_OC_x09(OC_x09),
.o_OC_x25(OC_x25) .o_OC_x25(OC_x25),
.o_err(cpld_err_flag)
); );
@@ -107,12 +134,34 @@ module RelayConTop (
assign o_RC_S = RC_S; assign o_RC_S = RC_S;
assign o_RC_T = RC_T[25:0]; assign o_RC_T = RC_T[25:0];
//assign o_OC_1[8] = OC_x09[0]; assign o_PMU_OC_1[8] = OC_x09[0];
//assign o_OC_2[8] = OC_x09[1]; assign o_PMU_OC_2[8] = OC_x09[1];
//assign o_OC_3[8] = OC_x09[2]; assign o_PMU_OC_3[8] = OC_x09[2];
//assign o_OC_4[8] = OC_x09[3]; assign o_PMU_OC_4[8] = OC_x09[3];
assign o_err = bus_err_flag || reg_err_flag; assign o_PMU_OC_1[24] = OC_x25[0];
assign o_PMU_OC_2[24] = OC_x25[1];
assign o_PMU_OC_3[24] = OC_x25[2];
assign o_PMU_OC_4[24] = OC_x25[3];
assign o_PMU_OC_1[7:0] = PMU_OC_1[7:0];
assign o_PMU_OC_1[23:9] = PMU_OC_1[23:8];
assign o_PMU_OC_1[31:25] = PMU_OC_1[31:25];
assign o_PMU_OC_2[7:0] = PMU_OC_2[7:0];
assign o_PMU_OC_2[23:9] = PMU_OC_2[23:9];
assign o_PMU_OC_2[31:25] = PMU_OC_2[31:25];
assign o_PMU_OC_3[7:0] = PMU_OC_3[7:0];
assign o_PMU_OC_3[23:9] = PMU_OC_3[23:9];
assign o_PMU_OC_3[31:25]= PMU_OC_3[31:25];
assign o_PMU_OC_4[7:0] = PMU_OC_4[7:0];
assign o_PMU_OC_4[23:9] = PMU_OC_4[23:9];
assign o_PMU_OC_4[31:25] = PMU_OC_4[31:25];
assign o_err = bus_err_flag || reg_err_flag || cpld_err_flag;
endmodule endmodule
2.FW/CPLD2/tb_RelayConTop.sv
+924 -270
View File
File diff suppressed because it is too large Load Diff
2.FW/CPLD3/.setting.ini
+3 -2
View File
@@ -1,2 +1,3 @@
[General] [General]
Export.auto_tasks=Bitgen, Jedecgen Export.auto_tasks=Bitgen, Jedecgen
Map.auto_tasks=MapTrace
2.FW/CPLD3/.spreadsheet_view.ini
+1 -1
View File
@@ -3,7 +3,7 @@ pin_sort_type=0
pin_sort_ascending=true pin_sort_ascending=true
sig_sort_type=0 sig_sort_type=0
sig_sort_ascending=true sig_sort_ascending=true
active_Sheet=Pin Assignments active_Sheet=Port Assignments
[Port%20Assignments] [Port%20Assignments]
Name="193,0" Name="193,0"
2.FW/CPLD3/CPLD_Con.v
+79 -21
View File
@@ -6,6 +6,13 @@ module CPLD_Con (
input [23:0]i_freq_relay2, input [23:0]i_freq_relay2,
input [23:0]i_freq_relay3, input [23:0]i_freq_relay3,
input [23:0]i_freq_relay4, input [23:0]i_freq_relay4,
// DC related Control
input [23:0]i_DC_Con1,
input [23:0]i_DC_Con2,
input [23:0]i_DC_Con3,
input [23:0]i_DC_Con4,
output o_con_done, output o_con_done,
output [3:0]o_PMU_RC, output [3:0]o_PMU_RC,
output o_err output o_err
@@ -14,10 +21,16 @@ module CPLD_Con (
//Relay Reg //Relay Reg
reg [3:0] PMU_RC; reg [3:0] PMU_RC;
//Condition Tester
reg [15:0]en_t ;
reg freq_t;
reg dc_t;
//Flags //Flags
reg exec_flag; reg exec_flag;
reg err_flag; reg err_flag;
reg [3:0]slot_exec_flag; reg [3:0]freq_slot_flag;
reg [3:0]dc_slot_flag;
reg done_flag; reg done_flag;
//Counter //Counter
@@ -37,11 +50,27 @@ module CPLD_Con (
end end
end end
//Function Identify
always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin
en_t <= 'd0;
freq_t <= 'd0;
dc_t <= 'd0;
end
else begin
en_t <= (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) + (i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0] );
freq_t <= i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0];
dc_t <= i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0];
end
end
// Main Controller Function
always @(posedge i_sys_clk) begin always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin if (i_rst_n == 1'b0) begin
exec_flag <= 1'b0; exec_flag <= 1'b0;
err_flag <= 1'b0; err_flag <= 1'b0;
slot_exec_flag <= 'd0; freq_slot_flag <= 'd0;
dc_slot_flag<='d0;
done_flag <= 'd1; done_flag <= 'd1;
PMU_RC <= 4'b1111; PMU_RC <= 4'b1111;
end end
@@ -50,31 +79,60 @@ module CPLD_Con (
exec_flag <= 1'b1; exec_flag <= 1'b1;
done_flag <= 1'b0; done_flag <= 1'b0;
//To DO: More Sanity Check? //To DO: More Sanity Check?
if ( (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) > 2'd1 ) begin if (en_t > 'd1) begin //Only ONE Enable bit should be set!
err_flag <= 1'b1; err_flag <= 1'b1;
end end
else begin else begin
slot_exec_flag[0] <= i_freq_relay1[0]; freq_slot_flag[0] <= i_freq_relay1[0];
slot_exec_flag[1] <= i_freq_relay2[0]; freq_slot_flag[1] <= i_freq_relay2[0];
slot_exec_flag[2] <= i_freq_relay3[0]; freq_slot_flag[2] <= i_freq_relay3[0];
slot_exec_flag[3] <= i_freq_relay4[0]; freq_slot_flag[3] <= i_freq_relay4[0];
dc_slot_flag[0] <= i_DC_Con1[0];
dc_slot_flag[1] <= i_DC_Con2[0];
dc_slot_flag[2] <= i_DC_Con3[0];
dc_slot_flag[3] <= i_DC_Con4[0];
end end
end end
else if (exec_flag == 1'b1) begin else if (exec_flag == 1'b1) begin
case (slot_exec_flag) if (freq_t == 1'b1) begin
4'b0001: begin case (freq_slot_flag)
PMU_RC <= 4'b1111; 4'b0001: begin
end PMU_RC <= 4'b1111;
4'b0010: begin end
PMU_RC <= 4'b1100; 4'b0010: begin
end PMU_RC <= 4'b1100;
4'b0100: begin end
PMU_RC <= 4'b1010; 4'b0100: begin
end PMU_RC <= 4'b1010;
4'b1000: begin end
PMU_RC <= 4'b0110; 4'b1000: begin
end PMU_RC <= 4'b0110;
endcase end
default:begin
PMU_RC <= 4'b0000;
end
endcase
end
else if (dc_t == 1'b1) begin
case (dc_slot_flag)
4'b0001: begin
PMU_RC <= 4'b0001;
end
4'b0010: begin
PMU_RC <= 4'b0010;
end
4'b0100: begin
PMU_RC <= 4'b0100;
end
4'b1000: begin
PMU_RC <= 4'b1000;
end
default:begin
PMU_RC <= 4'b0000;
end
endcase
end
done_flag <= 1'b1; done_flag <= 1'b1;
end end
end end
2.FW/CPLD3/Reg_file.v
+16 -3
View File
@@ -21,13 +21,19 @@ module Reg_file (
output [23:0] o_freq1, output [23:0] o_freq1,
output [23:0] o_freq2, output [23:0] o_freq2,
output [23:0] o_freq3, output [23:0] o_freq3,
output [23:0] o_freq4 output [23:0] o_freq4,
//DC Regs
output [23:0] o_DC1,
output [23:0] o_DC2,
output [23:0] o_DC3,
output [23:0] o_DC4
); );
// --- Parameters --- // --- Parameters ---
localparam REG_COUNT = 16; localparam REG_COUNT = 16;
localparam [23:0] localparam [23:0]
IDENT = 24'h800000|| 12'b0001_0000_0000, //CPLD3==1,version=1.0.0 IDENT = 24'h800000 | 12'b0001_0000_0000, //CPLD3==1,version=1.0.0
STATE_INIT = 24'h800000; STATE_INIT = 24'h800000;
// State Machine Definition // State Machine Definition
@@ -125,7 +131,9 @@ module Reg_file (
// Wait for Controller to register the command and pull 'done' LOW (Busy) // Wait for Controller to register the command and pull 'done' LOW (Busy)
EXEC_ACK: begin EXEC_ACK: begin
busy_flag <= 1'b1; busy_flag <= 1'b1;
state <= EXEC_WAIT; if (i_con_done == 1'b0) begin
state <= EXEC_WAIT;
end
// Optional: Timeout counter here to prevent hanging if Controller is dead // Optional: Timeout counter here to prevent hanging if Controller is dead
end end
@@ -162,4 +170,9 @@ module Reg_file (
assign o_freq3 = regtable[4]; assign o_freq3 = regtable[4];
assign o_freq4 = regtable[5]; assign o_freq4 = regtable[5];
assign o_DC1 = regtable[6];
assign o_DC2 = regtable[7];
assign o_DC3 = regtable[8];
assign o_DC4 = regtable[9];
endmodule endmodule
2.FW/CPLD3/RelayConTop.v
+23 -8
View File
@@ -6,23 +6,24 @@ module RelayConTop (
input i_mosi, input i_mosi,
input i_cs, input i_cs,
output o_miso, output o_miso,
output o_rvaild, output o_rvalid,
input i_rready, input i_rready,
input i_wvaild, input i_wvaild,
output [3:0]o_PMU_RC,
output o_wready, output o_wready,
output o_err, output o_err,
output o_con_done, output o_con_done
output [3:0]o_PMU_RC
); );
wire [3:0]PMU_RC ; wire [3:0]PMU_RC ;
wire [23:0]r_data ; wire [23:0]r_data ;
wire [23:0]w_data ; wire [23:0]w_data ;
wire [6:0]reg_addr ; wire [6:0]reg_addr ;
wire cmd_vaild; wire cmd_valid;
wire reg_busy; wire reg_busy;
wire wr_flag; //1=write,0=read wire wr_flag; //1=write,0=read
wire bus_err_flag; wire bus_err_flag;
@@ -34,8 +35,14 @@ module RelayConTop (
wire [23:0]freq2_relay ; wire [23:0]freq2_relay ;
wire [23:0]freq3_relay ; wire [23:0]freq3_relay ;
wire [23:0]freq4_relay ; wire [23:0]freq4_relay ;
wire con_rvaild;
//DC Control Reg output
wire [23:0]DC_Con1 ;
wire [23:0]DC_Con2 ;
wire [23:0]DC_Con3 ;
wire [23:0]DC_Con4 ;
wire con_rvaild;
wire con_done; wire con_done;
BUS_Con Bus_Con_3( BUS_Con Bus_Con_3(
@@ -48,7 +55,7 @@ module RelayConTop (
.i_wvalid(i_wvalid), .i_wvalid(i_wvalid),
.i_reg_busy(reg_busy), .i_reg_busy(reg_busy),
.i_rdata(r_data), .i_rdata(r_data),
.o_cmd_valid(cmd_vaild), .o_cmd_valid(cmd_valid),
.o_wr(wr_flag), .o_wr(wr_flag),
.o_miso(o_miso), .o_miso(o_miso),
.o_rvalid(o_rvalid), .o_rvalid(o_rvalid),
@@ -61,7 +68,7 @@ module RelayConTop (
Reg_file CPLD_Reg_3( Reg_file CPLD_Reg_3(
.i_sys_clk(i_sys_clk), .i_sys_clk(i_sys_clk),
.i_rst_n(i_rst_n), .i_rst_n(i_rst_n),
.i_wr_req(cmd_vaild), .i_wr_req(cmd_valid),
.i_wr(wr_flag), .i_wr(wr_flag),
.i_addr(reg_addr), .i_addr(reg_addr),
.i_wdata(w_data), .i_wdata(w_data),
@@ -70,6 +77,10 @@ module RelayConTop (
.o_freq2(freq2_relay), //Freq_Slot2 .o_freq2(freq2_relay), //Freq_Slot2
.o_freq3(freq3_relay), //Freq_Slot3 .o_freq3(freq3_relay), //Freq_Slot3
.o_freq4(freq4_relay), //Freq_Slot4 .o_freq4(freq4_relay), //Freq_Slot4
.o_DC1(DC_Con1),
.o_DC2(DC_Con2),
.o_DC3(DC_Con3),
.o_DC4(DC_Con4),
.o_rvalid(con_rvalid), .o_rvalid(con_rvalid),
.o_rdata(r_data), .o_rdata(r_data),
.o_exec(con_exec), //Exec cmd .o_exec(con_exec), //Exec cmd
@@ -81,6 +92,10 @@ module RelayConTop (
.i_sys_clk(i_sys_clk), .i_sys_clk(i_sys_clk),
.i_rst_n(i_rst_n), .i_rst_n(i_rst_n),
.i_con_exec(con_exec), .i_con_exec(con_exec),
.i_DC_Con1(DC_Con1),
.i_DC_Con2(DC_Con2),
.i_DC_Con3(DC_Con3),
.i_DC_Con4(DC_Con4),
.i_freq_relay1(freq1_relay), .i_freq_relay1(freq1_relay),
.i_freq_relay2(freq2_relay), .i_freq_relay2(freq2_relay),
.i_freq_relay3(freq3_relay), .i_freq_relay3(freq3_relay),
2.FW/CPLD3/tb_RelayConTop.sv
+799 -270
View File
File diff suppressed because it is too large Load Diff
2.FW/Zynq/proj_cal/Vitis/.gitignore
+17
View File
@@ -0,0 +1,17 @@
# Ignore build output directory
/build
# Ignore object files and dependent files
.o
.d
#Ignore logs folder and log files
/logs
.log
#Ignore lock files
.lock
.bin
.pdi
2.FW/Zynq/proj_cal/Vitis/.peers.ini
+65
View File
@@ -0,0 +1,65 @@
DefaultTarget=true
ServiceManagerID=0362f829-e89b-432f-b55e-58f745adaf5d
TransportName=TCP
AutoSetJtagFrequency=false
PeerTypeId=LINUX_EMULATION
UserName=ly0kos
Port=1440
Host=127.0.0.1
OSName=Linux
ID=LinuxEmulation
AgentID=0362f829-e89b-432f-b55e-58f745adaf5d
Name=LinuxEmulation
DefaultTarget=true
ServiceManagerID=0362f829-e89b-432f-b55e-58f745adaf5d
TransportName=TCP
AutoSetJtagFrequency=false
PeerTypeId=XRT_SERVER
UserName=ly0kos
Port=1222
Host=127.0.0.1
OSName=Linux
ID=XRTServer
AgentID=0362f829-e89b-432f-b55e-58f745adaf5d
Name=XRTServer
DefaultTarget=true
ServiceManagerID=0362f829-e89b-432f-b55e-58f745adaf5d
TransportName=TCP
AutoSetJtagFrequency=true
PeerTypeId=HARDWARE_SERVER
UserName=ly0kos
Port=3121
Host=127.0.0.1
OSName=Linux
ID=Local
AgentID=0362f829-e89b-432f-b55e-58f745adaf5d
Name=Local
DefaultTarget=true
ServiceManagerID=0362f829-e89b-432f-b55e-58f745adaf5d
TransportName=TCP
AutoSetJtagFrequency=false
PeerTypeId=LINUX_TCF_AGENT
UserName=ly0kos
Port=1534
Host=192.168.0.1
OSName=Linux
ID=Linux Agent
AgentID=0362f829-e89b-432f-b55e-58f745adaf5d
Name=Linux Agent
DefaultTarget=true
ServiceManagerID=0362f829-e89b-432f-b55e-58f745adaf5d
TransportName=TCP
AutoSetJtagFrequency=false
PeerTypeId=QEMU_TCF_GDB_CLIENT
UserName=ly0kos
Port=1138
Host=127.0.0.1
OSName=Linux
ID=QEMU
AgentID=0362f829-e89b-432f-b55e-58f745adaf5d
Name=QEMU
2.FW/Zynq/proj_cal/Vitis/.repo.yaml
+436
View File
@@ -0,0 +1,436 @@
paths:
/data/xilinx/Vitis/2023.2/data/embeddedsw: {}
os:
freertos10_xilinx:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/ThirdParty/bsp/freertos10_xilinx_v1_14
standalone:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/lib/bsp/standalone_v9_0
driver:
devcfg:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/devcfg_v3_8
qspips:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/qspips_v3_11
resetps:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/resetps_v1_6
scugic:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/scugic_v5_2
sysmonpsv:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/sysmonpsv_v4_1
uartps:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/uartps_v3_13
uartlite:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/uartlite_v3_9
wdttb:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/wdttb_v5_7
wdtps:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/wdtps_v3_6
cfupmc:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/cfupmc_v1_6
csudma:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/csudma_v1_14
dfeccf:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/dfeccf_v1_6
dfxasm:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/dfxasm_v1_2
ipipsu:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/ipipsu_v2_14
pciepsu:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/pciepsu_v1_6
rtcpsu:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/rtcpsu_v1_13
uartpsv:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/uartpsv_v1_9
common:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/common_v1_3
dfemix:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/dfemix_v1_6
dfeprach:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/dfeprach_v1_6
qspipsu:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/qspipsu_v1_18
trngpsv:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/trngpsv_v1_4
trngpsx:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/trngpsx_v1_1
ttcps:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/ttcps_v3_18
ddrcpsu:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/ddrcpsu_v1_5
dfeequ:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/dfeequ_v1_5
sdps:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/sdps_v4_2
emacps:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/emacps_v3_19
sd_fec:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/sd_fec_v1_3
cframe:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/cframe_v1_5
clockps:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/clockps_v1_5
coresightps_dcc:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/coresightps_dcc_v1_9
dfeofdm:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/dfeofdm_v1_1
zdma:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/zdma_v1_17
iomodule:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/iomodule_v2_15
xdmapcie:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/xdmapcie_v1_7
ospipsv:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/ospipsv_v1_9
aienginev2:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/aienginev2_v3_4
axicdma:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/axicdma_v4_12
axis_switch:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/axis_switch_v1_6
bram:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/bram_v4_9
clk_wiz:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/clk_wiz_v1_6
hwicap:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/hwicap_v11_6
mcdma:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/mcdma_v1_9
spi:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/spi_v4_11
tmrctr:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/tmrctr_v4_11
usbpsu:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/usbpsu_v1_14
v_frmbuf_rd:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/v_frmbuf_rd_v4_7
avbuf:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/avbuf_v2_6
axidma:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/axidma_v9_17
canfd:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/canfd_v2_8
gpio:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/gpio_v4_10
iicps:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/iicps_v3_18
intc:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/intc_v3_17
mbox:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/mbox_v4_6
prd:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/prd_v2_2
spips:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/spips_v3_9
sysmonpsu:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/sysmonpsu_v2_9
tft:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/tft_v6_4
trafgen:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/trafgen_v4_5
usbps:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/usbps_v2_8
usb:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/usb_v5_6
v_tpg:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/v_tpg_v8_5
can:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/can_v3_7
dpdma:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/dpdma_v1_5
dppsu:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/dppsu_v1_7
emaclite:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/emaclite_v4_8
rfdc:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/rfdc_v12_1
scutimer:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/scutimer_v2_5
sysmon:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/sysmon_v7_8
video_common:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/video_common_v4_14
xadcps:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/xadcps_v2_7
axiethernet:
path:
- /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/axiethernet_v5_16
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]
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/.clangd
+4
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@@ -0,0 +1,4 @@
CompileFlags:
Add: [-Wno-unknown-warning-option, -U__linux__, -U__clang__]
Remove: [-m*, -f*]
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/CMakeLists.txt
+64
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@@ -0,0 +1,64 @@
# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
# SPDX-License-Identifier: MIT
cmake_minimum_required(VERSION 3.16)
include(${CMAKE_SOURCE_DIR}/Empty_applicationExample.cmake)
include(${CMAKE_CURRENT_SOURCE_DIR}/UserConfig.cmake)
set(APP_NAME NewCalBoard_APP)
project(${APP_NAME})
find_package(common)
enable_language(C ASM CXX)
collect(PROJECT_LIB_DEPS xilstandalone)
collect(PROJECT_LIB_DEPS xil)
collect(PROJECT_LIB_DEPS xiltimer;lwip213)
collect(PROJECT_LIB_DEPS gcc)
collect(PROJECT_LIB_DEPS c)
aux_source_directory(${CMAKE_SOURCE_DIR} _sources)
foreach (source ${_sources})
get_filename_component(ext ${source} EXT)
list(APPEND src_ext ${ext})
endforeach()
find_project_type ("${src_ext}" PROJECT_TYPE)
if("${PROJECT_TYPE}" STREQUAL "c++")
collect(PROJECT_LIB_DEPS stdc++)
endif()
collector_list (_deps PROJECT_LIB_DEPS)
list (APPEND _deps ${USER_LINK_LIBRARIES})
if("${PROJECT_TYPE}" STREQUAL "c++")
string (REPLACE ";" ",-l" _deps "${_deps}")
endif()
if(CMAKE_EXPORT_COMPILE_COMMANDS)
set(CMAKE_CXX_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_CXX_IMPLICIT_INCLUDE_DIRECTORIES})
set(CMAKE_C_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_C_IMPLICIT_INCLUDE_DIRECTORIES})
endif()
linker_gen("${CMAKE_SOURCE_DIR}/linker_files/")
string(APPEND CMAKE_C_FLAGS ${USER_COMPILE_OPTIONS})
string(APPEND CMAKE_CXX_FLAGS ${USER_COMPILE_OPTIONS})
string(APPEND CMAKE_C_LINK_FLAGS ${USER_LINK_OPTIONS})
string(APPEND CMAKE_CXX_LINK_FLAGS ${USER_LINK_OPTIONS})
if(NOT "${_sources}" STREQUAL "")
set_source_files_properties(${_sources} OBJECT_DEPENDS "${CMAKE_LIBRARY_PATH}/*.a")
add_executable(${APP_NAME}.elf ${_sources})
set_target_properties(${APP_NAME}.elf PROPERTIES LINK_DEPENDS ${CMAKE_SOURCE_DIR}/lscript.ld)
target_link_libraries(${APP_NAME}.elf -Wl,-T -Wl,\"${CMAKE_SOURCE_DIR}/lscript.ld\" -L\"${CMAKE_SOURCE_DIR}/\" -L\"${CMAKE_LIBRARY_PATH}/\" -L\"${USER_LINK_DIRECTORIES}/\" -Wl,--start-group,-l${_deps} -Wl,--end-group)
target_compile_definitions(${APP_NAME}.elf PUBLIC ${USER_COMPILE_DEFINITIONS})
target_include_directories(${APP_NAME}.elf PUBLIC ${USER_INCLUDE_DIRECTORIES})
print_elf_size(CMAKE_SIZE ${APP_NAME})
endif()
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/Empty_applicationExample.cmake
+13
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@@ -0,0 +1,13 @@
set(DDR ps7_ddr_0)
set(ps7_ddr_0 "0x100000;0x3ff00000")
set(ps7_ram_0 "0x0;0x30000")
set(ps7_ram_1 "0xffff0000;0xfe00")
set(TOTAL_MEM_CONTROLLERS "ps7_ddr_0;ps7_ram_0;ps7_ram_1")
set(MEMORY_SECTION "MEMORY
{
ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x3ff00000
ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
ps7_ram_1 : ORIGIN = 0xffff0000, LENGTH = 0xfe00
}")
set(STACK_SIZE 0x2000)
set(HEAP_SIZE 0x2000)
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/GPIO_Driv.c
+113
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@@ -0,0 +1,113 @@
/*
* GPIO_Driv.c
*
* Created on: 2021年5月7日
* Author: Administrator
*/
#include "GPIO_Driv.h"
#include "xil_printf.h"
#include "xparameters.h"
XGpioPs psGpioInstancePtr; //端口
XGpioPs_Config* GpioConfigPtr; //设备ID
//sck,cs,sdi,sdo,rst
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
void EMIO_config(void)
{
int xStatus;
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_XGPIOPS_0_BASEADDR);
if(GpioConfigPtr == NULL)
{
xil_printf("PS GPIO LookupConfig failed\n\r");
return;
}
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
if(XST_SUCCESS != xStatus)
print(" PS GPIO INIT FAILED \n\r");
/*-------------------------------------CPLD_U1------------------------------------*/
//--设置EMIO方向
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---cs
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---sdi
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 0);//57---sdo
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 1);//58---rst_n
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
//使能EMIO输出 1=output 0=input
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---cs
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---sdi
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);//57---sdo
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);//58---rst_n
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//59
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//60
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//61
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//62
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//63
/*-------------------------------------CPLD_U2------------------------------------*/
//--设置EMIO方向
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---cs
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---sdi
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//68---sdo
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//69---rst_n
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//70
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//71
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//72
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//73
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//74
//使能EMIO输出 1=output 0=input
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---cs
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---sdi
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);//68---sdo
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);//69---rst_n
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);//70
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);//71
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);//72
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);//73
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);//74
/*-------------------------------------CPLD_U3------------------------------------*/
//--设置EMIO方向
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//76---sck
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//77---cs
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//78---sdi
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 0);//79---sdo
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 1);//80---rst_n
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//81
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//82
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//83
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//84
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//85
//使能EMIO输出 1=output 0=input
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//76---sck
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//77---cs
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//78---sdi
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 0);//79---sdo
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 1);//80---rst_n
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);//81
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);//82
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);//83
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);//84
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);//85
}
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/GPIO_Driv.h
+25
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@@ -0,0 +1,25 @@
/*
* GPIO_Driv.h
*
* Created on: 2021年4月2日
* Author: dell
*/
#ifndef SRC_GPIO_DRIV_H_
#define SRC_GPIO_DRIV_H_
#include "stdio.h"
#include "xgpiops.h"
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
extern u32 CPLD_U1[11];
extern u32 CPLD_U2[11];
extern u32 CPLD_U3[11];
void EMIO_config(void);
#endif /* SRC_GPIO_DRIV_H_ */
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/README.txt
Executable
+1
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@@ -0,0 +1 @@
Empty application. Add your own sources.
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/SPI_Driv.c
+558
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/*
* SPI_Driv.c
*
* Created on: 2021年4月2日
* Author: dell
*/
#include "SPI_Driv.h"
extern XGpioPs psGpioInstancePtr; //端口
extern XGpioPs_Config* GpioConfigPtr; //设备ID
extern u32 K7_U0[16];
extern u32 molex_4_bank_3[4];
extern u32 cs_en_bank_3[4];
/******************************************************************************
* Function : void interface_initial(u32* device,u32 num_wire)
* Description : interface initial
* Parameter : device -- CPLD
* num_wire -- 复位线编号
* Return : void
******************************************************************************/
void interface_initial(u32* device) //wire_num = cs sck sdi/o
{
u32 sck = *(device+0);
u32 cs = *(device+1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
}
/******************************************************************************
* Function : void rst_CPLD(u32* device,u32 num_wire)
* Description : CPLD reset
* Parameter : device -- CPLD
* num_wire -- 复位线编号
* Return : void
******************************************************************************/
void rst_CPLD(u32* device,u32 num_wire) //wire_num = cs sck sdi/o
{
u32 rst_n = *(device+num_wire);
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
usleep(2);
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
}
/******************************************************************************
* Function : void spi_write_onewire(char addr, u32 data, char width, u32* device)
* Description : spi onewire write
* Parameter : addr -- 地址
* data -- 数据
* width -- 数据长度
* device -- CPLD
* Return : void
******************************************************************************/
void spi_write_onewire(char addr, char *data, char width, u32* device)
{
char temp_addr = 0;
//u32 temp_data = 0;
u32 temp_data = 0;
char i = 0,j=0;
u32 sck = *(device+0);
u32 cs= *(device+1);
u32 sdi= *(device+2);
temp_addr = addr;
///temp_data = data;
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
//XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); // w/r标志位 1=w 0=r
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
for(i = 0; i < 8; i++) // 8bit地址
{
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
if(temp_addr&0x80)
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据 数据从中间变量到通信线上
else
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
temp_addr = temp_addr<<1; //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
}
for(j=0;j<width;j++)
{
temp_data = *(data+j);
for(i = 0; i < 8; i++) //nbit数据
{
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
if(temp_data&0x80) //注意数据位nbit，要从[n-1]取位
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1);
else
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
temp_data <<= 1;
}
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
}
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs , 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
}
/******************************************************************************
* Function : u32 spi_read_onewire(char addr, char width, u32* device)
* Description : spi onewire read
* Parameter : addr -- 地址
* data -- 数据
* width -- 数据长度
* device -- CPLD
* Return : void
******************************************************************************/
u32 spi_read_onewire(char addr, char width, u32* device,char* read_data)
{
char temp_addr=0;
u32 temp_data=0;
char i=0,j=0;
u32 sck = *(device+0);
u32 cs= *(device+1);
u32 sdi= *(device+2);
u32 sdo= *(device+3);
temp_addr = addr;
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
//XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0); // w/r标志位 1=w 0=r
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
for(i = 0; i < 8; i++) // 8bit地址
{
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
if(temp_addr&0x80)
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据 数据从中间变量到通信线上
else
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
temp_addr = temp_addr<<1; //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
}
for(j=0; j<width; j++)
{
for(i = 0; i < 8; i++) //nbit数据
{
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
temp_data = temp_data << 1; //sck低电平准备数据 准备好数位，此时的数据相当于从右边的FPGA移进MCU(先准备好中间变量)
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
if(XGpioPs_ReadPin(&psGpioInstancePtr,sdo)) //sck高电平接收数据 数据匹配到准备好的数位，等待一起传递到MCU
temp_data = temp_data| 0x00000001;
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
}
}
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
read_data[0] = (u8)(temp_data>>16);
read_data[1] = (u8)(temp_data>>8);
read_data[0] = (u8)(temp_data);
return temp_data;
}
/******************************************************************************
* Function : void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
* Description : forwire write to reg
* Parameter : txdata--数据
* sdi0,sdi1,sdi2,sdi3--IO
* Return : void
******************************************************************************/
void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
{
switch(txdata & 0x0F)
{
case 0x00:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x01:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x02:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x03:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x04:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x05:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x06:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x07:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x08:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
case 0x09:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
case 0x0A:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
case 0x0B:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
case 0x0C:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
case 0x0D:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
case 0x0E:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
case 0x0F:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
}
}
/******************************************************************************
* Function : void spi_write_fourwire(char addr, u16 data, u32* device)
* Description : spi fourwire write
* Parameter : addr -- 地址
* data -- 数据
* width -- 数据长度
* device -- CPLD
* Return : void
******************************************************************************/
void spi_write_fourwire(char addr, u16 data, u32* device)
{
u8 temp_addr = 0;
u16 temp_data = 0;
u8 split_addr[2] = {0}; //将8bit地址拆分，分别给4线传输，
u8 split_data[4] = {0}; //16bit数据拆成4个4bit
u8 i;
u32 sck = *(device+0);
u32 cs = *(device+1);
u32 sdi0 = *(device+2);
u32 sdi1 = *(device+3);
u32 sdi2 = *(device+4);
u32 sdi3 = *(device+5);
temp_addr = addr;
temp_data = data;
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
fourwire_write(0x01,sdi0,sdi1,sdi2,sdi3); // w/r标志位 1=w 0=r
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
for(i = 0; i < 2;i++) // 8bit地址 四根线分两次传输
{
split_addr[i] = (temp_addr>>(4*(1-i)))&0x0F; //sck高电平准备数据 数据从MCU到中间变量上
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
fourwire_write(split_addr[i],sdi0,sdi1,sdi2,sdi3); //sck低电平传输数据 数据从中间变量到通信线上
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
}
for(i = 0; i < 4;i++) //16bit数据 4根线分四次传输
{
split_data[i] = (temp_data>>(4*(3-i)))&0x0F;
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
fourwire_write(split_data[i],sdi0,sdi1,sdi2,sdi3);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
}
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
fourwire_write(0x00,sdi0,sdi1,sdi2,sdi3);
//usleep(20);
}
/******************************************************************************
* Function : u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
* Description : forwire read from reg
* Parameter : sdo0,sdo1,sdo2,sdo3--IO
* Return : rxdata--数据
******************************************************************************/
u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
{
u32 GPIO_PIN[4];
u16 rdata[4];
u16 rxdata = 0;
GPIO_PIN[0] = sdo0;
GPIO_PIN[1] = sdo1;
GPIO_PIN[2] = sdo2;
GPIO_PIN[3] = sdo3;
for(u8 i = 0; i < 4 ; i++)
{
rdata[i] = XGpioPs_ReadPin(&psGpioInstancePtr,GPIO_PIN[i]);
//xil_printf("rdata[i] = %x\r\n",rdata[i]);
rxdata = ((rdata[i])<<i) + rxdata ;
}
return rxdata;
}
/******************************************************************************
* Function : void spi_read_fourwire(char addr, u16* rxdata, u32* device)
* Description : spi fourwire read
* Parameter : addr -- 地址
* rxdata -- 数据
* device -- CPLD
* Return : void
******************************************************************************/
void spi_read_fourwire(char addr, u16* rxdata, u32* device) //接收数据使用指针传递，方便接收多个
{
u8 temp_addr = 0;
u16 temp_data = 0;
u8 split_addr[2] = {0}; //将8bit地址拆分，分别给4线传输，
u16 split_data[4] = {0}; //16bit数据拆成4个4bit
u8 i = 0;
u32 sck = *(device+0);
u32 cs = *(device+1);
u32 sdio0 = *(device+2);
u32 sdio1 = *(device+3);
u32 sdio2 = *(device+4);
u32 sdio3 = *(device+5);
temp_addr = addr;
split_addr[0] = (temp_addr >> 4)&0x0F;
split_addr[1] = (temp_addr)&0x0F;
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3); // w/r标志位 1=w 0=r
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
for(i = 0; i < 2; i++) // 8bit地址 四根线分两次传输
{
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
fourwire_write(split_addr[i],sdio0,sdio1,sdio2,sdio3); //sck低电平传输数据 数据从中间变量到通信线上
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
}
for(i = 0; i < 4; i++)
{
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),0); //input
}
for(i = 0; i < 4; i++) //16bit数据 4根线分四次接收
{
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
split_data[i] = fourwire_read(sdio0,sdio1,sdio2,sdio3); //sck低电平准备数据 数据从通信线到中间变量上
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
temp_data = temp_data<<4;
temp_data = temp_data + split_data[i];
//temp_data = (split_data[i]<<(4*(3-i))) + temp_data; //sck高电平接收数据 数据从中间变量到MCU上
// xil_printf("split_data[i],temp_data = %x,%x\r\n",split_data[i],temp_data);
}
for(i = 0; i < 4; i++)
{
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),1); //output
}
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3);
*rxdata = temp_data;
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);//add 2 lines
//usleep(20);
}
/******************************************************************************
* Function : void GPIO_dir_set(u32* device,char dir)
* Description : change GPIO direction
* Parameter : device -- CPLD
* dir -- GPIO_OUT/GPIO_IN
* Return : void
******************************************************************************/
void GPIO_dir_set_16(u32* device,char dir)
{
u32 sdio[16] = {0};
u8 i;
for(i = 0; i < 16;i++)
{
sdio[i] = *(device+i);
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, sdio[i],1);
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir);
}
}
void GPIO_dir_set_cs_enable(u32* device,u8 dir)
{
u32 sdio[4] = {0};
u8 i;
u8 dir_temp = 0;
for(i = 0; i < 4;i++)
{
sdio[i] = *(device+i);
dir_temp = (((dir >> (3-i))) & 0x01);
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir_temp);
}
}
void rst(char *d)
{
XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
XGpioPs_WritePin(&psGpioInstancePtr, *d, 1);
usleep(20);
XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
}
void func_test(void)
{
XGpioPs_Write(&psGpioInstancePtr, 0x03, 0x12345678);
}
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/SPI_Driv.h
+47
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@@ -0,0 +1,47 @@
/*
* SPI_Driv.h
*
* Created on: 2021Äê4ÔÂ2ÈÕ
* Author: dell
*/
#ifndef SRC_SPI_DRIV_H_
#define SRC_SPI_DRIV_H_
#include "sleep.h"
#include "stdio.h"
#include "xgpiops.h"
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
#define wr_flag 1
#define rd_flag 0
#define GPIO_OUT 1
#define GPIO_IN 0
#define NUM_SCK_CMD 4
#define NUM_SCK_ADDR 8
#define NUM_SCK_LENGTH 4
#define NUM_SCK_ENABLE 8
#define NUM_SCK_BYTE 2
void interface_initial(u32* device);
void rst_CPLD(u32* device,u32 num_wire);
void rst(char *d);
void spi_write_onewire(char addr, char *data, char width, u32* device);
u32 spi_read_onewire(char addr,char width,u32* device,char* read_data);
void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3);
u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3);
void spi_write_fourwire(char addr,u16 data,u32* device);
void spi_read_fourwire(char addr,u16* rxdata,u32* device);
void GPIO_dir_set_16(u32* device,char dir);
void GPIO_dir_set_cs_enable(u32* device,u8 dir);
#endif /* SRC_SPI_DRIV_H_ */
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/UserConfig.cmake
+158
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@@ -0,0 +1,158 @@
# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
# SPDX-License-Identifier: MIT
cmake_minimum_required(VERSION 3.16)
### USER SETTINGS START ###
# Below settings can be customized
# User need to edit it manually as per their needs.
### DO NOT ADD OR REMOVE VARIABLES FROM THIS SECTION ###
# -----------------------------------------
# Add any compiler definitions, they will be added as extra definitions
# Example adding VERBOSE=1 will pass -DVERBOSE=1 to the compiler.
set(USER_COMPILE_DEFINITIONS
""
)
# Undefine any previously specified compiler definitions, either built in or provided with a -D option
# Example adding MY_SYMBOL will pass -UMY_SYMBOL to the compiler.
set(USER_UNDEFINED_SYMBOLS
"__clang__"
)
# Add any directories below, they will be added as extra include directories.
# Example 1: Adding /proj/data/include will pass -I/proj/data/include
# Example 2: Adding ../../common/include will consider the path as relative to this component directory.
# Example 3: Adding ${CMAKE_SOURCE_DIR}/data/include to add data/include from this project.
set(USER_INCLUDE_DIRECTORIES
"${CMAKE_SOURCE_DIR}/../../NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include"
)
# -----------------------------------------
# Turn on all optional warnings (-Wall)
set(USER_COMPILE_WARNINGS_ALL -Wall)
# Enable extra warning flags (-Wextra)
set(USER_COMPILE_WARNINGS_EXTRA -Wextra)
# Make all warnings into hard errors (-Werror)
set(USER_COMPILE_WARNINGS_AS_ERRORS )
# Check the code for syntax errors, but don't do anything beyond that. (-fsyntax-only)
set(USER_COMPILE_WARNINGS_CHECK_SYNTAX_ONLY )
# Issue all the mandatory diagnostics listed in the C standard (-pedantic)
set(USER_COMPILE_WARNINGS_PEDANTIC )
# Issue all the mandatory diagnostics, and make all mandatory diagnostics into errors. (-pedantic-errors)
set(USER_COMPILE_WARNINGS_PEDANTIC_AS_ERRORS )
# Suppress all warnings (-w)
set(USER_COMPILE_WARNINGS_INHIBIT_ALL )
# -----------------------------------------
# Optimization level "-O0" [None] , "-O1" [Optimize] , "-O2" [Optimize More], "-O3" [Optimize Most] or "-Os" [Optimize Size]
set(USER_COMPILE_OPTIMIZATION_LEVEL -O0)
# Other flags related to optimization
set(USER_COMPILE_OPTIMIZATION_OTHER_FLAGS )
# -----------------------------------------
# Debug level "" [None], "-g1" [Minimum], "g2" [Default], "g3" [Maximim]
set(USER_COMPILE_DEBUG_LEVEL -g3)
# Other flags releated to debugging
set(USER_COMPILE_DEBUG_OTHER_FLAGS )
# -----------------------------------------
# Enable Profiling (-pg) (This feature is not supported currently)
# set(USER_COMPILE_PROFILING_ENABLE )
# -----------------------------------------
# Verbose (-v)
set(USER_COMPILE_VERBOSE )
# Support ANSI_PROGRAM (-ansi)
set(USER_COMPILE_ANSI )
# Add any compiler options that are not covered by the above variables, they will be added as extra compiler options
# To enable profiling -pg [ for gprof ] or -p [ for prof information ]
set(USER_COMPILE_OTHER_FLAGS )
# -----------------------------------------
# Linker options
# Do not use the standard system startup files when linking.
# The standard system libraries are used normally, unless -nostdlib or -nodefaultlibs is used. (-nostartfiles)
set(USER_LINK_NO_START_FILES )
# Do not use the standard system libraries when linking. (-nodefaultlibs)
set(USER_LINK_NO_DEFAULT_LIBS )
# Do not use the standard system startup files or libraries when linking. (-nostdlib)
set(USER_LINK_NO_STDLIB )
# Omit all symbol information (-s)
set(USER_LINK_OMIT_ALL_SYMBOL_INFO )
# -----------------------------------------
# Add any libraries to be linked below, they will be added as extra libraries.
# User need to update USER_LINK_DIRECTORIES below with these library paths.
set(USER_LINK_LIBRARIES
)
# Add any directories to look for the libraries to be linked.
# Example 1: Adding /proj/compression/lib will pass -L/proj/compression/lib to the linker.
# Example adding Adding ../../common/lib will consider the path as relative to this directory. and will pass the path to -L option.
set(USER_LINK_DIRECTORIES
)
# -----------------------------------------
set(USER_LINKER_SCRIPT "${CMAKE_SOURCE_DIR}/lscript.ld")
# Add linker options to be passed, they will be added as extra linker options
# Example : adding -s will pass -s to the linker.
set(USER_LINK_OTHER_FLAGS
)
# -----------------------------------------
### END OF USER SETTINGS SECTION ###
### DO NOT EDIT BEYOND THIS LINE ###
set(USER_COMPILE_OPTIONS
" ${USER_COMPILE_WARNINGS_ALL}"
" ${USER_COMPILE_WARNINGS_EXTRA}"
" ${USER_COMPILE_WARNINGS_AS_ERRORS}"
" ${USER_COMPILE_WARNINGS_CHECK_SYNTAX_ONLY}"
" ${USER_COMPILE_WARNINGS_PEDANTIC}"
" ${USER_COMPILE_WARNINGS_PEDANTIC_AS_ERRORS}"
" ${USER_COMPILE_WARNINGS_INHIBIT_ALL}"
" ${USER_COMPILE_OPTIMIZATION_LEVEL}"
" ${USER_COMPILE_OPTIMIZATION_OTHER_FLAGS}"
" ${USER_COMPILE_DEBUG_LEVEL}"
" ${USER_COMPILE_DEBUG_OTHER_FLAGS}"
" ${USER_COMPILE_VERBOSE}"
" ${USER_COMPILE_ANSI}"
" ${USER_COMPILE_OTHER_FLAGS}"
)
foreach(entry ${USER_UNDEFINED_SYMBOLS})
list(APPEND USER_COMPILE_OPTIONS " -U${entry}")
endforeach()
set(USER_LINK_OPTIONS
" ${USER_LINKER_NO_START_FILES}"
" ${USER_LINKER_NO_DEFAULT_LIBS}"
" ${USER_LINKER_NO_STDLIB}"
" ${USER_LINKER_OMIT_ALL_SYMBOL_INFO}"
" ${USER_LINK_OTHER_FLAGS}"
)
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/app.yaml
+3
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@@ -0,0 +1,3 @@
domain_path: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0
app_src_dir: /data/xilinx/Vitis/2023.2/data/embeddedsw/lib/sw_apps/empty_application
template: empty_application
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/cal_meas.c
+255
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@@ -0,0 +1,255 @@
/*
* cal_meas.c
*
* Created on: 2023年7月19日
* Author: dell
*/
#include "cal_meas.h"
#include "SPI_Driv.h"
char sw_config_data[3] = {0x00,0x00,0x00};
void sw_config(char *slot_start)
{
char slot = (*slot_start);
char m_fun = *(slot_start+1);
char ch_num_h = *(slot_start+2);
char ch_num_l = *(slot_start+3);
char volt_cur = *(slot_start+4);
char load = *(slot_start+5);
char memt_areal = *(slot_start+6);
u16 ch_num = 0;
u32 ch_num_dat = 0;
u32 relay_ctrl = 0;
u32 slot_en = 0x00000001;
u8 cpld_addr = 0;
u32 cpld_dat = 0;
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
if(slot==1)
{
cpld_addr = 0x82;
}
else if(slot==2)
{
cpld_addr = 0x83;
}
else if(slot==3)
{
cpld_addr = 0x84;
}
else
{
cpld_addr = 0x85;
}
switch(ch_num)
{
case 0x0001:
{
relay_ctrl = 0x00000000;
break;
}
case 0x0002:
{
relay_ctrl = 0x00020000;
break;
}
case 0x0003:
{
relay_ctrl = 0x00200000;
break;
}
case 0x0004:
{
relay_ctrl = 0x00220000;
break;
}
case 0x0005:
{
relay_ctrl = 0x00800000;
break;
}
case 0x0006:
{
relay_ctrl = 0x00810000;
break;
}
case 0x0007:
{
relay_ctrl = 0x00A00000;
break;
}
case 0x0008:
{
relay_ctrl = 0x00A10000;
break;
}
case 0x0041:
{
relay_ctrl = 0x00000000;
break;
}
case 0x0042:
{
relay_ctrl = 0x00008000;
break;
}
case 0x0043:
{
relay_ctrl = 0x00100000;
break;
}
case 0x0044:
{
relay_ctrl = 0x00108000;
break;
}
case 0x0045:
{
relay_ctrl = 0x00800000;
break;
}
case 0x0046:
{
relay_ctrl = 0x00804000;
break;
}
case 0x0047:
{
relay_ctrl = 0x00900000;
break;
}
case 0x0048:
{
relay_ctrl = 0x00904000;
break;
}
case 0x0081:
{
relay_ctrl = 0x00000000;
break;
}
case 0x0082:
{
relay_ctrl = 0x00002000;
break;
}
case 0x0083:
{
relay_ctrl = 0x00080000;
break;
}
case 0x0084:
{
relay_ctrl = 0x00082000;
break;
}
case 0x0085:
{
relay_ctrl = 0x00400000;
break;
}
case 0x0086:
{
relay_ctrl = 0x00401000;
break;
}
case 0x0087:
{
relay_ctrl = 0x00480000;
break;
}
case 0x0088:
{
relay_ctrl = 0x00481000;
break;
}
case 0x00C1:
{
relay_ctrl = 0x00000000;
break;
}
case 0x00C2:
{
relay_ctrl = 0x00000800;
break;
}
case 0x00C3:
{
relay_ctrl = 0x00040000;
break;
}
case 0x00C4:
{
relay_ctrl = 0x00040800;
break;
}
case 0x00C5:
{
relay_ctrl = 0x00400000;
break;
}
case 0x00C6:
{
relay_ctrl = 0x00400400;
break;
}
case 0x00C7:
{
relay_ctrl = 0x00440000;
break;
}
case 0x00C8:
{
relay_ctrl = 0x00440400;
break;
}
}
ch_num_dat = ((u32)ch_num)<<1;
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
sw_config_data[0] = (u8)(cpld_dat>>16);
sw_config_data[1] = (u8)(cpld_dat>>8);
sw_config_data[2] = (u8)(cpld_dat);
xil_printf("relay_ctrl: %d\n\r", relay_ctrl);
xil_printf("ch_num_dat: %d\n\r", ch_num_dat);
xil_printf("cpld_addr: %d\n\r", cpld_addr);
xil_printf("cpld_dat: %d\n\r", cpld_dat);
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[0]);
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[1]);
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[2]);
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
sw_config_data[0] = 0x00;
sw_config_data[1] = 0x00;
sw_config_data[2] = 0x01;
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U1);
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U2);
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U3);
slot_en = 0x00000000;
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
sw_config_data[0] = (u8)(cpld_dat>>16);
sw_config_data[1] = (u8)(cpld_dat>>8);
sw_config_data[2] = (u8)(cpld_dat);
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
}
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/cal_meas.h
+23
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@@ -0,0 +1,23 @@
/*
* cal_meas.h
*
* Created on: 2023年7月19日
* Author: dell
*/
#ifndef SRC_CAL_MEAS_H_
#define SRC_CAL_MEAS_H_
#include "sleep.h"
#include "stdio.h"
#include "xgpiops.h"
#include "SPI_Driv.h"
#include "GPIO_Driv.h"
#define dat_width 3
void sw_config(char *slot_start);
#endif /* SRC_CAL_MEAS_H_ */
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/compile_commands.json
+62
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@@ -0,0 +1,62 @@
[
{
"directory": "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/build",
"command": "/data/xilinx/Vitis/2023.2/gnu/aarch32/lin/gcc-arm-none-eabi/bin/arm-none-eabi-gcc -I/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/../../NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include -isystem /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include -isystem /data/xilinx/Vitis/2023.2/gnu/aarch32/lin/gcc-arm-none-eabi/x86_64-oesdk-linux/usr/lib/arm-xilinx-eabi/gcc/arm-xilinx-eabi/12.2.0/include -isystem /data/xilinx/Vitis/2023.2/gnu/aarch32/lin/gcc-arm-none-eabi/x86_64-oesdk-linux/usr/lib/arm-xilinx-eabi/gcc/arm-xilinx-eabi/12.2.0/include-fixed -isystem /data/xilinx/Vitis/2023.2/gnu/aarch32/lin/gcc-arm-none-eabi/aarch32-xilinx-eabi/usr/include -O2 -DSDT -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -MMD -MP -specs=/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/Xilinx.spec -I/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include -Wall -Wextra -O0 -g3 -U__clang__ -o CMakeFiles/NewCalBoard_APP.elf.dir/GPIO_Driv.c.obj -c /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/GPIO_Driv.c",
"file": "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/GPIO_Driv.c"
},
{
"directory": "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/build",
"command": "/data/xilinx/Vitis/2023.2/gnu/aarch32/lin/gcc-arm-none-eabi/bin/arm-none-eabi-gcc -I/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/../../NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include -isystem /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include -isystem /data/xilinx/Vitis/2023.2/gnu/aarch32/lin/gcc-arm-none-eabi/x86_64-oesdk-linux/usr/lib/arm-xilinx-eabi/gcc/arm-xilinx-eabi/12.2.0/include -isystem /data/xilinx/Vitis/2023.2/gnu/aarch32/lin/gcc-arm-none-eabi/x86_64-oesdk-linux/usr/lib/arm-xilinx-eabi/gcc/arm-xilinx-eabi/12.2.0/include-fixed -isystem /data/xilinx/Vitis/2023.2/gnu/aarch32/lin/gcc-arm-none-eabi/aarch32-xilinx-eabi/usr/include -O2 -DSDT -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -MMD -MP -specs=/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/Xilinx.spec -I/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include -Wall -Wextra -O0 -g3 -U__clang__ -o CMakeFiles/NewCalBoard_APP.elf.dir/SPI_Driv.c.obj -c /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/SPI_Driv.c",
"file": "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/SPI_Driv.c"
},
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2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/crc16.c
+57
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@@ -0,0 +1,57 @@
/*
* crc16.c
*
* Created on: 2022年2月24日
* Author: Administrator
*/
#include "crc16.h"
const unsigned int crc_table[256] = {
0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
};
unsigned short do_crc_table(unsigned char* ptr, int len)
{
unsigned short crc = 0x0000;
while (len--)
{
crc = (crc >> 8) ^ crc_table[(crc ^ *ptr++) & 0xff];
}
return crc;
}
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/crc16.h
+13
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/*
* crc16.h
*
* Created on: 2022年2月24日
* Author: Administrator
*/
#ifndef SRC_CRC16_H_
#define SRC_CRC16_H_
unsigned short do_crc_table(unsigned char* ptr, int len);
#endif /* SRC_CRC16_H_ */
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/dna_read.c
+30
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@@ -0,0 +1,30 @@
/*
* dna_read.c
*
* Created on: 2023年6月27日
* Author: dell
*/
#include "dna_read.h"
#include <unistd.h>
#include "xil_io.h"
#include "xparameters.h"
#define DNA_ADDR XPAR_MYDNA_READ_V1_0_0_BASEADDR
void dna_port_read(char* read_data) //addr_change, because the board is 88d_a.
{
unsigned read_data_mem[2] = {0};
Xil_Out32(DNA_ADDR,0x01);
usleep(20);
read_data_mem[0] = Xil_In32(DNA_ADDR+4);
read_data_mem[1] = Xil_In32(DNA_ADDR+8);
for(int i = 0; i < 8; i++)
{
*(read_data+i) = (u8)(read_data_mem[i/4]>> (24 - (8*(i%4))));
}
}
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/dna_read.h
+14
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@@ -0,0 +1,14 @@
/*
* dna_read.h
*
* Created on: 2023年6月27日
* Author: dell
*/
#ifndef SRC_DNA_READ_H_
#define SRC_DNA_READ_H_
void dna_port_read(char* read_data); //addr_change, because the board is 88d_a.
#endif /* SRC_DNA_READ_H_ */
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/echo.c
+237
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/*
* Copyright (C) 2009 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
#include <stdio.h>
#include <string.h>
#include "dna_read.h"
#include "crc16.h"
#include "GPIO_Driv.h"
#include "SPI_Driv.h"
#include "cal_meas.h"
#include "lwip/err.h"
#include "lwip/tcp.h"
#if defined (__arm__) || defined (__aarch64__)
#include "xil_printf.h"
#endif
char *recv_data;
char dna_data[10];
unsigned short recv_len;
unsigned read_dat = 0;
char dat_0[20] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
unsigned crc_read_dat = 0;
char crc_alg_dat[2] = {0,0};
char send_data_cpld1[2] = {0xAA,0x56};
int transfer_data() {
return 0;
}
void print_app_header()
{
#if (LWIP_IPV6==0)
xil_printf("\n\r\n\r-----lwIP TCP echo server ------\n\r");
#else
xil_printf("\n\r\n\r-----lwIPv6 TCP echo server ------\n\r");
#endif
xil_printf("TCP packets sent to port 6001 will be echoed back\n\r");
}
err_t recv_callback(void *arg, struct tcp_pcb *tpcb,
struct pbuf *p, err_t err)
{
/* do not read the packet if we are not in ESTABLISHED state */
if (!p) {
tcp_close(tpcb);
tcp_recv(tpcb, NULL);
return ERR_OK;
}
/* indicate that the packet has been received */
tcp_recved(tpcb, p->len);
/* echo back the payload */
/* in this case, we assume that the payload is < TCP_SND_BUF */
if (tcp_sndbuf(tpcb) > p->len) {
recv_len = p->len;
recv_data = (char*)malloc(sizeof(char)*recv_len);
memcpy(recv_data,p->payload,recv_len);
if(recv_data[6] == 0x0E)
{
crc_read_dat = do_crc_table(recv_data+6, recv_len-8);
crc_alg_dat[0] = (u8)crc_read_dat;
crc_alg_dat[1] = (u8)(crc_read_dat>>8);
dat_0[0]= 0x00;
switch(recv_data[7])
{
case 0xA2://SLOT
{
dat_0[1]= 0x06;
dat_0[2]= recv_data[2];
dat_0[3]= recv_data[3];
dat_0[4]= recv_data[4];
dat_0[5]= recv_data[5];
dat_0[6]= recv_data[6];
dat_0[7]= recv_data[7];
if(recv_data[15]==crc_alg_dat[1]&&recv_data[16]==crc_alg_dat[0])
{
dat_0[8]= 0x01;
dat_0[9]= 0x01;
}
else
{
dat_0[8]= 0xff;
dat_0[9]= 0xff;
}
dat_0[10]= recv_data[15];
dat_0[11]= recv_data[16];
char slot_start[7] = {recv_data[8],recv_data[9],recv_data[10],recv_data[11],recv_data[12],recv_data[13],recv_data[14]};
//xil_printf("slot_start[0]:%x, slot_start[1]:%x,slot_start[2]:%x,slot_start[3]:%x,slot_start[4]:%x,slot_start[5]:%x,slot_start[6]:%x\n\r", slot_start[0],slot_start[1],slot_start[2],slot_start[3],slot_start[4],slot_start[5],slot_start[6]);
//rst_CPLD(CPLD_U1,4);
//rst_CPLD(CPLD_U2,4);
//rst_CPLD(CPLD_U3,4);
sw_config(slot_start);
tcp_write(tpcb, dat_0, 12, 1);
break;
}
case 0xA3://dna_port_read
{
dna_port_read(dna_data);
dat_0[1]=0x0e;
dat_0[2]=recv_data[2];
dat_0[3]=recv_data[3];
dat_0[4]=recv_data[4];
dat_0[5]=recv_data[5];
dat_0[6]=recv_data[6];
dat_0[7]=recv_data[7];
if(recv_data[8]==crc_alg_dat[1]&&recv_data[9]==crc_alg_dat[0])
{
dat_0[8]= 0x01;
dat_0[9]= 0x01;
}
else
{
dat_0[8]= 0xff;
dat_0[9]= 0xff;
}
dat_0[10]= dna_data[0];
dat_0[11]= dna_data[1];
dat_0[12]= dna_data[2];
dat_0[13]= dna_data[3];
dat_0[14]= dna_data[4];
dat_0[15]= dna_data[5];
dat_0[16]= dna_data[6];
dat_0[17]= dna_data[7];
dat_0[18]= recv_data[8];
dat_0[19]= recv_data[9];
tcp_write(tpcb, dat_0, 20, 1);
break;
}
}
}
} else
xil_printf("no space in tcp_sndbuf\n\r");
/* free the received pbuf */
pbuf_free(p);
return ERR_OK;
}
err_t accept_callback(void *arg, struct tcp_pcb *newpcb, err_t err)
{
static int connection = 1;
/* set the receive callback for this connection */
tcp_recv(newpcb, recv_callback);
/* just use an integer number indicating the connection id as the
callback argument */
tcp_arg(newpcb, (void*)(UINTPTR)connection);
/* increment for subsequent accepted connections */
connection++;
return ERR_OK;
}
int start_application()
{
struct tcp_pcb *pcb;
err_t err;
unsigned port = 200;
/* create new TCP PCB structure */
pcb = tcp_new_ip_type(IPADDR_TYPE_ANY);
if (!pcb) {
xil_printf("Error creating PCB. Out of Memory\n\r");
return -1;
}
/* bind to specified @port */
err = tcp_bind(pcb, IP_ANY_TYPE, port);
if (err != ERR_OK) {
xil_printf("Unable to bind to port %d: err = %d\n\r", port, err);
return -2;
}
/* we do not need any arguments to callback functions */
tcp_arg(pcb, NULL);
/* listen for connections */
pcb = tcp_listen(pcb);
if (!pcb) {
xil_printf("Out of memory while tcp_listen\n\r");
return -3;
}
/* specify callback to use for incoming connections */
tcp_accept(pcb, accept_callback);
xil_printf("TCP echo server started @ port %d\n\r", port);
return 0;
}
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/i2c_access.c
+420
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@@ -0,0 +1,420 @@
/*
* Copyright (C) 2013 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
/*****************************************************************************/
/**
* @file i2c_lib.c
*
* This file contains library functions to initialize, control and access
* IIC devices.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 1.0 srt 10/19/13 Initial Version
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#if defined (__arm__) && !defined (ARMR5)
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || \
XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
#include "xil_exception.h"
#include "xil_printf.h"
#include "xiicps.h"
#include "sleep.h"
#include "xscugic.h"
/************************** Constant Definitions *****************************/
#define IIC_DEVICE_ID XPAR_XIICPS_0_DEVICE_ID
#define XIIC XIicPs
#define XIICCFG XIicPs_Config
#define I2cSetStatusHandler XIicPs_SetStatusHandler
#define I2cLookupConfig XIicPs_LookupConfig
#define I2cCfgInitialize XIicPs_CfgInitialize
#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
#define IIC_INTR_ID XPAR_XIICPS_0_INTR
#define INTC_HANDLER XScuGic_InterruptHandler
#define IIC_HANDLER XIicPs_IntrHandler
#define INTC XScuGic
#define IIC_SCLK_RATE 100000
/**************************** Type Definitions *******************************/
typedef struct {
XIIC I2cInstance;
INTC IntcInstance;
volatile u8 TransmitComplete; /* Flag to check completion of Transmission */
volatile u8 ReceiveComplete; /* Flag to check completion of Reception */
volatile u32 TotalErrorCount;
} XIIC_LIB;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
int I2cPhyWrite(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 Data, u16 SlaveAddr);
int I2cPhyRead(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 *Data, u16 SlaveAddr);
int I2cSetupHardware(XIIC_LIB *I2cLibPtr);
int I2cWriteData(XIIC_LIB *I2cLibPtr, u8 *WrBuffer, u16 ByteCount, u16 SlaveAddr);
int I2cReadData(XIIC_LIB *I2cLibPtr, u8 *RdBuffer, u16 ByteCount, u16 SlaveAddr);
static int SetupInterruptSystem(XIIC_LIB *I2cLibPtr);
static void StatusHandler(XIIC_LIB *I2cLibPtr, int Event);
/************************* Global Definitions *****************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
* This function configures the IIC hardware.
*
* @param I2cLibPtr contains a pointer to the instance of the IIC library
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int I2cSetupHardware(XIIC_LIB *I2cLibPtr)
{
int Status;
XIICCFG *ConfigPtr;
XIIC *I2cInstancePtr;
I2cInstancePtr = &I2cLibPtr->I2cInstance;
/*
* Initialize the IIC driver so that it is ready to use.
*/
ConfigPtr = I2cLookupConfig(IIC_DEVICE_ID);
if (ConfigPtr == NULL) {
return XST_FAILURE;
}
Status = I2cCfgInitialize(I2cInstancePtr, ConfigPtr,
ConfigPtr->BaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* GPIO Code to pull MUX out of reset.
*/
Xil_Out32(0xe000a204, 0x2000);
Xil_Out32(0xe000a208, 0x2000);
Xil_Out32(0xe000a040, 0x2000);
/*
* Setup the Interrupt System.
*/
Status = SetupInterruptSystem(I2cLibPtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
I2cSetStatusHandler(I2cInstancePtr, I2cLibPtr, (IIC_HANDLER) StatusHandler);
/*
* Set the IIC serial clock rate.
*/
XIicPs_SetSClk(I2cInstancePtr, IIC_SCLK_RATE);
I2cLibPtr->TotalErrorCount = 0;
I2cLibPtr->TransmitComplete = FALSE;
I2cLibPtr->ReceiveComplete = FALSE;
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function writes data to the PHY.
*
* @param I2cLibPtr contains a pointer to the instance of the IIC library
* @param PhyAddr is the address of PHY to be written
* @param Reg is the register address to be written to
* @param Data is the pointer which contains the data to be written
* @param SlaveAddr is the address of the slave we are sending to.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int I2cPhyWrite(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 Data, u16 SlaveAddr)
{
int Status;
u8 WrBuffer[3];
WrBuffer[0] = Reg;
WrBuffer[1] = Data >> 8;
WrBuffer[2] = Data;
Status = I2cWriteData(I2cLibPtr, WrBuffer, 3, SlaveAddr);
if (Status != XST_SUCCESS) {
xil_printf("PhyWrite: Writing data failed\n\r");
return Status;
}
return Status;
}
/*****************************************************************************/
/**
* This function reads data from the PHY.
*
* @param I2cLibPtr contains a pointer to the instance of the IIC library
* @param PhyAddr is the address of PHY to be read from
* @param Reg is the register address to be read from
* @param Data is the pointer which stores the data read
* @param SlaveAddr is the address of the slave we are sending to.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int I2cPhyRead(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 *Data, u16 SlaveAddr)
{
int Status;
u8 WrBuffer[2];
u8 RdBuffer[2];
WrBuffer[0] = Reg;
Status = I2cWriteData(I2cLibPtr, WrBuffer, 1, SlaveAddr);
if (Status != XST_SUCCESS) {
xil_printf("PhyWrite: Writing data failed\n\r");
return Status;
}
Status = I2cReadData(I2cLibPtr, RdBuffer, 2, SlaveAddr);
if (Status != XST_SUCCESS) {
xil_printf("PhyRead: Reading data failed\n\r");
return Status;
}
*Data = RdBuffer[0] << 8 | RdBuffer[1];
return Status;
}
/*****************************************************************************/
/**
* This function writes a buffer of data to the IIC Device.
*
* @param I2cLibPtr contains a pointer to the instance of the IIC library
* @param WrBuffer is the buffer which contains data to be written
* @param ByteCount contains the number of bytes in the buffer to be
* written.
* @param SlaveAddr is the address of the slave we are sending to.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int I2cWriteData(XIIC_LIB *I2cLibPtr, u8 *WrBuffer, u16 ByteCount,
u16 SlaveAddr)
{
XIIC *I2cInstancePtr;
I2cInstancePtr = &I2cLibPtr->I2cInstance;
I2cLibPtr->TransmitComplete = FALSE;
/*
* Send the Data.
*/
XIicPs_MasterSend(I2cInstancePtr, WrBuffer, ByteCount, SlaveAddr);
/*
* Wait for the entire buffer to be sent, letting the interrupt
* processing work in the background, this function may get
* locked up in this loop if the interrupts are not working
* correctly.
*/
while (I2cLibPtr->TransmitComplete == FALSE) {
if (0 != I2cLibPtr->TotalErrorCount) {
xil_printf("I2cWriteData: Failed due to errors\n\r");
return XST_FAILURE;
}
}
/*
* Wait until bus is idle to start another transfer.
*/
while (XIicPs_BusIsBusy(I2cInstancePtr));
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function read data from the IIC Device.
*
* @param I2cLibPtr contains a pointer to the instance of the IIC library
* @param RdBuffer is the buffer into which data read
* @param ByteCount contains the number of bytes in the buffer to be
* written.
* @param SlaveAddr is the address of the slave we are sending to.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int I2cReadData(XIIC_LIB *I2cLibPtr, u8 *RdBuffer, u16 ByteCount, u16 SlaveAddr)
{
XIIC *I2cInstancePtr;
I2cInstancePtr = &I2cLibPtr->I2cInstance;
I2cLibPtr->ReceiveComplete = FALSE;
/*
* Receive the Data.
*/
XIicPs_MasterRecv(I2cInstancePtr, RdBuffer, ByteCount, SlaveAddr);
while (I2cLibPtr->ReceiveComplete == FALSE) {
if (0 != I2cLibPtr->TotalErrorCount) {
xil_printf("I2cReadData: Failed due to errors %d\n\r",
I2cLibPtr->TotalErrorCount);
return XST_FAILURE;
}
}
/*
* Wait until bus is idle to start another transfer.
*/
while (XIicPs_BusIsBusy(I2cInstancePtr))
;
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function setups the interrupt system so interrupts can occur for the
* IIC device. The function is application-specific since the actual system may
* or may not have an interrupt controller. The IIC device could be directly
* connected to a processor without an interrupt controller. The user should
* modify this function to fit the application.
*
* @param IicInstPtr contains a pointer to the instance of the IIC device
* which is going to be connected to the interrupt controller.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
* @note None.
*
******************************************************************************/
static int SetupInterruptSystem(XIIC_LIB *I2cLibPtr)
{
int Status;
XIIC *I2cInstancePtr;
INTC *IntcPtr;
I2cInstancePtr = &I2cLibPtr->I2cInstance;
IntcPtr = &I2cLibPtr->IntcInstance;
XScuGic_Config *IntcConfig;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcPtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(IntcPtr, IIC_INTR_ID, 0xA0, 0x3);
/*
* Connect the interrupt handler that will be called when an
* interrupt occurs for the device.
*/
Status = XScuGic_Connect(IntcPtr, IIC_INTR_ID,
(Xil_InterruptHandler) XIicPs_MasterInterruptHandler,
I2cInstancePtr);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Enable the interrupt for the IIC device.
*/
XScuGic_Enable(IntcPtr, IIC_INTR_ID);
/*
* Initialize the exception table and register the interrupt
* controller handler with the exception table
*/
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler) INTC_HANDLER, IntcPtr);
/* Enable non-critical exceptions */Xil_ExceptionEnable();
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This Status handler is called asynchronously from an interrupt
* context and indicates the events that have occurred.
*
* @param InstancePtr is a pointer to the IIC driver instance for which
* the handler is being called for.
* @param Event indicates the condition that has occurred.
*
* @return None.
*
* @note None.
*
******************************************************************************/
static void StatusHandler(XIIC_LIB *I2cLibPtr, int Event)
{
/*
* All of the data transfer has been finished.
*/
if (0 != (Event & XIICPS_EVENT_COMPLETE_RECV)) {
I2cLibPtr->ReceiveComplete = TRUE;
} else if (0 != (Event & XIICPS_EVENT_COMPLETE_SEND)) {
I2cLibPtr->TransmitComplete = TRUE;
} else if (0 == (Event & XIICPS_EVENT_SLAVE_RDY)) {
/*
* If it is other interrupt but not slave ready interrupt, it is
* an error.
* Data was received with an error.
*/
I2cLibPtr->TotalErrorCount++;
}
}
#endif
#endif
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/iic_phyreset.c
+117
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@@ -0,0 +1,117 @@
/*
* Copyright (C) 2016 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
#include <stdio.h>
#include "xparameters.h"
#if defined (__arm__) || defined(__aarch64__)
#include "xil_printf.h"
#endif
#ifdef XPS_BOARD_ZCU102
#ifdef XPAR_XIICPS_0_DEVICE_ID
#include "xiicps.h"
#define BUF_LEN 10U
#define IOEXPANDER1_ADDR 0x20U
#define IIC_SCLK_RATE_IOEXP 400000
#define CMD_CFG_0_REG 0x06U
#define CMD_OUTPUT_0_REG 0x02U
#define DATA_OUTPUT 0x0U
#define DATA_COMMON_CFG 0xE0U
#define DATA_GT_0000_CFG 0x00U
XIicPs I2c0InstancePtr;
int IicPhyReset(void)
{
u8 WriteBuffer[BUF_LEN] = {0};
XIicPs_Config *I2c0CfgPtr;
int Status = XST_SUCCESS;
/* Initialize the IIC0 driver so that it is ready to use */
I2c0CfgPtr = XIicPs_LookupConfig(XPAR_XIICPS_0_DEVICE_ID);
if (I2c0CfgPtr == NULL) {
Status = XST_FAILURE;
return Status;
}
Status = XIicPs_CfgInitialize(&I2c0InstancePtr, I2c0CfgPtr,
I2c0CfgPtr->BaseAddress);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
return Status;
}
/* Set the IIC serial clock rate */
XIicPs_SetSClk(&I2c0InstancePtr, IIC_SCLK_RATE_IOEXP);
/* Configure I/O pins as Output */
WriteBuffer[0] = CMD_CFG_0_REG;
WriteBuffer[1] = DATA_OUTPUT;
Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
WriteBuffer, 2, IOEXPANDER1_ADDR);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
return Status;
}
/* Wait until bus is idle to start another transfer */
while (XIicPs_BusIsBusy(&I2c0InstancePtr));
/*
* Deasserting I2C_MUX_RESETB
* And GEM3 Resetb
* Selecting lanes based on configuration
*/
WriteBuffer[0] = CMD_OUTPUT_0_REG;
/* gt0000 or no GT configuration */
WriteBuffer[1] = DATA_COMMON_CFG | DATA_GT_0000_CFG;
/* Send the Data */
Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
WriteBuffer, 2, IOEXPANDER1_ADDR);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
return Status;
}
/* Wait until bus is idle */
while (XIicPs_BusIsBusy(&I2c0InstancePtr));
xil_printf("IIC PHY reset on ZCU102 successful \n\r");
return XST_SUCCESS;
}
#endif
#endif
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/lscript.ld
+286
View File
@@ -0,0 +1,286 @@
/******************************************************************************
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
MEMORY
{
ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x3ff00000
ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
ps7_ram_1 : ORIGIN = 0xffff0000, LENGTH = 0xfe00
}
/* Specify the default entry point to the program */
ENTRY(_vector_table)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
.text : {
KEEP (*(.vectors))
*(.boot)
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
*(.plt)
*(.gnu_warning)
*(.gcc_execpt_table)
*(.glue_7)
*(.glue_7t)
*(.vfp11_veneer)
*(.ARM.extab)
*(.gnu.linkonce.armextab.*)
*(.note.gnu.build-id)
} > ps7_ddr_0
.init : {
KEEP (*(.init))
} > ps7_ddr_0
.fini : {
KEEP (*(.fini))
} > ps7_ddr_0
.rodata : {
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > ps7_ddr_0
.rodata1 : {
__rodata1_start = .;
*(.rodata1)
*(.rodata1.*)
__rodata1_end = .;
} > ps7_ddr_0
.sdata2 : {
__sdata2_start = .;
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
__sdata2_end = .;
} > ps7_ddr_0
.sbss2 : {
__sbss2_start = .;
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
} > ps7_ddr_0
.data : {
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.jcr)
*(.got)
*(.got.plt)
__data_end = .;
} > ps7_ddr_0
.data1 : {
__data1_start = .;
*(.data1)
*(.data1.*)
__data1_end = .;
} > ps7_ddr_0
.got : {
*(.got)
} > ps7_ddr_0
.ctors : {
__CTOR_LIST__ = .;
___CTORS_LIST___ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > ps7_ddr_0
.dtors : {
__DTOR_LIST__ = .;
___DTORS_LIST___ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
___DTORS_END___ = .;
} > ps7_ddr_0
.fixup : {
__fixup_start = .;
*(.fixup)
__fixup_end = .;
} > ps7_ddr_0
.eh_frame : {
*(.eh_frame)
} > ps7_ddr_0
.eh_framehdr : {
__eh_framehdr_start = .;
*(.eh_framehdr)
__eh_framehdr_end = .;
} > ps7_ddr_0
.gcc_except_table : {
*(.gcc_except_table)
} > ps7_ddr_0
.mmu_tbl (ALIGN(16384)) : {
__mmu_tbl_start = .;
*(.mmu_tbl)
__mmu_tbl_end = .;
} > ps7_ddr_0
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidix.*.*)
__exidx_end = .;
} > ps7_ddr_0
.preinit_array : {
__preinit_array_start = .;
KEEP (*(SORT(.preinit_array.*)))
KEEP (*(.preinit_array))
__preinit_array_end = .;
} > ps7_ddr_0
.init_array : {
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
} > ps7_ddr_0
.fini_array : {
__fini_array_start = .;
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
} > ps7_ddr_0
.drvcfg_sec : {
. = ALIGN(8);
__drvcfgsecdata_start = .;
KEEP (*(.drvcfg_sec))
__drvcfgsecdata_end = .;
__drvcfgsecdata_size = __drvcfgsecdata_end - __drvcfgsecdata_start;
} > ps7_ddr_0
.ARM.attributes : {
__ARM.attributes_start = .;
*(.ARM.attributes)
__ARM.attributes_end = .;
} > ps7_ddr_0
.sdata : {
__sdata_start = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > ps7_ddr_0
.sbss (NOLOAD) : {
__sbss_start = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
__sbss_end = .;
} > ps7_ddr_0
.tdata : {
__tdata_start = .;
*(.tdata)
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > ps7_ddr_0
.tbss : {
__tbss_start = .;
*(.tbss)
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > ps7_ddr_0
.bss (NOLOAD) : {
__bss_start = .;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
__bss_end = .;
} > ps7_ddr_0
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
/* Generate Stack and Heap definitions */
.heap (NOLOAD) : {
. = ALIGN(16);
_heap = .;
HeapBase = .;
_heap_start = .;
. += _HEAP_SIZE;
_heap_end = .;
HeapLimit = .;
} > ps7_ddr_0
.stack (NOLOAD) : {
. = ALIGN(16);
_stack_end = .;
. += _STACK_SIZE;
. = ALIGN(16);
_stack = .;
__stack = _stack;
. = ALIGN(16);
_irq_stack_end = .;
. += _IRQ_STACK_SIZE;
. = ALIGN(16);
__irq_stack = .;
_supervisor_stack_end = .;
. += _SUPERVISOR_STACK_SIZE;
. = ALIGN(16);
__supervisor_stack = .;
_abort_stack_end = .;
. += _ABORT_STACK_SIZE;
. = ALIGN(16);
__abort_stack = .;
_fiq_stack_end = .;
. += _FIQ_STACK_SIZE;
. = ALIGN(16);
__fiq_stack = .;
_undef_stack_end = .;
. += _UNDEF_STACK_SIZE;
. = ALIGN(16);
__undef_stack = .;
} > ps7_ddr_0
end = .;
}
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/main.c
+249
View File
@@ -0,0 +1,249 @@
/*
* Copyright (C) 2009 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
#include <stdio.h>
#include "xparameters.h"
#include "netif/xadapter.h"
#include "platform.h"
#include "platform_config.h"
#if defined (__arm__) || defined(__aarch64__)
#include "xil_printf.h"
#endif
#include "lwip/tcp.h"
extern void tcp_tmr(void); /* declared in tcp_priv.h, not in public tcp.h */
#include "xil_cache.h"
#include "GPIO_Driv.h"
#include "SPI_Driv.h"
#include "cal_meas.h"
#if LWIP_IPV6==1
#include "lwip/ip.h"
#else
#if LWIP_DHCP==1
#include "lwip/dhcp.h"
#endif
#endif
/* defined by each RAW mode application */
void print_app_header();
int start_application();
int transfer_data();
/* missing declaration in lwIP */
void lwip_init();
#if LWIP_IPV6==0
#if LWIP_DHCP==1
extern volatile int dhcp_timoutcntr;
err_t dhcp_start(struct netif *netif);
#endif
#endif
static struct netif server_netif;
struct netif *echo_netif;
#if LWIP_IPV6==1
void print_ip6(char *msg, ip_addr_t *ip)
{
print(msg);
xil_printf(" %x:%x:%x:%x:%x:%x:%x:%x\n\r",
IP6_ADDR_BLOCK1(&ip->u_addr.ip6),
IP6_ADDR_BLOCK2(&ip->u_addr.ip6),
IP6_ADDR_BLOCK3(&ip->u_addr.ip6),
IP6_ADDR_BLOCK4(&ip->u_addr.ip6),
IP6_ADDR_BLOCK5(&ip->u_addr.ip6),
IP6_ADDR_BLOCK6(&ip->u_addr.ip6),
IP6_ADDR_BLOCK7(&ip->u_addr.ip6),
IP6_ADDR_BLOCK8(&ip->u_addr.ip6));
}
#else
void
print_ip(char *msg, ip_addr_t *ip)
{
print(msg);
xil_printf("%d.%d.%d.%d\n\r", ip4_addr1(ip), ip4_addr2(ip),
ip4_addr3(ip), ip4_addr4(ip));
}
void
print_ip_settings(ip_addr_t *ip, ip_addr_t *mask, ip_addr_t *gw)
{
print_ip("Board IP: ", ip);
print_ip("Netmask : ", mask);
print_ip("Gateway : ", gw);
}
#endif
#if defined (__arm__) && !defined (ARMR5)
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
int ProgramSi5324(void);
int ProgramSfpPhy(void);
#endif
#endif
#ifdef XPS_BOARD_ZCU102
#ifdef XPAR_XIICPS_0_DEVICE_ID
int IicPhyReset(void);
#endif
#endif
int main()
{
#if LWIP_IPV6==0
ip_addr_t ipaddr, netmask, gw;
#endif
/* the mac address of the board. this should be unique per board */
unsigned char mac_ethernet_address[] =
{ 0x00, 0x0a, 0x35, 0x00, 0x01, 0x01 };
echo_netif = &server_netif;
#if defined (__arm__) && !defined (ARMR5)
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
ProgramSi5324();
ProgramSfpPhy();
#endif
#endif
/* Define this board specific macro in order perform PHY reset on ZCU102 */
#ifdef XPS_BOARD_ZCU102
if(IicPhyReset()) {
xil_printf("Error performing PHY reset \n\r");
return -1;
}
#endif
init_platform();
#if LWIP_IPV6==0
#if LWIP_DHCP==1
ipaddr.addr = 0;
gw.addr = 0;
netmask.addr = 0;
#else
/* initialize IP addresses to be used */
IP4_ADDR(&ipaddr, 192, 168, 100, 110);
IP4_ADDR(&netmask, 255, 255, 255, 0);
IP4_ADDR(&gw, 192, 168, 100, 1);
#endif
#endif
print_app_header();
lwip_init();
#if (LWIP_IPV6 == 0)
/* Add network interface to the netif_list, and set it as default */
if (!xemac_add(echo_netif, &ipaddr, &netmask,
&gw, mac_ethernet_address,
PLATFORM_EMAC_BASEADDR)) {
xil_printf("Error adding N/W interface\n\r");
return -1;
}
#else
/* Add network interface to the netif_list, and set it as default */
if (!xemac_add(echo_netif, NULL, NULL, NULL, mac_ethernet_address,
PLATFORM_EMAC_BASEADDR)) {
xil_printf("Error adding N/W interface\n\r");
return -1;
}
echo_netif->ip6_autoconfig_enabled = 1;
netif_create_ip6_linklocal_address(echo_netif, 1);
netif_ip6_addr_set_state(echo_netif, 0, IP6_ADDR_VALID);
print_ip6("\n\rBoard IPv6 address ", &echo_netif->ip6_addr[0].u_addr.ip6);
#endif
netif_set_default(echo_netif);
/* now enable interrupts */
//platform_enable_interrupts();
/* specify that the network if is up */
netif_set_up(echo_netif);
#if (LWIP_IPV6 == 0)
#if (LWIP_DHCP==1)
/* Create a new DHCP client for this interface.
* Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at
* the predefined regular intervals after starting the client.
*/
dhcp_start(echo_netif);
dhcp_timoutcntr = 24;
while(((echo_netif->ip_addr.addr) == 0) && (dhcp_timoutcntr > 0))
xemacif_input(echo_netif);
if (dhcp_timoutcntr <= 0) {
if ((echo_netif->ip_addr.addr) == 0) {
xil_printf("DHCP Timeout\r\n");
xil_printf("Configuring default IP of 192.168.100.110\r\n");
IP4_ADDR(&(echo_netif->ip_addr), 192, 168, 100, 110);
IP4_ADDR(&(echo_netif->netmask), 255, 255, 255, 0);
IP4_ADDR(&(echo_netif->gw), 192, 168, 100, 1);
}
}
ipaddr.addr = echo_netif->ip_addr.addr;
gw.addr = echo_netif->gw.addr;
netmask.addr = echo_netif->netmask.addr;
#endif
print_ip_settings(&ipaddr, &netmask, &gw);
#endif
EMIO_config();
interface_initial(CPLD_U1);
interface_initial(CPLD_U2);
interface_initial(CPLD_U3);
rst_CPLD(CPLD_U1,4);
rst_CPLD(CPLD_U2,4);
rst_CPLD(CPLD_U3,4);
/* start the application (web server, rxtest, txtest, etc..) */
start_application();
/* receive and process packets */
while (1) {
tcp_tmr();
xemacif_input(echo_netif);
transfer_data();
}
/* never reached */
cleanup_platform();
return 0;
}
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/platform.c
+86
View File
@@ -0,0 +1,86 @@
/******************************************************************************
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xparameters.h"
#include "xil_cache.h"
#ifndef SDT
#include "platform_config.h"
#endif
/*
* Uncomment one of the following two lines, depending on the target,
* if ps7/psu init source files are added in the source directory for
* compiling example outside of SDK.
*/
/*#include "ps7_init.h"*/
/*#include "psu_init.h"*/
#ifdef STDOUT_IS_16550
#include "xuartns550_l.h"
#define UART_BAUD 9600
#endif
void
enable_caches()
{
#ifdef __PPC__
Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
#elif __MICROBLAZE__
#ifdef XPAR_MICROBLAZE_USE_ICACHE
Xil_ICacheEnable();
#endif
#ifdef XPAR_MICROBLAZE_USE_DCACHE
Xil_DCacheEnable();
#endif
#endif
}
void
disable_caches()
{
#ifdef __MICROBLAZE__
#ifdef XPAR_MICROBLAZE_USE_DCACHE
Xil_DCacheDisable();
#endif
#ifdef XPAR_MICROBLAZE_USE_ICACHE
Xil_ICacheDisable();
#endif
#endif
}
void
init_uart()
{
#ifdef STDOUT_IS_16550
XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
#endif
/* Bootrom/BSP configures PS7/PSU UART to 115200 bps */
}
void
init_platform()
{
/*
* If you want to run this example outside of SDK,
* uncomment one of the following two lines and also #include "ps7_init.h"
* or #include "ps7_init.h" at the top, depending on the target.
* Make sure that the ps7/psu_init.c and ps7/psu_init.h files are included
* along with this example source files for compilation.
*/
/* ps7_init();*/
/* psu_init();*/
enable_caches();
init_uart();
}
void
cleanup_platform()
{
disable_caches();
}
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/platform.h
+16
View File
@@ -0,0 +1,16 @@
/******************************************************************************
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef __PLATFORM_H_
#define __PLATFORM_H_
#ifndef SDT
#include "platform_config.h"
#endif
void init_platform();
void cleanup_platform();
#endif
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/platform_config.h
+10
View File
@@ -0,0 +1,10 @@
#ifndef __PLATFORM_CONFIG_H_
#define __PLATFORM_CONFIG_H_
#define PLATFORM_EMAC_BASEADDR XPAR_XEMACPS_0_BASEADDR
#define PLATFORM_ZYNQ
#endif
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/sfp.c
+192
View File
@@ -0,0 +1,192 @@
/*
* Copyright (C) 2013 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
/*****************************************************************************/
/**
* @file sfp.c
*
* This file programs sfp phy chip.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 1.0 srt 10/19/13 Initial Version
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#if defined (__arm__) && !defined (ARMR5)
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || \
XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
#include "xil_printf.h"
#include "xiicps.h"
#include "sleep.h"
#include "xscugic.h"
/************************** Constant Definitions *****************************/
#define IIC_SLAVE_ADDR 0x56
#define IIC_MUX_ADDRESS 0x74
#define IIC_CHANNEL_ADDRESS 0x01
#define XIIC XIicPs
#define INTC XScuGic
/**************************** Type Definitions *******************************/
typedef struct {
XIIC I2cInstance;
INTC IntcInstance;
volatile u8 TransmitComplete; /* Flag to check completion of Transmission */
volatile u8 ReceiveComplete; /* Flag to check completion of Reception */
volatile u32 TotalErrorCount;
} XIIC_LIB;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
int I2cWriteData(XIIC_LIB *I2cLibPtr, u8 *WrBuffer, u16 ByteCount, u16 SlaveAddr);
int I2cReadData(XIIC_LIB *I2cLibPtr, u8 *RdBuffer, u16 ByteCount, u16 SlaveAddr);
int I2cPhyWrite(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 Data, u16 SlaveAddr);
int I2cPhyRead(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 *Data, u16 SlaveAddr);
int I2cSetupHardware(XIIC_LIB *I2cLibPtr);
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
* This function initializes ZC706 MUX.
*
* @param I2cLibPtr contains a pointer to the instance of the IIC library
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int ZC706MuxInit(XIIC_LIB *I2cLibInstancePtr)
{
u8 WrBuffer;
int Status;
WrBuffer = IIC_CHANNEL_ADDRESS;
Status = I2cWriteData(I2cLibInstancePtr, &WrBuffer, 1, IIC_MUX_ADDRESS);
if (Status != XST_SUCCESS) {
xil_printf("SFP_PHY: Writing failed\n\r");
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function program SFP PHY.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int ProgramSfpPhy(void)
{
XIIC_LIB I2cLibInstance;
int Status;
u8 WrBuffer[2];
u16 phy_read_val;
Status = I2cSetupHardware(&I2cLibInstance);
if (Status != XST_SUCCESS) {
xil_printf("Fail!!!\n\r");
xil_printf("SFP_PHY: Configuring HW failed\n\r");
return XST_FAILURE;
}
Status = ZC706MuxInit(&I2cLibInstance);
if (Status != XST_SUCCESS) {
xil_printf("SFP_PHY: Mux Init failed\n\r");
return XST_FAILURE;
}
WrBuffer[0] = 0;
Status = I2cWriteData(&I2cLibInstance, WrBuffer, 1, IIC_SLAVE_ADDR);
if (Status != XST_SUCCESS) {
xil_printf("SFP_PHY: Writing failed\n\r");
return XST_FAILURE;
}
#if XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
/* Enabling 1000BASEX */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x1B, 0x9088, IIC_SLAVE_ADDR);
#else
/* Enabling SGMII */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x1B, 0x9084, IIC_SLAVE_ADDR);
#endif
/* Apply Soft Reset */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
/* Enable 1000BaseT Full Duplex capabilities */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x09, 0x0E00, IIC_SLAVE_ADDR);
/* Apply Soft Reset */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
/* Advertise 10/100 Capabilities else change the capabilities */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x04, 0x0141, IIC_SLAVE_ADDR);
/* Apply Soft Reset */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
/* Apply Soft Reset */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x10, 0xF079, IIC_SLAVE_ADDR);
/* Apply Soft Reset */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0001, IIC_SLAVE_ADDR);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9340, IIC_SLAVE_ADDR);
usleep(1);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0, IIC_SLAVE_ADDR);
phy_read_val = 0x0;
while((phy_read_val & 0x0C00) != 0x0C00) {
I2cPhyRead(&I2cLibInstance, IIC_SLAVE_ADDR, 0x11, &phy_read_val, IIC_SLAVE_ADDR);
}
usleep(1);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0, IIC_SLAVE_ADDR);
I2cPhyRead(&I2cLibInstance, IIC_SLAVE_ADDR, 0x11, &phy_read_val, IIC_SLAVE_ADDR);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0001, IIC_SLAVE_ADDR);
/* configure speed */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x14, 0x0c61, IIC_SLAVE_ADDR);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9340, IIC_SLAVE_ADDR);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0, IIC_SLAVE_ADDR);
return XST_SUCCESS;
}
#endif
#endif
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/si5324.c
+187
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/*
* Copyright (C) 2013 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
/*****************************************************************************/
/**
* @file si5324.c
*
* This file programs si5324 chip which generates clock for the peripherals.
*
* Please refer to Si5324 Datasheet for more information
* http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5324.pdf
*
* Tested on Zynq ZC706 platform
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 1.0 srt 10/19/13 Initial Version
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#if defined (__arm__) && !defined (ARMR5)
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || \
XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
#include "xil_printf.h"
#include "xiicps.h"
#include "sleep.h"
#include "xscugic.h"
/************************** Constant Definitions *****************************/
#define IIC_SLAVE_ADDR 0x68
#define IIC_MUX_ADDRESS 0x74
#define IIC_CHANNEL_ADDRESS 0x10
#define XIIC XIicPs
#define INTC XScuGic
/**************************** Type Definitions *******************************/
typedef struct SI324Info
{
u32 RegIndex; /* Register Number */
u32 Value; /* Value to be Written */
} SI324Info;
typedef struct {
XIIC I2cInstance;
INTC IntcInstance;
volatile u8 TransmitComplete; /* Flag to check completion of Transmission */
volatile u8 ReceiveComplete; /* Flag to check completion of Reception */
volatile u32 TotalErrorCount;
} XIIC_LIB;
/************************** Function Prototypes *****************************/
int I2cWriteData(XIIC_LIB *I2cLibPtr, u8 *WrBuffer, u16 ByteCount, u16 SlaveAddr);
int I2cReadData(XIIC_LIB *I2cLibPtr, u8 *RdBuffer, u16 ByteCount, u16 SlaveAddr);
int I2cPhyWrite(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 Data, u16 SlaveAddr);
int I2cPhyRead(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 *Data, u16 SlaveAddr);
int I2cSetupHardware(XIIC_LIB *I2cLibPtr);
/************************* Global Definitions *****************************/
/*
* These configuration values generates 125MHz clock
* For more information please refer to Si5324 Datasheet.
*/
SI324Info InitTable[] = {
{ 0, 0x54}, /* Register 0 */
{ 1, 0xE4}, /* Register 1 */
{ 2, 0x12}, /* Register 2 */
{ 3, 0x15}, /* Register 3 */
{ 4, 0x92}, /* Register 4 */
{ 5, 0xed}, /* Register 5 */
{ 6, 0x2d}, /* Register 6 */
{ 7, 0x2a}, /* Register 7 */
{ 8, 0x00}, /* Register 8 */
{ 9, 0xc0}, /* Register 9 */
{ 10, 0x08}, /* Register 10 */
{ 11, 0x40}, /* Register 11 */
{ 19, 0x29}, /* Register 19 */
{ 20, 0x3e}, /* Register 20 */
{ 21, 0xff}, /* Register 21 */
{ 22, 0xdf}, /* Register 22 */
{ 23, 0x1f}, /* Register 23 */
{ 24, 0x3f}, /* Register 24 */
{ 25, 0x60}, /* Register 25 */
{ 31, 0x00}, /* Register 31 */
{ 32, 0x00}, /* Register 32 */
{ 33, 0x05}, /* Register 33 */
{ 34, 0x00}, /* Register 34 */
{ 35, 0x00}, /* Register 35 */
{ 36, 0x05}, /* Register 36 */
{ 40, 0xc2}, /* Register 40 */
{ 41, 0x22}, /* Register 41 */
{ 42, 0xdf}, /* Register 42 */
{ 43, 0x00}, /* Register 43 */
{ 44, 0x77}, /* Register 44 */
{ 45, 0x0b}, /* Register 45 */
{ 46, 0x00}, /* Register 46 */
{ 47, 0x77}, /* Register 47 */
{ 48, 0x0b}, /* Register 48 */
{ 55, 0x00}, /* Register 55 */
{131, 0x1f}, /* Register 131 */
{132, 0x02}, /* Register 132 */
{137, 0x01}, /* Register 137 */
{138, 0x0f}, /* Register 138 */
{139, 0xff}, /* Register 139 */
{142, 0x00}, /* Register 142 */
{143, 0x00}, /* Register 143 */
{136, 0x40} /* Register 136 */
};
/************************** Function Definitions *****************************/
int MuxInit(XIIC_LIB *I2cLibInstancePtr)
{
u8 WrBuffer[0];
int Status;
WrBuffer[0] = IIC_CHANNEL_ADDRESS;
Status = I2cWriteData(I2cLibInstancePtr,
WrBuffer, 1, IIC_MUX_ADDRESS);
if (Status != XST_SUCCESS) {
xil_printf("Si5324: Writing failed\n\r");
return XST_FAILURE;
}
return XST_SUCCESS;
}
int ProgramSi5324(void)
{
XIIC_LIB I2cLibInstance;
int Index;
int Status;
u8 WrBuffer[2];
Status = I2cSetupHardware(&I2cLibInstance);
if (Status != XST_SUCCESS) {
xil_printf("Si5324: Configuring HW failed\n\r");
return XST_FAILURE;
}
Status = MuxInit(&I2cLibInstance);
if (Status != XST_SUCCESS) {
xil_printf("Si5324: Mux Init failed\n\r");
return XST_FAILURE;
}
for (Index = 0; Index < sizeof(InitTable)/8; Index++) {
WrBuffer[0] = InitTable[Index].RegIndex;
WrBuffer[1] = InitTable[Index].Value;
Status = I2cWriteData(&I2cLibInstance, WrBuffer, 2, IIC_SLAVE_ADDR);
if (Status != XST_SUCCESS) {
xil_printf("Si5324: Writing failed\n\r");
return XST_FAILURE;
}
}
return XST_SUCCESS;
}
#endif
#endif
2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/vitis-comp.json
+18
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@@ -0,0 +1,18 @@
{
"name": "NewCalBoard_APP",
"type": "HOST",
"platform": "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/NewInstrCalBoard_bsp.xpfm",
"domain": "standalone_ps7_cortexa9_0",
"cpuInstance": "ps7_cortexa9_0",
"cpuType": "cortex-a9",
"os": "standalone",
"configuration": {
"componentType": "HOST",
"hostToolchainConfigurations": []
},
"domainRealName": "standalone_ps7_cortexa9_0",
"applicationFlow": "EMBEDDED",
"previousBuildStatusMap": {
"hw": "ERROR"
}
}
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/.gitignore
+17
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@@ -0,0 +1,17 @@
# Ignore build output directory
/build
# Ignore object files and dependent files
.o
.d
#Ignore logs folder and log files
/logs
.log
#Ignore lock files
.lock
.bin
.pdi
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/NewInstrCalBoard_bsp.xpfm
+10
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@@ -0,0 +1,10 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<sdx:platform xmlns:sdx="http://www.xilinx.com/sdx" sdx:library="sdx" sdx:name="NewInstrCalBoard_bsp" sdx:vendor="xilinx.com" sdx:version="1.0">
<sdx:description/>
<sdx:hardwarePlatforms>
<sdx:hardwarePlatform sdx:name="system_wrapper.xsa" sdx:path="hw"/>
</sdx:hardwarePlatforms>
<sdx:softwarePlatforms>
<sdx:softwarePlatform sdx:name="NewInstrCalBoard_bsp.spfm" sdx:path="sw"/>
</sdx:softwarePlatforms>
</sdx:platform>
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h
+16
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@@ -0,0 +1,16 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright 2019 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
*/
#ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__
#define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__
#define ZYNQMP_DPDMA_VIDEO0 0
#define ZYNQMP_DPDMA_VIDEO1 1
#define ZYNQMP_DPDMA_VIDEO2 2
#define ZYNQMP_DPDMA_GRAPHICS 3
#define ZYNQMP_DPDMA_AUDIO0 4
#define ZYNQMP_DPDMA_AUDIO1 5
#endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/gpio/gpio.h
+42
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@@ -0,0 +1,42 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for most GPIO bindings.
*
* Most GPIO bindings include a flags cell as part of the GPIO specifier.
* In most cases, the format of the flags cell uses the standard values
* defined in this header.
*/
#ifndef _DT_BINDINGS_GPIO_GPIO_H
#define _DT_BINDINGS_GPIO_GPIO_H
/* Bit 0 express polarity */
#define GPIO_ACTIVE_HIGH 0
#define GPIO_ACTIVE_LOW 1
/* Bit 1 express single-endedness */
#define GPIO_PUSH_PULL 0
#define GPIO_SINGLE_ENDED 2
/* Bit 2 express Open drain or open source */
#define GPIO_LINE_OPEN_SOURCE 0
#define GPIO_LINE_OPEN_DRAIN 4
/*
* Open Drain/Collector is the combination of single-ended open drain interface.
* Open Source/Emitter is the combination of single-ended open source interface.
*/
#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)
#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)
/* Bit 3 express GPIO suspend/resume and reset persistence */
#define GPIO_PERSISTENT 0
#define GPIO_TRANSITORY 8
/* Bit 4 express pull up */
#define GPIO_PULL_UP 16
/* Bit 5 express pull down */
#define GPIO_PULL_DOWN 32
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/input/input.h
+802
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@@ -0,0 +1,802 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for most input bindings.
*
* Most input bindings include key code, matrix key code format.
* In most cases, key code and matrix key code format uses
* the standard values/macro defined in this header.
*/
#ifndef _DT_BINDINGS_INPUT_INPUT_H
#define _DT_BINDINGS_INPUT_INPUT_H
/*
* Device properties and quirks
*/
#define INPUT_PROP_POINTER 0x00 /* needs a pointer */
#define INPUT_PROP_DIRECT 0x01 /* direct input devices */
#define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */
#define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */
#define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */
#define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */
#define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */
#define INPUT_PROP_MAX 0x1f
#define INPUT_PROP_CNT (INPUT_PROP_MAX + 1)
/*
* Event types
*/
#define EV_SYN 0x00
#define EV_KEY 0x01
#define EV_REL 0x02
#define EV_ABS 0x03
#define EV_MSC 0x04
#define EV_SW 0x05
#define EV_LED 0x11
#define EV_SND 0x12
#define EV_REP 0x14
#define EV_FF 0x15
#define EV_PWR 0x16
#define EV_FF_STATUS 0x17
#define EV_MAX 0x1f
#define EV_CNT (EV_MAX+1)
/*
* Synchronization events.
*/
#define SYN_REPORT 0
#define SYN_CONFIG 1
#define SYN_MT_REPORT 2
#define SYN_DROPPED 3
#define SYN_MAX 0xf
#define SYN_CNT (SYN_MAX+1)
/*
* Keys and buttons
*
* Most of the keys/buttons are modeled after USB HUT 1.12
* (see http://www.usb.org/developers/hidpage).
* Abbreviations in the comments:
* AC - Application Control
* AL - Application Launch Button
* SC - System Control
*/
#define KEY_RESERVED 0
#define KEY_ESC 1
#define KEY_1 2
#define KEY_2 3
#define KEY_3 4
#define KEY_4 5
#define KEY_5 6
#define KEY_6 7
#define KEY_7 8
#define KEY_8 9
#define KEY_9 10
#define KEY_0 11
#define KEY_MINUS 12
#define KEY_EQUAL 13
#define KEY_BACKSPACE 14
#define KEY_TAB 15
#define KEY_Q 16
#define KEY_W 17
#define KEY_E 18
#define KEY_R 19
#define KEY_T 20
#define KEY_Y 21
#define KEY_U 22
#define KEY_I 23
#define KEY_O 24
#define KEY_P 25
#define KEY_LEFTBRACE 26
#define KEY_RIGHTBRACE 27
#define KEY_ENTER 28
#define KEY_LEFTCTRL 29
#define KEY_A 30
#define KEY_S 31
#define KEY_D 32
#define KEY_F 33
#define KEY_G 34
#define KEY_H 35
#define KEY_J 36
#define KEY_K 37
#define KEY_L 38
#define KEY_SEMICOLON 39
#define KEY_APOSTROPHE 40
#define KEY_GRAVE 41
#define KEY_LEFTSHIFT 42
#define KEY_BACKSLASH 43
#define KEY_Z 44
#define KEY_X 45
#define KEY_C 46
#define KEY_V 47
#define KEY_B 48
#define KEY_N 49
#define KEY_M 50
#define KEY_COMMA 51
#define KEY_DOT 52
#define KEY_SLASH 53
#define KEY_RIGHTSHIFT 54
#define KEY_KPASTERISK 55
#define KEY_LEFTALT 56
#define KEY_SPACE 57
#define KEY_CAPSLOCK 58
#define KEY_F1 59
#define KEY_F2 60
#define KEY_F3 61
#define KEY_F4 62
#define KEY_F5 63
#define KEY_F6 64
#define KEY_F7 65
#define KEY_F8 66
#define KEY_F9 67
#define KEY_F10 68
#define KEY_NUMLOCK 69
#define KEY_SCROLLLOCK 70
#define KEY_KP7 71
#define KEY_KP8 72
#define KEY_KP9 73
#define KEY_KPMINUS 74
#define KEY_KP4 75
#define KEY_KP5 76
#define KEY_KP6 77
#define KEY_KPPLUS 78
#define KEY_KP1 79
#define KEY_KP2 80
#define KEY_KP3 81
#define KEY_KP0 82
#define KEY_KPDOT 83
#define KEY_ZENKAKUHANKAKU 85
#define KEY_102ND 86
#define KEY_F11 87
#define KEY_F12 88
#define KEY_RO 89
#define KEY_KATAKANA 90
#define KEY_HIRAGANA 91
#define KEY_HENKAN 92
#define KEY_KATAKANAHIRAGANA 93
#define KEY_MUHENKAN 94
#define KEY_KPJPCOMMA 95
#define KEY_KPENTER 96
#define KEY_RIGHTCTRL 97
#define KEY_KPSLASH 98
#define KEY_SYSRQ 99
#define KEY_RIGHTALT 100
#define KEY_LINEFEED 101
#define KEY_HOME 102
#define KEY_UP 103
#define KEY_PAGEUP 104
#define KEY_LEFT 105
#define KEY_RIGHT 106
#define KEY_END 107
#define KEY_DOWN 108
#define KEY_PAGEDOWN 109
#define KEY_INSERT 110
#define KEY_DELETE 111
#define KEY_MACRO 112
#define KEY_MUTE 113
#define KEY_VOLUMEDOWN 114
#define KEY_VOLUMEUP 115
#define KEY_POWER 116 /* SC System Power Down */
#define KEY_KPEQUAL 117
#define KEY_KPPLUSMINUS 118
#define KEY_PAUSE 119
#define KEY_SCALE 120 /* AL Compiz Scale (Expose) */
#define KEY_KPCOMMA 121
#define KEY_HANGEUL 122
#define KEY_HANGUEL KEY_HANGEUL
#define KEY_HANJA 123
#define KEY_YEN 124
#define KEY_LEFTMETA 125
#define KEY_RIGHTMETA 126
#define KEY_COMPOSE 127
#define KEY_STOP 128 /* AC Stop */
#define KEY_AGAIN 129
#define KEY_PROPS 130 /* AC Properties */
#define KEY_UNDO 131 /* AC Undo */
#define KEY_FRONT 132
#define KEY_COPY 133 /* AC Copy */
#define KEY_OPEN 134 /* AC Open */
#define KEY_PASTE 135 /* AC Paste */
#define KEY_FIND 136 /* AC Search */
#define KEY_CUT 137 /* AC Cut */
#define KEY_HELP 138 /* AL Integrated Help Center */
#define KEY_MENU 139 /* Menu (show menu) */
#define KEY_CALC 140 /* AL Calculator */
#define KEY_SETUP 141
#define KEY_SLEEP 142 /* SC System Sleep */
#define KEY_WAKEUP 143 /* System Wake Up */
#define KEY_FILE 144 /* AL Local Machine Browser */
#define KEY_SENDFILE 145
#define KEY_DELETEFILE 146
#define KEY_XFER 147
#define KEY_PROG1 148
#define KEY_PROG2 149
#define KEY_WWW 150 /* AL Internet Browser */
#define KEY_MSDOS 151
#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */
#define KEY_SCREENLOCK KEY_COFFEE
#define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */
#define KEY_DIRECTION KEY_ROTATE_DISPLAY
#define KEY_CYCLEWINDOWS 154
#define KEY_MAIL 155
#define KEY_BOOKMARKS 156 /* AC Bookmarks */
#define KEY_COMPUTER 157
#define KEY_BACK 158 /* AC Back */
#define KEY_FORWARD 159 /* AC Forward */
#define KEY_CLOSECD 160
#define KEY_EJECTCD 161
#define KEY_EJECTCLOSECD 162
#define KEY_NEXTSONG 163
#define KEY_PLAYPAUSE 164
#define KEY_PREVIOUSSONG 165
#define KEY_STOPCD 166
#define KEY_RECORD 167
#define KEY_REWIND 168
#define KEY_PHONE 169 /* Media Select Telephone */
#define KEY_ISO 170
#define KEY_CONFIG 171 /* AL Consumer Control Configuration */
#define KEY_HOMEPAGE 172 /* AC Home */
#define KEY_REFRESH 173 /* AC Refresh */
#define KEY_EXIT 174 /* AC Exit */
#define KEY_MOVE 175
#define KEY_EDIT 176
#define KEY_SCROLLUP 177
#define KEY_SCROLLDOWN 178
#define KEY_KPLEFTPAREN 179
#define KEY_KPRIGHTPAREN 180
#define KEY_NEW 181 /* AC New */
#define KEY_REDO 182 /* AC Redo/Repeat */
#define KEY_F13 183
#define KEY_F14 184
#define KEY_F15 185
#define KEY_F16 186
#define KEY_F17 187
#define KEY_F18 188
#define KEY_F19 189
#define KEY_F20 190
#define KEY_F21 191
#define KEY_F22 192
#define KEY_F23 193
#define KEY_F24 194
#define KEY_PLAYCD 200
#define KEY_PAUSECD 201
#define KEY_PROG3 202
#define KEY_PROG4 203
#define KEY_DASHBOARD 204 /* AL Dashboard */
#define KEY_SUSPEND 205
#define KEY_CLOSE 206 /* AC Close */
#define KEY_PLAY 207
#define KEY_FASTFORWARD 208
#define KEY_BASSBOOST 209
#define KEY_PRINT 210 /* AC Print */
#define KEY_HP 211
#define KEY_CAMERA 212
#define KEY_SOUND 213
#define KEY_QUESTION 214
#define KEY_EMAIL 215
#define KEY_CHAT 216
#define KEY_SEARCH 217
#define KEY_CONNECT 218
#define KEY_FINANCE 219 /* AL Checkbook/Finance */
#define KEY_SPORT 220
#define KEY_SHOP 221
#define KEY_ALTERASE 222
#define KEY_CANCEL 223 /* AC Cancel */
#define KEY_BRIGHTNESSDOWN 224
#define KEY_BRIGHTNESSUP 225
#define KEY_MEDIA 226
#define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video
outputs (Monitor/LCD/TV-out/etc) */
#define KEY_KBDILLUMTOGGLE 228
#define KEY_KBDILLUMDOWN 229
#define KEY_KBDILLUMUP 230
#define KEY_SEND 231 /* AC Send */
#define KEY_REPLY 232 /* AC Reply */
#define KEY_FORWARDMAIL 233 /* AC Forward Msg */
#define KEY_SAVE 234 /* AC Save */
#define KEY_DOCUMENTS 235
#define KEY_BATTERY 236
#define KEY_BLUETOOTH 237
#define KEY_WLAN 238
#define KEY_UWB 239
#define KEY_UNKNOWN 240
#define KEY_VIDEO_NEXT 241 /* drive next video source */
#define KEY_VIDEO_PREV 242 /* drive previous video source */
#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */
#define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual
brightness control is off,
rely on ambient */
#define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO
#define KEY_DISPLAY_OFF 245 /* display device to off state */
#define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */
#define KEY_WIMAX KEY_WWAN
#define KEY_RFKILL 247 /* Key that controls all radios */
#define KEY_MICMUTE 248 /* Mute / unmute the microphone */
/* Code 255 is reserved for special needs of AT keyboard driver */
#define BTN_MISC 0x100
#define BTN_0 0x100
#define BTN_1 0x101
#define BTN_2 0x102
#define BTN_3 0x103
#define BTN_4 0x104
#define BTN_5 0x105
#define BTN_6 0x106
#define BTN_7 0x107
#define BTN_8 0x108
#define BTN_9 0x109
#define BTN_MOUSE 0x110
#define BTN_LEFT 0x110
#define BTN_RIGHT 0x111
#define BTN_MIDDLE 0x112
#define BTN_SIDE 0x113
#define BTN_EXTRA 0x114
#define BTN_FORWARD 0x115
#define BTN_BACK 0x116
#define BTN_TASK 0x117
#define BTN_JOYSTICK 0x120
#define BTN_TRIGGER 0x120
#define BTN_THUMB 0x121
#define BTN_THUMB2 0x122
#define BTN_TOP 0x123
#define BTN_TOP2 0x124
#define BTN_PINKIE 0x125
#define BTN_BASE 0x126
#define BTN_BASE2 0x127
#define BTN_BASE3 0x128
#define BTN_BASE4 0x129
#define BTN_BASE5 0x12a
#define BTN_BASE6 0x12b
#define BTN_DEAD 0x12f
#define BTN_GAMEPAD 0x130
#define BTN_SOUTH 0x130
#define BTN_A BTN_SOUTH
#define BTN_EAST 0x131
#define BTN_B BTN_EAST
#define BTN_C 0x132
#define BTN_NORTH 0x133
#define BTN_X BTN_NORTH
#define BTN_WEST 0x134
#define BTN_Y BTN_WEST
#define BTN_Z 0x135
#define BTN_TL 0x136
#define BTN_TR 0x137
#define BTN_TL2 0x138
#define BTN_TR2 0x139
#define BTN_SELECT 0x13a
#define BTN_START 0x13b
#define BTN_MODE 0x13c
#define BTN_THUMBL 0x13d
#define BTN_THUMBR 0x13e
#define BTN_DIGI 0x140
#define BTN_TOOL_PEN 0x140
#define BTN_TOOL_RUBBER 0x141
#define BTN_TOOL_BRUSH 0x142
#define BTN_TOOL_PENCIL 0x143
#define BTN_TOOL_AIRBRUSH 0x144
#define BTN_TOOL_FINGER 0x145
#define BTN_TOOL_MOUSE 0x146
#define BTN_TOOL_LENS 0x147
#define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */
#define BTN_TOUCH 0x14a
#define BTN_STYLUS 0x14b
#define BTN_STYLUS2 0x14c
#define BTN_TOOL_DOUBLETAP 0x14d
#define BTN_TOOL_TRIPLETAP 0x14e
#define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */
#define BTN_WHEEL 0x150
#define BTN_GEAR_DOWN 0x150
#define BTN_GEAR_UP 0x151
#define KEY_OK 0x160
#define KEY_SELECT 0x161
#define KEY_GOTO 0x162
#define KEY_CLEAR 0x163
#define KEY_POWER2 0x164
#define KEY_OPTION 0x165
#define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */
#define KEY_TIME 0x167
#define KEY_VENDOR 0x168
#define KEY_ARCHIVE 0x169
#define KEY_PROGRAM 0x16a /* Media Select Program Guide */
#define KEY_CHANNEL 0x16b
#define KEY_FAVORITES 0x16c
#define KEY_EPG 0x16d
#define KEY_PVR 0x16e /* Media Select Home */
#define KEY_MHP 0x16f
#define KEY_LANGUAGE 0x170
#define KEY_TITLE 0x171
#define KEY_SUBTITLE 0x172
#define KEY_ANGLE 0x173
#define KEY_ZOOM 0x174
#define KEY_MODE 0x175
#define KEY_KEYBOARD 0x176
#define KEY_SCREEN 0x177
#define KEY_PC 0x178 /* Media Select Computer */
#define KEY_TV 0x179 /* Media Select TV */
#define KEY_TV2 0x17a /* Media Select Cable */
#define KEY_VCR 0x17b /* Media Select VCR */
#define KEY_VCR2 0x17c /* VCR Plus */
#define KEY_SAT 0x17d /* Media Select Satellite */
#define KEY_SAT2 0x17e
#define KEY_CD 0x17f /* Media Select CD */
#define KEY_TAPE 0x180 /* Media Select Tape */
#define KEY_RADIO 0x181
#define KEY_TUNER 0x182 /* Media Select Tuner */
#define KEY_PLAYER 0x183
#define KEY_TEXT 0x184
#define KEY_DVD 0x185 /* Media Select DVD */
#define KEY_AUX 0x186
#define KEY_MP3 0x187
#define KEY_AUDIO 0x188 /* AL Audio Browser */
#define KEY_VIDEO 0x189 /* AL Movie Browser */
#define KEY_DIRECTORY 0x18a
#define KEY_LIST 0x18b
#define KEY_MEMO 0x18c /* Media Select Messages */
#define KEY_CALENDAR 0x18d
#define KEY_RED 0x18e
#define KEY_GREEN 0x18f
#define KEY_YELLOW 0x190
#define KEY_BLUE 0x191
#define KEY_CHANNELUP 0x192 /* Channel Increment */
#define KEY_CHANNELDOWN 0x193 /* Channel Decrement */
#define KEY_FIRST 0x194
#define KEY_LAST 0x195 /* Recall Last */
#define KEY_AB 0x196
#define KEY_NEXT 0x197
#define KEY_RESTART 0x198
#define KEY_SLOW 0x199
#define KEY_SHUFFLE 0x19a
#define KEY_BREAK 0x19b
#define KEY_PREVIOUS 0x19c
#define KEY_DIGITS 0x19d
#define KEY_TEEN 0x19e
#define KEY_TWEN 0x19f
#define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */
#define KEY_GAMES 0x1a1 /* Media Select Games */
#define KEY_ZOOMIN 0x1a2 /* AC Zoom In */
#define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */
#define KEY_ZOOMRESET 0x1a4 /* AC Zoom */
#define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */
#define KEY_EDITOR 0x1a6 /* AL Text Editor */
#define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */
#define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */
#define KEY_PRESENTATION 0x1a9 /* AL Presentation App */
#define KEY_DATABASE 0x1aa /* AL Database App */
#define KEY_NEWS 0x1ab /* AL Newsreader */
#define KEY_VOICEMAIL 0x1ac /* AL Voicemail */
#define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */
#define KEY_MESSENGER 0x1ae /* AL Instant Messaging */
#define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */
#define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE
#define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */
#define KEY_LOGOFF 0x1b1 /* AL Logoff */
#define KEY_DOLLAR 0x1b2
#define KEY_EURO 0x1b3
#define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */
#define KEY_FRAMEFORWARD 0x1b5
#define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */
#define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */
#define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */
#define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */
#define KEY_IMAGES 0x1ba /* AL Image Browser */
#define KEY_DEL_EOL 0x1c0
#define KEY_DEL_EOS 0x1c1
#define KEY_INS_LINE 0x1c2
#define KEY_DEL_LINE 0x1c3
#define KEY_FN 0x1d0
#define KEY_FN_ESC 0x1d1
#define KEY_FN_F1 0x1d2
#define KEY_FN_F2 0x1d3
#define KEY_FN_F3 0x1d4
#define KEY_FN_F4 0x1d5
#define KEY_FN_F5 0x1d6
#define KEY_FN_F6 0x1d7
#define KEY_FN_F7 0x1d8
#define KEY_FN_F8 0x1d9
#define KEY_FN_F9 0x1da
#define KEY_FN_F10 0x1db
#define KEY_FN_F11 0x1dc
#define KEY_FN_F12 0x1dd
#define KEY_FN_1 0x1de
#define KEY_FN_2 0x1df
#define KEY_FN_D 0x1e0
#define KEY_FN_E 0x1e1
#define KEY_FN_F 0x1e2
#define KEY_FN_S 0x1e3
#define KEY_FN_B 0x1e4
#define KEY_BRL_DOT1 0x1f1
#define KEY_BRL_DOT2 0x1f2
#define KEY_BRL_DOT3 0x1f3
#define KEY_BRL_DOT4 0x1f4
#define KEY_BRL_DOT5 0x1f5
#define KEY_BRL_DOT6 0x1f6
#define KEY_BRL_DOT7 0x1f7
#define KEY_BRL_DOT8 0x1f8
#define KEY_BRL_DOT9 0x1f9
#define KEY_BRL_DOT10 0x1fa
#define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */
#define KEY_NUMERIC_1 0x201 /* and other keypads */
#define KEY_NUMERIC_2 0x202
#define KEY_NUMERIC_3 0x203
#define KEY_NUMERIC_4 0x204
#define KEY_NUMERIC_5 0x205
#define KEY_NUMERIC_6 0x206
#define KEY_NUMERIC_7 0x207
#define KEY_NUMERIC_8 0x208
#define KEY_NUMERIC_9 0x209
#define KEY_NUMERIC_STAR 0x20a
#define KEY_NUMERIC_POUND 0x20b
#define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */
#define KEY_NUMERIC_B 0x20d
#define KEY_NUMERIC_C 0x20e
#define KEY_NUMERIC_D 0x20f
#define KEY_CAMERA_FOCUS 0x210
#define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */
#define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */
#define KEY_TOUCHPAD_ON 0x213
#define KEY_TOUCHPAD_OFF 0x214
#define KEY_CAMERA_ZOOMIN 0x215
#define KEY_CAMERA_ZOOMOUT 0x216
#define KEY_CAMERA_UP 0x217
#define KEY_CAMERA_DOWN 0x218
#define KEY_CAMERA_LEFT 0x219
#define KEY_CAMERA_RIGHT 0x21a
#define KEY_ATTENDANT_ON 0x21b
#define KEY_ATTENDANT_OFF 0x21c
#define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */
#define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */
#define BTN_DPAD_UP 0x220
#define BTN_DPAD_DOWN 0x221
#define BTN_DPAD_LEFT 0x222
#define BTN_DPAD_RIGHT 0x223
#define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */
#define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */
#define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */
#define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */
#define KEY_CONTROLPANEL 0x243 /* AL Control Panel */
#define KEY_APPSELECT 0x244 /* AL Select Task/Application */
#define KEY_SCREENSAVER 0x245 /* AL Screen Saver */
#define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */
#define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */
#define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */
#define KEY_KBDINPUTASSIST_PREV 0x260
#define KEY_KBDINPUTASSIST_NEXT 0x261
#define KEY_KBDINPUTASSIST_PREVGROUP 0x262
#define KEY_KBDINPUTASSIST_NEXTGROUP 0x263
#define KEY_KBDINPUTASSIST_ACCEPT 0x264
#define KEY_KBDINPUTASSIST_CANCEL 0x265
#define BTN_TRIGGER_HAPPY 0x2c0
#define BTN_TRIGGER_HAPPY1 0x2c0
#define BTN_TRIGGER_HAPPY2 0x2c1
#define BTN_TRIGGER_HAPPY3 0x2c2
#define BTN_TRIGGER_HAPPY4 0x2c3
#define BTN_TRIGGER_HAPPY5 0x2c4
#define BTN_TRIGGER_HAPPY6 0x2c5
#define BTN_TRIGGER_HAPPY7 0x2c6
#define BTN_TRIGGER_HAPPY8 0x2c7
#define BTN_TRIGGER_HAPPY9 0x2c8
#define BTN_TRIGGER_HAPPY10 0x2c9
#define BTN_TRIGGER_HAPPY11 0x2ca
#define BTN_TRIGGER_HAPPY12 0x2cb
#define BTN_TRIGGER_HAPPY13 0x2cc
#define BTN_TRIGGER_HAPPY14 0x2cd
#define BTN_TRIGGER_HAPPY15 0x2ce
#define BTN_TRIGGER_HAPPY16 0x2cf
#define BTN_TRIGGER_HAPPY17 0x2d0
#define BTN_TRIGGER_HAPPY18 0x2d1
#define BTN_TRIGGER_HAPPY19 0x2d2
#define BTN_TRIGGER_HAPPY20 0x2d3
#define BTN_TRIGGER_HAPPY21 0x2d4
#define BTN_TRIGGER_HAPPY22 0x2d5
#define BTN_TRIGGER_HAPPY23 0x2d6
#define BTN_TRIGGER_HAPPY24 0x2d7
#define BTN_TRIGGER_HAPPY25 0x2d8
#define BTN_TRIGGER_HAPPY26 0x2d9
#define BTN_TRIGGER_HAPPY27 0x2da
#define BTN_TRIGGER_HAPPY28 0x2db
#define BTN_TRIGGER_HAPPY29 0x2dc
#define BTN_TRIGGER_HAPPY30 0x2dd
#define BTN_TRIGGER_HAPPY31 0x2de
#define BTN_TRIGGER_HAPPY32 0x2df
#define BTN_TRIGGER_HAPPY33 0x2e0
#define BTN_TRIGGER_HAPPY34 0x2e1
#define BTN_TRIGGER_HAPPY35 0x2e2
#define BTN_TRIGGER_HAPPY36 0x2e3
#define BTN_TRIGGER_HAPPY37 0x2e4
#define BTN_TRIGGER_HAPPY38 0x2e5
#define BTN_TRIGGER_HAPPY39 0x2e6
#define BTN_TRIGGER_HAPPY40 0x2e7
/* We avoid low common keys in module aliases so they don't get huge. */
#define KEY_MIN_INTERESTING KEY_MUTE
#define KEY_MAX 0x2ff
#define KEY_CNT (KEY_MAX+1)
/*
* Relative axes
*/
#define REL_X 0x00
#define REL_Y 0x01
#define REL_Z 0x02
#define REL_RX 0x03
#define REL_RY 0x04
#define REL_RZ 0x05
#define REL_HWHEEL 0x06
#define REL_DIAL 0x07
#define REL_WHEEL 0x08
#define REL_MISC 0x09
#define REL_MAX 0x0f
#define REL_CNT (REL_MAX+1)
/*
* Absolute axes
*/
#define ABS_X 0x00
#define ABS_Y 0x01
#define ABS_Z 0x02
#define ABS_RX 0x03
#define ABS_RY 0x04
#define ABS_RZ 0x05
#define ABS_THROTTLE 0x06
#define ABS_RUDDER 0x07
#define ABS_WHEEL 0x08
#define ABS_GAS 0x09
#define ABS_BRAKE 0x0a
#define ABS_HAT0X 0x10
#define ABS_HAT0Y 0x11
#define ABS_HAT1X 0x12
#define ABS_HAT1Y 0x13
#define ABS_HAT2X 0x14
#define ABS_HAT2Y 0x15
#define ABS_HAT3X 0x16
#define ABS_HAT3Y 0x17
#define ABS_PRESSURE 0x18
#define ABS_DISTANCE 0x19
#define ABS_TILT_X 0x1a
#define ABS_TILT_Y 0x1b
#define ABS_TOOL_WIDTH 0x1c
#define ABS_VOLUME 0x20
#define ABS_MISC 0x28
#define ABS_MT_SLOT 0x2f /* MT slot being modified */
#define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */
#define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */
#define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */
#define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */
#define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */
#define ABS_MT_POSITION_X 0x35 /* Center X touch position */
#define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */
#define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */
#define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */
#define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */
#define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */
#define ABS_MT_DISTANCE 0x3b /* Contact hover distance */
#define ABS_MT_TOOL_X 0x3c /* Center X tool position */
#define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */
#define ABS_MAX 0x3f
#define ABS_CNT (ABS_MAX+1)
/*
* Switch events
*/
#define SW_LID 0x00 /* set = lid shut */
#define SW_TABLET_MODE 0x01 /* set = tablet mode */
#define SW_HEADPHONE_INSERT 0x02 /* set = inserted */
#define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any"
set = radio enabled */
#define SW_RADIO SW_RFKILL_ALL /* deprecated */
#define SW_MICROPHONE_INSERT 0x04 /* set = inserted */
#define SW_DOCK 0x05 /* set = plugged into dock */
#define SW_LINEOUT_INSERT 0x06 /* set = inserted */
#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */
#define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */
#define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */
#define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */
#define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */
#define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */
#define SW_LINEIN_INSERT 0x0d /* set = inserted */
#define SW_MUTE_DEVICE 0x0e /* set = device disabled */
#define SW_MAX 0x0f
#define SW_CNT (SW_MAX+1)
/*
* Misc events
*/
#define MSC_SERIAL 0x00
#define MSC_PULSELED 0x01
#define MSC_GESTURE 0x02
#define MSC_RAW 0x03
#define MSC_SCAN 0x04
#define MSC_TIMESTAMP 0x05
#define MSC_MAX 0x07
#define MSC_CNT (MSC_MAX+1)
/*
* LEDs
*/
#define LED_NUML 0x00
#define LED_CAPSL 0x01
#define LED_SCROLLL 0x02
#define LED_COMPOSE 0x03
#define LED_KANA 0x04
#define LED_SLEEP 0x05
#define LED_SUSPEND 0x06
#define LED_MUTE 0x07
#define LED_MISC 0x08
#define LED_MAIL 0x09
#define LED_CHARGING 0x0a
#define LED_MAX 0x0f
#define LED_CNT (LED_MAX+1)
/*
* Autorepeat values
*/
#define REP_DELAY 0x00
#define REP_PERIOD 0x01
#define REP_MAX 0x01
#define REP_CNT (REP_MAX+1)
/*
* Sounds
*/
#define SND_CLICK 0x00
#define SND_BELL 0x01
#define SND_TONE 0x02
#define SND_MAX 0x07
#define SND_CNT (SND_MAX+1)
#define MATRIX_KEY(row, col, code) \
((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))
#endif /* _DT_BINDINGS_INPUT_INPUT_H */
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/interrupt-controller/irq.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for most IRQ bindings.
*
* Most IRQ bindings include a flags cell as part of the IRQ specifier.
* In most cases, the format of the flags cell uses the standard values
* defined in this header.
*/
#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
#define IRQ_TYPE_NONE 0
#define IRQ_TYPE_EDGE_RISING 1
#define IRQ_TYPE_EDGE_FALLING 2
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
#define IRQ_TYPE_LEVEL_HIGH 4
#define IRQ_TYPE_LEVEL_LOW 8
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/net/mscc-phy-vsc8531.h
+40
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Device Tree constants for Microsemi VSC8531 PHY
*
* Author: Nagaraju Lakkaraju
*
* Copyright (c) 2017 Microsemi Corporation
*/
#ifndef _DT_BINDINGS_MSCC_VSC8531_H
#define _DT_BINDINGS_MSCC_VSC8531_H
/* PHY LED Modes */
#define VSC8531_LINK_ACTIVITY 0
#define VSC8531_LINK_1000_ACTIVITY 1
#define VSC8531_LINK_100_ACTIVITY 2
#define VSC8531_LINK_10_ACTIVITY 3
#define VSC8531_LINK_100_1000_ACTIVITY 4
#define VSC8531_LINK_10_1000_ACTIVITY 5
#define VSC8531_LINK_10_100_ACTIVITY 6
#define VSC8584_LINK_100FX_1000X_ACTIVITY 7
#define VSC8531_DUPLEX_COLLISION 8
#define VSC8531_COLLISION 9
#define VSC8531_ACTIVITY 10
#define VSC8584_100FX_1000X_ACTIVITY 11
#define VSC8531_AUTONEG_FAULT 12
#define VSC8531_SERIAL_MODE 13
#define VSC8531_FORCE_LED_OFF 14
#define VSC8531_FORCE_LED_ON 15
#define VSC8531_RGMII_CLK_DELAY_0_2_NS 0
#define VSC8531_RGMII_CLK_DELAY_0_8_NS 1
#define VSC8531_RGMII_CLK_DELAY_1_1_NS 2
#define VSC8531_RGMII_CLK_DELAY_1_7_NS 3
#define VSC8531_RGMII_CLK_DELAY_2_0_NS 4
#define VSC8531_RGMII_CLK_DELAY_2_3_NS 5
#define VSC8531_RGMII_CLK_DELAY_2_6_NS 6
#define VSC8531_RGMII_CLK_DELAY_3_4_NS 7
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/net/ti-dp83867.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Device Tree constants for the Texas Instruments DP83867 PHY
*
* Author: Dan Murphy <dmurphy@ti.com>
*
* Copyright: (C) 2015 Texas Instruments, Inc.
*/
#ifndef _DT_BINDINGS_TI_DP83867_H
#define _DT_BINDINGS_TI_DP83867_H
/* PHY CTRL bits */
#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00
#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01
#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02
#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03
/* RGMIIDCTL internal delay for rx and tx */
#define DP83867_RGMIIDCTL_250_PS 0x0
#define DP83867_RGMIIDCTL_500_PS 0x1
#define DP83867_RGMIIDCTL_750_PS 0x2
#define DP83867_RGMIIDCTL_1_NS 0x3
#define DP83867_RGMIIDCTL_1_25_NS 0x4
#define DP83867_RGMIIDCTL_1_50_NS 0x5
#define DP83867_RGMIIDCTL_1_75_NS 0x6
#define DP83867_RGMIIDCTL_2_00_NS 0x7
#define DP83867_RGMIIDCTL_2_25_NS 0x8
#define DP83867_RGMIIDCTL_2_50_NS 0x9
#define DP83867_RGMIIDCTL_2_75_NS 0xa
#define DP83867_RGMIIDCTL_3_00_NS 0xb
#define DP83867_RGMIIDCTL_3_25_NS 0xc
#define DP83867_RGMIIDCTL_3_50_NS 0xd
#define DP83867_RGMIIDCTL_3_75_NS 0xe
#define DP83867_RGMIIDCTL_4_00_NS 0xf
/* IO_MUX_CFG - Clock output selection */
#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0
#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1
#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2
#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3
#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4
#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5
#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6
#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7
#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8
#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9
#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA
#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB
#define DP83867_CLK_O_SEL_REF_CLK 0xC
/* Special flag to indicate clock should be off */
#define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/phy/phy.h
+24
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/*
*
* This header provides constants for the phy framework
*
* Copyright (C) 2014 STMicroelectronics
* Author: Gabriel Fernandez <gabriel.fernandez@st.com>
* License terms: GNU General Public License (GPL), version 2
*/
#ifndef _DT_BINDINGS_PHY
#define _DT_BINDINGS_PHY
#define PHY_NONE 0
#define PHY_TYPE_SATA 1
#define PHY_TYPE_PCIE 2
#define PHY_TYPE_USB2 3
#define PHY_TYPE_USB3 4
#define PHY_TYPE_UFS 5
#define PHY_TYPE_DP 6
#define PHY_TYPE_XPCS 7
#define PHY_TYPE_SGMII 8
#define PHY_TYPE_QSGMII 9
#endif /* _DT_BINDINGS_PHY */
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/pinctrl/pinctrl-zynqmp.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* MIO pin configuration defines for Xilinx ZynqMP
*
* Copyright (C) 2020-2022 Xilinx, Inc.
* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
*/
#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H
#define _DT_BINDINGS_PINCTRL_ZYNQMP_H
/* Bit value for different voltage levels */
#define IO_STANDARD_LVCMOS33 0
#define IO_STANDARD_LVCMOS18 1
/* Bit values for Slew Rates */
#define SLEW_RATE_FAST 0
#define SLEW_RATE_SLOW 1
/* Bit values for Pin drive strength */
#define DRIVE_STRENGTH_2MA 2
#define DRIVE_STRENGTH_4MA 4
#define DRIVE_STRENGTH_8MA 8
#define DRIVE_STRENGTH_12MA 12
#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/power/xlnx-versal-net-power.h
+32
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022-2022 Xilinx, Inc.
* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
*/
#ifndef _DT_BINDINGS_VERSAL_NET_POWER_H
#define _DT_BINDINGS_VERSAL_NET_POWER_H
#include "xlnx-versal-power.h"
#define PM_DEV_USB_1 (0x182240D7U)
#define PM_DEV_FPD_SWDT_0 (0x182240DBU)
#define PM_DEV_FPD_SWDT_1 (0x182240DCU)
#define PM_DEV_FPD_SWDT_2 (0x182240DDU)
#define PM_DEV_FPD_SWDT_3 (0x182240DEU)
/* Remove Versal specific node IDs */
#undef PM_DEV_RPU0_0
#undef PM_DEV_RPU0_1
#undef PM_DEV_OCM_0
#undef PM_DEV_OCM_1
#undef PM_DEV_OCM_2
#undef PM_DEV_OCM_3
#undef PM_DEV_TCM_0_A
#undef PM_DEV_TCM_1_A
#undef PM_DEV_TCM_0_B
#undef PM_DEV_TCM_1_B
#undef PM_DEV_SWDT_FPD
#undef PM_DEV_AI
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/power/xlnx-versal-power.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019-2022 Xilinx, Inc.
* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
*/
#ifndef _DT_BINDINGS_VERSAL_POWER_H
#define _DT_BINDINGS_VERSAL_POWER_H
#define PM_DEV_RPU0_0 (0x18110005U)
#define PM_DEV_RPU0_1 (0x18110006U)
#define PM_DEV_OCM_0 (0x18314007U)
#define PM_DEV_OCM_1 (0x18314008U)
#define PM_DEV_OCM_2 (0x18314009U)
#define PM_DEV_OCM_3 (0x1831400aU)
#define PM_DEV_TCM_0_A (0x1831800bU)
#define PM_DEV_TCM_0_B (0x1831800cU)
#define PM_DEV_TCM_1_A (0x1831800dU)
#define PM_DEV_TCM_1_B (0x1831800eU)
#define PM_DEV_USB_0 (0x18224018U)
#define PM_DEV_GEM_0 (0x18224019U)
#define PM_DEV_GEM_1 (0x1822401aU)
#define PM_DEV_SPI_0 (0x1822401bU)
#define PM_DEV_SPI_1 (0x1822401cU)
#define PM_DEV_I2C_0 (0x1822401dU)
#define PM_DEV_I2C_1 (0x1822401eU)
#define PM_DEV_I2C_PMC (0x1822402dU)
#define PM_DEV_CAN_FD_0 (0x1822401fU)
#define PM_DEV_CAN_FD_1 (0x18224020U)
#define PM_DEV_UART_0 (0x18224021U)
#define PM_DEV_UART_1 (0x18224022U)
#define PM_DEV_GPIO (0x18224023U)
#define PM_DEV_TTC_0 (0x18224024U)
#define PM_DEV_TTC_1 (0x18224025U)
#define PM_DEV_TTC_2 (0x18224026U)
#define PM_DEV_TTC_3 (0x18224027U)
#define PM_DEV_SWDT_FPD (0x18224029U)
#define PM_DEV_OSPI (0x1822402aU)
#define PM_DEV_QSPI (0x1822402bU)
#define PM_DEV_GPIO_PMC (0x1822402cU)
#define PM_DEV_SDIO_0 (0x1822402eU)
#define PM_DEV_SDIO_1 (0x1822402fU)
#define PM_DEV_RTC (0x18224034U)
#define PM_DEV_ADMA_0 (0x18224035U)
#define PM_DEV_ADMA_1 (0x18224036U)
#define PM_DEV_ADMA_2 (0x18224037U)
#define PM_DEV_ADMA_3 (0x18224038U)
#define PM_DEV_ADMA_4 (0x18224039U)
#define PM_DEV_ADMA_5 (0x1822403aU)
#define PM_DEV_ADMA_6 (0x1822403bU)
#define PM_DEV_ADMA_7 (0x1822403cU)
#define PM_DEV_AI (0x18224072U)
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/power/xlnx-versal-regnode.h
+15
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022-2022 Xilinx, Inc.
* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
*/
#ifndef _DT_BINDINGS_VERSAL_REGNODE_H
#define _DT_BINDINGS_VERSAL_REGNODE_H
#define PM_REGNODE_SYSMON_ROOT_0 (0x18224055U)
#define PM_REGNODE_SYSMON_ROOT_1 (0x18225055U)
#define PM_REGNODE_SYSMON_ROOT_2 (0x18226055U)
#define PM_REGNODE_SYSMON_ROOT_3 (0x18227055U)
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/power/xlnx-zynqmp-power.h
+52
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018-2022 Xilinx, Inc.
* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
*/
#ifndef _DT_BINDINGS_ZYNQMP_POWER_H
#define _DT_BINDINGS_ZYNQMP_POWER_H
#define PD_RPU 6
#define PD_RPU_0 7
#define PD_RPU_1 8
#define PD_OCM_0 11
#define PD_OCM_1 12
#define PD_OCM_2 13
#define PD_OCM_3 14
#define PD_TCM_0_A 15
#define PD_TCM_0_B 16
#define PD_TCM_1_A 17
#define PD_TCM_1_B 18
#define PD_USB_0 22
#define PD_USB_1 23
#define PD_TTC_0 24
#define PD_TTC_1 25
#define PD_TTC_2 26
#define PD_TTC_3 27
#define PD_SATA 28
#define PD_ETH_0 29
#define PD_ETH_1 30
#define PD_ETH_2 31
#define PD_ETH_3 32
#define PD_UART_0 33
#define PD_UART_1 34
#define PD_SPI_0 35
#define PD_SPI_1 36
#define PD_I2C_0 37
#define PD_I2C_1 38
#define PD_SD_0 39
#define PD_SD_1 40
#define PD_DP 41
#define PD_GDMA 42
#define PD_ADMA 43
#define PD_NAND 44
#define PD_QSPI 45
#define PD_GPIO 46
#define PD_CAN_0 47
#define PD_CAN_1 48
#define PD_GPU 58
#define PD_PCIE 59
#define PD_PL 69
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/reset/xlnx-versal-net-resets.h
+53
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020-2022 Xilinx, Inc.
* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
*/
#ifndef _DT_BINDINGS_VERSAL_NET_RESETS_H
#define _DT_BINDINGS_VERSAL_NET_RESETS_H
#include "xlnx-versal-resets.h"
#define VERSAL_RST_USB_1 (0xC1040C6U)
/* Remove Versal specific reset IDs */
#undef VERSAL_RST_ACPU_0_POR
#undef VERSAL_RST_ACPU_1_POR
#undef VERSAL_RST_OCM2_POR
#undef VERSAL_RST_APU
#undef VERSAL_RST_ACPU_0
#undef VERSAL_RST_ACPU_1
#undef VERSAL_RST_ACPU_L2
#undef VERSAL_RST_RPU_ISLAND
#undef VERSAL_RST_RPU_AMBA
#undef VERSAL_RST_R5_0
#undef VERSAL_RST_R5_1
#undef VERSAL_RST_OCM2_RST
#undef VERSAL_RST_I2C_PMC
#undef VERSAL_RST_I2C_0
#undef VERSAL_RST_I2C_1
#undef VERSAL_RST_SWDT_FPD
#undef VERSAL_RST_SWDT_LPD
#undef VERSAL_RST_USB
#undef VERSAL_RST_DPC
#undef VERSAL_RST_DBG_TRACE
#undef VERSAL_RST_DBG_TSTMP
#undef VERSAL_RST_RPU0_DBG
#undef VERSAL_RST_RPU1_DBG
#undef VERSAL_RST_HSDP
#undef VERSAL_RST_CPMDBG
#undef VERSAL_RST_PCIE_CFG
#undef VERSAL_RST_PCIE_CORE0
#undef VERSAL_RST_PCIE_CORE1
#undef VERSAL_RST_PCIE_DMA
#undef VERSAL_RST_L2_0
#undef VERSAL_RST_L2_1
#undef VERSAL_RST_ADDR_REMAP
#undef VERSAL_RST_CPI0
#undef VERSAL_RST_CPI1
#undef VERSAL_RST_XRAM
#undef VERSAL_RST_AIE_ARRAY
#undef VERSAL_RST_AIE_SHIM
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/reset/xlnx-versal-resets.h
+106
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020-2022 Xilinx, Inc.
* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
*/
#ifndef _DT_BINDINGS_VERSAL_RESETS_H
#define _DT_BINDINGS_VERSAL_RESETS_H
#define VERSAL_RST_PMC_POR (0xc30c001U)
#define VERSAL_RST_PMC (0xc410002U)
#define VERSAL_RST_PS_POR (0xc30c003U)
#define VERSAL_RST_PL_POR (0xc30c004U)
#define VERSAL_RST_NOC_POR (0xc30c005U)
#define VERSAL_RST_FPD_POR (0xc30c006U)
#define VERSAL_RST_ACPU_0_POR (0xc30c007U)
#define VERSAL_RST_ACPU_1_POR (0xc30c008U)
#define VERSAL_RST_OCM2_POR (0xc30c009U)
#define VERSAL_RST_PS_SRST (0xc41000aU)
#define VERSAL_RST_PL_SRST (0xc41000bU)
#define VERSAL_RST_NOC (0xc41000cU)
#define VERSAL_RST_NPI (0xc41000dU)
#define VERSAL_RST_SYS_RST_1 (0xc41000eU)
#define VERSAL_RST_SYS_RST_2 (0xc41000fU)
#define VERSAL_RST_SYS_RST_3 (0xc410010U)
#define VERSAL_RST_FPD (0xc410011U)
#define VERSAL_RST_PL0 (0xc410012U)
#define VERSAL_RST_PL1 (0xc410013U)
#define VERSAL_RST_PL2 (0xc410014U)
#define VERSAL_RST_PL3 (0xc410015U)
#define VERSAL_RST_APU (0xc410016U)
#define VERSAL_RST_ACPU_0 (0xc410017U)
#define VERSAL_RST_ACPU_1 (0xc410018U)
#define VERSAL_RST_ACPU_L2 (0xc410019U)
#define VERSAL_RST_ACPU_GIC (0xc41001aU)
#define VERSAL_RST_RPU_ISLAND (0xc41001bU)
#define VERSAL_RST_RPU_AMBA (0xc41001cU)
#define VERSAL_RST_R5_0 (0xc41001dU)
#define VERSAL_RST_R5_1 (0xc41001eU)
#define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU)
#define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U)
#define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U)
#define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U)
#define VERSAL_RST_SYSMON_LPD (0xc410023U)
#define VERSAL_RST_PDMA_RST1 (0xc410024U)
#define VERSAL_RST_PDMA_RST0 (0xc410025U)
#define VERSAL_RST_ADMA (0xc410026U)
#define VERSAL_RST_TIMESTAMP (0xc410027U)
#define VERSAL_RST_OCM (0xc410028U)
#define VERSAL_RST_OCM2_RST (0xc410029U)
#define VERSAL_RST_IPI (0xc41002aU)
#define VERSAL_RST_SBI (0xc41002bU)
#define VERSAL_RST_LPD (0xc41002cU)
#define VERSAL_RST_QSPI (0xc10402dU)
#define VERSAL_RST_OSPI (0xc10402eU)
#define VERSAL_RST_SDIO_0 (0xc10402fU)
#define VERSAL_RST_SDIO_1 (0xc104030U)
#define VERSAL_RST_I2C_PMC (0xc104031U)
#define VERSAL_RST_GPIO_PMC (0xc104032U)
#define VERSAL_RST_GEM_0 (0xc104033U)
#define VERSAL_RST_GEM_1 (0xc104034U)
#define VERSAL_RST_SPARE (0xc104035U)
#define VERSAL_RST_USB_0 (0xc104036U)
#define VERSAL_RST_UART_0 (0xc104037U)
#define VERSAL_RST_UART_1 (0xc104038U)
#define VERSAL_RST_SPI_0 (0xc104039U)
#define VERSAL_RST_SPI_1 (0xc10403aU)
#define VERSAL_RST_CAN_FD_0 (0xc10403bU)
#define VERSAL_RST_CAN_FD_1 (0xc10403cU)
#define VERSAL_RST_I2C_0 (0xc10403dU)
#define VERSAL_RST_I2C_1 (0xc10403eU)
#define VERSAL_RST_GPIO_LPD (0xc10403fU)
#define VERSAL_RST_TTC_0 (0xc104040U)
#define VERSAL_RST_TTC_1 (0xc104041U)
#define VERSAL_RST_TTC_2 (0xc104042U)
#define VERSAL_RST_TTC_3 (0xc104043U)
#define VERSAL_RST_SWDT_FPD (0xc104044U)
#define VERSAL_RST_SWDT_LPD (0xc104045U)
#define VERSAL_RST_USB (0xc104046U)
#define VERSAL_RST_DPC (0xc208047U)
#define VERSAL_RST_PMCDBG (0xc208048U)
#define VERSAL_RST_DBG_TRACE (0xc208049U)
#define VERSAL_RST_DBG_FPD (0xc20804aU)
#define VERSAL_RST_DBG_TSTMP (0xc20804bU)
#define VERSAL_RST_RPU0_DBG (0xc20804cU)
#define VERSAL_RST_RPU1_DBG (0xc20804dU)
#define VERSAL_RST_HSDP (0xc20804eU)
#define VERSAL_RST_DBG_LPD (0xc20804fU)
#define VERSAL_RST_CPM_POR (0xc30c050U)
#define VERSAL_RST_CPM (0xc410051U)
#define VERSAL_RST_CPMDBG (0xc208052U)
#define VERSAL_RST_PCIE_CFG (0xc410053U)
#define VERSAL_RST_PCIE_CORE0 (0xc410054U)
#define VERSAL_RST_PCIE_CORE1 (0xc410055U)
#define VERSAL_RST_PCIE_DMA (0xc410056U)
#define VERSAL_RST_CMN (0xc410057U)
#define VERSAL_RST_L2_0 (0xc410058U)
#define VERSAL_RST_L2_1 (0xc410059U)
#define VERSAL_RST_ADDR_REMAP (0xc41005aU)
#define VERSAL_RST_CPI0 (0xc41005bU)
#define VERSAL_RST_CPI1 (0xc41005cU)
#define VERSAL_RST_XRAM (0xc30c05dU)
#define VERSAL_RST_AIE_ARRAY (0xc10405eU)
#define VERSAL_RST_AIE_SHIM (0xc10405fU)
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/reset/xlnx-zynqmp-resets.h
+131
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018-2022 Xilinx, Inc.
* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
*/
#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H
#define _DT_BINDINGS_ZYNQMP_RESETS_H
#define ZYNQMP_RESET_PCIE_CFG 0
#define ZYNQMP_RESET_PCIE_BRIDGE 1
#define ZYNQMP_RESET_PCIE_CTRL 2
#define ZYNQMP_RESET_DP 3
#define ZYNQMP_RESET_SWDT_CRF 4
#define ZYNQMP_RESET_AFI_FM5 5
#define ZYNQMP_RESET_AFI_FM4 6
#define ZYNQMP_RESET_AFI_FM3 7
#define ZYNQMP_RESET_AFI_FM2 8
#define ZYNQMP_RESET_AFI_FM1 9
#define ZYNQMP_RESET_AFI_FM0 10
#define ZYNQMP_RESET_GDMA 11
#define ZYNQMP_RESET_GPU_PP1 12
#define ZYNQMP_RESET_GPU_PP0 13
#define ZYNQMP_RESET_GPU 14
#define ZYNQMP_RESET_GT 15
#define ZYNQMP_RESET_SATA 16
#define ZYNQMP_RESET_ACPU3_PWRON 17
#define ZYNQMP_RESET_ACPU2_PWRON 18
#define ZYNQMP_RESET_ACPU1_PWRON 19
#define ZYNQMP_RESET_ACPU0_PWRON 20
#define ZYNQMP_RESET_APU_L2 21
#define ZYNQMP_RESET_ACPU3 22
#define ZYNQMP_RESET_ACPU2 23
#define ZYNQMP_RESET_ACPU1 24
#define ZYNQMP_RESET_ACPU0 25
#define ZYNQMP_RESET_DDR 26
#define ZYNQMP_RESET_APM_FPD 27
#define ZYNQMP_RESET_SOFT 28
#define ZYNQMP_RESET_GEM0 29
#define ZYNQMP_RESET_GEM1 30
#define ZYNQMP_RESET_GEM2 31
#define ZYNQMP_RESET_GEM3 32
#define ZYNQMP_RESET_QSPI 33
#define ZYNQMP_RESET_UART0 34
#define ZYNQMP_RESET_UART1 35
#define ZYNQMP_RESET_SPI0 36
#define ZYNQMP_RESET_SPI1 37
#define ZYNQMP_RESET_SDIO0 38
#define ZYNQMP_RESET_SDIO1 39
#define ZYNQMP_RESET_CAN0 40
#define ZYNQMP_RESET_CAN1 41
#define ZYNQMP_RESET_I2C0 42
#define ZYNQMP_RESET_I2C1 43
#define ZYNQMP_RESET_TTC0 44
#define ZYNQMP_RESET_TTC1 45
#define ZYNQMP_RESET_TTC2 46
#define ZYNQMP_RESET_TTC3 47
#define ZYNQMP_RESET_SWDT_CRL 48
#define ZYNQMP_RESET_NAND 49
#define ZYNQMP_RESET_ADMA 50
#define ZYNQMP_RESET_GPIO 51
#define ZYNQMP_RESET_IOU_CC 52
#define ZYNQMP_RESET_TIMESTAMP 53
#define ZYNQMP_RESET_RPU_R50 54
#define ZYNQMP_RESET_RPU_R51 55
#define ZYNQMP_RESET_RPU_AMBA 56
#define ZYNQMP_RESET_OCM 57
#define ZYNQMP_RESET_RPU_PGE 58
#define ZYNQMP_RESET_USB0_CORERESET 59
#define ZYNQMP_RESET_USB1_CORERESET 60
#define ZYNQMP_RESET_USB0_HIBERRESET 61
#define ZYNQMP_RESET_USB1_HIBERRESET 62
#define ZYNQMP_RESET_USB0_APB 63
#define ZYNQMP_RESET_USB1_APB 64
#define ZYNQMP_RESET_IPI 65
#define ZYNQMP_RESET_APM_LPD 66
#define ZYNQMP_RESET_RTC 67
#define ZYNQMP_RESET_SYSMON 68
#define ZYNQMP_RESET_AFI_FM6 69
#define ZYNQMP_RESET_LPD_SWDT 70
#define ZYNQMP_RESET_FPD 71
#define ZYNQMP_RESET_RPU_DBG1 72
#define ZYNQMP_RESET_RPU_DBG0 73
#define ZYNQMP_RESET_DBG_LPD 74
#define ZYNQMP_RESET_DBG_FPD 75
#define ZYNQMP_RESET_APLL 76
#define ZYNQMP_RESET_DPLL 77
#define ZYNQMP_RESET_VPLL 78
#define ZYNQMP_RESET_IOPLL 79
#define ZYNQMP_RESET_RPLL 80
#define ZYNQMP_RESET_GPO3_PL_0 81
#define ZYNQMP_RESET_GPO3_PL_1 82
#define ZYNQMP_RESET_GPO3_PL_2 83
#define ZYNQMP_RESET_GPO3_PL_3 84
#define ZYNQMP_RESET_GPO3_PL_4 85
#define ZYNQMP_RESET_GPO3_PL_5 86
#define ZYNQMP_RESET_GPO3_PL_6 87
#define ZYNQMP_RESET_GPO3_PL_7 88
#define ZYNQMP_RESET_GPO3_PL_8 89
#define ZYNQMP_RESET_GPO3_PL_9 90
#define ZYNQMP_RESET_GPO3_PL_10 91
#define ZYNQMP_RESET_GPO3_PL_11 92
#define ZYNQMP_RESET_GPO3_PL_12 93
#define ZYNQMP_RESET_GPO3_PL_13 94
#define ZYNQMP_RESET_GPO3_PL_14 95
#define ZYNQMP_RESET_GPO3_PL_15 96
#define ZYNQMP_RESET_GPO3_PL_16 97
#define ZYNQMP_RESET_GPO3_PL_17 98
#define ZYNQMP_RESET_GPO3_PL_18 99
#define ZYNQMP_RESET_GPO3_PL_19 100
#define ZYNQMP_RESET_GPO3_PL_20 101
#define ZYNQMP_RESET_GPO3_PL_21 102
#define ZYNQMP_RESET_GPO3_PL_22 103
#define ZYNQMP_RESET_GPO3_PL_23 104
#define ZYNQMP_RESET_GPO3_PL_24 105
#define ZYNQMP_RESET_GPO3_PL_25 106
#define ZYNQMP_RESET_GPO3_PL_26 107
#define ZYNQMP_RESET_GPO3_PL_27 108
#define ZYNQMP_RESET_GPO3_PL_28 109
#define ZYNQMP_RESET_GPO3_PL_29 110
#define ZYNQMP_RESET_GPO3_PL_30 111
#define ZYNQMP_RESET_GPO3_PL_31 112
#define ZYNQMP_RESET_RPU_LS 113
#define ZYNQMP_RESET_PS_ONLY 114
#define ZYNQMP_RESET_PL 115
#define ZYNQMP_RESET_PS_PL0 116
#define ZYNQMP_RESET_PS_PL1 117
#define ZYNQMP_RESET_PS_PL2 118
#define ZYNQMP_RESET_PS_PL3 119
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/pcw.dtsi
+329
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@@ -0,0 +1,329 @@
&ps7_cortexa9_0 {
xlnx,rable = <0>;
xlnx,i-cache-size = <0x8000>;
xlnx,d-cache-line-size = <20>;
xlnx,i-cache-line-size = <20>;
xlnx,cpu-1x-clk-freq-hz = <111111115>;
xlnx,ip-name = "ps7_cortexa9";
xlnx,num-cores = <2>;
xlnx,d-cache-size = <0x8000>;
xlnx,cpu-clk-freq-hz = <666666687>;
bus-handle = <&amba>;
};
&ps7_cortexa9_1 {
xlnx,rable = <0>;
xlnx,i-cache-size = <0x8000>;
xlnx,d-cache-line-size = <20>;
xlnx,i-cache-line-size = <20>;
xlnx,cpu-1x-clk-freq-hz = <111111115>;
xlnx,ip-name = "ps7_cortexa9";
xlnx,d-cache-size = <0x8000>;
xlnx,cpu-clk-freq-hz = <666666687>;
bus-handle = <&amba>;
};
&amba {
ps7_pmu_0: ps7_pmu@f8891000 {
xlnx,rable = <0>;
xlnx,pmu1-s-axi-highaddr = <0xF8893FFF>;
compatible = "xlnx,ps7-pmu-1.00.a";
status = "okay";
xlnx,ip-name = "ps7_pmu";
reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
xlnx,pmu1-s-axi-baseaddr = <0xF8893000>;
xlnx,name = "ps7_pmu_0";
};
ps7_qspi_linear_0: ps7_qspi_linear@fc000000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-qspi-linear-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_qspi_linear";
reg = <0xfc000000 0x1000000>;
xlnx,name = "ps7_qspi_linear_0";
};
ps7_ddr_0: ps7_ddr@100000 {
compatible = "xlnx,ps7-ddr-1.00.a";
xlnx,s-axi-hp1-baseaddr = <0x0fffffff>;
xlnx,s-axi-hp3-baseaddr = <0x0fffffff>;
xlnx,rable = <0>;
xlnx,ip-name = "ps7_ddr";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
reg = <0x00100000 0x3ff00000>;
xlnx,s-axi-hp1-highaddr = <0x0fffffff>;
xlnx,s-axi-hp3-highaddr = <0x0fffffff>;
xlnx,s-axi-hp0-baseaddr = <0x0fffffff>;
xlnx,s-axi-hp2-baseaddr = <0x0fffffff>;
status = "okay";
xlnx,s-axi-hp0-highaddr = <0x0fffffff>;
xlnx,s-axi-hp2-highaddr = <0x0fffffff>;
xlnx,name = "ps7_ddr_0";
};
ps7_ocmc_0: ps7_ocmc@f800c000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-ocmc-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_ocmc";
reg = <0xf800c000 0x1000>;
xlnx,name = "ps7_ocmc_0";
};
ps7_gpv_0: ps7_gpv@f8900000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-gpv-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_gpv";
reg = <0xf8900000 0x100000>;
xlnx,name = "ps7_gpv_0";
};
ps7_scuc_0: ps7_scuc@f8f00000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-scuc-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_scuc";
reg = <0xf8f00000 0xfd>;
xlnx,name = "ps7_scuc_0";
};
ps7_iop_bus_config_0: ps7_iop_bus_config@e0200000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-iop-bus-config-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_iop_bus_config";
reg = <0xe0200000 0x1000>;
xlnx,name = "ps7_iop_bus_config_0";
};
ps7_ram_0: ps7_ram@0 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-ram-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_ram";
reg = <0x00000000 0x30000>;
xlnx,name = "ps7_ram_0";
};
ps7_ram_1: ps7_ram@ffff0000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-ram-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_ram";
reg = <0xffff0000 0xfe00>;
xlnx,name = "ps7_ram_1";
};
ps7_dma_ns: ps7_dma@f8004000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-dma-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_dma";
xlnx,is-secure;
reg = <0xf8004000 0x1000>;
xlnx,name = "ps7_dma_ns";
};
ps7_afi_0: ps7_afi@f8008000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-afi-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_afi";
reg = <0xf8008000 0x1000>;
xlnx,name = "ps7_afi_0";
};
ps7_afi_1: ps7_afi@f8009000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-afi-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_afi";
reg = <0xf8009000 0x1000>;
xlnx,name = "ps7_afi_1";
};
ps7_afi_2: ps7_afi@f800a000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-afi-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_afi";
reg = <0xf800a000 0x1000>;
xlnx,name = "ps7_afi_2";
};
ps7_afi_3: ps7_afi@f800b000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-afi-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_afi";
reg = <0xf800b000 0x1000>;
xlnx,name = "ps7_afi_3";
};
ps7_m_axi_gp0: ps7_m_axi_gp@40000000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-m-axi-gp-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_m_axi_gp";
reg = <0x40000000 0x40000000>;
xlnx,name = "ps7_m_axi_gp0";
};
};
&uart1 {
xlnx,rable = <0>;
status = "okay";
xlnx,clock-freq = <100000000>;
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,has-modem = <0>;
xlnx,ip-name = "ps7_uart";
cts-override;
port-number = <0>;
xlnx,uart-clk-freq-hz = <100000000>;
xlnx,name = "ps7_uart_1";
};
&qspi {
xlnx,qspi-clk-freq-hz = <142857132>;
xlnx,rable = <0>;
xlnx,bus-width = <2>;
xlnx,ip-name = "ps7_qspi";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
spi-rx-bus-width = <4>;
xlnx,connection-mode = <0>;
spi-tx-bus-width = <4>;
status = "okay";
qspi-fbclk = <0>;
xlnx,clock-freq = <142857132>;
xlnx,fb-clk = <1>;
xlnx,qspi-mode = <0>;
xlnx,name = "ps7_qspi_0";
xlnx,qspi-bus-width = <2>;
is-dual = <0>;
};
&gem0 {
xlnx,has-mdio = <1>;
phy-mode = "rgmii-id";
xlnx,enet-slcr-1000mbps-div0 = <8>;
xlnx,enet-slcr-10mbps-div0 = <8>;
xlnx,rable = <0>;
xlnx,enet-slcr-1000mbps-div1 = <1>;
xlnx,enet-slcr-10mbps-div1 = <50>;
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_ethernet";
xlnx,eth-mode = <1>;
xlnx,enet-clk-freq-hz = <125000000>;
xlnx,enet-slcr-100mbps-div0 = <8>;
xlnx,ptp-enet-clock = <0x69f6bcb>;
local-mac-address = [ 00 0a 23 00 00 00 ];
status = "okay";
xlnx,enet-slcr-100mbps-div1 = <5>;
xlnx,name = "ps7_ethernet_0";
};
&sdhci0 {
xlnx,rable = <0>;
xlnx,has-power = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_sdio";
xlnx,sdio-clk-freq-hz = <50000000>;
xlnx,has-wp = <1>;
xlnx,has-cd = <1>;
xlnx,name = "ps7_sd_0";
};
&gpio0 {
xlnx,rable = <0>;
xlnx,mio-gpio-mask = <0x5600>;
status = "okay";
gpio-mask-high = <0>;
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,emio-gpio-width = <33>;
xlnx,ip-name = "ps7_gpio";
gpio-mask-low = <22016>;
emio-gpio-width = <0x21>;
xlnx,name = "ps7_gpio_0";
};
&mc {
xlnx,rable = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ddr-clk-freq-hz = <533333374>;
xlnx,ip-name = "ps7_ddrc";
xlnx,has-ecc = <0>;
xlnx,name = "ps7_ddrc_0";
};
&devcfg {
xlnx,rable = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_dev_cfg";
xlnx,name = "ps7_dev_cfg_0";
};
&adc {
xlnx,rable = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_xadc";
xlnx,name = "ps7_xadc_0";
};
&coresight {
xlnx,rable = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_coresight_comp";
xlnx,name = "ps7_coresight_comp_0";
};
&global_timer {
xlnx,rable = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_globaltimer";
xlnx,name = "ps7_globaltimer_0";
};
&L2 {
xlnx,rable = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_pl310";
xlnx,name = "ps7_pl310_0";
};
&dmac_s {
xlnx,rable = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_dma";
xlnx,is-secure;
xlnx,name = "ps7_dma_s";
};
&intc {
xlnx,rable = <0>;
status = "okay";
xlnx,ppi-s-axi-baseaddr = <0xF8F01000>;
xlnx,irq-f2p-mode = "DIRECT";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_intc_dist";
xlnx,ppi-s-axi-highaddr = <0xF8F01FFF>;
xlnx,name = "ps7_intc_dist_0";
};
&scutimer {
xlnx,rable = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_scutimer";
xlnx,name = "ps7_scutimer_0";
};
&scuwdt {
xlnx,rable = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_scuwdt";
xlnx,name = "ps7_scuwdt_0";
};
&slcr {
xlnx,rable = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_slcr";
xlnx,name = "ps7_slcr_0";
};
&clkc {
fclk-enable = <0x1>;
ps-clk-frequency = <33333333>;
};
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/pl.dtsi
+21
View File
@@ -0,0 +1,21 @@
/ {
amba_pl: amba_pl {
ranges;
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
mydna_read_v1_0_0: mydna_read_v1_0@43c00000 {
xlnx,s00-axi-data-width = <32>;
xlnx,rable = <0>;
compatible = "xlnx,mydna-read-v1-0-1.0";
status = "okay";
clock-names = "s00_axi_aclk";
xlnx,s00-axi-addr-width = <4>;
xlnx,ip-name = "mydna_read_v1_0";
xlnx,edk-iptype = "PERIPHERAL";
reg = <0x43c00000 0x10000>;
clocks = <&clkc 15>;
xlnx,name = "mydna_read_v1_0_0";
};
};
};
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/ps7_init.c
+10066
View File
File diff suppressed because it is too large Load Diff
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/ps7_init.h
+117
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@@ -0,0 +1,117 @@
/******************************************************************************
*
* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 142857132
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/ps7_init_gpl.c
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2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/ps7_init_gpl.h
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/******************************************************************************
*
* Copyright (C) 2010-2020 <Xilinx Inc.>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>
*
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init_gpl.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 142857132
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/skeleton.dtsi
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/*
* Skeleton device tree; the bare minimum needed to boot; just include and
* add a compatible value. The bootloader will typically populate the memory
* node.
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
chosen { };
aliases { };
memory { device_type = "memory"; reg = <0 0>; };
};
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/system-top.dts
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/dts-v1/;
#include "zynq-7000.dtsi"
#include "pl.dtsi"
#include "pcw.dtsi"
/ {
device_id = "7z035";
slrcount = <1>;
ps7_ddr_0_memory: memory@00100000 {
compatible = "xlnx,ps7-ddr-1.00.a";
device_type = "memory";
reg = <0x00100000 0x3ff00000>;
};
ps7_ram_0_memory: memory@0 {
compatible = "xlnx,ps7-ram-1.00.a";
device_type = "memory";
reg = <0x0 0x30000>;
};
ps7_ram_1_memory: memory@ffff0000 {
compatible = "xlnx,ps7-ram-1.00.a";
device_type = "memory";
reg = <0xffff0000 0xfe00>;
};
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &uart1;
spi0 = &qspi;
serial1 = &coresight;
ethernet0 = &gem0;
};
cpus_a9: cpus-a9@0 {
compatible = "cpus,cluster";
address-map = <0xf0000000 &amba 0xf0000000 0x10000000>,
<0x00100000 &ps7_ddr_0_memory 0x00100000 0x3ff00000>,
<0x0 &ps7_ram_0_memory 0x0 0x30000>,
<0xffff0000 &ps7_ram_1_memory 0xffff0000 0xfe00>,
<0x43c00000 &mydna_read_v1_0_0 0x43c00000 0x10000>,
<0xf8008000 &ps7_afi_0 0xf8008000 0x1000>,
<0xf8009000 &ps7_afi_1 0xf8009000 0x1000>,
<0xf800a000 &ps7_afi_2 0xf800a000 0x1000>,
<0xf800b000 &ps7_afi_3 0xf800b000 0x1000>,
<0xf8800000 &coresight 0xf8800000 0x100000>,
<0xf8006000 &mc 0xf8006000 0x1000>,
<0xf8007000 &devcfg 0xf8007000 0x100>,
<0xf8004000 &ps7_dma_ns 0xf8004000 0x1000>,
<0xf8003000 &dmac_s 0xf8003000 0x1000>,
<0xe000b000 &gem0 0xe000b000 0x1000>,
<0xf8f00200 &global_timer 0xf8f00200 0x100>,
<0xe000a000 &gpio0 0xe000a000 0x1000>,
<0xf8900000 &ps7_gpv_0 0xf8900000 0x100000>,
<0xf8f01000 &intc 0xf8f01000 0x1000>,
<0xe0200000 &ps7_iop_bus_config_0 0xe0200000 0x1000>,
<0xf8f02000 &L2 0xf8f02000 0x1000>,
<0xf800c000 &ps7_ocmc_0 0xf800c000 0x1000>,
<0xf8891000 &ps7_pmu_0 0xf8891000 0x1000>,
<0xe000d000 &qspi 0xe000d000 0x1000>,
<0xfc000000 &ps7_qspi_linear_0 0xfc000000 0x1000000>,
<0xf8f00000 &ps7_scuc_0 0xf8f00000 0xfd>,
<0xf8f00600 &scutimer 0xf8f00600 0x20>,
<0xf8f00620 &scuwdt 0xf8f00620 0xe0>,
<0xe0100000 &sdhci0 0xe0100000 0x1000>,
<0xf8000000 &slcr 0xf8000000 0x1000>,
<0xe0001000 &uart1 0xe0001000 0x1000>,
<0xf8007100 &adc 0xf8007100 0x21>;
#ranges-address-cells = <0x1>;
#ranges-size-cells = <0x1>;
};
};
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/system_wrapper.bit
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2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/zynq-7000.dtsi
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2011-2022 Xilinx, Inc.
* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "xlnx,zynq-7000";
model = "Xilinx Zynq";
cpus_a9: cpus-a9@0 {
#address-cells = <1>;
#size-cells = <0>;
ps7_cortexa9_0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
clocks = <&clkc 3>;
clock-latency = <1000>;
cpu0-supply = <&regulator_vccpint>;
operating-points = <
666667 1000000
333334 1000000
>;
};
ps7_cortexa9_1: cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
clocks = <&clkc 3>;
};
};
fpga_full: fpga-full {
compatible = "fpga-region";
fpga-mgr = <&devcfg>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
pmu@f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 5 4>, <0 6 4>;
interrupt-parent = <&intc>;
reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
};
regulator_vccpint: fixedregulator {
compatible = "regulator-fixed";
regulator-name = "VCCPINT";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
};
replicator {
compatible = "arm,coresight-static-replicator";
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
out-ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator_out_port0: endpoint {
remote-endpoint = <&tpiu_in_port>;
};
};
port@1 {
reg = <1>;
replicator_out_port1: endpoint {
remote-endpoint = <&etb_in_port>;
};
};
};
in-ports {
/* replicator input port */
port {
replicator_in_port0: endpoint {
remote-endpoint = <&funnel_out_port>;
};
};
};
};
amba: axi {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
ranges;
adc: adc@f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0 7 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 12>;
};
can0: can@e0008000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <&clkc 19>, <&clkc 36>;
clock-names = "can_clk", "pclk";
reg = <0xe0008000 0x1000>;
interrupts = <0 28 4>;
interrupt-parent = <&intc>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can1: can@e0009000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <&clkc 20>, <&clkc 37>;
clock-names = "can_clk", "pclk";
reg = <0xe0009000 0x1000>;
interrupts = <0 51 4>;
interrupt-parent = <&intc>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
gpio0: gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <2>;
clocks = <&clkc 42>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <0 20 4>;
reg = <0xe000a000 0x1000>;
};
i2c0: i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <&clkc 38>;
clock-frequency = <400000>;
interrupt-parent = <&intc>;
interrupts = <0 25 4>;
reg = <0xe0004000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@e0005000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <&clkc 39>;
clock-frequency = <400000>;
interrupt-parent = <&intc>;
interrupts = <0 48 4>;
reg = <0xe0005000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
};
intc: interrupt-controller@f8f01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0xF8F01000 0x1000>,
<0xF8F00100 0x100>;
};
L2: cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xF8F02000 0x1000>;
interrupts = <0 2 4>;
arm,data-latency = <3 2 2>;
arm,tag-latency = <2 2 2>;
cache-unified;
cache-level = <2>;
};
mc: memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
};
ocm: sram@fffc0000 {
compatible = "mmio-sram";
reg = <0xfffc0000 0x10000>;
};
uart0: serial@e0000000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";
clocks = <&clkc 23>, <&clkc 40>;
clock-names = "uart_clk", "pclk";
reg = <0xE0000000 0x1000>;
interrupts = <0 27 4>;
interrupt-parent = <&intc>;
};
uart1: serial@e0001000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";
clocks = <&clkc 24>, <&clkc 41>;
clock-names = "uart_clk", "pclk";
reg = <0xE0001000 0x1000>;
interrupts = <0 50 4>;
interrupt-parent = <&intc>;
};
spi0: spi@e0006000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0006000 0x1000>;
status = "disabled";
interrupt-parent = <&intc>;
interrupts = <0 26 4>;
clocks = <&clkc 25>, <&clkc 34>;
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
};
spi1: spi@e0007000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
status = "disabled";
interrupt-parent = <&intc>;
interrupts = <0 49 4>;
clocks = <&clkc 26>, <&clkc 35>;
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
};
qspi: spi@e000d000 {
compatible = "xlnx,zynq-qspi-1.0";
reg = <0xe000d000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <0 19 4>;
clocks = <&clkc 10>, <&clkc 43>;
clock-names = "ref_clk", "pclk";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
gem0: ethernet@e000b000 {
compatible = "xlnx,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
status = "disabled";
interrupts = <0 22 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
};
gem1: ethernet@e000c000 {
compatible = "xlnx,zynq-gem", "cdns,gem";
reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0 45 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
};
smcc: memory-controller@e000e000 {
compatible = "arm,pl353-smc-r2p1", "arm,primecell";
reg = <0xe000e000 0x0001000>;
status = "disabled";
clock-names = "memclk", "apb_pclk";
clocks = <&clkc 11>, <&clkc 44>;
ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
#address-cells = <2>;
#size-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <0 18 4>;
nfc0: nand-controller@0,0 {
compatible = "arm,pl353-nand-r2p1";
reg = <0 0 0x1000000>;
status = "disabled";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
nor0: flash@1,0 {
status = "disabled";
compatible = "cfi-flash";
reg = <1 0 0x2000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
sdhci0: mmc@e0100000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin", "clk_ahb";
clocks = <&clkc 21>, <&clkc 32>;
interrupt-parent = <&intc>;
interrupts = <0 24 4>;
reg = <0xe0100000 0x1000>;
};
sdhci1: mmc@e0101000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin", "clk_ahb";
clocks = <&clkc 22>, <&clkc 33>;
interrupt-parent = <&intc>;
interrupts = <0 47 4>;
reg = <0xe0101000 0x1000>;
};
slcr: slcr@f8000000 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
reg = <0xF8000000 0x1000>;
ranges;
clkc: clkc@100 {
u-boot,dm-pre-reloc;
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
"dma", "usb0_aper", "usb1_aper", "gem0_aper",
"gem1_aper", "sdio0_aper", "sdio1_aper",
"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
"dbg_trc", "dbg_apb";
reg = <0x100 0x100>;
};
rstc: rstc@200 {
compatible = "xlnx,zynq-reset";
reg = <0x200 0x48>;
#reset-cells = <1>;
syscon = <&slcr>;
};
pinctrl0: pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <&slcr>;
};
};
dmac_s: dma-controller@f8003000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-parent = <&intc>;
/*
* interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
* "dma4", "dma5", "dma6", "dma7";
*/
interrupts = <0 13 4>,
<0 14 4>, <0 15 4>,
<0 16 4>, <0 17 4>,
<0 40 4>, <0 41 4>,
<0 42 4>, <0 43 4>;
#dma-cells = <1>;
clocks = <&clkc 27>;
clock-names = "apb_pclk";
};
devcfg: devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
reg = <0xf8007000 0x100>;
interrupt-parent = <&intc>;
interrupts = <0 8 4>;
clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
syscon = <&slcr>;
};
efuse: efuse@f800d000 {
compatible = "xlnx,zynq-efuse";
reg = <0xf800d000 0x20>;
};
global_timer: timer@f8f00200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xf8f00200 0x20>;
interrupts = <1 11 0x301>;
interrupt-parent = <&intc>;
clocks = <&clkc 4>;
};
ttc0: timer@f8001000 {
interrupt-parent = <&intc>;
interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
compatible = "cdns,ttc";
clocks = <&clkc 6>;
reg = <0xF8001000 0x1000>;
};
ttc1: timer@f8002000 {
interrupt-parent = <&intc>;
interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
compatible = "cdns,ttc";
clocks = <&clkc 6>;
reg = <0xF8002000 0x1000>;
};
scutimer: timer@f8f00600 {
interrupt-parent = <&intc>;
interrupts = <1 13 0x301>;
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clocks = <&clkc 4>;
};
scuwdt: scuwatchdog@f8f00620 {
interrupt-parent = <&intc>;
interrupts = <1 14 4>;
compatible = "xlnx,ps7-scuwdt-1.00.a";
reg = <0xf8f00620 0xe0>;
};
usb0: usb@e0002000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "disabled";
clocks = <&clkc 28>;
interrupt-parent = <&intc>;
interrupts = <0 21 4>;
reg = <0xe0002000 0x1000>;
phy_type = "ulpi";
};
usb1: usb@e0003000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "disabled";
clocks = <&clkc 29>;
interrupt-parent = <&intc>;
interrupts = <0 44 4>;
reg = <0xe0003000 0x1000>;
phy_type = "ulpi";
};
watchdog0: watchdog@f8005000 {
clocks = <&clkc 45>;
compatible = "cdns,wdt-r1p2";
interrupt-parent = <&intc>;
interrupts = <0 9 1>;
reg = <0xf8005000 0x1000>;
timeout-sec = <10>;
};
coresight: coresight@f8800000 {
compatible = "xlnx,ps7-coresight-comp-1.00.a";
status = "disabled";
reg = <0xf8800000 0x100000>;
};
etb@f8801000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0xf8801000 0x1000>;
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
in-ports {
port {
etb_in_port: endpoint {
remote-endpoint = <&replicator_out_port1>;
};
};
};
};
tpiu@f8803000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0xf8803000 0x1000>;
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
in-ports {
port {
tpiu_in_port: endpoint {
remote-endpoint = <&replicator_out_port0>;
};
};
};
};
funnel@f8804000 {
compatible = "arm,coresight-static-funnel", "arm,primecell";
reg = <0xf8804000 0x1000>;
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
/* funnel output ports */
out-ports {
port {
funnel_out_port: endpoint {
remote-endpoint =
<&replicator_in_port0>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
/* funnel input ports */
port@0 {
reg = <0>;
funnel0_in_port0: endpoint {
remote-endpoint = <&ptm0_out_port>;
};
};
port@1 {
reg = <1>;
funnel0_in_port1: endpoint {
remote-endpoint = <&ptm1_out_port>;
};
};
port@2 {
reg = <2>;
funnel0_in_port2: endpoint {
};
};
/* The other input ports are not connect to anything */
};
};
ptm@f889c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0xf889c000 0x1000>;
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
cpu = <&ps7_cortexa9_0>;
out-ports {
port {
ptm0_out_port: endpoint {
remote-endpoint = <&funnel0_in_port0>;
};
};
};
};
ptm@f889d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0xf889d000 0x1000>;
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
cpu = <&ps7_cortexa9_1>;
out-ports {
port {
ptm1_out_port: endpoint {
remote-endpoint = <&funnel0_in_port1>;
};
};
};
};
};
};
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/NewInstrCalBoard_bsp.spfm
+16
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@@ -0,0 +1,16 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<sdx:platform xmlns:sdx="http://www.xilinx.com/sdx" sdx:library="sdx" sdx:name="NewInstrCalBoard_bsp" sdx:vendor="xilinx.com" sdx:version="1.0">
<sdx:description/>
<sdx:systemConfigurations sdx:defaultConfiguration="NewInstrCalBoard_bsp">
<sdx:configuration sdx:defaultProcessorGroup="standalone_ps7_cortexa9_0" sdx:displayName="NewInstrCalBoard_bsp" sdx:name="NewInstrCalBoard_bsp" sdx:runtimes="cpp">
<sdx:description/>
<sdx:bootImages sdx:default="standard">
<sdx:image sdx:bif="" sdx:imageData="" sdx:name="standard" sdx:qemuArguments="qemu/pmu_args.txt:qemu/qemu_args.txt" sdx:readme=""/>
<sdx:image sdx:name="standalone_ps7_cortexa9_0" sdx:qemuArguments=":standalone_ps7_cortexa9_0/qemu/qemu_args.txt"/>
</sdx:bootImages>
<sdx:processorGroup sdx:cpuInstance="ps7_cortexa9_0" sdx:cpuType="cortex-a9" sdx:displayName="standalone_ps7_cortexa9_0" sdx:name="standalone_ps7_cortexa9_0">
<sdx:os sdx:bspConfig="standalone_ps7_cortexa9_0" sdx:displayName="standalone_ps7_cortexa9_0" sdx:name="standalone"/>
</sdx:processorGroup>
</sdx:configuration>
</sdx:systemConfigurations>
</sdx:platform>
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/qemu/qemu_args.txt
+51
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@@ -0,0 +1,51 @@
########################################################################
# This is file which used to generate QEMU(which emulates A9 core)
# commandline(start_qemu.sh script) which used in Zynq HW-EMU.
# This is a template file which is packaged in platform and it gets
# processed by Vitis tool to generate meaningful file.
#
# This file contains flag and value pairs and they must be seperated
# into two lines value followed by flag. Below are the common/mandated
# flag and value pairs used for emulating Zynq. User can add more
# commandline args to this file depends on requirements.
#
# For more details on the QEMU commandline, please refer to
# the QEMU user guide UG1169.
########################################################################
#
#
# selects emulated machine
-M
arm-generic-fdt-7series
#
#
# redirect the serial port to specified char dev (i.e stdio, tcp port, file etc)
-serial
/dev/null
-serial
mon:stdio
#
#
# Register writes to SLCR block, to set PLL and CLK_CTRL regs (required for linux)
-device
loader,addr=0xf8000008,data=0xDF0D,data-len=4
-device
loader,addr=0xf8000140,data=0x00500801,data-len=4
-device
loader,addr=0xf800012c,data=0x1ed044d,data-len=4
-device
loader,addr=0xf8000108,data=0x0001e008,data-len=4
-device
loader,addr=0xF800025C,data=0x00000005,data-len=4
-device
loader,addr=0xF8000240,data=0x00000000,data-len=4
#
#
# Boot device selection
-boot
mode=5
#
#
# Guest software to load during boot up
-kernel
<elf>
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/CMakeLists.txt
+33
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@@ -0,0 +1,33 @@
cmake_minimum_required(VERSION 3.15)
project(bsp)
find_package(common)
if(CMAKE_EXPORT_COMPILE_COMMANDS)
set(CMAKE_CXX_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_CXX_IMPLICIT_INCLUDE_DIRECTORIES})
set(CMAKE_C_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_C_IMPLICIT_INCLUDE_DIRECTORIES})
endif()
ADD_DEFINITIONS(-c ${proc_extra_compiler_flags})
include_directories(${CMAKE_BINARY_DIR}/include)
if (EXISTS ${metal_BINARY_DIR})
include_directories(${metal_BINARY_DIR}/lib/include)
endif()
set (BSP_LIBSRC_SUBDIRS libsrc standalone lwip213)
if (SUBDIR_LIST STREQUAL "ALL")
set (SUBDIR_LIST ${BSP_LIBSRC_SUBDIRS})
endif()
foreach(entry ${SUBDIR_LIST})
if(entry STREQUAL "libsrc")
set (path "${CMAKE_LIBRARY_PATH}/../libsrc")
else()
set (path "${CMAKE_LIBRARY_PATH}/../libsrc/${entry}/src")
endif()
if(EXISTS ${path})
add_subdirectory(${path})
endif()
endforeach()
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/Findcommon.cmake
+219
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@@ -0,0 +1,219 @@
# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
# SPDX-License-Identifier: MIT
option(NON_YOCTO "Non Yocto embeddedsw FLOW" OFF)
set(CMAKE_POLICY_DEFAULT_CMP0140 OLD)
set (CMAKE_INSTALL_LIBDIR "lib")
function (collector_create name base)
set_property (GLOBAL PROPERTY "COLLECT_${name}_LIST")
set_property (GLOBAL PROPERTY "COLLECT_${name}_BASE" "${base}")
endfunction (collector_create)
function (collector_list var name)
get_property (_list GLOBAL PROPERTY "COLLECT_${name}_LIST")
set (${var} "${_list}" PARENT_SCOPE)
endfunction (collector_list)
function (collector_base var name)
get_property (_base GLOBAL PROPERTY "COLLECT_${name}_BASE")
set (${var} "${_base}" PARENT_SCOPE)
endfunction (collector_base)
function (collect name)
collector_base (_base ${name})
string(COMPARE NOTEQUAL "${_base}" "" _is_rel)
set (_list)
foreach (s IN LISTS ARGN)
if (_is_rel)
get_filename_component (s "${s}" ABSOLUTE)
file (RELATIVE_PATH s "${_base}" "${s}")
endif (_is_rel)
list (APPEND _list "${s}")
endforeach ()
set_property (GLOBAL APPEND PROPERTY "COLLECT_${name}_LIST" "${_list}")
endfunction (collect)
function(LIST_INDEX index match PROP)
foreach (prop ${PROP})
if ("${prop}" STREQUAL "${match}")
set(index ${index} PARENT_SCOPE)
return()
endif()
MATH(EXPR index "${index}+1")
endforeach()
endfunction()
function(get_headers headers)
foreach(header ${_headers})
string(REPLACE "/" ";" PATH_LIST ${header})
list(GET PATH_LIST -1 header)
list(APPEND clean_headers ${CMAKE_INCLUDE_PATH}/${header})
set(clean_headers ${clean_headers} PARENT_SCOPE)
endforeach()
return(${clean_headers})
endfunction()
macro(subdirlist result curdir)
file(GLOB subdirs RELATIVE ${curdir} ${curdir}/*)
set(dirlist "")
foreach(subdir ${subdirs})
if(IS_DIRECTORY ${curdir}/${subdir})
list(APPEND dirlist ${subdir})
endif()
endforeach()
set(${result} ${dirlist})
endmacro()
function (linker_gen path)
if (NOT EXISTS "${CMAKE_SOURCE_DIR}/lscript.ld")
if (NOT DEFINED STACK_SIZE)
if("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "microblaze")
set(STACK_SIZE 0x400)
else()
set(STACK_SIZE 0x2000)
endif()
endif()
if (NOT DEFINED HEAP_SIZE)
if("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "microblaze")
set(HEAP_SIZE 0x400)
else()
set(HEAP_SIZE 0x2000)
endif()
endif()
SET(MEM_NODE_INSTANCES "${TOTAL_MEM_CONTROLLERS}" CACHE STRING "Memory Controller")
SET_PROPERTY(CACHE MEM_NODE_INSTANCES PROPERTY STRINGS "${TOTAL_MEM_CONTROLLERS}")
set(CUSTOM_LINKER_FILE "None" CACHE STRING "Custom Linker Script")
list(LENGTH MEM_NODE_INSTANCES _len)
if (${_len} EQUAL 1)
set(DDR ${MEM_NODE_INSTANCES})
endif()
if(("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortexa72")
OR ("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortexa78")
OR ("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortexa53")
OR ("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortexa53-32")
OR ("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "aarch64"))
configure_file(${path}/lscript_a53.ld.in ${CMAKE_SOURCE_DIR}/lscript.ld)
list(APPEND LINKER_FILE_PATH ${path}/lscript_a53.ld.in)
list(APPEND LINKER_FILE lscript_a53.ld.in)
endif()
if(("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "microblaze") OR
("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "microblazeel") OR
("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "plm_microblaze") OR
("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "pmu_microblaze"))
configure_file(${path}/lscript_mb.ld.in ${CMAKE_SOURCE_DIR}/lscript.ld)
list(APPEND LINKER_FILE_PATH ${path}/lscript_mb.ld.in)
list(APPEND LINKER_FILE lscript_mb.ld.in)
endif()
if(("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortexr5"))
if("${CMAKE_MACHINE}" STREQUAL "Versal")
configure_file(${path}/lscript_versal_r5.ld.in ${CMAKE_SOURCE_DIR}/lscript.ld)
list(APPEND LINKER_FILE_PATH ${path}/lscript_versal_r5.ld.in)
list(APPEND LINKER_FILE lscript_versal_r5.ld.in)
else()
configure_file(${path}/lscript_r5.ld.in ${CMAKE_SOURCE_DIR}/lscript.ld)
list(APPEND LINKER_FILE_PATH ${path}/lscript_r5.ld.in)
list(APPEND LINKER_FILE lscript_r5.ld.in)
endif()
endif()
if(("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortexr52"))
configure_file(${path}/lscript_versal_net_r5.ld.in ${CMAKE_SOURCE_DIR}/lscript.ld)
list(APPEND LINKER_FILE_PATH ${path}/lscript_versal_net_r5.ld.in)
list(APPEND LINKER_FILE lscript_versal_net_r5.ld.in)
endif()
if(("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortexa9"))
configure_file(${path}/lscript_a9.ld.in ${CMAKE_SOURCE_DIR}/lscript.ld)
list(APPEND LINKER_FILE_PATH ${path}/lscript_a9.ld.in)
list(APPEND LINKER_FILE lscript_a9.ld.in)
endif()
if (NOT "${CUSTOM_LINKER_FILE}" STREQUAL "None")
execute_process(COMMAND ${CMAKE_COMMAND} -E copy ${CUSTOM_LINKER_FILE} ${CMAKE_SOURCE_DIR}/)
endif()
if (${NON_YOCTO})
file (REMOVE_RECURSE ${path})
endif()
endif()
endfunction(linker_gen)
function(gen_exheader path drvname addr prefix)
string(TOUPPER ${drvname} DRVNAME)
set(ADDR_DEFINE "#define X${DRVNAME}_BASEADDRESS ${addr}U")
if (NOT ${prefix})
set(DRVNAME X${DRVNAME})
configure_file(${path}/example.h.in ${CMAKE_SOURCE_DIR}/${prefix}${drvname}_example.h)
else()
configure_file(${path}/example.h.in ${CMAKE_SOURCE_DIR}/${drvname}_example.h)
endif()
endfunction(gen_exheader)
function(gen_bspconfig)
execute_process(COMMAND lopper $ENV{SYSTEM_DTFILE} -- baremetal_bspconfig_xlnx ${ESW_MACHINE} ${CMAKE_SOURCE_DIR}
WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/common
RESULT_VARIABLE output)
execute_process(COMMAND ${CMAKE_COMMAND} -E copy ${CMAKE_SOURCE_DIR}/common/MemConfig.cmake ${CMAKE_SOURCE_DIR}/MemConfig.cmake)
endfunction(gen_bspconfig)
function(get_drvlist)
execute_process(COMMAND lopper $ENV{SYSTEM_DTFILE} -- baremetaldrvlist_xlnx ${ESW_MACHINE} ${CMAKE_SOURCE_DIR}/../../
WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}
RESULT_VARIABLE output)
endfunction(get_drvlist)
function(gen_drvconfig drvname)
if ("${drvname}" STREQUAL "uartps" OR
"${drvname}" STREQUAL "uartlite" OR
"${drvname}" STREQUAL "uartpsv")
execute_process(COMMAND lopper $ENV{SYSTEM_DTFILE} -- baremetalconfig_xlnx ${ESW_MACHINE} ${CMAKE_SOURCE_DIR}/${drvname}/src/ stdin
WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/${drvname}/src/
RESULT_VARIABLE output)
else()
execute_process(COMMAND lopper $ENV{SYSTEM_DTFILE} -- baremetalconfig_xlnx ${ESW_MACHINE} ${CMAKE_SOURCE_DIR}/${drvname}/src/
WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/${drvname}/src/
RESULT_VARIABLE output)
endif()
endfunction(gen_drvconfig)
function(gen_xparams)
execute_process(COMMAND lopper $ENV{SYSTEM_DTFILE} -- baremetal_xparameters_xlnx ${ESW_MACHINE} ${CMAKE_SOURCE_DIR}/../../
WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}
RESULT_VARIABLE output)
endfunction(gen_xparams)
function(gen_linker)
execute_process(COMMAND lopper $ENV{SYSTEM_DTFILE} -- baremetallinker_xlnx ${ESW_MACHINE} ${CMAKE_SOURCE_DIR}/
WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}
RESULT_VARIABLE output)
endfunction(gen_linker)
function(gen_libconfig)
execute_process(COMMAND lopper $ENV{SYSTEM_DTFILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${CMAKE_SOURCE_DIR}/ hwcmake_metadata ${CMAKE_SOURCE_DIR}/../../../../
WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}
RESULT_VARIABLE output)
endfunction(gen_libconfig)
macro(print_elf_size size_command app_name)
if(DEFINED ${size_command})
add_custom_command(
TARGET ${app_name}.elf POST_BUILD
COMMAND ${${size_command}} --format=berkeley ${app_name}.elf
COMMAND ${${size_command}} --format=berkeley ${app_name}.elf > ${CMAKE_BINARY_DIR}/${app_name}.elf.size
VERBATIM)
endif()
endmacro()
function(find_project_type src_ext PROJECT_TYPE)
set(cpp_extensions ".cpp;.cc;.CPP;.c++;.cxx")
foreach(extension ${cpp_extensions})
if (${extension} IN_LIST src_ext)
set(PROJECT_TYPE "c++" PARENT_SCOPE)
return()
endif()
endforeach()
set(PROJECT_TYPE "c" PARENT_SCOPE)
endfunction()
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/Xilinx.spec
+4
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@@ -0,0 +1,4 @@
# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
# SPDX-License-Identifier: MIT
*startfile:
%:if-exists(crti%O%s) %:if-exists(crtbegin%O%s) %:if-exists(crtinit%O%s)
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/app_list.yaml
+96
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@@ -0,0 +1,96 @@
ps7_cortexa9_0:
standalone:
zynq_fsbl:
description: First Stage Bootloader (FSBL) for Zynq. The FSBL configures the FPGA with HW bit stream (if it exists) and loads the Operating System (OS) Image or Standalone (SA) Image or 2nd Stage Boot Loader image from the non-volatile memory (NAND/NOR/QSPI) to RAM (DDR) and starts executing it. It supports multiple partitions, and each partition can be a code image or a bit stream.
depends_libs:
- xiltimer
- xilffs
- xilrsa
peripheral_tests:
description: Simple test routines for all peripherals in the hardware.
depends_libs:
- xiltimer
hello_world:
description: Let's say 'Hello World' in C.
depends_libs:
- xiltimer
zynq_dram_test:
description: This application runs out of OCM and performs memory tests on Zynq DRAM. For more information about the test, refer to ZYNQ_DRAM_DIAGNOSTICS_TEST.docx, in the src directory of the application.
depends_libs:
- xiltimer
empty_application:
description: A blank C project.
depends_libs:
- xiltimer
dhrystone:
description: Dhrystone synthetic benchmark program for baremetal environment.
depends_libs:
- xiltimer
lwip_tcp_perf_server:
description: The LwIP TCP Server application is used for creating TCP server using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10 and IPv6 link local address when ipv6_enable is true, with MAC address 00:0a:35:00:01:02. The application creates TCP server on board and starts listening for TCP client connections. It will display client connection info and also display interim and average TCP statistics for data transfer. This application handles only 1 client connection at a time.
depends_libs:
- lwip213
- xiltimer
lwip_udp_perf_server:
description: The LwIP UDP Perf Server application is used for creating UDP server and measure downlink performance using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10, with MAC address 00:0a:35:00:01:02. The application creates UDP server on board and starts listening for UDP client connections. It will display client connection information with interim and average UDP statistics for data transfer.
depends_libs:
- lwip213
- xiltimer
memory_tests:
description: This application tests Memory Regions present in the hardware.
depends_libs:
- xiltimer
lwip_tcp_perf_client:
description: The LwIP TCP Perf Client application is used for creating TCP client and measure TCP uplink performance using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10 and IPv6 link local address whenipv6_enable is true, with MAC address 00:0a:35:00:01:02. This application creates TCP client on board and make connection with TCP server running on host machine. It will display connection information along with interim and average TCP statistics for data transfer.
depends_libs:
- lwip213
- xiltimer
lwip_udp_perf_client:
description: The LwIP UDP Perf Client application is used for creating UDP client and measure UDP uplink performance using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10, with MAC address 00:0a:35:00:01:02. This application creates UDP client on board and make connection with UDP server running on host machine. It will display connection information along with interim and average UDP statistics for data transfer.
depends_libs:
- lwip213
- xiltimer
lwip_echo_server:
description: The lwIP Echo Server application provides a simple demonstration of how to use the light-weight IP stack (lwIP). This application sets up the board to use IP address 192.168.1.10 or IPv6 FE80:0:0:0:20A:35FF:FE00:102, with MAC address 00:0a:35:00:01:02. The server listens for input at port 7 and simply echoes back whatever data is sent to that port.
depends_libs:
- lwip213
- xiltimer
rsa_auth_app:
description: Used to RSA authenticate a user application.
depends_libs:
- xiltimer
- xilrsa
freertos:
empty_application:
description: A blank C project.
depends_libs:
- xiltimer
freertos_lwip_tcp_perf_server:
description: The FreeRTOS LwIP TCP Server application is used for creating TCP server using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10 and IPv6 link local address when ipv6_enable is true, with MAC address 00:0a:35:00:01:02. The application creates TCP server on board and starts listening for TCP client connections. It will display client connection info and also display interim and average TCP statistics for data transfer. This application handles only 1 client connection at a time.
depends_libs:
- lwip213
- xiltimer
freertos_lwip_udp_perf_server:
description: The FreeRTOS LwIP UDP Perf Server application is used for creating UDP server and measure downlink performance using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10, with MAC address 00:0a:35:00:01:02. The application creates UDP server on board and starts listening for UDP client connections. It will display client connection information with interim and average UDP statistics for data transfer..
depends_libs:
- lwip213
- xiltimer
freertos_lwip_echo_server:
description: The FreeRTOS lwIP Echo Server application provides a simple demonstration of how to use the light-weight IP stack (lwIP) with FreeRTOS. This application sets up the board to use IP address 192.168.1.10 or IPv6 address FE80:0:0:0:20A:35FF:FE00:102, with MAC address 00:0a:35:00:01:02. The server listens for input at port 7 and simply echoes back whatever data is sent to that port.
depends_libs:
- lwip213
- xiltimer
freertos_lwip_tcp_perf_client:
description: The FreeRTOS LwIP TCP Perf Client application is used for creating TCP client and measure TCP uplink performance using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10 and IPv6 link local address whenipv6_enable is true, with MAC address 00:0a:35:00:01:02. This application creates TCP client on board and make connection with TCP server running on host machine. It will display connection information along with interim and average TCP statistics for data transfer.
depends_libs:
- lwip213
- xiltimer
freertos_hello_world:
description: FreeRTOS Hello World application.
depends_libs:
- xiltimer
freertos_lwip_udp_perf_client:
description: The FreeRTOS LwIP UDP Perf Client application is used for creating UDP client and measure UDP uplink performance using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10, with MAC address 00:0a:35:00:01:02. This application creates UDP client on board and make connection with UDP server running on host machine. It will display connection information along with interim and average UDP statistics for data transfer.
depends_libs:
- lwip213
- xiltimer
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/bsp.yaml
+862
View File
@@ -0,0 +1,862 @@
sdt: hw_artifacts/ps7_cortexa9_0_baremetal.dts
family: Zynq
path: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp
os: standalone
os_info:
standalone:
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/lib/bsp/standalone_v9_0
os_config:
standalone:
standalone_stdin:
name: standalone_stdin
permission: read_write
type: string
value: ps7_uart_1
default: ps7_uart_1
options:
- None
- ps7_uart_1
- ps7_coresight_comp_0
description: stdin peripheral
standalone_stdout:
name: standalone_stdout
permission: read_write
type: string
value: ps7_uart_1
default: ps7_uart_1
options:
- None
- ps7_uart_1
- ps7_coresight_comp_0
description: stdout peripheral
toolchain_file: cortexa9_toolchain.cmake
specs_file: Xilinx.spec
proc: ps7_cortexa9_0
proc_config:
ps7_cortexa9_0:
proc_archiver:
name: proc_archiver
permission: readonly
type: string
value: arm-none-eabi-gcc-ar
default: arm-none-eabi-gcc-ar
options: []
description: Archiver
proc_assembler:
name: proc_assembler
permission: readonly
type: string
value: arm-none-eabi-gcc
default: arm-none-eabi-gcc
options: []
description: Assembler
proc_compiler:
name: proc_compiler
permission: readonly
type: string
value: arm-none-eabi-gcc
default: arm-none-eabi-gcc
options: []
description: Compiler
proc_compiler_flags:
name: proc_compiler_flags
permission: readonly
type: string
value: ' -O2 -DSDT -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard;-c'
default: ' -O2 -DSDT -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard;-c'
options: []
description: Compiler Flags
proc_extra_compiler_flags:
name: proc_extra_compiler_flags
permission: read_write
type: string
value: ' -g -Wall -Wextra -fno-tree-loop-distribute-patterns'
default: ' -g -Wall -Wextra -fno-tree-loop-distribute-patterns'
options: []
description: Extra Compiler Flags
template: empty_application
compiler_flags: ''
include_folder: include
lib_folder: lib
libsrc_folder: libsrc
drv_info:
mydna_read_v1_0_0: None
ps7_afi_0: None
ps7_afi_1: None
ps7_afi_2: None
ps7_afi_3: None
ps7_coresight_comp_0:
driver: coresightps_dcc
ip_name: ps7_coresight_comp
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/coresightps_dcc_v1_9
ps7_ddrc_0: None
ps7_dev_cfg_0:
driver: devcfg
ip_name: ps7_dev_cfg
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/devcfg_v3_8
ps7_dma_ns: None
ps7_dma_s:
driver: dmaps
ip_name: ps7_dma
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/dmaps_v2_9
ps7_ethernet_0:
driver: emacps
ip_name: ps7_ethernet
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/emacps_v3_19
ps7_globaltimer_0: None
ps7_gpio_0:
driver: gpiops
ip_name: ps7_gpio
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/gpiops_v3_12
ps7_gpv_0: None
ps7_intc_dist_0:
driver: scugic
ip_name: ps7_intc_dist
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/scugic_v5_2
ps7_iop_bus_config_0: None
ps7_ocmc_0: None
ps7_pl310_0: None
ps7_pmu_0: None
ps7_qspi_0:
driver: qspips
ip_name: ps7_qspi
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/qspips_v3_11
ps7_qspi_linear_0: None
ps7_scuc_0: None
ps7_scutimer_0:
driver: scutimer
ip_name: ps7_scutimer
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/scutimer_v2_5
ps7_scuwdt_0:
driver: scuwdt
ip_name: ps7_scuwdt
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/scuwdt_v2_5
ps7_sd_0:
driver: sdps
ip_name: ps7_sdio
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/sdps_v4_2
ps7_slcr_0: None
ps7_uart_1:
driver: uartps
ip_name: ps7_uart
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/uartps_v3_13
ps7_xadc_0:
driver: xadcps
ip_name: ps7_xadc
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/xadcps_v2_7
lib_info:
xiltimer:
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/lib/sw_services/xiltimer_v1_3
lwip213:
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/ThirdParty/sw_services/lwip213_v1_1
lib_config:
xiltimer:
XILTIMER_en_interval_timer:
name: XILTIMER_en_interval_timer
permission: read_write
type: boolean
value: 'true'
default: 'false'
options:
- 'true'
- 'false'
description: Enable Interval Timer
XILTIMER_sleep_timer:
name: XILTIMER_sleep_timer
permission: read_write
type: string
value: Default
default: ps7_scutimer_0
options:
- Default
- ps7_scutimer_0
description: This parameter is used to select specific timer for sleep functionality
XILTIMER_tick_timer:
name: XILTIMER_tick_timer
permission: read_write
type: string
value: ps7_scutimer_0
default: None
options:
- None
- ps7_scutimer_0
description: This parameter is used to select specific timer for tick functionality
lwip213:
lwip213_api_mode:
name: lwip213_api_mode
permission: read_write
type: string
value: RAW_API
default: RAW_API
options:
- RAW_API
- SOCKET_API
description: Mode of operation for lwIP (RAW API/Sockets API)
lwip213_arp_queueing:
name: lwip213_arp_queueing
permission: read_write
type: integer
value: '1'
default: '1'
options:
- '0'
- '1'
description: If enabled outgoing packets are queued during hardware address
resolution.
lwip213_arp_table_size:
name: lwip213_arp_table_size
permission: read_write
type: integer
value: '10'
default: '10'
options: []
description: Number of active hardware address IP address pairs cached.
lwip213_debug:
name: lwip213_debug
permission: read_write
type: boolean
value: 'false'
default: 'false'
options:
- 'true'
- 'false'
description: Turn on lwIP Debug?
lwip213_debug_options:
name: lwip213_debug_options
permission: read_write
type: boolean
value: 'true'
default: 'true'
options:
- 'true'
- 'false'
description: Turn on lwIP Debug?
lwip213_default_tcp_recvmbox_size:
name: lwip213_default_tcp_recvmbox_size
permission: read_write
type: integer
value: '200'
default: '200'
options: []
description: Size of TCP receive mbox queue.
lwip213_default_udp_recvmbox_size:
name: lwip213_default_udp_recvmbox_size
permission: read_write
type: integer
value: '100'
default: '100'
options: []
description: Size of UDP receive mbox queue.
lwip213_dhcp:
name: lwip213_dhcp
permission: read_write
type: boolean
value: 'false'
default: 'false'
options:
- 'true'
- 'false'
description: Is DHCP required?
lwip213_dhcp_does_arp_check:
name: lwip213_dhcp_does_arp_check
permission: read_write
type: boolean
value: 'false'
default: 'false'
options:
- 'true'
- 'false'
description: ARP check on offered addresses?
lwip213_dhcp_options:
name: lwip213_dhcp_options
permission: read_write
type: boolean
value: 'true'
default: 'true'
options:
- 'true'
- 'false'
description: Is DHCP required?
lwip213_icmp_debug:
name: lwip213_icmp_debug
permission: read_write
type: boolean
value: 'false'
default: 'false'
options:
- 'true'
- 'false'
description: Debug ICMP protocol
lwip213_icmp_options:
name: lwip213_icmp_options
permission: read_write
type: boolean
value: 'true'
default: 'true'
options:
- 'true'
- 'false'
description: ICMP Options
lwip213_icmp_ttl:
name: lwip213_icmp_ttl
permission: read_write
type: integer
value: '255'
default: '255'
options: []
description: ICMP TTL value
lwip213_igmp_debug:
name: lwip213_igmp_debug
permission: read_write
type: boolean
value: 'false'
default: 'false'
options:
- 'true'
- 'false'
description: Debug IGMP protocol
lwip213_igmp_options:
name: lwip213_igmp_options
permission: read_write
type: boolean
value: 'false'
default: 'false'
options:
- 'true'
- 'false'
description: IGMP Options
lwip213_ip_debug:
name: lwip213_ip_debug
permission: read_write
type: boolean
value: 'false'
default: 'false'
options:
- 'true'
- 'false'
description: Debug IP layer
lwip213_ip_default_ttl:
name: lwip213_ip_default_ttl
permission: read_write
type: integer
value: '255'
default: '255'
options: []
description: Global default TTL used by transport layers
lwip213_ip_forward:
name: lwip213_ip_forward
permission: read_write
type: integer
value: '0'
default: '0'
options:
- '0'
- '1'
description: Enable forwarding IP packets across network interfaces.
lwip213_ip_frag:
name: lwip213_ip_frag
permission: read_write
type: integer
value: '1'
default: '1'
options:
- '0'
- '1'
description: Fragment outgoing IP packets if their size exceeds MTU
lwip213_ip_frag_max_mtu:
name: lwip213_ip_frag_max_mtu
permission: read_write
type: integer
value: '1500'
default: '1500'
options: []
description: Assumed max MTU on any interface for IP frag buffer
lwip213_ip_options:
name: lwip213_ip_options
permission: read_write
type: integer
value: '0'
default: '0'
options:
- '0'
- '1'
description: 1 = IP options are allowed (but not parsed). 0 = packets with IP
options are dropped
lwip213_ip_reass_max_pbufs:
name: lwip213_ip_reass_max_pbufs
permission: read_write
type: integer
value: '128'
default: '128'
options: []
description: Reassembly PBUF Queue Length
lwip213_ip_reassembly:
name: lwip213_ip_reassembly
permission: read_write
type: integer
value: '1'
default: '1'
options:
- '0'
- '1'
description: Reassemble incoming fragmented IP packets
lwip213_ipv6_enable:
name: lwip213_ipv6_enable
permission: read_write
type: boolean
value: 'false'
default: 'false'
options:
- 'true'
- 'false'
description: IPv6 enable value
lwip213_ipv6_options:
name: lwip213_ipv6_options
permission: read_write
type: boolean
value: 'true'
default: 'true'
options:
- 'true'
- 'false'
description: IPv6 Options
lwip213_lwip_tcpip_core_locking_input:
name: lwip213_lwip_tcpip_core_locking_input
permission: read_write
type: boolean
value: 'false'
default: 'false'
options:
- 'true'
- 'false'
description: TCPIP input core locking
lwip213_mem_size:
name: lwip213_mem_size
permission: read_write
type: integer
value: '131072'
default: '131072'
options: []
description: Size of the heap memory (bytes).
lwip213_memp_n_pbuf:
name: lwip213_memp_n_pbuf
permission: read_write
type: integer
value: '16'
default: '16'
options: []
description: Number of memp struct pbufs. Set this high if application sends
lot of data out of ROM
lwip213_memp_n_sys_timeout:
name: lwip213_memp_n_sys_timeout
permission: read_write
type: integer
value: '8'
default: '8'
options: []
description: Number of simultaneously active timeouts
lwip213_memp_n_tcp_pcb:
name: lwip213_memp_n_tcp_pcb
permission: read_write
type: integer
value: '32'
default: '32'
options: []
description: Number of active TCP PCBs. One per active TCP connection
lwip213_memp_n_tcp_pcb_listen:
name: lwip213_memp_n_tcp_pcb_listen
permission: read_write
type: integer
value: '8'
default: '8'
options: []
description: Number of listening TCP connections
lwip213_memp_n_tcp_seg:
name: lwip213_memp_n_tcp_seg
permission: read_write
type: integer
value: '256'
default: '256'
options: []
description: Number of simultaneously queued TCP segments
lwip213_memp_n_udp_pcb:
name: lwip213_memp_n_udp_pcb
permission: read_write
type: integer
value: '4'
default: '4'
options: []
description: Number of active UDP PCBs. One per active UDP connection
lwip213_memp_num_api_msg:
name: lwip213_memp_num_api_msg
permission: read_write
type: integer
value: '16'
default: '16'
options: []
description: Number of api msg structures (socket mode only)
lwip213_memp_num_netbuf:
name: lwip213_memp_num_netbuf
permission: read_write
type: integer
value: '8'
default: '8'
options: []
description: Number of struct netbufs (socket mode only)
lwip213_memp_num_netconn:
name: lwip213_memp_num_netconn
permission: read_write
type: integer
value: '16'
default: '16'
options: []
description: Number of struct netconns (socket mode only)
lwip213_memp_num_tcpip_msg:
name: lwip213_memp_num_tcpip_msg
permission: read_write
type: integer
value: '64'
default: '64'
options: []
description: Number of tcpip msg structures (socket mode only)
lwip213_n_rx_coalesce:
name: lwip213_n_rx_coalesce
permission: read_write
type: integer
value: '1'
default: '1'
options: []
description: Setting for RX Interrupt coalescing.
lwip213_n_rx_descriptors:
name: lwip213_n_rx_descriptors
permission: read_write
type: integer
value: '64'
default: '64'
options: []
description: Number of RX Buffer Descriptors to be used in SDMA mode
lwip213_n_tx_coalesce:
name: lwip213_n_tx_coalesce
permission: read_write
type: integer
value: '1'
default: '1'
options: []
description: Setting for TX Interrupt coalescing.
lwip213_n_tx_descriptors:
name: lwip213_n_tx_descriptors
permission: read_write
type: integer
value: '64'
default: '64'
options: []
description: Number of TX Buffer Descriptors to be used in SDMA mode
lwip213_netif_debug:
name: lwip213_netif_debug
permission: read_write
type: boolean
value: 'false'
default: 'false'
options:
- 'true'
- 'false'
description: Debug network interface layer
lwip213_no_sys_no_timers:
name: lwip213_no_sys_no_timers
permission: read_write
type: boolean
value: 'true'
default: 'true'
options:
- 'true'
- 'false'
description: Drops support for sys_timeout when NO_SYS==1
lwip213_pbuf_debug:
name: lwip213_pbuf_debug
permission: read_write
type: boolean
value: 'false'
default: 'false'
options:
- 'true'
- 'false'
description: Debug pbuf layer
lwip213_pbuf_link_hlen:
name: lwip213_pbuf_link_hlen
permission: read_write
type: integer
value: '16'
default: '16'
options: []
description: Number of bytes that should be allocated for a link level header.
lwip213_pbuf_pool_bufsize:
name: lwip213_pbuf_pool_bufsize
permission: read_write
type: integer
value: '1700'
default: '1700'
options: []
description: Size of each pbuf in pbuf pool.
lwip213_pbuf_pool_size:
name: lwip213_pbuf_pool_size
permission: read_write
type: integer
value: '256'
default: '256'
options: []
description: Number of buffers in pbuf pool.
lwip213_socket_mode_thread_prio:
name: lwip213_socket_mode_thread_prio
permission: read_write
type: integer
value: '2'
default: '2'
options: []
description: Priority of threads in socket mode
lwip213_stats:
name: lwip213_stats
permission: read_write
type: boolean
value: 'false'
default: 'false'
options:
- 'true'
- 'false'
description: Turn on lwIP statistics?
lwip213_stats_options:
name: lwip213_stats_options
permission: read_write
type: boolean
value: 'true'
default: 'true'
options:
- 'true'
- 'false'
description: Turn on lwIP statistics?
lwip213_sys_debug:
name: lwip213_sys_debug
permission: read_write
type: boolean
value: 'false'
default: 'false'
options:
- 'true'
- 'false'
description: Debug sys arch layer
lwip213_tcp:
name: lwip213_tcp
permission: read_write
type: boolean
value: 'true'
default: 'true'
options:
- 'true'
- 'false'
description: Is TCP required ?
lwip213_tcp_debug:
name: lwip213_tcp_debug
permission: read_write
type: boolean
value: 'false'
default: 'false'
options:
- 'true'
- 'false'
description: Debug TCP layer
lwip213_tcp_keepalive:
name: lwip213_tcp_keepalive
permission: read_write
type: boolean
value: 'false'
default: 'false'
options:
- 'true'
- 'false'
description: Enable keepalive processing with default interval
lwip213_tcp_maxrtx:
name: lwip213_tcp_maxrtx
permission: read_write
type: integer
value: '12'
default: '12'
options: []
description: TCP Maximum retransmission value
lwip213_tcp_mss:
name: lwip213_tcp_mss
permission: read_write
type: integer
value: '1460'
default: '1460'
options: []
description: TCP Maximum segment size (bytes)
lwip213_tcp_options:
name: lwip213_tcp_options
permission: read_write
type: boolean
value: 'true'
default: 'true'
options:
- 'true'
- 'false'
description: Is TCP required ?
lwip213_tcp_queue_ooseq:
name: lwip213_tcp_queue_ooseq
permission: read_write
type: integer
value: '1'
default: '1'
options:
- '0'
- '1'
description: Should TCP queue segments arriving out of order. Set to 0 if your
device is low on memory
lwip213_tcp_snd_buf:
name: lwip213_tcp_snd_buf
permission: read_write
type: integer
value: '8192'
default: '8192'
options: []
description: TCP sender buffer space (bytes)
lwip213_tcp_synmaxrtx:
name: lwip213_tcp_synmaxrtx
permission: read_write
type: integer
value: '4'
default: '4'
options: []
description: TCP Maximum SYN retransmission value
lwip213_tcp_ttl:
name: lwip213_tcp_ttl
permission: read_write
type: integer
value: '255'
default: '255'
options: []
description: TCP TTL value
lwip213_tcp_wnd:
name: lwip213_tcp_wnd
permission: read_write
type: integer
value: '2048'
default: '2048'
options: []
description: TCP Window (bytes)
lwip213_tcpip_mbox_size:
name: lwip213_tcpip_mbox_size
permission: read_write
type: integer
value: '200'
default: '200'
options: []
description: Size of TCPIP mbox queue.
lwip213_temac_emac_number:
name: lwip213_temac_emac_number
permission: read_write
type: integer
value: '0'
default: '0'
options: []
description: Zynq Ethernet Interface number
lwip213_temac_phy_link_speed:
name: lwip213_temac_phy_link_speed
permission: read_write
type: string
value: CONFIG_LINKSPEED_AUTODETECT
default: CONFIG_LINKSPEED_AUTODETECT
options:
- CONFIG_LINKSPEED10
- CONFIG_LINKSPEED100
- CONFIG_LINKSPEED1000
- CONFIG_LINKSPEED_AUTODETECT
description: link speed as negotiated by the PHY
lwip213_temac_tcp_ip_rx_checksum_offload:
name: lwip213_temac_tcp_ip_rx_checksum_offload
permission: read_write
type: boolean
value: 'false'
default: 'false'
options:
- 'true'
- 'false'
description: Offload TCP and IP Receive checksum calculation (hardware support
required)
lwip213_temac_tcp_ip_tx_checksum_offload:
name: lwip213_temac_tcp_ip_tx_checksum_offload
permission: read_write
type: boolean
value: 'false'
default: 'false'
options:
- 'true'
- 'false'
description: Offload TCP and IP Transmit checksum calculation (hardware support
required)
lwip213_temac_tcp_rx_checksum_offload:
name: lwip213_temac_tcp_rx_checksum_offload
permission: read_write
type: boolean
value: 'false'
default: 'false'
options:
- 'true'
- 'false'
description: Offload TCP Receive checksum calculation (hardware support required)
lwip213_temac_tcp_tx_checksum_offload:
name: lwip213_temac_tcp_tx_checksum_offload
permission: read_write
type: boolean
value: 'false'
default: 'false'
options:
- 'true'
- 'false'
description: Offload TCP Transmit checksum calculation (hardware support required)
lwip213_temac_use_jumbo_frames:
name: lwip213_temac_use_jumbo_frames
permission: read_write
type: boolean
value: 'false'
default: 'false'
options:
- 'true'
- 'false'
description: use jumbo frames
lwip213_udp:
name: lwip213_udp
permission: read_write
type: boolean
value: 'true'
default: 'true'
options:
- 'true'
- 'false'
description: Is UDP required
lwip213_udp_debug:
name: lwip213_udp_debug
permission: read_write
type: boolean
value: 'false'
default: 'false'
options:
- 'true'
- 'false'
description: Debug UDP layer
lwip213_udp_options:
name: lwip213_udp_options
permission: read_write
type: boolean
value: 'true'
default: 'true'
options:
- 'true'
- 'false'
description: UDP Options
lwip213_udp_ttl:
name: lwip213_udp_ttl
permission: read_write
type: integer
value: '255'
default: '255'
options: []
description: UDP TTL value
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/cortexa9_toolchain.cmake
+26
View File
@@ -0,0 +1,26 @@
# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
# SPDX-License-Identifier: MIT
set( CMAKE_EXPORT_COMPILE_COMMANDS ON)
set( CMAKE_INSTALL_MESSAGE LAZY)
set( CMAKE_C_COMPILER arm-none-eabi-gcc )
set( CMAKE_CXX_COMPILER arm-none-eabi-g++ )
set( CMAKE_C_COMPILER_LAUNCHER )
set( CMAKE_CXX_COMPILER_LAUNCHER )
set( CMAKE_ASM_COMPILER arm-none-eabi-gcc )
set( CMAKE_AR arm-none-eabi-ar CACHE FILEPATH "Archiver" )
set( CMAKE_SIZE arm-none-eabi-size CACHE FILEPATH "Size" )
set( CMAKE_SYSTEM_PROCESSOR "cortexa9" )
set( CMAKE_MACHINE "Zynq" )
set( CMAKE_SYSTEM_NAME "Generic" )
set( CMAKE_SPECS_FILE "$ENV{ESW_REPO}/scripts/specs/arm/Xilinx.spec" CACHE STRING "Specs file path for using CMAKE toolchain files" )
set( TOOLCHAIN_C_FLAGS " -O2 -DSDT -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard" CACHE STRING "CFLAGS" )
set( TOOLCHAIN_CXX_FLAGS " -O2 -DSDT -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard" CACHE STRING "CXXFLAGS" )
set( TOOLCHAIN_ASM_FLAGS " -O2 -DSDT -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard" CACHE STRING "ASM FLAGS" )
set( TOOLCHAIN_DEP_FLAGS " -MMD -MP" CACHE STRING "Flags used by compiler to generate dependency files")
set( TOOLCHAIN_EXTRA_C_FLAGS " -g -Wall -Wextra -fno-tree-loop-distribute-patterns" CACHE STRING "Extra CFLAGS")
set( CMAKE_C_FLAGS_RELEASE "-DNDEBUG" CACHE STRING "Additional CFLAGS for release" )
set( CMAKE_CXX_FLAGS_RELEASE "-DNDEBUG" CACHE STRING "Additional CXXFLAGS for release" )
set( CMAKE_ASM_FLAGS_RELEASE "-DNDEBUG" CACHE STRING "Additional ASM FLAGS for release" )
set( CMAKE_C_FLAGS "${TOOLCHAIN_C_FLAGS} ${TOOLCHAIN_DEP_FLAGS} -specs=${CMAKE_SPECS_FILE} -I${CMAKE_INCLUDE_PATH}" CACHE STRING "CFLAGS")
set( CMAKE_CXX_FLAGS "${TOOLCHAIN_CXX_FLAGS} ${TOOLCHAIN_DEP_FLAGS} -specs=${CMAKE_SPECS_FILE} -I${CMAKE_INCLUDE_PATH}" CACHE STRING "CXXFLAGS")
set( CMAKE_ASM_FLAGS "${TOOLCHAIN_ASM_FLAGS} ${TOOLCHAIN_DEP_FLAGS} -specs=${CMAKE_SPECS_FILE} -I${CMAKE_INCLUDE_PATH}" CACHE STRING "ASMFLAGS")

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