149 lines
4.5 KiB
Verilog
149 lines
4.5 KiB
Verilog
module CPLD_Con (
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input i_sys_clk,
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input i_rst_n,
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input i_con_exec,
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input [23:0]i_freq_relay1,
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input [23:0]i_freq_relay2,
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input [23:0]i_freq_relay3,
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input [23:0]i_freq_relay4,
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// DC related Control
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input [23:0]i_DC_Con1,
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input [23:0]i_DC_Con2,
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input [23:0]i_DC_Con3,
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input [23:0]i_DC_Con4,
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output o_con_done,
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output [3:0]o_PMU_RC,
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output o_err
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);
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//Relay Reg
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reg [3:0] PMU_RC;
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//Condition Tester
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reg [15:0]en_t ;
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reg freq_t;
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reg dc_t;
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//Flags
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reg exec_flag;
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reg err_flag;
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reg [3:0]freq_slot_flag;
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reg [3:0]dc_slot_flag;
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reg done_flag;
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//Counter
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reg [15:0]delay_cnt;
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always @(posedge i_sys_clk) begin
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if (i_rst_n == 1'b0) begin
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delay_cnt <= 'd0;
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end
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else begin
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if (exec_flag == 1'b1) begin
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delay_cnt <= delay_cnt + 1'd1;
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end
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else begin
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delay_cnt <= 'd0;
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end
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end
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end
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//Function Identify
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always @(posedge i_sys_clk) begin
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if (i_rst_n == 1'b0) begin
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en_t <= 'd0;
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freq_t <= 'd0;
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dc_t <= 'd0;
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end
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else begin
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en_t <= (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) + (i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0] );
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freq_t <= i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0];
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dc_t <= i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0];
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end
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end
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// Main Controller Function
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always @(posedge i_sys_clk) begin
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if (i_rst_n == 1'b0) begin
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exec_flag <= 1'b0;
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err_flag <= 1'b0;
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freq_slot_flag <= 'd0;
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dc_slot_flag<='d0;
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done_flag <= 'd1;
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PMU_RC <= 4'b1111;
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end
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else begin
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if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin
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exec_flag <= 1'b1;
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done_flag <= 1'b0;
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//To DO: More Sanity Check?
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if (en_t > 'd1) begin //Only ONE Enable bit should be set!
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err_flag <= 1'b1;
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end
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else begin
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freq_slot_flag[0] <= i_freq_relay1[0];
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freq_slot_flag[1] <= i_freq_relay2[0];
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freq_slot_flag[2] <= i_freq_relay3[0];
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freq_slot_flag[3] <= i_freq_relay4[0];
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dc_slot_flag[0] <= i_DC_Con1[0];
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dc_slot_flag[1] <= i_DC_Con2[0];
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dc_slot_flag[2] <= i_DC_Con3[0];
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dc_slot_flag[3] <= i_DC_Con4[0];
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end
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end
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else if (exec_flag == 1'b1) begin
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if (freq_t == 1'b1) begin
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case (freq_slot_flag)
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4'b0001: begin
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PMU_RC <= 4'b1111;
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end
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4'b0010: begin
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PMU_RC <= 4'b1100;
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end
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4'b0100: begin
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PMU_RC <= 4'b1010;
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end
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4'b1000: begin
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PMU_RC <= 4'b0110;
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end
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default:begin
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PMU_RC <= 4'b0000;
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end
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endcase
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end
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else if (dc_t == 1'b1) begin
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case (dc_slot_flag)
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4'b0001: begin
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PMU_RC <= 4'b0001;
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end
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4'b0010: begin
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PMU_RC <= 4'b0010;
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end
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4'b0100: begin
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PMU_RC <= 4'b0100;
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end
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4'b1000: begin
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PMU_RC <= 4'b1000;
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end
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default:begin
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PMU_RC <= 4'b0000;
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end
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endcase
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end
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done_flag <= 1'b1;
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end
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end
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if (done_flag == 1) begin
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exec_flag <= 1'b0;
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end
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end
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assign o_con_done = done_flag;
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assign o_PMU_RC = PMU_RC;
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assign o_err = err_flag;
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endmodule |