Add Zynq test prj
This commit is contained in:
Jeremy Shen
+5
@@ -0,0 +1,5 @@
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<?xml version="1.0"?>
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<ProcessHandle Version="1" Minor="0">
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<Process Command="vivado" Owner="ly0kos" Host="mkb" Pid="127481" HostCore="32" HostMemory="131001520">
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</Process>
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</ProcessHandle>
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Executable
+270
@@ -0,0 +1,270 @@
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//
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// Vivado(TM)
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// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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//
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// GLOBAL VARIABLES
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var ISEShell = new ActiveXObject( "WScript.Shell" );
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var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
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var ISERunDir = "";
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var ISELogFile = "runme.log";
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var ISELogFileStr = null;
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var ISELogEcho = true;
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var ISEOldVersionWSH = false;
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// BOOTSTRAP
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ISEInit();
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//
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// ISE FUNCTIONS
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//
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function ISEInit() {
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// 1. RUN DIR setup
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var ISEScrFP = WScript.ScriptFullName;
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var ISEScrN = WScript.ScriptName;
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ISERunDir =
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ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
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// 2. LOG file setup
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ISELogFileStr = ISEOpenFile( ISELogFile );
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// 3. LOG echo?
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var ISEScriptArgs = WScript.Arguments;
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for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
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if ( ISEScriptArgs(loopi) == "-quiet" ) {
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ISELogEcho = false;
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break;
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}
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}
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// 4. WSH version check
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var ISEOptimalVersionWSH = 5.6;
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var ISECurrentVersionWSH = WScript.Version;
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if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
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ISEStdErr( "" );
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ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
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ISEOptimalVersionWSH + " or higher. Downloads" );
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ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
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ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
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ISEStdErr( "" );
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ISEOldVersionWSH = true;
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}
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}
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function ISEStep( ISEProg, ISEArgs ) {
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// CHECK for a STOP FILE
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if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
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ISEStdErr( "" );
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ISEStdErr( "*** Halting run - EA reset detected ***" );
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ISEStdErr( "" );
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WScript.Quit( 1 );
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}
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// WRITE STEP HEADER to LOG
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ISEStdOut( "" );
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ISEStdOut( "*** Running " + ISEProg );
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ISEStdOut( " with args " + ISEArgs );
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ISEStdOut( "" );
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// LAUNCH!
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var ISEExitCode = ISEExec( ISEProg, ISEArgs );
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if ( ISEExitCode != 0 ) {
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WScript.Quit( ISEExitCode );
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}
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}
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function ISEExec( ISEProg, ISEArgs ) {
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var ISEStep = ISEProg;
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if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
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ISEProg += ".bat";
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}
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var ISECmdLine = ISEProg + " " + ISEArgs;
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var ISEExitCode = 1;
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if ( ISEOldVersionWSH ) { // WSH 5.1
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// BEGIN file creation
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ISETouchFile( ISEStep, "begin" );
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// LAUNCH!
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ISELogFileStr.Close();
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ISECmdLine =
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"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
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ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
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ISELogFileStr = ISEOpenFile( ISELogFile );
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} else { // WSH 5.6
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// LAUNCH!
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ISEShell.CurrentDirectory = ISERunDir;
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// Redirect STDERR to STDOUT
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ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
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var ISEProcess = ISEShell.Exec( ISECmdLine );
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// BEGIN file creation
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var wbemFlagReturnImmediately = 0x10;
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var wbemFlagForwardOnly = 0x20;
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var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
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var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
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var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
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var NOC = 0;
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var NOLP = 0;
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var TPM = 0;
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var cpuInfos = new Enumerator(processor);
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for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
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var cpuInfo = cpuInfos.item();
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NOC += cpuInfo.NumberOfCores;
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NOLP += cpuInfo.NumberOfLogicalProcessors;
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}
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var csInfos = new Enumerator(computerSystem);
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for(;!csInfos.atEnd(); csInfos.moveNext()) {
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var csInfo = csInfos.item();
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TPM += csInfo.TotalPhysicalMemory;
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}
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var ISEHOSTCORE = NOLP
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var ISEMEMTOTAL = TPM
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var ISENetwork = WScript.CreateObject( "WScript.Network" );
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var ISEHost = ISENetwork.ComputerName;
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var ISEUser = ISENetwork.UserName;
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var ISEPid = ISEProcess.ProcessID;
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var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
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ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
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ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
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ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
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"\" Owner=\"" + ISEUser +
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"\" Host=\"" + ISEHost +
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"\" Pid=\"" + ISEPid +
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"\" HostCore=\"" + ISEHOSTCORE +
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"\" HostMemory=\"" + ISEMEMTOTAL +
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"\">" );
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ISEBeginFile.WriteLine( " </Process>" );
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ISEBeginFile.WriteLine( "</ProcessHandle>" );
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ISEBeginFile.Close();
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var ISEOutStr = ISEProcess.StdOut;
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var ISEErrStr = ISEProcess.StdErr;
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// WAIT for ISEStep to finish
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while ( ISEProcess.Status == 0 ) {
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// dump stdout then stderr - feels a little arbitrary
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while ( !ISEOutStr.AtEndOfStream ) {
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ISEStdOut( ISEOutStr.ReadLine() );
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}
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WScript.Sleep( 100 );
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}
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ISEExitCode = ISEProcess.ExitCode;
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}
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ISELogFileStr.Close();
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// END/ERROR file creation
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if ( ISEExitCode != 0 ) {
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ISETouchFile( ISEStep, "error" );
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} else {
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ISETouchFile( ISEStep, "end" );
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}
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return ISEExitCode;
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}
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//
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// UTILITIES
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//
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function ISEStdOut( ISELine ) {
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ISELogFileStr.WriteLine( ISELine );
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if ( ISELogEcho ) {
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WScript.StdOut.WriteLine( ISELine );
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}
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}
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function ISEStdErr( ISELine ) {
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ISELogFileStr.WriteLine( ISELine );
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if ( ISELogEcho ) {
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WScript.StdErr.WriteLine( ISELine );
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}
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}
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function ISETouchFile( ISERoot, ISEStatus ) {
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var ISETFile =
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ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
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ISETFile.Close();
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}
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function ISEOpenFile( ISEFilename ) {
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// This function has been updated to deal with a problem seen in CR #870871.
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// In that case the user runs a script that runs impl_1, and then turns around
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// and runs impl_1 -to_step write_bitstream. That second run takes place in
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// the same directory, which means we may hit some of the same files, and in
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// particular, we will open the runme.log file. Even though this script closes
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// the file (now), we see cases where a subsequent attempt to open the file
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// fails. Perhaps the OS is slow to release the lock, or the disk comes into
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// play? In any case, we try to work around this by first waiting if the file
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// is already there for an arbitrary 5 seconds. Then we use a try-catch block
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// and try to open the file 10 times with a one second delay after each attempt.
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// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
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// If there is an unrecognized exception when trying to open the file, we output
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// an error message and write details to an exception.log file.
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var ISEFullPath = ISERunDir + "/" + ISEFilename;
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if (ISEFileSys.FileExists(ISEFullPath)) {
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// File is already there. This could be a problem. Wait in case it is still in use.
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WScript.Sleep(5000);
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}
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var i;
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for (i = 0; i < 10; ++i) {
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try {
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return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
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} catch (exception) {
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var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
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if (error_code == 52) { // 52 is bad file name or number.
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// Wait a second and try again.
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WScript.Sleep(1000);
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continue;
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} else {
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WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
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var exceptionFilePath = ISERunDir + "/exception.log";
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if (!ISEFileSys.FileExists(exceptionFilePath)) {
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WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
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var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
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exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
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exceptionFile.WriteLine("\tException name: " + exception.name);
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exceptionFile.WriteLine("\tException error code: " + error_code);
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exceptionFile.WriteLine("\tException message: " + exception.message);
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exceptionFile.Close();
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}
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throw exception;
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}
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}
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}
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// If we reached this point, we failed to open the file after 10 attempts.
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// We need to error out.
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WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
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WScript.Quit(1);
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}
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Executable
+85
@@ -0,0 +1,85 @@
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#!/bin/sh
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#
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# Vivado(TM)
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# ISEWrap.sh: Vivado Runs Script for UNIX
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# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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#
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cmd_exists()
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{
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command -v "$1" >/dev/null 2>&1
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}
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HD_LOG=$1
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shift
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# CHECK for a STOP FILE
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if [ -f .stop.rst ]
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then
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echo "" >> $HD_LOG
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echo "*** Halting run - EA reset detected ***" >> $HD_LOG
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echo "" >> $HD_LOG
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exit 1
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fi
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ISE_STEP=$1
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shift
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# WRITE STEP HEADER to LOG
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echo "" >> $HD_LOG
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echo "*** Running $ISE_STEP" >> $HD_LOG
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echo " with args $@" >> $HD_LOG
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echo "" >> $HD_LOG
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# LAUNCH!
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$ISE_STEP "$@" >> $HD_LOG 2>&1 &
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# BEGIN file creation
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ISE_PID=$!
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HostNameFile=/proc/sys/kernel/hostname
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if cmd_exists hostname
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then
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ISE_HOST=$(hostname)
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elif cmd_exists uname
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then
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ISE_HOST=$(uname -n)
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elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
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then
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ISE_HOST=$(cat $HostNameFile)
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elif [ X != X$HOSTNAME ]
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then
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ISE_HOST=$HOSTNAME #bash
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else
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ISE_HOST=$HOST #csh
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fi
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ISE_USER=$USER
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ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
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ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
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ISE_BEGINFILE=.$ISE_STEP.begin.rst
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/bin/touch $ISE_BEGINFILE
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echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
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echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
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echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
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echo " </Process>" >> $ISE_BEGINFILE
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echo "</ProcessHandle>" >> $ISE_BEGINFILE
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# WAIT for ISEStep to finish
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wait $ISE_PID
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# END/ERROR file creation
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RETVAL=$?
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if [ $RETVAL -eq 0 ]
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then
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/bin/touch .$ISE_STEP.end.rst
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else
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/bin/touch .$ISE_STEP.error.rst
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fi
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exit $RETVAL
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+244
@@ -0,0 +1,244 @@
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#
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# Synthesis run script generated by Vivado
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#
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set TIME_start [clock seconds]
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namespace eval ::optrace {
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variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0.tcl"
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variable category "vivado_synth"
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}
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# Try to connect to running dispatch if we haven't done so already.
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# This code assumes that the Tcl interpreter is not using threads,
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# since the ::dispatch::connected variable isn't mutex protected.
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if {![info exists ::dispatch::connected]} {
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namespace eval ::dispatch {
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variable connected false
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if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
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set result "true"
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if {[catch {
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if {[lsearch -exact [package names] DispatchTcl] < 0} {
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set result [load librdi_cd_clienttcl[info sharedlibextension]]
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}
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if {$result eq "false"} {
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puts "WARNING: Could not load dispatch client library"
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}
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set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
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if { $connect_id eq "" } {
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puts "WARNING: Could not initialize dispatch client"
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} else {
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puts "INFO: Dispatch client connection id - $connect_id"
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set connected true
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}
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||||
} catch_res]} {
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puts "WARNING: failed to connect to dispatch server - $catch_res"
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}
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||||
}
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}
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||||
}
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if {$::dispatch::connected} {
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# Remove the dummy proc if it exists.
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if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
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rename ::OPTRACE ""
|
||||
}
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||||
proc ::OPTRACE { task action {tags {} } } {
|
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::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
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}
|
||||
# dispatch is generic. We specifically want to attach logging.
|
||||
::vitis_log::connect_client
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} else {
|
||||
# Add dummy proc if it doesn't exist.
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||||
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
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||||
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
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||||
# Do nothing
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc create_report { reportName command } {
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||||
set status "."
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||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
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eval file delete [glob $status]
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||||
}
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send_msg_id runtcl-4 info "Executing : $command"
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set retval [eval catch { $command } msg]
|
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if { $retval != 0 } {
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set fp [open $status w]
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close $fp
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send_msg_id runtcl-5 warning "$msg"
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||||
}
|
||||
}
|
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OPTRACE "NewExtInst_TOP_SPI_Con_0_0_synth_1" START { ROLLUP_AUTO }
|
||||
set_param chipscope.maxJobs 8
|
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set_msg_config -id {HDL-1065} -limit 10000
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
OPTRACE "Creating in-memory project" START { }
|
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create_project -in_memory -part xc7z035ffg676-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/wt [current_project]
|
||||
set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.xpr [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_repo_paths /home/ly0kos/work/Zynq/ip_repo [current_project]
|
||||
update_ip_catalog
|
||||
set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
OPTRACE "Creating in-memory project" END { }
|
||||
OPTRACE "Adding files" START { }
|
||||
read_ip -quiet /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0.xci
|
||||
|
||||
OPTRACE "Adding files" END { }
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
OPTRACE "Configure IP Cache" START { }
|
||||
|
||||
set cacheID [config_ip_cache -export -no_bom -dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1 -new_name NewExtInst_TOP_SPI_Con_0_0 -ip [get_ips NewExtInst_TOP_SPI_Con_0_0]]
|
||||
|
||||
OPTRACE "Configure IP Cache" END { }
|
||||
if { $cacheID == "" } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
OPTRACE "synth_design" START { }
|
||||
synth_design -top NewExtInst_TOP_SPI_Con_0_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context
|
||||
OPTRACE "synth_design" END { }
|
||||
OPTRACE "Write IP Cache" START { }
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix NewExtInst_TOP_SPI_Con_0_0_ NewExtInst_TOP_SPI_Con_0_0.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_0_stub.v
|
||||
lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_0_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_0_stub.vhdl
|
||||
lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_0_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_0_sim_netlist.v
|
||||
lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_0_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_0_sim_netlist.vhdl
|
||||
lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_0_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } {
|
||||
config_ip_cache -add -dcp NewExtInst_TOP_SPI_Con_0_0.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips NewExtInst_TOP_SPI_Con_0_0]
|
||||
}
|
||||
OPTRACE "Write IP Cache" END { }
|
||||
}
|
||||
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
|
||||
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
|
||||
}
|
||||
|
||||
rename_ref -prefix_all NewExtInst_TOP_SPI_Con_0_0_
|
||||
|
||||
OPTRACE "write_checkpoint" START { CHECKPOINT }
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef NewExtInst_TOP_SPI_Con_0_0.dcp
|
||||
OPTRACE "write_checkpoint" END { }
|
||||
OPTRACE "synth reports" START { REPORT }
|
||||
create_report "NewExtInst_TOP_SPI_Con_0_0_synth_1_synth_report_utilization_0" "report_utilization -file NewExtInst_TOP_SPI_Con_0_0_utilization_synth.rpt -pb NewExtInst_TOP_SPI_Con_0_0_utilization_synth.pb"
|
||||
OPTRACE "synth reports" END { }
|
||||
|
||||
if { [catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0.dcp
|
||||
} _RESULT ] } {
|
||||
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
if { [catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0.dcp
|
||||
} _RESULT ] } {
|
||||
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0_sim_netlist.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0_sim_netlist.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
close [open .end.used_ip_cache.rst w]
|
||||
}; # end if cacheID
|
||||
|
||||
if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_0]} {
|
||||
catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_0
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_0]} {
|
||||
catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/NewExtInst_TOP_SPI_Con_0_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_0
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
OPTRACE "NewExtInst_TOP_SPI_Con_0_0_synth_1" END { }
|
||||
+48
@@ -0,0 +1,48 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2023.2 (64-bit)
|
||||
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Fri May 15 15:32:50 2026
|
||||
# Process ID: 127523
|
||||
# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1
|
||||
# Command line: vivado -log NewExtInst_TOP_SPI_Con_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_0.tcl
|
||||
# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/NewExtInst_TOP_SPI_Con_0_0.vds
|
||||
# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1/vivado.jou
|
||||
# Running On: mkb, OS: Linux, CPU Frequency: 5101.762 MHz, CPU Physical cores: 32, Host memory: 134145 MB
|
||||
#-----------------------------------------------------------
|
||||
source NewExtInst_TOP_SPI_Con_0_0.tcl -notrace
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ly0kos/work/Zynq/ip_repo'.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'.
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: NewExtInst_TOP_SPI_Con_0_0
|
||||
Command: synth_design -top NewExtInst_TOP_SPI_Con_0_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035'
|
||||
INFO: [Device 21-403] Loading part xc7z035ffg676-2
|
||||
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
|
||||
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 127567
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2113.016 ; gain = 402.746 ; free physical = 40854 ; free virtual = 102695
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'NewExtInst_TOP_SPI_Con_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/synth/NewExtInst_TOP_SPI_Con_0_0.v:53]
|
||||
INFO: [Synth 8-6157] synthesizing module 'SPI_Con_v1_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:4]
|
||||
INFO: [Synth 8-6157] synthesizing module 'SPI_Con_v1_0_S00_AXI' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:4]
|
||||
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:291]
|
||||
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:656]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'SPI_Con_v1_0_S00_AXI' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:4]
|
||||
WARNING: [Synth 8-689] width (24) of port connection 'i_spi_data' does not match port width (1) of module 'SPI_Con_v1_0_S00_AXI' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:86]
|
||||
ERROR: [Synth 8-685] variable 'w_req' should not be used in output port connection [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:88]
|
||||
ERROR: [Synth 8-6156] failed synthesizing module 'SPI_Con_v1_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:4]
|
||||
ERROR: [Synth 8-6156] failed synthesizing module 'NewExtInst_TOP_SPI_Con_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/synth/NewExtInst_TOP_SPI_Con_0_0.v:53]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2191.984 ; gain = 481.715 ; free physical = 40761 ; free virtual = 102602
|
||||
---------------------------------------------------------------------------------
|
||||
RTL Elaboration failed
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
16 Infos, 1 Warnings, 0 Critical Warnings and 4 Errors encountered.
|
||||
synth_design failed
|
||||
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri May 15 15:32:58 2026...
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
#
|
||||
# Vivado(TM)
|
||||
# htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
# the basic steps of a run. Note that runme.bat/sh needs
|
||||
# to be invoked for Vivado to track run status.
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
vivado -log NewExtInst_TOP_SPI_Con_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_0.tcl
|
||||
+41
@@ -0,0 +1,41 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH variable below, before executing this script"
|
||||
exit
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;";
|
||||
} else {
|
||||
PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log NewExtInst_TOP_SPI_Con_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_0.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
+12
@@ -0,0 +1,12 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
set PATH=%SYSTEMROOT%\system32;%PATH%
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin
|
||||
else
|
||||
PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_0_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log NewExtInst_TOP_SPI_Con_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_0.tcl
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="ly0kos" Host="mkb" Pid="127663" HostCore="32" HostMemory="131001520">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
Executable
+270
@@ -0,0 +1,270 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
Executable
+85
@@ -0,0 +1,85 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
cmd_exists()
|
||||
{
|
||||
command -v "$1" >/dev/null 2>&1
|
||||
}
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
|
||||
HostNameFile=/proc/sys/kernel/hostname
|
||||
if cmd_exists hostname
|
||||
then
|
||||
ISE_HOST=$(hostname)
|
||||
elif cmd_exists uname
|
||||
then
|
||||
ISE_HOST=$(uname -n)
|
||||
elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
|
||||
then
|
||||
ISE_HOST=$(cat $HostNameFile)
|
||||
elif [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
+244
@@ -0,0 +1,244 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
namespace eval ::optrace {
|
||||
variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1.tcl"
|
||||
variable category "vivado_synth"
|
||||
}
|
||||
|
||||
# Try to connect to running dispatch if we haven't done so already.
|
||||
# This code assumes that the Tcl interpreter is not using threads,
|
||||
# since the ::dispatch::connected variable isn't mutex protected.
|
||||
if {![info exists ::dispatch::connected]} {
|
||||
namespace eval ::dispatch {
|
||||
variable connected false
|
||||
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
|
||||
set result "true"
|
||||
if {[catch {
|
||||
if {[lsearch -exact [package names] DispatchTcl] < 0} {
|
||||
set result [load librdi_cd_clienttcl[info sharedlibextension]]
|
||||
}
|
||||
if {$result eq "false"} {
|
||||
puts "WARNING: Could not load dispatch client library"
|
||||
}
|
||||
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
|
||||
if { $connect_id eq "" } {
|
||||
puts "WARNING: Could not initialize dispatch client"
|
||||
} else {
|
||||
puts "INFO: Dispatch client connection id - $connect_id"
|
||||
set connected true
|
||||
}
|
||||
} catch_res]} {
|
||||
puts "WARNING: failed to connect to dispatch server - $catch_res"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if {$::dispatch::connected} {
|
||||
# Remove the dummy proc if it exists.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
|
||||
rename ::OPTRACE ""
|
||||
}
|
||||
proc ::OPTRACE { task action {tags {} } } {
|
||||
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
|
||||
}
|
||||
# dispatch is generic. We specifically want to attach logging.
|
||||
::vitis_log::connect_client
|
||||
} else {
|
||||
# Add dummy proc if it doesn't exist.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
|
||||
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
|
||||
# Do nothing
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
OPTRACE "NewExtInst_TOP_SPI_Con_0_1_synth_1" START { ROLLUP_AUTO }
|
||||
set_param chipscope.maxJobs 8
|
||||
set_msg_config -id {HDL-1065} -limit 10000
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
OPTRACE "Creating in-memory project" START { }
|
||||
create_project -in_memory -part xc7z035ffg676-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/wt [current_project]
|
||||
set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.xpr [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_repo_paths /home/ly0kos/work/Zynq/ip_repo [current_project]
|
||||
update_ip_catalog
|
||||
set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
OPTRACE "Creating in-memory project" END { }
|
||||
OPTRACE "Adding files" START { }
|
||||
read_ip -quiet /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1.xci
|
||||
|
||||
OPTRACE "Adding files" END { }
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
OPTRACE "Configure IP Cache" START { }
|
||||
|
||||
set cacheID [config_ip_cache -export -no_bom -dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1 -new_name NewExtInst_TOP_SPI_Con_0_1 -ip [get_ips NewExtInst_TOP_SPI_Con_0_1]]
|
||||
|
||||
OPTRACE "Configure IP Cache" END { }
|
||||
if { $cacheID == "" } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
OPTRACE "synth_design" START { }
|
||||
synth_design -top NewExtInst_TOP_SPI_Con_0_1 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context
|
||||
OPTRACE "synth_design" END { }
|
||||
OPTRACE "Write IP Cache" START { }
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix NewExtInst_TOP_SPI_Con_0_1_ NewExtInst_TOP_SPI_Con_0_1.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_1_stub.v
|
||||
lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_1_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_1_stub.vhdl
|
||||
lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_1_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_1_sim_netlist.v
|
||||
lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_1_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_1_sim_netlist.vhdl
|
||||
lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_1_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } {
|
||||
config_ip_cache -add -dcp NewExtInst_TOP_SPI_Con_0_1.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips NewExtInst_TOP_SPI_Con_0_1]
|
||||
}
|
||||
OPTRACE "Write IP Cache" END { }
|
||||
}
|
||||
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
|
||||
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
|
||||
}
|
||||
|
||||
rename_ref -prefix_all NewExtInst_TOP_SPI_Con_0_1_
|
||||
|
||||
OPTRACE "write_checkpoint" START { CHECKPOINT }
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef NewExtInst_TOP_SPI_Con_0_1.dcp
|
||||
OPTRACE "write_checkpoint" END { }
|
||||
OPTRACE "synth reports" START { REPORT }
|
||||
create_report "NewExtInst_TOP_SPI_Con_0_1_synth_1_synth_report_utilization_0" "report_utilization -file NewExtInst_TOP_SPI_Con_0_1_utilization_synth.rpt -pb NewExtInst_TOP_SPI_Con_0_1_utilization_synth.pb"
|
||||
OPTRACE "synth reports" END { }
|
||||
|
||||
if { [catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1.dcp
|
||||
} _RESULT ] } {
|
||||
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
if { [catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1.dcp
|
||||
} _RESULT ] } {
|
||||
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1_sim_netlist.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1_sim_netlist.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
close [open .end.used_ip_cache.rst w]
|
||||
}; # end if cacheID
|
||||
|
||||
if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_1]} {
|
||||
catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_1
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_1]} {
|
||||
catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/NewExtInst_TOP_SPI_Con_0_1_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_1
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
OPTRACE "NewExtInst_TOP_SPI_Con_0_1_synth_1" END { }
|
||||
+48
@@ -0,0 +1,48 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2023.2 (64-bit)
|
||||
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Fri May 15 15:33:09 2026
|
||||
# Process ID: 127747
|
||||
# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1
|
||||
# Command line: vivado -log NewExtInst_TOP_SPI_Con_0_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_1.tcl
|
||||
# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/NewExtInst_TOP_SPI_Con_0_1.vds
|
||||
# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1/vivado.jou
|
||||
# Running On: mkb, OS: Linux, CPU Frequency: 5097.889 MHz, CPU Physical cores: 32, Host memory: 134145 MB
|
||||
#-----------------------------------------------------------
|
||||
source NewExtInst_TOP_SPI_Con_0_1.tcl -notrace
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ly0kos/work/Zynq/ip_repo'.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'.
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: NewExtInst_TOP_SPI_Con_0_1
|
||||
Command: synth_design -top NewExtInst_TOP_SPI_Con_0_1 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035'
|
||||
INFO: [Device 21-403] Loading part xc7z035ffg676-2
|
||||
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
|
||||
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 127781
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2112.500 ; gain = 402.746 ; free physical = 39342 ; free virtual = 101182
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'NewExtInst_TOP_SPI_Con_0_1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/synth/NewExtInst_TOP_SPI_Con_0_1.v:53]
|
||||
INFO: [Synth 8-6157] synthesizing module 'SPI_Con_v1_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:4]
|
||||
INFO: [Synth 8-6157] synthesizing module 'SPI_Con_v1_0_S00_AXI' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:4]
|
||||
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:291]
|
||||
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:656]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'SPI_Con_v1_0_S00_AXI' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:4]
|
||||
WARNING: [Synth 8-689] width (24) of port connection 'i_spi_data' does not match port width (1) of module 'SPI_Con_v1_0_S00_AXI' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:86]
|
||||
ERROR: [Synth 8-685] variable 'w_req' should not be used in output port connection [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:88]
|
||||
ERROR: [Synth 8-6156] failed synthesizing module 'SPI_Con_v1_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:4]
|
||||
ERROR: [Synth 8-6156] failed synthesizing module 'NewExtInst_TOP_SPI_Con_0_1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/synth/NewExtInst_TOP_SPI_Con_0_1.v:53]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2191.438 ; gain = 481.684 ; free physical = 39155 ; free virtual = 100996
|
||||
---------------------------------------------------------------------------------
|
||||
RTL Elaboration failed
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
16 Infos, 1 Warnings, 0 Critical Warnings and 4 Errors encountered.
|
||||
synth_design failed
|
||||
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri May 15 15:33:17 2026...
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
#
|
||||
# Vivado(TM)
|
||||
# htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
# the basic steps of a run. Note that runme.bat/sh needs
|
||||
# to be invoked for Vivado to track run status.
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
vivado -log NewExtInst_TOP_SPI_Con_0_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_1.tcl
|
||||
+41
@@ -0,0 +1,41 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH variable below, before executing this script"
|
||||
exit
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;";
|
||||
} else {
|
||||
PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log NewExtInst_TOP_SPI_Con_0_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_1.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
+12
@@ -0,0 +1,12 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
set PATH=%SYSTEMROOT%\system32;%PATH%
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin
|
||||
else
|
||||
PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_1_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log NewExtInst_TOP_SPI_Con_0_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_1.tcl
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="ly0kos" Host="mkb" Pid="127665" HostCore="32" HostMemory="131001520">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
Executable
+270
@@ -0,0 +1,270 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
Executable
+85
@@ -0,0 +1,85 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
cmd_exists()
|
||||
{
|
||||
command -v "$1" >/dev/null 2>&1
|
||||
}
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
|
||||
HostNameFile=/proc/sys/kernel/hostname
|
||||
if cmd_exists hostname
|
||||
then
|
||||
ISE_HOST=$(hostname)
|
||||
elif cmd_exists uname
|
||||
then
|
||||
ISE_HOST=$(uname -n)
|
||||
elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
|
||||
then
|
||||
ISE_HOST=$(cat $HostNameFile)
|
||||
elif [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
+244
@@ -0,0 +1,244 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
namespace eval ::optrace {
|
||||
variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2.tcl"
|
||||
variable category "vivado_synth"
|
||||
}
|
||||
|
||||
# Try to connect to running dispatch if we haven't done so already.
|
||||
# This code assumes that the Tcl interpreter is not using threads,
|
||||
# since the ::dispatch::connected variable isn't mutex protected.
|
||||
if {![info exists ::dispatch::connected]} {
|
||||
namespace eval ::dispatch {
|
||||
variable connected false
|
||||
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
|
||||
set result "true"
|
||||
if {[catch {
|
||||
if {[lsearch -exact [package names] DispatchTcl] < 0} {
|
||||
set result [load librdi_cd_clienttcl[info sharedlibextension]]
|
||||
}
|
||||
if {$result eq "false"} {
|
||||
puts "WARNING: Could not load dispatch client library"
|
||||
}
|
||||
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
|
||||
if { $connect_id eq "" } {
|
||||
puts "WARNING: Could not initialize dispatch client"
|
||||
} else {
|
||||
puts "INFO: Dispatch client connection id - $connect_id"
|
||||
set connected true
|
||||
}
|
||||
} catch_res]} {
|
||||
puts "WARNING: failed to connect to dispatch server - $catch_res"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if {$::dispatch::connected} {
|
||||
# Remove the dummy proc if it exists.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
|
||||
rename ::OPTRACE ""
|
||||
}
|
||||
proc ::OPTRACE { task action {tags {} } } {
|
||||
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
|
||||
}
|
||||
# dispatch is generic. We specifically want to attach logging.
|
||||
::vitis_log::connect_client
|
||||
} else {
|
||||
# Add dummy proc if it doesn't exist.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
|
||||
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
|
||||
# Do nothing
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
OPTRACE "NewExtInst_TOP_SPI_Con_0_2_synth_1" START { ROLLUP_AUTO }
|
||||
set_param chipscope.maxJobs 8
|
||||
set_msg_config -id {HDL-1065} -limit 10000
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
OPTRACE "Creating in-memory project" START { }
|
||||
create_project -in_memory -part xc7z035ffg676-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/wt [current_project]
|
||||
set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.xpr [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_repo_paths /home/ly0kos/work/Zynq/ip_repo [current_project]
|
||||
update_ip_catalog
|
||||
set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
OPTRACE "Creating in-memory project" END { }
|
||||
OPTRACE "Adding files" START { }
|
||||
read_ip -quiet /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2.xci
|
||||
|
||||
OPTRACE "Adding files" END { }
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
OPTRACE "Configure IP Cache" START { }
|
||||
|
||||
set cacheID [config_ip_cache -export -no_bom -dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1 -new_name NewExtInst_TOP_SPI_Con_0_2 -ip [get_ips NewExtInst_TOP_SPI_Con_0_2]]
|
||||
|
||||
OPTRACE "Configure IP Cache" END { }
|
||||
if { $cacheID == "" } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
OPTRACE "synth_design" START { }
|
||||
synth_design -top NewExtInst_TOP_SPI_Con_0_2 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context
|
||||
OPTRACE "synth_design" END { }
|
||||
OPTRACE "Write IP Cache" START { }
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix NewExtInst_TOP_SPI_Con_0_2_ NewExtInst_TOP_SPI_Con_0_2.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_2_stub.v
|
||||
lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_2_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_2_stub.vhdl
|
||||
lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_2_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_2_sim_netlist.v
|
||||
lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_2_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_SPI_Con_0_2_sim_netlist.vhdl
|
||||
lappend ipCachedFiles NewExtInst_TOP_SPI_Con_0_2_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } {
|
||||
config_ip_cache -add -dcp NewExtInst_TOP_SPI_Con_0_2.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips NewExtInst_TOP_SPI_Con_0_2]
|
||||
}
|
||||
OPTRACE "Write IP Cache" END { }
|
||||
}
|
||||
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
|
||||
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
|
||||
}
|
||||
|
||||
rename_ref -prefix_all NewExtInst_TOP_SPI_Con_0_2_
|
||||
|
||||
OPTRACE "write_checkpoint" START { CHECKPOINT }
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef NewExtInst_TOP_SPI_Con_0_2.dcp
|
||||
OPTRACE "write_checkpoint" END { }
|
||||
OPTRACE "synth reports" START { REPORT }
|
||||
create_report "NewExtInst_TOP_SPI_Con_0_2_synth_1_synth_report_utilization_0" "report_utilization -file NewExtInst_TOP_SPI_Con_0_2_utilization_synth.rpt -pb NewExtInst_TOP_SPI_Con_0_2_utilization_synth.pb"
|
||||
OPTRACE "synth reports" END { }
|
||||
|
||||
if { [catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2.dcp
|
||||
} _RESULT ] } {
|
||||
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
if { [catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2.dcp
|
||||
} _RESULT ] } {
|
||||
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2_sim_netlist.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2_sim_netlist.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
close [open .end.used_ip_cache.rst w]
|
||||
}; # end if cacheID
|
||||
|
||||
if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_2]} {
|
||||
catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_2
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_2]} {
|
||||
catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/NewExtInst_TOP_SPI_Con_0_2_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_SPI_Con_0_2
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
OPTRACE "NewExtInst_TOP_SPI_Con_0_2_synth_1" END { }
|
||||
+48
@@ -0,0 +1,48 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2023.2 (64-bit)
|
||||
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Fri May 15 15:33:09 2026
|
||||
# Process ID: 127748
|
||||
# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1
|
||||
# Command line: vivado -log NewExtInst_TOP_SPI_Con_0_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_2.tcl
|
||||
# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/NewExtInst_TOP_SPI_Con_0_2.vds
|
||||
# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1/vivado.jou
|
||||
# Running On: mkb, OS: Linux, CPU Frequency: 5087.536 MHz, CPU Physical cores: 32, Host memory: 134145 MB
|
||||
#-----------------------------------------------------------
|
||||
source NewExtInst_TOP_SPI_Con_0_2.tcl -notrace
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ly0kos/work/Zynq/ip_repo'.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'.
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: NewExtInst_TOP_SPI_Con_0_2
|
||||
Command: synth_design -top NewExtInst_TOP_SPI_Con_0_2 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035'
|
||||
INFO: [Device 21-403] Loading part xc7z035ffg676-2
|
||||
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
|
||||
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 127773
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2113.031 ; gain = 404.715 ; free physical = 39342 ; free virtual = 101182
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'NewExtInst_TOP_SPI_Con_0_2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/synth/NewExtInst_TOP_SPI_Con_0_2.v:53]
|
||||
INFO: [Synth 8-6157] synthesizing module 'SPI_Con_v1_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:4]
|
||||
INFO: [Synth 8-6157] synthesizing module 'SPI_Con_v1_0_S00_AXI' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:4]
|
||||
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:291]
|
||||
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:656]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'SPI_Con_v1_0_S00_AXI' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v:4]
|
||||
WARNING: [Synth 8-689] width (24) of port connection 'i_spi_data' does not match port width (1) of module 'SPI_Con_v1_0_S00_AXI' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:86]
|
||||
ERROR: [Synth 8-685] variable 'w_req' should not be used in output port connection [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:88]
|
||||
ERROR: [Synth 8-6156] failed synthesizing module 'SPI_Con_v1_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v:4]
|
||||
ERROR: [Synth 8-6156] failed synthesizing module 'NewExtInst_TOP_SPI_Con_0_2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/synth/NewExtInst_TOP_SPI_Con_0_2.v:53]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2192.000 ; gain = 483.684 ; free physical = 39155 ; free virtual = 100996
|
||||
---------------------------------------------------------------------------------
|
||||
RTL Elaboration failed
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
16 Infos, 1 Warnings, 0 Critical Warnings and 4 Errors encountered.
|
||||
synth_design failed
|
||||
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri May 15 15:33:17 2026...
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
#
|
||||
# Vivado(TM)
|
||||
# htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
# the basic steps of a run. Note that runme.bat/sh needs
|
||||
# to be invoked for Vivado to track run status.
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
vivado -log NewExtInst_TOP_SPI_Con_0_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_2.tcl
|
||||
+41
@@ -0,0 +1,41 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH variable below, before executing this script"
|
||||
exit
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;";
|
||||
} else {
|
||||
PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log NewExtInst_TOP_SPI_Con_0_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_2.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
+12
@@ -0,0 +1,12 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
set PATH=%SYSTEMROOT%\system32;%PATH%
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin
|
||||
else
|
||||
PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_SPI_Con_0_2_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log NewExtInst_TOP_SPI_Con_0_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_SPI_Con_0_2.tcl
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="ly0kos" Host="mkb" Pid="123147" HostCore="32" HostMemory="131001520">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
Executable
+270
@@ -0,0 +1,270 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
Executable
+85
@@ -0,0 +1,85 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
cmd_exists()
|
||||
{
|
||||
command -v "$1" >/dev/null 2>&1
|
||||
}
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
|
||||
HostNameFile=/proc/sys/kernel/hostname
|
||||
if cmd_exists hostname
|
||||
then
|
||||
ISE_HOST=$(hostname)
|
||||
elif cmd_exists uname
|
||||
then
|
||||
ISE_HOST=$(uname -n)
|
||||
elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
|
||||
then
|
||||
ISE_HOST=$(cat $HostNameFile)
|
||||
elif [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
BIN
Binary file not shown.
+248
@@ -0,0 +1,248 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
namespace eval ::optrace {
|
||||
variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0.tcl"
|
||||
variable category "vivado_synth"
|
||||
}
|
||||
|
||||
# Try to connect to running dispatch if we haven't done so already.
|
||||
# This code assumes that the Tcl interpreter is not using threads,
|
||||
# since the ::dispatch::connected variable isn't mutex protected.
|
||||
if {![info exists ::dispatch::connected]} {
|
||||
namespace eval ::dispatch {
|
||||
variable connected false
|
||||
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
|
||||
set result "true"
|
||||
if {[catch {
|
||||
if {[lsearch -exact [package names] DispatchTcl] < 0} {
|
||||
set result [load librdi_cd_clienttcl[info sharedlibextension]]
|
||||
}
|
||||
if {$result eq "false"} {
|
||||
puts "WARNING: Could not load dispatch client library"
|
||||
}
|
||||
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
|
||||
if { $connect_id eq "" } {
|
||||
puts "WARNING: Could not initialize dispatch client"
|
||||
} else {
|
||||
puts "INFO: Dispatch client connection id - $connect_id"
|
||||
set connected true
|
||||
}
|
||||
} catch_res]} {
|
||||
puts "WARNING: failed to connect to dispatch server - $catch_res"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if {$::dispatch::connected} {
|
||||
# Remove the dummy proc if it exists.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
|
||||
rename ::OPTRACE ""
|
||||
}
|
||||
proc ::OPTRACE { task action {tags {} } } {
|
||||
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
|
||||
}
|
||||
# dispatch is generic. We specifically want to attach logging.
|
||||
::vitis_log::connect_client
|
||||
} else {
|
||||
# Add dummy proc if it doesn't exist.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
|
||||
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
|
||||
# Do nothing
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
OPTRACE "NewExtInst_TOP_clk_wiz_0_0_synth_1" START { ROLLUP_AUTO }
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
OPTRACE "Creating in-memory project" START { }
|
||||
create_project -in_memory -part xc7z035ffg676-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/wt [current_project]
|
||||
set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.xpr [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_repo_paths /home/ly0kos/work/Zynq/ip_repo [current_project]
|
||||
update_ip_catalog
|
||||
set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
OPTRACE "Creating in-memory project" END { }
|
||||
OPTRACE "Adding files" START { }
|
||||
read_ip -quiet /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xci
|
||||
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_board.xdc]
|
||||
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xdc]
|
||||
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_ooc.xdc]
|
||||
|
||||
OPTRACE "Adding files" END { }
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
OPTRACE "Configure IP Cache" START { }
|
||||
|
||||
set cacheID [config_ip_cache -export -no_bom -dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1 -new_name NewExtInst_TOP_clk_wiz_0_0 -ip [get_ips NewExtInst_TOP_clk_wiz_0_0]]
|
||||
|
||||
OPTRACE "Configure IP Cache" END { }
|
||||
if { $cacheID == "" } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
OPTRACE "synth_design" START { }
|
||||
synth_design -top NewExtInst_TOP_clk_wiz_0_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context
|
||||
OPTRACE "synth_design" END { }
|
||||
OPTRACE "Write IP Cache" START { }
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix NewExtInst_TOP_clk_wiz_0_0_ NewExtInst_TOP_clk_wiz_0_0.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_clk_wiz_0_0_stub.v
|
||||
lappend ipCachedFiles NewExtInst_TOP_clk_wiz_0_0_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_clk_wiz_0_0_stub.vhdl
|
||||
lappend ipCachedFiles NewExtInst_TOP_clk_wiz_0_0_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_clk_wiz_0_0_sim_netlist.v
|
||||
lappend ipCachedFiles NewExtInst_TOP_clk_wiz_0_0_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_clk_wiz_0_0_sim_netlist.vhdl
|
||||
lappend ipCachedFiles NewExtInst_TOP_clk_wiz_0_0_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } {
|
||||
config_ip_cache -add -dcp NewExtInst_TOP_clk_wiz_0_0.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips NewExtInst_TOP_clk_wiz_0_0]
|
||||
}
|
||||
OPTRACE "Write IP Cache" END { }
|
||||
}
|
||||
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
|
||||
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
|
||||
}
|
||||
|
||||
rename_ref -prefix_all NewExtInst_TOP_clk_wiz_0_0_
|
||||
|
||||
OPTRACE "write_checkpoint" START { CHECKPOINT }
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef NewExtInst_TOP_clk_wiz_0_0.dcp
|
||||
OPTRACE "write_checkpoint" END { }
|
||||
OPTRACE "synth reports" START { REPORT }
|
||||
create_report "NewExtInst_TOP_clk_wiz_0_0_synth_1_synth_report_utilization_0" "report_utilization -file NewExtInst_TOP_clk_wiz_0_0_utilization_synth.rpt -pb NewExtInst_TOP_clk_wiz_0_0_utilization_synth.pb"
|
||||
OPTRACE "synth reports" END { }
|
||||
|
||||
if { [catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.dcp
|
||||
} _RESULT ] } {
|
||||
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
if { [catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.dcp
|
||||
} _RESULT ] } {
|
||||
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
close [open .end.used_ip_cache.rst w]
|
||||
}; # end if cacheID
|
||||
|
||||
if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_clk_wiz_0_0]} {
|
||||
catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_clk_wiz_0_0
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_clk_wiz_0_0]} {
|
||||
catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_clk_wiz_0_0
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
OPTRACE "NewExtInst_TOP_clk_wiz_0_0_synth_1" END { }
|
||||
+247
@@ -0,0 +1,247 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2023.2 (64-bit)
|
||||
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Fri May 15 15:26:41 2026
|
||||
# Process ID: 123454
|
||||
# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1
|
||||
# Command line: vivado -log NewExtInst_TOP_clk_wiz_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_clk_wiz_0_0.tcl
|
||||
# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0.vds
|
||||
# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/vivado.jou
|
||||
# Running On: mkb, OS: Linux, CPU Frequency: 5012.890 MHz, CPU Physical cores: 32, Host memory: 134145 MB
|
||||
#-----------------------------------------------------------
|
||||
source NewExtInst_TOP_clk_wiz_0_0.tcl -notrace
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ly0kos/work/Zynq/ip_repo'.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'.
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: NewExtInst_TOP_clk_wiz_0_0
|
||||
Command: synth_design -top NewExtInst_TOP_clk_wiz_0_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035'
|
||||
INFO: [Device 21-403] Loading part xc7z035ffg676-2
|
||||
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
|
||||
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 123539
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2123.926 ; gain = 413.684 ; free physical = 32203 ; free virtual = 94029
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'NewExtInst_TOP_clk_wiz_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.v:65]
|
||||
INFO: [Synth 8-6157] synthesizing module 'NewExtInst_TOP_clk_wiz_0_0_clk_wiz' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_clk_wiz.v:65]
|
||||
INFO: [Synth 8-6157] synthesizing module 'IBUF' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:73631]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:73631]
|
||||
INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:82174]
|
||||
Parameter BANDWIDTH bound to: OPTIMIZED - type: string
|
||||
Parameter CLKFBOUT_MULT_F bound to: 40.000000 - type: double
|
||||
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double
|
||||
Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string
|
||||
Parameter CLKIN1_PERIOD bound to: 40.000000 - type: double
|
||||
Parameter CLKOUT0_DIVIDE_F bound to: 10.000000 - type: double
|
||||
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double
|
||||
Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double
|
||||
Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string
|
||||
Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
|
||||
Parameter COMPENSATION bound to: ZHOLD - type: string
|
||||
Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
|
||||
Parameter STARTUP_WAIT bound to: FALSE - type: string
|
||||
INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:82174]
|
||||
INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'NewExtInst_TOP_clk_wiz_0_0_clk_wiz' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_clk_wiz.v:65]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'NewExtInst_TOP_clk_wiz_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.v:65]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2199.895 ; gain = 489.652 ; free physical = 31617 ; free virtual = 93444
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2214.738 ; gain = 504.496 ; free physical = 31608 ; free virtual = 93436
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2214.738 ; gain = 504.496 ; free physical = 31608 ; free virtual = 93436
|
||||
---------------------------------------------------------------------------------
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2220.676 ; gain = 0.000 ; free physical = 31636 ; free virtual = 93464
|
||||
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_ooc.xdc] for cell 'inst'
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_ooc.xdc] for cell 'inst'
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_board.xdc] for cell 'inst'
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_board.xdc] for cell 'inst'
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xdc] for cell 'inst'
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xdc] for cell 'inst'
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/NewExtInst_TOP_clk_wiz_0_0_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/NewExtInst_TOP_clk_wiz_0_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
INFO: [Timing 38-2] Deriving generated clocks
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/dont_touch.xdc]
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/dont_touch.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2287.676 ; gain = 0.000 ; free physical = 31381 ; free virtual = 93209
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2287.711 ; gain = 0.000 ; free physical = 31380 ; free virtual = 93208
|
||||
INFO: [Designutils 20-5008] Incremental synthesis strategy off
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31246 ; free virtual = 93076
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7z035ffg676-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31246 ; free virtual = 93076
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/dont_touch.xdc, line 9).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31246 ; free virtual = 93077
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31243 ; free virtual = 93075
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 900 (col length:140)
|
||||
BRAMs: 1000 (col length: RAMB18 140 RAMB36 70)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31257 ; free virtual = 93092
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31284 ; free virtual = 93120
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31284 ; free virtual = 93120
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31284 ; free virtual = 93120
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31144 ; free virtual = 92979
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31144 ; free virtual = 92979
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31144 ; free virtual = 92979
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31144 ; free virtual = 92979
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31144 ; free virtual = 92979
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31144 ; free virtual = 92979
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-----------+------+
|
||||
| |Cell |Count |
|
||||
+------+-----------+------+
|
||||
|1 |BUFG | 2|
|
||||
|2 |MMCME2_ADV | 1|
|
||||
|3 |IBUF | 1|
|
||||
+------+-----------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31144 ; free virtual = 92979
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2287.711 ; gain = 504.496 ; free physical = 31145 ; free virtual = 92980
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2287.711 ; gain = 577.469 ; free physical = 31145 ; free virtual = 92980
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2287.711 ; gain = 0.000 ; free physical = 31145 ; free virtual = 92980
|
||||
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2287.711 ; gain = 0.000 ; free physical = 31675 ; free virtual = 93510
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Synth Design complete | Checksum: 9139fe31
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
33 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 2287.711 ; gain = 956.957 ; free physical = 31956 ; free virtual = 93791
|
||||
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1660.118; main = 1359.195; forked = 307.572
|
||||
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3258.320; main = 2255.664; forked = 1002.656
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2287.711 ; gain = 0.000 ; free physical = 31968 ; free virtual = 93803
|
||||
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0.dcp' has been generated.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP NewExtInst_TOP_clk_wiz_0_0, cache-ID = fd36933d4d3c9079
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.688 ; gain = 0.000 ; free physical = 31968 ; free virtual = 93804
|
||||
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1/NewExtInst_TOP_clk_wiz_0_0.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file NewExtInst_TOP_clk_wiz_0_0_utilization_synth.rpt -pb NewExtInst_TOP_clk_wiz_0_0_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri May 15 15:26:59 2026...
|
||||
+32
@@ -0,0 +1,32 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# IP: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xci
|
||||
# IP: The module: 'NewExtInst_TOP_clk_wiz_0_0' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_board.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_clk_wiz_0_0'. Do not add the DONT_TOUCH constraint.
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_clk_wiz_0_0'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_clk_wiz_0_0'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
|
||||
|
||||
# IP: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xci
|
||||
# IP: The module: 'NewExtInst_TOP_clk_wiz_0_0' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_board.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_clk_wiz_0_0'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_clk_wiz_0_0'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_clk_wiz_0_0'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
#
|
||||
# Vivado(TM)
|
||||
# htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
# the basic steps of a run. Note that runme.bat/sh needs
|
||||
# to be invoked for Vivado to track run status.
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
vivado -log NewExtInst_TOP_clk_wiz_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_clk_wiz_0_0.tcl
|
||||
+41
@@ -0,0 +1,41 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH variable below, before executing this script"
|
||||
exit
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;";
|
||||
} else {
|
||||
PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log NewExtInst_TOP_clk_wiz_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_clk_wiz_0_0.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
+12
@@ -0,0 +1,12 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
set PATH=%SYSTEMROOT%\system32;%PATH%
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin
|
||||
else
|
||||
PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_clk_wiz_0_0_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log NewExtInst_TOP_clk_wiz_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_clk_wiz_0_0.tcl
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="ly0kos" Host="mkb" Pid="123156" HostCore="32" HostMemory="131001520">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
Executable
+270
@@ -0,0 +1,270 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
Executable
+85
@@ -0,0 +1,85 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
cmd_exists()
|
||||
{
|
||||
command -v "$1" >/dev/null 2>&1
|
||||
}
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
|
||||
HostNameFile=/proc/sys/kernel/hostname
|
||||
if cmd_exists hostname
|
||||
then
|
||||
ISE_HOST=$(hostname)
|
||||
elif cmd_exists uname
|
||||
then
|
||||
ISE_HOST=$(uname -n)
|
||||
elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
|
||||
then
|
||||
ISE_HOST=$(cat $HostNameFile)
|
||||
elif [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
BIN
Binary file not shown.
+248
@@ -0,0 +1,248 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
namespace eval ::optrace {
|
||||
variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0.tcl"
|
||||
variable category "vivado_synth"
|
||||
}
|
||||
|
||||
# Try to connect to running dispatch if we haven't done so already.
|
||||
# This code assumes that the Tcl interpreter is not using threads,
|
||||
# since the ::dispatch::connected variable isn't mutex protected.
|
||||
if {![info exists ::dispatch::connected]} {
|
||||
namespace eval ::dispatch {
|
||||
variable connected false
|
||||
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
|
||||
set result "true"
|
||||
if {[catch {
|
||||
if {[lsearch -exact [package names] DispatchTcl] < 0} {
|
||||
set result [load librdi_cd_clienttcl[info sharedlibextension]]
|
||||
}
|
||||
if {$result eq "false"} {
|
||||
puts "WARNING: Could not load dispatch client library"
|
||||
}
|
||||
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
|
||||
if { $connect_id eq "" } {
|
||||
puts "WARNING: Could not initialize dispatch client"
|
||||
} else {
|
||||
puts "INFO: Dispatch client connection id - $connect_id"
|
||||
set connected true
|
||||
}
|
||||
} catch_res]} {
|
||||
puts "WARNING: failed to connect to dispatch server - $catch_res"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if {$::dispatch::connected} {
|
||||
# Remove the dummy proc if it exists.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
|
||||
rename ::OPTRACE ""
|
||||
}
|
||||
proc ::OPTRACE { task action {tags {} } } {
|
||||
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
|
||||
}
|
||||
# dispatch is generic. We specifically want to attach logging.
|
||||
::vitis_log::connect_client
|
||||
} else {
|
||||
# Add dummy proc if it doesn't exist.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
|
||||
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
|
||||
# Do nothing
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
OPTRACE "NewExtInst_TOP_proc_sys_reset_0_0_synth_1" START { ROLLUP_AUTO }
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
OPTRACE "Creating in-memory project" START { }
|
||||
create_project -in_memory -part xc7z035ffg676-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/wt [current_project]
|
||||
set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.xpr [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_repo_paths /home/ly0kos/work/Zynq/ip_repo [current_project]
|
||||
update_ip_catalog
|
||||
set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
OPTRACE "Creating in-memory project" END { }
|
||||
OPTRACE "Adding files" START { }
|
||||
read_ip -quiet /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.xci
|
||||
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_board.xdc]
|
||||
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.xdc]
|
||||
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_ooc.xdc]
|
||||
|
||||
OPTRACE "Adding files" END { }
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
OPTRACE "Configure IP Cache" START { }
|
||||
|
||||
set cacheID [config_ip_cache -export -no_bom -dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1 -new_name NewExtInst_TOP_proc_sys_reset_0_0 -ip [get_ips NewExtInst_TOP_proc_sys_reset_0_0]]
|
||||
|
||||
OPTRACE "Configure IP Cache" END { }
|
||||
if { $cacheID == "" } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
OPTRACE "synth_design" START { }
|
||||
synth_design -top NewExtInst_TOP_proc_sys_reset_0_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context
|
||||
OPTRACE "synth_design" END { }
|
||||
OPTRACE "Write IP Cache" START { }
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix NewExtInst_TOP_proc_sys_reset_0_0_ NewExtInst_TOP_proc_sys_reset_0_0.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_proc_sys_reset_0_0_stub.v
|
||||
lappend ipCachedFiles NewExtInst_TOP_proc_sys_reset_0_0_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_proc_sys_reset_0_0_stub.vhdl
|
||||
lappend ipCachedFiles NewExtInst_TOP_proc_sys_reset_0_0_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.v
|
||||
lappend ipCachedFiles NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.vhdl
|
||||
lappend ipCachedFiles NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } {
|
||||
config_ip_cache -add -dcp NewExtInst_TOP_proc_sys_reset_0_0.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips NewExtInst_TOP_proc_sys_reset_0_0]
|
||||
}
|
||||
OPTRACE "Write IP Cache" END { }
|
||||
}
|
||||
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
|
||||
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
|
||||
}
|
||||
|
||||
rename_ref -prefix_all NewExtInst_TOP_proc_sys_reset_0_0_
|
||||
|
||||
OPTRACE "write_checkpoint" START { CHECKPOINT }
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef NewExtInst_TOP_proc_sys_reset_0_0.dcp
|
||||
OPTRACE "write_checkpoint" END { }
|
||||
OPTRACE "synth reports" START { REPORT }
|
||||
create_report "NewExtInst_TOP_proc_sys_reset_0_0_synth_1_synth_report_utilization_0" "report_utilization -file NewExtInst_TOP_proc_sys_reset_0_0_utilization_synth.rpt -pb NewExtInst_TOP_proc_sys_reset_0_0_utilization_synth.pb"
|
||||
OPTRACE "synth reports" END { }
|
||||
|
||||
if { [catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.dcp
|
||||
} _RESULT ] } {
|
||||
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
if { [catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.dcp
|
||||
} _RESULT ] } {
|
||||
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
close [open .end.used_ip_cache.rst w]
|
||||
}; # end if cacheID
|
||||
|
||||
if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_proc_sys_reset_0_0]} {
|
||||
catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_proc_sys_reset_0_0
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_proc_sys_reset_0_0]} {
|
||||
catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_proc_sys_reset_0_0
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
OPTRACE "NewExtInst_TOP_proc_sys_reset_0_0_synth_1" END { }
|
||||
+300
@@ -0,0 +1,300 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2023.2 (64-bit)
|
||||
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Fri May 15 15:26:41 2026
|
||||
# Process ID: 123448
|
||||
# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1
|
||||
# Command line: vivado -log NewExtInst_TOP_proc_sys_reset_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_proc_sys_reset_0_0.tcl
|
||||
# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0.vds
|
||||
# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/vivado.jou
|
||||
# Running On: mkb, OS: Linux, CPU Frequency: 5005.748 MHz, CPU Physical cores: 32, Host memory: 134145 MB
|
||||
#-----------------------------------------------------------
|
||||
source NewExtInst_TOP_proc_sys_reset_0_0.tcl -notrace
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ly0kos/work/Zynq/ip_repo'.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'.
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: NewExtInst_TOP_proc_sys_reset_0_0
|
||||
Command: synth_design -top NewExtInst_TOP_proc_sys_reset_0_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035'
|
||||
INFO: [Device 21-403] Loading part xc7z035ffg676-2
|
||||
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
|
||||
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 123650
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2121.020 ; gain = 411.746 ; free physical = 32054 ; free virtual = 93879
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'NewExtInst_TOP_proc_sys_reset_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/synth/NewExtInst_TOP_proc_sys_reset_0_0.vhd:74]
|
||||
Parameter C_FAMILY bound to: zynq - type: string
|
||||
Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer
|
||||
Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer
|
||||
Parameter C_EXT_RESET_HIGH bound to: 1'b0
|
||||
Parameter C_AUX_RESET_HIGH bound to: 1'b0
|
||||
Parameter C_NUM_BUS_RST bound to: 1 - type: integer
|
||||
Parameter C_NUM_PERP_RST bound to: 1 - type: integer
|
||||
Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer
|
||||
Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer
|
||||
INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1271' bound to instance 'U0' of component 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/synth/NewExtInst_TOP_proc_sys_reset_0_0.vhd:129]
|
||||
INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330]
|
||||
Parameter INIT bound to: 1'b1
|
||||
INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1399]
|
||||
Parameter INIT bound to: 1'b1
|
||||
INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1415]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1441]
|
||||
Parameter INIT bound to: 1'b1
|
||||
INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1464]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1488]
|
||||
INFO: [Synth 8-638] synthesizing module 'lpf' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821]
|
||||
INFO: [Synth 8-3491] module 'SRL16' declared at '/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721' bound to instance 'POR_SRL_I' of component 'SRL16' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:873]
|
||||
INFO: [Synth 8-6157] synthesizing module 'SRL16' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'SRL16' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721]
|
||||
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:514]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:545]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:554]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:564]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:574]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:584]
|
||||
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
|
||||
INFO: [Synth 8-256] done synthesizing module 'lpf' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821]
|
||||
INFO: [Synth 8-638] synthesizing module 'sequence_psr' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304]
|
||||
INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126]
|
||||
INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126]
|
||||
INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304]
|
||||
INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330]
|
||||
INFO: [Synth 8-256] done synthesizing module 'NewExtInst_TOP_proc_sys_reset_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/synth/NewExtInst_TOP_proc_sys_reset_0_0.vhd:74]
|
||||
WARNING: [Synth 8-7129] Port prmry_aclk in module cdc_sync is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port prmry_resetn in module cdc_sync is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port prmry_vect_in[1] in module cdc_sync is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port prmry_vect_in[0] in module cdc_sync is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port scndry_resetn in module cdc_sync is either unconnected or has no load
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2199.988 ; gain = 490.715 ; free physical = 31580 ; free virtual = 93409
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2214.832 ; gain = 505.559 ; free physical = 31565 ; free virtual = 93393
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2214.832 ; gain = 505.559 ; free physical = 31565 ; free virtual = 93393
|
||||
---------------------------------------------------------------------------------
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2220.770 ; gain = 0.000 ; free physical = 31562 ; free virtual = 93390
|
||||
INFO: [Netlist 29-17] Analyzing 13 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_ooc.xdc] for cell 'U0'
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_ooc.xdc] for cell 'U0'
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_board.xdc] for cell 'U0'
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_board.xdc] for cell 'U0'
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.xdc] for cell 'U0'
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.xdc] for cell 'U0'
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/NewExtInst_TOP_proc_sys_reset_0_0_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/NewExtInst_TOP_proc_sys_reset_0_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/dont_touch.xdc]
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/dont_touch.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2368.582 ; gain = 0.000 ; free physical = 31353 ; free virtual = 93181
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 13 instances were transformed.
|
||||
FDR => FDRE: 12 instances
|
||||
SRL16 => SRL16E: 1 instance
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2368.617 ; gain = 0.000 ; free physical = 31345 ; free virtual = 93174
|
||||
INFO: [Designutils 20-5008] Incremental synthesis strategy off
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31241 ; free virtual = 93074
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7z035ffg676-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31241 ; free virtual = 93074
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for U0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/dont_touch.xdc, line 9).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31241 ; free virtual = 93074
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31238 ; free virtual = 93073
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 6 Bit Adders := 1
|
||||
+---Registers :
|
||||
6 Bit Registers := 1
|
||||
3 Bit Registers := 3
|
||||
1 Bit Registers := 8
|
||||
+---Muxes :
|
||||
2 Input 6 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 900 (col length:140)
|
||||
BRAMs: 1000 (col length: RAMB18 140 RAMB36 70)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31257 ; free virtual = 93091
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31261 ; free virtual = 93096
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31261 ; free virtual = 93096
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31245 ; free virtual = 93081
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31675 ; free virtual = 93510
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31675 ; free virtual = 93510
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31675 ; free virtual = 93510
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31675 ; free virtual = 93510
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31675 ; free virtual = 93510
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31675 ; free virtual = 93510
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+------+------+
|
||||
| |Cell |Count |
|
||||
+------+------+------+
|
||||
|1 |LUT1 | 5|
|
||||
|2 |LUT2 | 9|
|
||||
|3 |LUT3 | 1|
|
||||
|4 |LUT4 | 6|
|
||||
|5 |LUT5 | 3|
|
||||
|6 |LUT6 | 1|
|
||||
|7 |SRL16 | 1|
|
||||
|8 |FDR | 8|
|
||||
|9 |FDRE | 28|
|
||||
|10 |FDSE | 4|
|
||||
+------+------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31675 ; free virtual = 93510
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 5 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2368.617 ; gain = 505.559 ; free physical = 31675 ; free virtual = 93510
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2368.617 ; gain = 659.344 ; free physical = 31675 ; free virtual = 93510
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2368.617 ; gain = 0.000 ; free physical = 31675 ; free virtual = 93510
|
||||
INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2368.617 ; gain = 0.000 ; free physical = 31970 ; free virtual = 93803
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 9 instances were transformed.
|
||||
FDR => FDRE: 8 instances
|
||||
SRL16 => SRL16E: 1 instance
|
||||
|
||||
Synth Design complete | Checksum: afc55a15
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
49 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 2368.617 ; gain = 1038.895 ; free physical = 31970 ; free virtual = 93803
|
||||
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1683.673; main = 1382.355; forked = 308.374
|
||||
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3339.230; main = 2368.586; forked = 1002.660
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2392.594 ; gain = 0.000 ; free physical = 31970 ; free virtual = 93803
|
||||
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0.dcp' has been generated.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP NewExtInst_TOP_proc_sys_reset_0_0, cache-ID = 38386ef74787698d
|
||||
INFO: [Coretcl 2-1174] Renamed 6 cell refs.
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2392.594 ; gain = 0.000 ; free physical = 31970 ; free virtual = 93803
|
||||
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1/NewExtInst_TOP_proc_sys_reset_0_0.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file NewExtInst_TOP_proc_sys_reset_0_0_utilization_synth.rpt -pb NewExtInst_TOP_proc_sys_reset_0_0_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri May 15 15:26:59 2026...
|
||||
+32
@@ -0,0 +1,32 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# IP: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.xci
|
||||
# IP: The module: 'NewExtInst_TOP_proc_sys_reset_0_0' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_board.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_proc_sys_reset_0_0'. Do not add the DONT_TOUCH constraint.
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_proc_sys_reset_0_0'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_proc_sys_reset_0_0'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
|
||||
|
||||
# IP: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.xci
|
||||
# IP: The module: 'NewExtInst_TOP_proc_sys_reset_0_0' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_board.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_proc_sys_reset_0_0'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_proc_sys_reset_0_0'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0/NewExtInst_TOP_proc_sys_reset_0_0_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_proc_sys_reset_0_0'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
#
|
||||
# Vivado(TM)
|
||||
# htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
# the basic steps of a run. Note that runme.bat/sh needs
|
||||
# to be invoked for Vivado to track run status.
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
vivado -log NewExtInst_TOP_proc_sys_reset_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_proc_sys_reset_0_0.tcl
|
||||
+41
@@ -0,0 +1,41 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH variable below, before executing this script"
|
||||
exit
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;";
|
||||
} else {
|
||||
PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log NewExtInst_TOP_proc_sys_reset_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_proc_sys_reset_0_0.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
+12
@@ -0,0 +1,12 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
set PATH=%SYSTEMROOT%\system32;%PATH%
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
Executable
+40
@@ -0,0 +1,40 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin
|
||||
else
|
||||
PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_proc_sys_reset_0_0_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log NewExtInst_TOP_proc_sys_reset_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_proc_sys_reset_0_0.tcl
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="ly0kos" Host="mkb" Pid="123149" HostCore="32" HostMemory="131001520">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/ISEWrap.js
Executable
+270
@@ -0,0 +1,270 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/ISEWrap.sh
Executable
+85
@@ -0,0 +1,85 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
cmd_exists()
|
||||
{
|
||||
command -v "$1" >/dev/null 2>&1
|
||||
}
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
|
||||
HostNameFile=/proc/sys/kernel/hostname
|
||||
if cmd_exists hostname
|
||||
then
|
||||
ISE_HOST=$(hostname)
|
||||
elif cmd_exists uname
|
||||
then
|
||||
ISE_HOST=$(uname -n)
|
||||
elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
|
||||
then
|
||||
ISE_HOST=$(cat $HostNameFile)
|
||||
elif [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
BIN
Binary file not shown.
+172
@@ -0,0 +1,172 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
namespace eval ::optrace {
|
||||
variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/NewExtInst_TOP_processing_system7_0_0.tcl"
|
||||
variable category "vivado_synth"
|
||||
}
|
||||
|
||||
# Try to connect to running dispatch if we haven't done so already.
|
||||
# This code assumes that the Tcl interpreter is not using threads,
|
||||
# since the ::dispatch::connected variable isn't mutex protected.
|
||||
if {![info exists ::dispatch::connected]} {
|
||||
namespace eval ::dispatch {
|
||||
variable connected false
|
||||
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
|
||||
set result "true"
|
||||
if {[catch {
|
||||
if {[lsearch -exact [package names] DispatchTcl] < 0} {
|
||||
set result [load librdi_cd_clienttcl[info sharedlibextension]]
|
||||
}
|
||||
if {$result eq "false"} {
|
||||
puts "WARNING: Could not load dispatch client library"
|
||||
}
|
||||
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
|
||||
if { $connect_id eq "" } {
|
||||
puts "WARNING: Could not initialize dispatch client"
|
||||
} else {
|
||||
puts "INFO: Dispatch client connection id - $connect_id"
|
||||
set connected true
|
||||
}
|
||||
} catch_res]} {
|
||||
puts "WARNING: failed to connect to dispatch server - $catch_res"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if {$::dispatch::connected} {
|
||||
# Remove the dummy proc if it exists.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
|
||||
rename ::OPTRACE ""
|
||||
}
|
||||
proc ::OPTRACE { task action {tags {} } } {
|
||||
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
|
||||
}
|
||||
# dispatch is generic. We specifically want to attach logging.
|
||||
::vitis_log::connect_client
|
||||
} else {
|
||||
# Add dummy proc if it doesn't exist.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
|
||||
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
|
||||
# Do nothing
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
OPTRACE "NewExtInst_TOP_processing_system7_0_0_synth_1" START { ROLLUP_AUTO }
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
OPTRACE "Creating in-memory project" START { }
|
||||
create_project -in_memory -part xc7z035ffg676-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/wt [current_project]
|
||||
set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.xpr [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_repo_paths /home/ly0kos/work/Zynq/ip_repo [current_project]
|
||||
update_ip_catalog
|
||||
set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
OPTRACE "Creating in-memory project" END { }
|
||||
OPTRACE "Adding files" START { }
|
||||
read_ip -quiet /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xci
|
||||
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xdc]
|
||||
|
||||
OPTRACE "Adding files" END { }
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
OPTRACE "synth_design" START { }
|
||||
synth_design -top NewExtInst_TOP_processing_system7_0_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context
|
||||
OPTRACE "synth_design" END { }
|
||||
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
|
||||
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
|
||||
}
|
||||
|
||||
rename_ref -prefix_all NewExtInst_TOP_processing_system7_0_0_
|
||||
|
||||
OPTRACE "write_checkpoint" START { CHECKPOINT }
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef NewExtInst_TOP_processing_system7_0_0.dcp
|
||||
OPTRACE "write_checkpoint" END { }
|
||||
OPTRACE "synth reports" START { REPORT }
|
||||
create_report "NewExtInst_TOP_processing_system7_0_0_synth_1_synth_report_utilization_0" "report_utilization -file NewExtInst_TOP_processing_system7_0_0_utilization_synth.rpt -pb NewExtInst_TOP_processing_system7_0_0_utilization_synth.pb"
|
||||
OPTRACE "synth reports" END { }
|
||||
|
||||
if { [catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/NewExtInst_TOP_processing_system7_0_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.dcp
|
||||
} _RESULT ] } {
|
||||
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_processing_system7_0_0]} {
|
||||
catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_processing_system7_0_0
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_processing_system7_0_0]} {
|
||||
catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_processing_system7_0_0
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
OPTRACE "NewExtInst_TOP_processing_system7_0_0_synth_1" END { }
|
||||
+337
@@ -0,0 +1,337 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2023.2 (64-bit)
|
||||
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Fri May 15 15:26:41 2026
|
||||
# Process ID: 123452
|
||||
# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1
|
||||
# Command line: vivado -log NewExtInst_TOP_processing_system7_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_processing_system7_0_0.tcl
|
||||
# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/NewExtInst_TOP_processing_system7_0_0.vds
|
||||
# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/vivado.jou
|
||||
# Running On: mkb, OS: Linux, CPU Frequency: 4987.800 MHz, CPU Physical cores: 32, Host memory: 134145 MB
|
||||
#-----------------------------------------------------------
|
||||
source NewExtInst_TOP_processing_system7_0_0.tcl -notrace
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ly0kos/work/Zynq/ip_repo'.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'.
|
||||
Command: synth_design -top NewExtInst_TOP_processing_system7_0_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035'
|
||||
INFO: [Device 21-403] Loading part xc7z035ffg676-2
|
||||
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
|
||||
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 123729
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2118.531 ; gain = 402.715 ; free physical = 32101 ; free virtual = 93926
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'NewExtInst_TOP_processing_system7_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:53]
|
||||
INFO: [Synth 8-6157] synthesizing module 'processing_system7_v5_5_processing_system7' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152]
|
||||
INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
|
||||
INFO: [Synth 8-6157] synthesizing module 'BIBUF' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1598]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'BIBUF' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1598]
|
||||
INFO: [Synth 8-6157] synthesizing module 'PS7' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111859]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'PS7' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111859]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'processing_system7_v5_5_processing_system7' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152]
|
||||
WARNING: [Synth 8-7071] port 'M_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326]
|
||||
WARNING: [Synth 8-7071] port 'M_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326]
|
||||
WARNING: [Synth 8-7071] port 'S_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326]
|
||||
WARNING: [Synth 8-7071] port 'S_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326]
|
||||
WARNING: [Synth 8-7071] port 'S_AXI_ACP_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326]
|
||||
WARNING: [Synth 8-7071] port 'S_AXI_HP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326]
|
||||
WARNING: [Synth 8-7071] port 'S_AXI_HP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326]
|
||||
WARNING: [Synth 8-7071] port 'S_AXI_HP2_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326]
|
||||
WARNING: [Synth 8-7071] port 'S_AXI_HP3_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326]
|
||||
WARNING: [Synth 8-7071] port 'DMA0_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326]
|
||||
WARNING: [Synth 8-7071] port 'DMA1_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326]
|
||||
WARNING: [Synth 8-7071] port 'DMA2_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326]
|
||||
WARNING: [Synth 8-7071] port 'DMA3_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326]
|
||||
WARNING: [Synth 8-7023] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:326]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'NewExtInst_TOP_processing_system7_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/synth/NewExtInst_TOP_processing_system7_0_0.v:53]
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_COL in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_CRS in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_RX_DV in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_RX_ER in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[7] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[6] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[5] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[4] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[3] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[1] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[0] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET1_GMII_COL in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET1_GMII_CRS in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET1_GMII_RX_DV in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET1_GMII_RX_ER in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[7] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[6] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[5] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[4] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[3] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[1] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[0] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_GP0_ARSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_GP0_AWSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_GP1_ARSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_GP1_AWSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_ACP_ARSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_ACP_AWSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_HP0_ARSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_HP0_AWSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_HP1_ARSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_HP1_AWSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_HP2_ARSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_HP2_AWSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_HP3_ARSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_HP3_AWSIZE[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FCLK_CLKTRIG3_N in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FCLK_CLKTRIG2_N in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FCLK_CLKTRIG1_N in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FCLK_CLKTRIG0_N in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[31] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[30] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[29] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[28] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[27] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[26] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[25] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[24] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[23] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[22] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[21] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[20] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[19] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[18] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[17] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[16] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[15] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[14] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[13] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[12] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[11] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[10] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[9] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[8] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[7] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[6] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[5] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[4] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[3] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[1] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_DATA[0] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_VALID in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_ATID[3] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_ATID[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_ATID[1] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port FTMD_TRACEIN_ATID[0] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2211.500 ; gain = 495.684 ; free physical = 31589 ; free virtual = 93418
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2223.375 ; gain = 507.559 ; free physical = 31580 ; free virtual = 93409
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2223.375 ; gain = 507.559 ; free physical = 31580 ; free virtual = 93409
|
||||
---------------------------------------------------------------------------------
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2229.312 ; gain = 0.000 ; free physical = 31562 ; free virtual = 93390
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xdc] for cell 'inst'
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xdc] for cell 'inst'
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/NewExtInst_TOP_processing_system7_0_0_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/NewExtInst_TOP_processing_system7_0_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/dont_touch.xdc]
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/dont_touch.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2293.344 ; gain = 0.000 ; free physical = 31329 ; free virtual = 93158
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2293.379 ; gain = 0.000 ; free physical = 31329 ; free virtual = 93158
|
||||
INFO: [Designutils 20-5008] Incremental synthesis strategy off
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2293.379 ; gain = 577.562 ; free physical = 31238 ; free virtual = 93071
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7z035ffg676-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2293.379 ; gain = 577.562 ; free physical = 31238 ; free virtual = 93071
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/dont_touch.xdc, line 9).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2293.379 ; gain = 577.562 ; free physical = 31257 ; free virtual = 93089
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2293.379 ; gain = 577.562 ; free physical = 31257 ; free virtual = 93090
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 900 (col length:140)
|
||||
BRAMs: 1000 (col length: RAMB18 140 RAMB36 70)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_COL in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_CRS in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_RX_DV in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_RX_ER in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[7] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[6] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[5] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[4] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[3] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[2] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[1] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET0_GMII_RXD[0] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET1_GMII_COL in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET1_GMII_CRS in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET1_GMII_RX_DV in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET1_GMII_RX_ER in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[7] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[6] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[5] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[4] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ENET1_GMII_RXD[3] in module processing_system7_v5_5_processing_system7 is either unconnected or has no load
|
||||
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2293.379 ; gain = 577.562 ; free physical = 31257 ; free virtual = 93091
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2342.328 ; gain = 626.512 ; free physical = 31151 ; free virtual = 92987
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2361.336 ; gain = 645.520 ; free physical = 31136 ; free virtual = 92971
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2369.344 ; gain = 653.527 ; free physical = 31142 ; free virtual = 92977
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2378.250 ; gain = 662.434 ; free physical = 31970 ; free virtual = 93803
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2378.250 ; gain = 662.434 ; free physical = 31970 ; free virtual = 93803
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2378.250 ; gain = 662.434 ; free physical = 31970 ; free virtual = 93803
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2378.250 ; gain = 662.434 ; free physical = 31970 ; free virtual = 93803
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2378.250 ; gain = 662.434 ; free physical = 31970 ; free virtual = 93803
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2378.250 ; gain = 662.434 ; free physical = 31970 ; free virtual = 93803
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+------+------+
|
||||
| |Cell |Count |
|
||||
+------+------+------+
|
||||
|1 |BIBUF | 130|
|
||||
|2 |BUFG | 4|
|
||||
|3 |LUT1 | 24|
|
||||
|4 |PS7 | 1|
|
||||
+------+------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2378.250 ; gain = 662.434 ; free physical = 31970 ; free virtual = 93803
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 80 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2378.250 ; gain = 592.430 ; free physical = 31970 ; free virtual = 93802
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2378.258 ; gain = 662.434 ; free physical = 31970 ; free virtual = 93802
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2378.258 ; gain = 0.000 ; free physical = 32196 ; free virtual = 94028
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2403.031 ; gain = 0.000 ; free physical = 32195 ; free virtual = 94027
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Synth Design complete | Checksum: 31c0eba1
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
28 Infos, 115 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 2403.066 ; gain = 1106.738 ; free physical = 32194 ; free virtual = 94026
|
||||
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1768.330; main = 1489.861; forked = 307.605
|
||||
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3388.105; main = 2403.035; forked = 1026.766
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2403.066 ; gain = 0.000 ; free physical = 32194 ; free virtual = 94026
|
||||
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1/NewExtInst_TOP_processing_system7_0_0.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file NewExtInst_TOP_processing_system7_0_0_utilization_synth.rpt -pb NewExtInst_TOP_processing_system7_0_0_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri May 15 15:27:00 2026...
|
||||
+16
@@ -0,0 +1,16 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# IP: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xci
|
||||
# IP: The module: 'NewExtInst_TOP_processing_system7_0_0' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_processing_system7_0_0'. Do not add the DONT_TOUCH constraint.
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
|
||||
|
||||
# IP: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xci
|
||||
# IP: The module: 'NewExtInst_TOP_processing_system7_0_0' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/NewExtInst_TOP_processing_system7_0_0.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_processing_system7_0_0'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
#
|
||||
# Vivado(TM)
|
||||
# htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
# the basic steps of a run. Note that runme.bat/sh needs
|
||||
# to be invoked for Vivado to track run status.
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
vivado -log NewExtInst_TOP_processing_system7_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_processing_system7_0_0.tcl
|
||||
+41
@@ -0,0 +1,41 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH variable below, before executing this script"
|
||||
exit
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;";
|
||||
} else {
|
||||
PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log NewExtInst_TOP_processing_system7_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_processing_system7_0_0.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
+12
@@ -0,0 +1,12 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
set PATH=%SYSTEMROOT%\system32;%PATH%
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
Executable
+40
@@ -0,0 +1,40 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin
|
||||
else
|
||||
PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_processing_system7_0_0_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log NewExtInst_TOP_processing_system7_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_processing_system7_0_0.tcl
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="ly0kos" Host="mkb" Pid="123172" HostCore="32" HostMemory="131001520">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
Executable
+270
@@ -0,0 +1,270 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
Executable
+85
@@ -0,0 +1,85 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
cmd_exists()
|
||||
{
|
||||
command -v "$1" >/dev/null 2>&1
|
||||
}
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
|
||||
HostNameFile=/proc/sys/kernel/hostname
|
||||
if cmd_exists hostname
|
||||
then
|
||||
ISE_HOST=$(hostname)
|
||||
elif cmd_exists uname
|
||||
then
|
||||
ISE_HOST=$(uname -n)
|
||||
elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
|
||||
then
|
||||
ISE_HOST=$(cat $HostNameFile)
|
||||
elif [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
BIN
Binary file not shown.
+248
@@ -0,0 +1,248 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
namespace eval ::optrace {
|
||||
variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.tcl"
|
||||
variable category "vivado_synth"
|
||||
}
|
||||
|
||||
# Try to connect to running dispatch if we haven't done so already.
|
||||
# This code assumes that the Tcl interpreter is not using threads,
|
||||
# since the ::dispatch::connected variable isn't mutex protected.
|
||||
if {![info exists ::dispatch::connected]} {
|
||||
namespace eval ::dispatch {
|
||||
variable connected false
|
||||
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
|
||||
set result "true"
|
||||
if {[catch {
|
||||
if {[lsearch -exact [package names] DispatchTcl] < 0} {
|
||||
set result [load librdi_cd_clienttcl[info sharedlibextension]]
|
||||
}
|
||||
if {$result eq "false"} {
|
||||
puts "WARNING: Could not load dispatch client library"
|
||||
}
|
||||
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
|
||||
if { $connect_id eq "" } {
|
||||
puts "WARNING: Could not initialize dispatch client"
|
||||
} else {
|
||||
puts "INFO: Dispatch client connection id - $connect_id"
|
||||
set connected true
|
||||
}
|
||||
} catch_res]} {
|
||||
puts "WARNING: failed to connect to dispatch server - $catch_res"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if {$::dispatch::connected} {
|
||||
# Remove the dummy proc if it exists.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
|
||||
rename ::OPTRACE ""
|
||||
}
|
||||
proc ::OPTRACE { task action {tags {} } } {
|
||||
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
|
||||
}
|
||||
# dispatch is generic. We specifically want to attach logging.
|
||||
::vitis_log::connect_client
|
||||
} else {
|
||||
# Add dummy proc if it doesn't exist.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
|
||||
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
|
||||
# Do nothing
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
OPTRACE "NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1" START { ROLLUP_AUTO }
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
OPTRACE "Creating in-memory project" START { }
|
||||
create_project -in_memory -part xc7z035ffg676-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/wt [current_project]
|
||||
set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.xpr [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_repo_paths /home/ly0kos/work/Zynq/ip_repo [current_project]
|
||||
update_ip_catalog
|
||||
set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
OPTRACE "Creating in-memory project" END { }
|
||||
OPTRACE "Adding files" START { }
|
||||
read_ip -quiet /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xci
|
||||
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_board.xdc]
|
||||
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xdc]
|
||||
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_ooc.xdc]
|
||||
|
||||
OPTRACE "Adding files" END { }
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
OPTRACE "Configure IP Cache" START { }
|
||||
|
||||
set cacheID [config_ip_cache -export -no_bom -dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1 -new_name NewExtInst_TOP_rst_clk_wiz_0_100M_0 -ip [get_ips NewExtInst_TOP_rst_clk_wiz_0_100M_0]]
|
||||
|
||||
OPTRACE "Configure IP Cache" END { }
|
||||
if { $cacheID == "" } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
OPTRACE "synth_design" START { }
|
||||
synth_design -top NewExtInst_TOP_rst_clk_wiz_0_100M_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context
|
||||
OPTRACE "synth_design" END { }
|
||||
OPTRACE "Write IP Cache" START { }
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix NewExtInst_TOP_rst_clk_wiz_0_100M_0_ NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.v
|
||||
lappend ipCachedFiles NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.vhdl
|
||||
lappend ipCachedFiles NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.v
|
||||
lappend ipCachedFiles NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.vhdl
|
||||
lappend ipCachedFiles NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } {
|
||||
config_ip_cache -add -dcp NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips NewExtInst_TOP_rst_clk_wiz_0_100M_0]
|
||||
}
|
||||
OPTRACE "Write IP Cache" END { }
|
||||
}
|
||||
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
|
||||
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
|
||||
}
|
||||
|
||||
rename_ref -prefix_all NewExtInst_TOP_rst_clk_wiz_0_100M_0_
|
||||
|
||||
OPTRACE "write_checkpoint" START { CHECKPOINT }
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp
|
||||
OPTRACE "write_checkpoint" END { }
|
||||
OPTRACE "synth reports" START { REPORT }
|
||||
create_report "NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1_synth_report_utilization_0" "report_utilization -file NewExtInst_TOP_rst_clk_wiz_0_100M_0_utilization_synth.rpt -pb NewExtInst_TOP_rst_clk_wiz_0_100M_0_utilization_synth.pb"
|
||||
OPTRACE "synth reports" END { }
|
||||
|
||||
if { [catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp
|
||||
} _RESULT ] } {
|
||||
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
if { [catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp
|
||||
} _RESULT ] } {
|
||||
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
close [open .end.used_ip_cache.rst w]
|
||||
}; # end if cacheID
|
||||
|
||||
if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0]} {
|
||||
catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0]} {
|
||||
catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
OPTRACE "NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1" END { }
|
||||
+300
@@ -0,0 +1,300 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2023.2 (64-bit)
|
||||
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Fri May 15 15:26:41 2026
|
||||
# Process ID: 123451
|
||||
# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1
|
||||
# Command line: vivado -log NewExtInst_TOP_rst_clk_wiz_0_100M_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_rst_clk_wiz_0_100M_0.tcl
|
||||
# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vds
|
||||
# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/vivado.jou
|
||||
# Running On: mkb, OS: Linux, CPU Frequency: 4998.693 MHz, CPU Physical cores: 32, Host memory: 134145 MB
|
||||
#-----------------------------------------------------------
|
||||
source NewExtInst_TOP_rst_clk_wiz_0_100M_0.tcl -notrace
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ly0kos/work/Zynq/ip_repo'.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'.
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: NewExtInst_TOP_rst_clk_wiz_0_100M_0
|
||||
Command: synth_design -top NewExtInst_TOP_rst_clk_wiz_0_100M_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035'
|
||||
INFO: [Device 21-403] Loading part xc7z035ffg676-2
|
||||
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
|
||||
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 123548
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2112.535 ; gain = 402.715 ; free physical = 32328 ; free virtual = 94154
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'NewExtInst_TOP_rst_clk_wiz_0_100M_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/synth/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd:74]
|
||||
Parameter C_FAMILY bound to: zynq - type: string
|
||||
Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer
|
||||
Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer
|
||||
Parameter C_EXT_RESET_HIGH bound to: 1'b1
|
||||
Parameter C_AUX_RESET_HIGH bound to: 1'b0
|
||||
Parameter C_NUM_BUS_RST bound to: 1 - type: integer
|
||||
Parameter C_NUM_PERP_RST bound to: 1 - type: integer
|
||||
Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer
|
||||
Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer
|
||||
INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1271' bound to instance 'U0' of component 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/synth/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd:129]
|
||||
INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330]
|
||||
Parameter INIT bound to: 1'b1
|
||||
INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1399]
|
||||
Parameter INIT bound to: 1'b1
|
||||
INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1415]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1441]
|
||||
Parameter INIT bound to: 1'b1
|
||||
INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1464]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1488]
|
||||
INFO: [Synth 8-638] synthesizing module 'lpf' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821]
|
||||
INFO: [Synth 8-3491] module 'SRL16' declared at '/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721' bound to instance 'POR_SRL_I' of component 'SRL16' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:873]
|
||||
INFO: [Synth 8-6157] synthesizing module 'SRL16' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'SRL16' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721]
|
||||
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:514]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:545]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:554]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:564]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:574]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:584]
|
||||
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
|
||||
INFO: [Synth 8-256] done synthesizing module 'lpf' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821]
|
||||
INFO: [Synth 8-638] synthesizing module 'sequence_psr' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304]
|
||||
INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126]
|
||||
INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126]
|
||||
INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304]
|
||||
INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330]
|
||||
INFO: [Synth 8-256] done synthesizing module 'NewExtInst_TOP_rst_clk_wiz_0_100M_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/synth/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd:74]
|
||||
WARNING: [Synth 8-7129] Port prmry_aclk in module cdc_sync is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port prmry_resetn in module cdc_sync is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port prmry_vect_in[1] in module cdc_sync is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port prmry_vect_in[0] in module cdc_sync is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port scndry_resetn in module cdc_sync is either unconnected or has no load
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2191.504 ; gain = 481.684 ; free physical = 31641 ; free virtual = 93467
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2206.348 ; gain = 496.527 ; free physical = 31623 ; free virtual = 93451
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2206.348 ; gain = 496.527 ; free physical = 31623 ; free virtual = 93451
|
||||
---------------------------------------------------------------------------------
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2212.285 ; gain = 0.000 ; free physical = 31616 ; free virtual = 93444
|
||||
INFO: [Netlist 29-17] Analyzing 13 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_ooc.xdc] for cell 'U0'
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_ooc.xdc] for cell 'U0'
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_board.xdc] for cell 'U0'
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_board.xdc] for cell 'U0'
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xdc] for cell 'U0'
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xdc] for cell 'U0'
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/NewExtInst_TOP_rst_clk_wiz_0_100M_0_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/NewExtInst_TOP_rst_clk_wiz_0_100M_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/dont_touch.xdc]
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/dont_touch.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2351.098 ; gain = 0.000 ; free physical = 31382 ; free virtual = 93210
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 13 instances were transformed.
|
||||
FDR => FDRE: 12 instances
|
||||
SRL16 => SRL16E: 1 instance
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2351.133 ; gain = 0.000 ; free physical = 31381 ; free virtual = 93209
|
||||
INFO: [Designutils 20-5008] Incremental synthesis strategy off
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31246 ; free virtual = 93077
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7z035ffg676-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31246 ; free virtual = 93077
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for U0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/dont_touch.xdc, line 9).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31246 ; free virtual = 93077
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31243 ; free virtual = 93075
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 6 Bit Adders := 1
|
||||
+---Registers :
|
||||
6 Bit Registers := 1
|
||||
3 Bit Registers := 3
|
||||
1 Bit Registers := 8
|
||||
+---Muxes :
|
||||
2 Input 6 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 900 (col length:140)
|
||||
BRAMs: 1000 (col length: RAMB18 140 RAMB36 70)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31257 ; free virtual = 93092
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31284 ; free virtual = 93120
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31284 ; free virtual = 93120
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31262 ; free virtual = 93097
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31144 ; free virtual = 92979
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31144 ; free virtual = 92979
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31144 ; free virtual = 92979
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31144 ; free virtual = 92979
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31144 ; free virtual = 92979
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31144 ; free virtual = 92979
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+------+------+
|
||||
| |Cell |Count |
|
||||
+------+------+------+
|
||||
|1 |LUT1 | 5|
|
||||
|2 |LUT2 | 9|
|
||||
|3 |LUT3 | 1|
|
||||
|4 |LUT4 | 6|
|
||||
|5 |LUT5 | 3|
|
||||
|6 |LUT6 | 1|
|
||||
|7 |SRL16 | 1|
|
||||
|8 |FDR | 8|
|
||||
|9 |FDRE | 28|
|
||||
|10 |FDSE | 4|
|
||||
+------+------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31144 ; free virtual = 92979
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 5 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2351.133 ; gain = 496.527 ; free physical = 31392 ; free virtual = 93228
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31392 ; free virtual = 93228
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2351.133 ; gain = 0.000 ; free physical = 31392 ; free virtual = 93228
|
||||
INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2351.133 ; gain = 0.000 ; free physical = 31675 ; free virtual = 93510
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 9 instances were transformed.
|
||||
FDR => FDRE: 8 instances
|
||||
SRL16 => SRL16E: 1 instance
|
||||
|
||||
Synth Design complete | Checksum: 2497e3b9
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
49 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 2351.133 ; gain = 1058.770 ; free physical = 31968 ; free virtual = 93804
|
||||
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1679.910; main = 1379.216; forked = 307.635
|
||||
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3321.746; main = 2351.102; forked = 1002.660
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2375.109 ; gain = 0.000 ; free physical = 31968 ; free virtual = 93804
|
||||
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp' has been generated.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP NewExtInst_TOP_rst_clk_wiz_0_100M_0, cache-ID = 2e8c33c5e53a7d6d
|
||||
INFO: [Coretcl 2-1174] Renamed 6 cell refs.
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2375.109 ; gain = 0.000 ; free physical = 31970 ; free virtual = 93804
|
||||
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file NewExtInst_TOP_rst_clk_wiz_0_100M_0_utilization_synth.rpt -pb NewExtInst_TOP_rst_clk_wiz_0_100M_0_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri May 15 15:26:59 2026...
|
||||
+32
@@ -0,0 +1,32 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# IP: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xci
|
||||
# IP: The module: 'NewExtInst_TOP_rst_clk_wiz_0_100M_0' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_board.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_rst_clk_wiz_0_100M_0'. Do not add the DONT_TOUCH constraint.
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_rst_clk_wiz_0_100M_0'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_rst_clk_wiz_0_100M_0'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
|
||||
|
||||
# IP: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xci
|
||||
# IP: The module: 'NewExtInst_TOP_rst_clk_wiz_0_100M_0' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_board.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_rst_clk_wiz_0_100M_0'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_rst_clk_wiz_0_100M_0'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'NewExtInst_TOP_rst_clk_wiz_0_100M_0'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
#
|
||||
# Vivado(TM)
|
||||
# htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
# the basic steps of a run. Note that runme.bat/sh needs
|
||||
# to be invoked for Vivado to track run status.
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
vivado -log NewExtInst_TOP_rst_clk_wiz_0_100M_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_rst_clk_wiz_0_100M_0.tcl
|
||||
+41
@@ -0,0 +1,41 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH variable below, before executing this script"
|
||||
exit
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;";
|
||||
} else {
|
||||
PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log NewExtInst_TOP_rst_clk_wiz_0_100M_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_rst_clk_wiz_0_100M_0.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
+12
@@ -0,0 +1,12 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
set PATH=%SYSTEMROOT%\system32;%PATH%
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
Executable
+40
@@ -0,0 +1,40 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin
|
||||
else
|
||||
PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log NewExtInst_TOP_rst_clk_wiz_0_100M_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_rst_clk_wiz_0_100M_0.tcl
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="ly0kos" Host="mkb" Pid="123171" HostCore="32" HostMemory="131001520">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
+270
@@ -0,0 +1,270 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
+85
@@ -0,0 +1,85 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
cmd_exists()
|
||||
{
|
||||
command -v "$1" >/dev/null 2>&1
|
||||
}
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
|
||||
HostNameFile=/proc/sys/kernel/hostname
|
||||
if cmd_exists hostname
|
||||
then
|
||||
ISE_HOST=$(hostname)
|
||||
elif cmd_exists uname
|
||||
then
|
||||
ISE_HOST=$(uname -n)
|
||||
elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
|
||||
then
|
||||
ISE_HOST=$(cat $HostNameFile)
|
||||
elif [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
BIN
Binary file not shown.
+246
@@ -0,0 +1,246 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
namespace eval ::optrace {
|
||||
variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0.tcl"
|
||||
variable category "vivado_synth"
|
||||
}
|
||||
|
||||
# Try to connect to running dispatch if we haven't done so already.
|
||||
# This code assumes that the Tcl interpreter is not using threads,
|
||||
# since the ::dispatch::connected variable isn't mutex protected.
|
||||
if {![info exists ::dispatch::connected]} {
|
||||
namespace eval ::dispatch {
|
||||
variable connected false
|
||||
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
|
||||
set result "true"
|
||||
if {[catch {
|
||||
if {[lsearch -exact [package names] DispatchTcl] < 0} {
|
||||
set result [load librdi_cd_clienttcl[info sharedlibextension]]
|
||||
}
|
||||
if {$result eq "false"} {
|
||||
puts "WARNING: Could not load dispatch client library"
|
||||
}
|
||||
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
|
||||
if { $connect_id eq "" } {
|
||||
puts "WARNING: Could not initialize dispatch client"
|
||||
} else {
|
||||
puts "INFO: Dispatch client connection id - $connect_id"
|
||||
set connected true
|
||||
}
|
||||
} catch_res]} {
|
||||
puts "WARNING: failed to connect to dispatch server - $catch_res"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if {$::dispatch::connected} {
|
||||
# Remove the dummy proc if it exists.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
|
||||
rename ::OPTRACE ""
|
||||
}
|
||||
proc ::OPTRACE { task action {tags {} } } {
|
||||
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
|
||||
}
|
||||
# dispatch is generic. We specifically want to attach logging.
|
||||
::vitis_log::connect_client
|
||||
} else {
|
||||
# Add dummy proc if it doesn't exist.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
|
||||
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
|
||||
# Do nothing
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
OPTRACE "NewExtInst_TOP_xbar_0_synth_1" START { ROLLUP_AUTO }
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
OPTRACE "Creating in-memory project" START { }
|
||||
create_project -in_memory -part xc7z035ffg676-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/wt [current_project]
|
||||
set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.xpr [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_repo_paths /home/ly0kos/work/Zynq/ip_repo [current_project]
|
||||
update_ip_catalog
|
||||
set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
OPTRACE "Creating in-memory project" END { }
|
||||
OPTRACE "Adding files" START { }
|
||||
read_ip -quiet /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.srcs/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0.xci
|
||||
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_ooc.xdc]
|
||||
|
||||
OPTRACE "Adding files" END { }
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
OPTRACE "Configure IP Cache" START { }
|
||||
|
||||
set cacheID [config_ip_cache -export -no_bom -dir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1 -new_name NewExtInst_TOP_xbar_0 -ip [get_ips NewExtInst_TOP_xbar_0]]
|
||||
|
||||
OPTRACE "Configure IP Cache" END { }
|
||||
if { $cacheID == "" } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
OPTRACE "synth_design" START { }
|
||||
synth_design -top NewExtInst_TOP_xbar_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context
|
||||
OPTRACE "synth_design" END { }
|
||||
OPTRACE "Write IP Cache" START { }
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix NewExtInst_TOP_xbar_0_ NewExtInst_TOP_xbar_0.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_xbar_0_stub.v
|
||||
lappend ipCachedFiles NewExtInst_TOP_xbar_0_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_xbar_0_stub.vhdl
|
||||
lappend ipCachedFiles NewExtInst_TOP_xbar_0_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_xbar_0_sim_netlist.v
|
||||
lappend ipCachedFiles NewExtInst_TOP_xbar_0_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ NewExtInst_TOP_xbar_0_sim_netlist.vhdl
|
||||
lappend ipCachedFiles NewExtInst_TOP_xbar_0_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } {
|
||||
config_ip_cache -add -dcp NewExtInst_TOP_xbar_0.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips NewExtInst_TOP_xbar_0]
|
||||
}
|
||||
OPTRACE "Write IP Cache" END { }
|
||||
}
|
||||
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
|
||||
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
|
||||
}
|
||||
|
||||
rename_ref -prefix_all NewExtInst_TOP_xbar_0_
|
||||
|
||||
OPTRACE "write_checkpoint" START { CHECKPOINT }
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef NewExtInst_TOP_xbar_0.dcp
|
||||
OPTRACE "write_checkpoint" END { }
|
||||
OPTRACE "synth reports" START { REPORT }
|
||||
create_report "NewExtInst_TOP_xbar_0_synth_1_synth_report_utilization_0" "report_utilization -file NewExtInst_TOP_xbar_0_utilization_synth.rpt -pb NewExtInst_TOP_xbar_0_utilization_synth.pb"
|
||||
OPTRACE "synth reports" END { }
|
||||
|
||||
if { [catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0.dcp
|
||||
} _RESULT ] } {
|
||||
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
if { [catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0.dcp /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0.dcp
|
||||
} _RESULT ] } {
|
||||
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0_sim_netlist.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
file rename -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0_sim_netlist.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
close [open .end.used_ip_cache.rst w]
|
||||
}; # end if cacheID
|
||||
|
||||
if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_xbar_0]} {
|
||||
catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_stub.v /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_xbar_0
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_xbar_0]} {
|
||||
catch {
|
||||
file copy -force /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_stub.vhdl /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.ip_user_files/ip/NewExtInst_TOP_xbar_0
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
OPTRACE "NewExtInst_TOP_xbar_0_synth_1" END { }
|
||||
+371
@@ -0,0 +1,371 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2023.2 (64-bit)
|
||||
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Fri May 15 15:26:41 2026
|
||||
# Process ID: 123449
|
||||
# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1
|
||||
# Command line: vivado -log NewExtInst_TOP_xbar_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_xbar_0.tcl
|
||||
# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0.vds
|
||||
# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/vivado.jou
|
||||
# Running On: mkb, OS: Linux, CPU Frequency: 4976.515 MHz, CPU Physical cores: 32, Host memory: 134145 MB
|
||||
#-----------------------------------------------------------
|
||||
source NewExtInst_TOP_xbar_0.tcl -notrace
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ly0kos/work/Zynq/ip_repo'.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'.
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: NewExtInst_TOP_xbar_0
|
||||
Command: synth_design -top NewExtInst_TOP_xbar_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035'
|
||||
INFO: [Device 21-403] Loading part xc7z035ffg676-2
|
||||
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
|
||||
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 123767
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2121.438 ; gain = 399.746 ; free physical = 31605 ; free virtual = 93432
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'NewExtInst_TOP_xbar_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/synth/NewExtInst_TOP_xbar_0.v:53]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_axi_crossbar' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4871]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_crossbar_sasd' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:1234]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_addr_decoder' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:790]
|
||||
INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_comparator_static' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119]
|
||||
INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_carry_and' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:60]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_carry_and' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:60]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_comparator_static' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119]
|
||||
INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_comparator_static__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_comparator_static__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119]
|
||||
INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_comparator_static__parameterized1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_comparator_static__parameterized1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2119]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_addr_decoder' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:790]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_decerr_slave' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3493]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_decerr_slave' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:3493]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_addr_arbiter_sasd' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:63]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_addr_arbiter_sasd' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:63]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_splitter' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4451]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_splitter' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4451]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_30_splitter__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4451]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_splitter__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4451]
|
||||
INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_mux_enc' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_mux_enc' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436]
|
||||
INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_mux_enc__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_mux_enc__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436]
|
||||
INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_mux_enc__parameterized1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_mux_enc__parameterized1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_1_mux_enc__parameterized2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_1_mux_enc__parameterized2' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v:2436]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_crossbar_sasd' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:1234]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_30_axi_crossbar' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:4871]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'NewExtInst_TOP_xbar_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/synth/NewExtInst_TOP_xbar_0.v:53]
|
||||
WARNING: [Synth 8-6014] Unused sequential element gen_debug_trans_seq.debug_aw_trans_seq_i_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:2051]
|
||||
WARNING: [Synth 8-6014] Unused sequential element gen_debug_trans_seq.debug_ar_trans_seq_i_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:2062]
|
||||
WARNING: [Synth 8-6014] Unused sequential element gen_debug_trans_seq.debug_w_beat_cnt_i_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:2073]
|
||||
WARNING: [Synth 8-6014] Unused sequential element gen_debug_trans_seq.debug_r_beat_cnt_i_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/fb47/hdl/axi_crossbar_v2_1_vl_rfs.v:2086]
|
||||
WARNING: [Synth 8-7129] Port S[0] in module generic_baseblocks_v2_1_1_mux_enc__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_AWID[0] in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_WLAST in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_ARID[0] in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_ARLEN[7] in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_ARLEN[6] in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_ARLEN[5] in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_ARLEN[4] in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_ARLEN[3] in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_ARLEN[2] in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_ARLEN[1] in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_ARLEN[0] in module axi_crossbar_v2_1_30_decerr_slave is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ADDR[1] in module axi_crossbar_v2_1_30_addr_decoder is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ADDR[0] in module axi_crossbar_v2_1_30_addr_decoder is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_AWID[0] in module axi_crossbar_v2_1_30_crossbar_sasd is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port S_AXI_ARID[0] in module axi_crossbar_v2_1_30_crossbar_sasd is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port M_AXI_BID[2] in module axi_crossbar_v2_1_30_crossbar_sasd is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port M_AXI_BID[1] in module axi_crossbar_v2_1_30_crossbar_sasd is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port M_AXI_BID[0] in module axi_crossbar_v2_1_30_crossbar_sasd is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port M_AXI_RID[2] in module axi_crossbar_v2_1_30_crossbar_sasd is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port M_AXI_RID[1] in module axi_crossbar_v2_1_30_crossbar_sasd is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port M_AXI_RID[0] in module axi_crossbar_v2_1_30_crossbar_sasd is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awid[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[7] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[6] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[5] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[4] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[3] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awsize[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awsize[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awsize[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awburst[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awburst[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlock[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awcache[3] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awcache[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awcache[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awcache[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awqos[3] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awqos[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awqos[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awqos[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awuser[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_wid[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_wlast[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_wuser[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arid[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[7] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[6] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[5] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[4] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[3] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arsize[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arsize[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arsize[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arburst[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arburst[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlock[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arcache[3] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arcache[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arcache[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arcache[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arqos[3] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arqos[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arqos[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arqos[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_aruser[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_bid[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_bid[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_bid[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_buser[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_buser[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_buser[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_rid[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_rid[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_rid[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_rlast[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_rlast[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_rlast[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_ruser[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_ruser[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_ruser[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2315.375 ; gain = 593.684 ; free physical = 31245 ; free virtual = 93076
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2315.375 ; gain = 593.684 ; free physical = 31245 ; free virtual = 93075
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2315.375 ; gain = 593.684 ; free physical = 31245 ; free virtual = 93075
|
||||
---------------------------------------------------------------------------------
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2315.375 ; gain = 0.000 ; free physical = 31245 ; free virtual = 93075
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_ooc.xdc] for cell 'inst'
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/NewExtInst_TOP_xbar_0_ooc.xdc] for cell 'inst'
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/dont_touch.xdc]
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/dont_touch.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2412.219 ; gain = 0.000 ; free physical = 31249 ; free virtual = 93079
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2412.254 ; gain = 0.000 ; free physical = 31248 ; free virtual = 93078
|
||||
INFO: [Designutils 20-5008] Incremental synthesis strategy off
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 31275 ; free virtual = 93110
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7z035ffg676-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 31275 ; free virtual = 93110
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/dont_touch.xdc, line 9).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 31275 ; free virtual = 93111
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 31261 ; free virtual = 93097
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
64 Bit Registers := 1
|
||||
36 Bit Registers := 2
|
||||
4 Bit Registers := 1
|
||||
3 Bit Registers := 1
|
||||
2 Bit Registers := 3
|
||||
1 Bit Registers := 14
|
||||
+---Muxes :
|
||||
2 Input 64 Bit Muxes := 1
|
||||
2 Input 36 Bit Muxes := 2
|
||||
2 Input 4 Bit Muxes := 1
|
||||
2 Input 3 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 36
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 900 (col length:140)
|
||||
BRAMs: 1000 (col length: RAMB18 140 RAMB36 70)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
|
||||
INFO: [Synth 8-3936] Found unconnected internal register 'gen_sasd.crossbar_sasd_0/reg_slice_r/m_payload_i_reg' and it is trimmed from '36' to '35' bits. [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726]
|
||||
WARNING: [Synth 8-7129] Port s_axi_awid[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[7] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[6] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[5] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[4] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[3] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awsize[2] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awsize[1] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awsize[0] in module axi_crossbar_v2_1_30_axi_crossbar is either unconnected or has no load
|
||||
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 31159 ; free virtual = 92994
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 31970 ; free virtual = 93803
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 32217 ; free virtual = 94049
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 32212 ; free virtual = 94044
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 33246 ; free virtual = 95077
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 33246 ; free virtual = 95077
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 33246 ; free virtual = 95077
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 33246 ; free virtual = 95077
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 33246 ; free virtual = 95077
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 33246 ; free virtual = 95077
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-----+------+
|
||||
| |Cell |Count |
|
||||
+------+-----+------+
|
||||
|1 |LUT1 | 1|
|
||||
|2 |LUT2 | 8|
|
||||
|3 |LUT3 | 39|
|
||||
|4 |LUT4 | 49|
|
||||
|5 |LUT5 | 33|
|
||||
|6 |LUT6 | 42|
|
||||
|7 |FDRE | 131|
|
||||
+------+-----+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 33246 ; free virtual = 95077
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 67 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2412.254 ; gain = 593.684 ; free physical = 33259 ; free virtual = 95091
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2412.254 ; gain = 690.562 ; free physical = 33259 ; free virtual = 95091
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2412.254 ; gain = 0.000 ; free physical = 33519 ; free virtual = 95350
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2412.254 ; gain = 0.000 ; free physical = 33517 ; free virtual = 95348
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Synth Design complete | Checksum: f26108b
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
53 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 2412.254 ; gain = 1114.926 ; free physical = 33515 ; free virtual = 95346
|
||||
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1765.393; main = 1479.902; forked = 307.549
|
||||
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3382.863; main = 2412.223; forked = 1002.656
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2436.230 ; gain = 0.000 ; free physical = 33515 ; free virtual = 95346
|
||||
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0.dcp' has been generated.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP NewExtInst_TOP_xbar_0, cache-ID = 244f670d2d87c357
|
||||
INFO: [Coretcl 2-1174] Renamed 7 cell refs.
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2436.230 ; gain = 0.000 ; free physical = 33505 ; free virtual = 95337
|
||||
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_xbar_0_synth_1/NewExtInst_TOP_xbar_0.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file NewExtInst_TOP_xbar_0_utilization_synth.rpt -pb NewExtInst_TOP_xbar_0_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri May 15 15:27:02 2026...
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user