Jeremy Shen
95c04d94ae
Rename erase_before_program → erase_all (semantics fix): - erase_all: true → -erase_all -erase_only (entire flash chip) - erase_all: false → -erase_only (sectors matching BIN size) Both options always erase; the checkbox controls scope, not yes/no. UI additions: - SubStepFrame widget: collapsible Erase/Program/Verify sub-steps with status dots (○/◉/●) and colored labels - Automatically expands on Step 2 start, collapses on completion - Phase and progress driven by real-time program_flash output parsing - Checkbox label: '整片Flash擦除 (Erase entire flash)' subprocess_utils.py phase detection: - Parses 'Performing Erase/Program/Verify Operation' for phase transitions - Emits 'phase' callbacks (erase/program/verify/done) - Progress % tracked within current phase
54 lines
1.7 KiB
YAML
54 lines
1.7 KiB
YAML
# Default configuration for Zynq XC7Z100 Flasher
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# Paths are relative to this config file's directory.
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# Vitis/Vivado installation path (where bootgen, impact, etc. reside)
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vitis_path: ""
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# Zynq device network settings
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zynq_ip: "192.168.100.11"
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tftp_upload_name: "z7bin"
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# Serial port settings
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serial_port: ""
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serial_baudrate: 115200
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# File paths (relative to config file directory)
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# Bootloader files (Step 3: Load Bootloader)
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bootloader_bit_path: ""
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bootloader_elf_path: ""
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# Flash programming (Step 2: Program & Verify Flash)
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# bootloader_bin_path is the bootloader image to program into QSPI flash
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# fsbl_elf_path is the FSBL (First Stage Boot Loader) required by program_flash
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# flash_type sets the QSPI interface mode (qspi-x4-single, qspi-x8-dual_parallel, etc.)
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# erase_all: if true, erase entire flash chip; if false, only erase sectors needed
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bootloader_bin_path: ""
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fsbl_elf_path: ""
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flash_type: "qspi-x4-single"
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flash_model: "s25fl256s1"
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erase_all: false
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# Firmware upload (Step 4: Load Main Program via TFTP)
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firmware_bin_path: ""
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# Reboot settings
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reboot_timeout: 30
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# Ping verification settings
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ping_timeout: 5
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ping_count: 3
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# Step timing (seconds) — used for progress bar max and timeout (experience × 2)
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step_timeouts:
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check_env: 30 # Step 1: tool detection + JTAG scan (~5s actual)
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flash_erase: 120 # Step 2a: QSPI chip erase (~40s actual for 17MB)
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flash_program: 600 # Step 2b: QSPI program+verify (~300s actual for 17MB at x4)
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bitstream: 60 # Step 3a: FPGA configuration via JTAG (~16s actual)
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elf_download: 60 # Step 3b: ELF download to PS via JTAG (~9s actual)
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tftp_reboot: 120 # Step 4: TFTP upload + reboot + boot verify (~30s network)
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# Delays (seconds)
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inter_step_delay: 2
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uart_delay: 3
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