yuysh
1619dc194f
Previously the boot wait loop broke on the first detection of EITHER IP or version. The Zynq firmware outputs its version string early in the boot sequence (e.g. firmware header), while the board IP arrives in a later burst via 'Boot=, IP=192.168.100.13, Ver=...'. The loop would break on the version-only signal, leaving IP empty. Changes: 1. Phase 1: log boot signal (version) but keep polling for IP 2. Phase 2: break only when IP address is actually found 3. After timeout: final check of latest_info for late-arriving IP 4. UART buffer fallback: parse all accumulated lines for IP (handles lines that arrived between the last poll and exit) 5. 3s pre-scan delay before UDP discover to let network stack settle (board's UDP server starts at the very end of boot sequence)