feat: boot mode parsing, FSBL-first flow, UI reorder

1. Boot mode parsing:
   - BootInfo.boot_mode field added
   - Matches 'Boot mode is JTAG', 'Boot Mode: QSPI', etc.
   - Fixed false version match: 'Boot mode is' no longer
     captures 'mode' as a version string

2. UART window cleanup:
   - Parsed boot info (mode/IP/ver) now only goes to main log
   - Raw serial lines still appear in UART window

3. Step 3 FSBL enforcement:
   - BIT step: after fpga -file, CPU is immediately halted (stop)
     to prevent Flash code from enabling MMU
   - ELF step: always dow FSBL → con → stop → dow bootloader

4. UI reorder:
   - FSBL ELF selector moved BEFORE Bootloader BIT
   - New layout: FSBL → BIT → ELF → Bootloader BIN → Flash → FW BIN
   - Fixed grid overlap (FSBL and Flash were both at row 6)

src/bitstream_programmer.py

@@ -214,7 +214,7 @@ def _program_with_xsct(
     if callback:
         callback("progress", "Initializing PS then programming FPGA...")
 
-    # Build TCL: PS init first, then FPGA config, then post-config
+    # Build TCL: PS init → FPGA config → post-config → halt CPU → disable Flash boot
     lines = ["connect"]
     if ps7_init_tcl and Path(ps7_init_tcl).exists():
         lines.append("targets 1")
@@ -227,6 +227,11 @@ def _program_with_xsct(
         lines.append("ps7_post_config")
         if callback:
             callback("progress", "PS post-config (PL-PS interfaces)")
+    # After FPGA config, CPU may be reset — halt it to prevent Flash code
+    # from enabling MMU before the ELF step can download FSBL
+    lines.append("targets 2")
+    lines.append("after 100")
+    lines.append("stop")
     # Prevent boot from Flash by disabling PCAP reconfiguration
     lines.append("mwr 0xF800025C 0x00000001")
     lines.append("exit")