118 lines
3.4 KiB
C
118 lines
3.4 KiB
C
/*
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* Copyright (C) 2016 - 2019 Xilinx, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
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* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*
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*/
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#include <stdio.h>
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#include "xparameters.h"
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#if defined (__arm__) || defined(__aarch64__)
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#include "xil_printf.h"
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#endif
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#ifdef XPS_BOARD_ZCU102
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#ifdef XPAR_XIICPS_0_DEVICE_ID
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#include "xiicps.h"
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#define BUF_LEN 10U
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#define IOEXPANDER1_ADDR 0x20U
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#define IIC_SCLK_RATE_IOEXP 400000
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#define CMD_CFG_0_REG 0x06U
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#define CMD_OUTPUT_0_REG 0x02U
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#define DATA_OUTPUT 0x0U
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#define DATA_COMMON_CFG 0xE0U
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#define DATA_GT_0000_CFG 0x00U
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XIicPs I2c0InstancePtr;
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int IicPhyReset(void)
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{
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u8 WriteBuffer[BUF_LEN] = {0};
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XIicPs_Config *I2c0CfgPtr;
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int Status = XST_SUCCESS;
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/* Initialize the IIC0 driver so that it is ready to use */
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I2c0CfgPtr = XIicPs_LookupConfig(XPAR_XIICPS_0_DEVICE_ID);
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if (I2c0CfgPtr == NULL) {
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Status = XST_FAILURE;
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return Status;
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}
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Status = XIicPs_CfgInitialize(&I2c0InstancePtr, I2c0CfgPtr,
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I2c0CfgPtr->BaseAddress);
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if (Status != XST_SUCCESS) {
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Status = XST_FAILURE;
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return Status;
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}
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/* Set the IIC serial clock rate */
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XIicPs_SetSClk(&I2c0InstancePtr, IIC_SCLK_RATE_IOEXP);
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/* Configure I/O pins as Output */
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WriteBuffer[0] = CMD_CFG_0_REG;
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WriteBuffer[1] = DATA_OUTPUT;
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Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
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WriteBuffer, 2, IOEXPANDER1_ADDR);
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if (Status != XST_SUCCESS) {
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Status = XST_FAILURE;
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return Status;
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}
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/* Wait until bus is idle to start another transfer */
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while (XIicPs_BusIsBusy(&I2c0InstancePtr));
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/*
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* Deasserting I2C_MUX_RESETB
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* And GEM3 Resetb
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* Selecting lanes based on configuration
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*/
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WriteBuffer[0] = CMD_OUTPUT_0_REG;
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/* gt0000 or no GT configuration */
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WriteBuffer[1] = DATA_COMMON_CFG | DATA_GT_0000_CFG;
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/* Send the Data */
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Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
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WriteBuffer, 2, IOEXPANDER1_ADDR);
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if (Status != XST_SUCCESS) {
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Status = XST_FAILURE;
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return Status;
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}
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/* Wait until bus is idle */
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while (XIicPs_BusIsBusy(&I2c0InstancePtr));
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xil_printf("IIC PHY reset on ZCU102 successful \n\r");
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return XST_SUCCESS;
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}
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#endif
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#endif
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