319 lines
6.8 KiB
C
319 lines
6.8 KiB
C
/*
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* cal_meas.c
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*
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* Created on: 2023年7月19日
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* Author: dell
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*/
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#include "cal_meas.h"
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#include "SPI_Driv.h"
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char sw_config_data[3] = {0x00,0x00,0x00};
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int Command_Parser(u8* recvbuffer)
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{
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switch (recvbuffer[0])
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{
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case 0xA0:
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{
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xil_printf("[D] Matched Command Reset\r\n");
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rst_CPLD(CPLD_U1,4);
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rst_CPLD(CPLD_U2,4);
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rst_CPLD(CPLD_U3,4);
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xil_printf("[I] CPLD RST Done\r\n");
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break;
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}
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case 0xA1: //PMU Cal
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{
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break;
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}
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case 0xA2: //Freq Cal
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{
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break;
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}
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default:
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{
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xil_printf("[E] Command Header No Match! \r\n[D] Received Command Header:0x%02X Check Command!\r\n",recvbuffer[0]);
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break;
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}
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}
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}
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int CPLD_Write(u8 addr,u32 data)
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{
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u16 reg_addr = addr | 0x80; //Write bit set to 1'b1
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//Data Sanity Check
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if ((data >> 24) > 0)
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{
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/* code */
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xil_printf("[E] CPLD data length should within 24 bits!\r\n");
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return XST_FAILURE;
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}
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spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U1);
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spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U2);
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spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U3);
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}
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int CPLD_exec()
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{
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u8 reg_addr = 0x01;
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sw_config_data[0] = 0x00;
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sw_config_data[1] = 0x00;
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sw_config_data[2] = 0x01;
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reg_addr = reg_addr | 0x80;
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spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U1);
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spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U2);
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spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U3);
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return XST_SUCCESS;
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}
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void sw_config(char *slot_start)
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{
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char slot = (*slot_start);
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char m_fun = *(slot_start+1);
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char ch_num_h = *(slot_start+2);
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char ch_num_l = *(slot_start+3);
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char volt_cur = *(slot_start+4);
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char load = *(slot_start+5);
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char memt_areal = *(slot_start+6);
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u16 ch_num = 0;
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u32 ch_num_dat = 0;
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u32 relay_ctrl = 0;
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u32 slot_en = 0x00000001;
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u8 cpld_addr = 0;
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u32 cpld_dat = 0;
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ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
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if(slot==1)
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{
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cpld_addr = 0x82;
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}
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else if(slot==2)
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{
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cpld_addr = 0x83;
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}
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else if(slot==3)
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{
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cpld_addr = 0x84;
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}
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else
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{
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cpld_addr = 0x85;
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}
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switch(ch_num)
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{
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case 0x0001:
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{
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relay_ctrl = 0x00000000;
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break;
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}
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case 0x0002:
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{
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relay_ctrl = 0x00020000;
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break;
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}
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case 0x0003:
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{
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relay_ctrl = 0x00200000;
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break;
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}
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case 0x0004:
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{
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relay_ctrl = 0x00220000;
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break;
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}
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case 0x0005:
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{
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relay_ctrl = 0x00800000;
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break;
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}
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case 0x0006:
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{
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relay_ctrl = 0x00810000;
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break;
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}
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case 0x0007:
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{
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relay_ctrl = 0x00A00000;
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break;
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}
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case 0x0008:
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{
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relay_ctrl = 0x00A10000;
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break;
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}
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case 0x0041:
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{
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relay_ctrl = 0x00000000;
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break;
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}
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case 0x0042:
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{
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relay_ctrl = 0x00008000;
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break;
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}
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case 0x0043:
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{
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relay_ctrl = 0x00100000;
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break;
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}
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case 0x0044:
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{
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relay_ctrl = 0x00108000;
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break;
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}
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case 0x0045:
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{
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relay_ctrl = 0x00800000;
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break;
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}
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case 0x0046:
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{
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relay_ctrl = 0x00804000;
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break;
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}
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case 0x0047:
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{
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relay_ctrl = 0x00900000;
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break;
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}
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case 0x0048:
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{
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relay_ctrl = 0x00904000;
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break;
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}
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case 0x0081:
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{
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relay_ctrl = 0x00000000;
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break;
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}
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case 0x0082:
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{
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relay_ctrl = 0x00002000;
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break;
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}
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case 0x0083:
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{
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relay_ctrl = 0x00080000;
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break;
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}
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case 0x0084:
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{
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relay_ctrl = 0x00082000;
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break;
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}
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case 0x0085:
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{
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relay_ctrl = 0x00400000;
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break;
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}
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case 0x0086:
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{
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relay_ctrl = 0x00401000;
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break;
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}
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case 0x0087:
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{
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relay_ctrl = 0x00480000;
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break;
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}
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case 0x0088:
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{
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relay_ctrl = 0x00481000;
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break;
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}
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case 0x00C1:
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{
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relay_ctrl = 0x00000000;
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break;
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}
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case 0x00C2:
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{
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relay_ctrl = 0x00000800;
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break;
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}
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case 0x00C3:
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{
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relay_ctrl = 0x00040000;
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break;
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}
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case 0x00C4:
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{
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relay_ctrl = 0x00040800;
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break;
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}
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case 0x00C5:
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{
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relay_ctrl = 0x00400000;
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break;
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}
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case 0x00C6:
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{
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relay_ctrl = 0x00400400;
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break;
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}
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case 0x00C7:
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{
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relay_ctrl = 0x00440000;
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break;
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}
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case 0x00C8:
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{
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relay_ctrl = 0x00440400;
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break;
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}
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}
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ch_num_dat = ((u32)ch_num)<<1;
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cpld_dat = relay_ctrl|ch_num_dat|slot_en;
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sw_config_data[0] = (u8)(cpld_dat>>16);
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sw_config_data[1] = (u8)(cpld_dat>>8);
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sw_config_data[2] = (u8)(cpld_dat);
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xil_printf("relay_ctrl: %d\n\r", relay_ctrl);
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xil_printf("ch_num_dat: %d\n\r", ch_num_dat);
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xil_printf("cpld_addr: %d\n\r", cpld_addr);
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xil_printf("cpld_dat: %d\n\r", cpld_dat);
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xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[0]);
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xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[1]);
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xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[2]);
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spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
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spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
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spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
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sw_config_data[0] = 0x00;
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sw_config_data[1] = 0x00;
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sw_config_data[2] = 0x01;
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spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U1);
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spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U2);
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spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U3);
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slot_en = 0x00000000;
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cpld_dat = relay_ctrl|ch_num_dat|slot_en;
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sw_config_data[0] = (u8)(cpld_dat>>16);
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sw_config_data[1] = (u8)(cpld_dat>>8);
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sw_config_data[2] = (u8)(cpld_dat);
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spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
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spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
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spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
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}
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