/*
 * cal_meas.c
 *
 *  Created on: 2023年7月19日
 *      Author: dell
 */

#include "cal_meas.h"
#include "SPI_Driv.h"
char     sw_config_data[3] = {0x00,0x00,0x00};

int Command_Parser(u8* recvbuffer)
{
	switch (recvbuffer[0])
	{
		case 0xA0:
		{
			xil_printf("[D] Matched Command Reset\r\n");
			rst_CPLD(CPLD_U1,4);
			rst_CPLD(CPLD_U2,4);
			rst_CPLD(CPLD_U3,4);
			xil_printf("[I] CPLD RST Done\r\n");
			break;
		}
		case 0xA1:			//PMU Cal
		{
			break;
		}
		case 0xA2:			//Freq Cal
		{

			break;
		}
		
		default:
		{
			xil_printf("[E] Command Header No Match! \r\n[D] Received Command Header:0x%02X Check Command!\r\n",recvbuffer[0]);
			break;
		}
		
	}
}

int CPLD_Write(u8 addr,u32 data)
{
	u16 reg_addr = addr | 0x80;				//Write bit set to 1'b1
	//Data Sanity Check
	if ((data >> 24) > 0)
	{
		/* code */
		xil_printf("[E] CPLD data length should within 24 bits!\r\n");
		return XST_FAILURE;
	}
	spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U1);
	spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U2);
	spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U3);
}

int CPLD_exec()
{
	u8 reg_addr = 0x01;

	sw_config_data[0] = 0x00;
	sw_config_data[1] = 0x00;
	sw_config_data[2] = 0x01;

	reg_addr = reg_addr | 0x80;
	spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U1);
	spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U2);
	spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U3);

	return XST_SUCCESS;
}

void  sw_config(char *slot_start)
{
		 char  slot       = (*slot_start);
		 char  m_fun      = *(slot_start+1);
		 char  ch_num_h   = *(slot_start+2);
		 char  ch_num_l   = *(slot_start+3);
		 char  volt_cur   = *(slot_start+4);
		 char  load       = *(slot_start+5);
		 char  memt_areal = *(slot_start+6);

		 u16 	 ch_num     = 0;
		 u32     ch_num_dat = 0;
		 u32     relay_ctrl = 0;
		 u32     slot_en    = 0x00000001;

		 u8      cpld_addr = 0;
		 u32     cpld_dat  = 0;

		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);


		 if(slot==1)
		 {
			 cpld_addr = 0x82;
		 }
		 else if(slot==2)
		 {
			 cpld_addr = 0x83;
		 }
		 else if(slot==3)
		 {
			 cpld_addr = 0x84;
		 }
		 else
		 {
			 cpld_addr = 0x85;
		 }

		 switch(ch_num)
		 {
		   case 0x0001:
		 	   {
		 		   relay_ctrl = 0x00000000;
		 		   break;
		 	   }
		   case 0x0002:
		   	   {
		   		   relay_ctrl = 0x00020000;
		   		   break;
		   	   }
		   case 0x0003:
		   	   {
		   		   relay_ctrl = 0x00200000;
		   		   break;
		   	   }
		   case 0x0004:
		   	   {
		   		   relay_ctrl = 0x00220000;
		   		   break;
		   	   }
		   case 0x0005:
		   	   {
		   		   relay_ctrl = 0x00800000;
		   		   break;
		   	   }
		   case 0x0006:
		   	   {
		   		   relay_ctrl = 0x00810000;
		   		   break;
		   	   }
		   case 0x0007:
		   	   {
		   		   relay_ctrl = 0x00A00000;
		   		   break;
		   	   }
		   case 0x0008:
		   	   {
		   		   relay_ctrl = 0x00A10000;
		   		   break;
		   	   }
		   case 0x0041:
		   	   {
		   		   relay_ctrl = 0x00000000;
		   		   break;
		   	   }
		   case 0x0042:
		   	   {
		   		   relay_ctrl = 0x00008000;
		   		   break;
		   	   }
		   case 0x0043:
		   	   {
		   		   relay_ctrl = 0x00100000;
		   		   break;
		   	   }
		   case 0x0044:
		   	   {
		   		   relay_ctrl = 0x00108000;
		   		   break;
		   	   }
		   case 0x0045:
		   	   {
		   		   relay_ctrl = 0x00800000;
		   		   break;
		   	   }
		   case 0x0046:
		   	   {
		   		   relay_ctrl = 0x00804000;
		   		   break;
		   	   }
		   case 0x0047:
		   	   {
		   		   relay_ctrl = 0x00900000;
		   		   break;
		   	   }
		   case 0x0048:
		   	   {
		   		   relay_ctrl = 0x00904000;
		   		   break;
		   	   }
		   case 0x0081:
		   	   {
		   		   relay_ctrl = 0x00000000;
		   		   break;
		   	   }
		   case 0x0082:
		   	   {
		   		   relay_ctrl = 0x00002000;
		   		   break;
		   	   }
		   case 0x0083:
		   	   {
		   		   relay_ctrl = 0x00080000;
		   		   break;
		   	   }
		   case 0x0084:
		   	   {
		   		   relay_ctrl = 0x00082000;
		   		   break;
		   	   }
		   case 0x0085:
		   	   {
		   		   relay_ctrl = 0x00400000;
		   		   break;
		   	   }
		   case 0x0086:
		   	   {
		   		   relay_ctrl = 0x00401000;
		   		   break;
		   	   }
		   case 0x0087:
		   	   {
		   		   relay_ctrl = 0x00480000;
		   		   break;
		   	   }
		   case 0x0088:
		   	   {
		   		   relay_ctrl = 0x00481000;
		   		   break;
		   	   }
		   case 0x00C1:
		   	   {
		   		   relay_ctrl = 0x00000000;
		   		   break;
		   	   }
		   case 0x00C2:
		   	   {
		   		   relay_ctrl = 0x00000800;
		   		   break;
		   	   }
		   case 0x00C3:
		   	   {
		   		   relay_ctrl = 0x00040000;
		   		   break;
		   	   }
		   case 0x00C4:
		   	   {
		   		   relay_ctrl = 0x00040800;
		   		   break;
		   	   }
		   case 0x00C5:
		   	   {
		   		   relay_ctrl = 0x00400000;
		   		   break;
		   	   }
		   case 0x00C6:
		   	   {
		   		   relay_ctrl = 0x00400400;
		   		   break;
		   	   }
		   case 0x00C7:
		   	   {
		   		   relay_ctrl = 0x00440000;
		   		   break;
		   	   }
		   case 0x00C8:
		   	   {
		   		   relay_ctrl = 0x00440400;
		   		   break;
		   	   }
		 }

		 ch_num_dat = ((u32)ch_num)<<1;
		 cpld_dat   = relay_ctrl|ch_num_dat|slot_en;

		 sw_config_data[0] = (u8)(cpld_dat>>16);
		 sw_config_data[1] = (u8)(cpld_dat>>8);
		 sw_config_data[2] = (u8)(cpld_dat);

		 xil_printf("relay_ctrl: %d\n\r", relay_ctrl);
		 xil_printf("ch_num_dat: %d\n\r", ch_num_dat);

		 xil_printf("cpld_addr: %d\n\r",  cpld_addr);
		 xil_printf("cpld_dat: %d\n\r",   cpld_dat);

		 xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[0]);
		 xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[1]);
		 xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[2]);

		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);

		 sw_config_data[0] = 0x00;
		 sw_config_data[1] = 0x00;
		 sw_config_data[2] = 0x01;
		 spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U1);
		 spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U2);
		 spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U3);

		 slot_en   = 0x00000000;
		 cpld_dat   = relay_ctrl|ch_num_dat|slot_en;

		 sw_config_data[0] = (u8)(cpld_dat>>16);
		 sw_config_data[1] = (u8)(cpld_dat>>8);
		 sw_config_data[2] = (u8)(cpld_dat);

		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
		 spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
}