Add LWIP CMD Server Stack

Add lwip cmd server
Add CPLD_Con.c/h: Move CPLD Control Code to seperate file.
2026-06-18 09:59:22 +08:00 · 2026-06-17 15:47:27 +08:00 · 2026-06-01 10:50:36 +08:00 · 2026-05-29 18:18:49 +08:00 · 2026-05-29 14:11:26 +08:00 · 2026-05-28 18:39:13 +08:00
55 changed files with 1407 additions and 10414 deletions
@@ -24,6 +24,9 @@
 # Directory: <ProjectName>.cache/ - regenerated by Vivado
 *.cache/
 # ----- Logs -----
 *.log
 # ----- Vivado Generated Sources -----
 # Directory: <ProjectName>.gen/ - keep HDL, ignore sim files
 *.gen/*/ip/*/sim/
@@ -1,845 +0,0 @@
 *** Running vivado
    with args -log system_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace
 ****** Vivado v2023.2 (64-bit)
  **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
  **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
  **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
 source system_wrapper.tcl -notrace
 INFO: [IP_Flow 19-234] Refreshing IP repositories
 INFO: [IP_Flow 19-1704] No user IP repositories specified
 INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'.
 Command: link_design -top system_wrapper -part xc7z035ffg676-2
 Design is defaulting to srcset: sources_1
 Design is defaulting to constrset: constrs_1
 INFO: [Device 21-403] Loading part xc7z035ffg676-2
 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1722.395 ; gain = 0.000 ; free physical = 1995 ; free virtual = 71203
 INFO: [Netlist 29-17] Analyzing 39 Unisim elements for replacement
 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
 INFO: [Project 1-479] Netlist was created with Vivado 2023.2
 INFO: [Project 1-570] Preparing netlist for logic optimization
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
 WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-11' -to list should not be empty. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc:50]
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
 INFO: [Project 1-1687] 1 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design.
 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2307.883 ; gain = 0.000 ; free physical = 1722 ; free virtual = 70993
 INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 33 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 33 instances
 11 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
 link_design completed successfully
 link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2307.883 ; gain = 962.004 ; free physical = 1730 ; free virtual = 71000
 Command: opt_design
 Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
 Running DRC as a precondition to command opt_design
 Starting DRC Task
 INFO: [DRC 23-27] Running DRC with 8 threads
 INFO: [Project 1-461] DRC finished with 0 Errors
 INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
 Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2307.883 ; gain = 0.000 ; free physical = 1727 ; free virtual = 71012
 Starting Cache Timing Information Task
 INFO: [Timing 38-35] Done setting XDC timing constraints.
 Ending Cache Timing Information Task | Checksum: 2382775f8
 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2762.520 ; gain = 454.637 ; free physical = 1293 ; free virtual = 70618
 Starting Logic Optimization Task
 Phase 1 Initialization
 Phase 1.1 Core Generation And Design Setup
 Phase 1.1.1 Generate And Synthesize Debug Cores
 INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub 
 INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV.
 INFO: [Chipscope 16-329] Generating Script for core instance : u_ila_0 
 INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:ila:6.2 for cell u_ila_0_CV.
 Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3095.020 ; gain = 0.000 ; free physical = 9128 ; free virtual = 68708
 Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3201.777 ; gain = 0.000 ; free physical = 8923 ; free virtual = 68563
 Netlist sorting complete. Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.24 . Memory (MB): peak = 3378.160 ; gain = 0.000 ; free physical = 8306 ; free virtual = 68085
 Phase 1.1.1 Generate And Synthesize Debug Cores | Checksum: 1a85f7bbe
 Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8306 ; free virtual = 68085
 Phase 1.1 Core Generation And Design Setup | Checksum: 1a85f7bbe
 Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8306 ; free virtual = 68085
 Phase 1.2 Setup Constraints And Sort Netlist
 Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1a85f7bbe
 Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8306 ; free virtual = 68086
 Phase 1 Initialization | Checksum: 1a85f7bbe
 Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8300 ; free virtual = 68083
 Phase 2 Timer Update And Timing Data Collection
 Phase 2.1 Timer Update
 Phase 2.1 Timer Update | Checksum: 1a85f7bbe
 Time (s): cpu = 00:03:06 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8296 ; free virtual = 68078
 Phase 2.2 Timing Data Collection
 Phase 2.2 Timing Data Collection | Checksum: 1a85f7bbe
 Time (s): cpu = 00:03:06 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8279 ; free virtual = 68065
 Phase 2 Timer Update And Timing Data Collection | Checksum: 1a85f7bbe
 Time (s): cpu = 00:03:06 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8279 ; free virtual = 68065
 Phase 3 Retarget
 INFO: [Opt 31-138] Pushed 1 inverter(s) to 1 load pin(s).
 INFO: [Opt 31-49] Retargeted 0 cell(s).
 Phase 3 Retarget | Checksum: 20e292eaa
 Time (s): cpu = 00:03:07 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8270 ; free virtual = 68062
 Retarget | Checksum: 20e292eaa
 INFO: [Opt 31-389] Phase Retarget created 4 cells and removed 35 cells
 INFO: [Opt 31-1021] In phase Retarget, 99 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
 Phase 4 Constant propagation
 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
 Phase 4 Constant propagation | Checksum: 1fb9c5663
 Time (s): cpu = 00:03:07 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8271 ; free virtual = 68063
 Constant propagation | Checksum: 1fb9c5663
 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 16 cells
 INFO: [Opt 31-1021] In phase Constant propagation, 49 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
 Phase 5 Sweep
 Phase 5 Sweep | Checksum: 1dd19d44b
 Time (s): cpu = 00:03:08 ; elapsed = 00:03:18 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8274 ; free virtual = 68074
 Sweep | Checksum: 1dd19d44b
 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 46 cells
 INFO: [Opt 31-1021] In phase Sweep, 956 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
 Phase 6 BUFG optimization
 INFO: [Opt 31-194] Inserted BUFG system_i/dna_port_read_0/inst/read_vld_BUFG_inst to drive 57 load(s) on clock net system_i/dna_port_read_0/inst/read_vld_BUFG
 INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
 Phase 6 BUFG optimization | Checksum: 202feca59
 Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8266 ; free virtual = 68070
 BUFG optimization | Checksum: 202feca59
 INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 0 cells.
 Phase 7 Shift Register Optimization
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_A due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_B due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/I_YESLUT6.U_SRLC16E due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_A due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_B due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 due to none static srl address bits
 WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 due to none static srl address bits
 INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
 Phase 7 Shift Register Optimization | Checksum: 202feca59
 Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8263 ; free virtual = 68069
 Shift Register Optimization | Checksum: 202feca59
 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
 Phase 8 Post Processing Netlist
 Phase 8 Post Processing Netlist | Checksum: 202feca59
 Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8260 ; free virtual = 68067
 Post Processing Netlist | Checksum: 202feca59
 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
 INFO: [Opt 31-1021] In phase Post Processing Netlist, 57 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
 Phase 9 Finalization
 Phase 9.1 Finalizing Design Cores and Updating Shapes
 Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2572a104c
 Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8258 ; free virtual = 68070
 Phase 9.2 Verifying Netlist Connectivity
 Starting Connectivity Check Task
 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3442.176 ; gain = 0.000 ; free physical = 8255 ; free virtual = 68068
 Phase 9.2 Verifying Netlist Connectivity | Checksum: 2572a104c
 Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8255 ; free virtual = 68068
 Phase 9 Finalization | Checksum: 2572a104c
 Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8255 ; free virtual = 68068
 Opt_design Change Summary
 =========================
 -------------------------------------------------------------------------------------------------------------------------
 |  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
 -------------------------------------------------------------------------------------------------------------------------
 |  Retarget                     |               4  |              35  |                                             99  |
 |  Constant propagation         |               0  |              16  |                                             49  |
 |  Sweep                        |               0  |              46  |                                            956  |
 |  BUFG optimization            |               1  |               0  |                                              0  |
 |  Shift Register Optimization  |               0  |               0  |                                              0  |
 |  Post Processing Netlist      |               0  |               0  |                                             57  |
 -------------------------------------------------------------------------------------------------------------------------
 Ending Logic Optimization Task | Checksum: 2572a104c
 Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8254 ; free virtual = 68068
 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
 Done building netlist checker database: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3442.176 ; gain = 0.000 ; free physical = 8253 ; free virtual = 68067
 Starting Power Optimization Task
 INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
 INFO: [Power 33-23] Power model is not available for DNA_PORT_inst
 INFO: [Pwropt 34-9] Applying IDT optimizations ...
 INFO: [Pwropt 34-10] Applying ODC optimizations ...
 INFO: [Timing 38-35] Done setting XDC timing constraints.
 Running Vector-less Activity Propagation...
 Finished Running Vector-less Activity Propagation
 Starting PowerOpt Patch Enables Task
 INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 3 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
 INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
 Number of BRAM Ports augmented: 3 newly gated: 0 Total Ports: 6
 Ending PowerOpt Patch Enables Task | Checksum: 1c6a995af
 Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.24 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7922 ; free virtual = 67775
 Ending Power Optimization Task | Checksum: 1c6a995af
 Time (s): cpu = 00:00:11 ; elapsed = 00:00:04 . Memory (MB): peak = 3998.043 ; gain = 555.867 ; free physical = 7922 ; free virtual = 67775
 Starting Final Cleanup Task
 Ending Final Cleanup Task | Checksum: 1c6a995af
 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7922 ; free virtual = 67774
 Starting Netlist Obfuscation Task
 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7921 ; free virtual = 67776
 Ending Netlist Obfuscation Task | Checksum: 1b06a1b26
 Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7921 ; free virtual = 67776
 INFO: [Common 17-83] Releasing license: Implementation
 54 Infos, 82 Warnings, 0 Critical Warnings and 0 Errors encountered.
 opt_design completed successfully
 opt_design: Time (s): cpu = 00:03:26 ; elapsed = 00:03:28 . Memory (MB): peak = 3998.043 ; gain = 1690.160 ; free physical = 7921 ; free virtual = 67776
 INFO: [runtcl-4] Executing : report_drc -file system_wrapper_drc_opted.rpt -pb system_wrapper_drc_opted.pb -rpx system_wrapper_drc_opted.rpx
 Command: report_drc -file system_wrapper_drc_opted.rpt -pb system_wrapper_drc_opted.pb -rpx system_wrapper_drc_opted.rpx
 INFO: [IP_Flow 19-1839] IP Catalog is up to date.
 INFO: [DRC 23-27] Running DRC with 8 threads
 INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_drc_opted.rpt.
 report_drc completed successfully
 INFO: [Timing 38-35] Done setting XDC timing constraints.
 INFO: [Timing 38-480] Writing timing data to binary archive.
 Wrote PlaceDB: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7766 ; free virtual = 67648
 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7766 ; free virtual = 67648
 Writing XDEF routing.
 Writing XDEF routing logical nets.
 Write ShapeDB Complete: Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67652
 Writing XDEF routing special nets.
 Wrote RouteStorage: Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67653
 Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67653
 Wrote Device Cache: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67654
 Write Physdb Complete: Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67654
 INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_opt.dcp' has been generated.
 INFO: [Chipscope 16-240] Debug cores have already been implemented
 Command: place_design
 Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
 INFO: [Common 17-83] Releasing license: Implementation
 INFO: [DRC 23-27] Running DRC with 8 threads
 INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
 INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
 Running DRC as a precondition to command place_design
 INFO: [DRC 23-27] Running DRC with 8 threads
 INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
 INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
 Starting Placer Task
 Phase 1 Placer Initialization
 Phase 1.1 Placer Initialization Netlist Sorting
 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7612 ; free virtual = 67560
 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 19758bd7a
 Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7612 ; free virtual = 67559
 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7611 ; free virtual = 67559
 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 8751fbf6
 Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7587 ; free virtual = 67558
 Phase 1.3 Build Placer Netlist Model
 Phase 1.3 Build Placer Netlist Model | Checksum: dd0b0e99
 Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7431 ; free virtual = 67481
 Phase 1.4 Constrain Clocks/Macros
 Phase 1.4 Constrain Clocks/Macros | Checksum: dd0b0e99
 Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7428 ; free virtual = 67479
 Phase 1 Placer Initialization | Checksum: dd0b0e99
 Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7428 ; free virtual = 67479
 Phase 2 Global Placement
 Phase 2.1 Floorplanning
 Phase 2.1 Floorplanning | Checksum: eecb6848
 Time (s): cpu = 00:00:20 ; elapsed = 00:00:11 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7404 ; free virtual = 67474
 Phase 2.2 Update Timing before SLR Path Opt
 Phase 2.2 Update Timing before SLR Path Opt | Checksum: db55687b
 Time (s): cpu = 00:00:23 ; elapsed = 00:00:12 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7407 ; free virtual = 67493
 Phase 2.3 Post-Processing in Floorplanning
 Phase 2.3 Post-Processing in Floorplanning | Checksum: db55687b
 Time (s): cpu = 00:00:24 ; elapsed = 00:00:12 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7401 ; free virtual = 67488
 Phase 2.4 Global Placement Core
 Phase 2.4.1 UpdateTiming Before Physical Synthesis
 Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1e9ca9de9
 Time (s): cpu = 00:00:54 ; elapsed = 00:00:25 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7017 ; free virtual = 67264
 Phase 2.4.2 Physical Synthesis In Placer
 INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 1172 LUT instances to create LUTNM shape
 INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
 INFO: [Physopt 32-1138] End 1 Pass. Optimized 565 nets or LUTs. Breaked 0 LUT, combined 565 existing LUTs and moved 0 existing LUT
 INFO: [Physopt 32-65] No nets found for high-fanout optimization.
 INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
 INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
 INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
 INFO: [Physopt 32-670] No setup violation found.  Shift Register to Pipeline Optimization was not performed.
 INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
 INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
 INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
 INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
 INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7022 ; free virtual = 67279
 Summary of Physical Synthesis Optimizations
 ============================================
 -----------------------------------------------------------------------------------------------------------------------------------------------------------
 |  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
 -----------------------------------------------------------------------------------------------------------------------------------------------------------
 |  LUT Combining                                    |            0  |            565  |                   565  |           0  |           1  |  00:00:00  |
 |  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
 |  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
 |  DSP Register                                     |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
 |  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
 |  Shift Register                                   |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
 |  BRAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
 |  URAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
 |  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
 |  Total                                            |            0  |            565  |                   565  |           0  |           4  |  00:00:01  |
 -----------------------------------------------------------------------------------------------------------------------------------------------------------
 Phase 2.4.2 Physical Synthesis In Placer | Checksum: 2be40b2db
 Time (s): cpu = 00:00:59 ; elapsed = 00:00:28 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7014 ; free virtual = 67290
 Phase 2.4 Global Placement Core | Checksum: 2859c5ffd
 Time (s): cpu = 00:01:01 ; elapsed = 00:00:29 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7011 ; free virtual = 67293
 Phase 2 Global Placement | Checksum: 2859c5ffd
 Time (s): cpu = 00:01:01 ; elapsed = 00:00:29 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7011 ; free virtual = 67293
 Phase 3 Detail Placement
 Phase 3.1 Commit Multi Column Macros
 Phase 3.1 Commit Multi Column Macros | Checksum: 1ea091a8d
 Time (s): cpu = 00:01:05 ; elapsed = 00:00:30 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7007 ; free virtual = 67305
 Phase 3.2 Commit Most Macros & LUTRAMs
 Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 29969cf51
 Time (s): cpu = 00:01:13 ; elapsed = 00:00:35 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6986 ; free virtual = 67345
 Phase 3.3 Area Swap Optimization
 Phase 3.3 Area Swap Optimization | Checksum: 2b62d77e5
 Time (s): cpu = 00:01:14 ; elapsed = 00:00:35 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6984 ; free virtual = 67343
 Phase 3.4 Pipeline Register Optimization
 Phase 3.4 Pipeline Register Optimization | Checksum: 1ed299be3
 Time (s): cpu = 00:01:14 ; elapsed = 00:00:35 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6982 ; free virtual = 67342
 Phase 3.5 Small Shape Detail Placement
 Phase 3.5.1 Place Remaining
 Phase 3.5.1 Place Remaining | Checksum: 21b5bb37c
 Time (s): cpu = 00:01:20 ; elapsed = 00:00:41 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6918 ; free virtual = 67346
 Phase 3.5 Small Shape Detail Placement | Checksum: 21b5bb37c
 Time (s): cpu = 00:01:20 ; elapsed = 00:00:41 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6849 ; free virtual = 67281
 Phase 3.6 Re-assign LUT pins
 Phase 3.6 Re-assign LUT pins | Checksum: 1a6b845f5
 Time (s): cpu = 00:01:21 ; elapsed = 00:00:42 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6838 ; free virtual = 67277
 Phase 3.7 Pipeline Register Optimization
 Phase 3.7 Pipeline Register Optimization | Checksum: 1a81ce610
 Time (s): cpu = 00:01:21 ; elapsed = 00:00:42 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6834 ; free virtual = 67277
 Phase 3 Detail Placement | Checksum: 1a81ce610
 Time (s): cpu = 00:01:21 ; elapsed = 00:00:42 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6828 ; free virtual = 67276
 Phase 4 Post Placement Optimization and Clean-Up
 Phase 4.1 Post Commit Optimization
 INFO: [Timing 38-35] Done setting XDC timing constraints.
 Phase 4.1.1 Post Placement Optimization
 Post Placement Optimization Initialization | Checksum: 1472dfedc
 Phase 4.1.1.1 BUFG Insertion
 Starting Physical Synthesis Task
 Phase 1 Physical Synthesis Initialization
 INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.626 | TNS=0.000 |
 Phase 1 Physical Synthesis Initialization | Checksum: a925bbef
 Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6782 ; free virtual = 67315
 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
 Ending Physical Synthesis Task | Checksum: a925bbef
 Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6769 ; free virtual = 67309
 Phase 4.1.1.1 BUFG Insertion | Checksum: 1472dfedc
 Time (s): cpu = 00:01:38 ; elapsed = 00:00:50 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6768 ; free virtual = 67314
 Phase 4.1.1.2 Post Placement Timing Optimization
 INFO: [Place 30-746] Post Placement Timing Summary WNS=2.626. For the most accurate timing information please run report_timing.
 Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 14f55351a
 Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6755 ; free virtual = 67307
 Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6755 ; free virtual = 67307
 Phase 4.1 Post Commit Optimization | Checksum: 14f55351a
 Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6755 ; free virtual = 67307
 Phase 4.2 Post Placement Cleanup
 Phase 4.2 Post Placement Cleanup | Checksum: 14f55351a
 Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6750 ; free virtual = 67308
 Phase 4.3 Placer Reporting
 Phase 4.3.1 Print Estimated Congestion
 INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
 |           | Global Congestion | Short Congestion  |
 | Direction | Region Size       | Region Size       |
 |___________|___________________|___________________|
 |      North|                2x2|                2x2|
 |___________|___________________|___________________|
 |      South|                1x1|                1x1|
 |___________|___________________|___________________|
 |       East|                1x1|                1x1|
 |___________|___________________|___________________|
 |       West|                1x1|                1x1|
 |___________|___________________|___________________|
 Phase 4.3.1 Print Estimated Congestion | Checksum: 14f55351a
 Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6748 ; free virtual = 67312
 Phase 4.3 Placer Reporting | Checksum: 14f55351a
 Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6751 ; free virtual = 67321
 Phase 4.4 Final Placement Cleanup
 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6751 ; free virtual = 67321
 Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6751 ; free virtual = 67321
 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 19c30fa75
 Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6741 ; free virtual = 67314
 Ending Placer Task | Checksum: dcf0239e
 Time (s): cpu = 00:01:41 ; elapsed = 00:00:53 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6725 ; free virtual = 67298
 90 Infos, 82 Warnings, 0 Critical Warnings and 0 Errors encountered.
 place_design completed successfully
 place_design: Time (s): cpu = 00:01:44 ; elapsed = 00:00:54 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6725 ; free virtual = 67298
 INFO: [runtcl-4] Executing : report_io -file system_wrapper_io_placed.rpt
 report_io: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6722 ; free virtual = 67295
 INFO: [runtcl-4] Executing : report_utilization -file system_wrapper_utilization_placed.rpt -pb system_wrapper_utilization_placed.pb
 INFO: [runtcl-4] Executing : report_control_sets -verbose -file system_wrapper_control_sets_placed.rpt
 report_control_sets: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6708 ; free virtual = 67293
 INFO: [Timing 38-480] Writing timing data to binary archive.
 Write ShapeDB Complete: Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6731 ; free virtual = 67329
 Wrote PlaceDB: Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6584 ; free virtual = 67235
 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6584 ; free virtual = 67235
 Writing XDEF routing.
 Writing XDEF routing logical nets.
 Writing XDEF routing special nets.
 Wrote RouteStorage: Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6584 ; free virtual = 67236
 Wrote Netlist Cache: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6582 ; free virtual = 67237
 Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6582 ; free virtual = 67238
 Write Physdb Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6581 ; free virtual = 67237
 INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_placed.dcp' has been generated.
 Command: route_design
 Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
 Running DRC as a precondition to command route_design
 INFO: [DRC 23-27] Running DRC with 8 threads
 INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
 INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
 Starting Routing Task
 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
 Phase 1 Build RT Design
 Checksum: PlaceDB: 76da8209 ConstDB: 0 ShapeSum: 6615a195 RouteDB: 0
 Post Restoration Checksum: NetGraph: 4a144a14 | NumContArr: af14b29e | Constraints: c2a8fa9d | Timing: c2a8fa9d
 Phase 1 Build RT Design | Checksum: 27e7af1ec
 Time (s): cpu = 00:00:49 ; elapsed = 00:00:32 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 5905 ; free virtual = 66985
 Phase 2 Router Initialization
 Phase 2.1 Fix Topology Constraints
 Phase 2.1 Fix Topology Constraints | Checksum: 27e7af1ec
 Time (s): cpu = 00:00:50 ; elapsed = 00:00:32 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 5899 ; free virtual = 66984
 Phase 2.2 Pre Route Cleanup
 Phase 2.2 Pre Route Cleanup | Checksum: 27e7af1ec
 Time (s): cpu = 00:00:50 ; elapsed = 00:00:32 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 5899 ; free virtual = 66984
 Number of Nodes with overlaps = 0
 Phase 2.3 Update Timing
 Phase 2.3 Update Timing | Checksum: 32928bcd2
 Time (s): cpu = 00:01:06 ; elapsed = 00:00:40 . Memory (MB): peak = 4046.500 ; gain = 48.457 ; free physical = 5635 ; free virtual = 66801
 INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.632  | TNS=0.000  | WHS=-0.263 | THS=-1616.164|
 Phase 2.4 Update Timing for Bus Skew
 Phase 2.4.1 Update Timing
 Phase 2.4.1 Update Timing | Checksum: 2864114c5
 Time (s): cpu = 00:01:19 ; elapsed = 00:00:43 . Memory (MB): peak = 4046.500 ; gain = 48.457 ; free physical = 5449 ; free virtual = 66672
 INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.632  | TNS=0.000  | WHS=N/A    | THS=N/A    |
 Phase 2.4 Update Timing for Bus Skew | Checksum: 291576a87
 Time (s): cpu = 00:01:19 ; elapsed = 00:00:44 . Memory (MB): peak = 4046.500 ; gain = 48.457 ; free physical = 5447 ; free virtual = 66671
 Router Utilization Summary
  Global Vertical Routing Utilization    = 0.0211705 %
  Global Horizontal Routing Utilization  = 0.00488761 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 38492
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 38484
  Number of Partially Routed Nets     = 8
  Number of Node Overlaps             = 6
 Phase 2 Router Initialization | Checksum: 2a426d310
 Time (s): cpu = 00:01:20 ; elapsed = 00:00:44 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5405 ; free virtual = 66633
 Phase 3 Initial Routing
 Phase 3.1 Global Routing
 Phase 3.1 Global Routing | Checksum: 2a426d310
 Time (s): cpu = 00:01:20 ; elapsed = 00:00:44 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5405 ; free virtual = 66633
 Phase 3.2 Initial Net Routing
 Phase 3.2 Initial Net Routing | Checksum: 22defbe6f
 Time (s): cpu = 00:01:27 ; elapsed = 00:00:46 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5394 ; free virtual = 66641
 Phase 3 Initial Routing | Checksum: 22defbe6f
 Time (s): cpu = 00:01:27 ; elapsed = 00:00:46 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5394 ; free virtual = 66641
 Phase 4 Rip-up And Reroute
 Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 2836
 Number of Nodes with overlaps = 86
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 0
 INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.177  | TNS=0.000  | WHS=N/A    | THS=N/A    |
 Phase 4.1 Global Iteration 0 | Checksum: 23a222cd5
 Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5385 ; free virtual = 66739
 Phase 4 Rip-up And Reroute | Checksum: 23a222cd5
 Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5385 ; free virtual = 66739
 Phase 5 Delay and Skew Optimization
 Phase 5.1 Delay CleanUp
 Phase 5.1 Delay CleanUp | Checksum: 23a222cd5
 Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5384 ; free virtual = 66738
 Phase 5.2 Clock Skew Optimization
 Phase 5.2 Clock Skew Optimization | Checksum: 23a222cd5
 Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5384 ; free virtual = 66738
 Phase 5 Delay and Skew Optimization | Checksum: 23a222cd5
 Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5384 ; free virtual = 66738
 Phase 6 Post Hold Fix
 Phase 6.1 Hold Fix Iter
 Phase 6.1.1 Update Timing
 Phase 6.1.1 Update Timing | Checksum: 2a8514d39
 Time (s): cpu = 00:01:47 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5382 ; free virtual = 66749
 INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.189  | TNS=0.000  | WHS=0.028  | THS=0.000  |
 Phase 6.1 Hold Fix Iter | Checksum: 253fa4620
 Time (s): cpu = 00:01:47 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748
 Phase 6 Post Hold Fix | Checksum: 253fa4620
 Time (s): cpu = 00:01:47 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748
 Phase 7 Route finalize
 Router Utilization Summary
  Global Vertical Routing Utilization    = 2.42898 %
  Global Horizontal Routing Utilization  = 2.87613 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0
 Phase 7 Route finalize | Checksum: 253fa4620
 Time (s): cpu = 00:01:48 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748
 Phase 8 Verifying routed nets
 Verification completed successfully
 Phase 8 Verifying routed nets | Checksum: 253fa4620
 Time (s): cpu = 00:01:48 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748
 Phase 9 Depositing Routes
 Phase 9 Depositing Routes | Checksum: 24ae08112
 Time (s): cpu = 00:01:50 ; elapsed = 00:00:57 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5378 ; free virtual = 66754
 Phase 10 Post Router Timing
 INFO: [Route 35-57] Estimated Timing Summary | WNS=1.189  | TNS=0.000  | WHS=0.028  | THS=0.000  |
 INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
 Phase 10 Post Router Timing | Checksum: 24ae08112
 Time (s): cpu = 00:01:53 ; elapsed = 00:00:58 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5367 ; free virtual = 66762
 INFO: [Route 35-16] Router Completed Successfully
 Phase 11 Post-Route Event Processing
 Phase 11 Post-Route Event Processing | Checksum: 10a817867
 Time (s): cpu = 00:01:54 ; elapsed = 00:00:59 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5358 ; free virtual = 66761
 Ending Routing Task | Checksum: 10a817867
 Time (s): cpu = 00:01:55 ; elapsed = 00:01:00 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5334 ; free virtual = 66752
 Routing Is Done.
 INFO: [Common 17-83] Releasing license: Implementation
 108 Infos, 82 Warnings, 0 Critical Warnings and 0 Errors encountered.
 route_design completed successfully
 route_design: Time (s): cpu = 00:01:59 ; elapsed = 00:01:02 . Memory (MB): peak = 4083.043 ; gain = 85.000 ; free physical = 5335 ; free virtual = 66757
 INFO: [runtcl-4] Executing : report_drc -file system_wrapper_drc_routed.rpt -pb system_wrapper_drc_routed.pb -rpx system_wrapper_drc_routed.rpx
 Command: report_drc -file system_wrapper_drc_routed.rpt -pb system_wrapper_drc_routed.pb -rpx system_wrapper_drc_routed.rpx
 INFO: [IP_Flow 19-1839] IP Catalog is up to date.
 INFO: [DRC 23-27] Running DRC with 8 threads
 INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_drc_routed.rpt.
 report_drc completed successfully
 INFO: [runtcl-4] Executing : report_methodology -file system_wrapper_methodology_drc_routed.rpt -pb system_wrapper_methodology_drc_routed.pb -rpx system_wrapper_methodology_drc_routed.rpx
 Command: report_methodology -file system_wrapper_methodology_drc_routed.rpt -pb system_wrapper_methodology_drc_routed.pb -rpx system_wrapper_methodology_drc_routed.rpx
 INFO: [Timing 38-35] Done setting XDC timing constraints.
 INFO: [DRC 23-133] Running Methodology with 8 threads
 INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_methodology_drc_routed.rpt.
 report_methodology completed successfully
 report_methodology: Time (s): cpu = 00:00:18 ; elapsed = 00:00:06 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5233 ; free virtual = 66738
 INFO: [runtcl-4] Executing : report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx
 Command: report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx
 INFO: [Power 33-23] Power model is not available for DNA_PORT_inst
 INFO: [Timing 38-35] Done setting XDC timing constraints.
 Running Vector-less Activity Propagation...
 Finished Running Vector-less Activity Propagation
 WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
 Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
 119 Infos, 83 Warnings, 0 Critical Warnings and 0 Errors encountered.
 report_power completed successfully
 report_power: Time (s): cpu = 00:00:16 ; elapsed = 00:00:06 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5140 ; free virtual = 66731
 INFO: [runtcl-4] Executing : report_route_status -file system_wrapper_route_status.rpt -pb system_wrapper_route_status.pb
 INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file system_wrapper_timing_summary_routed.rpt -pb system_wrapper_timing_summary_routed.pb -rpx system_wrapper_timing_summary_routed.rpx -warn_on_violation 
 INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
 INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
 WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
 INFO: [runtcl-4] Executing : report_incremental_reuse -file system_wrapper_incremental_reuse_routed.rpt
 INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
 INFO: [runtcl-4] Executing : report_clock_utilization -file system_wrapper_clock_utilization_routed.rpt
 INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file system_wrapper_bus_skew_routed.rpt -pb system_wrapper_bus_skew_routed.pb -rpx system_wrapper_bus_skew_routed.rpx
 INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
 INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
 INFO: [Timing 38-480] Writing timing data to binary archive.
 Write ShapeDB Complete: Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5090 ; free virtual = 66740
 Wrote PlaceDB: Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5008 ; free virtual = 66718
 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5008 ; free virtual = 66718
 Writing XDEF routing.
 Writing XDEF routing logical nets.
 Writing XDEF routing special nets.
 Wrote RouteStorage: Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.29 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66717
 Wrote Netlist Cache: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66719
 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66720
 Write Physdb Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66721
 INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_routed.dcp' has been generated.
 Command: write_bitstream -force system_wrapper.bit
 Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
 Running DRC as a precondition to command write_bitstream
 INFO: [IP_Flow 19-1839] IP Catalog is up to date.
 INFO: [DRC 23-27] Running DRC with 8 threads
 WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A3' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1/I0) is not included in the LUT equation: 'O5=(A1*A2)+(A1*(~A2)*(~A4))+((~A1))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
 WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A3' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[0]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[0]_i_1/I0) is not included in the LUT equation: 'O6=(A6+~A6)*((A5))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
 WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A5' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1/I1) is not included in the LUT equation: 'O5=(A1*A2)+(A1*(~A2)*(~A4))+((~A1))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
 WARNING: [DRC RTSTAT-10] No routable loads: 21 net(s) have no routable loads. The problem bus(es) and/or net(s) are dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TMS, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg[2:0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_capture[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_runtest[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i... and (the first 15 of 19 listed).
 INFO: [Vivado 12-3199] DRC finished with 0 Errors, 4 Warnings
 INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
 Loading data files...
 Loading site data...
 Loading route data...
 Processing options...
 Creating bitmap...
 Creating bitstream...
 Writing bitstream ./system_wrapper.bit...
 INFO: [Vivado 12-1842] Bitgen Completed Successfully.
 INFO: [Common 17-83] Releasing license: Implementation
 13 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
 write_bitstream completed successfully
 write_bitstream: Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 4599.906 ; gain = 300.855 ; free physical = 4256 ; free virtual = 66217
 INFO: [Common 17-206] Exiting Vivado at Wed May 27 16:43:10 2026...
@@ -1,696 +0,0 @@
 *** Running vivado
    with args -log system_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl
 ****** Vivado v2023.2 (64-bit)
  **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
  **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
  **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
 source system_wrapper.tcl -notrace
 INFO: [IP_Flow 19-234] Refreshing IP repositories
 INFO: [IP_Flow 19-1704] No user IP repositories specified
 INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'.
 Command: synth_design -top system_wrapper -part xc7z035ffg676-2
 Starting synth_design
 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035'
 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035'
 INFO: [Device 21-403] Loading part xc7z035ffg676-2
 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
 INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
 INFO: [Synth 8-7075] Helper process launched with PID 958941
 ---------------------------------------------------------------------------------
 Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2149.453 ; gain = 411.629 ; free physical = 845 ; free virtual = 70077
 ---------------------------------------------------------------------------------
 WARNING: [Synth 8-11121] redeclaration of ANSI port 'read_vld' is not allowed [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:33]
 WARNING: [Synth 8-11121] redeclaration of ANSI port 'dna_port' is not allowed [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:34]
 INFO: [Synth 8-6157] synthesizing module 'system_wrapper' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:13]
 INFO: [Synth 8-6157] synthesizing module 'IOBUF' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:78197]
 INFO: [Synth 8-6155] done synthesizing module 'IOBUF' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:78197]
 INFO: [Synth 8-6157] synthesizing module 'system' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:318]
 INFO: [Synth 8-6157] synthesizing module 'system_dna_port_read_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_dna_port_read_0_0/synth/system_dna_port_read_0_0.v:53]
 INFO: [Synth 8-6157] synthesizing module 'dna_port_read' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:23]
 INFO: [Synth 8-6157] synthesizing module 'DNA_PORT' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:39264]
 	Parameter SIM_DNA_VALUE bound to: 57'b000000000000000000000000000000000000000000000000000000000 
 INFO: [Synth 8-6155] done synthesizing module 'DNA_PORT' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:39264]
 INFO: [Synth 8-6155] done synthesizing module 'dna_port_read' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:23]
 INFO: [Synth 8-6155] done synthesizing module 'system_dna_port_read_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_dna_port_read_0_0/synth/system_dna_port_read_0_0.v:53]
 INFO: [Synth 8-6157] synthesizing module 'system_mydna_read_v1_0_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_mydna_read_v1_0_0_0/synth/system_mydna_read_v1_0_0_0.v:53]
 INFO: [Synth 8-6157] synthesizing module 'mydna_read_v1_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0.v:4]
 	Parameter C_S00_AXI_DATA_WIDTH bound to: 32 - type: integer 
 	Parameter C_S00_AXI_ADDR_WIDTH bound to: 4 - type: integer 
 INFO: [Synth 8-6157] synthesizing module 'mydna_read_v1_0_S00_AXI' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:4]
 	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
 	Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer 
 INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:235]
 INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:379]
 INFO: [Synth 8-6155] done synthesizing module 'mydna_read_v1_0_S00_AXI' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:4]
 INFO: [Synth 8-6155] done synthesizing module 'mydna_read_v1_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0.v:4]
 INFO: [Synth 8-6155] done synthesizing module 'system_mydna_read_v1_0_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_mydna_read_v1_0_0_0/synth/system_mydna_read_v1_0_0_0.v:53]
 INFO: [Synth 8-6157] synthesizing module 'system_processing_system7_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:53]
 INFO: [Synth 8-6157] synthesizing module 'processing_system7_v5_5_processing_system7' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152]
 INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
 INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
 INFO: [Synth 8-6157] synthesizing module 'BIBUF' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1598]
 INFO: [Synth 8-6155] done synthesizing module 'BIBUF' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1598]
 INFO: [Synth 8-6157] synthesizing module 'PS7' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111859]
 INFO: [Synth 8-6155] done synthesizing module 'PS7' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111859]
 INFO: [Synth 8-6155] done synthesizing module 'processing_system7_v5_5_processing_system7' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152]
 WARNING: [Synth 8-7071] port 'M_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'M_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'S_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'S_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'S_AXI_ACP_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'S_AXI_HP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'S_AXI_HP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'S_AXI_HP2_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'S_AXI_HP3_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'DMA0_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'DMA1_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'DMA2_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7071] port 'DMA3_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 WARNING: [Synth 8-7023] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
 INFO: [Synth 8-6155] done synthesizing module 'system_processing_system7_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:53]
 INFO: [Synth 8-6157] synthesizing module 'system_ps7_0_axi_periph_1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:632]
 INFO: [Synth 8-6157] synthesizing module 's00_couplers_imp_11SE3QO' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:13]
 INFO: [Synth 8-6157] synthesizing module 'system_auto_pc_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v:53]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_axi_protocol_converter' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5285]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4704]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_aw_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4360]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_cmd_translator' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3720]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_incr_cmd' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3216]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_incr_cmd' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3216]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wrap_cmd' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2982]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wrap_cmd' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2982]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_cmd_translator' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3720]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3392]
 INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3446]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3392]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_aw_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4360]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_b_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3906]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_b_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3906]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_ar_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4516]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3546]
 INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3608]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3546]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_ar_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4516]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_r_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4155]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_r_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4155]
 INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
 INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
 INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
 INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
 INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
 INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized2' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
 WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'SI_REG' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4871]
 WARNING: [Synth 8-7023] instance 'SI_REG' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4871]
 INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
 INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
 INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
 INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
 INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
 INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized3' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized3' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized4' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized4' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized5' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized5' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized6' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized6' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
 INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
 WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'MI_REG' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5126]
 WARNING: [Synth 8-7023] instance 'MI_REG' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5126]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4704]
 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_axi_protocol_converter' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5285]
 INFO: [Synth 8-6155] done synthesizing module 'system_auto_pc_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v:53]
 INFO: [Synth 8-6155] done synthesizing module 's00_couplers_imp_11SE3QO' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:13]
 INFO: [Synth 8-6155] done synthesizing module 'system_ps7_0_axi_periph_1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:632]
 INFO: [Synth 8-638] synthesizing module 'system_rst_ps7_0_100M_1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:74]
 	Parameter C_FAMILY bound to: zynq - type: string 
 	Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer 
 	Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer 
 	Parameter C_EXT_RESET_HIGH bound to: 1'b0 
 	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
 	Parameter C_NUM_BUS_RST bound to: 1 - type: integer 
 	Parameter C_NUM_PERP_RST bound to: 1 - type: integer 
 	Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer 
 	Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer 
 INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1271' bound to instance 'U0' of component 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:129]
 INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330]
 	Parameter INIT bound to: 1'b1 
 INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1399]
 	Parameter INIT bound to: 1'b1 
 INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1415]
 	Parameter INIT bound to: 1'b0 
 INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1441]
 	Parameter INIT bound to: 1'b1 
 INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1464]
 	Parameter INIT bound to: 1'b0 
 INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1488]
 INFO: [Synth 8-638] synthesizing module 'lpf' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821]
 INFO: [Synth 8-3491] module 'SRL16' declared at '/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721' bound to instance 'POR_SRL_I' of component 'SRL16' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:873]
 INFO: [Synth 8-6157] synthesizing module 'SRL16' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721]
 INFO: [Synth 8-6155] done synthesizing module 'SRL16' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721]
 INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
 	Parameter INIT bound to: 1'b0 
 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:514]
 	Parameter INIT bound to: 1'b0 
 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:545]
 	Parameter INIT bound to: 1'b0 
 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:554]
 	Parameter INIT bound to: 1'b0 
 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:564]
 	Parameter INIT bound to: 1'b0 
 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:574]
 	Parameter INIT bound to: 1'b0 
 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:584]
 INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
 INFO: [Synth 8-256] done synthesizing module 'lpf' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821]
 INFO: [Synth 8-638] synthesizing module 'sequence_psr' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304]
 INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126]
 INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126]
 INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304]
 INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330]
 INFO: [Synth 8-256] done synthesizing module 'system_rst_ps7_0_100M_1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:74]
 WARNING: [Synth 8-7071] port 'mb_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
 WARNING: [Synth 8-7071] port 'bus_struct_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
 WARNING: [Synth 8-7071] port 'peripheral_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
 WARNING: [Synth 8-7023] instance 'rst_ps7_0_100M' of module 'system_rst_ps7_0_100M_1' has 10 connections declared, but only 7 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
 INFO: [Synth 8-6155] done synthesizing module 'system' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:318]
 INFO: [Synth 8-6155] done synthesizing module 'system_wrapper' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:13]
 WARNING: [Synth 8-6014] Unused sequential element slv_reg1_reg was removed.  [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:228]
 WARNING: [Synth 8-6014] Unused sequential element slv_reg2_reg was removed.  [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:229]
 WARNING: [Synth 8-6014] Unused sequential element state_r1_reg was removed.  [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3596]
 WARNING: [Synth 8-6014] Unused sequential element s_arlen_r_reg was removed.  [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3597]
 WARNING: [Synth 8-7129] Port prmry_aclk in module cdc_sync is either unconnected or has no load
 WARNING: [Synth 8-7129] Port prmry_resetn in module cdc_sync is either unconnected or has no load
 WARNING: [Synth 8-7129] Port prmry_vect_in[1] in module cdc_sync is either unconnected or has no load
 WARNING: [Synth 8-7129] Port prmry_vect_in[0] in module cdc_sync is either unconnected or has no load
 WARNING: [Synth 8-7129] Port scndry_resetn in module cdc_sync is either unconnected or has no load
 WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized6 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized6 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized3 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized3 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized5 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized5 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized4 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized4 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port m_axi_bid[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port m_axi_buser[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port m_axi_rid[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port m_axi_rlast in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port m_axi_ruser[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awlen[7] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awlen[6] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awlen[5] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awlen[4] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awlen[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awlen[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awlen[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awlen[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awsize[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awsize[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awsize[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awburst[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awburst[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awlock[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awcache[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awcache[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awcache[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awcache[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awregion[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awregion[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awregion[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awregion[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awqos[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awqos[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awqos[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awqos[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awuser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_wid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_wlast in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_wuser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arlen[7] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arlen[6] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arlen[5] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arlen[4] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arlen[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arlen[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arlen[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arlen[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arsize[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arsize[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arsize[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arburst[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arburst[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arlock[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arcache[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arcache[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arcache[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arcache[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arregion[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arregion[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arregion[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arregion[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arqos[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arqos[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arqos[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arqos[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_aruser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port aclk2x in module axi_register_slice_v2_1_29_axi_register_slice__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized0 is either unconnected or has no load
 WARNING: [Synth 8-7129] Port m_axi_buser[0] in module axi_infrastructure_v1_1_0_vector2axi is either unconnected or has no load
 WARNING: [Synth 8-7129] Port m_axi_ruser[0] in module axi_infrastructure_v1_1_0_vector2axi is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awregion[3] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awregion[2] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awregion[1] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awregion[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_awuser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_wuser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arregion[3] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arregion[2] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arregion[1] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_arregion[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_axi_aruser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
 WARNING: [Synth 8-7129] Port aclk2x in module axi_register_slice_v2_1_29_axi_register_slice is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_arlen[7] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_arlen[6] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_arlen[5] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_arlen[4] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_arlen[3] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
 WARNING: [Synth 8-7129] Port s_arlen[2] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
 INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
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 Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 767 ; free virtual = 69885
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 ---------------------------------------------------------------------------------
 Start Handling Custom Attributes
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 768 ; free virtual = 69891
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 768 ; free virtual = 69891
 ---------------------------------------------------------------------------------
 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2359.391 ; gain = 0.000 ; free physical = 749 ; free virtual = 69874
 INFO: [Netlist 29-17] Analyzing 46 Unisim elements for replacement
 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
 INFO: [Project 1-570] Preparing netlist for logic optimization
 Processing XDC Constraints
 Initializing timing engine
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
 INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
 Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
 INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
 Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
 INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
 Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
 INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
 Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
 Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc]
 Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc]
 INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
 Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
 Completed Processing XDC Constraints
 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2518.867 ; gain = 0.000 ; free physical = 714 ; free virtual = 69858
 INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 46 instances were transformed.
  FDR => FDRE: 12 instances
  IOBUF => IOBUF (IBUF, OBUFT): 33 instances
  SRL16 => SRL16E: 1 instance 
 Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2518.902 ; gain = 0.000 ; free physical = 872 ; free virtual = 69870
 ---------------------------------------------------------------------------------
 Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 946 ; free virtual = 69833
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Loading Part and Timing Information
 ---------------------------------------------------------------------------------
 Loading part: xc7z035ffg676-2
 ---------------------------------------------------------------------------------
 Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 945 ; free virtual = 69833
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Applying 'set_property' XDC Constraints
 ---------------------------------------------------------------------------------
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_0. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 1).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_1. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 2).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_2. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 3).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_3. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 4).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_4. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 5).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_5. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 6).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_6. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 7).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_7. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 8).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_8. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 9).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_9. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 10).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_10. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 11).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_11. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 12).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_12. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 13).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_13. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 14).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_14. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 15).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_15. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 16).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_16. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 17).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_17. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 18).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_18. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 19).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_19. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 20).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_20. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 21).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_21. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 22).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_22. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 23).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_23. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 24).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_24. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 25).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_25. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 26).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_28. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 27).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_29. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 28).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_30. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 29).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_26. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 30).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_27. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 31).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_31. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 32).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_32. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 33).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_o_0. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 34).
 Applied set_property MARK_DEBUG = true for EMIO_0_tri_t_0. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 67).
 Applied set_property KEEP_HIERARCHY = SOFT for system_i/processing_system7_0/inst. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc, line 30).
 Applied set_property KEEP_HIERARCHY = SOFT for system_i/rst_ps7_0_100M/U0. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc, line 35).
 Applied set_property KEEP_HIERARCHY = SOFT for system_i. (constraint file  auto generated constraint).
 Applied set_property KEEP_HIERARCHY = SOFT for system_i/processing_system7_0. (constraint file  auto generated constraint).
 Applied set_property KEEP_HIERARCHY = SOFT for system_i/dna_port_read_0. (constraint file  auto generated constraint).
 Applied set_property KEEP_HIERARCHY = SOFT for system_i/mydna_read_v1_0_0. (constraint file  auto generated constraint).
 Applied set_property KEEP_HIERARCHY = SOFT for system_i/ps7_0_axi_periph/s00_couplers/auto_pc. (constraint file  auto generated constraint).
 Applied set_property KEEP_HIERARCHY = SOFT for system_i/ps7_0_axi_periph. (constraint file  auto generated constraint).
 Applied set_property KEEP_HIERARCHY = SOFT for system_i/rst_ps7_0_100M. (constraint file  auto generated constraint).
 ---------------------------------------------------------------------------------
 Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 940 ; free virtual = 69830
 ---------------------------------------------------------------------------------
 INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm'
 INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm'
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_0'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:213]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_1'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:218]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_2'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:273]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_3'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:328]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_4'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:348]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_5'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:353]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_6'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:358]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_7'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:363]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_8'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:368]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_9'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:373]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_10'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:223]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_11'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:228]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_12'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:233]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_13'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:238]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_14'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:243]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_15'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:248]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_16'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:253]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_17'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:258]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_18'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:263]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_19'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:268]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_20'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:278]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_21'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:283]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_22'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:288]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_23'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:293]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_24'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:298]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_25'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:303]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_28'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:318]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_29'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:323]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_30'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:333]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_26'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:308]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_27'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:313]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_31'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:338]
 INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_32'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:343]
 WARNING: [Synth 8-327] inferring latch for variable 'dna_port_reg_reg' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:413]
 ---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
 ---------------------------------------------------------------------------------------------------
                 SM_IDLE |                               01 |                               00
               SM_CMD_EN |                               11 |                               01
         SM_CMD_ACCEPTED |                               10 |                               10
            SM_DONE_WAIT |                               00 |                               11
 ---------------------------------------------------------------------------------------------------
 INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm'
 ---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
 ---------------------------------------------------------------------------------------------------
                 SM_IDLE |                               01 |                               00
               SM_CMD_EN |                               11 |                               01
         SM_CMD_ACCEPTED |                               10 |                               10
                 SM_DONE |                               00 |                               11
 ---------------------------------------------------------------------------------------------------
 INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm'
 ---------------------------------------------------------------------------------
 Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 929 ; free virtual = 69825
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start RTL Component Statistics 
 ---------------------------------------------------------------------------------
 Detailed RTL Component Info : 
 +---Adders : 
 	   2 Input   12 Bit       Adders := 8     
 	   2 Input    9 Bit       Adders := 2     
 	   2 Input    8 Bit       Adders := 2     
 	   2 Input    6 Bit       Adders := 1     
 	   2 Input    5 Bit       Adders := 4     
 	   2 Input    4 Bit       Adders := 4     
 	   2 Input    2 Bit       Adders := 2     
 +---Registers : 
 	               66 Bit    Registers := 4     
 	               57 Bit    Registers := 1     
 	               47 Bit    Registers := 2     
 	               32 Bit    Registers := 3     
 	               14 Bit    Registers := 2     
 	               12 Bit    Registers := 9     
 	                9 Bit    Registers := 2     
 	                8 Bit    Registers := 3     
 	                6 Bit    Registers := 1     
 	                5 Bit    Registers := 4     
 	                4 Bit    Registers := 8     
 	                3 Bit    Registers := 3     
 	                2 Bit    Registers := 9     
 	                1 Bit    Registers := 43    
 +---Muxes : 
 	   2 Input   66 Bit        Muxes := 4     
 	   2 Input   47 Bit        Muxes := 2     
 	   4 Input   32 Bit        Muxes := 3     
 	   2 Input   32 Bit        Muxes := 9     
 	   2 Input   14 Bit        Muxes := 2     
 	   2 Input   12 Bit        Muxes := 6     
 	   2 Input    9 Bit        Muxes := 4     
 	   2 Input    8 Bit        Muxes := 1     
 	   2 Input    6 Bit        Muxes := 1     
 	   2 Input    5 Bit        Muxes := 4     
 	   2 Input    4 Bit        Muxes := 18    
 	   2 Input    2 Bit        Muxes := 17    
 	   4 Input    2 Bit        Muxes := 4     
 	   2 Input    1 Bit        Muxes := 37    
 ---------------------------------------------------------------------------------
 Finished RTL Component Statistics 
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Part Resource Summary
 ---------------------------------------------------------------------------------
 Part Resources:
 DSPs: 900 (col length:140)
 BRAMs: 1000 (col length: RAMB18 140 RAMB36 70)
 ---------------------------------------------------------------------------------
 Finished Part Resource Summary
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Cross Boundary and Area Optimization
 ---------------------------------------------------------------------------------
 WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
 INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '66' to '62' bits. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726]
 INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '66' to '62' bits. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726]
 WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (FDRE_inst) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (BSR_OUT_DFF[0].FDRE_BSR) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N) is unused and will be removed from module proc_sys_reset.
 WARNING: [Synth 8-3332] Sequential element (PR_OUT_DFF[0].FDRE_PER) is unused and will be removed from module proc_sys_reset.
 ---------------------------------------------------------------------------------
 Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1838 ; free virtual = 70743
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Applying XDC Timing Constraints
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1815 ; free virtual = 70747
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Timing Optimization
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1781 ; free virtual = 70713
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Technology Mapping
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1765 ; free virtual = 70711
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start IO Insertion
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Flattening Before IO Insertion
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Flattening Before IO Insertion
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Final Netlist Cleanup
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Final Netlist Cleanup
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70517
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Renaming Generated Instances
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70517
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Rebuilding User Hierarchy
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Renaming Generated Ports
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Handling Custom Attributes
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Renaming Generated Nets
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start ROM, RAM, DSP, Shift Register and Retiming Reporting
 ---------------------------------------------------------------------------------
 Dynamic Shift Register Report:
 +------------+----------------+--------+------------+--------+---------+--------+--------+--------+
 |Module Name | RTL Name       | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 | 
 +------------+----------------+--------+------------+--------+---------+--------+--------+--------+
 |dsrl        | memory_reg[3]  | 20     | 20         | 20     | 0       | 0      | 0      | 0      | 
 |dsrl__1     | memory_reg[3]  | 2      | 2          | 2      | 0       | 0      | 0      | 0      | 
 |dsrl__2     | memory_reg[31] | 34     | 34         | 0      | 34      | 0      | 0      | 0      | 
 |dsrl__3     | memory_reg[31] | 13     | 13         | 0      | 13      | 0      | 0      | 0      | 
 +------------+----------------+--------+------------+--------+---------+--------+--------+--------+
 ---------------------------------------------------------------------------------
 Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Writing Synthesis Report
 ---------------------------------------------------------------------------------
 Report BlackBoxes: 
 +-+--------------+----------+
 | |BlackBox name |Instances |
 +-+--------------+----------+
 +-+--------------+----------+
 Report Cell Usage: 
 +------+---------+------+
 |      |Cell     |Count |
 +------+---------+------+
 |1     |BIBUF    |   130|
 |2     |BUFG     |     1|
 |3     |CARRY4   |     6|
 |4     |DNA_PORT |     1|
 |5     |LUT1     |    69|
 |6     |LUT2     |    24|
 |7     |LUT3     |   169|
 |8     |LUT4     |    52|
 |9     |LUT5     |    71|
 |10    |LUT6     |   118|
 |11    |PS7      |     1|
 |12    |SRL16    |     1|
 |13    |SRL16E   |    16|
 |14    |SRLC32E  |    45|
 |15    |FDCE     |    66|
 |16    |FDR      |     4|
 |17    |FDRE     |   501|
 |18    |FDSE     |    20|
 |19    |LD       |    57|
 |20    |IOBUF    |    33|
 +------+---------+------+
 ---------------------------------------------------------------------------------
 Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
 ---------------------------------------------------------------------------------
 Synthesis finished with 0 errors, 0 critical warnings and 136 warnings.
 Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 618.598 ; free physical = 1531 ; free virtual = 70510
 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1531 ; free virtual = 70509
 INFO: [Project 1-571] Translating synthesized netlist
 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2518.902 ; gain = 0.000 ; free physical = 1748 ; free virtual = 70732
 INFO: [Netlist 29-17] Analyzing 101 Unisim elements for replacement
 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
 INFO: [Project 1-570] Preparing netlist for logic optimization
 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2563.766 ; gain = 0.000 ; free physical = 1757 ; free virtual = 70743
 INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 95 instances were transformed.
  FDR => FDRE: 4 instances
  IOBUF => IOBUF (IBUF, OBUFT): 33 instances
  LD => LDCE: 57 instances
  SRL16 => SRL16E: 1 instance 
 Synth Design complete | Checksum: 8993d7c
 INFO: [Common 17-83] Releasing license: Synthesis
 187 Infos, 142 Warnings, 0 Critical Warnings and 0 Errors encountered.
 synth_design completed successfully
 synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 2563.801 ; gain = 1259.379 ; free physical = 1759 ; free virtual = 70746
 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1991.605; main = 1727.861; forked = 379.983
 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3465.613; main = 2563.770; forked = 1042.766
 Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2611.777 ; gain = 0.000 ; free physical = 1758 ; free virtual = 70746
 INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/system_wrapper.dcp' has been generated.
 INFO: [runtcl-4] Executing : report_utilization -file system_wrapper_utilization_synth.rpt -pb system_wrapper_utilization_synth.pb
 INFO: [Common 17-206] Exiting Vivado at Wed May 27 16:36:31 2026...
@@ -1,58 +0,0 @@
 #-----------------------------------------------------------
 # Webtalk v2018.3 (64-bit)
 # SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
 # 
 # Start of session at: Mon Jan 12 17:58:43 2026
 # Process ID: 9264
 # Current directory: E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/webtalk
 # Command line: wbtcv.exe -mode batch -source sdk_webtalk.tcl
 # Log file: E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/webtalk/webtalk.log
 # Journal file: E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/webtalk\webtalk.jou
 #-----------------------------------------------------------
 source sdk_webtalk.tcl
 # webtalk_init -webtalk_dir E:\\CALBOARD\\z035_mars1k_a1_sc1\\calboard_cp_a1\\proj_cal\\proj_cal.sdk\\webtalk
 # webtalk_register_client -client project
 # webtalk_add_data -client project -key date_generated -value "2026-01-12 17:58:41" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key product_version -value "SDK v2018.3" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key build_version -value "2018.3" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key os_platform -value "amd64" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key tool_flow -value "SDK" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key beta -value "false" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key route_design -value "NA" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key target_family -value "NA" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key target_device -value "NA" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key target_package -value "NA" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key target_speed -value "NA" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key random_id -value "2nggfjdmptbjko2tf7jbetillv" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key project_id -value "2018.3_84" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key project_iteration -value "84" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
 # webtalk_add_data -client project -key os_release -value "major release  (build 9200)" -context "user_environment"
 # webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz" -context "user_environment"
 # webtalk_add_data -client project -key cpu_speed -value "3096 MHz" -context "user_environment"
 # webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
 # webtalk_add_data -client project -key system_ram -value "68.455 GB" -context "user_environment"
 # webtalk_register_client -client sdk
 # webtalk_add_data -client sdk -key uid -value "1768211353816" -context "sdk\\\\hardware/1768211353816"
 # webtalk_add_data -client sdk -key isZynq -value "true" -context "sdk\\\\hardware/1768211353816"
 # webtalk_add_data -client sdk -key isZynqMP -value "false" -context "sdk\\\\hardware/1768211353816"
 # webtalk_add_data -client sdk -key Processors -value "2" -context "sdk\\\\hardware/1768211353816"
 # webtalk_add_data -client sdk -key VivadoVersion -value "2018.3" -context "sdk\\\\hardware/1768211353816"
 # webtalk_add_data -client sdk -key Arch -value "zynq" -context "sdk\\\\hardware/1768211353816"
 # webtalk_add_data -client sdk -key Device -value "7z035" -context "sdk\\\\hardware/1768211353816"
 # webtalk_add_data -client sdk -key IsHandoff -value "true" -context "sdk\\\\hardware/1768211353816"
 # webtalk_add_data -client sdk -key os -value "NA" -context "sdk\\\\hardware/1768211353816"
 # webtalk_add_data -client sdk -key apptemplate -value "NA" -context "sdk\\\\hardware/1768211353816"
 # webtalk_add_data -client sdk -key RecordType -value "HWCreation" -context "sdk\\\\hardware/1768211353816"
 # webtalk_add_data -client sdk -key uid -value "NA" -context "sdk\\\\bsp/1768211921541"
 # webtalk_add_data -client sdk -key RecordType -value "ToolUsage" -context "sdk\\\\bsp/1768211921541"
 # webtalk_add_data -client sdk -key BootgenCount -value "0" -context "sdk\\\\bsp/1768211921541"
 # webtalk_add_data -client sdk -key DebugCount -value "0" -context "sdk\\\\bsp/1768211921541"
 # webtalk_add_data -client sdk -key PerfCount -value "0" -context "sdk\\\\bsp/1768211921541"
 # webtalk_add_data -client sdk -key FlashCount -value "0" -context "sdk\\\\bsp/1768211921541"
 # webtalk_add_data -client sdk -key CrossTriggCount -value "0" -context "sdk\\\\bsp/1768211921541"
 # webtalk_add_data -client sdk -key QemuDebugCount -value "0" -context "sdk\\\\bsp/1768211921541"
 # webtalk_transmit -clientid 5615683 -regid "" -xml E:\\CALBOARD\\z035_mars1k_a1_sc1\\calboard_cp_a1\\proj_cal\\proj_cal.sdk\\webtalk\\usage_statistics_ext_sdk.xml -html E:\\CALBOARD\\z035_mars1k_a1_sc1\\calboard_cp_a1\\proj_cal\\proj_cal.sdk\\webtalk\\usage_statistics_ext_sdk.html -wdm E:\\CALBOARD\\z035_mars1k_a1_sc1\\calboard_cp_a1\\proj_cal\\proj_cal.sdk\\webtalk\\sdk_webtalk.wdm -intro "<H3>SDK Usage Report</H3><BR>"
 # webtalk_terminate
 INFO: [Common 17-206] Exiting Webtalk at Mon Jan 12 17:58:45 2026...
@@ -1,73 +0,0 @@
 #-----------------------------------------------------------
 # Webtalk v2018.3 (64-bit)
 # SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
 # 
 # Start of session at: Thu Jul 20 18:23:39 2023
 # Process ID: 20184
 # Current directory: G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/webtalk
 # Command line: wbtcv.exe -mode batch -source sdk_webtalk.tcl
 # Log file: G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/webtalk/webtalk.log
 # Journal file: G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/webtalk\webtalk.jou
 #-----------------------------------------------------------
 source sdk_webtalk.tcl
 # webtalk_init -webtalk_dir G:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk
 # webtalk_register_client -client project
 # webtalk_add_data -client project -key date_generated -value "2023-07-20 18:23:36" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key product_version -value "SDK v2018.3" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key build_version -value "2018.3" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key os_platform -value "amd64" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key tool_flow -value "SDK" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key beta -value "false" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key route_design -value "NA" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key target_family -value "NA" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key target_device -value "NA" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key target_package -value "NA" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key target_speed -value "NA" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key random_id -value "d93rb3douagiiu2qng7tjq9f0f" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key project_id -value "2018.3_39" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key project_iteration -value "39" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
 # webtalk_add_data -client project -key os_release -value "major release  (build 9200)" -context "user_environment"
 # webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz" -context "user_environment"
 # webtalk_add_data -client project -key cpu_speed -value "3096 MHz" -context "user_environment"
 # webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
 # webtalk_add_data -client project -key system_ram -value "16.915 GB" -context "user_environment"
 # webtalk_register_client -client sdk
 # webtalk_add_data -client sdk -key uid -value "1689821971742" -context "sdk\\\\hardware/1689821971742"
 # webtalk_add_data -client sdk -key isZynq -value "true" -context "sdk\\\\hardware/1689821971742"
 # webtalk_add_data -client sdk -key isZynqMP -value "false" -context "sdk\\\\hardware/1689821971742"
 # webtalk_add_data -client sdk -key Processors -value "2" -context "sdk\\\\hardware/1689821971742"
 # webtalk_add_data -client sdk -key VivadoVersion -value "2018.3" -context "sdk\\\\hardware/1689821971742"
 # webtalk_add_data -client sdk -key Arch -value "zynq" -context "sdk\\\\hardware/1689821971742"
 # webtalk_add_data -client sdk -key Device -value "7z035" -context "sdk\\\\hardware/1689821971742"
 # webtalk_add_data -client sdk -key IsHandoff -value "true" -context "sdk\\\\hardware/1689821971742"
 # webtalk_add_data -client sdk -key os -value "NA" -context "sdk\\\\hardware/1689821971742"
 # webtalk_add_data -client sdk -key apptemplate -value "NA" -context "sdk\\\\hardware/1689821971742"
 # webtalk_add_data -client sdk -key RecordType -value "HWCreation" -context "sdk\\\\hardware/1689821971742"
 # webtalk_add_data -client sdk -key uid -value "1689822029590" -context "sdk\\\\bsp/1689822029590"
 # webtalk_add_data -client sdk -key hwid -value "1689821971742" -context "sdk\\\\bsp/1689822029590"
 # webtalk_add_data -client sdk -key os -value "standalone" -context "sdk\\\\bsp/1689822029590"
 # webtalk_add_data -client sdk -key apptemplate -value "lwip_echo_server" -context "sdk\\\\bsp/1689822029590"
 # webtalk_add_data -client sdk -key RecordType -value "BSPCreation" -context "sdk\\\\bsp/1689822029590"
 # webtalk_add_data -client sdk -key uid -value "1689822033349" -context "sdk\\\\application/1689822033349"
 # webtalk_add_data -client sdk -key hwid -value "1689821971742" -context "sdk\\\\application/1689822033349"
 # webtalk_add_data -client sdk -key bspid -value "1689822029590" -context "sdk\\\\application/1689822033349"
 # webtalk_add_data -client sdk -key newbsp -value "true" -context "sdk\\\\application/1689822033349"
 # webtalk_add_data -client sdk -key os -value "standalone" -context "sdk\\\\application/1689822033349"
 # webtalk_add_data -client sdk -key apptemplate -value "lwip_echo_server" -context "sdk\\\\application/1689822033349"
 # webtalk_add_data -client sdk -key RecordType -value "APPCreation" -context "sdk\\\\application/1689822033349"
 # webtalk_add_data -client sdk -key LangUsed -value "C" -context "sdk\\\\application/1689822033349"
 # webtalk_add_data -client sdk -key Procused -value "ps7_cortexa9" -context "sdk\\\\application/1689822033349"
 # webtalk_add_data -client sdk -key projSize -value "1030.41015625" -context "sdk\\\\application/1689822033349"
 # webtalk_add_data -client sdk -key uid -value "NA" -context "sdk\\\\bsp/1689848616439"
 # webtalk_add_data -client sdk -key RecordType -value "ToolUsage" -context "sdk\\\\bsp/1689848616439"
 # webtalk_add_data -client sdk -key BootgenCount -value "0" -context "sdk\\\\bsp/1689848616439"
 # webtalk_add_data -client sdk -key DebugCount -value "19" -context "sdk\\\\bsp/1689848616439"
 # webtalk_add_data -client sdk -key PerfCount -value "0" -context "sdk\\\\bsp/1689848616439"
 # webtalk_add_data -client sdk -key FlashCount -value "0" -context "sdk\\\\bsp/1689848616439"
 # webtalk_add_data -client sdk -key CrossTriggCount -value "0" -context "sdk\\\\bsp/1689848616439"
 # webtalk_add_data -client sdk -key QemuDebugCount -value "0" -context "sdk\\\\bsp/1689848616439"
 # webtalk_transmit -clientid 3912584924 -regid "" -xml G:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk\\usage_statistics_ext_sdk.xml -html G:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk\\usage_statistics_ext_sdk.html -wdm G:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk\\sdk_webtalk.wdm -intro "<H3>SDK Usage Report</H3><BR>"
 # webtalk_terminate
 INFO: [Common 17-206] Exiting Webtalk at Thu Jul 20 18:23:42 2023...
@@ -1,62 +0,0 @@
 #-----------------------------------------------------------
 # Webtalk v2018.3 (64-bit)
 # SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
 # 
 # Start of session at: Mon Jul 31 11:37:17 2023
 # Process ID: 5900
 # Current directory: G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/webtalk
 # Command line: wbtcv.exe -mode batch -source sdk_webtalk.tcl
 # Log file: G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/webtalk/webtalk.log
 # Journal file: G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/webtalk\webtalk.jou
 #-----------------------------------------------------------
 source sdk_webtalk.tcl
 # webtalk_init -webtalk_dir G:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk
 # webtalk_register_client -client project
 # webtalk_add_data -client project -key date_generated -value "2023-07-31 11:37:16" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key product_version -value "SDK v2018.3" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key build_version -value "2018.3" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key os_platform -value "amd64" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key tool_flow -value "SDK" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key beta -value "false" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key route_design -value "NA" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key target_family -value "NA" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key target_device -value "NA" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key target_package -value "NA" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key target_speed -value "NA" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key random_id -value "6lutd0oqhp462m5qicot7tp33v" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key project_id -value "2018.3_40" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key project_iteration -value "40" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
 # webtalk_add_data -client project -key os_release -value "major release  (build 9200)" -context "user_environment"
 # webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz" -context "user_environment"
 # webtalk_add_data -client project -key cpu_speed -value "3096 MHz" -context "user_environment"
 # webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
 # webtalk_add_data -client project -key system_ram -value "16.915 GB" -context "user_environment"
 # webtalk_register_client -client sdk
 # webtalk_add_data -client sdk -key uid -value "1690773826104" -context "sdk\\\\bsp/1690773826104"
 # webtalk_add_data -client sdk -key hwid -value "1689821971742" -context "sdk\\\\bsp/1690773826104"
 # webtalk_add_data -client sdk -key os -value "standalone" -context "sdk\\\\bsp/1690773826104"
 # webtalk_add_data -client sdk -key apptemplate -value "zynq_fsbl" -context "sdk\\\\bsp/1690773826104"
 # webtalk_add_data -client sdk -key RecordType -value "BSPCreation" -context "sdk\\\\bsp/1690773826104"
 # webtalk_add_data -client sdk -key uid -value "1690773834491" -context "sdk\\\\application/1690773834491"
 # webtalk_add_data -client sdk -key hwid -value "1689821971742" -context "sdk\\\\application/1690773834491"
 # webtalk_add_data -client sdk -key bspid -value "1690773826104" -context "sdk\\\\application/1690773834491"
 # webtalk_add_data -client sdk -key newbsp -value "true" -context "sdk\\\\application/1690773834491"
 # webtalk_add_data -client sdk -key os -value "standalone" -context "sdk\\\\application/1690773834491"
 # webtalk_add_data -client sdk -key apptemplate -value "zynq_fsbl" -context "sdk\\\\application/1690773834491"
 # webtalk_add_data -client sdk -key RecordType -value "APPCreation" -context "sdk\\\\application/1690773834491"
 # webtalk_add_data -client sdk -key LangUsed -value "C" -context "sdk\\\\application/1690773834491"
 # webtalk_add_data -client sdk -key Procused -value "ps7_cortexa9" -context "sdk\\\\application/1690773834491"
 # webtalk_add_data -client sdk -key projSize -value "593.01953125" -context "sdk\\\\application/1690773834491"
 # webtalk_add_data -client sdk -key uid -value "NA" -context "sdk\\\\bsp/1690774636169"
 # webtalk_add_data -client sdk -key RecordType -value "ToolUsage" -context "sdk\\\\bsp/1690774636169"
 # webtalk_add_data -client sdk -key BootgenCount -value "1" -context "sdk\\\\bsp/1690774636169"
 # webtalk_add_data -client sdk -key DebugCount -value "0" -context "sdk\\\\bsp/1690774636169"
 # webtalk_add_data -client sdk -key PerfCount -value "0" -context "sdk\\\\bsp/1690774636169"
 # webtalk_add_data -client sdk -key FlashCount -value "0" -context "sdk\\\\bsp/1690774636169"
 # webtalk_add_data -client sdk -key CrossTriggCount -value "0" -context "sdk\\\\bsp/1690774636169"
 # webtalk_add_data -client sdk -key QemuDebugCount -value "0" -context "sdk\\\\bsp/1690774636169"
 # webtalk_transmit -clientid 2374953459 -regid "" -xml G:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk\\usage_statistics_ext_sdk.xml -html G:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk\\usage_statistics_ext_sdk.html -wdm G:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk\\sdk_webtalk.wdm -intro "<H3>SDK Usage Report</H3><BR>"
 # webtalk_terminate
 INFO: [Common 17-206] Exiting Webtalk at Mon Jul 31 11:37:19 2023...
@@ -1,58 +0,0 @@
 #-----------------------------------------------------------
 # Webtalk v2018.3 (64-bit)
 # SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
 # 
 # Start of session at: Fri Nov 22 13:59:32 2024
 # Process ID: 7548
 # Current directory: E:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/webtalk
 # Command line: wbtcv.exe -mode batch -source sdk_webtalk.tcl
 # Log file: E:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/webtalk/webtalk.log
 # Journal file: E:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/webtalk\webtalk.jou
 #-----------------------------------------------------------
 source sdk_webtalk.tcl
 # webtalk_init -webtalk_dir E:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk
 # webtalk_register_client -client project
 # webtalk_add_data -client project -key date_generated -value "2024-11-22 13:59:31" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key product_version -value "SDK v2018.3" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key build_version -value "2018.3" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key os_platform -value "amd64" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key tool_flow -value "SDK" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key beta -value "false" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key route_design -value "NA" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key target_family -value "NA" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key target_device -value "NA" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key target_package -value "NA" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key target_speed -value "NA" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key random_id -value "um90256p7r8dnau11ussq547e5" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key project_id -value "2018.3_78" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key project_iteration -value "78" -context "software_version_and_target_device"
 # webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
 # webtalk_add_data -client project -key os_release -value "major release  (build 9200)" -context "user_environment"
 # webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz" -context "user_environment"
 # webtalk_add_data -client project -key cpu_speed -value "3096 MHz" -context "user_environment"
 # webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
 # webtalk_add_data -client project -key system_ram -value "68.455 GB" -context "user_environment"
 # webtalk_register_client -client sdk
 # webtalk_add_data -client sdk -key uid -value "1732254221461" -context "sdk\\\\hardware/1732254221461"
 # webtalk_add_data -client sdk -key isZynq -value "true" -context "sdk\\\\hardware/1732254221461"
 # webtalk_add_data -client sdk -key isZynqMP -value "false" -context "sdk\\\\hardware/1732254221461"
 # webtalk_add_data -client sdk -key Processors -value "2" -context "sdk\\\\hardware/1732254221461"
 # webtalk_add_data -client sdk -key VivadoVersion -value "2018.3" -context "sdk\\\\hardware/1732254221461"
 # webtalk_add_data -client sdk -key Arch -value "zynq" -context "sdk\\\\hardware/1732254221461"
 # webtalk_add_data -client sdk -key Device -value "7z035" -context "sdk\\\\hardware/1732254221461"
 # webtalk_add_data -client sdk -key IsHandoff -value "true" -context "sdk\\\\hardware/1732254221461"
 # webtalk_add_data -client sdk -key os -value "NA" -context "sdk\\\\hardware/1732254221461"
 # webtalk_add_data -client sdk -key apptemplate -value "NA" -context "sdk\\\\hardware/1732254221461"
 # webtalk_add_data -client sdk -key RecordType -value "HWCreation" -context "sdk\\\\hardware/1732254221461"
 # webtalk_add_data -client sdk -key uid -value "NA" -context "sdk\\\\bsp/1732255170972"
 # webtalk_add_data -client sdk -key RecordType -value "ToolUsage" -context "sdk\\\\bsp/1732255170972"
 # webtalk_add_data -client sdk -key BootgenCount -value "1" -context "sdk\\\\bsp/1732255170972"
 # webtalk_add_data -client sdk -key DebugCount -value "0" -context "sdk\\\\bsp/1732255170972"
 # webtalk_add_data -client sdk -key PerfCount -value "0" -context "sdk\\\\bsp/1732255170972"
 # webtalk_add_data -client sdk -key FlashCount -value "0" -context "sdk\\\\bsp/1732255170972"
 # webtalk_add_data -client sdk -key CrossTriggCount -value "0" -context "sdk\\\\bsp/1732255170972"
 # webtalk_add_data -client sdk -key QemuDebugCount -value "0" -context "sdk\\\\bsp/1732255170972"
 # webtalk_transmit -clientid 61313245 -regid "" -xml E:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk\\usage_statistics_ext_sdk.xml -html E:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk\\usage_statistics_ext_sdk.html -wdm E:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk\\sdk_webtalk.wdm -intro "<H3>SDK Usage Report</H3><BR>"
 # webtalk_terminate
 INFO: [Common 17-206] Exiting Webtalk at Fri Nov 22 13:59:37 2024...
@@ -1,4 +1,67 @@
-timestamp=[2026-05-27 09:47:20], mode=WORKBENCH_START, duration=0:00:02.140, duration_ms=2140, data={}
+timestamp=[2026-05-28 18:29:18], mode=PLATFORM_GENERATION, duration=0:00:15.265, duration_ms=15265, data={name=NewInstCal_bsp}
-timestamp=[2026-05-27 09:47:20], mode=PLATFORM_REPOSITORY_INIT, duration=0:00:00.014, duration_ms=14, data={}
+timestamp=[2026-05-28 18:29:21], mode=BUILD, duration=0:00:02.313, duration_ms=2313, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
-timestamp=[2026-05-27 09:47:20], mode=WORKBENCH_UI_INIT, duration=0:00:00.170, duration_ms=170, data={editors_count=0, platform_editors_count=0, projects_count=0, platform_projects_count=0, active_platform_editor=false, projects=}
+timestamp=[2026-05-28 18:29:49], mode=PLATFORM_GENERATION, duration=0:00:12.429, duration_ms=12429, data={name=NewInstCal_bsp}
-timestamp=[2026-05-27 09:48:49], mode=PLATFORM_GENERATION, duration=0:00:10.747, duration_ms=10747, data={name=NewInstCal_bsp}
+timestamp=[2026-05-28 18:30:07], mode=PLATFORM_GENERATION, duration=0:00:07.057, duration_ms=7057, data={name=NewInstCal_bsp}
 timestamp=[2026-05-28 18:30:39], mode=PLATFORM_GENERATION, duration=0:00:21.949, duration_ms=21949, data={name=NewInstCal_bsp}
 timestamp=[2026-05-28 18:31:05], mode=PLATFORM_GENERATION, duration=0:00:11.136, duration_ms=11136, data={name=NewInstCal_bsp}
 timestamp=[2026-05-28 18:32:23], mode=PLATFORM_GENERATION, duration=0:00:22.520, duration_ms=22520, data={name=NewInstCal_bsp}
 timestamp=[2026-05-28 18:32:41], mode=BUILD, duration=0:00:01.927, duration_ms=1927, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-28 18:35:48], mode=BUILD, duration=0:00:00.239, duration_ms=239, data={name=NewInstrCalBoard, configuration=Debug, clean_build=true}
 timestamp=[2026-05-28 18:35:51], mode=BUILD, duration=0:00:02.453, duration_ms=2453, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-28 18:36:02], mode=BUILD, duration=0:00:02.193, duration_ms=2193, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-28 18:36:10], mode=BUILD, duration=0:00:06.939, duration_ms=6939, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-05-28 18:36:18], mode=BUILD, duration=0:00:01.197, duration_ms=1197, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-28 18:36:25], mode=BUILD, duration=0:00:06.800, duration_ms=6800, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 12:11:21], mode=BUILD, duration=0:00:01.756, duration_ms=1756, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 12:12:30], mode=BUILD, duration=0:00:01.836, duration_ms=1836, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 12:12:40], mode=BUILD, duration=0:00:10.066, duration_ms=10066, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 14:01:44], mode=BUILD, duration=0:00:01.237, duration_ms=1237, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 14:01:51], mode=BUILD, duration=0:00:07.132, duration_ms=7132, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 14:04:09], mode=BUILD, duration=0:00:01.170, duration_ms=1170, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 14:04:16], mode=BUILD, duration=0:00:06.969, duration_ms=6969, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 14:06:00], mode=BUILD, duration=0:00:01.181, duration_ms=1181, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 14:06:07], mode=BUILD, duration=0:00:06.894, duration_ms=6894, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 14:10:02], mode=BUILD, duration=0:00:01.176, duration_ms=1176, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 14:10:09], mode=BUILD, duration=0:00:06.854, duration_ms=6854, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 14:46:57], mode=BUILD, duration=0:00:01.200, duration_ms=1200, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 14:47:05], mode=BUILD, duration=0:00:06.955, duration_ms=6955, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 14:47:54], mode=BUILD, duration=0:00:01.167, duration_ms=1167, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 14:48:01], mode=BUILD, duration=0:00:06.885, duration_ms=6885, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 14:55:33], mode=BUILD, duration=0:00:01.180, duration_ms=1180, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 14:55:40], mode=BUILD, duration=0:00:06.884, duration_ms=6884, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 14:56:16], mode=BUILD, duration=0:00:00.686, duration_ms=686, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 14:56:34], mode=BUILD, duration=0:00:01.831, duration_ms=1831, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 14:56:41], mode=BUILD, duration=0:00:06.912, duration_ms=6912, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 14:57:21], mode=BUILD, duration=0:00:01.197, duration_ms=1197, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 14:57:28], mode=BUILD, duration=0:00:06.962, duration_ms=6962, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 14:58:53], mode=BUILD, duration=0:00:01.234, duration_ms=1234, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 14:59:00], mode=BUILD, duration=0:00:06.964, duration_ms=6964, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 15:03:44], mode=BUILD, duration=0:00:01.200, duration_ms=1200, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 15:03:51], mode=BUILD, duration=0:00:06.941, duration_ms=6941, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 15:07:59], mode=BUILD, duration=0:00:01.164, duration_ms=1164, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 15:08:07], mode=BUILD, duration=0:00:06.857, duration_ms=6857, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 15:10:19], mode=BUILD, duration=0:00:01.205, duration_ms=1205, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 15:10:26], mode=BUILD, duration=0:00:07.003, duration_ms=7003, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 15:37:57], mode=BUILD, duration=0:00:01.221, duration_ms=1221, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 15:38:04], mode=BUILD, duration=0:00:07.028, duration_ms=7028, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 16:00:10], mode=BUILD, duration=0:00:01.163, duration_ms=1163, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 16:00:18], mode=BUILD, duration=0:00:07.016, duration_ms=7016, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 18:12:30], mode=BUILD, duration=0:00:01.308, duration_ms=1308, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 18:12:37], mode=BUILD, duration=0:00:07.017, duration_ms=7017, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 18:15:29], mode=BUILD, duration=0:00:01.296, duration_ms=1296, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-29 18:15:37], mode=BUILD, duration=0:00:06.847, duration_ms=6847, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-06-18 09:37:33], mode=WORKBENCH_START, duration=0:00:10.982, duration_ms=10982, data={}
 timestamp=[2026-06-18 09:37:35], mode=WORKBENCH_UI_INIT, duration=0:00:01.636, duration_ms=1636, data={editors_count=5, platform_editors_count=3, projects_count=4, platform_projects_count=1, active_platform_editor=true, projects=NewInstCal_bsp,NewInstrCalBoard,NewInstrCalBoard_system,RemoteSystemsTempFiles}
 timestamp=[2026-06-18 09:37:36], mode=PLATFORM_REPOSITORY_INIT, duration=0:00:00.960, duration_ms=960, data={}
 timestamp=[2026-06-18 09:40:35], mode=PLATFORM_GENERATION, duration=0:00:26.819, duration_ms=26819, data={name=NewInstCal_bsp}
 timestamp=[2026-06-18 09:40:45], mode=BUILD, duration=0:00:06.425, duration_ms=6425, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-06-18 09:41:21], mode=BUILD, duration=0:00:00.260, duration_ms=260, data={name=NewInstrCalBoard, configuration=Debug, clean_build=true}
 timestamp=[2026-06-18 09:41:26], mode=BUILD, duration=0:00:05.117, duration_ms=5117, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-06-18 09:41:34], mode=BUILD, duration=0:00:07.756, duration_ms=7756, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-06-18 09:44:41], mode=PLATFORM_GENERATION, duration=0:00:11.485, duration_ms=11485, data={name=NewInstCal_bsp}
 timestamp=[2026-06-18 09:48:39], mode=PLATFORM_GENERATION, duration=0:00:44.378, duration_ms=44378, data={name=NewInstCal_bsp}
 timestamp=[2026-06-18 09:48:40], mode=BUILD, duration=0:00:00.259, duration_ms=259, data={name=NewInstrCalBoard, configuration=Debug, clean_build=true}
 timestamp=[2026-06-18 09:48:40], mode=BUILD, duration=0:00:00.202, duration_ms=202, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=true}
 timestamp=[2026-06-18 09:49:53], mode=PLATFORM_GENERATION, duration=0:00:34.064, duration_ms=34064, data={name=NewInstCal_bsp}
 timestamp=[2026-06-18 09:49:59], mode=BUILD, duration=0:00:06.185, duration_ms=6185, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-06-18 09:50:07], mode=BUILD, duration=0:00:07.806, duration_ms=7806, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
@@ -1,13 +0,0 @@
 09:47:19 DEBUG : Logs will be stored at '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/IDE.log'.
 09:47:20 INFO  : Launching XSCT server: xsct -n  -interactive /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/temp_xsdb_launch_script.tcl
 09:47:20 INFO  : Platform repository initialization has completed.
 09:47:20 INFO  : Registering command handlers for Vitis TCF services
 09:47:21 INFO  : XSCT server has started successfully.
 09:47:21 INFO  : Successfully done setting XSCT server connection channel  
 09:47:21 INFO  : Successfully done query RDI_DATADIR 
 09:47:21 INFO  : Successfully done setting workspace for the tool. 
 09:47:22 INFO  : plnx-install-location is set to ''
 09:48:02 INFO  : Platform 'NewInstCal_bsp' is added to custom repositories.
 09:48:28 INFO  : Hardware specification for platform project 'NewInstCal_bsp' is updated.
 09:48:46 INFO  : Result from executing command 'getProjects': NewInstCal_bsp
 09:48:46 INFO  : Result from executing command 'getPlatforms': NewInstCal_bsp|/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/export/NewInstCal_bsp/NewInstCal_bsp.xpfm
@@ -1,2 +0,0 @@
 2026-05-27T18:04:35.5315588000-Nothing to build in platform 'NewInstCal_bsp'
@@ -1 +1 @@
-{"platformName":"NewInstCal_bsp","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"NewInstCal_bsp","platHandOff":"/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/system_wrapper.xsa","platIntHandOff":"<platformDir>/hw/system_wrapper.xsa","deviceType":"zynq","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","fsblExtraCompilerFlags":"-MMD -MP       -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"NewInstCal_bsp","systems":[{"systemName":"NewInstCal_bsp","systemDesc":"NewInstCal_bsp","sysIsBootAutoGen":"true","systemDispName":"NewInstCal_bsp","sysActiveDom":"standalone_domain","sysDefaultDom":"standalone_domain","domains":[{"domainName":"zynq_fsbl","domainDispName":"zynq_fsbl","domainDesc":"FSBL Application BSP - Auto Generated.","processors":"ps7_cortexa9_0","os":"standalone","sdxOs":"standalone","debugEnable":"","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.0","mssFile":"","md5Digest":"3243e54020e3af7b58d483729f3822a1","compatibleApp":"zynq_fsbl","domType":"bootDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilffs:5.1","xilrsa:1.7"],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_domain","domainDispName":"standalone on ps7_cortexa9_0","domainDesc":"standalone_domain","processors":"ps7_cortexa9_0","os":"standalone","sdxOs":"standalone","qemuArgs":"<platformDir>/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt","qemuData":"<platformDir>/resources/NewInstCal_bsp/standalone_domain/qemu","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.0","mssFile":"","md5Digest":"1422839dbecb6fdfcf744dce689d156a","compatibleApp":"","domType":"mssDomain","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip213:1.1"],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}
+{"platformName":"NewInstCal_bsp","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"NewInstCal_bsp","platHandOff":"/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/system_wrapper.xsa","platIntHandOff":"<platformDir>/hw/system_wrapper.xsa","deviceType":"zynq","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","fsblExtraCompilerFlags":"-MMD -MP       -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"NewInstCal_bsp","systems":[{"systemName":"NewInstCal_bsp","systemDesc":"NewInstCal_bsp","sysIsBootAutoGen":"true","systemDispName":"NewInstCal_bsp","sysActiveDom":"standalone_domain","sysDefaultDom":"standalone_domain","domains":[{"domainName":"zynq_fsbl","domainDispName":"zynq_fsbl","domainDesc":"FSBL Application BSP - Auto Generated.","processors":"ps7_cortexa9_0","os":"standalone","sdxOs":"standalone","debugEnable":"","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.0","mssFile":"","md5Digest":"3243e54020e3af7b58d483729f3822a1","compatibleApp":"zynq_fsbl","domType":"bootDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilffs:5.1","xilrsa:1.7"],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_domain","domainDispName":"standalone on ps7_cortexa9_0","domainDesc":"standalone_domain","processors":"ps7_cortexa9_0","os":"standalone","sdxOs":"standalone","qemuArgs":"<platformDir>/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt","qemuData":"<platformDir>/resources/NewInstCal_bsp/standalone_domain/qemu","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.0","mssFile":"","md5Digest":"89622e7dd40f4ebcc78d10cff01d935b","compatibleApp":"","domType":"mssDomain","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip213:1.1"],"libOptions":{"lwip213":{"dhcp_does_arp_check":"true","lwip_dhcp":"true","libOptionNames":["dhcp_does_arp_check","lwip_dhcp"]},"libsContainingOptions":["lwip213"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}
@@ -29,3 +29,30 @@ platform config -updatehw {/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW
 platform generate
 platform active {NewInstCal_bsp}
 platform generate
 platform active {NewInstCal_bsp}
 platform generate
 platform clean
 platform active {NewInstCal_bsp}
 domain active {zynq_fsbl}
 bsp reload
 catch {bsp regenerate}
 domain active {standalone_domain}
 bsp reload
 bsp removelib -name lwip213
 bsp write
 bsp reload
 catch {bsp regenerate}
 catch {bsp regenerate}
 platform generate
 platform active {NewInstCal_bsp}
 bsp reload
 bsp setlib -name lwip213 -ver 1.1
 bsp config dhcp_does_arp_check "true"
 bsp config lwip_dhcp "true"
 bsp write
 bsp reload
 catch {bsp regenerate}
 platform generate -domains standalone_domain 
 platform generate -domains zynq_fsbl 
 platform clean
 platform generate
@@ -108,8 +108,8 @@
 #define IP_OPTIONS_ALLOWED 0
 #define TCP_OVERSIZE TCP_MSS
-#define LWIP_DHCP 0
+#define LWIP_DHCP 1
-#define DHCP_DOES_ARP_CHECK 0
+#define DHCP_DOES_ARP_CHECK 1
 #define CONFIG_LINKSPEED_AUTODETECT 1
@@ -108,8 +108,8 @@
 #define IP_OPTIONS_ALLOWED 0
 #define TCP_OVERSIZE TCP_MSS
-#define LWIP_DHCP 0
+#define LWIP_DHCP 1
-#define DHCP_DOES_ARP_CHECK 0
+#define DHCP_DOES_ARP_CHECK 1
 #define CONFIG_LINKSPEED_AUTODETECT 1
@@ -221,6 +221,8 @@ BEGIN LIBRARY
 PARAMETER LIBRARY_NAME = lwip213
 PARAMETER LIBRARY_VER = 1.1
 PARAMETER PROC_INSTANCE = ps7_cortexa9_0
 PARAMETER dhcp_does_arp_check = true
 PARAMETER lwip_dhcp = true
 END
@@ -1,226 +0,0 @@
 PARAMETER VERSION = 2.2.0
 BEGIN OS
 PARAMETER OS_NAME = standalone
 PARAMETER OS_VER = 9.0
 PARAMETER PROC_INSTANCE = ps7_cortexa9_0
 PARAMETER stdin = ps7_uart_1
 PARAMETER stdout = ps7_uart_1
 END
 BEGIN PROCESSOR
 PARAMETER DRIVER_NAME = cpu_cortexa9
 PARAMETER DRIVER_VER = 2.12
 PARAMETER HW_INSTANCE = ps7_cortexa9_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 3.1
 PARAMETER HW_INSTANCE = mydna_read_v1_0_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 3.1
 PARAMETER HW_INSTANCE = ps7_afi_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 3.1
 PARAMETER HW_INSTANCE = ps7_afi_1
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 3.1
 PARAMETER HW_INSTANCE = ps7_afi_2
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 3.1
 PARAMETER HW_INSTANCE = ps7_afi_3
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = coresightps_dcc
 PARAMETER DRIVER_VER = 1.9
 PARAMETER HW_INSTANCE = ps7_coresight_comp_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = ddrps
 PARAMETER DRIVER_VER = 1.2
 PARAMETER HW_INSTANCE = ps7_ddr_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 3.1
 PARAMETER HW_INSTANCE = ps7_ddrc_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = devcfg
 PARAMETER DRIVER_VER = 3.8
 PARAMETER HW_INSTANCE = ps7_dev_cfg_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = dmaps
 PARAMETER DRIVER_VER = 2.9
 PARAMETER HW_INSTANCE = ps7_dma_ns
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = dmaps
 PARAMETER DRIVER_VER = 2.9
 PARAMETER HW_INSTANCE = ps7_dma_s
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = emacps
 PARAMETER DRIVER_VER = 3.19
 PARAMETER HW_INSTANCE = ps7_ethernet_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 3.1
 PARAMETER HW_INSTANCE = ps7_globaltimer_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpiops
 PARAMETER DRIVER_VER = 3.12
 PARAMETER HW_INSTANCE = ps7_gpio_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 3.1
 PARAMETER HW_INSTANCE = ps7_gpv_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 3.1
 PARAMETER HW_INSTANCE = ps7_intc_dist_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 3.1
 PARAMETER HW_INSTANCE = ps7_iop_bus_config_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 3.1
 PARAMETER HW_INSTANCE = ps7_l2cachec_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 3.1
 PARAMETER HW_INSTANCE = ps7_ocmc_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 3.1
 PARAMETER HW_INSTANCE = ps7_pl310_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 3.1
 PARAMETER HW_INSTANCE = ps7_pmu_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = qspips
 PARAMETER DRIVER_VER = 3.11
 PARAMETER HW_INSTANCE = ps7_qspi_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 3.1
 PARAMETER HW_INSTANCE = ps7_qspi_linear_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 3.1
 PARAMETER HW_INSTANCE = ps7_ram_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 3.1
 PARAMETER HW_INSTANCE = ps7_ram_1
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 3.1
 PARAMETER HW_INSTANCE = ps7_scuc_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = scugic
 PARAMETER DRIVER_VER = 5.2
 PARAMETER HW_INSTANCE = ps7_scugic_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = scutimer
 PARAMETER DRIVER_VER = 2.5
 PARAMETER HW_INSTANCE = ps7_scutimer_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = scuwdt
 PARAMETER DRIVER_VER = 2.5
 PARAMETER HW_INSTANCE = ps7_scuwdt_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = sdps
 PARAMETER DRIVER_VER = 4.2
 PARAMETER HW_INSTANCE = ps7_sd_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 3.1
 PARAMETER HW_INSTANCE = ps7_slcr_0
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartps
 PARAMETER DRIVER_VER = 3.13
 PARAMETER HW_INSTANCE = ps7_uart_1
 END
 BEGIN DRIVER
 PARAMETER DRIVER_NAME = xadcps
 PARAMETER DRIVER_VER = 2.7
 PARAMETER HW_INSTANCE = ps7_xadc_0
 END
 BEGIN LIBRARY
 PARAMETER LIBRARY_NAME = lwip213
 PARAMETER LIBRARY_VER = 1.1
 PARAMETER PROC_INSTANCE = ps7_cortexa9_0
 END
@@ -30,6 +30,7 @@
 extern "C" {
 #endif
 #define FSBL_DEBUG
 #define DEBUG_GENERAL	0x00000001    /* general debug  messages */
 #define DEBUG_INFO	0x00000002    /* More debug information */
@@ -0,0 +1,2 @@
 eclipse.preferences.version=1
 encoding/<project>=UTF-8
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="ASCII"?>
-<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="NewInstrCalBoard" location="." platform="../NewInstCal_bsp/export/NewInstCal_bsp/NewInstCal_bsp.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="NewInstrCalBoard_system" sysConfig="NewInstCal_bsp" runtime="C/C++" cpu="standalone_domain" cpuInstance="ps7_cortexa9_0" os="standalone" mssSignature="85660551333151807e7dda7acb0fe4a4">
+<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="NewInstrCalBoard" location="." platform="../NewInstCal_bsp/export/NewInstCal_bsp/NewInstCal_bsp.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="NewInstrCalBoard_system" sysConfig="NewInstCal_bsp" runtime="C/C++" cpu="standalone_domain" cpuInstance="ps7_cortexa9_0" os="standalone" mssSignature="79092dccdc4c42c1a8a8821472211fad">
  <configuration name="Debug" id="xilinx.gnu.armv7.exe.debug.500963658">
    <configBuildOptions xsi:type="sdkproject:SdkOptions"/>
    <lastBuildOptions xsi:type="sdkproject:SdkOptions"/>
@@ -1 +1 @@
-1536657578
+4050237037
@@ -0,0 +1,215 @@
 #include "CPLD_Con.h"
 int CPLD_Checkin()
 {
    int iStatus = -255;
    u32 ureg_data = 0x0;
    u8  uCPLD_Count = 3;
    xil_printf("[I] Start CPLD Check In...\r\n");
    xil_printf("[-]\t Checking CPLD #1\r\n");
    //Read CPLD IDENT Reg
 	iStatus = CPLD_Read(0x1,0x0,&ureg_data);
 	if (iStatus != XST_SUCCESS)
 	{
 		xil_printf("[E] CPLD #1 Communication Failed!\r\n");
 		uCPLD_Count -= 1;
 	}
 	else
 	{
 		if (ureg_data == 0x0)
 		{
 			xil_printf("[E] CPLD #1 Not present! Or SPI communication Failed!\r\n");
 			uCPLD_Count -= 1;
 		}
 		else
 		{
 			if ((ureg_data & 0x200000) != 0x200000)
 			{
 				u8 uCID = 0;
 				uCID = (u8)(ureg_data >> 16);
 				xil_printf("[E] CPLD #1 Firmware mismatch!\r\n[D] Expect CPLD ID == 1, but we received CPLD ID = 0x%02X\r\n",uCID);
 				uCPLD_Count -= 1;
 			}
 			else
 			{
 				u8 uMajorV = 0;
 				u8 uMinorV = 0;
 				u8 uFixV = 0;
 				uMajorV = (u8)((ureg_data & 0x0f00)>>8);
 				uMinorV = (u8)((ureg_data & 0xf0)>>4);
 				uFixV = (u8)(ureg_data & 0xf);
 				xil_printf("[I]\t Successfully Found CPLD #1!\r\n");
 				xil_printf("[I]\t CPLD #1 Version: v%02d.%02d.%02d\r\n",uMajorV,uMinorV,uFixV);
 			}		
 		}
 	}
    xil_printf("[-]\t Checking CPLD #2\r\n");
    //Read CPLD IDENT Reg
 	iStatus = CPLD_Read(0x2,0x0,&ureg_data);
 	if (iStatus != XST_SUCCESS)
 	{
 		xil_printf("[E] CPLD #2 Communication Failed!\r\n");
 		uCPLD_Count -= 1;
 	}
 	else
 	{
 		if (ureg_data == 0x0)
 		{
 			xil_printf("[E] CPLD #2 Not present! Or SPI communication Failed!\r\n");
 			uCPLD_Count -= 1;
 		}
 		else
 		{
 			if ((ureg_data & 0x400000) != 0x400000)
 			{
 				u8 uCID = 0;
 				uCID = (u8)(ureg_data >> 16);
 				xil_printf("[E] CPLD #2 Firmware mismatch!\r\n[D] Expect CPLD ID == 2, but we received CPLD ID = 0x%02X\r\n",uCID);
 				uCPLD_Count -= 1;
 			}
 			else
 			{
 				u8 uMajorV = 0;
 				u8 uMinorV = 0;
 				u8 uFixV = 0;
 				uMajorV = (u8)((ureg_data & 0x0f00)>>8);
 				uMinorV = (u8)((ureg_data & 0xf0)>>4);
 				uFixV = (u8)(ureg_data & 0xf);
 				xil_printf("[I]\t Successfully Found CPLD #2!\r\n");
 				xil_printf("[I]\t CPLD #2 Version: v%02d.%02d.%02d\r\n",uMajorV,uMinorV,uFixV);
 			}		
 		}
 	}
    xil_printf("[-]\t Checking CPLD #3\r\n");
    //Read CPLD IDENT Reg
 	iStatus = CPLD_Read(0x3,0x0,&ureg_data);
 	if (iStatus != XST_SUCCESS)
 	{
 		xil_printf("[E] CPLD #3 Communication Failed!\r\n");
 		uCPLD_Count -= 1;
 	}
 	else
 	{
 		if (ureg_data == 0x0)
 		{
 			xil_printf("[E] CPLD #3 Not present! Or SPI communication Failed!\r\n");
 			uCPLD_Count -= 1;
 		}
 		else
 		{
 			if ((ureg_data & 0x800000) != 0x800000)
 			{
 				u8 uCID = 0;
 				uCID = (u8)(ureg_data >> 16);
 				xil_printf("[E] CPLD #3 Firmware mismatch! Expect CPLD ID == 3, but we received CPLD ID = 0x%02X\r\n",uCID);
 				uCPLD_Count -= 1;
 			}
 			else
 			{
 				u8 uMajorV = 0;
 				u8 uMinorV = 0;
 				u8 uFixV = 0;
 				uMajorV = (u8)((ureg_data & 0x0f00)>>8);
 				uMinorV = (u8)((ureg_data & 0xf0)>>4);
 				uFixV = (u8)(ureg_data & 0xf);
 				xil_printf("[I]\t Successfully Found CPLD #3!\r\n");
 				xil_printf("[I]\t CPLD #3 Version: v%02d.%02d.%02d\r\n",uMajorV,uMinorV,uFixV);
 			}		
 		}
 	}
 	if(uCPLD_Count == 3)
 	{
 		return XST_SUCCESS;
 	}
 	else
 	{
 		xil_printf("[E] Only %d/3 CPLD Device is/are healthy\r\n",uCPLD_Count);
        return XST_DEVICE_NOT_FOUND;
 	}
 }
 int CPLD_Write(u8 addr,u32 data)
 {
 	u16 reg_addr = addr | 0x80;				//Write bit set to 1'b1
 	u8 reg_data[dat_width] = {0};
 	//Data Sanity Check
 	if ((data >> 24) > 0)
 	{
 		xil_printf("[E] CPLD data length should within 24 bits!\r\n");
 		return XST_INVALID_PARAM;
 	}
 	reg_data[0] = (u8)(data >> 16);
 	reg_data[1] = (u8)(((data)&0xff00)>>8);
 	reg_data[2] = (u8)data;
 	spi_write_onewire(reg_addr, reg_data, dat_width, CPLD_U1);
 	spi_write_onewire(reg_addr, reg_data, dat_width, CPLD_U2);
 	spi_write_onewire(reg_addr, reg_data, dat_width, CPLD_U3);
 	return XST_SUCCESS;
 }
 int CPLD_Read(u8 CPLDSel, u8 reg_addr, u32* reg_data)
 {
    switch (CPLDSel)
    {
        case 1:
        {
            *reg_data = uspi_read_onewire(reg_addr, dat_width,CPLD_U1);
            break;
        }
        case 2:
        {
            *reg_data = uspi_read_onewire(reg_addr, dat_width,CPLD_U2);
            break;
        }
        case 3:
        {
            *reg_data = uspi_read_onewire(reg_addr, dat_width,CPLD_U3);
            break;
        }
        default:
        {
            xil_printf("[E] CPLD Select Num Error (Range 1-3)\r\n");
            return XST_INVALID_PARAM;
        }
    }
    return XST_SUCCESS;
 }
 int CPLD_Read_ALL(u8 reg_addr, u32* reg_data)
 {
    //TODO:Sanity Check
    reg_data[0]=uspi_read_onewire(reg_addr, dat_width,CPLD_U1);
    reg_data[1]=uspi_read_onewire(reg_addr, dat_width,CPLD_U2);
    reg_data[2]=uspi_read_onewire(reg_addr, dat_width,CPLD_U3);
    //TODO:SUCCESS Check
    return XST_SUCCESS;
 }
 int CPLD_exec()
 {
 	u8 reg_addr = 0x01;
    u8 sw_config_data[3] = {0x00,0x00,0x00};
 	sw_config_data[0] = 0x00;
 	sw_config_data[1] = 0x00;
 	sw_config_data[2] = 0x01;
 	reg_addr = reg_addr | 0x80;
 	spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U1);
 	spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U2);
 	spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U3);
 	return XST_SUCCESS;
 }
@@ -0,0 +1,20 @@
 #ifndef CPLD_CON_H_
 #define CPLD_CON_H_
 #include <stdio.h>
 #include <xstatus.h>
 #include <xparameters.h>
 #include "GPIO_Driv.h"
 #include "SPI_Driv.h"
 #define dat_width     3
 int CPLD_Checkin();
 int CPLD_Write(u8 addr,u32 data);
 int CPLD_Read(u8 CPLDSel, u8 reg_addr, u32* reg_data);
 int CPLD_Read_ALL(u8 reg_addr, u32* reg_data);
 int CPLD_exec();
 #endif /* CPLD_CON_H_ */
@@ -26,7 +26,7 @@ int EMIO_config(void)
 		}
 		else
 		{
-			xil_printf("[I] Successfully Find PS GPIO!\r\n");
+			xil_printf("[D] Successfully Find PS GPIO!\r\n");
 		}
 		xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
@@ -0,0 +1 @@
 Empty application. Add your own sources.
@@ -59,7 +59,7 @@ void rst_CPLD(u32* device,u32 num_wire) //wire_num = cs sck sdi/o
 * 				device -- CPLD
 * Return      : void
 ******************************************************************************/
-void spi_write_onewire(char addr, char *data, char width, u32* device)
+void spi_write_onewire(u8 addr, u8 *data, u8 width, u32* device)
 {
 	char  temp_addr = 0;
 	//u32   temp_data = 0;
@@ -128,7 +128,7 @@ void spi_write_onewire(char addr, char *data, char width, u32* device)
 * 				data   -- 数据
 * 				width  -- 数据长度
 * 				device -- CPLD
-* Return      : void
+* Return      : void		//??????
 ******************************************************************************/
 u32	spi_read_onewire(char addr, char width, u32* device,char* read_data)
 {
@@ -193,6 +193,74 @@ u32	spi_read_onewire(char addr, char width, u32* device,char* read_data)
 	return temp_data;
 }
 /******************************************************************************
 * Function    : u32	uspi_read_onewire(char addr, char width, u32* device)
 * Description : spi onewire read
 * Parameter   : addr   -- 地址
 * 				width  -- 数据长度
 * 				device -- CPLD
 * Return      : u32 reg_data
 ******************************************************************************/
 u32	uspi_read_onewire(char addr, char width, u32* device)
 {
 	char  temp_addr=0;
 	u32	  temp_data=0;
 	char  i=0,j=0;
 	u32   sck = *(device+0);
 	u32	  cs= *(device+1);
 	u32   sdi= *(device+2);
 	u32   sdo= *(device+3);
 	temp_addr = addr;
 	//XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
 	//XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);		// w/r标志位    1=w 0=r
 	//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	for(i = 0; i < 8; i++)								// 8bit地址
 	{
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 		XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 	    if(temp_addr&0x80)
 	    	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据     数据从中间变量到通信线上
 	    else
 	    	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 	    temp_addr = temp_addr<<1;                       //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
 	}
 	for(j=0; j<width; j++)
 	{
 			for(i = 0; i < 8; i++)                             //nbit数据
 			{
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 				temp_data = temp_data << 1;                     //sck低电平准备数据    准备好数位，此时的数据相当于从右边的FPGA移进MCU(先准备好中间变量)
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
 				if(XGpioPs_ReadPin(&psGpioInstancePtr,sdo))    //sck高电平接收数据     数据匹配到准备好的数位，等待一起传递到MCU
 					temp_data = temp_data| 0x00000001;
 				XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 			    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
 			}
 	}
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
    XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
 	XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
 	return temp_data;
 }
 /******************************************************************************
 * Function    : void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
 * Description : forwire write to reg
@@ -33,9 +33,11 @@ void rst_CPLD(u32* device,u32 num_wire);
 void  rst(char *d);
-void spi_write_onewire(char addr, char *data, char width, u32* device);
+void spi_write_onewire(u8 addr, u8 *data, u8 width, u32* device);
 u32	 spi_read_onewire(char addr,char width,u32* device,char* read_data);
 u32	 uspi_read_onewire(char addr, char width, u32* device);
 void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3);
 u16	fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3);
 void spi_write_fourwire(char addr,u16 data,u32* device);
@@ -6,8 +6,297 @@
 */
 #include "cal_meas.h"
-#include "SPI_Driv.h"
+
-char     sw_config_data[3] = {0x00,0x00,0x00};
+int Command_Parser(u8* recvbuffer, u8 len)
 {
 	int iStatus = -255;
 	switch (recvbuffer[0])
 	{
 		case 0x00:
 		{
 			xil_printf("[D] Match Command CPLD Read\r\n");
 			if (len != CPLD_SPI_READ + 1)
 			{
 				xil_printf("[E] Command Length Mismatch!\r\n[I] CPLD Read Format: \"00 [CPLD] [REG Addr]\"\r\n");
 				return XST_INVALID_PARAM;
 			}
 			u32 reg_data = 0x0;
 			iStatus = CPLD_Read(recvbuffer[1], recvbuffer[2], &reg_data);
 			xil_printf("[I] CPLD #%d: REG Addr #0x%01X: Data=0x%06X\r\n",recvbuffer[1], recvbuffer[2], reg_data);
 			break;
 		}
 		case 0x01:
 		{
 			xil_printf("[D] Match Command CPLD Write\r\n");
 			if (len != CPLD_SPI_WRITE + 1)
 			{
 				xil_printf("[E] Command Length Mismatch!\r\n[I] CPLD Write Format: \"01 [CPLD] [REG Addr] [Data]\"\r\n");
 				return XST_INVALID_PARAM;
 			}
 			xil_printf("[D] TBD!\r\n");
 			break;
 		}
 		case 0xA0:
 		{
 			int iStatus = -255;
 			xil_printf("[D] Matched Command Reset\r\n");
 			rst_CPLD(CPLD_U1,4);
 			rst_CPLD(CPLD_U2,4);
 			rst_CPLD(CPLD_U3,4);
 			xil_printf("[I] CPLD RST Done\r\n");
 			iStatus = CPLD_Checkin();
 			if (iStatus != XST_SUCCESS)
 			{
 				xil_printf("[E] CPLD Check-in Failed!\r\n");
 				return XST_FAILURE;
 			}
 			else
 			{
 				xil_printf("[I] All 3/3 CPLD Checked In!\r\n");
 			}
 			break;
 		}
 		case 0xA1:			//DC Cal
 		{
 			xil_printf("[D] Matched Command DC Cal\r\n");
 			//Command Len Sanity Check
 			if (len != DC_CMD_LEN + 1)		//Do NOT forget the command header
 			{
 				xil_printf("[E] Command Length Mismatch!\r\n[I] DC Cal Format: \"A1 [01-04:SLOT] [01:PMU/02:DPS] [0001-0100:Channel_Num] [01:V/02:I] [01-12:RLoad]\"\r\n");
 				return XST_INVALID_PARAM;
 			}
 			DC_Control(recvbuffer + 1);		//Op-out the command header
 			break;
 		}
 		case 0xA2:			//Freq Cal
 		{
 			xil_printf("[D] Matched Command Freq Cal\r\n");
 			if (len > Freq_CMD_LEN + 1)		//Do NOT forget the command header
 			{
 				//TODO: ADD Freq Command Format Hint
 				xil_printf("[E] Command Length Mismatch!\r\n[I] Freq Cal Format: TBD\r\n");
 				return XST_INVALID_PARAM;
 			}
 			sw_config(recvbuffer + 1);		//Op-out the command header
 			break;
 		}
 		default:
 		{
 			xil_printf("[E] Command Header No Match! \r\n[D] Received Command Header:0x%02X Check Command!\r\n",recvbuffer[0]);
 			return XST_NO_FEATURE;
 		}
 	}
 }
 int DC_Control(u8* idata)
 {
 	//Comannd Parse Variables
 	u8  u_slot       = 0x0;
 	u8  u_m_fun      = 0x0;			//PMU/DPS Sel
 	u16 u_ch_Num     = 0x0;			
 	u8  u_vi_Sel     = 0x0;			//DMM Connection Config
 	u8  u_rLoad      = 0x0;			//rLoadSel
 	//CPLD Variables
 	u8 reg_addr		= 0x0;
 	u32 reg_data 	= 0x0;
 	//Flags
 	int Status = -255;
 	int cmdValid = 1;
 	//We already did length check, so no need to do again here
 	u_slot = idata[0];										//1-4
 	u_m_fun = idata[1];										//1:PMU/2:DPS
 	u_ch_Num = (((u16)(idata[2])) << 8) | idata[3];
 	u_vi_Sel = idata[4];										//1:V/2:I
 	u_rLoad = idata[5];										//1~18: Refer to SCH/Protocol
 	//Let's do some sanity check
 	//Slot
 	if (u_slot > 4)
 	{
 		xil_printf("[E] Illege Slot Num check Command! (Slot:0(OFF)-4)\r\n");
 		cmdValid = -1;
 	}
 	//Dev Sel
 	if ((u_m_fun > 2) || (u_m_fun == 0))
 	{
 		xil_printf("[E] Illege Dev Select check Command! (1:PMU/2:DPS)\r\n");
 		cmdValid = -2;
 	}
 	//Channel
 	if (u_m_fun == 1)			//PMU
 	{
 		if ((u_ch_Num < 1) || (u_ch_Num > 256))
 		{
 			xil_printf("[E] Illege Channel! (PMU Ch:0x0001-0x0100)\r\n");
 			cmdValid = -2;
 		}
 	}
 	else
 	{
 		if ((u_ch_Num < 1) || (u_ch_Num > 64))
 		{
 			xil_printf("[E] Illege Channel! (DPS Ch:0x0000-0x0040)\r\n");
 			cmdValid = -3;
 		}
 	}
 	//V/I Sel
 	if ((u_vi_Sel > 2) || (u_vi_Sel == 0))
 	{
 		xil_printf("[E] Illege V/I Config check Command! (1:V/2:I)\r\n");
 		cmdValid = -5;
 	}
 	//RLoad Sel
 	if (u_rLoad > 18)
 	{
 		xil_printf("[E] Illege RLoad Select check Command! (RLoad:0x00(OPEN)-0x12)\r\n");
 		cmdValid = -6;
 	}
 	if (cmdValid != 1)
 	{
 		return XST_INVALID_PARAM;
 	}
 	//DEBUG Printout
 	xil_printf("[D] We Got:\r\n[-]\tSlot: #%d\r\n",u_slot);
 	if (u_m_fun == 1)
 	{
 		xil_printf("[-]\tDevice Select: PMU\r\n");
 	}
 	else
 	{
 		xil_printf("[-]\tDevice Select: DPS\r\n");
 	}
 	xil_printf("[-]\tChannel Select: #%d\r\n",u_ch_Num);
 	if (u_vi_Sel == 1)
 	{
 		xil_printf("[-]\tDMM Measure Select: Voltage\r\n");
 	}
 	else
 	{
 		xil_printf("[-]\tDMM Measure Select: Current\r\n");
 	}
 	if (u_rLoad == 0)
 	{
 		xil_printf("[-]\tRLoad Select: #0(No Load)\r\n",u_rLoad);
 	}
 	else
 	{
 		xil_printf("[-]\tRLoad Select: #%d\r\n",u_rLoad);
 	}
 	//Sanity Check Done
 	//Let's format the CPLD Reg Data
 	//As the structure of DC regs are the same, we can format the data uniformly
 	//Dev Sel
 	if (u_m_fun == 0x2)
 	{
 		reg_data = 0x800000;			//1:DPS/0:PMU
 	}
 	//V/I Sel
 	if (u_vi_Sel == 0x2)
 	{
 		reg_data = reg_data | 0x400000;	//1:I/0:V
 	}
 	//RLoad Sel
 	reg_data = reg_data | (((u32)u_rLoad)<<17);
 	//Channel Sel
 	reg_data = reg_data |((u32)(u_ch_Num)<<1) | 0x1;			//0x1:Slot_EN
 	//We should clear out other slot's enable flag to prevent error
 	Status = 0;
 	//Note here as the CPLD_Write() will smartly set the R/W bit to 1'b1, so no need to handle that here, addr is addr
 	switch (u_slot)
 	{
 		case 1:
 		{
 			Status = Status + CPLD_Write(0x07, 0x0);
 			Status = Status + CPLD_Write(0x08, 0x0);
 			Status = Status + CPLD_Write(0x09, 0x0);
 			reg_addr = 0x06;
 			Status = Status + CPLD_Write(reg_addr, reg_data);
 			break;
 		}
 		case 2:
 		{
 			Status = Status + CPLD_Write(0x06, 0x0);
 			Status = Status + CPLD_Write(0x08, 0x0);
 			Status = Status + CPLD_Write(0x09, 0x0);
 			reg_addr = 0x07;
 			Status = Status + CPLD_Write(reg_addr, reg_data);
 			break;
 		}
 		case 3:
 		{
 			Status = Status + CPLD_Write(0x06, 0x0);
 			Status = Status + CPLD_Write(0x07, 0x0);
 			Status = Status + CPLD_Write(0x09, 0x0);
 			reg_addr = 0x08;
 			Status = Status + CPLD_Write(reg_addr, reg_data);
 			break;
 		}
 		case 4:
 		{
 			Status = Status + CPLD_Write(0x06, 0x0);
 			Status = Status + CPLD_Write(0x07, 0x0);
 			Status = Status + CPLD_Write(0x08, 0x0);
 			reg_addr = 0x09;
 			Status = Status + CPLD_Write(reg_addr, reg_data);
 			break;
 		}
 		default:				//You should NOT be here
 		{
 			xil_printf("[E] Error Reaching Invaild Slot CPLD Formatting, Check PS Code!\r\n");
 			return XST_FAILURE;
 		}
 	}
 	if (Status != XST_SUCCESS)
 	{
 		xil_printf("[E] Error Writing CPLD Reg! Check Log ABOVE!\r\n");
 		return XST_FAILURE;
 	}
 	else
 	{
 		xil_printf("[D] CPLD Write Successfully Done!\r\n");
 	}
 	Status = CPLD_exec();
 	if (Status != XST_SUCCESS)
 	{
 		xil_printf("[E] Error Exec CPLD ! Check Log ABOVE!\r\n");
 		return XST_FAILURE;
 	}
 	else
 	{
 		xil_printf("[D] CPLD Exec Successfully Done!\r\n");
 	}
 	return XST_SUCCESS;
 }
 void  sw_config(char *slot_start)
 {
@@ -26,6 +315,7 @@ void  sw_config(char *slot_start)
 		 u8      cpld_addr = 0;
 		 u32     cpld_dat  = 0;
 		 u8      sw_config_data[3] = {0x00,0x00,0x00};
 		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
@@ -10,14 +10,22 @@
 #include "sleep.h"
 #include "stdio.h"
 #include "xstatus.h"
 #include "xgpiops.h"
-#include "SPI_Driv.h"
+
 #include "GPIO_Driv.h"
 #include "CPLD_Con.h"
 #define CPLD_SPI_WRITE 5
 #define CPLD_SPI_READ 2
 #define DC_CMD_LEN 6
 #define Freq_CMD_LEN 7      //TODO: Update sw_config()!
-#define    dat_width     3
+int Command_Parser(u8 *recvbuffer, u8 len);
-
+int DC_Control(u8* idata);
-void       sw_config(char *slot_start);
+int CPLD_Write(u8 addr,u32 data);
 int CPLD_exec();
 void sw_config(char *slot_start);
 #endif /* SRC_CAL_MEAS_H_ */
@@ -1,237 +0,0 @@
 /*
 * Copyright (C) 2009 - 2019 Xilinx, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
 * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
 * OF SUCH DAMAGE.
 *
 */
 #include <stdio.h>
 #include <string.h>
 #include "dna_read.h"
 #include "crc16.h"
 #include "GPIO_Driv.h"
 #include "SPI_Driv.h"
 #include "cal_meas.h"
 #include "lwip/err.h"
 #include "lwip/tcp.h"
 #if defined (__arm__) || defined (__aarch64__)
 #include "xil_printf.h"
 #endif
 char *recv_data;
 char dna_data[10];
 unsigned short recv_len;
 unsigned  read_dat = 0;
 char 	  dat_0[20] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
 unsigned  crc_read_dat = 0;
 char     crc_alg_dat[2] = {0,0};
 char     send_data_cpld1[2] = {0xAA,0x56};
 int transfer_data() {
 	return 0;
 }
 void print_app_header()
 {
 #if (LWIP_IPV6==0)
 	xil_printf("\n\r\n\r-----lwIP TCP echo server ------\n\r");
 #else
 	xil_printf("\n\r\n\r-----lwIPv6 TCP echo server ------\n\r");
 #endif
 	xil_printf("TCP packets sent to port 6001 will be echoed back\n\r");
 }
 err_t recv_callback(void *arg, struct tcp_pcb *tpcb,
                               struct pbuf *p, err_t err)
 {
 	/* do not read the packet if we are not in ESTABLISHED state */
 	if (!p) {
 		tcp_close(tpcb);
 		tcp_recv(tpcb, NULL);
 		return ERR_OK;
 	}
 	/* indicate that the packet has been received */
 	tcp_recved(tpcb, p->len);
 	/* echo back the payload */
 	/* in this case, we assume that the payload is < TCP_SND_BUF */
 	if (tcp_sndbuf(tpcb) > p->len) {
 		recv_len = p->len;
 		recv_data = (char*)malloc(sizeof(char)*recv_len);
 	    memcpy(recv_data,p->payload,recv_len);
 	    if(recv_data[6] == 0x0E)
 	    {
 	    	crc_read_dat = do_crc_table(recv_data+6, recv_len-8);
 	    	crc_alg_dat[0] = (u8)crc_read_dat;
 	    	crc_alg_dat[1] = (u8)(crc_read_dat>>8);
 	    	dat_0[0]= 0x00;
 	    	switch(recv_data[7])
 	    	{
 	    	  case 0xA2://SLOT
 	    	          {
 						  dat_0[1]= 0x06;
 						  dat_0[2]= recv_data[2];
 						  dat_0[3]= recv_data[3];
 						  dat_0[4]= recv_data[4];
 						  dat_0[5]= recv_data[5];
 						  dat_0[6]= recv_data[6];
 						  dat_0[7]= recv_data[7];
 	    	        	  if(recv_data[15]==crc_alg_dat[1]&&recv_data[16]==crc_alg_dat[0])
 	    	        	  {
 	    	        		  dat_0[8]= 0x01;
 	    	        		  dat_0[9]= 0x01;
 	    	        	  }
 	    	        	  else
 						  {
 							  dat_0[8]= 0xff;
 							  dat_0[9]= 0xff;
 						  }
 	    	        	  dat_0[10]= recv_data[15];
 	    	        	  dat_0[11]= recv_data[16];
 	    	        	  char slot_start[7] = {recv_data[8],recv_data[9],recv_data[10],recv_data[11],recv_data[12],recv_data[13],recv_data[14]};
 	    	        	  //xil_printf("slot_start[0]:%x, slot_start[1]:%x,slot_start[2]:%x,slot_start[3]:%x,slot_start[4]:%x,slot_start[5]:%x,slot_start[6]:%x\n\r", slot_start[0],slot_start[1],slot_start[2],slot_start[3],slot_start[4],slot_start[5],slot_start[6]);
 	    	        	  //rst_CPLD(CPLD_U1,4);
 	    	        	  //rst_CPLD(CPLD_U2,4);
 	    	        	  //rst_CPLD(CPLD_U3,4);
 	    	        	  sw_config(slot_start);
 	    	        	  tcp_write(tpcb, dat_0, 12, 1);
 	    	        	  break;
 	    	          }
 	    	  case 0xA3://dna_port_read
 					  {
 						  dna_port_read(dna_data);
 						  dat_0[1]=0x0e;
 						  dat_0[2]=recv_data[2];
 						  dat_0[3]=recv_data[3];
 						  dat_0[4]=recv_data[4];
 						  dat_0[5]=recv_data[5];
 						  dat_0[6]=recv_data[6];
 						  dat_0[7]=recv_data[7];
 						  if(recv_data[8]==crc_alg_dat[1]&&recv_data[9]==crc_alg_dat[0])
 						  {
 							  dat_0[8]= 0x01;
 							  dat_0[9]= 0x01;
 						  }
 						  else
 						  {
 							  dat_0[8]= 0xff;
 							  dat_0[9]= 0xff;
 						  }
 						  dat_0[10]= dna_data[0];
 						  dat_0[11]= dna_data[1];
 						  dat_0[12]= dna_data[2];
 						  dat_0[13]= dna_data[3];
 						  dat_0[14]= dna_data[4];
 						  dat_0[15]= dna_data[5];
 						  dat_0[16]= dna_data[6];
 						  dat_0[17]= dna_data[7];
 						  dat_0[18]= recv_data[8];
 						  dat_0[19]= recv_data[9];
 						  tcp_write(tpcb, dat_0, 20, 1);
 						  break;
 					  }
 	    	}
 	    }
 	} else
 		xil_printf("no space in tcp_sndbuf\n\r");
 	/* free the received pbuf */
 	pbuf_free(p);
 	return ERR_OK;
 }
 err_t accept_callback(void *arg, struct tcp_pcb *newpcb, err_t err)
 {
 	static int connection = 1;
 	/* set the receive callback for this connection */
 	tcp_recv(newpcb, recv_callback);
 	/* just use an integer number indicating the connection id as the
 	   callback argument */
 	tcp_arg(newpcb, (void*)(UINTPTR)connection);
 	/* increment for subsequent accepted connections */
 	connection++;
 	return ERR_OK;
 }
 int start_application()
 {
 	struct tcp_pcb *pcb;
 	err_t err;
 	unsigned port = 200;
 	/* create new TCP PCB structure */
 	pcb = tcp_new_ip_type(IPADDR_TYPE_ANY);
 	if (!pcb) {
 		xil_printf("Error creating PCB. Out of Memory\n\r");
 		return -1;
 	}
 	/* bind to specified @port */
 	err = tcp_bind(pcb, IP_ANY_TYPE, port);
 	if (err != ERR_OK) {
 		xil_printf("Unable to bind to port %d: err = %d\n\r", port, err);
 		return -2;
 	}
 	/* we do not need any arguments to callback functions */
 	tcp_arg(pcb, NULL);
 	/* listen for connections */
 	pcb = tcp_listen(pcb);
 	if (!pcb) {
 		xil_printf("Out of memory while tcp_listen\n\r");
 		return -3;
 	}
 	/* specify callback to use for incoming connections */
 	tcp_accept(pcb, accept_callback);
 	xil_printf("TCP echo server started @ port %d\n\r", port);
 	return 0;
 }
@@ -0,0 +1,194 @@
 #include "lwip_server.h"
 int transfer_data() {
 	return 0;
 }
 void print_app_header()
 {
 	xil_printf("[I] New ExtInstrument Calibration Board Zynq Controller lwip stack...\r\n");
 	xil_printf("[I] Net: Hello World!\r\n");
 }
 int start_application()
 {
 	struct tcp_pcb *pcb;
 	err_t err;
 	unsigned port = 200;
 	/* create new TCP PCB structure */
 	pcb = tcp_new_ip_type(IPADDR_TYPE_ANY);
 	if (!pcb) {
 		xil_printf("[E] Error creating PCB. Out of Memory\n\r");
 		return -1;
 	}
 	/* bind to specified @port */
 	err = tcp_bind(pcb, IP_ANY_TYPE, port);
 	if (err != ERR_OK) {
 		xil_printf("[E] Unable to bind to port %d: err = %d\n\r", port, err);
 		return -2;
 	}
 	/* we do not need any arguments to callback functions */
 	tcp_arg(pcb, NULL);
 	/* listen for connections */
 	pcb = tcp_listen(pcb);
 	if (!pcb) {
 		xil_printf("Out of memory while tcp_listen\n\r");
 		return -3;
 	}
 	/* specify callback to use for incoming connections */
 	tcp_accept(pcb, accept_callback);
 	xil_printf("[I] NewExtInstCal Zynq server started @ port %d\n\r", port);
 	return 0;
 }
 err_t accept_callback(void *arg, struct tcp_pcb *newpcb, err_t err)
 {
 	static int connection = 1;
 	/* set the receive callback for this connection */
 	tcp_recv(newpcb, recv_callback);
 	/* just use an integer number indicating the connection id as the
 	   callback argument */
 	tcp_arg(newpcb, (void*)(UINTPTR)connection);
 	/* increment for subsequent accepted connections */
 	connection++;
 	return ERR_OK;
 }
 err_t recv_callback(void *arg, struct tcp_pcb *tpcb,
                               struct pbuf *p, err_t err)
 {
    u32 Recv_Len;
    char *Recv_Data;
    u16 uCRC_Read_Dat;
    u8 uCRC_Result[2]={0};
    u8 uSend_Data[20] = {0};
    u8 uCRC_Flag = 255;
 	/* do not read the packet if we are not in ESTABLISHED state */
 	if (!p) {
 		tcp_close(tpcb);
 		tcp_recv(tpcb, NULL);
 		return ERR_OK;
 	}
 	/* indicate that the packet has been received */
 	tcp_recved(tpcb, p->len);
 	/* Here, we assume that the payload is < TCP_SND_BUF */
    if (tcp_sndbuf(tpcb) > p->len) {
 		Recv_Len = p->len;
 		Recv_Data = (char*)malloc(sizeof(char)*Recv_Len);
 	    memcpy(Recv_Data,p->payload,Recv_Len);
    //Start of CRC Check 
        uCRC_Read_Dat = do_crc_table(Recv_Data+6, Recv_Len-8);
        uCRC_Result[0] = (u8)uCRC_Read_Dat;
        uCRC_Result[1] = (u8)(uCRC_Read_Dat>>8);
        if (!(Recv_Data[15]==uCRC_Result[1]&&Recv_Data[16]==uCRC_Result[0]))
        {
            xil_printf("[E] CRC Mismatch! Check communication!\r\n");
            uCRC_Flag = 255;
        }
        else
        {
            xil_printf("[D] CRC Match!\r\n");
            uCRC_Flag = 1;
        }
    //End of CRC Check 
    //Start of SendBack Formation
        uSend_Data[0] = 0x00;
        uSend_Data[1] = Recv_Data[1];
        uSend_Data[2] = Recv_Data[2];
        uSend_Data[3] = Recv_Data[3];
        uSend_Data[4] = Recv_Data[4];
        uSend_Data[5] = Recv_Data[5];
        uSend_Data[6] = Recv_Data[6];
        uSend_Data[7] = Recv_Data[7];
        uSend_Data[8] = uCRC_Flag;
        uSend_Data[9] = uCRC_Flag;
        uSend_Data[10] = Recv_Data[15];             //Shouldn't We Re-calculate CRC? Why send back the old CRC?
        uSend_Data[11] = Recv_Data[16];             //Same as above
    //End of SendBack Formation
        //Matching Zynq Cal Instruction Header
        if(Recv_Data[6] == 0x0E)
        {
            if (Recv_Data[7] == 0xA2)               //Cal
            {
                switch (Recv_Data[14])              //By Judging Equipment to decide cal type
                {
                case 0x00:                          //DC Cal
                {
                    u8 uCMD[DC_CMD_LEN] = {0};
                    uCMD[0] = Recv_Data[8];
                    if (Recv_Data[9] < 3)
                    {
                        xil_printf("[E] DPS Single Force/Sense Not Support!\r\n");
                    }
                    else
                    {
                        if (Recv_Data[9] == 0x03)   //Select DPS
                        {
                            uCMD[1] = 0x2;
                        }
                        else if (Recv_Data[9] == 0x04)//Select PMU
                        {
                            uCMD[1] = 0x1;
                        }
                        else
                        {
                            xil_printf("[E] Device Not Support!\r\n");
                        }
                    }
                    uCMD[2] = Recv_Data[10];
                    uCMD[3] = Recv_Data[11];
                    uCMD[4] = Recv_Data[12] + 1;
                    uCMD[5] = Recv_Data[13];
                    DC_Control(uCMD);
                    break;
                }
                case 0x01:                          //Freq Cal
                {
                    u8 uCMD[Freq_CMD_LEN] = {Recv_Data[8],Recv_Data[9],Recv_Data[10],Recv_Data[11],Recv_Data[12],Recv_Data[13],Recv_Data[14]};
                    sw_config(uCMD);
                    break;
                }
                default:                            //You shouldn't be here
                    break;
                }
            }
        }
        tcp_write(tpcb, uSend_Data, sizeof(uSend_Data), 1);
    }
    else
    {
 		xil_printf("no space in tcp_sndbuf\n\r");
    }
    /* free the received pbuf */
 	pbuf_free(p);
 	return ERR_OK;
 }
@@ -0,0 +1,29 @@
 #ifndef SRC_LWIP_SERVER_H_
 #define SRC_LWIP_SERVER_H_
 #include <stdio.h>
 #include <string.h>
 #include "xstatus.h"
 #include "xgpiops.h"
 #include "lwip/err.h"
 #include "lwip/tcp.h"
 #if defined (__arm__) || defined (__aarch64__)
 #include "xil_printf.h"
 #endif
 #include "cal_meas.h"
 int transfer_data();
 void print_app_header();
 int start_application();
 err_t accept_callback(void *arg, struct tcp_pcb *newpcb, err_t err);
 err_t recv_callback(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err);
 err_t accept_callback(void *arg, struct tcp_pcb *newpcb, err_t err);
 #endif
@@ -28,28 +28,169 @@
 #include <stdio.h>
 #include "xparameters.h"
 #include "netif/xadapter.h"
 #include "platform.h"
 #include "platform_config.h"
 #if defined (__arm__) || defined(__aarch64__)
 #include "xil_printf.h"
 #endif
-
+#include "netif/xadapter.h"
 #include "lwipopts.h"
 #include "sleep.h"
 #include "lwip/priv/tcp_priv.h"
 #include "lwip/init.h"
 #include "lwip/inet.h"
 #include "xil_cache.h"
 extern void tcp_tmr(void);  /* declared in tcp_priv.h, not in public tcp.h */
 #include "xil_cache.h"
 #if LWIP_DHCP==1
 #include "lwip/dhcp.h"
 extern volatile int dhcp_timoutcntr;
 #endif
 #include "GPIO_Driv.h"
 #include "SPI_Driv.h"
 #include "cal_meas.h"
 #include "uart_IO.h"
 #include "CPLD_Con.h"
 #include "lwip_server.h"
 #define MAJORV 0
 #define MINORV 1
 #define FIXV 3
 #define DEFAULT_IP_ADDRESS	"192.168.100.110"
 #define DEFAULT_IP_MASK		"255.255.255.0"
 #define DEFAULT_GW_ADDRESS	"192.168.100.1"
 u8 recvbuffer[1024] = {0};
 extern volatile int TcpFastTmrFlag;
 extern volatile int TcpSlowTmrFlag;
 /* defined by each RAW mode application */
 void print_app_header();
 int start_application();
 int transfer_data();
 /* missing declaration in lwIP */
 void lwip_init();
 struct netif server_netif;
 struct netif *netif;
 static void print_ip(char *msg, ip_addr_t *ip)
 {
 	print(msg);
 	xil_printf("%d.%d.%d.%d\r\n", ip4_addr1(ip), ip4_addr2(ip),
 			ip4_addr3(ip), ip4_addr4(ip));
 }
 static void print_ip_settings(ip_addr_t *ip, ip_addr_t *mask, ip_addr_t *gw)
 {
 	print_ip("Board IP:       ", ip);
 	print_ip("Netmask :       ", mask);
 	print_ip("Gateway :       ", gw);
 }
 static void assign_default_ip(ip_addr_t *ip, ip_addr_t *mask, ip_addr_t *gw)
 {
 	int err;
 	xil_printf("Configuring default IP %s \r\n", DEFAULT_IP_ADDRESS);
 	err = inet_aton(DEFAULT_IP_ADDRESS, ip);
 	if (!err)
 		xil_printf("Invalid default IP address: %d\r\n", err);
 	err = inet_aton(DEFAULT_IP_MASK, mask);
 	if (!err)
 		xil_printf("Invalid default IP MASK: %d\r\n", err);
 	err = inet_aton(DEFAULT_GW_ADDRESS, gw);
 	if (!err)
 		xil_printf("Invalid default gateway address: %d\r\n", err);
 }
 static int net_is_available(void)
 {
 	if (netif == NULL)
 		return 0;
 	if (!netif_is_up(netif))
 		return 0;
 	if (netif->ip_addr.addr == 0)
 		return 0;
 	return 1;
 }
 int main()
 {
 	int iMainCom = 1;
 	int iStatus = -255;
 	ip_addr_t ipaddr, netmask, gw;
 	unsigned char mac_ethernet_address[] = { 0x00, 0x0a, 0x35, 0x00, 0x01, 0x01 };
 	netif = &server_netif;
 	init_platform();
-	xil_printf("=====================\r\n[I] System Init Done!\r\n");
+//LWIP Related Init Start
 	lwip_init();
 	/* Add network interface to the netif_list, and set it as default */
 	if (!xemac_add(netif, NULL, NULL, NULL, mac_ethernet_address,
 				PLATFORM_EMAC_BASEADDR)) {
 		xil_printf("Error adding N/W interface\r\n");
 		return -1;
 	}
 	netif_set_default(netif);
 #ifndef SDT
 	/* now enable interrupts */
 	platform_enable_interrupts();
 #endif
 	/* specify that the network if is up */
 	netif_set_up(netif);
 #if (LWIP_DHCP==1)
 	/* Create a new DHCP client for this interface.
 	 * Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at
 	 * the predefined regular intervals after starting the client.
 	 */
 	dhcp_start(netif);
 	dhcp_timoutcntr = 3;
 	while (((netif->ip_addr.addr) == 0) && (dhcp_timoutcntr > 0))
 		xemacif_input(netif);
 	if (dhcp_timoutcntr <= 0) {
 		if ((netif->ip_addr.addr) == 0) {
 			xil_printf("ERROR: DHCP request timed out\r\n");
 			assign_default_ip(&(netif->ip_addr),
 					&(netif->netmask), &(netif->gw));
 		}
 	}
 	/* print IP address, netmask and gateway */
 #else
 	assign_default_ip(&(netif->ip_addr), &(netif->netmask), &(netif->gw));
 #endif
 	print_ip_settings(&(netif->ip_addr), &(netif->netmask), &(netif->gw));
 	xil_printf("\r\n");
 	/* start the application (web server, rxtest, txtest, etc..) */
 	start_application();
 //LWIP Related Init END
 	/* Check if network is actually available, fallback to UART if not */
 	if (!net_is_available()) {
 		xil_printf("[W] Network unavailable, falling back to UART\r\n");
 		iMainCom = 0;
 	}
 	xil_printf("\r\n=====================[I] System Init Done!=====================\r\n");
 	xil_printf("\r\n[I] Zynq Version:NewInstCal v%d.%d.%d\r\n\r\n",MAJORV,MINORV,FIXV);
 	xil_printf("[D] Start EMIO Config\r\n");
 	EMIO_config();
@@ -66,18 +207,52 @@ int main()
 	interface_initial(CPLD_U2);
 	interface_initial(CPLD_U3);
-	xil_printf("[I] Board Init Complete!\r\n[I] Waiting for Command...\r\n");
+	iStatus = CPLD_Checkin();
-	/* receive and process Instructions */
+	if (iStatus != XST_SUCCESS)
 	int len = 0;
 	while (1) 
 	{
-		int Status = -255;
+		xil_printf("[E] main() stopped!\r\n");
-		Status = UART_RecvInstr(recvbuffer);
+		return XST_FAILURE;
-		if (Status < 0)
+	}
 	else
 	{
 		xil_printf("[I] All 3/3 CPLD Checked In!\r\n");
 	}
 	xil_printf("\r\n=====================[I] Board Init Complete!=====================\r\n[I] Waiting for Command...\r\n");
 	/* receive and process Instructions */
 	if (iMainCom == 1)
 	{
 		print_app_header();
 		while (1) {
 			if (TcpFastTmrFlag) {
 				tcp_fasttmr();
 				TcpFastTmrFlag = 0;
 			}
 			if (TcpSlowTmrFlag) {
 				tcp_slowtmr();
 				TcpSlowTmrFlag = 0;
 			}
 			xemacif_input(netif);
 		}
 	}
 	else
 	{
 		while (1) 
 		{
-			xil_printf("[E] UART Receive ERROR!!! Check PrintOut Ahead\r\n");
+			int Status = -255;
 			Status = UART_RecvInstr(recvbuffer);
 			if (Status < 0)
 			{
 				xil_printf("[E] UART Receive ERROR!!! Check PrintOut Ahead\r\n");
 			}
 			else if (Status > 0)
 			{
 				Command_Parser(recvbuffer,Status);		//Here Status should equal to length
 			}
 		}
 	}
 	/* never reached */
@@ -85,4 +260,3 @@ int main()
 	return 0;
 }
@@ -1,86 +0,0 @@
 /******************************************************************************
 * Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 #include "xparameters.h"
 #include "xil_cache.h"
 #ifndef SDT
 #include "platform_config.h"
 #endif
 /*
 * Uncomment one of the following two lines, depending on the target,
 * if ps7/psu init source files are added in the source directory for
 * compiling example outside of SDK.
 */
 /*#include "ps7_init.h"*/
 /*#include "psu_init.h"*/
 #ifdef STDOUT_IS_16550
 #include "xuartns550_l.h"
 #define UART_BAUD 9600
 #endif
 void
 enable_caches()
 {
 #ifdef __PPC__
    Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
    Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
 #elif __MICROBLAZE__
 #ifdef XPAR_MICROBLAZE_USE_ICACHE
    Xil_ICacheEnable();
 #endif
 #ifdef XPAR_MICROBLAZE_USE_DCACHE
    Xil_DCacheEnable();
 #endif
 #endif
 }
 void
 disable_caches()
 {
 #ifdef __MICROBLAZE__
 #ifdef XPAR_MICROBLAZE_USE_DCACHE
    Xil_DCacheDisable();
 #endif
 #ifdef XPAR_MICROBLAZE_USE_ICACHE
    Xil_ICacheDisable();
 #endif
 #endif
 }
 void
 init_uart()
 {
 #ifdef STDOUT_IS_16550
    XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
    XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
 #endif
    /* Bootrom/BSP configures PS7/PSU UART to 115200 bps */
 }
 void
 init_platform()
 {
    /*
     * If you want to run this example outside of SDK,
     * uncomment one of the following two lines and also #include "ps7_init.h"
     * or #include "ps7_init.h" at the top, depending on the target.
     * Make sure that the ps7/psu_init.c and ps7/psu_init.h files are included
     * along with this example source files for compilation.
     */
    /* ps7_init();*/
    /* psu_init();*/
    enable_caches();
    init_uart();
 }
 void
 cleanup_platform()
 {
    disable_caches();
 }
@@ -1,16 +0,0 @@
 /******************************************************************************
 * Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 #ifndef __PLATFORM_H_
 #define __PLATFORM_H_
 #ifndef SDT
 #include "platform_config.h"
 #endif
 void init_platform();
 void cleanup_platform();
 #endif
@@ -6,4 +6,6 @@
 #define PLATFORM_EMAC_BASEADDR XPAR_XEMACPS_0_BASEADDR
 #define PLATFORM_ZYNQ
 #endif
@@ -0,0 +1,238 @@
 /*
 * Copyright (C) 2010 - 2022 Xilinx, Inc.
 * Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
 * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
 * OF SUCH DAMAGE.
 *
 */
 /*
 * platform_zynq.c
 *
 * Zynq platform specific functions.
 *
 * 02/29/2012: UART initialization is removed. Timer initializations are
 * removed. All unnecessary include files and hash defines are removed.
 * 03/01/2013: Timer initialization is added back. Support for SI #692601 is
 * added in the timer callback. The SI #692601 refers to the following issue.
 *
 * The EmacPs has a HW bug on the Rx path for heavy Rx traffic.
 * Under heavy Rx traffic because of the HW bug there are times when the Rx path
 * becomes unresponsive. The workaround for it is to check for the Rx path for
 * traffic (by reading the stats registers regularly). If the stats register
 * does not increment for sometime (proving no Rx traffic), the function resets
 * the Rx data path.
 *
 * </pre>
 */
 #ifndef SDT
 #ifdef __arm__
 #include "xparameters.h"
 #include "xparameters_ps.h"	/* defines XPAR values */
 #include "xil_cache.h"
 #include "xscugic.h"
 #include "lwip/tcp.h"
 #include "xil_printf.h"
 #include "platform_config.h"
 #include "netif/xadapter.h"
 #ifdef PLATFORM_ZYNQ
 #include "xscutimer.h"
 #include "xtime_l.h"
 #define INTC_DEVICE_ID		XPAR_SCUGIC_SINGLE_DEVICE_ID
 #define TIMER_DEVICE_ID		XPAR_SCUTIMER_DEVICE_ID
 #define INTC_BASE_ADDR		XPAR_SCUGIC_0_CPU_BASEADDR
 #define INTC_DIST_BASE_ADDR	XPAR_SCUGIC_0_DIST_BASEADDR
 #define TIMER_IRPT_INTR		XPAR_SCUTIMER_INTR
 #define RESET_RX_CNTR_LIMIT	400
 void tcp_fasttmr(void);
 void tcp_slowtmr(void);
 static XScuTimer TimerInstance;
 #ifndef USE_SOFTETH_ON_ZYNQ
 static int ResetRxCntr = 0;
 extern struct netif server_netif;
 #endif
 volatile int TcpFastTmrFlag = 0;
 volatile int TcpSlowTmrFlag = 0;
 #if LWIP_DHCP==1
 volatile int dhcp_timoutcntr = 24;
 void dhcp_fine_tmr();
 void dhcp_coarse_tmr();
 #endif
 void
 timer_callback(XScuTimer * TimerInstance)
 {
 	/* we need to call tcp_fasttmr & tcp_slowtmr at intervals specified
 	 * by lwIP. It is not important that the timing is absoluetly accurate.
 	 */
 	static int odd = 1;
 #if LWIP_DHCP==1
    static int dhcp_timer = 0;
 #endif
 	 TcpFastTmrFlag = 1;
 	odd = !odd;
 #ifndef USE_SOFTETH_ON_ZYNQ
 	ResetRxCntr++;
 #endif
 	if (odd) {
 #if LWIP_DHCP==1
 		dhcp_timer++;
 		dhcp_timoutcntr--;
 #endif
 		TcpSlowTmrFlag = 1;
 #if LWIP_DHCP==1
 		dhcp_fine_tmr();
 		if (dhcp_timer >= 120) {
 			dhcp_coarse_tmr();
 			dhcp_timer = 0;
 		}
 #endif
 	}
 	/* For providing an SW alternative for the SI #692601. Under heavy
 	 * Rx traffic if at some point the Rx path becomes unresponsive, the
 	 * following API call will ensures a SW reset of the Rx path. The
 	 * API xemacpsif_resetrx_on_no_rxdata is called every 100 milliseconds.
 	 * This ensures that if the above HW bug is hit, in the worst case,
 	 * the Rx path cannot become unresponsive for more than 100
 	 * milliseconds.
 	 */
 #ifndef USE_SOFTETH_ON_ZYNQ
 	if (ResetRxCntr >= RESET_RX_CNTR_LIMIT) {
 		xemacpsif_resetrx_on_no_rxdata(&server_netif);
 		ResetRxCntr = 0;
 	}
 #endif
 	XScuTimer_ClearInterruptStatus(TimerInstance);
 }
 void platform_setup_timer(void)
 {
 	int Status = XST_SUCCESS;
 	XScuTimer_Config *ConfigPtr;
 	int TimerLoadValue = 0;
 	ConfigPtr = XScuTimer_LookupConfig(TIMER_DEVICE_ID);
 	Status = XScuTimer_CfgInitialize(&TimerInstance, ConfigPtr,
 			ConfigPtr->BaseAddr);
 	if (Status != XST_SUCCESS) {
 		xil_printf("In %s: Scutimer Cfg initialization failed...\r\n",
 		__func__);
 		return;
 	}
 	Status = XScuTimer_SelfTest(&TimerInstance);
 	if (Status != XST_SUCCESS) {
 		xil_printf("In %s: Scutimer Self test failed...\r\n",
 		__func__);
 		return;
 	}
 	XScuTimer_EnableAutoReload(&TimerInstance);
 	/*
 	 * Set for 250 milli seconds timeout.
 	 */
 	TimerLoadValue = XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ / 8;
 	XScuTimer_LoadTimer(&TimerInstance, TimerLoadValue);
 	return;
 }
 void platform_setup_interrupts(void)
 {
 	Xil_ExceptionInit();
 	XScuGic_DeviceInitialize(INTC_DEVICE_ID);
 	/*
 	 * Connect the interrupt controller interrupt handler to the hardware
 	 * interrupt handling logic in the processor.
 	 */
 	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
 			(Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
 			(void *)INTC_DEVICE_ID);
 	/*
 	 * Connect the device driver handler that will be called when an
 	 * interrupt for the device occurs, the handler defined above performs
 	 * the specific interrupt processing for the device.
 	 */
 	XScuGic_RegisterHandler(INTC_BASE_ADDR, TIMER_IRPT_INTR,
 					(Xil_ExceptionHandler)timer_callback,
 					(void *)&TimerInstance);
 	/*
 	 * Enable the interrupt for scu timer.
 	 */
 	XScuGic_EnableIntr(INTC_DIST_BASE_ADDR, TIMER_IRPT_INTR);
 	return;
 }
 void platform_enable_interrupts()
 {
 	/*
 	 * Enable non-critical exceptions.
 	 */
 	Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
 	XScuTimer_EnableInterrupt(&TimerInstance);
 	XScuTimer_Start(&TimerInstance);
 	return;
 }
 void init_platform()
 {
 	platform_setup_timer();
 	platform_setup_interrupts();
 	return;
 }
 void cleanup_platform()
 {
 	Xil_ICacheDisable();
 	Xil_DCacheDisable();
 	return;
 }
 u64_t get_time_ms()
 {
 #define COUNTS_PER_MILLI_SECOND (COUNTS_PER_SECOND/1000)
 	XTime tCur = 0;
 	XTime_GetTime(&tCur);
 	return (tCur/COUNTS_PER_MILLI_SECOND);
 }
 #endif
 #endif
 #endif /* NOT SDT */
@@ -3,8 +3,6 @@
 #include <stdio.h>
 #include "xparameters.h"
 #include "platform.h"
 #include "platform.h"
 #include "xil_types.h"
 #include "xil_printf.h"
@@ -0,0 +1,2 @@
 eclipse.preferences.version=1
 encoding/<project>=UTF-8
@@ -0,0 +1,31 @@
 # Usage with Vitis IDE:
 # In Vitis IDE create a Single Application Debug launch configuration,
 # change the debug type to 'Attach to running target' and provide this 
 # tcl script in 'Execute Script' option.
 # Path of this script: C:\Users\testrong\Documents\Work\NewInstrCalBoard\2.FW\Zynq\Debug_FW\Vitis_Classic\NewInstrCalBoard_system\_ide\scripts\debugger_newinstrcalboard-default.tcl
 # 
 # 
 # Usage with xsct:
 # To debug using xsct, launch xsct and run below command
 # source C:\Users\testrong\Documents\Work\NewInstrCalBoard\2.FW\Zynq\Debug_FW\Vitis_Classic\NewInstrCalBoard_system\_ide\scripts\debugger_newinstrcalboard-default.tcl
 # 
 connect -url tcp:127.0.0.1:3121
 targets -set -nocase -filter {name =~"APU*"}
 rst -system
 after 3000
 targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS1 210249859440" && level==0 && jtag_device_ctx=="jsn-JTAG-HS1-210249859440-23732093-0"}
 fpga -file C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstrCalBoard/_ide/bitstream/system_wrapper.bit
 targets -set -nocase -filter {name =~"APU*"}
 loadhw -hw C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/export/NewInstCal_bsp/hw/system_wrapper.xsa -mem-ranges [list {0x40000000 0xbfffffff}] -regs
 configparams force-mem-access 1
 targets -set -nocase -filter {name =~"APU*"}
 targets -set -nocase -filter {name =~ "*A9*#0"}
 rst -processor
 dow C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/fsbl.elf
 set bp_53_28_fsbl_bp [bpadd -addr &FsblHandoffJtagExit]
 con -block -timeout 60
 bpremove $bp_53_28_fsbl_bp
 targets -set -nocase -filter {name =~ "*A9*#0"}
 dow C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstrCalBoard/Debug/NewInstrCalBoard.elf
 configparams force-mem-access 0
 bpadd -addr &main
Author	SHA1	Message	Date
yuysh	05f7cfa375	Add LWIP CMD Server Stack	2026-06-18 09:59:22 +08:00
yuysh	dcb0ef6159	Add lwip cmd server	2026-06-17 15:47:27 +08:00
Jeremy Shen	6991600083	Add CPLD_Con.c/h: Move CPLD Control Code to seperate file. Add CPLD Read/Write Command.	2026-06-01 10:50:36 +08:00
yuysh	a4abf50594	Fix u_rLoad shifting bug Change char to u8	2026-05-29 18:18:49 +08:00
yuysh	893467bdfe	Add CPLD DC Processing	2026-05-29 14:11:26 +08:00
yuysh	6f02f47407	Moved echo.c -> echo.c.bak Removed lwip support from BSP Added Command_Parser(), CPLD_exec() and CPLD_Write()	2026-05-28 18:39:13 +08:00
yuysh	54777d3fd9	Add Command Parser	2026-05-28 17:46:44 +08:00
yuysh	67faaf25d2	Remove unnecessary tracked files	2026-05-28 17:30:52 +08:00
yuysh	f4150f12fe	Update gitignore	2026-05-28 17:29:55 +08:00
yuysh	0424f932a1	Remove unnecessary tracked files	2026-05-28 17:28:39 +08:00
		`@@ -1,2 +0,0 @@`
			`2026-05-27T18:04:35.5315588000-Nothing to build in platform 'NewInstCal_bsp'`
`@@ -1 +1 @@`
	{"platformName":"NewInstCal_bsp","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"NewInstCal_bsp","platHandOff":"/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/system_wrapper.xsa","platIntHandOff":"<platformDir>/hw/system_wrapper.xsa","deviceType":"zynq","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","fsblExtraCompilerFlags":"-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"NewInstCal_bsp","systems":[{"systemName":"NewInstCal_bsp","systemDesc":"NewInstCal_bsp","sysIsBootAutoGen":"true","systemDispName":"NewInstCal_bsp","sysActiveDom":"standalone_domain","sysDefaultDom":"standalone_domain","domains":[{"domainName":"zynq_fsbl","domainDispName":"zynq_fsbl","domainDesc":"FSBL Application BSP - Auto Generated.","processors":"ps7_cortexa9_0","os":"standalone","sdxOs":"standalone","debugEnable":"","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.0","mssFile":"","md5Digest":"3243e54020e3af7b58d483729f3822a1","compatibleApp":"zynq_fsbl","domType":"bootDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilffs:5.1","xilrsa:1.7"],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_domain","domainDispName":"standalone on ps7_cortexa9_0","domainDesc":"standalone_domain","processors":"ps7_cortexa9_0","os":"standalone","sdxOs":"standalone","qemuArgs":"<platformDir>/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt","qemuData":"<platformDir>/resources/NewInstCal_bsp/standalone_domain/qemu","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.0","mssFile":"","md5Digest":"1422839dbecb6fdfcf744dce689d156a","compatibleApp":"","domType":"mssDomain","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip213:1.1"],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}	{"platformName":"NewInstCal_bsp","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"NewInstCal_bsp","platHandOff":"/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/system_wrapper.xsa","platIntHandOff":"<platformDir>/hw/system_wrapper.xsa","deviceType":"zynq","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","fsblExtraCompilerFlags":"-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"NewInstCal_bsp","systems":[{"systemName":"NewInstCal_bsp","systemDesc":"NewInstCal_bsp","sysIsBootAutoGen":"true","systemDispName":"NewInstCal_bsp","sysActiveDom":"standalone_domain","sysDefaultDom":"standalone_domain","domains":[{"domainName":"zynq_fsbl","domainDispName":"zynq_fsbl","domainDesc":"FSBL Application BSP - Auto Generated.","processors":"ps7_cortexa9_0","os":"standalone","sdxOs":"standalone","debugEnable":"","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.0","mssFile":"","md5Digest":"3243e54020e3af7b58d483729f3822a1","compatibleApp":"zynq_fsbl","domType":"bootDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilffs:5.1","xilrsa:1.7"],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_domain","domainDispName":"standalone on ps7_cortexa9_0","domainDesc":"standalone_domain","processors":"ps7_cortexa9_0","os":"standalone","sdxOs":"standalone","qemuArgs":"<platformDir>/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt","qemuData":"<platformDir>/resources/NewInstCal_bsp/standalone_domain/qemu","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.0","mssFile":"","md5Digest":"89622e7dd40f4ebcc78d10cff01d935b","compatibleApp":"","domType":"mssDomain","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip213:1.1"],"libOptions":{"lwip213":{"dhcp_does_arp_check":"true","lwip_dhcp":"true","libOptionNames":["dhcp_does_arp_check","lwip_dhcp"]},"libsContainingOptions":["lwip213"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}
		`@@ -0,0 +1,2 @@`
							`eclipse.preferences.version=1`
							`encoding/<project>=UTF-8`