yuysh/NewInstrCalBoard_Zynq
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15 Commits 2 Branches 1 Tag
a4abf50594a029f039f6a016ed4385d1819d5115
Commit Graph
13 Commits
Author SHA1 Message Date
yuysh a4abf50594 Fix u_rLoad shifting bug 
Change char to u8
 2026-05-29 18:18:49 +08:00
yuysh 893467bdfe Add CPLD DC Processing 2026-05-29 14:11:26 +08:00
yuysh 6f02f47407 Moved echo.c -> echo.c.bak 
Removed lwip support from BSP
Added Command_Parser(), CPLD_exec() and CPLD_Write()
 2026-05-28 18:39:13 +08:00
yuysh 54777d3fd9 Add Command Parser 2026-05-28 17:46:44 +08:00
yuysh 67faaf25d2 Remove unnecessary tracked files 2026-05-28 17:30:52 +08:00
yuysh 0424f932a1 Remove unnecessary tracked files 2026-05-28 17:28:39 +08:00
yuysh 50d16ab13d Merge branch 'master' of http://mkb.local:3000/yuysh/NewInstrCalBoard_Zynq 2026-05-28 17:04:05 +08:00
yuysh 480f680726 Add UART Debugging code 2026-05-28 17:02:45 +08:00
Jeremy Shen fd6f7b6332 Add general .gitignore for Xilinx Vivado/Vitis/SDK projects 
Universal patterns using wildcard naming conventions:
- *.cache/ - Vivado IP cache
- *.gen/*/ip/*/sim/ - Generated sim files
- *.ip_user_files/sim_scripts/, *.ip_user_files/bd/ - IP user artifacts
- *.sim/ - Simulation directories
- *.runs/synth_1/ and *.runs/impl_1/* - Run outputs (keep control scripts)
- *.sdk/.metadata/, *.sdk/.sdk/ - SDK workspace state
- *.sdk/RemoteSystemsTempFiles/, *.sdk/SDK.log, *.sdk/webtalk/ - SDK logs

Preserved: sources, .xpr, .project, .cproject, .xci, .xsa, .bit, .elf,
           BSP files, run control scripts

Removed from index: cache, .metadata, export, tempdsa, RemoteSystemsTempFiles
(515 build artifact files)

# Conflicts:
#	Vitis_Classic/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/boot/fsbl.elf
#	Vitis_Classic/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bsplib/lib/liblwip4.a
#	Vitis_Classic/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bsplib/lib/libxil.a
 2026-05-28 16:46:13 +08:00
yuysh d744efedf0 Remove network related code as they are not needed for this debug project 2026-05-27 18:21:20 +08:00
yuysh 393ca2948c Modify the EMIO_config(): 
- Add more debug info
- Add return value
 2026-05-27 18:20:48 +08:00
yuysh 9723d04512 Add FSBL debug and QSPI Bypass 2026-05-27 18:06:29 +08:00
Jeremy Shen ee3ede1152 Init Commit 2026-05-27 09:56:09 +00:00