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Fix u_rLoad shifting bug

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Change char to u8
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yuysh
2026-05-29 18:18:49 +08:00
parent 893467bdfe
commit a4abf50594
6 changed files with 147 additions and 46 deletions
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Vitis_Classic/.analytics
+27
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@@ -23,3 +23,30 @@ timestamp=[2026-05-29 14:06:00], mode=BUILD, duration=0:00:01.181, duration_ms=1
timestamp=[2026-05-29 14:06:07], mode=BUILD, duration=0:00:06.894, duration_ms=6894, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 14:10:02], mode=BUILD, duration=0:00:01.176, duration_ms=1176, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 14:10:09], mode=BUILD, duration=0:00:06.854, duration_ms=6854, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 14:46:57], mode=BUILD, duration=0:00:01.200, duration_ms=1200, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 14:47:05], mode=BUILD, duration=0:00:06.955, duration_ms=6955, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 14:47:54], mode=BUILD, duration=0:00:01.167, duration_ms=1167, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 14:48:01], mode=BUILD, duration=0:00:06.885, duration_ms=6885, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 14:55:33], mode=BUILD, duration=0:00:01.180, duration_ms=1180, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 14:55:40], mode=BUILD, duration=0:00:06.884, duration_ms=6884, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 14:56:16], mode=BUILD, duration=0:00:00.686, duration_ms=686, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 14:56:34], mode=BUILD, duration=0:00:01.831, duration_ms=1831, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 14:56:41], mode=BUILD, duration=0:00:06.912, duration_ms=6912, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 14:57:21], mode=BUILD, duration=0:00:01.197, duration_ms=1197, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 14:57:28], mode=BUILD, duration=0:00:06.962, duration_ms=6962, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 14:58:53], mode=BUILD, duration=0:00:01.234, duration_ms=1234, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 14:59:00], mode=BUILD, duration=0:00:06.964, duration_ms=6964, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 15:03:44], mode=BUILD, duration=0:00:01.200, duration_ms=1200, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 15:03:51], mode=BUILD, duration=0:00:06.941, duration_ms=6941, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 15:07:59], mode=BUILD, duration=0:00:01.164, duration_ms=1164, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 15:08:07], mode=BUILD, duration=0:00:06.857, duration_ms=6857, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 15:10:19], mode=BUILD, duration=0:00:01.205, duration_ms=1205, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 15:10:26], mode=BUILD, duration=0:00:07.003, duration_ms=7003, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 15:37:57], mode=BUILD, duration=0:00:01.221, duration_ms=1221, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 15:38:04], mode=BUILD, duration=0:00:07.028, duration_ms=7028, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 16:00:10], mode=BUILD, duration=0:00:01.163, duration_ms=1163, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 16:00:18], mode=BUILD, duration=0:00:07.016, duration_ms=7016, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 18:12:30], mode=BUILD, duration=0:00:01.308, duration_ms=1308, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 18:12:37], mode=BUILD, duration=0:00:07.017, duration_ms=7017, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 18:15:29], mode=BUILD, duration=0:00:01.296, duration_ms=1296, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
timestamp=[2026-05-29 18:15:37], mode=BUILD, duration=0:00:06.847, duration_ms=6847, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
Vitis_Classic/NewInstrCalBoard/.settings/org.eclipse.core.resources.prefs
+2
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@@ -0,0 +1,2 @@
eclipse.preferences.version=1
encoding/<project>=UTF-8
Vitis_Classic/NewInstrCalBoard/src/SPI_Driv.c
+1 -1
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@@ -59,7 +59,7 @@ void rst_CPLD(u32* device,u32 num_wire) //wire_num = cs sck sdi/o
* device -- CPLD
* Return : void
******************************************************************************/
void spi_write_onewire(char addr, char *data, char width, u32* device)
void spi_write_onewire(u8 addr, u8 *data, u8 width, u32* device)
{
char temp_addr = 0;
//u32 temp_data = 0;
Vitis_Classic/NewInstrCalBoard/src/SPI_Driv.h
+1 -1
View File
@@ -33,7 +33,7 @@ void rst_CPLD(u32* device,u32 num_wire);
void rst(char *d);
void spi_write_onewire(char addr, char *data, char width, u32* device);
void spi_write_onewire(u8 addr, u8 *data, u8 width, u32* device);
u32 spi_read_onewire(char addr,char width,u32* device,char* read_data);
void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3);
Vitis_Classic/NewInstrCalBoard/src/cal_meas.c
+114 -44
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@@ -7,7 +7,7 @@
#include "cal_meas.h"
#include "SPI_Driv.h"
char sw_config_data[3] = {0x00,0x00,0x00};
u8 sw_config_data[3] = {0x00,0x00,0x00};
int Command_Parser(u8* recvbuffer, u8 len)
{
@@ -39,7 +39,7 @@ int Command_Parser(u8* recvbuffer, u8 len)
xil_printf("[D] Matched Command Freq Cal\r\n");
if (len > Freq_CMD_LEN + 1) //Do NOT forget the command header
{
/* code */
xil_printf("[E] \r\n");
return XST_INVALID_PARAM;
}
@@ -82,63 +82,82 @@ int DC_Control(u8* idata)
u_rLoad = idata[5]; //1~18: Refer to SCH/Protocol
//Let's do some sanity check
//Slot
if ((u_slot > 4) || (u_slot == 0))
{
xil_printf("[E] Illege Slot Num check Command! (Slot:1-4)\r\n");
cmdValid = -1;
}
//Dev Sel
if ((u_m_fun > 2) || (u_m_fun == 0))
{
xil_printf("[E] Illege Dev Select check Command! (1:PMU/2:DPS)\r\n");
cmdValid = -2;
}
//Channel
if (u_m_fun == 1) //PMU
{
if ((u_ch_Num < 1) || (u_ch_Num > 256))
{
xil_printf("[E] Illege Channel! (PMU Ch:0x0001-0x0100)\r\n");
cmdValid = -2;
}
}
else
{
if ((u_ch_Num < 1) || (u_ch_Num > 64))
{
xil_printf("[E] Illege Channel! (PMU Ch:0x0001-0x0040)\r\n");
cmdValid = -3;
}
}
//V/I Sel
if ((u_vi_Sel > 2) || (u_vi_Sel == 0))
{
xil_printf("[E] Illege V/I Config check Command! (1:V/2:I)\r\n");
cmdValid = -3;
cmdValid = -5;
}
//RLoad Sel
if ((u_rLoad > 18) || (u_rLoad == 0))
{
xil_printf("[E] Illege RLoad Select check Command! (RLoad:1-18)\r\n");
cmdValid = -4;
xil_printf("[E] Illege RLoad Select check Command! (RLoad:0x01-0x12)\r\n");
cmdValid = -6;
}
if (cmdValid != 1)
{
/* code */
return XST_INVALID_PARAM;
}
//DEBUG Printout
xil_printf("[D] We Got:\r\n[-]\tSlot: #%d\r\n",u_slot);
if (u_m_fun == 1)
{
xil_printf("[-]\tDevice Select: PMU\r\n");
}
else
{
xil_printf("[-]\tDevice Select: DPS\r\n");
}
xil_printf("[-]\tChannel Select: #%d\r\n",u_ch_Num);
if (u_vi_Sel == 1)
{
xil_printf("[-]\tDMM Measure Select: Voltage\r\n");
}
else
{
xil_printf("[-]\tDMM Measure Select: Current\r\n");
}
xil_printf("[-]\tRLoad Select: #%d\r\n",u_rLoad);
//Sanity Check Done
//Let's format the CPLD Reg Data
//Note here as the CPLD_Write() will smartly set the R/W bit to 1'b1, so no need to handle that here, addr is addr
switch (u_rLoad)
{
case 1:
{
reg_addr = 0x06;
break;
}
case 2:
{
reg_addr = 0x07;
break;
}
case 3:
{
reg_addr = 0x08;
break;
}
case 4:
{
reg_addr = 0x09;
break;
}
default: //You should be here
{
xil_printf("[E] Error Reaching Invaild Slot CPLD Formatting, Check PS Code!\r\n");
return XST_FAILURE;
}
}
//As the structure of DC regs are the same, we can format the data uniformly
//Dev Sel
@@ -150,19 +169,66 @@ int DC_Control(u8* idata)
//V/I Sel
if (u_vi_Sel == 0x2)
{
/* code */
reg_data = reg_data | 0x400000; //1:I/0:V
}
//RLoad Sel
reg_data = reg_data | (((u32)u_rLoad)<<20);
reg_data = reg_data | (((u32)u_rLoad)<<17);
//Channel Sel
reg_data = reg_data | u_ch_Num;
reg_data = reg_data |((u32)(u_ch_Num)<<1) | 0x1; //0x1:Slot_EN
Status = CPLD_Write(reg_addr, reg_data);
//We should clear out other slot's enable flag to prevent error
Status = 0;
//Note here as the CPLD_Write() will smartly set the R/W bit to 1'b1, so no need to handle that here, addr is addr
switch (u_slot)
{
case 1:
{
Status = Status + CPLD_Write(0x07, 0x0);
Status = Status + CPLD_Write(0x08, 0x0);
Status = Status + CPLD_Write(0x09, 0x0);
reg_addr = 0x06;
Status = Status + CPLD_Write(reg_addr, reg_data);
break;
}
case 2:
{
Status = Status + CPLD_Write(0x06, 0x0);
Status = Status + CPLD_Write(0x08, 0x0);
Status = Status + CPLD_Write(0x09, 0x0);
reg_addr = 0x07;
Status = Status + CPLD_Write(reg_addr, reg_data);
break;
}
case 3:
{
Status = Status + CPLD_Write(0x06, 0x0);
Status = Status + CPLD_Write(0x07, 0x0);
Status = Status + CPLD_Write(0x09, 0x0);
reg_addr = 0x08;
Status = Status + CPLD_Write(reg_addr, reg_data);
break;
}
case 4:
{
Status = Status + CPLD_Write(0x06, 0x0);
Status = Status + CPLD_Write(0x07, 0x0);
Status = Status + CPLD_Write(0x08, 0x0);
reg_addr = 0x09;
Status = Status + CPLD_Write(reg_addr, reg_data);
break;
}
default: //You should NOT be here
{
xil_printf("[E] Error Reaching Invaild Slot CPLD Formatting, Check PS Code!\r\n");
return XST_FAILURE;
}
}
if (Status != XST_SUCCESS)
{
/* code */
xil_printf("[E] Error Writing CPLD Reg! Check Log ABOVE!\r\n");
return XST_FAILURE;
}
@@ -191,16 +257,20 @@ int DC_Control(u8* idata)
int CPLD_Write(u8 addr,u32 data)
{
u16 reg_addr = addr | 0x80; //Write bit set to 1'b1
u8 reg_data[dat_width] = {0};
//Data Sanity Check
if ((data >> 24) > 0)
{
/* code */
xil_printf("[E] CPLD data length should within 24 bits!\r\n");
return XST_INVALID_PARAM;
}
spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U1);
spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U2);
spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U3);
reg_data[0] = (u8)(data >> 16);
reg_data[1] = (u8)(((data)&0xff00)>>8);
reg_data[2] = (u8)data;
spi_write_onewire(reg_addr, reg_data, dat_width, CPLD_U1);
spi_write_onewire(reg_addr, reg_data, dat_width, CPLD_U2);
spi_write_onewire(reg_addr, reg_data, dat_width, CPLD_U3);
return XST_SUCCESS;
}
Vitis_Classic/NewInstrCalBoard_system/.settings/org.eclipse.core.resources.prefs
+2
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@@ -0,0 +1,2 @@
eclipse.preferences.version=1
encoding/<project>=UTF-8