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Jeremy Shen
2026-05-27 09:56:09 +00:00
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Vitis_Classic/NewInstrCalBoard/.cproject
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="xilinx.gnu.armv7.exe.debug.500963658">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.armv7.exe.debug.500963658" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<externalSettings/>
<extensions>
<extension id="com.xilinx.sdk.managedbuilder.XELF.arm.a53.x32" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="xilinx.gnu.armv7.exe.debug.500963658" name="Debug" parent="xilinx.gnu.armv7.exe.debug" prebuildStep="a9-linaro-pre-build-step">
<folderInfo id="xilinx.gnu.armv7.exe.debug.500963658." name="/" resourcePath="">
<toolChain id="xilinx.gnu.armv7.exe.debug.toolchain.1129454916" name="Vitis ARM v7 GNU Toolchain" superClass="xilinx.gnu.armv7.exe.debug.toolchain">
<targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm.a53.x32" id="xilinx.armv7.target.gnu.base.debug.458105419" isAbstract="false" name="Debug Platform" superClass="xilinx.armv7.target.gnu.base.debug"/>
<builder buildPath="${workspace_loc:/NewInstrCalBoard}/Debug" enableAutoBuild="true" id="xilinx.gnu.armv7.toolchain.builder.debug.206837781" managedBuildOn="true" name="GNU make.Debug" superClass="xilinx.gnu.armv7.toolchain.builder.debug"/>
<tool id="xilinx.gnu.armv7.c.toolchain.assembler.debug.692738950" name="ARM v7 gcc assembler" superClass="xilinx.gnu.armv7.c.toolchain.assembler.debug">
<inputType id="xilinx.gnu.assembler.input.1325849065" superClass="xilinx.gnu.assembler.input"/>
</tool>
<tool id="xilinx.gnu.armv7.c.toolchain.compiler.debug.202982000" name="ARM v7 gcc compiler" superClass="xilinx.gnu.armv7.c.toolchain.compiler.debug">
<option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.123403256" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.option.debugging.level.224133858" superClass="xilinx.gnu.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.max" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.1038675777" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=NewInstrCalBoard,fileType=bspInclude}"/>
</option>
<option id="xilinx.gnu.compiler.misc.other.835147797" superClass="xilinx.gnu.compiler.misc.other" value="-c -fmessage-length=0 -MT&quot;$@&quot; -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard" valueType="string"/>
<option id="xilinx.gnu.compiler.inferred.swplatform.flags.661365681" superClass="xilinx.gnu.compiler.inferred.swplatform.flags" value=" " valueType="string"/>
<inputType id="xilinx.gnu.armv7.c.compiler.input.1938869707" name="C source files" superClass="xilinx.gnu.armv7.c.compiler.input"/>
</tool>
<tool id="xilinx.gnu.armv7.cxx.toolchain.compiler.debug.25557254" name="ARM v7 g++ compiler" superClass="xilinx.gnu.armv7.cxx.toolchain.compiler.debug">
<option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.824585981" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.option.debugging.level.1828097787" superClass="xilinx.gnu.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.max" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.719144333" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=NewInstrCalBoard,fileType=bspInclude}"/>
</option>
<option id="xilinx.gnu.compiler.inferred.swplatform.flags.2059724481" superClass="xilinx.gnu.compiler.inferred.swplatform.flags" value=" " valueType="string"/>
</tool>
<tool id="xilinx.gnu.armv7.toolchain.archiver.1534027778" name="ARM v7 archiver" superClass="xilinx.gnu.armv7.toolchain.archiver"/>
<tool id="xilinx.gnu.armv7.c.toolchain.linker.debug.1688017382" name="ARM v7 gcc linker" superClass="xilinx.gnu.armv7.c.toolchain.linker.debug">
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.489427649" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=NewInstrCalBoard,fileType=bspLib}"/>
</option>
<option id="xilinx.gnu.linker.inferred.swplatform.flags.1086872743" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-llwip4,-lgcc,-lc,--end-group"/>
</option>
<option id="xilinx.gnu.c.linker.option.lscript.186234746" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
<option id="xilinx.gnu.c.link.option.ldflags.424769846" superClass="xilinx.gnu.c.link.option.ldflags" value=" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec" valueType="string"/>
<inputType id="xilinx.gnu.linker.input.366135171" superClass="xilinx.gnu.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
<inputType id="xilinx.gnu.linker.input.lscript.643832580" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
</tool>
<tool id="xilinx.gnu.armv7.cxx.toolchain.linker.debug.226193513" name="ARM v7 g++ linker" superClass="xilinx.gnu.armv7.cxx.toolchain.linker.debug">
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.294868340" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=NewInstrCalBoard,fileType=bspLib}"/>
</option>
<option id="xilinx.gnu.linker.inferred.swplatform.flags.589531348" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-llwip4,-lgcc,-lc,--end-group"/>
</option>
<option id="xilinx.gnu.c.linker.option.lscript.479845834" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
</tool>
<tool id="xilinx.gnu.armv7.size.debug.1181417531" name="ARM v7 Print Size" superClass="xilinx.gnu.armv7.size.debug"/>
</toolChain>
</folderInfo>
<sourceEntries>
<entry excluding="_ide" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
<cconfiguration id="xilinx.gnu.armv7.exe.release.835983251">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.armv7.exe.release.835983251" moduleId="org.eclipse.cdt.core.settings" name="Release">
<externalSettings/>
<extensions>
<extension id="com.xilinx.sdk.managedbuilder.XELF.arm.a53.x32" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="xilinx.gnu.armv7.exe.release.835983251" name="Release" parent="xilinx.gnu.armv7.exe.release" prebuildStep="a9-linaro-pre-build-step">
<folderInfo id="xilinx.gnu.armv7.exe.release.835983251." name="/" resourcePath="">
<toolChain id="xilinx.gnu.armv7.exe.release.toolchain.1475336559" name="Vitis ARM v7 GNU Toolchain" superClass="xilinx.gnu.armv7.exe.release.toolchain">
<targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm.a53.x32" id="xilinx.armv7.target.gnu.base.release.852156263" isAbstract="false" name="Release Platform" superClass="xilinx.armv7.target.gnu.base.release"/>
<builder buildPath="${workspace_loc:/NewInstrCalBoard}/Release" enableAutoBuild="true" id="xilinx.gnu.armv7.toolchain.builder.release.954626107" managedBuildOn="true" name="GNU make.Release" superClass="xilinx.gnu.armv7.toolchain.builder.release"/>
<tool id="xilinx.gnu.armv7.c.toolchain.assembler.release.894863828" name="ARM v7 gcc assembler" superClass="xilinx.gnu.armv7.c.toolchain.assembler.release">
<inputType id="xilinx.gnu.assembler.input.528326859" superClass="xilinx.gnu.assembler.input"/>
</tool>
<tool id="xilinx.gnu.armv7.c.toolchain.compiler.release.268074158" name="ARM v7 gcc compiler" superClass="xilinx.gnu.armv7.c.toolchain.compiler.release">
<option defaultValue="gnu.c.optimization.level.more" id="xilinx.gnu.compiler.option.optimization.level.1956701094" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.option.debugging.level.99099777" superClass="xilinx.gnu.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.none" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.445358035" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=NewInstrCalBoard,fileType=bspInclude}"/>
</option>
<option id="xilinx.gnu.compiler.misc.other.1338975813" superClass="xilinx.gnu.compiler.misc.other" value="-c -fmessage-length=0 -MT&quot;$@&quot; -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard" valueType="string"/>
<option id="xilinx.gnu.compiler.inferred.swplatform.flags.1248116077" superClass="xilinx.gnu.compiler.inferred.swplatform.flags" value=" " valueType="string"/>
<inputType id="xilinx.gnu.armv7.c.compiler.input.1519007223" name="C source files" superClass="xilinx.gnu.armv7.c.compiler.input"/>
</tool>
<tool id="xilinx.gnu.armv7.cxx.toolchain.compiler.release.1778188442" name="ARM v7 g++ compiler" superClass="xilinx.gnu.armv7.cxx.toolchain.compiler.release">
<option defaultValue="gnu.c.optimization.level.more" id="xilinx.gnu.compiler.option.optimization.level.887519747" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.option.debugging.level.634973419" superClass="xilinx.gnu.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.none" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.455641985" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=NewInstrCalBoard,fileType=bspInclude}"/>
</option>
<option id="xilinx.gnu.compiler.inferred.swplatform.flags.175086072" superClass="xilinx.gnu.compiler.inferred.swplatform.flags" value=" " valueType="string"/>
</tool>
<tool id="xilinx.gnu.armv7.toolchain.archiver.827288920" name="ARM v7 archiver" superClass="xilinx.gnu.armv7.toolchain.archiver"/>
<tool id="xilinx.gnu.armv7.c.toolchain.linker.release.1102407467" name="ARM v7 gcc linker" superClass="xilinx.gnu.armv7.c.toolchain.linker.release">
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.406568699" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=NewInstrCalBoard,fileType=bspLib}"/>
</option>
<option id="xilinx.gnu.linker.inferred.swplatform.flags.975340720" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-llwip4,-lgcc,-lc,--end-group"/>
</option>
<option id="xilinx.gnu.c.linker.option.lscript.1433039276" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
<option id="xilinx.gnu.c.link.option.ldflags.1499900191" superClass="xilinx.gnu.c.link.option.ldflags" value=" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec" valueType="string"/>
<inputType id="xilinx.gnu.linker.input.1142748896" superClass="xilinx.gnu.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
<inputType id="xilinx.gnu.linker.input.lscript.280471685" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
</tool>
<tool id="xilinx.gnu.armv7.cxx.toolchain.linker.release.1715649489" name="ARM v7 g++ linker" superClass="xilinx.gnu.armv7.cxx.toolchain.linker.release">
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.1307461918" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=NewInstrCalBoard,fileType=bspLib}"/>
</option>
<option id="xilinx.gnu.linker.inferred.swplatform.flags.1267787228" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-llwip4,-lgcc,-lc,--end-group"/>
</option>
<option id="xilinx.gnu.c.linker.option.lscript.311805804" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
</tool>
<tool id="xilinx.gnu.armv7.size.release.312718915" name="ARM v7 Print Size" superClass="xilinx.gnu.armv7.size.release"/>
</toolChain>
</folderInfo>
<sourceEntries>
<entry excluding="_ide" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="NewInstrCalBoard.xilinx.gnu.armv7.exe.1322943714" name="Vitis ARM v7 Executable" projectType="xilinx.gnu.armv7.exe"/>
</storageModule>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
<scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.debug.500963658;xilinx.gnu.armv7.exe.debug.500963658.;xilinx.gnu.armv7.c.toolchain.compiler.debug.202982000;xilinx.gnu.armv7.c.compiler.input.1938869707">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.release.835983251;xilinx.gnu.armv7.exe.release.835983251.;xilinx.gnu.armv7.c.toolchain.compiler.release.268074158;xilinx.gnu.armv7.c.compiler.input.1519007223">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.debug.500963658;xilinx.gnu.armv7.exe.debug.500963658.">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.release.835983251;xilinx.gnu.armv7.exe.release.835983251.">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="refreshScope"/>
</cproject>
Vitis_Classic/NewInstrCalBoard/.gitignore
+2
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/Debug/
/Release/
Vitis_Classic/NewInstrCalBoard/.project
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>NewInstrCalBoard</name>
<comment>Created by Vitis v2023.2</comment>
<projects>
<project>NewInstCal_bsp</project>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.xilinx.sdx.sdk.core.SdkProjectNature</nature>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
</projectDescription>
Vitis_Classic/NewInstrCalBoard/NewInstrCalBoard.prj
+11
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@@ -0,0 +1,11 @@
<?xml version="1.0" encoding="ASCII"?>
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="NewInstrCalBoard" location="." platform="../NewInstCal_bsp/export/NewInstCal_bsp/NewInstCal_bsp.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="NewInstrCalBoard_system" sysConfig="NewInstCal_bsp" runtime="C/C++" cpu="standalone_domain" cpuInstance="ps7_cortexa9_0" os="standalone" mssSignature="85660551333151807e7dda7acb0fe4a4">
<configuration name="Debug" id="xilinx.gnu.armv7.exe.debug.500963658">
<configBuildOptions xsi:type="sdkproject:SdkOptions"/>
<lastBuildOptions xsi:type="sdkproject:SdkOptions"/>
</configuration>
<configuration name="Release" id="xilinx.gnu.armv7.exe.release.835983251" dirty="true">
<configBuildOptions xsi:type="sdkproject:SdkOptions"/>
</configuration>
<template appTemplateName="hello_world"/>
</sdkproject:SdkProject>
Vitis_Classic/NewInstrCalBoard/_ide/bitstream/system_wrapper.bit
BIN
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Vitis_Classic/NewInstrCalBoard/_ide/hwspec.checksum
+1
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@@ -0,0 +1 @@
1536657578
Vitis_Classic/NewInstrCalBoard/_ide/psinit/ps7_init.tcl
+745
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proc ps7_pll_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000701
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00200500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x0007FFFF 0x00001082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00000003 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x0003F03F 0x0003C008
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x00010000 0x00000000
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x00000200 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
mask_write 0XF8006120 0x7FFFFFCF 0x40000001
mask_write 0XF8006124 0x7FFFFFCF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000703FF 0x000003FF
mask_write 0XF800620C 0x000703FF 0x000003FF
mask_write 0XF8006210 0x000703FF 0x000003FF
mask_write 0XF8006214 0x000703FF 0x000003FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF5 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000260
mask_write 0XF8000B70 0x00000001 0x00000001
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002F002E
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x000003FF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_3_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
proc ps7_pll_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000701
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00200500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000260
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002F002E
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_2_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
proc ps7_pll_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000701
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00200500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x000073FF 0x00000260
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002F002E
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_1_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
set PCW_SILICON_VER_1_0 "0x0"
set PCW_SILICON_VER_2_0 "0x1"
set PCW_SILICON_VER_3_0 "0x2"
set APU_FREQ 666666666
proc mask_poll { addr mask } {
set count 1
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
while { $maskedval == 0 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
set count [ expr { $count + 1 } ]
if { $count == 100000000 } {
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
break
}
}
}
proc mask_delay { addr val } {
set delay [ get_number_of_cycles_for_delay $val ]
perf_reset_and_start_timer
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
while { $maskedval == 1 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
}
perf_reset_clock
}
proc ps_version { } {
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
return $mask_sil_ver;
}
proc ps7_post_config {} {
set saved_mode [configparams force-mem-accesses]
configparams force-mem-accesses 1
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_post_config_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_post_config_2_0
} else {
ps7_post_config_3_0
}
configparams force-mem-accesses $saved_mode
}
proc ps7_debug {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_debug_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_debug_2_0
} else {
ps7_debug_3_0
}
}
proc ps7_init {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_mio_init_data_1_0
ps7_pll_init_data_1_0
ps7_clock_init_data_1_0
ps7_ddr_init_data_1_0
ps7_peripherals_init_data_1_0
#puts "PCW Silicon Version : 1.0"
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_mio_init_data_2_0
ps7_pll_init_data_2_0
ps7_clock_init_data_2_0
ps7_ddr_init_data_2_0
ps7_peripherals_init_data_2_0
#puts "PCW Silicon Version : 2.0"
} else {
ps7_mio_init_data_3_0
ps7_pll_init_data_3_0
ps7_clock_init_data_3_0
ps7_ddr_init_data_3_0
ps7_peripherals_init_data_3_0
#puts "PCW Silicon Version : 3.0"
}
}
# For delay calculation using global timer
# start timer
proc perf_start_clock { } {
#writing SCU_GLOBAL_TIMER_CONTROL register
mask_write 0xF8F00208 0x00000109 0x00000009
}
# stop timer and reset timer count regs
proc perf_reset_clock { } {
perf_disable_clock
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
}
# Compute mask for given delay in miliseconds
proc get_number_of_cycles_for_delay { delay } {
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
variable APU_FREQ
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
}
# stop timer
proc perf_disable_clock {} {
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
}
proc perf_reset_and_start_timer {} {
perf_reset_clock
perf_start_clock
}
Vitis_Classic/NewInstrCalBoard/src/GPIO_Driv.c
+113
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@@ -0,0 +1,113 @@
/*
* GPIO_Driv.c
*
* Created on: 2021年5月7日
* Author: Administrator
*/
#include "GPIO_Driv.h"
#include "xil_printf.h"
#include "xparameters.h"
XGpioPs psGpioInstancePtr; //端口
XGpioPs_Config* GpioConfigPtr; //设备ID
//sck,cs,sdi,sdo,rst
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
void EMIO_config(void)
{
int xStatus;
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_XGPIOPS_0_BASEADDR);
if(GpioConfigPtr == NULL)
{
xil_printf("PS GPIO LookupConfig failed\n\r");
return;
}
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
if(XST_SUCCESS != xStatus)
print(" PS GPIO INIT FAILED \n\r");
/*-------------------------------------CPLD_U1------------------------------------*/
//--设置EMIO方向
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---cs
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---sdi
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 0);//57---sdo
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 1);//58---rst_n
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
//使能EMIO输出 1=output 0=input
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---cs
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---sdi
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);//57---sdo
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);//58---rst_n
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//59
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//60
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//61
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//62
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//63
/*-------------------------------------CPLD_U2------------------------------------*/
//--设置EMIO方向
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---cs
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---sdi
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//68---sdo
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//69---rst_n
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//70
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//71
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//72
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//73
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//74
//使能EMIO输出 1=output 0=input
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---cs
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---sdi
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);//68---sdo
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);//69---rst_n
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);//70
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);//71
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);//72
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);//73
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);//74
/*-------------------------------------CPLD_U3------------------------------------*/
//--设置EMIO方向
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//76---sck
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//77---cs
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//78---sdi
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 0);//79---sdo
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 1);//80---rst_n
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//81
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//82
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//83
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//84
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//85
//使能EMIO输出 1=output 0=input
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//76---sck
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//77---cs
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//78---sdi
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 0);//79---sdo
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 1);//80---rst_n
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);//81
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);//82
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);//83
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);//84
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);//85
}
Vitis_Classic/NewInstrCalBoard/src/GPIO_Driv.h
+25
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/*
* GPIO_Driv.h
*
* Created on: 2021年4月2日
* Author: dell
*/
#ifndef SRC_GPIO_DRIV_H_
#define SRC_GPIO_DRIV_H_
#include "stdio.h"
#include "xgpiops.h"
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
extern u32 CPLD_U1[11];
extern u32 CPLD_U2[11];
extern u32 CPLD_U3[11];
void EMIO_config(void);
#endif /* SRC_GPIO_DRIV_H_ */
Vitis_Classic/NewInstrCalBoard/src/SPI_Driv.c
+558
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@@ -0,0 +1,558 @@
/*
* SPI_Driv.c
*
* Created on: 2021年4月2日
* Author: dell
*/
#include "SPI_Driv.h"
extern XGpioPs psGpioInstancePtr; //端口
extern XGpioPs_Config* GpioConfigPtr; //设备ID
extern u32 K7_U0[16];
extern u32 molex_4_bank_3[4];
extern u32 cs_en_bank_3[4];
/******************************************************************************
* Function : void interface_initial(u32* device,u32 num_wire)
* Description : interface initial
* Parameter : device -- CPLD
* num_wire -- 复位线编号
* Return : void
******************************************************************************/
void interface_initial(u32* device) //wire_num = cs sck sdi/o
{
u32 sck = *(device+0);
u32 cs = *(device+1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
}
/******************************************************************************
* Function : void rst_CPLD(u32* device,u32 num_wire)
* Description : CPLD reset
* Parameter : device -- CPLD
* num_wire -- 复位线编号
* Return : void
******************************************************************************/
void rst_CPLD(u32* device,u32 num_wire) //wire_num = cs sck sdi/o
{
u32 rst_n = *(device+num_wire);
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
usleep(2);
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
}
/******************************************************************************
* Function : void spi_write_onewire(char addr, u32 data, char width, u32* device)
* Description : spi onewire write
* Parameter : addr -- 地址
* data -- 数据
* width -- 数据长度
* device -- CPLD
* Return : void
******************************************************************************/
void spi_write_onewire(char addr, char *data, char width, u32* device)
{
char temp_addr = 0;
//u32 temp_data = 0;
u32 temp_data = 0;
char i = 0,j=0;
u32 sck = *(device+0);
u32 cs= *(device+1);
u32 sdi= *(device+2);
temp_addr = addr;
///temp_data = data;
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
//XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); // w/r标志位 1=w 0=r
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
for(i = 0; i < 8; i++) // 8bit地址
{
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
if(temp_addr&0x80)
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据 数据从中间变量到通信线上
else
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
temp_addr = temp_addr<<1; //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
}
for(j=0;j<width;j++)
{
temp_data = *(data+j);
for(i = 0; i < 8; i++) //nbit数据
{
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
if(temp_data&0x80) //注意数据位nbit，要从[n-1]取位
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1);
else
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
temp_data <<= 1;
}
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
}
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs , 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
}
/******************************************************************************
* Function : u32 spi_read_onewire(char addr, char width, u32* device)
* Description : spi onewire read
* Parameter : addr -- 地址
* data -- 数据
* width -- 数据长度
* device -- CPLD
* Return : void
******************************************************************************/
u32 spi_read_onewire(char addr, char width, u32* device,char* read_data)
{
char temp_addr=0;
u32 temp_data=0;
char i=0,j=0;
u32 sck = *(device+0);
u32 cs= *(device+1);
u32 sdi= *(device+2);
u32 sdo= *(device+3);
temp_addr = addr;
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
//XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0); // w/r标志位 1=w 0=r
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
for(i = 0; i < 8; i++) // 8bit地址
{
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
if(temp_addr&0x80)
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据 数据从中间变量到通信线上
else
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
temp_addr = temp_addr<<1; //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
}
for(j=0; j<width; j++)
{
for(i = 0; i < 8; i++) //nbit数据
{
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
temp_data = temp_data << 1; //sck低电平准备数据 准备好数位，此时的数据相当于从右边的FPGA移进MCU(先准备好中间变量)
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
if(XGpioPs_ReadPin(&psGpioInstancePtr,sdo)) //sck高电平接收数据 数据匹配到准备好的数位，等待一起传递到MCU
temp_data = temp_data| 0x00000001;
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
}
}
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
read_data[0] = (u8)(temp_data>>16);
read_data[1] = (u8)(temp_data>>8);
read_data[0] = (u8)(temp_data);
return temp_data;
}
/******************************************************************************
* Function : void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
* Description : forwire write to reg
* Parameter : txdata--数据
* sdi0,sdi1,sdi2,sdi3--IO
* Return : void
******************************************************************************/
void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
{
switch(txdata & 0x0F)
{
case 0x00:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x01:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x02:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x03:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x04:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x05:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x06:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x07:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x08:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
case 0x09:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
case 0x0A:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
case 0x0B:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
case 0x0C:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
case 0x0D:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
case 0x0E:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
case 0x0F:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
}
}
/******************************************************************************
* Function : void spi_write_fourwire(char addr, u16 data, u32* device)
* Description : spi fourwire write
* Parameter : addr -- 地址
* data -- 数据
* width -- 数据长度
* device -- CPLD
* Return : void
******************************************************************************/
void spi_write_fourwire(char addr, u16 data, u32* device)
{
u8 temp_addr = 0;
u16 temp_data = 0;
u8 split_addr[2] = {0}; //将8bit地址拆分，分别给4线传输，
u8 split_data[4] = {0}; //16bit数据拆成4个4bit
u8 i;
u32 sck = *(device+0);
u32 cs = *(device+1);
u32 sdi0 = *(device+2);
u32 sdi1 = *(device+3);
u32 sdi2 = *(device+4);
u32 sdi3 = *(device+5);
temp_addr = addr;
temp_data = data;
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
fourwire_write(0x01,sdi0,sdi1,sdi2,sdi3); // w/r标志位 1=w 0=r
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
for(i = 0; i < 2;i++) // 8bit地址 四根线分两次传输
{
split_addr[i] = (temp_addr>>(4*(1-i)))&0x0F; //sck高电平准备数据 数据从MCU到中间变量上
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
fourwire_write(split_addr[i],sdi0,sdi1,sdi2,sdi3); //sck低电平传输数据 数据从中间变量到通信线上
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
}
for(i = 0; i < 4;i++) //16bit数据 4根线分四次传输
{
split_data[i] = (temp_data>>(4*(3-i)))&0x0F;
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
fourwire_write(split_data[i],sdi0,sdi1,sdi2,sdi3);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
}
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
fourwire_write(0x00,sdi0,sdi1,sdi2,sdi3);
//usleep(20);
}
/******************************************************************************
* Function : u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
* Description : forwire read from reg
* Parameter : sdo0,sdo1,sdo2,sdo3--IO
* Return : rxdata--数据
******************************************************************************/
u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
{
u32 GPIO_PIN[4];
u16 rdata[4];
u16 rxdata = 0;
GPIO_PIN[0] = sdo0;
GPIO_PIN[1] = sdo1;
GPIO_PIN[2] = sdo2;
GPIO_PIN[3] = sdo3;
for(u8 i = 0; i < 4 ; i++)
{
rdata[i] = XGpioPs_ReadPin(&psGpioInstancePtr,GPIO_PIN[i]);
//xil_printf("rdata[i] = %x\r\n",rdata[i]);
rxdata = ((rdata[i])<<i) + rxdata ;
}
return rxdata;
}
/******************************************************************************
* Function : void spi_read_fourwire(char addr, u16* rxdata, u32* device)
* Description : spi fourwire read
* Parameter : addr -- 地址
* rxdata -- 数据
* device -- CPLD
* Return : void
******************************************************************************/
void spi_read_fourwire(char addr, u16* rxdata, u32* device) //接收数据使用指针传递，方便接收多个
{
u8 temp_addr = 0;
u16 temp_data = 0;
u8 split_addr[2] = {0}; //将8bit地址拆分，分别给4线传输，
u16 split_data[4] = {0}; //16bit数据拆成4个4bit
u8 i = 0;
u32 sck = *(device+0);
u32 cs = *(device+1);
u32 sdio0 = *(device+2);
u32 sdio1 = *(device+3);
u32 sdio2 = *(device+4);
u32 sdio3 = *(device+5);
temp_addr = addr;
split_addr[0] = (temp_addr >> 4)&0x0F;
split_addr[1] = (temp_addr)&0x0F;
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3); // w/r标志位 1=w 0=r
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
for(i = 0; i < 2; i++) // 8bit地址 四根线分两次传输
{
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
fourwire_write(split_addr[i],sdio0,sdio1,sdio2,sdio3); //sck低电平传输数据 数据从中间变量到通信线上
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
}
for(i = 0; i < 4; i++)
{
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),0); //input
}
for(i = 0; i < 4; i++) //16bit数据 4根线分四次接收
{
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
split_data[i] = fourwire_read(sdio0,sdio1,sdio2,sdio3); //sck低电平准备数据 数据从通信线到中间变量上
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
temp_data = temp_data<<4;
temp_data = temp_data + split_data[i];
//temp_data = (split_data[i]<<(4*(3-i))) + temp_data; //sck高电平接收数据 数据从中间变量到MCU上
// xil_printf("split_data[i],temp_data = %x,%x\r\n",split_data[i],temp_data);
}
for(i = 0; i < 4; i++)
{
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),1); //output
}
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3);
*rxdata = temp_data;
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);//add 2 lines
//usleep(20);
}
/******************************************************************************
* Function : void GPIO_dir_set(u32* device,char dir)
* Description : change GPIO direction
* Parameter : device -- CPLD
* dir -- GPIO_OUT/GPIO_IN
* Return : void
******************************************************************************/
void GPIO_dir_set_16(u32* device,char dir)
{
u32 sdio[16] = {0};
u8 i;
for(i = 0; i < 16;i++)
{
sdio[i] = *(device+i);
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, sdio[i],1);
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir);
}
}
void GPIO_dir_set_cs_enable(u32* device,u8 dir)
{
u32 sdio[4] = {0};
u8 i;
u8 dir_temp = 0;
for(i = 0; i < 4;i++)
{
sdio[i] = *(device+i);
dir_temp = (((dir >> (3-i))) & 0x01);
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir_temp);
}
}
void rst(char *d)
{
XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
XGpioPs_WritePin(&psGpioInstancePtr, *d, 1);
usleep(20);
XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
}
void func_test(void)
{
XGpioPs_Write(&psGpioInstancePtr, 0x03, 0x12345678);
}
Vitis_Classic/NewInstrCalBoard/src/SPI_Driv.h
+47
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@@ -0,0 +1,47 @@
/*
* SPI_Driv.h
*
* Created on: 2021Äê4ÔÂ2ÈÕ
* Author: dell
*/
#ifndef SRC_SPI_DRIV_H_
#define SRC_SPI_DRIV_H_
#include "sleep.h"
#include "stdio.h"
#include "xgpiops.h"
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
#define wr_flag 1
#define rd_flag 0
#define GPIO_OUT 1
#define GPIO_IN 0
#define NUM_SCK_CMD 4
#define NUM_SCK_ADDR 8
#define NUM_SCK_LENGTH 4
#define NUM_SCK_ENABLE 8
#define NUM_SCK_BYTE 2
void interface_initial(u32* device);
void rst_CPLD(u32* device,u32 num_wire);
void rst(char *d);
void spi_write_onewire(char addr, char *data, char width, u32* device);
u32 spi_read_onewire(char addr,char width,u32* device,char* read_data);
void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3);
u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3);
void spi_write_fourwire(char addr,u16 data,u32* device);
void spi_read_fourwire(char addr,u16* rxdata,u32* device);
void GPIO_dir_set_16(u32* device,char dir);
void GPIO_dir_set_cs_enable(u32* device,u8 dir);
#endif /* SRC_SPI_DRIV_H_ */
Vitis_Classic/NewInstrCalBoard/src/Xilinx.spec
+2
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@@ -0,0 +1,2 @@
*startfile:
crti%O%s crtbegin%O%s
Vitis_Classic/NewInstrCalBoard/src/cal_meas.c
+255
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@@ -0,0 +1,255 @@
/*
* cal_meas.c
*
* Created on: 2023年7月19日
* Author: dell
*/
#include "cal_meas.h"
#include "SPI_Driv.h"
char sw_config_data[3] = {0x00,0x00,0x00};
void sw_config(char *slot_start)
{
char slot = (*slot_start);
char m_fun = *(slot_start+1);
char ch_num_h = *(slot_start+2);
char ch_num_l = *(slot_start+3);
char volt_cur = *(slot_start+4);
char load = *(slot_start+5);
char memt_areal = *(slot_start+6);
u16 ch_num = 0;
u32 ch_num_dat = 0;
u32 relay_ctrl = 0;
u32 slot_en = 0x00000001;
u8 cpld_addr = 0;
u32 cpld_dat = 0;
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
if(slot==1)
{
cpld_addr = 0x82;
}
else if(slot==2)
{
cpld_addr = 0x83;
}
else if(slot==3)
{
cpld_addr = 0x84;
}
else
{
cpld_addr = 0x85;
}
switch(ch_num)
{
case 0x0001:
{
relay_ctrl = 0x00000000;
break;
}
case 0x0002:
{
relay_ctrl = 0x00020000;
break;
}
case 0x0003:
{
relay_ctrl = 0x00200000;
break;
}
case 0x0004:
{
relay_ctrl = 0x00220000;
break;
}
case 0x0005:
{
relay_ctrl = 0x00800000;
break;
}
case 0x0006:
{
relay_ctrl = 0x00810000;
break;
}
case 0x0007:
{
relay_ctrl = 0x00A00000;
break;
}
case 0x0008:
{
relay_ctrl = 0x00A10000;
break;
}
case 0x0041:
{
relay_ctrl = 0x00000000;
break;
}
case 0x0042:
{
relay_ctrl = 0x00008000;
break;
}
case 0x0043:
{
relay_ctrl = 0x00100000;
break;
}
case 0x0044:
{
relay_ctrl = 0x00108000;
break;
}
case 0x0045:
{
relay_ctrl = 0x00800000;
break;
}
case 0x0046:
{
relay_ctrl = 0x00804000;
break;
}
case 0x0047:
{
relay_ctrl = 0x00900000;
break;
}
case 0x0048:
{
relay_ctrl = 0x00904000;
break;
}
case 0x0081:
{
relay_ctrl = 0x00000000;
break;
}
case 0x0082:
{
relay_ctrl = 0x00002000;
break;
}
case 0x0083:
{
relay_ctrl = 0x00080000;
break;
}
case 0x0084:
{
relay_ctrl = 0x00082000;
break;
}
case 0x0085:
{
relay_ctrl = 0x00400000;
break;
}
case 0x0086:
{
relay_ctrl = 0x00401000;
break;
}
case 0x0087:
{
relay_ctrl = 0x00480000;
break;
}
case 0x0088:
{
relay_ctrl = 0x00481000;
break;
}
case 0x00C1:
{
relay_ctrl = 0x00000000;
break;
}
case 0x00C2:
{
relay_ctrl = 0x00000800;
break;
}
case 0x00C3:
{
relay_ctrl = 0x00040000;
break;
}
case 0x00C4:
{
relay_ctrl = 0x00040800;
break;
}
case 0x00C5:
{
relay_ctrl = 0x00400000;
break;
}
case 0x00C6:
{
relay_ctrl = 0x00400400;
break;
}
case 0x00C7:
{
relay_ctrl = 0x00440000;
break;
}
case 0x00C8:
{
relay_ctrl = 0x00440400;
break;
}
}
ch_num_dat = ((u32)ch_num)<<1;
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
sw_config_data[0] = (u8)(cpld_dat>>16);
sw_config_data[1] = (u8)(cpld_dat>>8);
sw_config_data[2] = (u8)(cpld_dat);
xil_printf("relay_ctrl: %d\n\r", relay_ctrl);
xil_printf("ch_num_dat: %d\n\r", ch_num_dat);
xil_printf("cpld_addr: %d\n\r", cpld_addr);
xil_printf("cpld_dat: %d\n\r", cpld_dat);
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[0]);
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[1]);
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[2]);
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
sw_config_data[0] = 0x00;
sw_config_data[1] = 0x00;
sw_config_data[2] = 0x01;
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U1);
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U2);
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U3);
slot_en = 0x00000000;
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
sw_config_data[0] = (u8)(cpld_dat>>16);
sw_config_data[1] = (u8)(cpld_dat>>8);
sw_config_data[2] = (u8)(cpld_dat);
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
}
Vitis_Classic/NewInstrCalBoard/src/cal_meas.h
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/*
* cal_meas.h
*
* Created on: 2023年7月19日
* Author: dell
*/
#ifndef SRC_CAL_MEAS_H_
#define SRC_CAL_MEAS_H_
#include "sleep.h"
#include "stdio.h"
#include "xgpiops.h"
#include "SPI_Driv.h"
#include "GPIO_Driv.h"
#define dat_width 3
void sw_config(char *slot_start);
#endif /* SRC_CAL_MEAS_H_ */
Vitis_Classic/NewInstrCalBoard/src/crc16.c
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/*
* crc16.c
*
* Created on: 2022年2月24日
* Author: Administrator
*/
#include "crc16.h"
const unsigned int crc_table[256] = {
0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
};
unsigned short do_crc_table(unsigned char* ptr, int len)
{
unsigned short crc = 0x0000;
while (len--)
{
crc = (crc >> 8) ^ crc_table[(crc ^ *ptr++) & 0xff];
}
return crc;
}
Vitis_Classic/NewInstrCalBoard/src/crc16.h
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/*
* crc16.h
*
* Created on: 2022年2月24日
* Author: Administrator
*/
#ifndef SRC_CRC16_H_
#define SRC_CRC16_H_
unsigned short do_crc_table(unsigned char* ptr, int len);
#endif /* SRC_CRC16_H_ */
Vitis_Classic/NewInstrCalBoard/src/dna_read.c
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/*
* dna_read.c
*
* Created on: 2023年6月27日
* Author: dell
*/
#include "dna_read.h"
#include <unistd.h>
#include "xil_io.h"
#include "xparameters.h"
#define DNA_ADDR XPAR_MYDNA_READ_V1_0_0_BASEADDR
void dna_port_read(char* read_data) //addr_change, because the board is 88d_a.
{
unsigned read_data_mem[2] = {0};
Xil_Out32(DNA_ADDR,0x01);
usleep(20);
read_data_mem[0] = Xil_In32(DNA_ADDR+4);
read_data_mem[1] = Xil_In32(DNA_ADDR+8);
for(int i = 0; i < 8; i++)
{
*(read_data+i) = (u8)(read_data_mem[i/4]>> (24 - (8*(i%4))));
}
}
Vitis_Classic/NewInstrCalBoard/src/dna_read.h
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/*
* dna_read.h
*
* Created on: 2023年6月27日
* Author: dell
*/
#ifndef SRC_DNA_READ_H_
#define SRC_DNA_READ_H_
void dna_port_read(char* read_data); //addr_change, because the board is 88d_a.
#endif /* SRC_DNA_READ_H_ */
Vitis_Classic/NewInstrCalBoard/src/echo.c
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/*
* Copyright (C) 2009 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
#include <stdio.h>
#include <string.h>
#include "dna_read.h"
#include "crc16.h"
#include "GPIO_Driv.h"
#include "SPI_Driv.h"
#include "cal_meas.h"
#include "lwip/err.h"
#include "lwip/tcp.h"
#if defined (__arm__) || defined (__aarch64__)
#include "xil_printf.h"
#endif
char *recv_data;
char dna_data[10];
unsigned short recv_len;
unsigned read_dat = 0;
char dat_0[20] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
unsigned crc_read_dat = 0;
char crc_alg_dat[2] = {0,0};
char send_data_cpld1[2] = {0xAA,0x56};
int transfer_data() {
return 0;
}
void print_app_header()
{
#if (LWIP_IPV6==0)
xil_printf("\n\r\n\r-----lwIP TCP echo server ------\n\r");
#else
xil_printf("\n\r\n\r-----lwIPv6 TCP echo server ------\n\r");
#endif
xil_printf("TCP packets sent to port 6001 will be echoed back\n\r");
}
err_t recv_callback(void *arg, struct tcp_pcb *tpcb,
struct pbuf *p, err_t err)
{
/* do not read the packet if we are not in ESTABLISHED state */
if (!p) {
tcp_close(tpcb);
tcp_recv(tpcb, NULL);
return ERR_OK;
}
/* indicate that the packet has been received */
tcp_recved(tpcb, p->len);
/* echo back the payload */
/* in this case, we assume that the payload is < TCP_SND_BUF */
if (tcp_sndbuf(tpcb) > p->len) {
recv_len = p->len;
recv_data = (char*)malloc(sizeof(char)*recv_len);
memcpy(recv_data,p->payload,recv_len);
if(recv_data[6] == 0x0E)
{
crc_read_dat = do_crc_table(recv_data+6, recv_len-8);
crc_alg_dat[0] = (u8)crc_read_dat;
crc_alg_dat[1] = (u8)(crc_read_dat>>8);
dat_0[0]= 0x00;
switch(recv_data[7])
{
case 0xA2://SLOT
{
dat_0[1]= 0x06;
dat_0[2]= recv_data[2];
dat_0[3]= recv_data[3];
dat_0[4]= recv_data[4];
dat_0[5]= recv_data[5];
dat_0[6]= recv_data[6];
dat_0[7]= recv_data[7];
if(recv_data[15]==crc_alg_dat[1]&&recv_data[16]==crc_alg_dat[0])
{
dat_0[8]= 0x01;
dat_0[9]= 0x01;
}
else
{
dat_0[8]= 0xff;
dat_0[9]= 0xff;
}
dat_0[10]= recv_data[15];
dat_0[11]= recv_data[16];
char slot_start[7] = {recv_data[8],recv_data[9],recv_data[10],recv_data[11],recv_data[12],recv_data[13],recv_data[14]};
//xil_printf("slot_start[0]:%x, slot_start[1]:%x,slot_start[2]:%x,slot_start[3]:%x,slot_start[4]:%x,slot_start[5]:%x,slot_start[6]:%x\n\r", slot_start[0],slot_start[1],slot_start[2],slot_start[3],slot_start[4],slot_start[5],slot_start[6]);
//rst_CPLD(CPLD_U1,4);
//rst_CPLD(CPLD_U2,4);
//rst_CPLD(CPLD_U3,4);
sw_config(slot_start);
tcp_write(tpcb, dat_0, 12, 1);
break;
}
case 0xA3://dna_port_read
{
dna_port_read(dna_data);
dat_0[1]=0x0e;
dat_0[2]=recv_data[2];
dat_0[3]=recv_data[3];
dat_0[4]=recv_data[4];
dat_0[5]=recv_data[5];
dat_0[6]=recv_data[6];
dat_0[7]=recv_data[7];
if(recv_data[8]==crc_alg_dat[1]&&recv_data[9]==crc_alg_dat[0])
{
dat_0[8]= 0x01;
dat_0[9]= 0x01;
}
else
{
dat_0[8]= 0xff;
dat_0[9]= 0xff;
}
dat_0[10]= dna_data[0];
dat_0[11]= dna_data[1];
dat_0[12]= dna_data[2];
dat_0[13]= dna_data[3];
dat_0[14]= dna_data[4];
dat_0[15]= dna_data[5];
dat_0[16]= dna_data[6];
dat_0[17]= dna_data[7];
dat_0[18]= recv_data[8];
dat_0[19]= recv_data[9];
tcp_write(tpcb, dat_0, 20, 1);
break;
}
}
}
} else
xil_printf("no space in tcp_sndbuf\n\r");
/* free the received pbuf */
pbuf_free(p);
return ERR_OK;
}
err_t accept_callback(void *arg, struct tcp_pcb *newpcb, err_t err)
{
static int connection = 1;
/* set the receive callback for this connection */
tcp_recv(newpcb, recv_callback);
/* just use an integer number indicating the connection id as the
callback argument */
tcp_arg(newpcb, (void*)(UINTPTR)connection);
/* increment for subsequent accepted connections */
connection++;
return ERR_OK;
}
int start_application()
{
struct tcp_pcb *pcb;
err_t err;
unsigned port = 200;
/* create new TCP PCB structure */
pcb = tcp_new_ip_type(IPADDR_TYPE_ANY);
if (!pcb) {
xil_printf("Error creating PCB. Out of Memory\n\r");
return -1;
}
/* bind to specified @port */
err = tcp_bind(pcb, IP_ANY_TYPE, port);
if (err != ERR_OK) {
xil_printf("Unable to bind to port %d: err = %d\n\r", port, err);
return -2;
}
/* we do not need any arguments to callback functions */
tcp_arg(pcb, NULL);
/* listen for connections */
pcb = tcp_listen(pcb);
if (!pcb) {
xil_printf("Out of memory while tcp_listen\n\r");
return -3;
}
/* specify callback to use for incoming connections */
tcp_accept(pcb, accept_callback);
xil_printf("TCP echo server started @ port %d\n\r", port);
return 0;
}
Vitis_Classic/NewInstrCalBoard/src/i2c_access.c
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/*
* Copyright (C) 2013 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
/*****************************************************************************/
/**
* @file i2c_lib.c
*
* This file contains library functions to initialize, control and access
* IIC devices.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 1.0 srt 10/19/13 Initial Version
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#if defined (__arm__) && !defined (ARMR5)
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || \
XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
#include "xil_exception.h"
#include "xil_printf.h"
#include "xiicps.h"
#include "sleep.h"
#include "xscugic.h"
/************************** Constant Definitions *****************************/
#define IIC_DEVICE_ID XPAR_XIICPS_0_DEVICE_ID
#define XIIC XIicPs
#define XIICCFG XIicPs_Config
#define I2cSetStatusHandler XIicPs_SetStatusHandler
#define I2cLookupConfig XIicPs_LookupConfig
#define I2cCfgInitialize XIicPs_CfgInitialize
#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
#define IIC_INTR_ID XPAR_XIICPS_0_INTR
#define INTC_HANDLER XScuGic_InterruptHandler
#define IIC_HANDLER XIicPs_IntrHandler
#define INTC XScuGic
#define IIC_SCLK_RATE 100000
/**************************** Type Definitions *******************************/
typedef struct {
XIIC I2cInstance;
INTC IntcInstance;
volatile u8 TransmitComplete; /* Flag to check completion of Transmission */
volatile u8 ReceiveComplete; /* Flag to check completion of Reception */
volatile u32 TotalErrorCount;
} XIIC_LIB;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
int I2cPhyWrite(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 Data, u16 SlaveAddr);
int I2cPhyRead(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 *Data, u16 SlaveAddr);
int I2cSetupHardware(XIIC_LIB *I2cLibPtr);
int I2cWriteData(XIIC_LIB *I2cLibPtr, u8 *WrBuffer, u16 ByteCount, u16 SlaveAddr);
int I2cReadData(XIIC_LIB *I2cLibPtr, u8 *RdBuffer, u16 ByteCount, u16 SlaveAddr);
static int SetupInterruptSystem(XIIC_LIB *I2cLibPtr);
static void StatusHandler(XIIC_LIB *I2cLibPtr, int Event);
/************************* Global Definitions *****************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
* This function configures the IIC hardware.
*
* @param I2cLibPtr contains a pointer to the instance of the IIC library
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int I2cSetupHardware(XIIC_LIB *I2cLibPtr)
{
int Status;
XIICCFG *ConfigPtr;
XIIC *I2cInstancePtr;
I2cInstancePtr = &I2cLibPtr->I2cInstance;
/*
* Initialize the IIC driver so that it is ready to use.
*/
ConfigPtr = I2cLookupConfig(IIC_DEVICE_ID);
if (ConfigPtr == NULL) {
return XST_FAILURE;
}
Status = I2cCfgInitialize(I2cInstancePtr, ConfigPtr,
ConfigPtr->BaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* GPIO Code to pull MUX out of reset.
*/
Xil_Out32(0xe000a204, 0x2000);
Xil_Out32(0xe000a208, 0x2000);
Xil_Out32(0xe000a040, 0x2000);
/*
* Setup the Interrupt System.
*/
Status = SetupInterruptSystem(I2cLibPtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
I2cSetStatusHandler(I2cInstancePtr, I2cLibPtr, (IIC_HANDLER) StatusHandler);
/*
* Set the IIC serial clock rate.
*/
XIicPs_SetSClk(I2cInstancePtr, IIC_SCLK_RATE);
I2cLibPtr->TotalErrorCount = 0;
I2cLibPtr->TransmitComplete = FALSE;
I2cLibPtr->ReceiveComplete = FALSE;
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function writes data to the PHY.
*
* @param I2cLibPtr contains a pointer to the instance of the IIC library
* @param PhyAddr is the address of PHY to be written
* @param Reg is the register address to be written to
* @param Data is the pointer which contains the data to be written
* @param SlaveAddr is the address of the slave we are sending to.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int I2cPhyWrite(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 Data, u16 SlaveAddr)
{
int Status;
u8 WrBuffer[3];
WrBuffer[0] = Reg;
WrBuffer[1] = Data >> 8;
WrBuffer[2] = Data;
Status = I2cWriteData(I2cLibPtr, WrBuffer, 3, SlaveAddr);
if (Status != XST_SUCCESS) {
xil_printf("PhyWrite: Writing data failed\n\r");
return Status;
}
return Status;
}
/*****************************************************************************/
/**
* This function reads data from the PHY.
*
* @param I2cLibPtr contains a pointer to the instance of the IIC library
* @param PhyAddr is the address of PHY to be read from
* @param Reg is the register address to be read from
* @param Data is the pointer which stores the data read
* @param SlaveAddr is the address of the slave we are sending to.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int I2cPhyRead(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 *Data, u16 SlaveAddr)
{
int Status;
u8 WrBuffer[2];
u8 RdBuffer[2];
WrBuffer[0] = Reg;
Status = I2cWriteData(I2cLibPtr, WrBuffer, 1, SlaveAddr);
if (Status != XST_SUCCESS) {
xil_printf("PhyWrite: Writing data failed\n\r");
return Status;
}
Status = I2cReadData(I2cLibPtr, RdBuffer, 2, SlaveAddr);
if (Status != XST_SUCCESS) {
xil_printf("PhyRead: Reading data failed\n\r");
return Status;
}
*Data = RdBuffer[0] << 8 | RdBuffer[1];
return Status;
}
/*****************************************************************************/
/**
* This function writes a buffer of data to the IIC Device.
*
* @param I2cLibPtr contains a pointer to the instance of the IIC library
* @param WrBuffer is the buffer which contains data to be written
* @param ByteCount contains the number of bytes in the buffer to be
* written.
* @param SlaveAddr is the address of the slave we are sending to.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int I2cWriteData(XIIC_LIB *I2cLibPtr, u8 *WrBuffer, u16 ByteCount,
u16 SlaveAddr)
{
XIIC *I2cInstancePtr;
I2cInstancePtr = &I2cLibPtr->I2cInstance;
I2cLibPtr->TransmitComplete = FALSE;
/*
* Send the Data.
*/
XIicPs_MasterSend(I2cInstancePtr, WrBuffer, ByteCount, SlaveAddr);
/*
* Wait for the entire buffer to be sent, letting the interrupt
* processing work in the background, this function may get
* locked up in this loop if the interrupts are not working
* correctly.
*/
while (I2cLibPtr->TransmitComplete == FALSE) {
if (0 != I2cLibPtr->TotalErrorCount) {
xil_printf("I2cWriteData: Failed due to errors\n\r");
return XST_FAILURE;
}
}
/*
* Wait until bus is idle to start another transfer.
*/
while (XIicPs_BusIsBusy(I2cInstancePtr));
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function read data from the IIC Device.
*
* @param I2cLibPtr contains a pointer to the instance of the IIC library
* @param RdBuffer is the buffer into which data read
* @param ByteCount contains the number of bytes in the buffer to be
* written.
* @param SlaveAddr is the address of the slave we are sending to.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int I2cReadData(XIIC_LIB *I2cLibPtr, u8 *RdBuffer, u16 ByteCount, u16 SlaveAddr)
{
XIIC *I2cInstancePtr;
I2cInstancePtr = &I2cLibPtr->I2cInstance;
I2cLibPtr->ReceiveComplete = FALSE;
/*
* Receive the Data.
*/
XIicPs_MasterRecv(I2cInstancePtr, RdBuffer, ByteCount, SlaveAddr);
while (I2cLibPtr->ReceiveComplete == FALSE) {
if (0 != I2cLibPtr->TotalErrorCount) {
xil_printf("I2cReadData: Failed due to errors %d\n\r",
I2cLibPtr->TotalErrorCount);
return XST_FAILURE;
}
}
/*
* Wait until bus is idle to start another transfer.
*/
while (XIicPs_BusIsBusy(I2cInstancePtr))
;
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function setups the interrupt system so interrupts can occur for the
* IIC device. The function is application-specific since the actual system may
* or may not have an interrupt controller. The IIC device could be directly
* connected to a processor without an interrupt controller. The user should
* modify this function to fit the application.
*
* @param IicInstPtr contains a pointer to the instance of the IIC device
* which is going to be connected to the interrupt controller.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
* @note None.
*
******************************************************************************/
static int SetupInterruptSystem(XIIC_LIB *I2cLibPtr)
{
int Status;
XIIC *I2cInstancePtr;
INTC *IntcPtr;
I2cInstancePtr = &I2cLibPtr->I2cInstance;
IntcPtr = &I2cLibPtr->IntcInstance;
XScuGic_Config *IntcConfig;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcPtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(IntcPtr, IIC_INTR_ID, 0xA0, 0x3);
/*
* Connect the interrupt handler that will be called when an
* interrupt occurs for the device.
*/
Status = XScuGic_Connect(IntcPtr, IIC_INTR_ID,
(Xil_InterruptHandler) XIicPs_MasterInterruptHandler,
I2cInstancePtr);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Enable the interrupt for the IIC device.
*/
XScuGic_Enable(IntcPtr, IIC_INTR_ID);
/*
* Initialize the exception table and register the interrupt
* controller handler with the exception table
*/
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler) INTC_HANDLER, IntcPtr);
/* Enable non-critical exceptions */Xil_ExceptionEnable();
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This Status handler is called asynchronously from an interrupt
* context and indicates the events that have occurred.
*
* @param InstancePtr is a pointer to the IIC driver instance for which
* the handler is being called for.
* @param Event indicates the condition that has occurred.
*
* @return None.
*
* @note None.
*
******************************************************************************/
static void StatusHandler(XIIC_LIB *I2cLibPtr, int Event)
{
/*
* All of the data transfer has been finished.
*/
if (0 != (Event & XIICPS_EVENT_COMPLETE_RECV)) {
I2cLibPtr->ReceiveComplete = TRUE;
} else if (0 != (Event & XIICPS_EVENT_COMPLETE_SEND)) {
I2cLibPtr->TransmitComplete = TRUE;
} else if (0 == (Event & XIICPS_EVENT_SLAVE_RDY)) {
/*
* If it is other interrupt but not slave ready interrupt, it is
* an error.
* Data was received with an error.
*/
I2cLibPtr->TotalErrorCount++;
}
}
#endif
#endif
Vitis_Classic/NewInstrCalBoard/src/iic_phyreset.c
+117
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@@ -0,0 +1,117 @@
/*
* Copyright (C) 2016 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
#include <stdio.h>
#include "xparameters.h"
#if defined (__arm__) || defined(__aarch64__)
#include "xil_printf.h"
#endif
#ifdef XPS_BOARD_ZCU102
#ifdef XPAR_XIICPS_0_DEVICE_ID
#include "xiicps.h"
#define BUF_LEN 10U
#define IOEXPANDER1_ADDR 0x20U
#define IIC_SCLK_RATE_IOEXP 400000
#define CMD_CFG_0_REG 0x06U
#define CMD_OUTPUT_0_REG 0x02U
#define DATA_OUTPUT 0x0U
#define DATA_COMMON_CFG 0xE0U
#define DATA_GT_0000_CFG 0x00U
XIicPs I2c0InstancePtr;
int IicPhyReset(void)
{
u8 WriteBuffer[BUF_LEN] = {0};
XIicPs_Config *I2c0CfgPtr;
int Status = XST_SUCCESS;
/* Initialize the IIC0 driver so that it is ready to use */
I2c0CfgPtr = XIicPs_LookupConfig(XPAR_XIICPS_0_DEVICE_ID);
if (I2c0CfgPtr == NULL) {
Status = XST_FAILURE;
return Status;
}
Status = XIicPs_CfgInitialize(&I2c0InstancePtr, I2c0CfgPtr,
I2c0CfgPtr->BaseAddress);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
return Status;
}
/* Set the IIC serial clock rate */
XIicPs_SetSClk(&I2c0InstancePtr, IIC_SCLK_RATE_IOEXP);
/* Configure I/O pins as Output */
WriteBuffer[0] = CMD_CFG_0_REG;
WriteBuffer[1] = DATA_OUTPUT;
Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
WriteBuffer, 2, IOEXPANDER1_ADDR);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
return Status;
}
/* Wait until bus is idle to start another transfer */
while (XIicPs_BusIsBusy(&I2c0InstancePtr));
/*
* Deasserting I2C_MUX_RESETB
* And GEM3 Resetb
* Selecting lanes based on configuration
*/
WriteBuffer[0] = CMD_OUTPUT_0_REG;
/* gt0000 or no GT configuration */
WriteBuffer[1] = DATA_COMMON_CFG | DATA_GT_0000_CFG;
/* Send the Data */
Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
WriteBuffer, 2, IOEXPANDER1_ADDR);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
return Status;
}
/* Wait until bus is idle */
while (XIicPs_BusIsBusy(&I2c0InstancePtr));
xil_printf("IIC PHY reset on ZCU102 successful \n\r");
return XST_SUCCESS;
}
#endif
#endif
Vitis_Classic/NewInstrCalBoard/src/lscript.ld
+293
View File
@@ -0,0 +1,293 @@
/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: 2018.3 */
/* */
/* Copyright (c) 2010-2019 Xilinx, Inc. All rights reserved. */
/* */
/* Description : Cortex-A9 Linker Script */
/* */
/*******************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
/* Define Memories in the system */
MEMORY
{
ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x3FF00000
ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x1000000
ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
}
/* Specify the default entry point to the program */
ENTRY(_vector_table)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
.text : {
. = ALIGN(2048);
KEEP (*(.vectors))
*(.boot)
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
*(.plt)
*(.gnu_warning)
*(.gcc_execpt_table)
*(.glue_7)
*(.glue_7t)
*(.vfp11_veneer)
*(.ARM.extab)
*(.gnu.linkonce.armextab.*)
} > ps7_ddr_0
.init : {
KEEP (*(.init))
} > ps7_ddr_0
.fini : {
KEEP (*(.fini))
} > ps7_ddr_0
.rodata : {
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > ps7_ddr_0
.rodata1 : {
__rodata1_start = .;
*(.rodata1)
*(.rodata1.*)
__rodata1_end = .;
} > ps7_ddr_0
.sdata2 : {
__sdata2_start = .;
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
__sdata2_end = .;
} > ps7_ddr_0
.sbss2 : {
__sbss2_start = .;
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
} > ps7_ddr_0
.data : {
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.jcr)
*(.got)
*(.got.plt)
__data_end = .;
} > ps7_ddr_0
.data1 : {
__data1_start = .;
*(.data1)
*(.data1.*)
__data1_end = .;
} > ps7_ddr_0
.got : {
*(.got)
} > ps7_ddr_0
.note.gnu.build-id : {
KEEP (*(.note.gnu.build-id))
} > ps7_ddr_0
.ctors : {
__CTOR_LIST__ = .;
___CTORS_LIST___ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > ps7_ddr_0
.dtors : {
__DTOR_LIST__ = .;
___DTORS_LIST___ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
___DTORS_END___ = .;
} > ps7_ddr_0
.fixup : {
__fixup_start = .;
*(.fixup)
__fixup_end = .;
} > ps7_ddr_0
.eh_frame : {
*(.eh_frame)
} > ps7_ddr_0
.eh_framehdr : {
__eh_framehdr_start = .;
*(.eh_framehdr)
__eh_framehdr_end = .;
} > ps7_ddr_0
.gcc_except_table : {
*(.gcc_except_table)
} > ps7_ddr_0
.mmu_tbl (ALIGN(16384)) : {
__mmu_tbl_start = .;
*(.mmu_tbl)
__mmu_tbl_end = .;
} > ps7_ddr_0
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidix.*.*)
__exidx_end = .;
} > ps7_ddr_0
.preinit_array : {
__preinit_array_start = .;
KEEP (*(SORT(.preinit_array.*)))
KEEP (*(.preinit_array))
__preinit_array_end = .;
} > ps7_ddr_0
.init_array : {
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
} > ps7_ddr_0
.fini_array : {
__fini_array_start = .;
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
} > ps7_ddr_0
.ARM.attributes : {
__ARM.attributes_start = .;
*(.ARM.attributes)
__ARM.attributes_end = .;
} > ps7_ddr_0
.sdata : {
__sdata_start = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > ps7_ddr_0
.sbss (NOLOAD) : {
__sbss_start = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
__sbss_end = .;
} > ps7_ddr_0
.tdata : {
__tdata_start = .;
*(.tdata)
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > ps7_ddr_0
.tbss : {
__tbss_start = .;
*(.tbss)
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > ps7_ddr_0
.bss (NOLOAD) : {
__bss_start = .;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
__bss_end = .;
} > ps7_ddr_0
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
/* Generate Stack and Heap definitions */
.heap (NOLOAD) : {
. = ALIGN(16);
_heap = .;
HeapBase = .;
_heap_start = .;
. += _HEAP_SIZE;
_heap_end = .;
HeapLimit = .;
} > ps7_ddr_0
.stack (NOLOAD) : {
. = ALIGN(16);
_stack_end = .;
. += _STACK_SIZE;
. = ALIGN(16);
_stack = .;
__stack = _stack;
. = ALIGN(16);
_irq_stack_end = .;
. += _IRQ_STACK_SIZE;
. = ALIGN(16);
__irq_stack = .;
_supervisor_stack_end = .;
. += _SUPERVISOR_STACK_SIZE;
. = ALIGN(16);
__supervisor_stack = .;
_abort_stack_end = .;
. += _ABORT_STACK_SIZE;
. = ALIGN(16);
__abort_stack = .;
_fiq_stack_end = .;
. += _FIQ_STACK_SIZE;
. = ALIGN(16);
__fiq_stack = .;
_undef_stack_end = .;
. += _UNDEF_STACK_SIZE;
. = ALIGN(16);
__undef_stack = .;
} > ps7_ddr_0
_end = .;
}
Vitis_Classic/NewInstrCalBoard/src/main.c
+249
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@@ -0,0 +1,249 @@
/*
* Copyright (C) 2009 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
#include <stdio.h>
#include "xparameters.h"
#include "netif/xadapter.h"
#include "platform.h"
#include "platform_config.h"
#if defined (__arm__) || defined(__aarch64__)
#include "xil_printf.h"
#endif
#include "lwip/tcp.h"
extern void tcp_tmr(void); /* declared in tcp_priv.h, not in public tcp.h */
#include "xil_cache.h"
#include "GPIO_Driv.h"
#include "SPI_Driv.h"
#include "cal_meas.h"
#if LWIP_IPV6==1
#include "lwip/ip.h"
#else
#if LWIP_DHCP==1
#include "lwip/dhcp.h"
#endif
#endif
/* defined by each RAW mode application */
void print_app_header();
int start_application();
int transfer_data();
/* missing declaration in lwIP */
void lwip_init();
#if LWIP_IPV6==0
#if LWIP_DHCP==1
extern volatile int dhcp_timoutcntr;
err_t dhcp_start(struct netif *netif);
#endif
#endif
static struct netif server_netif;
struct netif *echo_netif;
#if LWIP_IPV6==1
void print_ip6(char *msg, ip_addr_t *ip)
{
print(msg);
xil_printf(" %x:%x:%x:%x:%x:%x:%x:%x\n\r",
IP6_ADDR_BLOCK1(&ip->u_addr.ip6),
IP6_ADDR_BLOCK2(&ip->u_addr.ip6),
IP6_ADDR_BLOCK3(&ip->u_addr.ip6),
IP6_ADDR_BLOCK4(&ip->u_addr.ip6),
IP6_ADDR_BLOCK5(&ip->u_addr.ip6),
IP6_ADDR_BLOCK6(&ip->u_addr.ip6),
IP6_ADDR_BLOCK7(&ip->u_addr.ip6),
IP6_ADDR_BLOCK8(&ip->u_addr.ip6));
}
#else
void
print_ip(char *msg, ip_addr_t *ip)
{
print(msg);
xil_printf("%d.%d.%d.%d\n\r", ip4_addr1(ip), ip4_addr2(ip),
ip4_addr3(ip), ip4_addr4(ip));
}
void
print_ip_settings(ip_addr_t *ip, ip_addr_t *mask, ip_addr_t *gw)
{
print_ip("Board IP: ", ip);
print_ip("Netmask : ", mask);
print_ip("Gateway : ", gw);
}
#endif
#if defined (__arm__) && !defined (ARMR5)
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
int ProgramSi5324(void);
int ProgramSfpPhy(void);
#endif
#endif
#ifdef XPS_BOARD_ZCU102
#ifdef XPAR_XIICPS_0_DEVICE_ID
int IicPhyReset(void);
#endif
#endif
int main()
{
#if LWIP_IPV6==0
ip_addr_t ipaddr, netmask, gw;
#endif
/* the mac address of the board. this should be unique per board */
unsigned char mac_ethernet_address[] =
{ 0x00, 0x0a, 0x35, 0x00, 0x01, 0x01 };
echo_netif = &server_netif;
#if defined (__arm__) && !defined (ARMR5)
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
ProgramSi5324();
ProgramSfpPhy();
#endif
#endif
/* Define this board specific macro in order perform PHY reset on ZCU102 */
#ifdef XPS_BOARD_ZCU102
if(IicPhyReset()) {
xil_printf("Error performing PHY reset \n\r");
return -1;
}
#endif
init_platform();
#if LWIP_IPV6==0
#if LWIP_DHCP==1
ipaddr.addr = 0;
gw.addr = 0;
netmask.addr = 0;
#else
/* initialize IP addresses to be used */
IP4_ADDR(&ipaddr, 192, 168, 100, 110);
IP4_ADDR(&netmask, 255, 255, 255, 0);
IP4_ADDR(&gw, 192, 168, 100, 1);
#endif
#endif
print_app_header();
lwip_init();
#if (LWIP_IPV6 == 0)
/* Add network interface to the netif_list, and set it as default */
if (!xemac_add(echo_netif, &ipaddr, &netmask,
&gw, mac_ethernet_address,
PLATFORM_EMAC_BASEADDR)) {
xil_printf("Error adding N/W interface\n\r");
return -1;
}
#else
/* Add network interface to the netif_list, and set it as default */
if (!xemac_add(echo_netif, NULL, NULL, NULL, mac_ethernet_address,
PLATFORM_EMAC_BASEADDR)) {
xil_printf("Error adding N/W interface\n\r");
return -1;
}
echo_netif->ip6_autoconfig_enabled = 1;
netif_create_ip6_linklocal_address(echo_netif, 1);
netif_ip6_addr_set_state(echo_netif, 0, IP6_ADDR_VALID);
print_ip6("\n\rBoard IPv6 address ", &echo_netif->ip6_addr[0].u_addr.ip6);
#endif
netif_set_default(echo_netif);
/* now enable interrupts */
//platform_enable_interrupts();
/* specify that the network if is up */
netif_set_up(echo_netif);
#if (LWIP_IPV6 == 0)
#if (LWIP_DHCP==1)
/* Create a new DHCP client for this interface.
* Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at
* the predefined regular intervals after starting the client.
*/
dhcp_start(echo_netif);
dhcp_timoutcntr = 24;
while(((echo_netif->ip_addr.addr) == 0) && (dhcp_timoutcntr > 0))
xemacif_input(echo_netif);
if (dhcp_timoutcntr <= 0) {
if ((echo_netif->ip_addr.addr) == 0) {
xil_printf("DHCP Timeout\r\n");
xil_printf("Configuring default IP of 192.168.100.110\r\n");
IP4_ADDR(&(echo_netif->ip_addr), 192, 168, 100, 110);
IP4_ADDR(&(echo_netif->netmask), 255, 255, 255, 0);
IP4_ADDR(&(echo_netif->gw), 192, 168, 100, 1);
}
}
ipaddr.addr = echo_netif->ip_addr.addr;
gw.addr = echo_netif->gw.addr;
netmask.addr = echo_netif->netmask.addr;
#endif
print_ip_settings(&ipaddr, &netmask, &gw);
#endif
EMIO_config();
interface_initial(CPLD_U1);
interface_initial(CPLD_U2);
interface_initial(CPLD_U3);
rst_CPLD(CPLD_U1,4);
rst_CPLD(CPLD_U2,4);
rst_CPLD(CPLD_U3,4);
/* start the application (web server, rxtest, txtest, etc..) */
start_application();
/* receive and process packets */
while (1) {
tcp_tmr();
xemacif_input(echo_netif);
transfer_data();
}
/* never reached */
cleanup_platform();
return 0;
}
Vitis_Classic/NewInstrCalBoard/src/platform.c
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/******************************************************************************
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xparameters.h"
#include "xil_cache.h"
#ifndef SDT
#include "platform_config.h"
#endif
/*
* Uncomment one of the following two lines, depending on the target,
* if ps7/psu init source files are added in the source directory for
* compiling example outside of SDK.
*/
/*#include "ps7_init.h"*/
/*#include "psu_init.h"*/
#ifdef STDOUT_IS_16550
#include "xuartns550_l.h"
#define UART_BAUD 9600
#endif
void
enable_caches()
{
#ifdef __PPC__
Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
#elif __MICROBLAZE__
#ifdef XPAR_MICROBLAZE_USE_ICACHE
Xil_ICacheEnable();
#endif
#ifdef XPAR_MICROBLAZE_USE_DCACHE
Xil_DCacheEnable();
#endif
#endif
}
void
disable_caches()
{
#ifdef __MICROBLAZE__
#ifdef XPAR_MICROBLAZE_USE_DCACHE
Xil_DCacheDisable();
#endif
#ifdef XPAR_MICROBLAZE_USE_ICACHE
Xil_ICacheDisable();
#endif
#endif
}
void
init_uart()
{
#ifdef STDOUT_IS_16550
XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
#endif
/* Bootrom/BSP configures PS7/PSU UART to 115200 bps */
}
void
init_platform()
{
/*
* If you want to run this example outside of SDK,
* uncomment one of the following two lines and also #include "ps7_init.h"
* or #include "ps7_init.h" at the top, depending on the target.
* Make sure that the ps7/psu_init.c and ps7/psu_init.h files are included
* along with this example source files for compilation.
*/
/* ps7_init();*/
/* psu_init();*/
enable_caches();
init_uart();
}
void
cleanup_platform()
{
disable_caches();
}
Vitis_Classic/NewInstrCalBoard/src/platform.h
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/******************************************************************************
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef __PLATFORM_H_
#define __PLATFORM_H_
#ifndef SDT
#include "platform_config.h"
#endif
void init_platform();
void cleanup_platform();
#endif
Vitis_Classic/NewInstrCalBoard/src/platform_config.h
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#ifndef __PLATFORM_CONFIG_H_
#define __PLATFORM_CONFIG_H_
#define STDOUT_IS_PS7_UART
#define UART_DEVICE_ID 0
#define PLATFORM_EMAC_BASEADDR XPAR_XEMACPS_0_BASEADDR
#endif
Vitis_Classic/NewInstrCalBoard/src/sfp.c
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/*
* Copyright (C) 2013 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
/*****************************************************************************/
/**
* @file sfp.c
*
* This file programs sfp phy chip.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 1.0 srt 10/19/13 Initial Version
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#if defined (__arm__) && !defined (ARMR5)
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || \
XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
#include "xil_printf.h"
#include "xiicps.h"
#include "sleep.h"
#include "xscugic.h"
/************************** Constant Definitions *****************************/
#define IIC_SLAVE_ADDR 0x56
#define IIC_MUX_ADDRESS 0x74
#define IIC_CHANNEL_ADDRESS 0x01
#define XIIC XIicPs
#define INTC XScuGic
/**************************** Type Definitions *******************************/
typedef struct {
XIIC I2cInstance;
INTC IntcInstance;
volatile u8 TransmitComplete; /* Flag to check completion of Transmission */
volatile u8 ReceiveComplete; /* Flag to check completion of Reception */
volatile u32 TotalErrorCount;
} XIIC_LIB;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
int I2cWriteData(XIIC_LIB *I2cLibPtr, u8 *WrBuffer, u16 ByteCount, u16 SlaveAddr);
int I2cReadData(XIIC_LIB *I2cLibPtr, u8 *RdBuffer, u16 ByteCount, u16 SlaveAddr);
int I2cPhyWrite(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 Data, u16 SlaveAddr);
int I2cPhyRead(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 *Data, u16 SlaveAddr);
int I2cSetupHardware(XIIC_LIB *I2cLibPtr);
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
* This function initializes ZC706 MUX.
*
* @param I2cLibPtr contains a pointer to the instance of the IIC library
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int ZC706MuxInit(XIIC_LIB *I2cLibInstancePtr)
{
u8 WrBuffer;
int Status;
WrBuffer = IIC_CHANNEL_ADDRESS;
Status = I2cWriteData(I2cLibInstancePtr, &WrBuffer, 1, IIC_MUX_ADDRESS);
if (Status != XST_SUCCESS) {
xil_printf("SFP_PHY: Writing failed\n\r");
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function program SFP PHY.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int ProgramSfpPhy(void)
{
XIIC_LIB I2cLibInstance;
int Status;
u8 WrBuffer[2];
u16 phy_read_val;
Status = I2cSetupHardware(&I2cLibInstance);
if (Status != XST_SUCCESS) {
xil_printf("Fail!!!\n\r");
xil_printf("SFP_PHY: Configuring HW failed\n\r");
return XST_FAILURE;
}
Status = ZC706MuxInit(&I2cLibInstance);
if (Status != XST_SUCCESS) {
xil_printf("SFP_PHY: Mux Init failed\n\r");
return XST_FAILURE;
}
WrBuffer[0] = 0;
Status = I2cWriteData(&I2cLibInstance, WrBuffer, 1, IIC_SLAVE_ADDR);
if (Status != XST_SUCCESS) {
xil_printf("SFP_PHY: Writing failed\n\r");
return XST_FAILURE;
}
#if XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
/* Enabling 1000BASEX */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x1B, 0x9088, IIC_SLAVE_ADDR);
#else
/* Enabling SGMII */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x1B, 0x9084, IIC_SLAVE_ADDR);
#endif
/* Apply Soft Reset */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
/* Enable 1000BaseT Full Duplex capabilities */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x09, 0x0E00, IIC_SLAVE_ADDR);
/* Apply Soft Reset */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
/* Advertise 10/100 Capabilities else change the capabilities */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x04, 0x0141, IIC_SLAVE_ADDR);
/* Apply Soft Reset */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
/* Apply Soft Reset */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x10, 0xF079, IIC_SLAVE_ADDR);
/* Apply Soft Reset */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0001, IIC_SLAVE_ADDR);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9340, IIC_SLAVE_ADDR);
usleep(1);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0, IIC_SLAVE_ADDR);
phy_read_val = 0x0;
while((phy_read_val & 0x0C00) != 0x0C00) {
I2cPhyRead(&I2cLibInstance, IIC_SLAVE_ADDR, 0x11, &phy_read_val, IIC_SLAVE_ADDR);
}
usleep(1);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0, IIC_SLAVE_ADDR);
I2cPhyRead(&I2cLibInstance, IIC_SLAVE_ADDR, 0x11, &phy_read_val, IIC_SLAVE_ADDR);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0001, IIC_SLAVE_ADDR);
/* configure speed */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x14, 0x0c61, IIC_SLAVE_ADDR);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9340, IIC_SLAVE_ADDR);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0, IIC_SLAVE_ADDR);
return XST_SUCCESS;
}
#endif
#endif
Vitis_Classic/NewInstrCalBoard/src/si5324.c
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/*
* Copyright (C) 2013 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
/*****************************************************************************/
/**
* @file si5324.c
*
* This file programs si5324 chip which generates clock for the peripherals.
*
* Please refer to Si5324 Datasheet for more information
* http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5324.pdf
*
* Tested on Zynq ZC706 platform
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 1.0 srt 10/19/13 Initial Version
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#if defined (__arm__) && !defined (ARMR5)
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || \
XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
#include "xil_printf.h"
#include "xiicps.h"
#include "sleep.h"
#include "xscugic.h"
/************************** Constant Definitions *****************************/
#define IIC_SLAVE_ADDR 0x68
#define IIC_MUX_ADDRESS 0x74
#define IIC_CHANNEL_ADDRESS 0x10
#define XIIC XIicPs
#define INTC XScuGic
/**************************** Type Definitions *******************************/
typedef struct SI324Info
{
u32 RegIndex; /* Register Number */
u32 Value; /* Value to be Written */
} SI324Info;
typedef struct {
XIIC I2cInstance;
INTC IntcInstance;
volatile u8 TransmitComplete; /* Flag to check completion of Transmission */
volatile u8 ReceiveComplete; /* Flag to check completion of Reception */
volatile u32 TotalErrorCount;
} XIIC_LIB;
/************************** Function Prototypes *****************************/
int I2cWriteData(XIIC_LIB *I2cLibPtr, u8 *WrBuffer, u16 ByteCount, u16 SlaveAddr);
int I2cReadData(XIIC_LIB *I2cLibPtr, u8 *RdBuffer, u16 ByteCount, u16 SlaveAddr);
int I2cPhyWrite(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 Data, u16 SlaveAddr);
int I2cPhyRead(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 *Data, u16 SlaveAddr);
int I2cSetupHardware(XIIC_LIB *I2cLibPtr);
/************************* Global Definitions *****************************/
/*
* These configuration values generates 125MHz clock
* For more information please refer to Si5324 Datasheet.
*/
SI324Info InitTable[] = {
{ 0, 0x54}, /* Register 0 */
{ 1, 0xE4}, /* Register 1 */
{ 2, 0x12}, /* Register 2 */
{ 3, 0x15}, /* Register 3 */
{ 4, 0x92}, /* Register 4 */
{ 5, 0xed}, /* Register 5 */
{ 6, 0x2d}, /* Register 6 */
{ 7, 0x2a}, /* Register 7 */
{ 8, 0x00}, /* Register 8 */
{ 9, 0xc0}, /* Register 9 */
{ 10, 0x08}, /* Register 10 */
{ 11, 0x40}, /* Register 11 */
{ 19, 0x29}, /* Register 19 */
{ 20, 0x3e}, /* Register 20 */
{ 21, 0xff}, /* Register 21 */
{ 22, 0xdf}, /* Register 22 */
{ 23, 0x1f}, /* Register 23 */
{ 24, 0x3f}, /* Register 24 */
{ 25, 0x60}, /* Register 25 */
{ 31, 0x00}, /* Register 31 */
{ 32, 0x00}, /* Register 32 */
{ 33, 0x05}, /* Register 33 */
{ 34, 0x00}, /* Register 34 */
{ 35, 0x00}, /* Register 35 */
{ 36, 0x05}, /* Register 36 */
{ 40, 0xc2}, /* Register 40 */
{ 41, 0x22}, /* Register 41 */
{ 42, 0xdf}, /* Register 42 */
{ 43, 0x00}, /* Register 43 */
{ 44, 0x77}, /* Register 44 */
{ 45, 0x0b}, /* Register 45 */
{ 46, 0x00}, /* Register 46 */
{ 47, 0x77}, /* Register 47 */
{ 48, 0x0b}, /* Register 48 */
{ 55, 0x00}, /* Register 55 */
{131, 0x1f}, /* Register 131 */
{132, 0x02}, /* Register 132 */
{137, 0x01}, /* Register 137 */
{138, 0x0f}, /* Register 138 */
{139, 0xff}, /* Register 139 */
{142, 0x00}, /* Register 142 */
{143, 0x00}, /* Register 143 */
{136, 0x40} /* Register 136 */
};
/************************** Function Definitions *****************************/
int MuxInit(XIIC_LIB *I2cLibInstancePtr)
{
u8 WrBuffer[0];
int Status;
WrBuffer[0] = IIC_CHANNEL_ADDRESS;
Status = I2cWriteData(I2cLibInstancePtr,
WrBuffer, 1, IIC_MUX_ADDRESS);
if (Status != XST_SUCCESS) {
xil_printf("Si5324: Writing failed\n\r");
return XST_FAILURE;
}
return XST_SUCCESS;
}
int ProgramSi5324(void)
{
XIIC_LIB I2cLibInstance;
int Index;
int Status;
u8 WrBuffer[2];
Status = I2cSetupHardware(&I2cLibInstance);
if (Status != XST_SUCCESS) {
xil_printf("Si5324: Configuring HW failed\n\r");
return XST_FAILURE;
}
Status = MuxInit(&I2cLibInstance);
if (Status != XST_SUCCESS) {
xil_printf("Si5324: Mux Init failed\n\r");
return XST_FAILURE;
}
for (Index = 0; Index < sizeof(InitTable)/8; Index++) {
WrBuffer[0] = InitTable[Index].RegIndex;
WrBuffer[1] = InitTable[Index].Value;
Status = I2cWriteData(&I2cLibInstance, WrBuffer, 2, IIC_SLAVE_ADDR);
if (Status != XST_SUCCESS) {
xil_printf("Si5324: Writing failed\n\r");
return XST_FAILURE;
}
}
return XST_SUCCESS;
}
#endif
#endif