Init Commit
This commit is contained in:
Jeremy Shen
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/*
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* Copyright (C) 2009 - 2019 Xilinx, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
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* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*
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*/
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#if __MICROBLAZE__ || __PPC__
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#include "arch/cc.h"
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#include "platform.h"
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#include "platform_config.h"
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#include "xil_cache.h"
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#include "xparameters.h"
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#include "xintc.h"
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#include "xil_exception.h"
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#include "lwip/tcp.h"
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#include "netif/xadapter.h"
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#ifdef STDOUT_IS_16550
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#include "xuartns550_l.h"
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#endif
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#include "lwip/tcp.h"
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#if LWIP_DHCP==1
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volatile int dhcp_timoutcntr = 24;
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void dhcp_fine_tmr();
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void dhcp_coarse_tmr();
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#endif
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volatile int TcpFastTmrFlag = 0;
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volatile int TcpSlowTmrFlag = 0;
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extern struct netif *echo_netif;
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void
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timer_callback()
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{
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static int DetectEthLinkStatus = 0;
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/* we need to call tcp_fasttmr & tcp_slowtmr at intervals specified by lwIP.
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* It is not important that the timing is absoluetly accurate.
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*/
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static int odd = 1;
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#if LWIP_DHCP==1
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static int dhcp_timer = 0;
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#endif
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DetectEthLinkStatus++;
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TcpFastTmrFlag = 1;
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odd = !odd;
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if (odd) {
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#if LWIP_DHCP==1
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dhcp_timer++;
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dhcp_timoutcntr--;
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#endif
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TcpSlowTmrFlag = 1;
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#if LWIP_DHCP==1
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dhcp_fine_tmr();
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if (dhcp_timer >= 120) {
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dhcp_coarse_tmr();
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dhcp_timer = 0;
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}
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#endif
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}
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/* For detecting Ethernet phy link status periodically */
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if (DetectEthLinkStatus == ETH_LINK_DETECT_INTERVAL) {
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eth_link_detect(echo_netif);
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DetectEthLinkStatus = 0;
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}
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}
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static XIntc intc;
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void platform_setup_interrupts()
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{
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XIntc *intcp;
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intcp = &intc;
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XIntc_Initialize(intcp, XPAR_INTC_0_DEVICE_ID);
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XIntc_Start(intcp, XIN_REAL_MODE);
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/* Start the interrupt controller */
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XIntc_MasterEnable(XPAR_INTC_0_BASEADDR);
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#ifdef __PPC__
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Xil_ExceptionInit();
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Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
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(XExceptionHandler)XIntc_DeviceInterruptHandler,
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(void*) XPAR_INTC_0_DEVICE_ID);
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#elif __MICROBLAZE__
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microblaze_register_handler((XInterruptHandler)XIntc_InterruptHandler, intcp);
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#endif
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platform_setup_timer();
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#ifdef XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK
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/* Enable timer and EMAC interrupts in the interrupt controller */
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XIntc_EnableIntr(XPAR_INTC_0_BASEADDR,
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#ifdef __MICROBLAZE__
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PLATFORM_TIMER_INTERRUPT_MASK |
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#endif
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XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK);
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#endif
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#ifdef XPAR_INTC_0_LLTEMAC_0_VEC_ID
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#ifdef __MICROBLAZE__
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XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR);
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#endif
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XIntc_Enable(intcp, XPAR_INTC_0_LLTEMAC_0_VEC_ID);
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#endif
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#ifdef XPAR_INTC_0_AXIETHERNET_0_VEC_ID
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XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR);
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XIntc_Enable(intcp, XPAR_INTC_0_AXIETHERNET_0_VEC_ID);
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#endif
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#ifdef XPAR_INTC_0_EMACLITE_0_VEC_ID
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#ifdef __MICROBLAZE__
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XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR);
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#endif
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XIntc_Enable(intcp, XPAR_INTC_0_EMACLITE_0_VEC_ID);
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#endif
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}
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void
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enable_caches()
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{
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#ifdef __PPC__
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Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
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Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
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#elif __MICROBLAZE__
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#ifdef XPAR_MICROBLAZE_USE_ICACHE
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Xil_ICacheEnable();
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#endif
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#ifdef XPAR_MICROBLAZE_USE_DCACHE
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Xil_DCacheEnable();
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#endif
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#endif
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}
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void
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disable_caches()
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{
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Xil_DCacheDisable();
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Xil_ICacheDisable();
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}
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void init_platform()
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{
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enable_caches();
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#ifdef STDOUT_IS_16550
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XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, 9600);
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XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
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#endif
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platform_setup_interrupts();
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}
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void cleanup_platform()
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{
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disable_caches();
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}
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#endif
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