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Jeremy Shen
2026-05-27 09:56:09 +00:00
commit ee3ede1152
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Debug_FW.sdk/calboard/.cproject
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Debug_FW.sdk/calboard/.project
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>calboard</name>
<comment>Created by SDK v2018.3. calboard_bsp - ps7_cortexa9_0</comment>
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Debug_FW.sdk/calboard/Debug/Xilinx.spec
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*startfile:
crti%O%s crtbegin%O%s
Debug_FW.sdk/calboard/Debug/calboard.elf
BIN
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Binary file not shown.
Debug_FW.sdk/calboard/Debug/calboard.elf.size
+2
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@@ -0,0 +1,2 @@
text data bss dec hex filename
132680 3184 5363760 5499624 53eae8 calboard.elf
Debug_FW.sdk/calboard/Debug/makefile
+65
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@@ -0,0 +1,65 @@
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
-include ../makefile.init
RM := rm -rf
# All of the sources participating in the build are defined here
-include sources.mk
-include src/subdir.mk
-include subdir.mk
-include objects.mk
ifneq ($(MAKECMDGOALS),clean)
ifneq ($(strip $(S_UPPER_DEPS)),)
-include $(S_UPPER_DEPS)
endif
ifneq ($(strip $(C_DEPS)),)
-include $(C_DEPS)
endif
endif
-include ../makefile.defs
# Add inputs and outputs from these tool invocations to the build variables
ELFSIZE += \
calboard.elf.size \
# All Target
all: pre-build main-build
# Main-build Target
main-build: calboard.elf secondary-outputs
# Tool invocations
calboard.elf: $(OBJS) ../src/lscript.ld $(USER_OBJS)
@echo 'Building target: $@'
@echo 'Invoking: ARM v7 gcc linker'
arm-none-eabi-gcc -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec -Wl,-T -Wl,../src/lscript.ld -L../../calboard_bsp/ps7_cortexa9_0/lib -o "calboard.elf" $(OBJS) $(USER_OBJS) $(LIBS)
@echo 'Finished building target: $@'
@echo ' '
calboard.elf.size: calboard.elf
@echo 'Invoking: ARM v7 Print Size'
arm-none-eabi-size calboard.elf |tee "calboard.elf.size"
@echo 'Finished building: $@'
@echo ' '
# Other Targets
clean:
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-@echo ' '
pre-build:
-a9-linaro-pre-build-step
-@echo ' '
secondary-outputs: $(ELFSIZE)
.PHONY: all clean dependents
.SECONDARY: main-build pre-build
-include ../makefile.targets
Debug_FW.sdk/calboard/Debug/objects.mk
+8
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@@ -0,0 +1,8 @@
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
USER_OBJS :=
LIBS := -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxil,-llwip4,-lgcc,-lc,--end-group
Debug_FW.sdk/calboard/Debug/sources.mk
+20
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@@ -0,0 +1,20 @@
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
LD_SRCS :=
OBJ_SRCS :=
S_SRCS :=
C_SRCS :=
S_UPPER_SRCS :=
O_SRCS :=
EXECUTABLES :=
OBJS :=
S_UPPER_DEPS :=
C_DEPS :=
ELFSIZE :=
# Every subdirectory with source files must be described here
SUBDIRS := \
src \
Debug_FW.sdk/calboard/Debug/src/GPIO_Driv.d
+45
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@@ -0,0 +1,45 @@
src/GPIO_Driv.o src/GPIO_Driv.o: ../src/GPIO_Driv.c ../src/GPIO_Driv.h \
../../calboard_bsp/ps7_cortexa9_0/include/xgpiops.h \
../../calboard_bsp/ps7_cortexa9_0/include/xstatus.h \
../../calboard_bsp/ps7_cortexa9_0/include/xil_types.h \
../../calboard_bsp/ps7_cortexa9_0/include/xil_assert.h \
../../calboard_bsp/ps7_cortexa9_0/include/xgpiops_hw.h \
../../calboard_bsp/ps7_cortexa9_0/include/xil_io.h \
../../calboard_bsp/ps7_cortexa9_0/include/xil_printf.h \
../../calboard_bsp/ps7_cortexa9_0/include/xparameters.h \
../../calboard_bsp/ps7_cortexa9_0/include/xparameters_ps.h \
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../src/GPIO_Driv.h:
../../calboard_bsp/ps7_cortexa9_0/include/xgpiops.h:
../../calboard_bsp/ps7_cortexa9_0/include/xstatus.h:
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Debug_FW.sdk/calboard/Debug/src/GPIO_Driv.o
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Debug_FW.sdk/calboard/Debug/src/SPI_Driv.d
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src/SPI_Driv.o src/SPI_Driv.o: ../src/SPI_Driv.c ../src/SPI_Driv.h \
../../calboard_bsp/ps7_cortexa9_0/include/sleep.h \
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../src/SPI_Driv.h:
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Debug_FW.sdk/calboard/Debug/src/SPI_Driv.o
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Debug_FW.sdk/calboard/Debug/src/cal_meas.d
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src/cal_meas.o src/cal_meas.o: ../src/cal_meas.c ../src/cal_meas.h \
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../src/SPI_Driv.h ../src/GPIO_Driv.h
../src/cal_meas.h:
../../calboard_bsp/ps7_cortexa9_0/include/sleep.h:
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../src/SPI_Driv.h:
../src/GPIO_Driv.h:
Debug_FW.sdk/calboard/Debug/src/cal_meas.o
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Debug_FW.sdk/calboard/Debug/src/crc16.d
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src/crc16.o src/crc16.o: ../src/crc16.c ../src/crc16.h
../src/crc16.h:
Debug_FW.sdk/calboard/Debug/src/crc16.o
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Debug_FW.sdk/calboard/Debug/src/dna_read.d
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src/dna_read.o src/dna_read.o: ../src/dna_read.c ../src/dna_read.h \
../../calboard_bsp/ps7_cortexa9_0/include/xil_io.h \
../../calboard_bsp/ps7_cortexa9_0/include/xil_types.h \
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../src/dna_read.h:
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../../calboard_bsp/ps7_cortexa9_0/include/xparameters.h:
Debug_FW.sdk/calboard/Debug/src/dna_read.o
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Debug_FW.sdk/calboard/Debug/src/echo.d
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src/echo.o src/echo.o: ../src/echo.c ../src/dna_read.h ../src/crc16.h \
../src/GPIO_Driv.h ../../calboard_bsp/ps7_cortexa9_0/include/xgpiops.h \
../../calboard_bsp/ps7_cortexa9_0/include/xstatus.h \
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../src/SPI_Driv.h ../../calboard_bsp/ps7_cortexa9_0/include/sleep.h \
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../src/dna_read.h:
../src/crc16.h:
../src/GPIO_Driv.h:
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Debug_FW.sdk/calboard/Debug/src/echo.o
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Debug_FW.sdk/calboard/Debug/src/i2c_access.d
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src/i2c_access.o src/i2c_access.o: ../src/i2c_access.c \
../../calboard_bsp/ps7_cortexa9_0/include/xparameters.h \
../../calboard_bsp/ps7_cortexa9_0/include/xparameters_ps.h
../../calboard_bsp/ps7_cortexa9_0/include/xparameters.h:
../../calboard_bsp/ps7_cortexa9_0/include/xparameters_ps.h:
Debug_FW.sdk/calboard/Debug/src/i2c_access.o
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Debug_FW.sdk/calboard/Debug/src/iic_phyreset.d
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src/iic_phyreset.o src/iic_phyreset.o: ../src/iic_phyreset.c \
../../calboard_bsp/ps7_cortexa9_0/include/xparameters.h \
../../calboard_bsp/ps7_cortexa9_0/include/xparameters_ps.h \
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../../calboard_bsp/ps7_cortexa9_0/include/xil_printf.h:
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../../calboard_bsp/ps7_cortexa9_0/include/xparameters.h:
../../calboard_bsp/ps7_cortexa9_0/include/bspconfig.h:
Debug_FW.sdk/calboard/Debug/src/iic_phyreset.o
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Debug_FW.sdk/calboard/Debug/src/main.d
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src/main.o src/main.o: ../src/main.c \
../../calboard_bsp/ps7_cortexa9_0/include/xparameters.h \
../../calboard_bsp/ps7_cortexa9_0/include/xparameters_ps.h \
../../calboard_bsp/ps7_cortexa9_0/include/netif/xadapter.h \
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../../calboard_bsp/ps7_cortexa9_0/include/netif/xtopology.h \
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../src/platform_config.h \
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Debug_FW.sdk/calboard/Debug/src/main.o
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Debug_FW.sdk/calboard/Debug/src/platform_zynq.o
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../../calboard_bsp/ps7_cortexa9_0/include/lwip/netif.h:
../../calboard_bsp/ps7_cortexa9_0/include/lwip/stats.h:
../../calboard_bsp/ps7_cortexa9_0/include/lwip/memp.h:
../../calboard_bsp/ps7_cortexa9_0/include/lwip/priv/memp_std.h:
../../calboard_bsp/ps7_cortexa9_0/include/lwip/priv/memp_priv.h:
../../calboard_bsp/ps7_cortexa9_0/include/lwip/priv/mem_priv.h:
../../calboard_bsp/ps7_cortexa9_0/include/lwip/ip4.h:
../../calboard_bsp/ps7_cortexa9_0/include/lwip/prot/ip4.h:
../../calboard_bsp/ps7_cortexa9_0/include/lwip/ip6.h:
../../calboard_bsp/ps7_cortexa9_0/include/lwip/prot/ip.h:
../../calboard_bsp/ps7_cortexa9_0/include/lwip/icmp.h:
../../calboard_bsp/ps7_cortexa9_0/include/lwip/prot/icmp.h:
../../calboard_bsp/ps7_cortexa9_0/include/xil_printf.h:
../src/platform.h:
../src/platform_config.h:
../../calboard_bsp/ps7_cortexa9_0/include/netif/xadapter.h:
../../calboard_bsp/ps7_cortexa9_0/include/netif/xtopology.h:
../../calboard_bsp/ps7_cortexa9_0/include/xil_types.h:
Debug_FW.sdk/calboard/Debug/src/platform_zynqmp.o
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Debug_FW.sdk/calboard/Debug/src/sfp.d
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src/sfp.o src/sfp.o: ../src/sfp.c \
../../calboard_bsp/ps7_cortexa9_0/include/xparameters.h \
../../calboard_bsp/ps7_cortexa9_0/include/xparameters_ps.h
../../calboard_bsp/ps7_cortexa9_0/include/xparameters.h:
../../calboard_bsp/ps7_cortexa9_0/include/xparameters_ps.h:
Debug_FW.sdk/calboard/Debug/src/sfp.o
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Debug_FW.sdk/calboard/Debug/src/si5324.d
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src/si5324.o src/si5324.o: ../src/si5324.c \
../../calboard_bsp/ps7_cortexa9_0/include/xparameters.h \
../../calboard_bsp/ps7_cortexa9_0/include/xparameters_ps.h
../../calboard_bsp/ps7_cortexa9_0/include/xparameters.h:
../../calboard_bsp/ps7_cortexa9_0/include/xparameters_ps.h:
Debug_FW.sdk/calboard/Debug/src/si5324.o
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Debug_FW.sdk/calboard/Debug/src/subdir.mk
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################################################################################
# Automatically-generated file. Do not edit!
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
LD_SRCS += \
../src/lscript.ld
C_SRCS += \
../src/GPIO_Driv.c \
../src/SPI_Driv.c \
../src/cal_meas.c \
../src/crc16.c \
../src/dna_read.c \
../src/echo.c \
../src/i2c_access.c \
../src/iic_phyreset.c \
../src/main.c \
../src/platform.c \
../src/platform_mb.c \
../src/platform_ppc.c \
../src/platform_zynq.c \
../src/platform_zynqmp.c \
../src/sfp.c \
../src/si5324.c
OBJS += \
./src/GPIO_Driv.o \
./src/SPI_Driv.o \
./src/cal_meas.o \
./src/crc16.o \
./src/dna_read.o \
./src/echo.o \
./src/i2c_access.o \
./src/iic_phyreset.o \
./src/main.o \
./src/platform.o \
./src/platform_mb.o \
./src/platform_ppc.o \
./src/platform_zynq.o \
./src/platform_zynqmp.o \
./src/sfp.o \
./src/si5324.o
C_DEPS += \
./src/GPIO_Driv.d \
./src/SPI_Driv.d \
./src/cal_meas.d \
./src/crc16.d \
./src/dna_read.d \
./src/echo.d \
./src/i2c_access.d \
./src/iic_phyreset.d \
./src/main.d \
./src/platform.d \
./src/platform_mb.d \
./src/platform_ppc.d \
./src/platform_zynq.d \
./src/platform_zynqmp.d \
./src/sfp.d \
./src/si5324.d
# Each subdirectory must supply rules for building sources it contributes
src/%.o: ../src/%.c
@echo 'Building file: $<'
@echo 'Invoking: ARM v7 gcc compiler'
arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"$@" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<"
@echo 'Finished building: $<'
@echo ' '
Debug_FW.sdk/calboard/bootimage/calboard.bif
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//arch = zynq; split = false; format = BIN
the_ROM_image:
{
[bootloader]E:\CALBOARD\z035_mars1k\bin\bin_11.13\FSBL.elf
E:\CALBOARD\z035_mars1k\bin\bin_11.13\system_wrapper.bit
E:\CALBOARD\z035_mars1k\bin\bin_11.13\calboard.elf
}
Debug_FW.sdk/calboard/src/GPIO_Driv.c
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/*
* GPIO_Driv.c
*
* Created on: 2021年5月7日
* Author: Administrator
*/
#include "GPIO_Driv.h"
XGpioPs psGpioInstancePtr; //端口
XGpioPs_Config* GpioConfigPtr; //设备ID
//sck,cs,sdi,sdo,rst
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
void EMIO_config(void)
{
int xStatus;
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
if(GpioConfigPtr == NULL)
return XST_FAILURE;
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
if(XST_SUCCESS != xStatus)
print(" PS GPIO INIT FAILED \n\r");
/*-------------------------------------CPLD_U1------------------------------------*/
//--设置EMIO方向
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---cs
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---sdi
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 0);//57---sdo
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 1);//58---rst_n
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
//使能EMIO输出 1=output 0=input
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---cs
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---sdi
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);//57---sdo
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);//58---rst_n
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//59
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//60
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//61
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//62
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//63
/*-------------------------------------CPLD_U2------------------------------------*/
//--设置EMIO方向
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---cs
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---sdi
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//68---sdo
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//69---rst_n
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//70
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//71
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//72
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//73
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//74
//使能EMIO输出 1=output 0=input
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---cs
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---sdi
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);//68---sdo
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);//69---rst_n
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);//70
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);//71
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);//72
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);//73
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);//74
/*-------------------------------------CPLD_U3------------------------------------*/
//--设置EMIO方向
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//76---sck
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//77---cs
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//78---sdi
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 0);//79---sdo
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 1);//80---rst_n
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//81
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//82
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//83
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//84
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//85
//使能EMIO输出 1=output 0=input
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//76---sck
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//77---cs
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//78---sdi
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 0);//79---sdo
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 1);//80---rst_n
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);//81
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);//82
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);//83
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);//84
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);//85
}
Debug_FW.sdk/calboard/src/GPIO_Driv.h
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/*
* GPIO_Driv.h
*
* Created on: 2021Äê4ÔÂ2ÈÕ
* Author: dell
*/
#ifndef SRC_GPIO_DRIV_H_
#define SRC_GPIO_DRIV_H_
#include "stdio.h"
#include "xgpiops.h"
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
extern u32 CPLD_U1[11];
extern u32 CPLD_U2[11];
extern u32 CPLD_U3[11];
void EMIO_config(void);
#endif /* SRC_GPIO_DRIV_H_ */
Debug_FW.sdk/calboard/src/README.txt
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lwIP Echo Server
----------------
The lwIP Echo server application starts an echo server at port 7. Any data sent to
this port is simply echoed back.
By default, the program assigns the following settings to the board:
IP Address: 192.168.1.10
Netmask : 255.255.255.0
Gateway : 192.168.1.1
MAC address: 00:0a:35:00:01:02
These settings can be changed in the file main.c.
The main echo server logic is present in the file echo.c.
platform.c implements certain processor and platform dependent functions.
The file platform_config.h is generated based on the hardware design. It makes two
assumptions: The timer has its interrupt line connected to the interrupt controller,
and all the ethernet peripherals (xps_ethernetlite or xps_ll_temac) accessible from
the processor can be used with lwIP.
Running the Echo Server example
-------------------------------
To connect and test the echo server, download and run the program on the board,
and then issue the following command from your host machine:
$ telnet 192.168.1.10 7
Trying 192.168.1.10...
Connected to 192.168.1.10.
Escape character is '^]'.
hello world
hello world
all messages will be echo'ed back
all messages will be echo'ed back
^]
telnet> quit
Connection closed.
$
lwIPv6 Echo Server
----------------
The lwIPv6 Echo server application starts an echo server at port 7. Any data sent to
this port is simply echoed back.
By default, the program assigns the following settings to the board:
IPv6 address: FE80:0:0:0:20A:35FF:FE00:102
MAC address: 00:0a:35:00:01:02
These settings can be changed in the file main.c.
The main echo server logic is present in the file echo.c.
platform.c implements certain processor and platform dependent functions.
The file platform_config.h is generated based on the hardware design. It makes two
assumptions: The timer has its interrupt line connected to the interrupt controller,
and all the ethernet peripherals (xps_ethernetlite or xps_ll_temac) accessible from
the processor can be used with lwIP.
Running the Echo Server example
-------------------------------
To connect and test the echo server, download and run the program on the board,
and then issue the following command from your host machine:
$ telnet -6 FE80:0:0:0:20A:35FF:FE00:102%eth1 7
Trying fe80::20a:35ff:fe00:102%eth1...
Connected to FE80:0:0:0:20A:35FF:FE00:102%eth1.
Escape character is '^]'.
hello world
hello world
all messages will be echo'ed back
all messages will be echo'ed back
^]
telnet> quit
Connection closed.
$
References
----------
More details regarding the echo server can be obtained from Xilinx XAPP 1026:
http://www.xilinx.com/support/documentation/application_notes/xapp1026.pdf
Debug_FW.sdk/calboard/src/SPI_Driv.c
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/*
* SPI_Driv.c
*
* Created on: 2021年4月2日
* Author: dell
*/
#include "SPI_Driv.h"
XGpioPs psGpioInstancePtr; //端口
XGpioPs_Config* GpioConfigPtr; //设备ID
extern u32 K7_U0[16];
extern u32 molex_4_bank_3[4];
extern u32 cs_en_bank_3[4];
/******************************************************************************
* Function : void interface_initial(u32* device,u32 num_wire)
* Description : interface initial
* Parameter : device -- CPLD
* num_wire -- 复位线编号
* Return : void
******************************************************************************/
void interface_initial(u32* device) //wire_num = cs sck sdi/o
{
u32 sck = *(device+0);
u32 cs = *(device+1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
}
/******************************************************************************
* Function : void rst_CPLD(u32* device,u32 num_wire)
* Description : CPLD reset
* Parameter : device -- CPLD
* num_wire -- 复位线编号
* Return : void
******************************************************************************/
void rst_CPLD(u32* device,u32 num_wire) //wire_num = cs sck sdi/o
{
u32 rst_n = *(device+num_wire);
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
usleep(2);
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
}
/******************************************************************************
* Function : void spi_write_onewire(char addr, u32 data, char width, u32* device)
* Description : spi onewire write
* Parameter : addr -- 地址
* data -- 数据
* width -- 数据长度
* device -- CPLD
* Return : void
******************************************************************************/
void spi_write_onewire(char addr, char *data, char width, u32* device)
{
char temp_addr = 0;
//u32 temp_data = 0;
u32 temp_data = 0;
char i = 0,j=0;
u32 sck = *(device+0);
u32 cs= *(device+1);
u32 sdi= *(device+2);
temp_addr = addr;
///temp_data = data;
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
//XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); // w/r标志位 1=w 0=r
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
for(i = 0; i < 8; i++) // 8bit地址
{
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
if(temp_addr&0x80)
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据 数据从中间变量到通信线上
else
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
temp_addr = temp_addr<<1; //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
}
for(j=0;j<width;j++)
{
temp_data = *(data+j);
for(i = 0; i < 8; i++) //nbit数据
{
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
if(temp_data&0x80) //注意数据位nbit，要从[n-1]取位
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1);
else
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
temp_data <<= 1;
}
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
}
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs , 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
}
/******************************************************************************
* Function : u32 spi_read_onewire(char addr, char width, u32* device)
* Description : spi onewire read
* Parameter : addr -- 地址
* data -- 数据
* width -- 数据长度
* device -- CPLD
* Return : void
******************************************************************************/
u32 spi_read_onewire(char addr, char width, u32* device,char* read_data)
{
char temp_addr=0;
u32 temp_data=0;
char i=0,j=0;
u32 sck = *(device+0);
u32 cs= *(device+1);
u32 sdi= *(device+2);
u32 sdo= *(device+3);
temp_addr = addr;
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
//XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0); // w/r标志位 1=w 0=r
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
for(i = 0; i < 8; i++) // 8bit地址
{
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
if(temp_addr&0x80)
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据 数据从中间变量到通信线上
else
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
temp_addr = temp_addr<<1; //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
}
for(j=0; j<width; j++)
{
for(i = 0; i < 8; i++) //nbit数据
{
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
temp_data = temp_data << 1; //sck低电平准备数据 准备好数位，此时的数据相当于从右边的FPGA移进MCU(先准备好中间变量)
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
if(XGpioPs_ReadPin(&psGpioInstancePtr,sdo)) //sck高电平接收数据 数据匹配到准备好的数位，等待一起传递到MCU
temp_data = temp_data| 0x00000001;
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
}
}
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
read_data[0] = (u8)(temp_data>>16);
read_data[1] = (u8)(temp_data>>8);
read_data[0] = (u8)(temp_data);
return temp_data;
}
/******************************************************************************
* Function : void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
* Description : forwire write to reg
* Parameter : txdata--数据
* sdi0,sdi1,sdi2,sdi3--IO
* Return : void
******************************************************************************/
void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
{
switch(txdata & 0x0F)
{
case 0x00:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x01:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x02:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x03:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x04:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x05:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x06:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x07:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
break;
}
case 0x08:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
case 0x09:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
case 0x0A:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
case 0x0B:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
case 0x0C:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
case 0x0D:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
case 0x0E:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
case 0x0F:
{
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
break;
}
}
}
/******************************************************************************
* Function : void spi_write_fourwire(char addr, u16 data, u32* device)
* Description : spi fourwire write
* Parameter : addr -- 地址
* data -- 数据
* width -- 数据长度
* device -- CPLD
* Return : void
******************************************************************************/
void spi_write_fourwire(char addr, u16 data, u32* device)
{
u8 temp_addr = 0;
u16 temp_data = 0;
u8 split_addr[2] = {0}; //将8bit地址拆分，分别给4线传输，
u8 split_data[4] = {0}; //16bit数据拆成4个4bit
u8 i;
u32 sck = *(device+0);
u32 cs = *(device+1);
u32 sdi0 = *(device+2);
u32 sdi1 = *(device+3);
u32 sdi2 = *(device+4);
u32 sdi3 = *(device+5);
temp_addr = addr;
temp_data = data;
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
fourwire_write(0x01,sdi0,sdi1,sdi2,sdi3); // w/r标志位 1=w 0=r
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
for(i = 0; i < 2;i++) // 8bit地址 四根线分两次传输
{
split_addr[i] = (temp_addr>>(4*(1-i)))&0x0F; //sck高电平准备数据 数据从MCU到中间变量上
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
fourwire_write(split_addr[i],sdi0,sdi1,sdi2,sdi3); //sck低电平传输数据 数据从中间变量到通信线上
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
}
for(i = 0; i < 4;i++) //16bit数据 4根线分四次传输
{
split_data[i] = (temp_data>>(4*(3-i)))&0x0F;
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
fourwire_write(split_data[i],sdi0,sdi1,sdi2,sdi3);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
}
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
fourwire_write(0x00,sdi0,sdi1,sdi2,sdi3);
//usleep(20);
}
/******************************************************************************
* Function : u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
* Description : forwire read from reg
* Parameter : sdo0,sdo1,sdo2,sdo3--IO
* Return : rxdata--数据
******************************************************************************/
u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
{
u32 GPIO_PIN[4];
u16 rdata[4];
u16 rxdata = 0;
GPIO_PIN[0] = sdo0;
GPIO_PIN[1] = sdo1;
GPIO_PIN[2] = sdo2;
GPIO_PIN[3] = sdo3;
for(u8 i = 0; i < 4 ; i++)
{
rdata[i] = XGpioPs_ReadPin(&psGpioInstancePtr,GPIO_PIN[i]);
//xil_printf("rdata[i] = %x\r\n",rdata[i]);
rxdata = ((rdata[i])<<i) + rxdata ;
}
return rxdata;
}
/******************************************************************************
* Function : void spi_read_fourwire(char addr, u16* rxdata, u32* device)
* Description : spi fourwire read
* Parameter : addr -- 地址
* rxdata -- 数据
* device -- CPLD
* Return : void
******************************************************************************/
void spi_read_fourwire(char addr, u16* rxdata, u32* device) //接收数据使用指针传递，方便接收多个
{
u8 temp_addr = 0;
u16 temp_data = 0;
u8 split_addr[2] = {0}; //将8bit地址拆分，分别给4线传输，
u16 split_data[4] = {0}; //16bit数据拆成4个4bit
u8 i = 0;
u32 sck = *(device+0);
u32 cs = *(device+1);
u32 sdio0 = *(device+2);
u32 sdio1 = *(device+3);
u32 sdio2 = *(device+4);
u32 sdio3 = *(device+5);
temp_addr = addr;
split_addr[0] = (temp_addr >> 4)&0x0F;
split_addr[1] = (temp_addr)&0x0F;
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3); // w/r标志位 1=w 0=r
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
for(i = 0; i < 2; i++) // 8bit地址 四根线分两次传输
{
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
fourwire_write(split_addr[i],sdio0,sdio1,sdio2,sdio3); //sck低电平传输数据 数据从中间变量到通信线上
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
}
for(i = 0; i < 4; i++)
{
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),0); //input
}
for(i = 0; i < 4; i++) //16bit数据 4根线分四次接收
{
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
split_data[i] = fourwire_read(sdio0,sdio1,sdio2,sdio3); //sck低电平准备数据 数据从通信线到中间变量上
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
temp_data = temp_data<<4;
temp_data = temp_data + split_data[i];
//temp_data = (split_data[i]<<(4*(3-i))) + temp_data; //sck高电平接收数据 数据从中间变量到MCU上
// xil_printf("split_data[i],temp_data = %x,%x\r\n",split_data[i],temp_data);
}
for(i = 0; i < 4; i++)
{
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),1); //output
}
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3);
*rxdata = temp_data;
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);//add 2 lines
//usleep(20);
}
/******************************************************************************
* Function : void GPIO_dir_set(u32* device,char dir)
* Description : change GPIO direction
* Parameter : device -- CPLD
* dir -- GPIO_OUT/GPIO_IN
* Return : void
******************************************************************************/
void GPIO_dir_set_16(u32* device,char dir)
{
u32 sdio[16] = {0};
u8 i;
for(i = 0; i < 16;i++)
{
sdio[i] = *(device+i);
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, sdio[i],1);
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir);
}
}
void GPIO_dir_set_cs_enable(u32* device,u8 dir)
{
u32 sdio[4] = {0};
u8 i;
u8 dir_temp = 0;
for(i = 0; i < 4;i++)
{
sdio[i] = *(device+i);
dir_temp = (((dir >> (3-i))) & 0x01);
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir_temp);
}
}
void rst(char *d)
{
XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
XGpioPs_WritePin(&psGpioInstancePtr, *d, 1);
usleep(20);
XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
}
void func_test(void)
{
XGpioPs_Write(&psGpioInstancePtr, 0x03, 0x12345678);
}
Debug_FW.sdk/calboard/src/SPI_Driv.h
+47
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/*
* SPI_Driv.h
*
* Created on: 2021Äê4ÔÂ2ÈÕ
* Author: dell
*/
#ifndef SRC_SPI_DRIV_H_
#define SRC_SPI_DRIV_H_
#include "sleep.h"
#include "stdio.h"
#include "xgpiops.h"
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
#define wr_flag 1
#define rd_flag 0
#define GPIO_OUT 1
#define GPIO_IN 0
#define NUM_SCK_CMD 4
#define NUM_SCK_ADDR 8
#define NUM_SCK_LENGTH 4
#define NUM_SCK_ENABLE 8
#define NUM_SCK_BYTE 2
void interface_initial(u32* device);
void rst_CPLD(u32* device,u32 num_wire);
void rst(char *d);
void spi_write_onewire(char addr, char *data, char width, u32* device);
u32 spi_read_onewire(char addr,char width,u32* device,char* read_data);
void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3);
u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3);
void spi_write_fourwire(char addr,u16 data,u32* device);
void spi_read_fourwire(char addr,u16* rxdata,u32* device);
void GPIO_dir_set_16(u32* device,char dir);
void GPIO_dir_set_cs_enable(u32* device,u8 dir);
#endif /* SRC_SPI_DRIV_H_ */
Debug_FW.sdk/calboard/src/Xilinx.spec
+2
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@@ -0,0 +1,2 @@
*startfile:
crti%O%s crtbegin%O%s
Debug_FW.sdk/calboard/src/cal_meas.c
+255
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/*
* cal_meas.c
*
* Created on: 2023Äê7ÔÂ19ÈÕ
* Author: dell
*/
#include "cal_meas.h"
#include "SPI_Driv.h"
char sw_config_data[3] = {0x00,0x00,0x00};
void sw_config(char *slot_start)
{
char slot = (*slot_start);
char m_fun = *(slot_start+1);
char ch_num_h = *(slot_start+2);
char ch_num_l = *(slot_start+3);
char volt_cur = *(slot_start+4);
char load = *(slot_start+5);
char memt_areal = *(slot_start+6);
u16 ch_num = 0;
u32 ch_num_dat = 0;
u32 relay_ctrl = 0;
u32 slot_en = 0x00000001;
u8 cpld_addr = 0;
u32 cpld_dat = 0;
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
if(slot==1)
{
cpld_addr = 0x82;
}
else if(slot==2)
{
cpld_addr = 0x83;
}
else if(slot==3)
{
cpld_addr = 0x84;
}
else
{
cpld_addr = 0x85;
}
switch(ch_num)
{
case 0x0001:
{
relay_ctrl = 0x00000000;
break;
}
case 0x0002:
{
relay_ctrl = 0x00020000;
break;
}
case 0x0003:
{
relay_ctrl = 0x00200000;
break;
}
case 0x0004:
{
relay_ctrl = 0x00220000;
break;
}
case 0x0005:
{
relay_ctrl = 0x00800000;
break;
}
case 0x0006:
{
relay_ctrl = 0x00810000;
break;
}
case 0x0007:
{
relay_ctrl = 0x00A00000;
break;
}
case 0x0008:
{
relay_ctrl = 0x00A10000;
break;
}
case 0x0041:
{
relay_ctrl = 0x00000000;
break;
}
case 0x0042:
{
relay_ctrl = 0x00008000;
break;
}
case 0x0043:
{
relay_ctrl = 0x00100000;
break;
}
case 0x0044:
{
relay_ctrl = 0x00108000;
break;
}
case 0x0045:
{
relay_ctrl = 0x00800000;
break;
}
case 0x0046:
{
relay_ctrl = 0x00804000;
break;
}
case 0x0047:
{
relay_ctrl = 0x00900000;
break;
}
case 0x0048:
{
relay_ctrl = 0x00904000;
break;
}
case 0x0081:
{
relay_ctrl = 0x00000000;
break;
}
case 0x0082:
{
relay_ctrl = 0x00002000;
break;
}
case 0x0083:
{
relay_ctrl = 0x00080000;
break;
}
case 0x0084:
{
relay_ctrl = 0x00082000;
break;
}
case 0x0085:
{
relay_ctrl = 0x00400000;
break;
}
case 0x0086:
{
relay_ctrl = 0x00401000;
break;
}
case 0x0087:
{
relay_ctrl = 0x00480000;
break;
}
case 0x0088:
{
relay_ctrl = 0x00481000;
break;
}
case 0x00C1:
{
relay_ctrl = 0x00000000;
break;
}
case 0x00C2:
{
relay_ctrl = 0x00000800;
break;
}
case 0x00C3:
{
relay_ctrl = 0x00040000;
break;
}
case 0x00C4:
{
relay_ctrl = 0x00040800;
break;
}
case 0x00C5:
{
relay_ctrl = 0x00400000;
break;
}
case 0x00C6:
{
relay_ctrl = 0x00400400;
break;
}
case 0x00C7:
{
relay_ctrl = 0x00440000;
break;
}
case 0x00C8:
{
relay_ctrl = 0x00440400;
break;
}
}
ch_num_dat = ((u32)ch_num)<<1;
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
sw_config_data[0] = (u8)(cpld_dat>>16);
sw_config_data[1] = (u8)(cpld_dat>>8);
sw_config_data[2] = (u8)(cpld_dat);
xil_printf("relay_ctrl: %d\n\r", relay_ctrl);
xil_printf("ch_num_dat: %d\n\r", ch_num_dat);
xil_printf("cpld_addr: %d\n\r", cpld_addr);
xil_printf("cpld_dat: %d\n\r", cpld_dat);
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[0]);
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[1]);
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[2]);
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
sw_config_data[0] = 0x00;
sw_config_data[1] = 0x00;
sw_config_data[2] = 0x01;
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U1);
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U2);
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U3);
slot_en = 0x00000000;
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
sw_config_data[0] = (u8)(cpld_dat>>16);
sw_config_data[1] = (u8)(cpld_dat>>8);
sw_config_data[2] = (u8)(cpld_dat);
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
}
Debug_FW.sdk/calboard/src/cal_meas.c.bak
+413
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/*
* cal_meas.c
*
* Created on: 2023Äê7ÔÂ19ÈÕ
* Author: dell
*/
#include "cal_meas.h"
#include "SPI_Driv.h"
char sw_config_data[2] = {0xFF,0xFF};
void sw_init( void )
{
//reg addr(cpld_u1)
spi_write_onewire(U1_SW_FC_DV0, sw_config_data, dat_width, CPLD_U1);//1
spi_write_onewire(U1_SW_FC_DV1, sw_config_data, dat_width, CPLD_U1);//2
spi_write_onewire(U1_SW_FC_DV2, sw_config_data, dat_width, CPLD_U1);//3
spi_write_onewire(U1_SW_FC_DV3, sw_config_data, dat_width, CPLD_U1);//4
spi_write_onewire(U1_SW_SC_DV0, sw_config_data, dat_width, CPLD_U1);//5
spi_write_onewire(U1_SW_SC_DV1, sw_config_data, dat_width, CPLD_U1);//6
spi_write_onewire(U1_SW_SC_DV2, sw_config_data, dat_width, CPLD_U1);//7
spi_write_onewire(U1_SW_SC_DV3, sw_config_data, dat_width, CPLD_U1);//8
spi_write_onewire(U1_SW_OC_DV0, sw_config_data, dat_width, CPLD_U1);//9
spi_write_onewire(U1_SW_OC_DV1, sw_config_data, dat_width, CPLD_U1);//10
spi_write_onewire(U1_SW_OC_DV2, sw_config_data, dat_width, CPLD_U1);//11
spi_write_onewire(U1_SW_OC_DV3, sw_config_data, dat_width, CPLD_U1);//12
spi_write_onewire(U1_SW_OC_DV4, sw_config_data, dat_width, CPLD_U1);//13
spi_write_onewire(U1_SW_OC_DV5, sw_config_data, dat_width, CPLD_U1);//14
spi_write_onewire(U1_SW_OC_DV6, sw_config_data, dat_width, CPLD_U1);//15
spi_write_onewire(U1_SW_OC_DV7, sw_config_data, dat_width, CPLD_U1);//16
spi_write_onewire(U1_SW_FMC_SMC, sw_config_data, dat_width, CPLD_U1);//17
spi_write_onewire(U1_SW_OC_DMM, sw_config_data, dat_width, CPLD_U1);//18
spi_write_onewire(U1_SW_MMC, sw_config_data, dat_width, CPLD_U1);//19
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);//20
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);//21
spi_write_onewire(U1_SW_RL1, sw_config_data, dat_width, CPLD_U1);//22
spi_write_onewire(U1_SW_RL2, sw_config_data, dat_width, CPLD_U1);//23
spi_write_onewire(U1_SW_LOFS_VPK, sw_config_data, dat_width, CPLD_U1);//24
spi_write_onewire(U1_SW_LOFS_APK, sw_config_data, dat_width, CPLD_U1);//25
//reg addr(cpld_u2)
spi_write_onewire(U2_SW_FC_DV0, sw_config_data, dat_width, CPLD_U2);//1
spi_write_onewire(U2_SW_FC_DV1, sw_config_data, dat_width, CPLD_U2);//2
spi_write_onewire(U2_SW_FC_DV2, sw_config_data, dat_width, CPLD_U2);//3
spi_write_onewire(U2_SW_FC_DV3, sw_config_data, dat_width, CPLD_U2);//4
spi_write_onewire(U2_SW_SC_DV0, sw_config_data, dat_width, CPLD_U2);//5
spi_write_onewire(U2_SW_SC_DV1, sw_config_data, dat_width, CPLD_U2);//6
spi_write_onewire(U2_SW_SC_DV2, sw_config_data, dat_width, CPLD_U2);//7
spi_write_onewire(U2_SW_SC_DV3, sw_config_data, dat_width, CPLD_U2);//8
spi_write_onewire(U2_SW_OC_DV0, sw_config_data, dat_width, CPLD_U2);//9
spi_write_onewire(U2_SW_OC_DV1, sw_config_data, dat_width, CPLD_U2);//10
spi_write_onewire(U2_SW_OC_DV2, sw_config_data, dat_width, CPLD_U2);//11
spi_write_onewire(U2_SW_OC_DV3, sw_config_data, dat_width, CPLD_U2);//12
spi_write_onewire(U2_SW_OC_DV4, sw_config_data, dat_width, CPLD_U2);//13
spi_write_onewire(U2_SW_OC_DV5, sw_config_data, dat_width, CPLD_U2);//14
spi_write_onewire(U2_SW_OC_DV6, sw_config_data, dat_width, CPLD_U2);//15
spi_write_onewire(U2_SW_OC_DV7, sw_config_data, dat_width, CPLD_U2);//16
}
void sw_config(char *slot_start)
{
char slot = (*slot_start);
char m_fun = *(slot_start+1);
char ch_num_h = *(slot_start+2);
char ch_num_l = *(slot_start+3);
char volt_cur = *(slot_start+4);
char load = *(slot_start+5);
char memt_areal = *(slot_start+6);
u16 u1_io_rc_dat = 0;
u16 u1_rc_dat = 0;
u16 u1_lofs_vpk_dat = 0;
u16 u1_lofs_apk_dat = 0;
u16 u1_lofs_vpk_apk_dat = 0;
u16 ch_num = 0;
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
//xil_printf("slot: %d\n\r", slot);
//xil_printf("m_fun: %d\n\r", m_fun);
//xil_printf("ch_num: %d\n\r", ch_num);
fsc_oc_config(slot,m_fun,ch_num);
if(m_fun==0x04)
{
dmm_config(slot,ch_num);
//xil_printf("memt_areal: %d\n\r", memt_areal);
if(memt_areal==0x01)
{
u1_io_rc_dat = 0xFFFE;
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
sw_config_data[1] = (u8)(u1_io_rc_dat);
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
}
else
{
u1_rc_dat = 0xFFFE;
sw_config_data[0] = (u8)(u1_rc_dat>>8);
sw_config_data[1] = (u8)(u1_rc_dat);
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
}
}
else
{
fsmc_mmc_config(slot,m_fun);
rc_config(m_fun);
}
if(memt_areal==0x00)
{
u1_lofs_vpk_apk_dat = 0xFFF8;
sw_config_data[0] = (u8)(u1_lofs_vpk_apk_dat>>8);
sw_config_data[1] = (u8)(u1_lofs_vpk_apk_dat);
if(volt_cur==0x00)
{
//xil_printf("volt_cur: %x\n\r", 0x00);
spi_write_onewire(U1_SW_LOFS_VPK, sw_config_data, dat_width, CPLD_U1);
}
else
{
//xil_printf("volt_cur: %x\n\r", 0x01);
spi_write_onewire(U1_SW_LOFS_APK, sw_config_data, dat_width, CPLD_U1);
}
//xil_printf("u1_lofs_vpk_apk_dat %x\n\r", u1_lofs_vpk_apk_dat);
}
if(load>=1)
{
rl_config(load);
}
}
void fsmc_mmc_config(char slot,char m_fun)
{
u16 fmc_smc_dat = 0;
u16 mmc_dat = 0;
switch(m_fun)
{
case 0x01:
{
fmc_smc_dat = (0x0001<<(slot-1));
fmc_smc_dat = ~fmc_smc_dat;
mmc_dat = (0x0001<<((slot-1)/2));
mmc_dat = ~mmc_dat;
break;
}
case 0x02:
{
fmc_smc_dat = (0x0010<<(slot-1));
fmc_smc_dat = ~fmc_smc_dat;
mmc_dat = (0x0004<<((slot-1)/2));
mmc_dat = ~mmc_dat;
break;
}
case 0x03:
{
fmc_smc_dat = (0x0011<<(slot-1));
fmc_smc_dat = ~fmc_smc_dat;
mmc_dat = (0x0005<<((slot-1)/2));
mmc_dat = ~mmc_dat;
break;
}
}
//xil_printf("fmc_smc_dat: %x\n\r", fmc_smc_dat);
sw_config_data[0] = (u8)(fmc_smc_dat>>8);
sw_config_data[1] = (u8)(fmc_smc_dat);
spi_write_onewire(U1_SW_FMC_SMC, sw_config_data, dat_width, CPLD_U1);
//xil_printf("mmc_dat: %x\n\r", mmc_dat);
sw_config_data[0] = (u8)(mmc_dat>>8);
sw_config_data[1] = (u8)(mmc_dat);
spi_write_onewire(U1_SW_MMC, sw_config_data, dat_width, CPLD_U1);
}
void dmm_config(char slot, u16 ch_num)
{
u16 sw_oc_dmm_dat = 0;
if(ch_num>=1&&ch_num<=64)
{
sw_oc_dmm_dat = (0x0001<<((slot-1)*4));
sw_oc_dmm_dat = ~sw_oc_dmm_dat;
}
else if(ch_num>=65&&ch_num<=128)
{
sw_oc_dmm_dat = (0x0001<<((slot-1)*4+1));
sw_oc_dmm_dat = ~sw_oc_dmm_dat;
}
else if(ch_num>=129&&ch_num<=192)
{
sw_oc_dmm_dat = (0x0001<<((slot-1)*4+2));
sw_oc_dmm_dat = ~sw_oc_dmm_dat;
}
else
{
sw_oc_dmm_dat = (0x0001<<((slot-1)*4+3));
sw_oc_dmm_dat = ~sw_oc_dmm_dat;
}
//xil_printf("oc_dmm_dat: %x\n\r", sw_oc_dmm_dat);
sw_config_data[0] = (u8)(sw_oc_dmm_dat>>8);
sw_config_data[1] = (u8)(sw_oc_dmm_dat);
spi_write_onewire(U1_SW_OC_DMM, sw_config_data, dat_width, CPLD_U1);
}
void rc_config(char m_fun)
{
u16 rc_dat = 0;
switch(m_fun)
{
case 0x01:
{
rc_dat = 0xFFFD;
break;
}
case 0x02:
{
rc_dat = 0xFFFB;
break;
}
case 0x03:
{
rc_dat = 0xFFF9;
break;
}
}
//xil_printf("rc_dat: %x\n\r", rc_dat);
sw_config_data[0] = (u8)(rc_dat>>8);
sw_config_data[1] = (u8)(rc_dat);
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
}
void rl_config(char load)
{
u16 rl_dat = 0;
if(load>=1&&load<=9)
{
rl_dat = (0x0001<<(load-1));
rl_dat = ~rl_dat;
//xil_printf("load: %x\n\r", load);
//xil_printf("rl_01_dat: %x\n\r", rl_dat);
sw_config_data[0] = (u8)(rl_dat>>8);
sw_config_data[1] = (u8)(rl_dat);
spi_write_onewire(U1_SW_RL1, sw_config_data, dat_width, CPLD_U1);
}
else
{
rl_dat = (0x0001<<(load-10));
rl_dat = ~rl_dat;
//xil_printf("load: %x\n\r", load);
//xil_printf("rl_02_dat: %x\n\r", rl_dat);
sw_config_data[0] = (u8)(rl_dat>>8);
sw_config_data[1] = (u8)(rl_dat);
spi_write_onewire(U1_SW_RL2, sw_config_data, dat_width, CPLD_U1);
}
}
void fsc_oc_config(char slot,char m_fun, u16 ch_num)
{
u16 fc_dv0_dat = 0;
switch(m_fun)
{
case 0x01:
{
if(ch_num>=1&&ch_num<=16)
{
//xil_printf("m_fun=0x01,ch_num=1~16 \n\r");
fc_dv0_dat = (0x0001<<(ch_num-1));
fc_dv0_dat = ~fc_dv0_dat;
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
sw_config_data[1] = (u8)(fc_dv0_dat);
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
//xil_printf("CPLD_U1:\n\r");
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
}
else
{
//xil_printf("m_fun=0x01,ch_num=17~32 \n\r");
fc_dv0_dat = (0x0001<<(ch_num-17));
fc_dv0_dat = ~fc_dv0_dat;
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
sw_config_data[1] = (u8)(fc_dv0_dat);
spi_write_onewire(U2_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
//xil_printf("CPLD_U2:\n\r");
//xil_printf("fc_reg_addr: %d\n\r", U2_SW_FC_DV0+slot-1);
}
//xil_printf("reg_data: %x\n\r", fc_dv0_dat);
break;
}
case 0x02:
{
if(ch_num>=1&&ch_num<=16)
{
//xil_printf("m_fun=0x02,ch_num=1~16 \n\r");
fc_dv0_dat = (0x0001<<(ch_num-1));
fc_dv0_dat = ~fc_dv0_dat;
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
sw_config_data[1] = (u8)(fc_dv0_dat);
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
//xil_printf("CPLD_U1:\n\r");
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
}
else
{
//xil_printf("m_fun=0x02,ch_num=17~32 \n\r");
fc_dv0_dat = (0x0001<<(ch_num-17));
fc_dv0_dat = ~fc_dv0_dat;
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
sw_config_data[1] = (u8)(fc_dv0_dat);
spi_write_onewire(U2_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
//xil_printf("CPLD_U2:\n\r");
//xil_printf("sc_reg_addr: %d\n\r", U2_SW_SC_DV0+slot-1);
}
//xil_printf("reg_data: %x\n\r", fc_dv0_dat);
break;
}
case 0x03:
{
if(ch_num>=1&&ch_num<=16)
{
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
fc_dv0_dat = (0x0001<<(ch_num-1));
fc_dv0_dat = ~fc_dv0_dat;
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
sw_config_data[1] = (u8)(fc_dv0_dat);
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
//xil_printf("CPLD_U1:\n\r");
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
}
else
{
//xil_printf("m_fun=0x03,ch_num=17~32 \n\r");
fc_dv0_dat = (0x0001<<(ch_num-17));
fc_dv0_dat = ~fc_dv0_dat;
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
sw_config_data[1] = (u8)(fc_dv0_dat);
spi_write_onewire(U2_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
spi_write_onewire(U2_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
//xil_printf("CPLD_U2:\n\r");
//xil_printf("fc_reg_addr: %d\n\r", U2_SW_FC_DV0+slot-1);
//xil_printf("sc_reg_addr: %d\n\r", U2_SW_SC_DV0+slot-1);
}
//xil_printf("reg_data: %x\n\r", fc_dv0_dat);
break;
}
case 0x04:
{
if(ch_num>=1&&ch_num<=64)
{
//xil_printf("m_fun=0x04,ch_num=1~64 \n\r");
fc_dv0_dat = (0x0001<<((ch_num-1)/8));
fc_dv0_dat = ~fc_dv0_dat;
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
sw_config_data[1] = (u8)(fc_dv0_dat);
spi_write_onewire(U1_SW_OC_DV0+(slot-1)*2, sw_config_data, dat_width, CPLD_U1);
//xil_printf("CPLD_U1:\n\r");
//xil_printf("oc_reg_addr: %d\n\r", U1_SW_OC_DV0+(slot-1)*2);
}
else if(ch_num>=65&&ch_num<=128)
{
//xil_printf("m_fun=0x04,ch_num=65~128 \n\r");
fc_dv0_dat = (0x0001<<((ch_num-65)/8));
fc_dv0_dat = ~fc_dv0_dat;
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
sw_config_data[1] = (u8)(fc_dv0_dat);
spi_write_onewire(U2_SW_OC_DV0+(slot-1)*2, sw_config_data, dat_width, CPLD_U2);
//xil_printf("CPLD_U2:\n\r");
//xil_printf("oc_reg_addr: %d\n\r", U2_SW_OC_DV0+(slot-1)*2);
}
else if(ch_num>=129&&ch_num<=192)
{
//xil_printf("m_fun=0x04,ch_num=129~192 \n\r");
fc_dv0_dat = (0x0001<<((ch_num-129)/8));
fc_dv0_dat = ~fc_dv0_dat;
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
sw_config_data[1] = (u8)(fc_dv0_dat);
spi_write_onewire(U1_SW_OC_DV1+(slot-1)*2, sw_config_data, dat_width, CPLD_U1);
//xil_printf("CPLD_U1:\n\r");
//xil_printf("oc_reg_addr: %d\n\r", U1_SW_OC_DV1+(slot-1)*2);
}
else if(ch_num>=193&&ch_num<=256)
{
//xil_printf("m_fun=0x04,ch_num=193~256 \n\r");
fc_dv0_dat = (0x0001<<((ch_num-193)/8));
fc_dv0_dat = ~fc_dv0_dat;
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
sw_config_data[1] = (u8)(fc_dv0_dat);
spi_write_onewire(U2_SW_OC_DV1+(slot-1)*2, sw_config_data, dat_width, CPLD_U2);
//xil_printf("CPLD_U2:\n\r");
//xil_printf("oc_reg_addr: %d\n\r", U2_SW_OC_DV1+(slot-1)*2);
}
//xil_printf("reg_data: %x\n\r", fc_dv0_dat);
break;
}
}
}
Debug_FW.sdk/calboard/src/cal_meas.h
+23
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@@ -0,0 +1,23 @@
/*
* cal_meas.h
*
* Created on: 2023Äê7ÔÂ19ÈÕ
* Author: dell
*/
#ifndef SRC_CAL_MEAS_H_
#define SRC_CAL_MEAS_H_
#include "sleep.h"
#include "stdio.h"
#include "xgpiops.h"
#include "SPI_Driv.h"
#include "GPIO_Driv.h"
#define dat_width 3
void sw_config(char *slot_start);
#endif /* SRC_CAL_MEAS_H_ */
Debug_FW.sdk/calboard/src/crc16.c
+57
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@@ -0,0 +1,57 @@
/*
* crc16.c
*
* Created on: 2022Äê2ÔÂ24ÈÕ
* Author: Administrator
*/
#include "crc16.h"
const unsigned int crc_table[256] = {
0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
};
unsigned short do_crc_table(unsigned char* ptr, int len)
{
unsigned short crc = 0x0000;
while (len--)
{
crc = (crc >> 8) ^ crc_table[(crc ^ *ptr++) & 0xff];
}
return crc;
}
Debug_FW.sdk/calboard/src/crc16.h
+13
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@@ -0,0 +1,13 @@
/*
* crc16.h
*
* Created on: 2022年2月24日
* Author: Administrator
*/
#ifndef SRC_CRC16_H_
#define SRC_CRC16_H_
unsigned short do_crc_table(unsigned char* ptr, int len);
#endif /* SRC_CRC16_H_ */
Debug_FW.sdk/calboard/src/dna_read.c
+29
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/*
* dna_read.c
*
* Created on: 2023Äê6ÔÂ27ÈÕ
* Author: dell
*/
#include "dna_read.h"
#include "xil_io.h"
#include "xparameters.h"
#define DNA_ADDR XPAR_MYDNA_READ_V1_0_0_BASEADDR
void dna_port_read(char* read_data) //addr_change, because the board is 88d_a.
{
unsigned read_data_mem[2] = {0};
Xil_Out32(DNA_ADDR,0x01);
usleep(20);
read_data_mem[0] = Xil_In32(DNA_ADDR+4);
read_data_mem[1] = Xil_In32(DNA_ADDR+8);
for(int i = 0; i < 8; i++)
{
*(read_data+i) = (u8)(read_data_mem[i/4]>> (24 - (8*(i%4))));
}
}
Debug_FW.sdk/calboard/src/dna_read.h
+14
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/*
* dna_read.h
*
* Created on: 2023年6月27日
* Author: dell
*/
#ifndef SRC_DNA_READ_H_
#define SRC_DNA_READ_H_
void dna_port_read(char* read_data); //addr_change, because the board is 88d_a.
#endif /* SRC_DNA_READ_H_ */
Debug_FW.sdk/calboard/src/echo.c
+237
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/*
* Copyright (C) 2009 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
#include <stdio.h>
#include <string.h>
#include "dna_read.h"
#include "crc16.h"
#include "GPIO_Driv.h"
#include "SPI_Driv.h"
#include "cal_meas.h"
#include "lwip/err.h"
#include "lwip/tcp.h"
#if defined (__arm__) || defined (__aarch64__)
#include "xil_printf.h"
#endif
char *recv_data;
char dna_data[10];
unsigned short recv_len;
unsigned read_dat = 0;
char dat_0[20] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
unsigned crc_read_dat = 0;
char crc_alg_dat[2] = {0,0};
char send_data_cpld1[2] = {0xAA,0x56};
int transfer_data() {
return 0;
}
void print_app_header()
{
#if (LWIP_IPV6==0)
xil_printf("\n\r\n\r-----lwIP TCP echo server ------\n\r");
#else
xil_printf("\n\r\n\r-----lwIPv6 TCP echo server ------\n\r");
#endif
xil_printf("TCP packets sent to port 6001 will be echoed back\n\r");
}
err_t recv_callback(void *arg, struct tcp_pcb *tpcb,
struct pbuf *p, err_t err)
{
/* do not read the packet if we are not in ESTABLISHED state */
if (!p) {
tcp_close(tpcb);
tcp_recv(tpcb, NULL);
return ERR_OK;
}
/* indicate that the packet has been received */
tcp_recved(tpcb, p->len);
/* echo back the payload */
/* in this case, we assume that the payload is < TCP_SND_BUF */
if (tcp_sndbuf(tpcb) > p->len) {
recv_len = p->len;
recv_data = (char*)malloc(sizeof(char)*recv_len);
memcpy(recv_data,p->payload,recv_len);
if(recv_data[6] == 0x0E)
{
crc_read_dat = do_crc_table(recv_data+6, recv_len-8);
crc_alg_dat[0] = (u8)crc_read_dat;
crc_alg_dat[1] = (u8)(crc_read_dat>>8);
dat_0[0]= 0x00;
switch(recv_data[7])
{
case 0xA2://SLOT
{
dat_0[1]= 0x06;
dat_0[2]= recv_data[2];
dat_0[3]= recv_data[3];
dat_0[4]= recv_data[4];
dat_0[5]= recv_data[5];
dat_0[6]= recv_data[6];
dat_0[7]= recv_data[7];
if(recv_data[15]==crc_alg_dat[1]&&recv_data[16]==crc_alg_dat[0])
{
dat_0[8]= 0x01;
dat_0[9]= 0x01;
}
else
{
dat_0[8]= 0xff;
dat_0[9]= 0xff;
}
dat_0[10]= recv_data[15];
dat_0[11]= recv_data[16];
char slot_start[7] = {recv_data[8],recv_data[9],recv_data[10],recv_data[11],recv_data[12],recv_data[13],recv_data[14]};
//xil_printf("slot_start[0]:%x, slot_start[1]:%x,slot_start[2]:%x,slot_start[3]:%x,slot_start[4]:%x,slot_start[5]:%x,slot_start[6]:%x\n\r", slot_start[0],slot_start[1],slot_start[2],slot_start[3],slot_start[4],slot_start[5],slot_start[6]);
//rst_CPLD(CPLD_U1,4);
//rst_CPLD(CPLD_U2,4);
//rst_CPLD(CPLD_U3,4);
sw_config(slot_start);
tcp_write(tpcb, dat_0, 12, 1);
break;
}
case 0xA3://dna_port_read
{
dna_port_read(dna_data);
dat_0[1]=0x0e;
dat_0[2]=recv_data[2];
dat_0[3]=recv_data[3];
dat_0[4]=recv_data[4];
dat_0[5]=recv_data[5];
dat_0[6]=recv_data[6];
dat_0[7]=recv_data[7];
if(recv_data[8]==crc_alg_dat[1]&&recv_data[9]==crc_alg_dat[0])
{
dat_0[8]= 0x01;
dat_0[9]= 0x01;
}
else
{
dat_0[8]= 0xff;
dat_0[9]= 0xff;
}
dat_0[10]= dna_data[0];
dat_0[11]= dna_data[1];
dat_0[12]= dna_data[2];
dat_0[13]= dna_data[3];
dat_0[14]= dna_data[4];
dat_0[15]= dna_data[5];
dat_0[16]= dna_data[6];
dat_0[17]= dna_data[7];
dat_0[18]= recv_data[8];
dat_0[19]= recv_data[9];
tcp_write(tpcb, dat_0, 20, 1);
break;
}
}
}
} else
xil_printf("no space in tcp_sndbuf\n\r");
/* free the received pbuf */
pbuf_free(p);
return ERR_OK;
}
err_t accept_callback(void *arg, struct tcp_pcb *newpcb, err_t err)
{
static int connection = 1;
/* set the receive callback for this connection */
tcp_recv(newpcb, recv_callback);
/* just use an integer number indicating the connection id as the
callback argument */
tcp_arg(newpcb, (void*)(UINTPTR)connection);
/* increment for subsequent accepted connections */
connection++;
return ERR_OK;
}
int start_application()
{
struct tcp_pcb *pcb;
err_t err;
unsigned port = 200;
/* create new TCP PCB structure */
pcb = tcp_new_ip_type(IPADDR_TYPE_ANY);
if (!pcb) {
xil_printf("Error creating PCB. Out of Memory\n\r");
return -1;
}
/* bind to specified @port */
err = tcp_bind(pcb, IP_ANY_TYPE, port);
if (err != ERR_OK) {
xil_printf("Unable to bind to port %d: err = %d\n\r", port, err);
return -2;
}
/* we do not need any arguments to callback functions */
tcp_arg(pcb, NULL);
/* listen for connections */
pcb = tcp_listen(pcb);
if (!pcb) {
xil_printf("Out of memory while tcp_listen\n\r");
return -3;
}
/* specify callback to use for incoming connections */
tcp_accept(pcb, accept_callback);
xil_printf("TCP echo server started @ port %d\n\r", port);
return 0;
}
Debug_FW.sdk/calboard/src/i2c_access.c
+420
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/*
* Copyright (C) 2013 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
/*****************************************************************************/
/**
* @file i2c_lib.c
*
* This file contains library functions to initialize, control and access
* IIC devices.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 1.0 srt 10/19/13 Initial Version
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#if defined (__arm__) && !defined (ARMR5)
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || \
XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
#include "xil_exception.h"
#include "xil_printf.h"
#include "xiicps.h"
#include "sleep.h"
#include "xscugic.h"
/************************** Constant Definitions *****************************/
#define IIC_DEVICE_ID XPAR_XIICPS_0_DEVICE_ID
#define XIIC XIicPs
#define XIICCFG XIicPs_Config
#define I2cSetStatusHandler XIicPs_SetStatusHandler
#define I2cLookupConfig XIicPs_LookupConfig
#define I2cCfgInitialize XIicPs_CfgInitialize
#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
#define IIC_INTR_ID XPAR_XIICPS_0_INTR
#define INTC_HANDLER XScuGic_InterruptHandler
#define IIC_HANDLER XIicPs_IntrHandler
#define INTC XScuGic
#define IIC_SCLK_RATE 100000
/**************************** Type Definitions *******************************/
typedef struct {
XIIC I2cInstance;
INTC IntcInstance;
volatile u8 TransmitComplete; /* Flag to check completion of Transmission */
volatile u8 ReceiveComplete; /* Flag to check completion of Reception */
volatile u32 TotalErrorCount;
} XIIC_LIB;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
int I2cPhyWrite(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 Data, u16 SlaveAddr);
int I2cPhyRead(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 *Data, u16 SlaveAddr);
int I2cSetupHardware(XIIC_LIB *I2cLibPtr);
int I2cWriteData(XIIC_LIB *I2cLibPtr, u8 *WrBuffer, u16 ByteCount, u16 SlaveAddr);
int I2cReadData(XIIC_LIB *I2cLibPtr, u8 *RdBuffer, u16 ByteCount, u16 SlaveAddr);
static int SetupInterruptSystem(XIIC_LIB *I2cLibPtr);
static void StatusHandler(XIIC_LIB *I2cLibPtr, int Event);
/************************* Global Definitions *****************************/
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
* This function configures the IIC hardware.
*
* @param I2cLibPtr contains a pointer to the instance of the IIC library
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int I2cSetupHardware(XIIC_LIB *I2cLibPtr)
{
int Status;
XIICCFG *ConfigPtr;
XIIC *I2cInstancePtr;
I2cInstancePtr = &I2cLibPtr->I2cInstance;
/*
* Initialize the IIC driver so that it is ready to use.
*/
ConfigPtr = I2cLookupConfig(IIC_DEVICE_ID);
if (ConfigPtr == NULL) {
return XST_FAILURE;
}
Status = I2cCfgInitialize(I2cInstancePtr, ConfigPtr,
ConfigPtr->BaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* GPIO Code to pull MUX out of reset.
*/
Xil_Out32(0xe000a204, 0x2000);
Xil_Out32(0xe000a208, 0x2000);
Xil_Out32(0xe000a040, 0x2000);
/*
* Setup the Interrupt System.
*/
Status = SetupInterruptSystem(I2cLibPtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
I2cSetStatusHandler(I2cInstancePtr, I2cLibPtr, (IIC_HANDLER) StatusHandler);
/*
* Set the IIC serial clock rate.
*/
XIicPs_SetSClk(I2cInstancePtr, IIC_SCLK_RATE);
I2cLibPtr->TotalErrorCount = 0;
I2cLibPtr->TransmitComplete = FALSE;
I2cLibPtr->ReceiveComplete = FALSE;
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function writes data to the PHY.
*
* @param I2cLibPtr contains a pointer to the instance of the IIC library
* @param PhyAddr is the address of PHY to be written
* @param Reg is the register address to be written to
* @param Data is the pointer which contains the data to be written
* @param SlaveAddr is the address of the slave we are sending to.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int I2cPhyWrite(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 Data, u16 SlaveAddr)
{
int Status;
u8 WrBuffer[3];
WrBuffer[0] = Reg;
WrBuffer[1] = Data >> 8;
WrBuffer[2] = Data;
Status = I2cWriteData(I2cLibPtr, WrBuffer, 3, SlaveAddr);
if (Status != XST_SUCCESS) {
xil_printf("PhyWrite: Writing data failed\n\r");
return Status;
}
return Status;
}
/*****************************************************************************/
/**
* This function reads data from the PHY.
*
* @param I2cLibPtr contains a pointer to the instance of the IIC library
* @param PhyAddr is the address of PHY to be read from
* @param Reg is the register address to be read from
* @param Data is the pointer which stores the data read
* @param SlaveAddr is the address of the slave we are sending to.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int I2cPhyRead(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 *Data, u16 SlaveAddr)
{
int Status;
u8 WrBuffer[2];
u8 RdBuffer[2];
WrBuffer[0] = Reg;
Status = I2cWriteData(I2cLibPtr, WrBuffer, 1, SlaveAddr);
if (Status != XST_SUCCESS) {
xil_printf("PhyWrite: Writing data failed\n\r");
return Status;
}
Status = I2cReadData(I2cLibPtr, RdBuffer, 2, SlaveAddr);
if (Status != XST_SUCCESS) {
xil_printf("PhyRead: Reading data failed\n\r");
return Status;
}
*Data = RdBuffer[0] << 8 | RdBuffer[1];
return Status;
}
/*****************************************************************************/
/**
* This function writes a buffer of data to the IIC Device.
*
* @param I2cLibPtr contains a pointer to the instance of the IIC library
* @param WrBuffer is the buffer which contains data to be written
* @param ByteCount contains the number of bytes in the buffer to be
* written.
* @param SlaveAddr is the address of the slave we are sending to.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int I2cWriteData(XIIC_LIB *I2cLibPtr, u8 *WrBuffer, u16 ByteCount,
u16 SlaveAddr)
{
XIIC *I2cInstancePtr;
I2cInstancePtr = &I2cLibPtr->I2cInstance;
I2cLibPtr->TransmitComplete = FALSE;
/*
* Send the Data.
*/
XIicPs_MasterSend(I2cInstancePtr, WrBuffer, ByteCount, SlaveAddr);
/*
* Wait for the entire buffer to be sent, letting the interrupt
* processing work in the background, this function may get
* locked up in this loop if the interrupts are not working
* correctly.
*/
while (I2cLibPtr->TransmitComplete == FALSE) {
if (0 != I2cLibPtr->TotalErrorCount) {
xil_printf("I2cWriteData: Failed due to errors\n\r");
return XST_FAILURE;
}
}
/*
* Wait until bus is idle to start another transfer.
*/
while (XIicPs_BusIsBusy(I2cInstancePtr));
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function read data from the IIC Device.
*
* @param I2cLibPtr contains a pointer to the instance of the IIC library
* @param RdBuffer is the buffer into which data read
* @param ByteCount contains the number of bytes in the buffer to be
* written.
* @param SlaveAddr is the address of the slave we are sending to.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int I2cReadData(XIIC_LIB *I2cLibPtr, u8 *RdBuffer, u16 ByteCount, u16 SlaveAddr)
{
XIIC *I2cInstancePtr;
I2cInstancePtr = &I2cLibPtr->I2cInstance;
I2cLibPtr->ReceiveComplete = FALSE;
/*
* Receive the Data.
*/
XIicPs_MasterRecv(I2cInstancePtr, RdBuffer, ByteCount, SlaveAddr);
while (I2cLibPtr->ReceiveComplete == FALSE) {
if (0 != I2cLibPtr->TotalErrorCount) {
xil_printf("I2cReadData: Failed due to errors %d\n\r",
I2cLibPtr->TotalErrorCount);
return XST_FAILURE;
}
}
/*
* Wait until bus is idle to start another transfer.
*/
while (XIicPs_BusIsBusy(I2cInstancePtr))
;
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function setups the interrupt system so interrupts can occur for the
* IIC device. The function is application-specific since the actual system may
* or may not have an interrupt controller. The IIC device could be directly
* connected to a processor without an interrupt controller. The user should
* modify this function to fit the application.
*
* @param IicInstPtr contains a pointer to the instance of the IIC device
* which is going to be connected to the interrupt controller.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
* @note None.
*
******************************************************************************/
static int SetupInterruptSystem(XIIC_LIB *I2cLibPtr)
{
int Status;
XIIC *I2cInstancePtr;
INTC *IntcPtr;
I2cInstancePtr = &I2cLibPtr->I2cInstance;
IntcPtr = &I2cLibPtr->IntcInstance;
XScuGic_Config *IntcConfig;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcPtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(IntcPtr, IIC_INTR_ID, 0xA0, 0x3);
/*
* Connect the interrupt handler that will be called when an
* interrupt occurs for the device.
*/
Status = XScuGic_Connect(IntcPtr, IIC_INTR_ID,
(Xil_InterruptHandler) XIicPs_MasterInterruptHandler,
I2cInstancePtr);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Enable the interrupt for the IIC device.
*/
XScuGic_Enable(IntcPtr, IIC_INTR_ID);
/*
* Initialize the exception table and register the interrupt
* controller handler with the exception table
*/
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler) INTC_HANDLER, IntcPtr);
/* Enable non-critical exceptions */Xil_ExceptionEnable();
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This Status handler is called asynchronously from an interrupt
* context and indicates the events that have occurred.
*
* @param InstancePtr is a pointer to the IIC driver instance for which
* the handler is being called for.
* @param Event indicates the condition that has occurred.
*
* @return None.
*
* @note None.
*
******************************************************************************/
static void StatusHandler(XIIC_LIB *I2cLibPtr, int Event)
{
/*
* All of the data transfer has been finished.
*/
if (0 != (Event & XIICPS_EVENT_COMPLETE_RECV)) {
I2cLibPtr->ReceiveComplete = TRUE;
} else if (0 != (Event & XIICPS_EVENT_COMPLETE_SEND)) {
I2cLibPtr->TransmitComplete = TRUE;
} else if (0 == (Event & XIICPS_EVENT_SLAVE_RDY)) {
/*
* If it is other interrupt but not slave ready interrupt, it is
* an error.
* Data was received with an error.
*/
I2cLibPtr->TotalErrorCount++;
}
}
#endif
#endif
Debug_FW.sdk/calboard/src/iic_phyreset.c
+117
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@@ -0,0 +1,117 @@
/*
* Copyright (C) 2016 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
#include <stdio.h>
#include "xparameters.h"
#if defined (__arm__) || defined(__aarch64__)
#include "xil_printf.h"
#endif
#ifdef XPS_BOARD_ZCU102
#ifdef XPAR_XIICPS_0_DEVICE_ID
#include "xiicps.h"
#define BUF_LEN 10U
#define IOEXPANDER1_ADDR 0x20U
#define IIC_SCLK_RATE_IOEXP 400000
#define CMD_CFG_0_REG 0x06U
#define CMD_OUTPUT_0_REG 0x02U
#define DATA_OUTPUT 0x0U
#define DATA_COMMON_CFG 0xE0U
#define DATA_GT_0000_CFG 0x00U
XIicPs I2c0InstancePtr;
int IicPhyReset(void)
{
u8 WriteBuffer[BUF_LEN] = {0};
XIicPs_Config *I2c0CfgPtr;
int Status = XST_SUCCESS;
/* Initialize the IIC0 driver so that it is ready to use */
I2c0CfgPtr = XIicPs_LookupConfig(XPAR_XIICPS_0_DEVICE_ID);
if (I2c0CfgPtr == NULL) {
Status = XST_FAILURE;
return Status;
}
Status = XIicPs_CfgInitialize(&I2c0InstancePtr, I2c0CfgPtr,
I2c0CfgPtr->BaseAddress);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
return Status;
}
/* Set the IIC serial clock rate */
XIicPs_SetSClk(&I2c0InstancePtr, IIC_SCLK_RATE_IOEXP);
/* Configure I/O pins as Output */
WriteBuffer[0] = CMD_CFG_0_REG;
WriteBuffer[1] = DATA_OUTPUT;
Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
WriteBuffer, 2, IOEXPANDER1_ADDR);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
return Status;
}
/* Wait until bus is idle to start another transfer */
while (XIicPs_BusIsBusy(&I2c0InstancePtr));
/*
* Deasserting I2C_MUX_RESETB
* And GEM3 Resetb
* Selecting lanes based on configuration
*/
WriteBuffer[0] = CMD_OUTPUT_0_REG;
/* gt0000 or no GT configuration */
WriteBuffer[1] = DATA_COMMON_CFG | DATA_GT_0000_CFG;
/* Send the Data */
Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
WriteBuffer, 2, IOEXPANDER1_ADDR);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
return Status;
}
/* Wait until bus is idle */
while (XIicPs_BusIsBusy(&I2c0InstancePtr));
xil_printf("IIC PHY reset on ZCU102 successful \n\r");
return XST_SUCCESS;
}
#endif
#endif
Debug_FW.sdk/calboard/src/lscript.ld
+287
View File
@@ -0,0 +1,287 @@
/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: 2018.3 */
/* */
/* Copyright (c) 2010-2016 Xilinx, Inc. All rights reserved. */
/* */
/* Description : Cortex-A9 Linker Script */
/* */
/*******************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0xA000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0xA000;
_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
/* Define Memories in the system */
MEMORY
{
ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x3FF00000
ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
}
/* Specify the default entry point to the program */
ENTRY(_vector_table)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
.text : {
KEEP (*(.vectors))
*(.boot)
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
*(.plt)
*(.gnu_warning)
*(.gcc_execpt_table)
*(.glue_7)
*(.glue_7t)
*(.vfp11_veneer)
*(.ARM.extab)
*(.gnu.linkonce.armextab.*)
} > ps7_ddr_0
.init : {
KEEP (*(.init))
} > ps7_ddr_0
.fini : {
KEEP (*(.fini))
} > ps7_ddr_0
.rodata : {
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > ps7_ddr_0
.rodata1 : {
__rodata1_start = .;
*(.rodata1)
*(.rodata1.*)
__rodata1_end = .;
} > ps7_ddr_0
.sdata2 : {
__sdata2_start = .;
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
__sdata2_end = .;
} > ps7_ddr_0
.sbss2 : {
__sbss2_start = .;
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
} > ps7_ddr_0
.data : {
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.jcr)
*(.got)
*(.got.plt)
__data_end = .;
} > ps7_ddr_0
.data1 : {
__data1_start = .;
*(.data1)
*(.data1.*)
__data1_end = .;
} > ps7_ddr_0
.got : {
*(.got)
} > ps7_ddr_0
.ctors : {
__CTOR_LIST__ = .;
___CTORS_LIST___ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > ps7_ddr_0
.dtors : {
__DTOR_LIST__ = .;
___DTORS_LIST___ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
___DTORS_END___ = .;
} > ps7_ddr_0
.fixup : {
__fixup_start = .;
*(.fixup)
__fixup_end = .;
} > ps7_ddr_0
.eh_frame : {
*(.eh_frame)
} > ps7_ddr_0
.eh_framehdr : {
__eh_framehdr_start = .;
*(.eh_framehdr)
__eh_framehdr_end = .;
} > ps7_ddr_0
.gcc_except_table : {
*(.gcc_except_table)
} > ps7_ddr_0
.mmu_tbl (ALIGN(16384)) : {
__mmu_tbl_start = .;
*(.mmu_tbl)
__mmu_tbl_end = .;
} > ps7_ddr_0
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidix.*.*)
__exidx_end = .;
} > ps7_ddr_0
.preinit_array : {
__preinit_array_start = .;
KEEP (*(SORT(.preinit_array.*)))
KEEP (*(.preinit_array))
__preinit_array_end = .;
} > ps7_ddr_0
.init_array : {
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
} > ps7_ddr_0
.fini_array : {
__fini_array_start = .;
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
} > ps7_ddr_0
.ARM.attributes : {
__ARM.attributes_start = .;
*(.ARM.attributes)
__ARM.attributes_end = .;
} > ps7_ddr_0
.sdata : {
__sdata_start = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > ps7_ddr_0
.sbss (NOLOAD) : {
__sbss_start = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
__sbss_end = .;
} > ps7_ddr_0
.tdata : {
__tdata_start = .;
*(.tdata)
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > ps7_ddr_0
.tbss : {
__tbss_start = .;
*(.tbss)
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > ps7_ddr_0
.bss (NOLOAD) : {
__bss_start = .;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
__bss_end = .;
} > ps7_ddr_0
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
/* Generate Stack and Heap definitions */
.heap (NOLOAD) : {
. = ALIGN(16);
_heap = .;
HeapBase = .;
_heap_start = .;
. += _HEAP_SIZE;
_heap_end = .;
HeapLimit = .;
} > ps7_ddr_0
.stack (NOLOAD) : {
. = ALIGN(16);
_stack_end = .;
. += _STACK_SIZE;
. = ALIGN(16);
_stack = .;
__stack = _stack;
. = ALIGN(16);
_irq_stack_end = .;
. += _IRQ_STACK_SIZE;
. = ALIGN(16);
__irq_stack = .;
_supervisor_stack_end = .;
. += _SUPERVISOR_STACK_SIZE;
. = ALIGN(16);
__supervisor_stack = .;
_abort_stack_end = .;
. += _ABORT_STACK_SIZE;
. = ALIGN(16);
__abort_stack = .;
_fiq_stack_end = .;
. += _FIQ_STACK_SIZE;
. = ALIGN(16);
__fiq_stack = .;
_undef_stack_end = .;
. += _UNDEF_STACK_SIZE;
. = ALIGN(16);
__undef_stack = .;
} > ps7_ddr_0
_end = .;
}
Debug_FW.sdk/calboard/src/main.c
+259
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@@ -0,0 +1,259 @@
/*
* Copyright (C) 2009 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
#include <stdio.h>
#include "xparameters.h"
#include "netif/xadapter.h"
#include "platform.h"
#include "platform_config.h"
#if defined (__arm__) || defined(__aarch64__)
#include "xil_printf.h"
#endif
#include "lwip/tcp.h"
#include "xil_cache.h"
#include "GPIO_Driv.h"
#include "SPI_Driv.h"
#include "cal_meas.h"
#if LWIP_IPV6==1
#include "lwip/ip.h"
#else
#if LWIP_DHCP==1
#include "lwip/dhcp.h"
#endif
#endif
/* defined by each RAW mode application */
void print_app_header();
int start_application();
int transfer_data();
void tcp_fasttmr(void);
void tcp_slowtmr(void);
/* missing declaration in lwIP */
void lwip_init();
#if LWIP_IPV6==0
#if LWIP_DHCP==1
extern volatile int dhcp_timoutcntr;
err_t dhcp_start(struct netif *netif);
#endif
#endif
extern volatile int TcpFastTmrFlag;
extern volatile int TcpSlowTmrFlag;
static struct netif server_netif;
struct netif *echo_netif;
#if LWIP_IPV6==1
void print_ip6(char *msg, ip_addr_t *ip)
{
print(msg);
xil_printf(" %x:%x:%x:%x:%x:%x:%x:%x\n\r",
IP6_ADDR_BLOCK1(&ip->u_addr.ip6),
IP6_ADDR_BLOCK2(&ip->u_addr.ip6),
IP6_ADDR_BLOCK3(&ip->u_addr.ip6),
IP6_ADDR_BLOCK4(&ip->u_addr.ip6),
IP6_ADDR_BLOCK5(&ip->u_addr.ip6),
IP6_ADDR_BLOCK6(&ip->u_addr.ip6),
IP6_ADDR_BLOCK7(&ip->u_addr.ip6),
IP6_ADDR_BLOCK8(&ip->u_addr.ip6));
}
#else
void
print_ip(char *msg, ip_addr_t *ip)
{
print(msg);
xil_printf("%d.%d.%d.%d\n\r", ip4_addr1(ip), ip4_addr2(ip),
ip4_addr3(ip), ip4_addr4(ip));
}
void
print_ip_settings(ip_addr_t *ip, ip_addr_t *mask, ip_addr_t *gw)
{
print_ip("Board IP: ", ip);
print_ip("Netmask : ", mask);
print_ip("Gateway : ", gw);
}
#endif
#if defined (__arm__) && !defined (ARMR5)
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
int ProgramSi5324(void);
int ProgramSfpPhy(void);
#endif
#endif
#ifdef XPS_BOARD_ZCU102
#ifdef XPAR_XIICPS_0_DEVICE_ID
int IicPhyReset(void);
#endif
#endif
int main()
{
#if LWIP_IPV6==0
ip_addr_t ipaddr, netmask, gw;
#endif
/* the mac address of the board. this should be unique per board */
unsigned char mac_ethernet_address[] =
{ 0x00, 0x0a, 0x35, 0x00, 0x01, 0x01 };
echo_netif = &server_netif;
#if defined (__arm__) && !defined (ARMR5)
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
ProgramSi5324();
ProgramSfpPhy();
#endif
#endif
/* Define this board specific macro in order perform PHY reset on ZCU102 */
#ifdef XPS_BOARD_ZCU102
if(IicPhyReset()) {
xil_printf("Error performing PHY reset \n\r");
return -1;
}
#endif
init_platform();
#if LWIP_IPV6==0
#if LWIP_DHCP==1
ipaddr.addr = 0;
gw.addr = 0;
netmask.addr = 0;
#else
/* initialize IP addresses to be used */
IP4_ADDR(&ipaddr, 192, 168, 100, 110);
IP4_ADDR(&netmask, 255, 255, 255, 0);
IP4_ADDR(&gw, 192, 168, 100, 1);
#endif
#endif
print_app_header();
lwip_init();
#if (LWIP_IPV6 == 0)
/* Add network interface to the netif_list, and set it as default */
if (!xemac_add(echo_netif, &ipaddr, &netmask,
&gw, mac_ethernet_address,
PLATFORM_EMAC_BASEADDR)) {
xil_printf("Error adding N/W interface\n\r");
return -1;
}
#else
/* Add network interface to the netif_list, and set it as default */
if (!xemac_add(echo_netif, NULL, NULL, NULL, mac_ethernet_address,
PLATFORM_EMAC_BASEADDR)) {
xil_printf("Error adding N/W interface\n\r");
return -1;
}
echo_netif->ip6_autoconfig_enabled = 1;
netif_create_ip6_linklocal_address(echo_netif, 1);
netif_ip6_addr_set_state(echo_netif, 0, IP6_ADDR_VALID);
print_ip6("\n\rBoard IPv6 address ", &echo_netif->ip6_addr[0].u_addr.ip6);
#endif
netif_set_default(echo_netif);
/* now enable interrupts */
platform_enable_interrupts();
/* specify that the network if is up */
netif_set_up(echo_netif);
#if (LWIP_IPV6 == 0)
#if (LWIP_DHCP==1)
/* Create a new DHCP client for this interface.
* Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at
* the predefined regular intervals after starting the client.
*/
dhcp_start(echo_netif);
dhcp_timoutcntr = 24;
while(((echo_netif->ip_addr.addr) == 0) && (dhcp_timoutcntr > 0))
xemacif_input(echo_netif);
if (dhcp_timoutcntr <= 0) {
if ((echo_netif->ip_addr.addr) == 0) {
xil_printf("DHCP Timeout\r\n");
xil_printf("Configuring default IP of 192.168.100.110\r\n");
IP4_ADDR(&(echo_netif->ip_addr), 192, 168, 100, 110);
IP4_ADDR(&(echo_netif->netmask), 255, 255, 255, 0);
IP4_ADDR(&(echo_netif->gw), 192, 168, 100, 1);
}
}
ipaddr.addr = echo_netif->ip_addr.addr;
gw.addr = echo_netif->gw.addr;
netmask.addr = echo_netif->netmask.addr;
#endif
print_ip_settings(&ipaddr, &netmask, &gw);
#endif
EMIO_config();
interface_initial(CPLD_U1);
interface_initial(CPLD_U2);
interface_initial(CPLD_U3);
rst_CPLD(CPLD_U1,4);
rst_CPLD(CPLD_U2,4);
rst_CPLD(CPLD_U3,4);
/* start the application (web server, rxtest, txtest, etc..) */
start_application();
/* receive and process packets */
while (1) {
if (TcpFastTmrFlag) {
tcp_fasttmr();
TcpFastTmrFlag = 0;
}
if (TcpSlowTmrFlag) {
tcp_slowtmr();
TcpSlowTmrFlag = 0;
}
xemacif_input(echo_netif);
transfer_data();
}
/* never reached */
cleanup_platform();
return 0;
}
Debug_FW.sdk/calboard/src/platform.c
+190
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@@ -0,0 +1,190 @@
/*
* Copyright (C) 2009 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
#if __MICROBLAZE__ || __PPC__
#include "arch/cc.h"
#include "platform.h"
#include "platform_config.h"
#include "xil_cache.h"
#include "xparameters.h"
#include "xintc.h"
#include "xil_exception.h"
#include "lwip/tcp.h"
#include "netif/xadapter.h"
#ifdef STDOUT_IS_16550
#include "xuartns550_l.h"
#endif
#include "lwip/tcp.h"
#if LWIP_DHCP==1
volatile int dhcp_timoutcntr = 24;
void dhcp_fine_tmr();
void dhcp_coarse_tmr();
#endif
volatile int TcpFastTmrFlag = 0;
volatile int TcpSlowTmrFlag = 0;
extern struct netif *echo_netif;
void
timer_callback()
{
static int DetectEthLinkStatus = 0;
/* we need to call tcp_fasttmr & tcp_slowtmr at intervals specified by lwIP.
* It is not important that the timing is absoluetly accurate.
*/
static int odd = 1;
#if LWIP_DHCP==1
static int dhcp_timer = 0;
#endif
DetectEthLinkStatus++;
TcpFastTmrFlag = 1;
odd = !odd;
if (odd) {
#if LWIP_DHCP==1
dhcp_timer++;
dhcp_timoutcntr--;
#endif
TcpSlowTmrFlag = 1;
#if LWIP_DHCP==1
dhcp_fine_tmr();
if (dhcp_timer >= 120) {
dhcp_coarse_tmr();
dhcp_timer = 0;
}
#endif
}
/* For detecting Ethernet phy link status periodically */
if (DetectEthLinkStatus == ETH_LINK_DETECT_INTERVAL) {
eth_link_detect(echo_netif);
DetectEthLinkStatus = 0;
}
}
static XIntc intc;
void platform_setup_interrupts()
{
XIntc *intcp;
intcp = &intc;
XIntc_Initialize(intcp, XPAR_INTC_0_DEVICE_ID);
XIntc_Start(intcp, XIN_REAL_MODE);
/* Start the interrupt controller */
XIntc_MasterEnable(XPAR_INTC_0_BASEADDR);
#ifdef __PPC__
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(XExceptionHandler)XIntc_DeviceInterruptHandler,
(void*) XPAR_INTC_0_DEVICE_ID);
#elif __MICROBLAZE__
microblaze_register_handler((XInterruptHandler)XIntc_InterruptHandler, intcp);
#endif
platform_setup_timer();
#ifdef XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK
/* Enable timer and EMAC interrupts in the interrupt controller */
XIntc_EnableIntr(XPAR_INTC_0_BASEADDR,
#ifdef __MICROBLAZE__
PLATFORM_TIMER_INTERRUPT_MASK |
#endif
XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK);
#endif
#ifdef XPAR_INTC_0_LLTEMAC_0_VEC_ID
#ifdef __MICROBLAZE__
XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR);
#endif
XIntc_Enable(intcp, XPAR_INTC_0_LLTEMAC_0_VEC_ID);
#endif
#ifdef XPAR_INTC_0_AXIETHERNET_0_VEC_ID
XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR);
XIntc_Enable(intcp, XPAR_INTC_0_AXIETHERNET_0_VEC_ID);
#endif
#ifdef XPAR_INTC_0_EMACLITE_0_VEC_ID
#ifdef __MICROBLAZE__
XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR);
#endif
XIntc_Enable(intcp, XPAR_INTC_0_EMACLITE_0_VEC_ID);
#endif
}
void
enable_caches()
{
#ifdef __PPC__
Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
#elif __MICROBLAZE__
#ifdef XPAR_MICROBLAZE_USE_ICACHE
Xil_ICacheEnable();
#endif
#ifdef XPAR_MICROBLAZE_USE_DCACHE
Xil_DCacheEnable();
#endif
#endif
}
void
disable_caches()
{
Xil_DCacheDisable();
Xil_ICacheDisable();
}
void init_platform()
{
enable_caches();
#ifdef STDOUT_IS_16550
XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, 9600);
XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
#endif
platform_setup_interrupts();
}
void cleanup_platform()
{
disable_caches();
}
#endif
Debug_FW.sdk/calboard/src/platform.h
+48
View File
@@ -0,0 +1,48 @@
/*
* Copyright (C) 2009 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
#ifndef __PLATFORM_H_
#define __PLATFORM_H_
/* Platform timer is calibrated for 250 ms, so kept interval value 4 to call
* eth_link_detect() at every one second
*/
#define ETH_LINK_DETECT_INTERVAL 4
void init_platform();
void cleanup_platform();
#ifdef __MICROBLAZE__
void timer_callback();
#endif
#ifdef __PPC__
void timer_callback();
#endif
void platform_setup_timer();
void platform_enable_interrupts();
#endif
Debug_FW.sdk/calboard/src/platform_config.h
+10
View File
@@ -0,0 +1,10 @@
#ifndef __PLATFORM_CONFIG_H_
#define __PLATFORM_CONFIG_H_
#define PLATFORM_EMAC_BASEADDR XPAR_XEMACPS_0_BASEADDR
#define PLATFORM_ZYNQ
#endif
Debug_FW.sdk/calboard/src/platform_mb.c
+93
View File
@@ -0,0 +1,93 @@
/*
* Copyright (C) 2010 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
/*
* platform_mb.c
*
* MicroBlaze platform specific functions.
*/
#ifdef __MICROBLAZE__
#include "platform.h"
#include "platform_config.h"
#include "mb_interface.h"
#include "xparameters.h"
#include "xintc.h"
#include "xtmrctr_l.h"
void
xadapter_timer_handler(void *p)
{
timer_callback();
/* Load timer, clear interrupt bit */
XTmrCtr_SetControlStatusReg(PLATFORM_TIMER_BASEADDR, 0,
XTC_CSR_INT_OCCURED_MASK
| XTC_CSR_LOAD_MASK);
XTmrCtr_SetControlStatusReg(PLATFORM_TIMER_BASEADDR, 0,
XTC_CSR_ENABLE_TMR_MASK
| XTC_CSR_ENABLE_INT_MASK
| XTC_CSR_AUTO_RELOAD_MASK
| XTC_CSR_DOWN_COUNT_MASK);
XIntc_AckIntr(XPAR_INTC_0_BASEADDR, PLATFORM_TIMER_INTERRUPT_MASK);
}
#define MHZ (66)
#define TIMER_TLR (25000000*((float)MHZ/100))
void
platform_setup_timer()
{
/* set the number of cycles the timer counts before interrupting */
/* 100 Mhz clock => .01us for 1 clk tick. For 100ms, 10000000 clk ticks need to elapse */
XTmrCtr_SetLoadReg(PLATFORM_TIMER_BASEADDR, 0, TIMER_TLR);
/* reset the timers, and clear interrupts */
XTmrCtr_SetControlStatusReg(PLATFORM_TIMER_BASEADDR, 0, XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK );
/* start the timers */
XTmrCtr_SetControlStatusReg(PLATFORM_TIMER_BASEADDR, 0,
XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK
| XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK);
/* Register Timer handler */
XIntc_RegisterHandler(XPAR_INTC_0_BASEADDR,
PLATFORM_TIMER_INTERRUPT_INTR,
(XInterruptHandler)xadapter_timer_handler,
0);
}
void platform_enable_interrupts()
{
microblaze_enable_interrupts();
}
#endif
Debug_FW.sdk/calboard/src/platform_ppc.c
+84
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/*
* Copyright (C) 2010 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
/*
* platform_ppc.c
*
* PPC specific functions to setup timer
*/
#ifdef __PPC__
#include "platform.h"
#include "platform_config.h"
#include "xexception_l.h"
#include "xil_exception.h"
#include "xtime_l.h"
#include "xparameters.h"
#define MHZ 400
#define PIT_INTERVAL (250*MHZ*1000)
void
xadapter_timer_handler(void *p)
{
timer_callback();
XTime_TSRClearStatusBits(XREG_TSR_CLEAR_ALL);
}
void
platform_setup_timer()
{
#ifdef XPAR_CPU_PPC440_CORE_CLOCK_FREQ_HZ
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_DEC_INT,
(XExceptionHandler)xadapter_timer_handler, NULL);
/* Set DEC to interrupt every 250 mseconds */
XTime_DECSetInterval(PIT_INTERVAL);
XTime_TSRClearStatusBits(XREG_TSR_CLEAR_ALL);
XTime_DECEnableAutoReload();
XTime_DECEnableInterrupt();
#else
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_PIT_INT,
(XExceptionHandler)xadapter_timer_handler, NULL);
/* Set PIT to interrupt every 250 mseconds */
XTime_PITSetInterval(PIT_INTERVAL);
XTime_TSRClearStatusBits(XREG_TSR_CLEAR_ALL);
XTime_PITEnableAutoReload();
XTime_PITEnableInterrupt();
#endif
}
void
platform_enable_interrupts()
{
Xil_ExceptionEnable();
}
#endif
Debug_FW.sdk/calboard/src/platform_zynq.c
+236
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/*
* Copyright (C) 2010 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
/*
* platform_zynq.c
*
* Zynq platform specific functions.
*
* 02/29/2012: UART initialization is removed. Timer initializations are
* removed. All unnecessary include files and hash defines are removed.
* 03/01/2013: Timer initialization is added back. Support for SI #692601 is
* added in the timer callback. The SI #692601 refers to the following issue.
*
* The EmacPs has a HW bug on the Rx path for heavy Rx traffic.
* Under heavy Rx traffic because of the HW bug there are times when the Rx path
* becomes unresponsive. The workaround for it is to check for the Rx path for
* traffic (by reading the stats registers regularly). If the stats register
* does not increment for sometime (proving no Rx traffic), the function resets
* the Rx data path.
*
* </pre>
*/
#ifdef __arm__
#include "xparameters.h"
#include "xparameters_ps.h" /* defines XPAR values */
#include "xil_cache.h"
#include "xscugic.h"
#include "lwip/tcp.h"
#include "xil_printf.h"
#include "platform.h"
#include "platform_config.h"
#include "netif/xadapter.h"
#ifdef PLATFORM_ZYNQ
#include "xscutimer.h"
#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
#define TIMER_DEVICE_ID XPAR_SCUTIMER_DEVICE_ID
#define INTC_BASE_ADDR XPAR_SCUGIC_0_CPU_BASEADDR
#define INTC_DIST_BASE_ADDR XPAR_SCUGIC_0_DIST_BASEADDR
#define TIMER_IRPT_INTR XPAR_SCUTIMER_INTR
#define RESET_RX_CNTR_LIMIT 400
void tcp_fasttmr(void);
void tcp_slowtmr(void);
static XScuTimer TimerInstance;
#ifndef USE_SOFTETH_ON_ZYNQ
static int ResetRxCntr = 0;
#endif
extern struct netif *echo_netif;
volatile int TcpFastTmrFlag = 0;
volatile int TcpSlowTmrFlag = 0;
#if LWIP_DHCP==1
volatile int dhcp_timoutcntr = 24;
void dhcp_fine_tmr();
void dhcp_coarse_tmr();
#endif
void
timer_callback(XScuTimer * TimerInstance)
{
static int DetectEthLinkStatus = 0;
/* we need to call tcp_fasttmr & tcp_slowtmr at intervals specified
* by lwIP. It is not important that the timing is absoluetly accurate.
*/
static int odd = 1;
#if LWIP_DHCP==1
static int dhcp_timer = 0;
#endif
DetectEthLinkStatus++;
TcpFastTmrFlag = 1;
odd = !odd;
#ifndef USE_SOFTETH_ON_ZYNQ
ResetRxCntr++;
#endif
if (odd) {
#if LWIP_DHCP==1
dhcp_timer++;
dhcp_timoutcntr--;
#endif
TcpSlowTmrFlag = 1;
#if LWIP_DHCP==1
dhcp_fine_tmr();
if (dhcp_timer >= 120) {
dhcp_coarse_tmr();
dhcp_timer = 0;
}
#endif
}
/* For providing an SW alternative for the SI #692601. Under heavy
* Rx traffic if at some point the Rx path becomes unresponsive, the
* following API call will ensures a SW reset of the Rx path. The
* API xemacpsif_resetrx_on_no_rxdata is called every 100 milliseconds.
* This ensures that if the above HW bug is hit, in the worst case,
* the Rx path cannot become unresponsive for more than 100
* milliseconds.
*/
#ifndef USE_SOFTETH_ON_ZYNQ
if (ResetRxCntr >= RESET_RX_CNTR_LIMIT) {
xemacpsif_resetrx_on_no_rxdata(echo_netif);
ResetRxCntr = 0;
}
#endif
/* For detecting Ethernet phy link status periodically */
if (DetectEthLinkStatus == ETH_LINK_DETECT_INTERVAL) {
eth_link_detect(echo_netif);
DetectEthLinkStatus = 0;
}
XScuTimer_ClearInterruptStatus(TimerInstance);
}
void platform_setup_timer(void)
{
int Status = XST_SUCCESS;
XScuTimer_Config *ConfigPtr;
int TimerLoadValue = 0;
ConfigPtr = XScuTimer_LookupConfig(TIMER_DEVICE_ID);
Status = XScuTimer_CfgInitialize(&TimerInstance, ConfigPtr,
ConfigPtr->BaseAddr);
if (Status != XST_SUCCESS) {
xil_printf("In %s: Scutimer Cfg initialization failed...\r\n",
__func__);
return;
}
Status = XScuTimer_SelfTest(&TimerInstance);
if (Status != XST_SUCCESS) {
xil_printf("In %s: Scutimer Self test failed...\r\n",
__func__);
return;
}
XScuTimer_EnableAutoReload(&TimerInstance);
/*
* Set for 250 milli seconds timeout.
*/
TimerLoadValue = XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ / 8;
XScuTimer_LoadTimer(&TimerInstance, TimerLoadValue);
return;
}
void platform_setup_interrupts(void)
{
Xil_ExceptionInit();
XScuGic_DeviceInitialize(INTC_DEVICE_ID);
/*
* Connect the interrupt controller interrupt handler to the hardware
* interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
(void *)INTC_DEVICE_ID);
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
XScuGic_RegisterHandler(INTC_BASE_ADDR, TIMER_IRPT_INTR,
(Xil_ExceptionHandler)timer_callback,
(void *)&TimerInstance);
/*
* Enable the interrupt for scu timer.
*/
XScuGic_EnableIntr(INTC_DIST_BASE_ADDR, TIMER_IRPT_INTR);
return;
}
void platform_enable_interrupts()
{
/*
* Enable non-critical exceptions.
*/
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
XScuTimer_EnableInterrupt(&TimerInstance);
XScuTimer_Start(&TimerInstance);
return;
}
void init_platform()
{
platform_setup_timer();
platform_setup_interrupts();
return;
}
void cleanup_platform()
{
Xil_ICacheDisable();
Xil_DCacheDisable();
return;
}
#endif
#endif
Debug_FW.sdk/calboard/src/platform_zynqmp.c
+199
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/*
* Copyright (C) 2015 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
/*
* platform_zynqmp.c
*
* ZynqMP platform specific functions.
*
*
* </pre>
*/
#if defined (__arm__) || defined (__aarch64__)
#include "xparameters.h"
#include "xparameters_ps.h" /* defines XPAR values */
#include "xil_cache.h"
#include "xscugic.h"
#include "lwip/tcp.h"
#include "xil_printf.h"
#include "platform.h"
#include "platform_config.h"
#include "netif/xadapter.h"
#if defined(PLATFORM_ZYNQMP) || defined(PLATFORM_VERSAL)
#include "xttcps.h"
#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
#define TIMER_DEVICE_ID XPAR_XTTCPS_0_DEVICE_ID
#define TIMER_IRPT_INTR XPAR_XTTCPS_0_INTR
#define INTC_BASE_ADDR XPAR_SCUGIC_0_CPU_BASEADDR
#define INTC_DIST_BASE_ADDR XPAR_SCUGIC_0_DIST_BASEADDR
#define PLATFORM_TIMER_INTR_RATE_HZ (4)
static XTtcPs TimerInstance;
static XInterval Interval;
static u8 Prescaler;
volatile int TcpFastTmrFlag = 0;
volatile int TcpSlowTmrFlag = 0;
#if LWIP_DHCP==1
volatile int dhcp_timoutcntr = 24;
void dhcp_fine_tmr();
void dhcp_coarse_tmr();
#endif
extern struct netif *echo_netif;
void platform_clear_interrupt( XTtcPs * TimerInstance );
void
timer_callback(XTtcPs * TimerInstance)
{
static int DetectEthLinkStatus = 0;
/* we need to call tcp_fasttmr & tcp_slowtmr at intervals specified
* by lwIP. It is not important that the timing is absoluetly accurate.
*/
static int odd = 1;
#if LWIP_DHCP==1
static int dhcp_timer = 0;
#endif
DetectEthLinkStatus++;
TcpFastTmrFlag = 1;
odd = !odd;
if (odd) {
#if LWIP_DHCP==1
dhcp_timer++;
dhcp_timoutcntr--;
#endif
TcpSlowTmrFlag = 1;
#if LWIP_DHCP==1
dhcp_fine_tmr();
if (dhcp_timer >= 120) {
dhcp_coarse_tmr();
dhcp_timer = 0;
}
#endif
}
/* For detecting Ethernet phy link status periodically */
if (DetectEthLinkStatus == ETH_LINK_DETECT_INTERVAL) {
eth_link_detect(echo_netif);
DetectEthLinkStatus = 0;
}
platform_clear_interrupt(TimerInstance);
}
void platform_setup_timer(void)
{
int Status;
XTtcPs * Timer = &TimerInstance;
XTtcPs_Config *Config;
Config = XTtcPs_LookupConfig(TIMER_DEVICE_ID);
Status = XTtcPs_CfgInitialize(Timer, Config, Config->BaseAddress);
if (Status != XST_SUCCESS) {
xil_printf("In %s: Timer Cfg initialization failed...\r\n",
__func__);
return;
}
XTtcPs_SetOptions(Timer, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE);
XTtcPs_CalcIntervalFromFreq(Timer, PLATFORM_TIMER_INTR_RATE_HZ, &Interval, &Prescaler);
XTtcPs_SetInterval(Timer, Interval);
XTtcPs_SetPrescaler(Timer, Prescaler);
}
void platform_clear_interrupt( XTtcPs * TimerInstance )
{
u32 StatusEvent;
StatusEvent = XTtcPs_GetInterruptStatus(TimerInstance);
XTtcPs_ClearInterruptStatus(TimerInstance, StatusEvent);
}
void platform_setup_interrupts(void)
{
Xil_ExceptionInit();
XScuGic_DeviceInitialize(INTC_DEVICE_ID);
/*
* Connect the interrupt controller interrupt handler to the hardware
* interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
(void *)INTC_DEVICE_ID);
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
XScuGic_RegisterHandler(INTC_BASE_ADDR, TIMER_IRPT_INTR,
(Xil_ExceptionHandler)timer_callback,
(void *)&TimerInstance);
/*
* Enable the interrupt for scu timer.
*/
XScuGic_EnableIntr(INTC_DIST_BASE_ADDR, TIMER_IRPT_INTR);
return;
}
void platform_enable_interrupts()
{
/*
* Enable non-critical exceptions.
*/
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
XScuGic_EnableIntr(INTC_DIST_BASE_ADDR, TIMER_IRPT_INTR);
XTtcPs_EnableInterrupts(&TimerInstance, XTTCPS_IXR_INTERVAL_MASK);
XTtcPs_Start(&TimerInstance);
return;
}
void init_platform()
{
platform_setup_timer();
platform_setup_interrupts();
return;
}
void cleanup_platform()
{
Xil_ICacheDisable();
Xil_DCacheDisable();
return;
}
#endif
#endif
Debug_FW.sdk/calboard/src/sfp.c
+192
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/*
* Copyright (C) 2013 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
/*****************************************************************************/
/**
* @file sfp.c
*
* This file programs sfp phy chip.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 1.0 srt 10/19/13 Initial Version
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#if defined (__arm__) && !defined (ARMR5)
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || \
XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
#include "xil_printf.h"
#include "xiicps.h"
#include "sleep.h"
#include "xscugic.h"
/************************** Constant Definitions *****************************/
#define IIC_SLAVE_ADDR 0x56
#define IIC_MUX_ADDRESS 0x74
#define IIC_CHANNEL_ADDRESS 0x01
#define XIIC XIicPs
#define INTC XScuGic
/**************************** Type Definitions *******************************/
typedef struct {
XIIC I2cInstance;
INTC IntcInstance;
volatile u8 TransmitComplete; /* Flag to check completion of Transmission */
volatile u8 ReceiveComplete; /* Flag to check completion of Reception */
volatile u32 TotalErrorCount;
} XIIC_LIB;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
int I2cWriteData(XIIC_LIB *I2cLibPtr, u8 *WrBuffer, u16 ByteCount, u16 SlaveAddr);
int I2cReadData(XIIC_LIB *I2cLibPtr, u8 *RdBuffer, u16 ByteCount, u16 SlaveAddr);
int I2cPhyWrite(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 Data, u16 SlaveAddr);
int I2cPhyRead(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 *Data, u16 SlaveAddr);
int I2cSetupHardware(XIIC_LIB *I2cLibPtr);
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
* This function initializes ZC706 MUX.
*
* @param I2cLibPtr contains a pointer to the instance of the IIC library
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int ZC706MuxInit(XIIC_LIB *I2cLibInstancePtr)
{
u8 WrBuffer;
int Status;
WrBuffer = IIC_CHANNEL_ADDRESS;
Status = I2cWriteData(I2cLibInstancePtr, &WrBuffer, 1, IIC_MUX_ADDRESS);
if (Status != XST_SUCCESS) {
xil_printf("SFP_PHY: Writing failed\n\r");
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function program SFP PHY.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
******************************************************************************/
int ProgramSfpPhy(void)
{
XIIC_LIB I2cLibInstance;
int Status;
u8 WrBuffer[2];
u16 phy_read_val;
Status = I2cSetupHardware(&I2cLibInstance);
if (Status != XST_SUCCESS) {
xil_printf("Fail!!!\n\r");
xil_printf("SFP_PHY: Configuring HW failed\n\r");
return XST_FAILURE;
}
Status = ZC706MuxInit(&I2cLibInstance);
if (Status != XST_SUCCESS) {
xil_printf("SFP_PHY: Mux Init failed\n\r");
return XST_FAILURE;
}
WrBuffer[0] = 0;
Status = I2cWriteData(&I2cLibInstance, WrBuffer, 1, IIC_SLAVE_ADDR);
if (Status != XST_SUCCESS) {
xil_printf("SFP_PHY: Writing failed\n\r");
return XST_FAILURE;
}
#if XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
/* Enabling 1000BASEX */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x1B, 0x9088, IIC_SLAVE_ADDR);
#else
/* Enabling SGMII */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x1B, 0x9084, IIC_SLAVE_ADDR);
#endif
/* Apply Soft Reset */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
/* Enable 1000BaseT Full Duplex capabilities */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x09, 0x0E00, IIC_SLAVE_ADDR);
/* Apply Soft Reset */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
/* Advertise 10/100 Capabilities else change the capabilities */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x04, 0x0141, IIC_SLAVE_ADDR);
/* Apply Soft Reset */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
/* Apply Soft Reset */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x10, 0xF079, IIC_SLAVE_ADDR);
/* Apply Soft Reset */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0001, IIC_SLAVE_ADDR);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9340, IIC_SLAVE_ADDR);
usleep(1);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0, IIC_SLAVE_ADDR);
phy_read_val = 0x0;
while((phy_read_val & 0x0C00) != 0x0C00) {
I2cPhyRead(&I2cLibInstance, IIC_SLAVE_ADDR, 0x11, &phy_read_val, IIC_SLAVE_ADDR);
}
usleep(1);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0, IIC_SLAVE_ADDR);
I2cPhyRead(&I2cLibInstance, IIC_SLAVE_ADDR, 0x11, &phy_read_val, IIC_SLAVE_ADDR);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0001, IIC_SLAVE_ADDR);
/* configure speed */
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x14, 0x0c61, IIC_SLAVE_ADDR);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9340, IIC_SLAVE_ADDR);
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0, IIC_SLAVE_ADDR);
return XST_SUCCESS;
}
#endif
#endif
Debug_FW.sdk/calboard/src/si5324.c
+187
View File
@@ -0,0 +1,187 @@
/*
* Copyright (C) 2013 - 2019 Xilinx, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
*/
/*****************************************************************************/
/**
* @file si5324.c
*
* This file programs si5324 chip which generates clock for the peripherals.
*
* Please refer to Si5324 Datasheet for more information
* http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5324.pdf
*
* Tested on Zynq ZC706 platform
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 1.0 srt 10/19/13 Initial Version
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#if defined (__arm__) && !defined (ARMR5)
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || \
XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
#include "xil_printf.h"
#include "xiicps.h"
#include "sleep.h"
#include "xscugic.h"
/************************** Constant Definitions *****************************/
#define IIC_SLAVE_ADDR 0x68
#define IIC_MUX_ADDRESS 0x74
#define IIC_CHANNEL_ADDRESS 0x10
#define XIIC XIicPs
#define INTC XScuGic
/**************************** Type Definitions *******************************/
typedef struct SI324Info
{
u32 RegIndex; /* Register Number */
u32 Value; /* Value to be Written */
} SI324Info;
typedef struct {
XIIC I2cInstance;
INTC IntcInstance;
volatile u8 TransmitComplete; /* Flag to check completion of Transmission */
volatile u8 ReceiveComplete; /* Flag to check completion of Reception */
volatile u32 TotalErrorCount;
} XIIC_LIB;
/************************** Function Prototypes *****************************/
int I2cWriteData(XIIC_LIB *I2cLibPtr, u8 *WrBuffer, u16 ByteCount, u16 SlaveAddr);
int I2cReadData(XIIC_LIB *I2cLibPtr, u8 *RdBuffer, u16 ByteCount, u16 SlaveAddr);
int I2cPhyWrite(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 Data, u16 SlaveAddr);
int I2cPhyRead(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 *Data, u16 SlaveAddr);
int I2cSetupHardware(XIIC_LIB *I2cLibPtr);
/************************* Global Definitions *****************************/
/*
* These configuration values generates 125MHz clock
* For more information please refer to Si5324 Datasheet.
*/
SI324Info InitTable[] = {
{ 0, 0x54}, /* Register 0 */
{ 1, 0xE4}, /* Register 1 */
{ 2, 0x12}, /* Register 2 */
{ 3, 0x15}, /* Register 3 */
{ 4, 0x92}, /* Register 4 */
{ 5, 0xed}, /* Register 5 */
{ 6, 0x2d}, /* Register 6 */
{ 7, 0x2a}, /* Register 7 */
{ 8, 0x00}, /* Register 8 */
{ 9, 0xc0}, /* Register 9 */
{ 10, 0x08}, /* Register 10 */
{ 11, 0x40}, /* Register 11 */
{ 19, 0x29}, /* Register 19 */
{ 20, 0x3e}, /* Register 20 */
{ 21, 0xff}, /* Register 21 */
{ 22, 0xdf}, /* Register 22 */
{ 23, 0x1f}, /* Register 23 */
{ 24, 0x3f}, /* Register 24 */
{ 25, 0x60}, /* Register 25 */
{ 31, 0x00}, /* Register 31 */
{ 32, 0x00}, /* Register 32 */
{ 33, 0x05}, /* Register 33 */
{ 34, 0x00}, /* Register 34 */
{ 35, 0x00}, /* Register 35 */
{ 36, 0x05}, /* Register 36 */
{ 40, 0xc2}, /* Register 40 */
{ 41, 0x22}, /* Register 41 */
{ 42, 0xdf}, /* Register 42 */
{ 43, 0x00}, /* Register 43 */
{ 44, 0x77}, /* Register 44 */
{ 45, 0x0b}, /* Register 45 */
{ 46, 0x00}, /* Register 46 */
{ 47, 0x77}, /* Register 47 */
{ 48, 0x0b}, /* Register 48 */
{ 55, 0x00}, /* Register 55 */
{131, 0x1f}, /* Register 131 */
{132, 0x02}, /* Register 132 */
{137, 0x01}, /* Register 137 */
{138, 0x0f}, /* Register 138 */
{139, 0xff}, /* Register 139 */
{142, 0x00}, /* Register 142 */
{143, 0x00}, /* Register 143 */
{136, 0x40} /* Register 136 */
};
/************************** Function Definitions *****************************/
int MuxInit(XIIC_LIB *I2cLibInstancePtr)
{
u8 WrBuffer[0];
int Status;
WrBuffer[0] = IIC_CHANNEL_ADDRESS;
Status = I2cWriteData(I2cLibInstancePtr,
WrBuffer, 1, IIC_MUX_ADDRESS);
if (Status != XST_SUCCESS) {
xil_printf("Si5324: Writing failed\n\r");
return XST_FAILURE;
}
return XST_SUCCESS;
}
int ProgramSi5324(void)
{
XIIC_LIB I2cLibInstance;
int Index;
int Status;
u8 WrBuffer[2];
Status = I2cSetupHardware(&I2cLibInstance);
if (Status != XST_SUCCESS) {
xil_printf("Si5324: Configuring HW failed\n\r");
return XST_FAILURE;
}
Status = MuxInit(&I2cLibInstance);
if (Status != XST_SUCCESS) {
xil_printf("Si5324: Mux Init failed\n\r");
return XST_FAILURE;
}
for (Index = 0; Index < sizeof(InitTable)/8; Index++) {
WrBuffer[0] = InitTable[Index].RegIndex;
WrBuffer[1] = InitTable[Index].Value;
Status = I2cWriteData(&I2cLibInstance, WrBuffer, 2, IIC_SLAVE_ADDR);
if (Status != XST_SUCCESS) {
xil_printf("Si5324: Writing failed\n\r");
return XST_FAILURE;
}
}
return XST_SUCCESS;
}
#endif
#endif