Init Commit
This commit is contained in:
Jeremy Shen
@@ -0,0 +1,202 @@
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||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>module_ref</spirit:library>
|
||||
<spirit:name>dna_port_read</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>rst_n</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>rst_n</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.RST_N.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>clk</spirit:name>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
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||||
<spirit:name>CLK</spirit:name>
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||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>clk</spirit:name>
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||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>dna_port_read</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
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||||
<spirit:value>72795763</spirit:value>
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||||
</spirit:parameter>
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||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
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||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
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||||
<spirit:displayName>Simulation</spirit:displayName>
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||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
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||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>dna_port_read</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>72795763</spirit:value>
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||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
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||||
<spirit:name>xilinx_xpgui</spirit:name>
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||||
<spirit:displayName>UI Layout</spirit:displayName>
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||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rst_n</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>start_vld</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
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||||
<spirit:port>
|
||||
<spirit:name>read_vld</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
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||||
<spirit:port>
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||||
<spirit:name>dna_port</spirit:name>
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||||
<spirit:wire>
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||||
<spirit:direction>out</spirit:direction>
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||||
<spirit:vector>
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||||
<spirit:left spirit:format="long">56</spirit:left>
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||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
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||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
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||||
<spirit:name>choice_list_74b5137e</spirit:name>
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||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/dna_port_read_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
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||||
<spirit:userFileType>CHECKSUM_f92e9879</spirit:userFileType>
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||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:dna_port_read:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">dna_port_read_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>dna_port_read_v1_0</xilinx:displayName>
|
||||
<xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
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||||
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
|
||||
<xilinx:designToolContexts>
|
||||
<xilinx:designToolContext>IPI</xilinx:designToolContext>
|
||||
</xilinx:designToolContexts>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2026-05-27T08:35:39Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.2</xilinx:xilinxVersion>
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||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
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||||
</spirit:component>
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||||
@@ -0,0 +1,10 @@
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# Definitional proc to organize widgets for parameters.
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proc init_gui { IPINST } {
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ipgui::add_param $IPINST -name "Component_Name"
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#Adding Page
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ipgui::add_page $IPINST -name "Page 0"
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||||
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||||
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||||
}
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||||
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||||
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||||
@@ -0,0 +1,726 @@
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<?xml version="1.0" encoding="UTF-8"?>
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||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>module_ref</spirit:library>
|
||||
<spirit:name>mydna_read_v1_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s00_axi</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave>
|
||||
<spirit:memoryMapRef spirit:memoryMapRef="s00_axi"/>
|
||||
</spirit:slave>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWADDR</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axi_awaddr</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWPROT</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axi_awprot</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axi_awvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axi_awready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axi_wdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WSTRB</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axi_wstrb</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axi_wvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axi_wready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>BRESP</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axi_bresp</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>BVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axi_bvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>BREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axi_bready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ARADDR</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axi_araddr</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ARPROT</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axi_arprot</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ARVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axi_arvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ARREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axi_arready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axi_rdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RRESP</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axi_rresp</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axi_rvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axi_rready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s00_axi_aresetn</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axi_aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_ARESETN.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s00_axi_aclk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axi_aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_ACLK.ASSOCIATED_BUSIF">s00_axi</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_ACLK.ASSOCIATED_RESET">s00_axi_aresetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:memoryMaps>
|
||||
<spirit:memoryMap>
|
||||
<spirit:name>s00_axi</spirit:name>
|
||||
<spirit:displayName>s00_axi</spirit:displayName>
|
||||
<spirit:addressBlock>
|
||||
<spirit:name>reg0</spirit:name>
|
||||
<spirit:displayName>reg0</spirit:displayName>
|
||||
<spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:baseAddress>
|
||||
<spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="pow(2,(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH')) - 1) - 0 + 1)" spirit:minimum="4096" spirit:rangeType="long">4096</spirit:range>
|
||||
<spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH')) - 1) - 0 + 1">32</spirit:width>
|
||||
<spirit:usage>register</spirit:usage>
|
||||
</spirit:addressBlock>
|
||||
</spirit:memoryMap>
|
||||
</spirit:memoryMaps>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>mydna_read_v1_0</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>e3bf4311</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>mydna_read_v1_0</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>e3bf4311</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>start_vld</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>read_vld</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>dna_port</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">56</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axi_aclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axi_aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axi_awaddr</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH')) - 1)">3</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axi_awprot</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axi_awvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axi_awready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axi_wdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH')) - 1)">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axi_wstrb</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH')) / 8) - 1)">3</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axi_wvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axi_wready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axi_bresp</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">1</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axi_bvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axi_bready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axi_araddr</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH')) - 1)">3</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axi_arprot</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axi_arvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axi_arready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axi_rdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH')) - 1)">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axi_rresp</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">1</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axi_rvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axi_rready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>C S00 Axi Data Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH">32</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
|
||||
<spirit:displayName>C S00 Axi Addr Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_74b5137e</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/mydna_read_v1_0_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_c6886ca5</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:mydna_read_v1_0:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>C S00 Axi Data Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_DATA_WIDTH">32</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
|
||||
<spirit:displayName>C S00 Axi Addr Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_ADDR_WIDTH">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">mydna_read_v1_0_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>mydna_read_v1_0_v1_0</xilinx:displayName>
|
||||
<xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
|
||||
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
|
||||
<xilinx:designToolContexts>
|
||||
<xilinx:designToolContext>IPI</xilinx:designToolContext>
|
||||
</xilinx:designToolContexts>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2026-05-27T08:35:39Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.2</xilinx:xilinxVersion>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,40 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to validate C_S00_AXI_ADDR_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
||||
# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
||||
# Procedure called to validate C_S00_AXI_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,403 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
//Date : Mon May 25 14:51:47 2026
|
||||
//Host : mkb running 64-bit unknown
|
||||
//Command : generate_target system_wrapper.bd
|
||||
//Design : system_wrapper
|
||||
//Purpose : IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module system_wrapper
|
||||
(DDR_addr,
|
||||
DDR_ba,
|
||||
DDR_cas_n,
|
||||
DDR_ck_n,
|
||||
DDR_ck_p,
|
||||
DDR_cke,
|
||||
DDR_cs_n,
|
||||
DDR_dm,
|
||||
DDR_dq,
|
||||
DDR_dqs_n,
|
||||
DDR_dqs_p,
|
||||
DDR_odt,
|
||||
DDR_ras_n,
|
||||
DDR_reset_n,
|
||||
DDR_we_n,
|
||||
EMIO_0_tri_io,
|
||||
FIXED_IO_ddr_vrn,
|
||||
FIXED_IO_ddr_vrp,
|
||||
FIXED_IO_mio,
|
||||
FIXED_IO_ps_clk,
|
||||
FIXED_IO_ps_porb,
|
||||
FIXED_IO_ps_srstb);
|
||||
inout [14:0]DDR_addr;
|
||||
inout [2:0]DDR_ba;
|
||||
inout DDR_cas_n;
|
||||
inout DDR_ck_n;
|
||||
inout DDR_ck_p;
|
||||
inout DDR_cke;
|
||||
inout DDR_cs_n;
|
||||
inout [3:0]DDR_dm;
|
||||
inout [31:0]DDR_dq;
|
||||
inout [3:0]DDR_dqs_n;
|
||||
inout [3:0]DDR_dqs_p;
|
||||
inout DDR_odt;
|
||||
inout DDR_ras_n;
|
||||
inout DDR_reset_n;
|
||||
inout DDR_we_n;
|
||||
inout [32:0]EMIO_0_tri_io;
|
||||
inout FIXED_IO_ddr_vrn;
|
||||
inout FIXED_IO_ddr_vrp;
|
||||
inout [53:0]FIXED_IO_mio;
|
||||
inout FIXED_IO_ps_clk;
|
||||
inout FIXED_IO_ps_porb;
|
||||
inout FIXED_IO_ps_srstb;
|
||||
|
||||
wire [14:0]DDR_addr;
|
||||
wire [2:0]DDR_ba;
|
||||
wire DDR_cas_n;
|
||||
wire DDR_ck_n;
|
||||
wire DDR_ck_p;
|
||||
wire DDR_cke;
|
||||
wire DDR_cs_n;
|
||||
wire [3:0]DDR_dm;
|
||||
wire [31:0]DDR_dq;
|
||||
wire [3:0]DDR_dqs_n;
|
||||
wire [3:0]DDR_dqs_p;
|
||||
wire DDR_odt;
|
||||
wire DDR_ras_n;
|
||||
wire DDR_reset_n;
|
||||
wire DDR_we_n;
|
||||
wire [0:0]EMIO_0_tri_i_0;
|
||||
wire [1:1]EMIO_0_tri_i_1;
|
||||
wire [10:10]EMIO_0_tri_i_10;
|
||||
wire [11:11]EMIO_0_tri_i_11;
|
||||
wire [12:12]EMIO_0_tri_i_12;
|
||||
wire [13:13]EMIO_0_tri_i_13;
|
||||
wire [14:14]EMIO_0_tri_i_14;
|
||||
wire [15:15]EMIO_0_tri_i_15;
|
||||
wire [16:16]EMIO_0_tri_i_16;
|
||||
wire [17:17]EMIO_0_tri_i_17;
|
||||
wire [18:18]EMIO_0_tri_i_18;
|
||||
wire [19:19]EMIO_0_tri_i_19;
|
||||
wire [2:2]EMIO_0_tri_i_2;
|
||||
wire [20:20]EMIO_0_tri_i_20;
|
||||
wire [21:21]EMIO_0_tri_i_21;
|
||||
wire [22:22]EMIO_0_tri_i_22;
|
||||
wire [23:23]EMIO_0_tri_i_23;
|
||||
wire [24:24]EMIO_0_tri_i_24;
|
||||
wire [25:25]EMIO_0_tri_i_25;
|
||||
wire [26:26]EMIO_0_tri_i_26;
|
||||
wire [27:27]EMIO_0_tri_i_27;
|
||||
wire [28:28]EMIO_0_tri_i_28;
|
||||
wire [29:29]EMIO_0_tri_i_29;
|
||||
wire [3:3]EMIO_0_tri_i_3;
|
||||
wire [30:30]EMIO_0_tri_i_30;
|
||||
wire [31:31]EMIO_0_tri_i_31;
|
||||
wire [32:32]EMIO_0_tri_i_32;
|
||||
wire [4:4]EMIO_0_tri_i_4;
|
||||
wire [5:5]EMIO_0_tri_i_5;
|
||||
wire [6:6]EMIO_0_tri_i_6;
|
||||
wire [7:7]EMIO_0_tri_i_7;
|
||||
wire [8:8]EMIO_0_tri_i_8;
|
||||
wire [9:9]EMIO_0_tri_i_9;
|
||||
wire [0:0]EMIO_0_tri_io_0;
|
||||
wire [1:1]EMIO_0_tri_io_1;
|
||||
wire [10:10]EMIO_0_tri_io_10;
|
||||
wire [11:11]EMIO_0_tri_io_11;
|
||||
wire [12:12]EMIO_0_tri_io_12;
|
||||
wire [13:13]EMIO_0_tri_io_13;
|
||||
wire [14:14]EMIO_0_tri_io_14;
|
||||
wire [15:15]EMIO_0_tri_io_15;
|
||||
wire [16:16]EMIO_0_tri_io_16;
|
||||
wire [17:17]EMIO_0_tri_io_17;
|
||||
wire [18:18]EMIO_0_tri_io_18;
|
||||
wire [19:19]EMIO_0_tri_io_19;
|
||||
wire [2:2]EMIO_0_tri_io_2;
|
||||
wire [20:20]EMIO_0_tri_io_20;
|
||||
wire [21:21]EMIO_0_tri_io_21;
|
||||
wire [22:22]EMIO_0_tri_io_22;
|
||||
wire [23:23]EMIO_0_tri_io_23;
|
||||
wire [24:24]EMIO_0_tri_io_24;
|
||||
wire [25:25]EMIO_0_tri_io_25;
|
||||
wire [26:26]EMIO_0_tri_io_26;
|
||||
wire [27:27]EMIO_0_tri_io_27;
|
||||
wire [28:28]EMIO_0_tri_io_28;
|
||||
wire [29:29]EMIO_0_tri_io_29;
|
||||
wire [3:3]EMIO_0_tri_io_3;
|
||||
wire [30:30]EMIO_0_tri_io_30;
|
||||
wire [31:31]EMIO_0_tri_io_31;
|
||||
wire [32:32]EMIO_0_tri_io_32;
|
||||
wire [4:4]EMIO_0_tri_io_4;
|
||||
wire [5:5]EMIO_0_tri_io_5;
|
||||
wire [6:6]EMIO_0_tri_io_6;
|
||||
wire [7:7]EMIO_0_tri_io_7;
|
||||
wire [8:8]EMIO_0_tri_io_8;
|
||||
wire [9:9]EMIO_0_tri_io_9;
|
||||
wire [0:0]EMIO_0_tri_o_0;
|
||||
wire [1:1]EMIO_0_tri_o_1;
|
||||
wire [10:10]EMIO_0_tri_o_10;
|
||||
wire [11:11]EMIO_0_tri_o_11;
|
||||
wire [12:12]EMIO_0_tri_o_12;
|
||||
wire [13:13]EMIO_0_tri_o_13;
|
||||
wire [14:14]EMIO_0_tri_o_14;
|
||||
wire [15:15]EMIO_0_tri_o_15;
|
||||
wire [16:16]EMIO_0_tri_o_16;
|
||||
wire [17:17]EMIO_0_tri_o_17;
|
||||
wire [18:18]EMIO_0_tri_o_18;
|
||||
wire [19:19]EMIO_0_tri_o_19;
|
||||
wire [2:2]EMIO_0_tri_o_2;
|
||||
wire [20:20]EMIO_0_tri_o_20;
|
||||
wire [21:21]EMIO_0_tri_o_21;
|
||||
wire [22:22]EMIO_0_tri_o_22;
|
||||
wire [23:23]EMIO_0_tri_o_23;
|
||||
wire [24:24]EMIO_0_tri_o_24;
|
||||
wire [25:25]EMIO_0_tri_o_25;
|
||||
wire [26:26]EMIO_0_tri_o_26;
|
||||
wire [27:27]EMIO_0_tri_o_27;
|
||||
wire [28:28]EMIO_0_tri_o_28;
|
||||
wire [29:29]EMIO_0_tri_o_29;
|
||||
wire [3:3]EMIO_0_tri_o_3;
|
||||
wire [30:30]EMIO_0_tri_o_30;
|
||||
wire [31:31]EMIO_0_tri_o_31;
|
||||
wire [32:32]EMIO_0_tri_o_32;
|
||||
wire [4:4]EMIO_0_tri_o_4;
|
||||
wire [5:5]EMIO_0_tri_o_5;
|
||||
wire [6:6]EMIO_0_tri_o_6;
|
||||
wire [7:7]EMIO_0_tri_o_7;
|
||||
wire [8:8]EMIO_0_tri_o_8;
|
||||
wire [9:9]EMIO_0_tri_o_9;
|
||||
wire [0:0]EMIO_0_tri_t_0;
|
||||
wire [1:1]EMIO_0_tri_t_1;
|
||||
wire [10:10]EMIO_0_tri_t_10;
|
||||
wire [11:11]EMIO_0_tri_t_11;
|
||||
wire [12:12]EMIO_0_tri_t_12;
|
||||
wire [13:13]EMIO_0_tri_t_13;
|
||||
wire [14:14]EMIO_0_tri_t_14;
|
||||
wire [15:15]EMIO_0_tri_t_15;
|
||||
wire [16:16]EMIO_0_tri_t_16;
|
||||
wire [17:17]EMIO_0_tri_t_17;
|
||||
wire [18:18]EMIO_0_tri_t_18;
|
||||
wire [19:19]EMIO_0_tri_t_19;
|
||||
wire [2:2]EMIO_0_tri_t_2;
|
||||
wire [20:20]EMIO_0_tri_t_20;
|
||||
wire [21:21]EMIO_0_tri_t_21;
|
||||
wire [22:22]EMIO_0_tri_t_22;
|
||||
wire [23:23]EMIO_0_tri_t_23;
|
||||
wire [24:24]EMIO_0_tri_t_24;
|
||||
wire [25:25]EMIO_0_tri_t_25;
|
||||
wire [26:26]EMIO_0_tri_t_26;
|
||||
wire [27:27]EMIO_0_tri_t_27;
|
||||
wire [28:28]EMIO_0_tri_t_28;
|
||||
wire [29:29]EMIO_0_tri_t_29;
|
||||
wire [3:3]EMIO_0_tri_t_3;
|
||||
wire [30:30]EMIO_0_tri_t_30;
|
||||
wire [31:31]EMIO_0_tri_t_31;
|
||||
wire [32:32]EMIO_0_tri_t_32;
|
||||
wire [4:4]EMIO_0_tri_t_4;
|
||||
wire [5:5]EMIO_0_tri_t_5;
|
||||
wire [6:6]EMIO_0_tri_t_6;
|
||||
wire [7:7]EMIO_0_tri_t_7;
|
||||
wire [8:8]EMIO_0_tri_t_8;
|
||||
wire [9:9]EMIO_0_tri_t_9;
|
||||
wire FIXED_IO_ddr_vrn;
|
||||
wire FIXED_IO_ddr_vrp;
|
||||
wire [53:0]FIXED_IO_mio;
|
||||
wire FIXED_IO_ps_clk;
|
||||
wire FIXED_IO_ps_porb;
|
||||
wire FIXED_IO_ps_srstb;
|
||||
|
||||
IOBUF EMIO_0_tri_iobuf_0
|
||||
(.I(EMIO_0_tri_o_0),
|
||||
.IO(EMIO_0_tri_io[0]),
|
||||
.O(EMIO_0_tri_i_0),
|
||||
.T(EMIO_0_tri_t_0));
|
||||
IOBUF EMIO_0_tri_iobuf_1
|
||||
(.I(EMIO_0_tri_o_1),
|
||||
.IO(EMIO_0_tri_io[1]),
|
||||
.O(EMIO_0_tri_i_1),
|
||||
.T(EMIO_0_tri_t_1));
|
||||
IOBUF EMIO_0_tri_iobuf_10
|
||||
(.I(EMIO_0_tri_o_10),
|
||||
.IO(EMIO_0_tri_io[10]),
|
||||
.O(EMIO_0_tri_i_10),
|
||||
.T(EMIO_0_tri_t_10));
|
||||
IOBUF EMIO_0_tri_iobuf_11
|
||||
(.I(EMIO_0_tri_o_11),
|
||||
.IO(EMIO_0_tri_io[11]),
|
||||
.O(EMIO_0_tri_i_11),
|
||||
.T(EMIO_0_tri_t_11));
|
||||
IOBUF EMIO_0_tri_iobuf_12
|
||||
(.I(EMIO_0_tri_o_12),
|
||||
.IO(EMIO_0_tri_io[12]),
|
||||
.O(EMIO_0_tri_i_12),
|
||||
.T(EMIO_0_tri_t_12));
|
||||
IOBUF EMIO_0_tri_iobuf_13
|
||||
(.I(EMIO_0_tri_o_13),
|
||||
.IO(EMIO_0_tri_io[13]),
|
||||
.O(EMIO_0_tri_i_13),
|
||||
.T(EMIO_0_tri_t_13));
|
||||
IOBUF EMIO_0_tri_iobuf_14
|
||||
(.I(EMIO_0_tri_o_14),
|
||||
.IO(EMIO_0_tri_io[14]),
|
||||
.O(EMIO_0_tri_i_14),
|
||||
.T(EMIO_0_tri_t_14));
|
||||
IOBUF EMIO_0_tri_iobuf_15
|
||||
(.I(EMIO_0_tri_o_15),
|
||||
.IO(EMIO_0_tri_io[15]),
|
||||
.O(EMIO_0_tri_i_15),
|
||||
.T(EMIO_0_tri_t_15));
|
||||
IOBUF EMIO_0_tri_iobuf_16
|
||||
(.I(EMIO_0_tri_o_16),
|
||||
.IO(EMIO_0_tri_io[16]),
|
||||
.O(EMIO_0_tri_i_16),
|
||||
.T(EMIO_0_tri_t_16));
|
||||
IOBUF EMIO_0_tri_iobuf_17
|
||||
(.I(EMIO_0_tri_o_17),
|
||||
.IO(EMIO_0_tri_io[17]),
|
||||
.O(EMIO_0_tri_i_17),
|
||||
.T(EMIO_0_tri_t_17));
|
||||
IOBUF EMIO_0_tri_iobuf_18
|
||||
(.I(EMIO_0_tri_o_18),
|
||||
.IO(EMIO_0_tri_io[18]),
|
||||
.O(EMIO_0_tri_i_18),
|
||||
.T(EMIO_0_tri_t_18));
|
||||
IOBUF EMIO_0_tri_iobuf_19
|
||||
(.I(EMIO_0_tri_o_19),
|
||||
.IO(EMIO_0_tri_io[19]),
|
||||
.O(EMIO_0_tri_i_19),
|
||||
.T(EMIO_0_tri_t_19));
|
||||
IOBUF EMIO_0_tri_iobuf_2
|
||||
(.I(EMIO_0_tri_o_2),
|
||||
.IO(EMIO_0_tri_io[2]),
|
||||
.O(EMIO_0_tri_i_2),
|
||||
.T(EMIO_0_tri_t_2));
|
||||
IOBUF EMIO_0_tri_iobuf_20
|
||||
(.I(EMIO_0_tri_o_20),
|
||||
.IO(EMIO_0_tri_io[20]),
|
||||
.O(EMIO_0_tri_i_20),
|
||||
.T(EMIO_0_tri_t_20));
|
||||
IOBUF EMIO_0_tri_iobuf_21
|
||||
(.I(EMIO_0_tri_o_21),
|
||||
.IO(EMIO_0_tri_io[21]),
|
||||
.O(EMIO_0_tri_i_21),
|
||||
.T(EMIO_0_tri_t_21));
|
||||
IOBUF EMIO_0_tri_iobuf_22
|
||||
(.I(EMIO_0_tri_o_22),
|
||||
.IO(EMIO_0_tri_io[22]),
|
||||
.O(EMIO_0_tri_i_22),
|
||||
.T(EMIO_0_tri_t_22));
|
||||
IOBUF EMIO_0_tri_iobuf_23
|
||||
(.I(EMIO_0_tri_o_23),
|
||||
.IO(EMIO_0_tri_io[23]),
|
||||
.O(EMIO_0_tri_i_23),
|
||||
.T(EMIO_0_tri_t_23));
|
||||
IOBUF EMIO_0_tri_iobuf_24
|
||||
(.I(EMIO_0_tri_o_24),
|
||||
.IO(EMIO_0_tri_io[24]),
|
||||
.O(EMIO_0_tri_i_24),
|
||||
.T(EMIO_0_tri_t_24));
|
||||
IOBUF EMIO_0_tri_iobuf_25
|
||||
(.I(EMIO_0_tri_o_25),
|
||||
.IO(EMIO_0_tri_io[25]),
|
||||
.O(EMIO_0_tri_i_25),
|
||||
.T(EMIO_0_tri_t_25));
|
||||
IOBUF EMIO_0_tri_iobuf_26
|
||||
(.I(EMIO_0_tri_o_26),
|
||||
.IO(EMIO_0_tri_io[26]),
|
||||
.O(EMIO_0_tri_i_26),
|
||||
.T(EMIO_0_tri_t_26));
|
||||
IOBUF EMIO_0_tri_iobuf_27
|
||||
(.I(EMIO_0_tri_o_27),
|
||||
.IO(EMIO_0_tri_io[27]),
|
||||
.O(EMIO_0_tri_i_27),
|
||||
.T(EMIO_0_tri_t_27));
|
||||
IOBUF EMIO_0_tri_iobuf_28
|
||||
(.I(EMIO_0_tri_o_28),
|
||||
.IO(EMIO_0_tri_io[28]),
|
||||
.O(EMIO_0_tri_i_28),
|
||||
.T(EMIO_0_tri_t_28));
|
||||
IOBUF EMIO_0_tri_iobuf_29
|
||||
(.I(EMIO_0_tri_o_29),
|
||||
.IO(EMIO_0_tri_io[29]),
|
||||
.O(EMIO_0_tri_i_29),
|
||||
.T(EMIO_0_tri_t_29));
|
||||
IOBUF EMIO_0_tri_iobuf_3
|
||||
(.I(EMIO_0_tri_o_3),
|
||||
.IO(EMIO_0_tri_io[3]),
|
||||
.O(EMIO_0_tri_i_3),
|
||||
.T(EMIO_0_tri_t_3));
|
||||
IOBUF EMIO_0_tri_iobuf_30
|
||||
(.I(EMIO_0_tri_o_30),
|
||||
.IO(EMIO_0_tri_io[30]),
|
||||
.O(EMIO_0_tri_i_30),
|
||||
.T(EMIO_0_tri_t_30));
|
||||
IOBUF EMIO_0_tri_iobuf_31
|
||||
(.I(EMIO_0_tri_o_31),
|
||||
.IO(EMIO_0_tri_io[31]),
|
||||
.O(EMIO_0_tri_i_31),
|
||||
.T(EMIO_0_tri_t_31));
|
||||
IOBUF EMIO_0_tri_iobuf_32
|
||||
(.I(EMIO_0_tri_o_32),
|
||||
.IO(EMIO_0_tri_io[32]),
|
||||
.O(EMIO_0_tri_i_32),
|
||||
.T(EMIO_0_tri_t_32));
|
||||
IOBUF EMIO_0_tri_iobuf_4
|
||||
(.I(EMIO_0_tri_o_4),
|
||||
.IO(EMIO_0_tri_io[4]),
|
||||
.O(EMIO_0_tri_i_4),
|
||||
.T(EMIO_0_tri_t_4));
|
||||
IOBUF EMIO_0_tri_iobuf_5
|
||||
(.I(EMIO_0_tri_o_5),
|
||||
.IO(EMIO_0_tri_io[5]),
|
||||
.O(EMIO_0_tri_i_5),
|
||||
.T(EMIO_0_tri_t_5));
|
||||
IOBUF EMIO_0_tri_iobuf_6
|
||||
(.I(EMIO_0_tri_o_6),
|
||||
.IO(EMIO_0_tri_io[6]),
|
||||
.O(EMIO_0_tri_i_6),
|
||||
.T(EMIO_0_tri_t_6));
|
||||
IOBUF EMIO_0_tri_iobuf_7
|
||||
(.I(EMIO_0_tri_o_7),
|
||||
.IO(EMIO_0_tri_io[7]),
|
||||
.O(EMIO_0_tri_i_7),
|
||||
.T(EMIO_0_tri_t_7));
|
||||
IOBUF EMIO_0_tri_iobuf_8
|
||||
(.I(EMIO_0_tri_o_8),
|
||||
.IO(EMIO_0_tri_io[8]),
|
||||
.O(EMIO_0_tri_i_8),
|
||||
.T(EMIO_0_tri_t_8));
|
||||
IOBUF EMIO_0_tri_iobuf_9
|
||||
(.I(EMIO_0_tri_o_9),
|
||||
.IO(EMIO_0_tri_io[9]),
|
||||
.O(EMIO_0_tri_i_9),
|
||||
.T(EMIO_0_tri_t_9));
|
||||
system system_i
|
||||
(.DDR_addr(DDR_addr),
|
||||
.DDR_ba(DDR_ba),
|
||||
.DDR_cas_n(DDR_cas_n),
|
||||
.DDR_ck_n(DDR_ck_n),
|
||||
.DDR_ck_p(DDR_ck_p),
|
||||
.DDR_cke(DDR_cke),
|
||||
.DDR_cs_n(DDR_cs_n),
|
||||
.DDR_dm(DDR_dm),
|
||||
.DDR_dq(DDR_dq),
|
||||
.DDR_dqs_n(DDR_dqs_n),
|
||||
.DDR_dqs_p(DDR_dqs_p),
|
||||
.DDR_odt(DDR_odt),
|
||||
.DDR_ras_n(DDR_ras_n),
|
||||
.DDR_reset_n(DDR_reset_n),
|
||||
.DDR_we_n(DDR_we_n),
|
||||
.EMIO_0_tri_i({EMIO_0_tri_i_32,EMIO_0_tri_i_31,EMIO_0_tri_i_30,EMIO_0_tri_i_29,EMIO_0_tri_i_28,EMIO_0_tri_i_27,EMIO_0_tri_i_26,EMIO_0_tri_i_25,EMIO_0_tri_i_24,EMIO_0_tri_i_23,EMIO_0_tri_i_22,EMIO_0_tri_i_21,EMIO_0_tri_i_20,EMIO_0_tri_i_19,EMIO_0_tri_i_18,EMIO_0_tri_i_17,EMIO_0_tri_i_16,EMIO_0_tri_i_15,EMIO_0_tri_i_14,EMIO_0_tri_i_13,EMIO_0_tri_i_12,EMIO_0_tri_i_11,EMIO_0_tri_i_10,EMIO_0_tri_i_9,EMIO_0_tri_i_8,EMIO_0_tri_i_7,EMIO_0_tri_i_6,EMIO_0_tri_i_5,EMIO_0_tri_i_4,EMIO_0_tri_i_3,EMIO_0_tri_i_2,EMIO_0_tri_i_1,EMIO_0_tri_i_0}),
|
||||
.EMIO_0_tri_o({EMIO_0_tri_o_32,EMIO_0_tri_o_31,EMIO_0_tri_o_30,EMIO_0_tri_o_29,EMIO_0_tri_o_28,EMIO_0_tri_o_27,EMIO_0_tri_o_26,EMIO_0_tri_o_25,EMIO_0_tri_o_24,EMIO_0_tri_o_23,EMIO_0_tri_o_22,EMIO_0_tri_o_21,EMIO_0_tri_o_20,EMIO_0_tri_o_19,EMIO_0_tri_o_18,EMIO_0_tri_o_17,EMIO_0_tri_o_16,EMIO_0_tri_o_15,EMIO_0_tri_o_14,EMIO_0_tri_o_13,EMIO_0_tri_o_12,EMIO_0_tri_o_11,EMIO_0_tri_o_10,EMIO_0_tri_o_9,EMIO_0_tri_o_8,EMIO_0_tri_o_7,EMIO_0_tri_o_6,EMIO_0_tri_o_5,EMIO_0_tri_o_4,EMIO_0_tri_o_3,EMIO_0_tri_o_2,EMIO_0_tri_o_1,EMIO_0_tri_o_0}),
|
||||
.EMIO_0_tri_t({EMIO_0_tri_t_32,EMIO_0_tri_t_31,EMIO_0_tri_t_30,EMIO_0_tri_t_29,EMIO_0_tri_t_28,EMIO_0_tri_t_27,EMIO_0_tri_t_26,EMIO_0_tri_t_25,EMIO_0_tri_t_24,EMIO_0_tri_t_23,EMIO_0_tri_t_22,EMIO_0_tri_t_21,EMIO_0_tri_t_20,EMIO_0_tri_t_19,EMIO_0_tri_t_18,EMIO_0_tri_t_17,EMIO_0_tri_t_16,EMIO_0_tri_t_15,EMIO_0_tri_t_14,EMIO_0_tri_t_13,EMIO_0_tri_t_12,EMIO_0_tri_t_11,EMIO_0_tri_t_10,EMIO_0_tri_t_9,EMIO_0_tri_t_8,EMIO_0_tri_t_7,EMIO_0_tri_t_6,EMIO_0_tri_t_5,EMIO_0_tri_t_4,EMIO_0_tri_t_3,EMIO_0_tri_t_2,EMIO_0_tri_t_1,EMIO_0_tri_t_0}),
|
||||
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
|
||||
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
|
||||
.FIXED_IO_mio(FIXED_IO_mio),
|
||||
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
|
||||
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
|
||||
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,573 @@
|
||||
#ifndef IP_SYSTEM_AUTO_PC_0_H_
|
||||
#define IP_SYSTEM_AUTO_PC_0_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
#include "system_auto_pc_0_sc.h"
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XILINX_SIMULATOR
|
||||
class DllExport system_auto_pc_0 : public system_auto_pc_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_auto_pc_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // XILINX_SIMULATOR
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
class DllExport system_auto_pc_0 : public system_auto_pc_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_auto_pc_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // XM_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef RIVIERA
|
||||
class DllExport system_auto_pc_0 : public system_auto_pc_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_auto_pc_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // RIVIERA
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef VCSSYSTEMC
|
||||
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport system_auto_pc_0 : public system_auto_pc_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_auto_pc_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // VCSSYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport system_auto_pc_0 : public system_auto_pc_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_auto_pc_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // MTI_SYSTEMC
|
||||
#endif // IP_SYSTEM_AUTO_PC_0_H_
|
||||
@@ -0,0 +1,354 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
|
||||
// IP Revision: 29
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_auto_pc_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awprot,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_araddr,
|
||||
m_axi_arprot,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [11 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [3 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [1 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
|
||||
input wire [11 : 0] s_axi_wid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [11 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [11 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [3 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [1 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [11 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4,\
|
||||
NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS \
|
||||
4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
axi_protocol_converter_v2_1_29_axi_protocol_converter #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_M_AXI_PROTOCOL(2),
|
||||
.C_S_AXI_PROTOCOL(1),
|
||||
.C_IGNORE_ID(0),
|
||||
.C_AXI_ID_WIDTH(12),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(32),
|
||||
.C_AXI_SUPPORTS_WRITE(1),
|
||||
.C_AXI_SUPPORTS_READ(1),
|
||||
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_TRANSLATION_MODE(2)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(4'H0),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(s_axi_wid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(4'H0),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(12'H000),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(1'H0),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(12'H000),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1'H0),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
@@ -0,0 +1,97 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#include "system_auto_pc_0_sc.h"
|
||||
|
||||
#include "axi_protocol_converter.h"
|
||||
|
||||
#include <map>
|
||||
#include <string>
|
||||
|
||||
system_auto_pc_0_sc::system_auto_pc_0_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
|
||||
{
|
||||
// configure connectivity manager
|
||||
xsc::utils::xsc_sim_manager::addInstance("system_auto_pc_0", this);
|
||||
|
||||
// initialize module
|
||||
xsc::common_cpp::properties model_param_props;
|
||||
model_param_props.addLong("C_M_AXI_PROTOCOL", "2");
|
||||
model_param_props.addLong("C_S_AXI_PROTOCOL", "1");
|
||||
model_param_props.addLong("C_IGNORE_ID", "0");
|
||||
model_param_props.addLong("C_AXI_ID_WIDTH", "12");
|
||||
model_param_props.addLong("C_AXI_ADDR_WIDTH", "32");
|
||||
model_param_props.addLong("C_AXI_DATA_WIDTH", "32");
|
||||
model_param_props.addLong("C_AXI_SUPPORTS_WRITE", "1");
|
||||
model_param_props.addLong("C_AXI_SUPPORTS_READ", "1");
|
||||
model_param_props.addLong("C_AXI_SUPPORTS_USER_SIGNALS", "0");
|
||||
model_param_props.addLong("C_AXI_AWUSER_WIDTH", "1");
|
||||
model_param_props.addLong("C_AXI_ARUSER_WIDTH", "1");
|
||||
model_param_props.addLong("C_AXI_WUSER_WIDTH", "1");
|
||||
model_param_props.addLong("C_AXI_RUSER_WIDTH", "1");
|
||||
model_param_props.addLong("C_AXI_BUSER_WIDTH", "1");
|
||||
model_param_props.addLong("C_TRANSLATION_MODE", "2");
|
||||
model_param_props.addString("C_FAMILY", "zynq");
|
||||
model_param_props.addString("COMPONENT_NAME", "system_auto_pc_0");
|
||||
|
||||
mp_impl = new axi_protocol_converter("inst", model_param_props);
|
||||
|
||||
// initialize AXI sockets
|
||||
target_rd_socket = mp_impl->target_rd_socket;
|
||||
target_wr_socket = mp_impl->target_wr_socket;
|
||||
initiator_rd_socket = mp_impl->initiator_rd_socket;
|
||||
initiator_wr_socket = mp_impl->initiator_wr_socket;
|
||||
}
|
||||
|
||||
system_auto_pc_0_sc::~system_auto_pc_0_sc()
|
||||
{
|
||||
xsc::utils::xsc_sim_manager::clean();
|
||||
|
||||
delete mp_impl;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,98 @@
|
||||
#ifndef IP_SYSTEM_AUTO_PC_0_SC_H_
|
||||
#define IP_SYSTEM_AUTO_PC_0_SC_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
class axi_protocol_converter;
|
||||
|
||||
class DllExport system_auto_pc_0_sc : public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
|
||||
system_auto_pc_0_sc(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_auto_pc_0_sc();
|
||||
|
||||
// module socket-to-socket AXI TLM interfaces
|
||||
|
||||
xtlm::xtlm_aximm_target_socket* target_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* target_wr_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
|
||||
|
||||
// module socket-to-socket TLM interfaces
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
axi_protocol_converter* mp_impl;
|
||||
|
||||
private:
|
||||
|
||||
system_auto_pc_0_sc(const system_auto_pc_0_sc&);
|
||||
const system_auto_pc_0_sc& operator=(const system_auto_pc_0_sc&);
|
||||
|
||||
};
|
||||
|
||||
#endif // IP_SYSTEM_AUTO_PC_0_SC_H_
|
||||
@@ -0,0 +1,197 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------------
|
||||
// Filename: system_auto_pc_0_stub.sv
|
||||
// Description: This HDL file is intended to be used with following simulators only:
|
||||
//
|
||||
// Vivado Simulator (XSim)
|
||||
// Cadence Xcelium Simulator
|
||||
//
|
||||
//------------------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`ifdef XILINX_SIMULATOR
|
||||
|
||||
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||
`define XILINX_SIMULATOR_BITASBOOL
|
||||
typedef bit bit_as_bool;
|
||||
`endif
|
||||
|
||||
(* SC_MODULE_EXPORT *)
|
||||
module system_auto_pc_0 (
|
||||
input bit_as_bool aclk,
|
||||
input bit_as_bool aresetn,
|
||||
input bit [11 : 0] s_axi_awid,
|
||||
input bit [31 : 0] s_axi_awaddr,
|
||||
input bit [3 : 0] s_axi_awlen,
|
||||
input bit [2 : 0] s_axi_awsize,
|
||||
input bit [1 : 0] s_axi_awburst,
|
||||
input bit [1 : 0] s_axi_awlock,
|
||||
input bit [3 : 0] s_axi_awcache,
|
||||
input bit [2 : 0] s_axi_awprot,
|
||||
input bit [3 : 0] s_axi_awqos,
|
||||
input bit_as_bool s_axi_awvalid,
|
||||
output bit_as_bool s_axi_awready,
|
||||
input bit [11 : 0] s_axi_wid,
|
||||
input bit [31 : 0] s_axi_wdata,
|
||||
input bit [3 : 0] s_axi_wstrb,
|
||||
input bit_as_bool s_axi_wlast,
|
||||
input bit_as_bool s_axi_wvalid,
|
||||
output bit_as_bool s_axi_wready,
|
||||
output bit [11 : 0] s_axi_bid,
|
||||
output bit [1 : 0] s_axi_bresp,
|
||||
output bit_as_bool s_axi_bvalid,
|
||||
input bit_as_bool s_axi_bready,
|
||||
input bit [11 : 0] s_axi_arid,
|
||||
input bit [31 : 0] s_axi_araddr,
|
||||
input bit [3 : 0] s_axi_arlen,
|
||||
input bit [2 : 0] s_axi_arsize,
|
||||
input bit [1 : 0] s_axi_arburst,
|
||||
input bit [1 : 0] s_axi_arlock,
|
||||
input bit [3 : 0] s_axi_arcache,
|
||||
input bit [2 : 0] s_axi_arprot,
|
||||
input bit [3 : 0] s_axi_arqos,
|
||||
input bit_as_bool s_axi_arvalid,
|
||||
output bit_as_bool s_axi_arready,
|
||||
output bit [11 : 0] s_axi_rid,
|
||||
output bit [31 : 0] s_axi_rdata,
|
||||
output bit [1 : 0] s_axi_rresp,
|
||||
output bit_as_bool s_axi_rlast,
|
||||
output bit_as_bool s_axi_rvalid,
|
||||
input bit_as_bool s_axi_rready,
|
||||
output bit [31 : 0] m_axi_awaddr,
|
||||
output bit [2 : 0] m_axi_awprot,
|
||||
output bit_as_bool m_axi_awvalid,
|
||||
input bit_as_bool m_axi_awready,
|
||||
output bit [31 : 0] m_axi_wdata,
|
||||
output bit [3 : 0] m_axi_wstrb,
|
||||
output bit_as_bool m_axi_wvalid,
|
||||
input bit_as_bool m_axi_wready,
|
||||
input bit [1 : 0] m_axi_bresp,
|
||||
input bit_as_bool m_axi_bvalid,
|
||||
output bit_as_bool m_axi_bready,
|
||||
output bit [31 : 0] m_axi_araddr,
|
||||
output bit [2 : 0] m_axi_arprot,
|
||||
output bit_as_bool m_axi_arvalid,
|
||||
input bit_as_bool m_axi_arready,
|
||||
input bit [31 : 0] m_axi_rdata,
|
||||
input bit [1 : 0] m_axi_rresp,
|
||||
input bit_as_bool m_axi_rvalid,
|
||||
output bit_as_bool m_axi_rready
|
||||
);
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef XCELIUM
|
||||
(* XMSC_MODULE_EXPORT *)
|
||||
module system_auto_pc_0 (aclk,aresetn,s_axi_awid,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wid,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_arid,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rid,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awprot,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arprot,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rvalid,m_axi_rready)
|
||||
(* integer foreign = "SystemC";
|
||||
*);
|
||||
input bit aclk;
|
||||
input bit aresetn;
|
||||
input bit [11 : 0] s_axi_awid;
|
||||
input bit [31 : 0] s_axi_awaddr;
|
||||
input bit [3 : 0] s_axi_awlen;
|
||||
input bit [2 : 0] s_axi_awsize;
|
||||
input bit [1 : 0] s_axi_awburst;
|
||||
input bit [1 : 0] s_axi_awlock;
|
||||
input bit [3 : 0] s_axi_awcache;
|
||||
input bit [2 : 0] s_axi_awprot;
|
||||
input bit [3 : 0] s_axi_awqos;
|
||||
input bit s_axi_awvalid;
|
||||
output wire s_axi_awready;
|
||||
input bit [11 : 0] s_axi_wid;
|
||||
input bit [31 : 0] s_axi_wdata;
|
||||
input bit [3 : 0] s_axi_wstrb;
|
||||
input bit s_axi_wlast;
|
||||
input bit s_axi_wvalid;
|
||||
output wire s_axi_wready;
|
||||
output wire [11 : 0] s_axi_bid;
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
output wire s_axi_bvalid;
|
||||
input bit s_axi_bready;
|
||||
input bit [11 : 0] s_axi_arid;
|
||||
input bit [31 : 0] s_axi_araddr;
|
||||
input bit [3 : 0] s_axi_arlen;
|
||||
input bit [2 : 0] s_axi_arsize;
|
||||
input bit [1 : 0] s_axi_arburst;
|
||||
input bit [1 : 0] s_axi_arlock;
|
||||
input bit [3 : 0] s_axi_arcache;
|
||||
input bit [2 : 0] s_axi_arprot;
|
||||
input bit [3 : 0] s_axi_arqos;
|
||||
input bit s_axi_arvalid;
|
||||
output wire s_axi_arready;
|
||||
output wire [11 : 0] s_axi_rid;
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
output wire s_axi_rlast;
|
||||
output wire s_axi_rvalid;
|
||||
input bit s_axi_rready;
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
output wire m_axi_awvalid;
|
||||
input bit m_axi_awready;
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
output wire m_axi_wvalid;
|
||||
input bit m_axi_wready;
|
||||
input bit [1 : 0] m_axi_bresp;
|
||||
input bit m_axi_bvalid;
|
||||
output wire m_axi_bready;
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
output wire m_axi_arvalid;
|
||||
input bit m_axi_arready;
|
||||
input bit [31 : 0] m_axi_rdata;
|
||||
input bit [1 : 0] m_axi_rresp;
|
||||
input bit m_axi_rvalid;
|
||||
output wire m_axi_rready;
|
||||
endmodule
|
||||
`endif
|
||||
@@ -0,0 +1,70 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
#include "axi_protocol_converter.h"
|
||||
#include <sstream>
|
||||
|
||||
axi_protocol_converter::axi_protocol_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&) :
|
||||
sc_module(module_name) {
|
||||
initiator_rd_socket = new xtlm::xtlm_aximm_initiator_socket("initiator_rd_socket",32);
|
||||
initiator_wr_socket = new xtlm::xtlm_aximm_initiator_socket("initiator_wr_socket",32);
|
||||
target_rd_socket = new xtlm::xtlm_aximm_target_socket("target_rd_socket",32);
|
||||
target_wr_socket = new xtlm::xtlm_aximm_target_socket("target_wr_socket",32);
|
||||
P1 = new xtlm::xtlm_aximm_passthru_module("P1");
|
||||
P2 = new xtlm::xtlm_aximm_passthru_module("P2");
|
||||
P1->initiator_socket->bind(*initiator_rd_socket);
|
||||
P2->initiator_socket->bind(*initiator_wr_socket);
|
||||
target_rd_socket->bind(*(P1->target_socket));
|
||||
target_wr_socket->bind(*(P2->target_socket));
|
||||
}
|
||||
|
||||
axi_protocol_converter::~axi_protocol_converter() {
|
||||
delete initiator_wr_socket;
|
||||
delete initiator_rd_socket;
|
||||
delete target_wr_socket;
|
||||
delete target_rd_socket;
|
||||
delete P1;
|
||||
delete P2;
|
||||
}
|
||||
@@ -0,0 +1,69 @@
|
||||
// (c) Copyright 1995-2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
#ifndef _axi_protocol_converter_
|
||||
#define _axi_protocol_converter_
|
||||
#include <xtlm.h>
|
||||
#include <utils/xtlm_aximm_passthru_module.h>
|
||||
#include <systemc>
|
||||
|
||||
class axi_protocol_converter:public sc_module{
|
||||
public:
|
||||
axi_protocol_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&);
|
||||
virtual ~axi_protocol_converter();
|
||||
SC_HAS_PROCESS(axi_protocol_converter);
|
||||
xtlm::xtlm_aximm_target_socket* target_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* target_wr_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
|
||||
sc_in<bool> aclk;
|
||||
sc_in<bool> aresetn;
|
||||
private:
|
||||
xtlm::xtlm_aximm_passthru_module *P1;
|
||||
xtlm::xtlm_aximm_passthru_module *P2;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,356 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
|
||||
// IP Revision: 29
|
||||
|
||||
(* X_CORE_INFO = "axi_protocol_converter_v2_1_29_axi_protocol_converter,Vivado 2023.2" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_auto_pc_0,axi_protocol_converter_v2_1_29_axi_protocol_converter,{}" *)
|
||||
(* CORE_GENERATION_INFO = "system_auto_pc_0,axi_protocol_converter_v2_1_29_axi_protocol_converter,{x_ipProduct=Vivado 2023.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=29,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_W\
|
||||
IDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_auto_pc_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awprot,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_araddr,
|
||||
m_axi_arprot,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [11 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [3 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [1 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
|
||||
input wire [11 : 0] s_axi_wid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [11 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [11 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [3 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [1 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [11 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4,\
|
||||
NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS \
|
||||
4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
axi_protocol_converter_v2_1_29_axi_protocol_converter #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_M_AXI_PROTOCOL(2),
|
||||
.C_S_AXI_PROTOCOL(1),
|
||||
.C_IGNORE_ID(0),
|
||||
.C_AXI_ID_WIDTH(12),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(32),
|
||||
.C_AXI_SUPPORTS_WRITE(1),
|
||||
.C_AXI_SUPPORTS_READ(1),
|
||||
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_TRANSLATION_MODE(2)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(4'H0),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(s_axi_wid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(4'H0),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(12'H000),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(1'H0),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(12'H000),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1'H0),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,50 @@
|
||||
################################################################################
|
||||
# (c) Copyright 2013 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Advanced Micro Devices, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
create_clock -period 100.0 -name aclk [get_ports aclk]
|
||||
|
||||
+82
@@ -0,0 +1,82 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:module_ref:dna_port_read:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* IP_DEFINITION_SOURCE = "module_ref" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_dna_port_read_0_0 (
|
||||
clk,
|
||||
rst_n,
|
||||
start_vld,
|
||||
read_vld,
|
||||
dna_port
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
|
||||
input wire clk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 rst_n RST" *)
|
||||
input wire rst_n;
|
||||
input wire start_vld;
|
||||
output wire read_vld;
|
||||
output wire [56 : 0] dna_port;
|
||||
|
||||
dna_port_read inst (
|
||||
.clk(clk),
|
||||
.rst_n(rst_n),
|
||||
.start_vld(start_vld),
|
||||
.read_vld(read_vld),
|
||||
.dna_port(dna_port)
|
||||
);
|
||||
endmodule
|
||||
+83
@@ -0,0 +1,83 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:module_ref:dna_port_read:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
(* X_CORE_INFO = "dna_port_read,Vivado 2023.2" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_dna_port_read_0_0,dna_port_read,{}" *)
|
||||
(* CORE_GENERATION_INFO = "system_dna_port_read_0_0,dna_port_read,{x_ipProduct=Vivado 2023.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=dna_port_read,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED}" *)
|
||||
(* IP_DEFINITION_SOURCE = "module_ref" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_dna_port_read_0_0 (
|
||||
clk,
|
||||
rst_n,
|
||||
start_vld,
|
||||
read_vld,
|
||||
dna_port
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
|
||||
input wire clk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 rst_n RST" *)
|
||||
input wire rst_n;
|
||||
input wire start_vld;
|
||||
output wire read_vld;
|
||||
output wire [56 : 0] dna_port;
|
||||
|
||||
dna_port_read inst (
|
||||
.clk(clk),
|
||||
.rst_n(rst_n),
|
||||
.start_vld(start_vld),
|
||||
.read_vld(read_vld),
|
||||
.dna_port(dna_port)
|
||||
);
|
||||
endmodule
|
||||
+312
@@ -0,0 +1,312 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>system_dna_port_read_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>rst_n</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>rst_n</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.RST_N.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST_N.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">system_processing_system7_0_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>dna_port_read</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:b22a9507</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:modelName>dna_port_read</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a962cfc1</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a962cfc1</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>system_dna_port_read_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon May 25 06:51:56 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:b22a9507</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>system_dna_port_read_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogsynthesiswrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon May 25 06:51:56 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a962cfc1</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rst_n</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>start_vld</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>read_vld</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>dna_port</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">56</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/system_dna_port_read_0_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/system_dna_port_read_0_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:dna_port_read:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">system_dna_port_read_0_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>dna_port_read_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST_N.POLARITY" xilinx:valuePermission="bd_and_user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2018.3</xilinx:xilinxVersion>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+163
@@ -0,0 +1,163 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:module_ref:mydna_read_v1_0:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* IP_DEFINITION_SOURCE = "module_ref" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_mydna_read_v1_0_0_0 (
|
||||
start_vld,
|
||||
read_vld,
|
||||
dna_port,
|
||||
s00_axi_aclk,
|
||||
s00_axi_aresetn,
|
||||
s00_axi_awaddr,
|
||||
s00_axi_awprot,
|
||||
s00_axi_awvalid,
|
||||
s00_axi_awready,
|
||||
s00_axi_wdata,
|
||||
s00_axi_wstrb,
|
||||
s00_axi_wvalid,
|
||||
s00_axi_wready,
|
||||
s00_axi_bresp,
|
||||
s00_axi_bvalid,
|
||||
s00_axi_bready,
|
||||
s00_axi_araddr,
|
||||
s00_axi_arprot,
|
||||
s00_axi_arvalid,
|
||||
s00_axi_arready,
|
||||
s00_axi_rdata,
|
||||
s00_axi_rresp,
|
||||
s00_axi_rvalid,
|
||||
s00_axi_rready
|
||||
);
|
||||
|
||||
output wire start_vld;
|
||||
input wire read_vld;
|
||||
input wire [56 : 0] dna_port;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s00_axi_aclk, ASSOCIATED_BUSIF s00_axi, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK" *)
|
||||
input wire s00_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s00_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST" *)
|
||||
input wire s00_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWADDR" *)
|
||||
input wire [3 : 0] s00_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWPROT" *)
|
||||
input wire [2 : 0] s00_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWVALID" *)
|
||||
input wire s00_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWREADY" *)
|
||||
output wire s00_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WDATA" *)
|
||||
input wire [31 : 0] s00_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WSTRB" *)
|
||||
input wire [3 : 0] s00_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WVALID" *)
|
||||
input wire s00_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WREADY" *)
|
||||
output wire s00_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BRESP" *)
|
||||
output wire [1 : 0] s00_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BVALID" *)
|
||||
output wire s00_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BREADY" *)
|
||||
input wire s00_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARADDR" *)
|
||||
input wire [3 : 0] s00_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARPROT" *)
|
||||
input wire [2 : 0] s00_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARVALID" *)
|
||||
input wire s00_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARREADY" *)
|
||||
output wire s00_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RDATA" *)
|
||||
output wire [31 : 0] s00_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RRESP" *)
|
||||
output wire [1 : 0] s00_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RVALID" *)
|
||||
output wire s00_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s00_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS\
|
||||
4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RREADY" *)
|
||||
input wire s00_axi_rready;
|
||||
|
||||
mydna_read_v1_0 #(
|
||||
.C_S00_AXI_DATA_WIDTH(32),
|
||||
.C_S00_AXI_ADDR_WIDTH(4)
|
||||
) inst (
|
||||
.start_vld(start_vld),
|
||||
.read_vld(read_vld),
|
||||
.dna_port(dna_port),
|
||||
.s00_axi_aclk(s00_axi_aclk),
|
||||
.s00_axi_aresetn(s00_axi_aresetn),
|
||||
.s00_axi_awaddr(s00_axi_awaddr),
|
||||
.s00_axi_awprot(s00_axi_awprot),
|
||||
.s00_axi_awvalid(s00_axi_awvalid),
|
||||
.s00_axi_awready(s00_axi_awready),
|
||||
.s00_axi_wdata(s00_axi_wdata),
|
||||
.s00_axi_wstrb(s00_axi_wstrb),
|
||||
.s00_axi_wvalid(s00_axi_wvalid),
|
||||
.s00_axi_wready(s00_axi_wready),
|
||||
.s00_axi_bresp(s00_axi_bresp),
|
||||
.s00_axi_bvalid(s00_axi_bvalid),
|
||||
.s00_axi_bready(s00_axi_bready),
|
||||
.s00_axi_araddr(s00_axi_araddr),
|
||||
.s00_axi_arprot(s00_axi_arprot),
|
||||
.s00_axi_arvalid(s00_axi_arvalid),
|
||||
.s00_axi_arready(s00_axi_arready),
|
||||
.s00_axi_rdata(s00_axi_rdata),
|
||||
.s00_axi_rresp(s00_axi_rresp),
|
||||
.s00_axi_rvalid(s00_axi_rvalid),
|
||||
.s00_axi_rready(s00_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+164
@@ -0,0 +1,164 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:module_ref:mydna_read_v1_0:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
(* X_CORE_INFO = "mydna_read_v1_0,Vivado 2023.2" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_mydna_read_v1_0_0_0,mydna_read_v1_0,{}" *)
|
||||
(* CORE_GENERATION_INFO = "system_mydna_read_v1_0_0_0,mydna_read_v1_0,{x_ipProduct=Vivado 2023.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=mydna_read_v1_0,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S00_AXI_DATA_WIDTH=32,C_S00_AXI_ADDR_WIDTH=4}" *)
|
||||
(* IP_DEFINITION_SOURCE = "module_ref" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_mydna_read_v1_0_0_0 (
|
||||
start_vld,
|
||||
read_vld,
|
||||
dna_port,
|
||||
s00_axi_aclk,
|
||||
s00_axi_aresetn,
|
||||
s00_axi_awaddr,
|
||||
s00_axi_awprot,
|
||||
s00_axi_awvalid,
|
||||
s00_axi_awready,
|
||||
s00_axi_wdata,
|
||||
s00_axi_wstrb,
|
||||
s00_axi_wvalid,
|
||||
s00_axi_wready,
|
||||
s00_axi_bresp,
|
||||
s00_axi_bvalid,
|
||||
s00_axi_bready,
|
||||
s00_axi_araddr,
|
||||
s00_axi_arprot,
|
||||
s00_axi_arvalid,
|
||||
s00_axi_arready,
|
||||
s00_axi_rdata,
|
||||
s00_axi_rresp,
|
||||
s00_axi_rvalid,
|
||||
s00_axi_rready
|
||||
);
|
||||
|
||||
output wire start_vld;
|
||||
input wire read_vld;
|
||||
input wire [56 : 0] dna_port;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s00_axi_aclk, ASSOCIATED_BUSIF s00_axi, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK" *)
|
||||
input wire s00_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s00_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST" *)
|
||||
input wire s00_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWADDR" *)
|
||||
input wire [3 : 0] s00_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWPROT" *)
|
||||
input wire [2 : 0] s00_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWVALID" *)
|
||||
input wire s00_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWREADY" *)
|
||||
output wire s00_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WDATA" *)
|
||||
input wire [31 : 0] s00_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WSTRB" *)
|
||||
input wire [3 : 0] s00_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WVALID" *)
|
||||
input wire s00_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WREADY" *)
|
||||
output wire s00_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BRESP" *)
|
||||
output wire [1 : 0] s00_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BVALID" *)
|
||||
output wire s00_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BREADY" *)
|
||||
input wire s00_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARADDR" *)
|
||||
input wire [3 : 0] s00_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARPROT" *)
|
||||
input wire [2 : 0] s00_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARVALID" *)
|
||||
input wire s00_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARREADY" *)
|
||||
output wire s00_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RDATA" *)
|
||||
output wire [31 : 0] s00_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RRESP" *)
|
||||
output wire [1 : 0] s00_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RVALID" *)
|
||||
output wire s00_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s00_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS\
|
||||
4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RREADY" *)
|
||||
input wire s00_axi_rready;
|
||||
|
||||
mydna_read_v1_0 #(
|
||||
.C_S00_AXI_DATA_WIDTH(32),
|
||||
.C_S00_AXI_ADDR_WIDTH(4)
|
||||
) inst (
|
||||
.start_vld(start_vld),
|
||||
.read_vld(read_vld),
|
||||
.dna_port(dna_port),
|
||||
.s00_axi_aclk(s00_axi_aclk),
|
||||
.s00_axi_aresetn(s00_axi_aresetn),
|
||||
.s00_axi_awaddr(s00_axi_awaddr),
|
||||
.s00_axi_awprot(s00_axi_awprot),
|
||||
.s00_axi_awvalid(s00_axi_awvalid),
|
||||
.s00_axi_awready(s00_axi_awready),
|
||||
.s00_axi_wdata(s00_axi_wdata),
|
||||
.s00_axi_wstrb(s00_axi_wstrb),
|
||||
.s00_axi_wvalid(s00_axi_wvalid),
|
||||
.s00_axi_wready(s00_axi_wready),
|
||||
.s00_axi_bresp(s00_axi_bresp),
|
||||
.s00_axi_bvalid(s00_axi_bvalid),
|
||||
.s00_axi_bready(s00_axi_bready),
|
||||
.s00_axi_araddr(s00_axi_araddr),
|
||||
.s00_axi_arprot(s00_axi_arprot),
|
||||
.s00_axi_arvalid(s00_axi_arvalid),
|
||||
.s00_axi_arready(s00_axi_arready),
|
||||
.s00_axi_rdata(s00_axi_rdata),
|
||||
.s00_axi_rresp(s00_axi_rresp),
|
||||
.s00_axi_rvalid(s00_axi_rvalid),
|
||||
.s00_axi_rready(s00_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+1145
File diff suppressed because it is too large
Load Diff
+3934
File diff suppressed because it is too large
Load Diff
BIN
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,117 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158730
|
||||
#define QSPI_FREQ 142857132
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 50000000
|
||||
#define UART_FREQ 100000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 100000000
|
||||
#define FPGA1_FREQ 10000000
|
||||
#define FPGA2_FREQ 10000000
|
||||
#define FPGA3_FREQ 10000000
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,745 @@
|
||||
proc ps7_pll_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000701
|
||||
mask_write 0XF8000150 0x00003F33 0x00001401
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A02
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_3_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x0007FFFF 0x00001082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
|
||||
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00000003 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x0003F03F 0x0003C008
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x00010000 0x00000000
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x00000200 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000080
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000703FF 0x000003FF
|
||||
mask_write 0XF800620C 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006210 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006214 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF5 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000260
|
||||
mask_write 0XF8000B70 0x00000001 0x00000001
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001202
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001203
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001203
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001203
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B8 0x00003F01 0x00001201
|
||||
mask_write 0XF80007BC 0x00003F01 0x00001201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000012E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000012E1
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F002E
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x000003FF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_3_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000701
|
||||
mask_write 0XF8000150 0x00003F33 0x00001401
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A02
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_2_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000080
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000260
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001202
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001203
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001203
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001203
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B8 0x00003F01 0x00001201
|
||||
mask_write 0XF80007BC 0x00003F01 0x00001201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000012E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000012E1
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F002E
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x00000FFF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_2_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000701
|
||||
mask_write 0XF8000150 0x00003F33 0x00001401
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A02
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_1_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000080
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x000073FF 0x00000260
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001202
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001203
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001203
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001203
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001203
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B8 0x00003F01 0x00001201
|
||||
mask_write 0XF80007BC 0x00003F01 0x00001201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000012E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000012E1
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F002E
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x00000FFF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_1_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
set PCW_SILICON_VER_1_0 "0x0"
|
||||
set PCW_SILICON_VER_2_0 "0x1"
|
||||
set PCW_SILICON_VER_3_0 "0x2"
|
||||
set APU_FREQ 666666666
|
||||
|
||||
|
||||
|
||||
proc mask_poll { addr mask } {
|
||||
set count 1
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
while { $maskedval == 0 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
set count [ expr { $count + 1 } ]
|
||||
if { $count == 100000000 } {
|
||||
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
|
||||
break
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
proc mask_delay { addr val } {
|
||||
set delay [ get_number_of_cycles_for_delay $val ]
|
||||
perf_reset_and_start_timer
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
while { $maskedval == 1 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
}
|
||||
perf_reset_clock
|
||||
}
|
||||
|
||||
proc ps_version { } {
|
||||
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
|
||||
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
|
||||
return $mask_sil_ver;
|
||||
}
|
||||
|
||||
proc ps7_post_config {} {
|
||||
set saved_mode [configparams force-mem-accesses]
|
||||
configparams force-mem-accesses 1
|
||||
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_post_config_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_post_config_2_0
|
||||
} else {
|
||||
ps7_post_config_3_0
|
||||
}
|
||||
configparams force-mem-accesses $saved_mode
|
||||
}
|
||||
|
||||
proc ps7_debug {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_debug_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_debug_2_0
|
||||
} else {
|
||||
ps7_debug_3_0
|
||||
}
|
||||
}
|
||||
proc ps7_init {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_mio_init_data_1_0
|
||||
ps7_pll_init_data_1_0
|
||||
ps7_clock_init_data_1_0
|
||||
ps7_ddr_init_data_1_0
|
||||
ps7_peripherals_init_data_1_0
|
||||
#puts "PCW Silicon Version : 1.0"
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_mio_init_data_2_0
|
||||
ps7_pll_init_data_2_0
|
||||
ps7_clock_init_data_2_0
|
||||
ps7_ddr_init_data_2_0
|
||||
ps7_peripherals_init_data_2_0
|
||||
#puts "PCW Silicon Version : 2.0"
|
||||
} else {
|
||||
ps7_mio_init_data_3_0
|
||||
ps7_pll_init_data_3_0
|
||||
ps7_clock_init_data_3_0
|
||||
ps7_ddr_init_data_3_0
|
||||
ps7_peripherals_init_data_3_0
|
||||
#puts "PCW Silicon Version : 3.0"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# For delay calculation using global timer
|
||||
|
||||
# start timer
|
||||
proc perf_start_clock { } {
|
||||
|
||||
#writing SCU_GLOBAL_TIMER_CONTROL register
|
||||
|
||||
mask_write 0xF8F00208 0x00000109 0x00000009
|
||||
}
|
||||
|
||||
# stop timer and reset timer count regs
|
||||
proc perf_reset_clock { } {
|
||||
perf_disable_clock
|
||||
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
|
||||
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
# Compute mask for given delay in miliseconds
|
||||
proc get_number_of_cycles_for_delay { delay } {
|
||||
|
||||
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
|
||||
variable APU_FREQ
|
||||
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
|
||||
}
|
||||
|
||||
|
||||
# stop timer
|
||||
proc perf_disable_clock {} {
|
||||
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
proc perf_reset_and_start_timer {} {
|
||||
perf_reset_clock
|
||||
perf_start_clock
|
||||
}
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,131 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010-2020 <Xilinx Inc.>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, see <http://www.gnu.org/licenses/>
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init_gpl.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158730
|
||||
#define QSPI_FREQ 142857132
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 50000000
|
||||
#define UART_FREQ 100000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 100000000
|
||||
#define FPGA1_FREQ 10000000
|
||||
#define FPGA2_FREQ 10000000
|
||||
#define FPGA3_FREQ 10000000
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,47 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
@@ -0,0 +1,47 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
+736
@@ -0,0 +1,736 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#include "system_processing_system7_0_0_sc.h"
|
||||
|
||||
#include "system_processing_system7_0_0.h"
|
||||
|
||||
#include "processing_system7_v5_5_tlm.h"
|
||||
|
||||
#include <map>
|
||||
#include <string>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XILINX_SIMULATOR
|
||||
system_processing_system7_0_0::system_processing_system7_0_0(const sc_core::sc_module_name& nm) : system_processing_system7_0_0_sc(nm), GPIO_I("GPIO_I"), GPIO_O("GPIO_O"), GPIO_T("GPIO_T"), M_AXI_GP0_ARVALID("M_AXI_GP0_ARVALID"), M_AXI_GP0_AWVALID("M_AXI_GP0_AWVALID"), M_AXI_GP0_BREADY("M_AXI_GP0_BREADY"), M_AXI_GP0_RREADY("M_AXI_GP0_RREADY"), M_AXI_GP0_WLAST("M_AXI_GP0_WLAST"), M_AXI_GP0_WVALID("M_AXI_GP0_WVALID"), M_AXI_GP0_ARID("M_AXI_GP0_ARID"), M_AXI_GP0_AWID("M_AXI_GP0_AWID"), M_AXI_GP0_WID("M_AXI_GP0_WID"), M_AXI_GP0_ARBURST("M_AXI_GP0_ARBURST"), M_AXI_GP0_ARLOCK("M_AXI_GP0_ARLOCK"), M_AXI_GP0_ARSIZE("M_AXI_GP0_ARSIZE"), M_AXI_GP0_AWBURST("M_AXI_GP0_AWBURST"), M_AXI_GP0_AWLOCK("M_AXI_GP0_AWLOCK"), M_AXI_GP0_AWSIZE("M_AXI_GP0_AWSIZE"), M_AXI_GP0_ARPROT("M_AXI_GP0_ARPROT"), M_AXI_GP0_AWPROT("M_AXI_GP0_AWPROT"), M_AXI_GP0_ARADDR("M_AXI_GP0_ARADDR"), M_AXI_GP0_AWADDR("M_AXI_GP0_AWADDR"), M_AXI_GP0_WDATA("M_AXI_GP0_WDATA"), M_AXI_GP0_ARCACHE("M_AXI_GP0_ARCACHE"), M_AXI_GP0_ARLEN("M_AXI_GP0_ARLEN"), M_AXI_GP0_ARQOS("M_AXI_GP0_ARQOS"), M_AXI_GP0_AWCACHE("M_AXI_GP0_AWCACHE"), M_AXI_GP0_AWLEN("M_AXI_GP0_AWLEN"), M_AXI_GP0_AWQOS("M_AXI_GP0_AWQOS"), M_AXI_GP0_WSTRB("M_AXI_GP0_WSTRB"), M_AXI_GP0_ACLK("M_AXI_GP0_ACLK"), M_AXI_GP0_ARREADY("M_AXI_GP0_ARREADY"), M_AXI_GP0_AWREADY("M_AXI_GP0_AWREADY"), M_AXI_GP0_BVALID("M_AXI_GP0_BVALID"), M_AXI_GP0_RLAST("M_AXI_GP0_RLAST"), M_AXI_GP0_RVALID("M_AXI_GP0_RVALID"), M_AXI_GP0_WREADY("M_AXI_GP0_WREADY"), M_AXI_GP0_BID("M_AXI_GP0_BID"), M_AXI_GP0_RID("M_AXI_GP0_RID"), M_AXI_GP0_BRESP("M_AXI_GP0_BRESP"), M_AXI_GP0_RRESP("M_AXI_GP0_RRESP"), M_AXI_GP0_RDATA("M_AXI_GP0_RDATA"), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
|
||||
{
|
||||
|
||||
// initialize pins
|
||||
mp_impl->GPIO_I(GPIO_I);
|
||||
mp_impl->GPIO_O(GPIO_O);
|
||||
mp_impl->GPIO_T(GPIO_T);
|
||||
mp_impl->M_AXI_GP0_ACLK(M_AXI_GP0_ACLK);
|
||||
mp_impl->FCLK_CLK0(FCLK_CLK0);
|
||||
mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
|
||||
mp_impl->MIO(MIO);
|
||||
mp_impl->DDR_CAS_n(DDR_CAS_n);
|
||||
mp_impl->DDR_CKE(DDR_CKE);
|
||||
mp_impl->DDR_Clk_n(DDR_Clk_n);
|
||||
mp_impl->DDR_Clk(DDR_Clk);
|
||||
mp_impl->DDR_CS_n(DDR_CS_n);
|
||||
mp_impl->DDR_DRSTB(DDR_DRSTB);
|
||||
mp_impl->DDR_ODT(DDR_ODT);
|
||||
mp_impl->DDR_RAS_n(DDR_RAS_n);
|
||||
mp_impl->DDR_WEB(DDR_WEB);
|
||||
mp_impl->DDR_BankAddr(DDR_BankAddr);
|
||||
mp_impl->DDR_Addr(DDR_Addr);
|
||||
mp_impl->DDR_VRN(DDR_VRN);
|
||||
mp_impl->DDR_VRP(DDR_VRP);
|
||||
mp_impl->DDR_DM(DDR_DM);
|
||||
mp_impl->DDR_DQ(DDR_DQ);
|
||||
mp_impl->DDR_DQS_n(DDR_DQS_n);
|
||||
mp_impl->DDR_DQS(DDR_DQS);
|
||||
mp_impl->PS_SRSTB(PS_SRSTB);
|
||||
mp_impl->PS_CLK(PS_CLK);
|
||||
mp_impl->PS_PORB(PS_PORB);
|
||||
|
||||
// initialize transactors
|
||||
mp_M_AXI_GP0_transactor = NULL;
|
||||
mp_M_AXI_GP0_ARLOCK_converter = NULL;
|
||||
mp_M_AXI_GP0_AWLOCK_converter = NULL;
|
||||
mp_M_AXI_GP0_ARLEN_converter = NULL;
|
||||
mp_M_AXI_GP0_AWLEN_converter = NULL;
|
||||
|
||||
}
|
||||
|
||||
void system_processing_system7_0_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'M_AXI_GP0' transactor
|
||||
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("system_processing_system7_0_0", "M_AXI_GP0_TLM_MODE") != 1)
|
||||
{
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// 'M_AXI_GP0' transactor parameters
|
||||
xsc::common_cpp::properties M_AXI_GP0_transactor_param_props;
|
||||
M_AXI_GP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_RESET", "0");
|
||||
M_AXI_GP0_transactor_param_props.addString("NUM_WRITE_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addString("NUM_READ_OUTSTANDING", "8");
|
||||
|
||||
mp_M_AXI_GP0_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>("M_AXI_GP0_transactor", M_AXI_GP0_transactor_param_props);
|
||||
|
||||
// M_AXI_GP0' transactor ports
|
||||
|
||||
mp_M_AXI_GP0_transactor->ARVALID(M_AXI_GP0_ARVALID);
|
||||
mp_M_AXI_GP0_transactor->AWVALID(M_AXI_GP0_AWVALID);
|
||||
mp_M_AXI_GP0_transactor->BREADY(M_AXI_GP0_BREADY);
|
||||
mp_M_AXI_GP0_transactor->RREADY(M_AXI_GP0_RREADY);
|
||||
mp_M_AXI_GP0_transactor->WLAST(M_AXI_GP0_WLAST);
|
||||
mp_M_AXI_GP0_transactor->WVALID(M_AXI_GP0_WVALID);
|
||||
mp_M_AXI_GP0_transactor->ARID(M_AXI_GP0_ARID);
|
||||
mp_M_AXI_GP0_transactor->AWID(M_AXI_GP0_AWID);
|
||||
mp_M_AXI_GP0_transactor->ARBURST(M_AXI_GP0_ARBURST);
|
||||
mp_M_AXI_GP0_ARLOCK_converter = new xsc::common::scalar2vectorN_converter<2>("M_AXI_GP0_ARLOCK_converter");
|
||||
mp_M_AXI_GP0_ARLOCK_converter->scalar_in(m_M_AXI_GP0_ARLOCK_converter_signal);
|
||||
mp_M_AXI_GP0_ARLOCK_converter->vector_out(M_AXI_GP0_ARLOCK);
|
||||
mp_M_AXI_GP0_transactor->ARLOCK(m_M_AXI_GP0_ARLOCK_converter_signal);
|
||||
mp_M_AXI_GP0_transactor->ARSIZE(M_AXI_GP0_ARSIZE);
|
||||
mp_M_AXI_GP0_transactor->AWBURST(M_AXI_GP0_AWBURST);
|
||||
mp_M_AXI_GP0_AWLOCK_converter = new xsc::common::scalar2vectorN_converter<2>("M_AXI_GP0_AWLOCK_converter");
|
||||
mp_M_AXI_GP0_AWLOCK_converter->scalar_in(m_M_AXI_GP0_AWLOCK_converter_signal);
|
||||
mp_M_AXI_GP0_AWLOCK_converter->vector_out(M_AXI_GP0_AWLOCK);
|
||||
mp_M_AXI_GP0_transactor->AWLOCK(m_M_AXI_GP0_AWLOCK_converter_signal);
|
||||
mp_M_AXI_GP0_transactor->AWSIZE(M_AXI_GP0_AWSIZE);
|
||||
mp_M_AXI_GP0_transactor->ARPROT(M_AXI_GP0_ARPROT);
|
||||
mp_M_AXI_GP0_transactor->AWPROT(M_AXI_GP0_AWPROT);
|
||||
mp_M_AXI_GP0_transactor->ARADDR(M_AXI_GP0_ARADDR);
|
||||
mp_M_AXI_GP0_transactor->AWADDR(M_AXI_GP0_AWADDR);
|
||||
mp_M_AXI_GP0_transactor->WDATA(M_AXI_GP0_WDATA);
|
||||
mp_M_AXI_GP0_transactor->ARCACHE(M_AXI_GP0_ARCACHE);
|
||||
mp_M_AXI_GP0_ARLEN_converter = new xsc::common::vector2vector_converter<8,4>("M_AXI_GP0_ARLEN_converter");
|
||||
mp_M_AXI_GP0_ARLEN_converter->vector_in(m_M_AXI_GP0_ARLEN_converter_signal);
|
||||
mp_M_AXI_GP0_ARLEN_converter->vector_out(M_AXI_GP0_ARLEN);
|
||||
mp_M_AXI_GP0_transactor->ARLEN(m_M_AXI_GP0_ARLEN_converter_signal);
|
||||
mp_M_AXI_GP0_transactor->ARQOS(M_AXI_GP0_ARQOS);
|
||||
mp_M_AXI_GP0_transactor->AWCACHE(M_AXI_GP0_AWCACHE);
|
||||
mp_M_AXI_GP0_AWLEN_converter = new xsc::common::vector2vector_converter<8,4>("M_AXI_GP0_AWLEN_converter");
|
||||
mp_M_AXI_GP0_AWLEN_converter->vector_in(m_M_AXI_GP0_AWLEN_converter_signal);
|
||||
mp_M_AXI_GP0_AWLEN_converter->vector_out(M_AXI_GP0_AWLEN);
|
||||
mp_M_AXI_GP0_transactor->AWLEN(m_M_AXI_GP0_AWLEN_converter_signal);
|
||||
mp_M_AXI_GP0_transactor->AWQOS(M_AXI_GP0_AWQOS);
|
||||
mp_M_AXI_GP0_transactor->WSTRB(M_AXI_GP0_WSTRB);
|
||||
mp_M_AXI_GP0_transactor->ARREADY(M_AXI_GP0_ARREADY);
|
||||
mp_M_AXI_GP0_transactor->AWREADY(M_AXI_GP0_AWREADY);
|
||||
mp_M_AXI_GP0_transactor->BVALID(M_AXI_GP0_BVALID);
|
||||
mp_M_AXI_GP0_transactor->RLAST(M_AXI_GP0_RLAST);
|
||||
mp_M_AXI_GP0_transactor->RVALID(M_AXI_GP0_RVALID);
|
||||
mp_M_AXI_GP0_transactor->WREADY(M_AXI_GP0_WREADY);
|
||||
mp_M_AXI_GP0_transactor->BID(M_AXI_GP0_BID);
|
||||
mp_M_AXI_GP0_transactor->RID(M_AXI_GP0_RID);
|
||||
mp_M_AXI_GP0_transactor->BRESP(M_AXI_GP0_BRESP);
|
||||
mp_M_AXI_GP0_transactor->RRESP(M_AXI_GP0_RRESP);
|
||||
mp_M_AXI_GP0_transactor->RDATA(M_AXI_GP0_RDATA);
|
||||
mp_M_AXI_GP0_transactor->CLK(M_AXI_GP0_ACLK);
|
||||
m_M_AXI_GP0_transactor_rst_signal.write(1);
|
||||
mp_M_AXI_GP0_transactor->RST(m_M_AXI_GP0_transactor_rst_signal);
|
||||
|
||||
// M_AXI_GP0' transactor sockets
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // XILINX_SIMULATOR
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
system_processing_system7_0_0::system_processing_system7_0_0(const sc_core::sc_module_name& nm) : system_processing_system7_0_0_sc(nm), GPIO_I("GPIO_I"), GPIO_O("GPIO_O"), GPIO_T("GPIO_T"), M_AXI_GP0_ARVALID("M_AXI_GP0_ARVALID"), M_AXI_GP0_AWVALID("M_AXI_GP0_AWVALID"), M_AXI_GP0_BREADY("M_AXI_GP0_BREADY"), M_AXI_GP0_RREADY("M_AXI_GP0_RREADY"), M_AXI_GP0_WLAST("M_AXI_GP0_WLAST"), M_AXI_GP0_WVALID("M_AXI_GP0_WVALID"), M_AXI_GP0_ARID("M_AXI_GP0_ARID"), M_AXI_GP0_AWID("M_AXI_GP0_AWID"), M_AXI_GP0_WID("M_AXI_GP0_WID"), M_AXI_GP0_ARBURST("M_AXI_GP0_ARBURST"), M_AXI_GP0_ARLOCK("M_AXI_GP0_ARLOCK"), M_AXI_GP0_ARSIZE("M_AXI_GP0_ARSIZE"), M_AXI_GP0_AWBURST("M_AXI_GP0_AWBURST"), M_AXI_GP0_AWLOCK("M_AXI_GP0_AWLOCK"), M_AXI_GP0_AWSIZE("M_AXI_GP0_AWSIZE"), M_AXI_GP0_ARPROT("M_AXI_GP0_ARPROT"), M_AXI_GP0_AWPROT("M_AXI_GP0_AWPROT"), M_AXI_GP0_ARADDR("M_AXI_GP0_ARADDR"), M_AXI_GP0_AWADDR("M_AXI_GP0_AWADDR"), M_AXI_GP0_WDATA("M_AXI_GP0_WDATA"), M_AXI_GP0_ARCACHE("M_AXI_GP0_ARCACHE"), M_AXI_GP0_ARLEN("M_AXI_GP0_ARLEN"), M_AXI_GP0_ARQOS("M_AXI_GP0_ARQOS"), M_AXI_GP0_AWCACHE("M_AXI_GP0_AWCACHE"), M_AXI_GP0_AWLEN("M_AXI_GP0_AWLEN"), M_AXI_GP0_AWQOS("M_AXI_GP0_AWQOS"), M_AXI_GP0_WSTRB("M_AXI_GP0_WSTRB"), M_AXI_GP0_ACLK("M_AXI_GP0_ACLK"), M_AXI_GP0_ARREADY("M_AXI_GP0_ARREADY"), M_AXI_GP0_AWREADY("M_AXI_GP0_AWREADY"), M_AXI_GP0_BVALID("M_AXI_GP0_BVALID"), M_AXI_GP0_RLAST("M_AXI_GP0_RLAST"), M_AXI_GP0_RVALID("M_AXI_GP0_RVALID"), M_AXI_GP0_WREADY("M_AXI_GP0_WREADY"), M_AXI_GP0_BID("M_AXI_GP0_BID"), M_AXI_GP0_RID("M_AXI_GP0_RID"), M_AXI_GP0_BRESP("M_AXI_GP0_BRESP"), M_AXI_GP0_RRESP("M_AXI_GP0_RRESP"), M_AXI_GP0_RDATA("M_AXI_GP0_RDATA"), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
|
||||
{
|
||||
|
||||
// initialize pins
|
||||
mp_impl->GPIO_I(GPIO_I);
|
||||
mp_impl->GPIO_O(GPIO_O);
|
||||
mp_impl->GPIO_T(GPIO_T);
|
||||
mp_impl->M_AXI_GP0_ACLK(M_AXI_GP0_ACLK);
|
||||
mp_impl->FCLK_CLK0(FCLK_CLK0);
|
||||
mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
|
||||
mp_impl->MIO(MIO);
|
||||
mp_impl->DDR_CAS_n(DDR_CAS_n);
|
||||
mp_impl->DDR_CKE(DDR_CKE);
|
||||
mp_impl->DDR_Clk_n(DDR_Clk_n);
|
||||
mp_impl->DDR_Clk(DDR_Clk);
|
||||
mp_impl->DDR_CS_n(DDR_CS_n);
|
||||
mp_impl->DDR_DRSTB(DDR_DRSTB);
|
||||
mp_impl->DDR_ODT(DDR_ODT);
|
||||
mp_impl->DDR_RAS_n(DDR_RAS_n);
|
||||
mp_impl->DDR_WEB(DDR_WEB);
|
||||
mp_impl->DDR_BankAddr(DDR_BankAddr);
|
||||
mp_impl->DDR_Addr(DDR_Addr);
|
||||
mp_impl->DDR_VRN(DDR_VRN);
|
||||
mp_impl->DDR_VRP(DDR_VRP);
|
||||
mp_impl->DDR_DM(DDR_DM);
|
||||
mp_impl->DDR_DQ(DDR_DQ);
|
||||
mp_impl->DDR_DQS_n(DDR_DQS_n);
|
||||
mp_impl->DDR_DQS(DDR_DQS);
|
||||
mp_impl->PS_SRSTB(PS_SRSTB);
|
||||
mp_impl->PS_CLK(PS_CLK);
|
||||
mp_impl->PS_PORB(PS_PORB);
|
||||
|
||||
// initialize transactors
|
||||
mp_M_AXI_GP0_transactor = NULL;
|
||||
mp_M_AXI_GP0_ARLOCK_converter = NULL;
|
||||
mp_M_AXI_GP0_AWLOCK_converter = NULL;
|
||||
mp_M_AXI_GP0_ARLEN_converter = NULL;
|
||||
mp_M_AXI_GP0_AWLEN_converter = NULL;
|
||||
|
||||
}
|
||||
|
||||
void system_processing_system7_0_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'M_AXI_GP0' transactor
|
||||
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("system_processing_system7_0_0", "M_AXI_GP0_TLM_MODE") != 1)
|
||||
{
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// 'M_AXI_GP0' transactor parameters
|
||||
xsc::common_cpp::properties M_AXI_GP0_transactor_param_props;
|
||||
M_AXI_GP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_RESET", "0");
|
||||
M_AXI_GP0_transactor_param_props.addString("NUM_WRITE_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addString("NUM_READ_OUTSTANDING", "8");
|
||||
|
||||
mp_M_AXI_GP0_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>("M_AXI_GP0_transactor", M_AXI_GP0_transactor_param_props);
|
||||
|
||||
// M_AXI_GP0' transactor ports
|
||||
|
||||
mp_M_AXI_GP0_transactor->ARVALID(M_AXI_GP0_ARVALID);
|
||||
mp_M_AXI_GP0_transactor->AWVALID(M_AXI_GP0_AWVALID);
|
||||
mp_M_AXI_GP0_transactor->BREADY(M_AXI_GP0_BREADY);
|
||||
mp_M_AXI_GP0_transactor->RREADY(M_AXI_GP0_RREADY);
|
||||
mp_M_AXI_GP0_transactor->WLAST(M_AXI_GP0_WLAST);
|
||||
mp_M_AXI_GP0_transactor->WVALID(M_AXI_GP0_WVALID);
|
||||
mp_M_AXI_GP0_transactor->ARID(M_AXI_GP0_ARID);
|
||||
mp_M_AXI_GP0_transactor->AWID(M_AXI_GP0_AWID);
|
||||
mp_M_AXI_GP0_transactor->ARBURST(M_AXI_GP0_ARBURST);
|
||||
mp_M_AXI_GP0_ARLOCK_converter = new xsc::common::scalar2vectorN_converter<2>("M_AXI_GP0_ARLOCK_converter");
|
||||
mp_M_AXI_GP0_ARLOCK_converter->scalar_in(m_M_AXI_GP0_ARLOCK_converter_signal);
|
||||
mp_M_AXI_GP0_ARLOCK_converter->vector_out(M_AXI_GP0_ARLOCK);
|
||||
mp_M_AXI_GP0_transactor->ARLOCK(m_M_AXI_GP0_ARLOCK_converter_signal);
|
||||
mp_M_AXI_GP0_transactor->ARSIZE(M_AXI_GP0_ARSIZE);
|
||||
mp_M_AXI_GP0_transactor->AWBURST(M_AXI_GP0_AWBURST);
|
||||
mp_M_AXI_GP0_AWLOCK_converter = new xsc::common::scalar2vectorN_converter<2>("M_AXI_GP0_AWLOCK_converter");
|
||||
mp_M_AXI_GP0_AWLOCK_converter->scalar_in(m_M_AXI_GP0_AWLOCK_converter_signal);
|
||||
mp_M_AXI_GP0_AWLOCK_converter->vector_out(M_AXI_GP0_AWLOCK);
|
||||
mp_M_AXI_GP0_transactor->AWLOCK(m_M_AXI_GP0_AWLOCK_converter_signal);
|
||||
mp_M_AXI_GP0_transactor->AWSIZE(M_AXI_GP0_AWSIZE);
|
||||
mp_M_AXI_GP0_transactor->ARPROT(M_AXI_GP0_ARPROT);
|
||||
mp_M_AXI_GP0_transactor->AWPROT(M_AXI_GP0_AWPROT);
|
||||
mp_M_AXI_GP0_transactor->ARADDR(M_AXI_GP0_ARADDR);
|
||||
mp_M_AXI_GP0_transactor->AWADDR(M_AXI_GP0_AWADDR);
|
||||
mp_M_AXI_GP0_transactor->WDATA(M_AXI_GP0_WDATA);
|
||||
mp_M_AXI_GP0_transactor->ARCACHE(M_AXI_GP0_ARCACHE);
|
||||
mp_M_AXI_GP0_ARLEN_converter = new xsc::common::vector2vector_converter<8,4>("M_AXI_GP0_ARLEN_converter");
|
||||
mp_M_AXI_GP0_ARLEN_converter->vector_in(m_M_AXI_GP0_ARLEN_converter_signal);
|
||||
mp_M_AXI_GP0_ARLEN_converter->vector_out(M_AXI_GP0_ARLEN);
|
||||
mp_M_AXI_GP0_transactor->ARLEN(m_M_AXI_GP0_ARLEN_converter_signal);
|
||||
mp_M_AXI_GP0_transactor->ARQOS(M_AXI_GP0_ARQOS);
|
||||
mp_M_AXI_GP0_transactor->AWCACHE(M_AXI_GP0_AWCACHE);
|
||||
mp_M_AXI_GP0_AWLEN_converter = new xsc::common::vector2vector_converter<8,4>("M_AXI_GP0_AWLEN_converter");
|
||||
mp_M_AXI_GP0_AWLEN_converter->vector_in(m_M_AXI_GP0_AWLEN_converter_signal);
|
||||
mp_M_AXI_GP0_AWLEN_converter->vector_out(M_AXI_GP0_AWLEN);
|
||||
mp_M_AXI_GP0_transactor->AWLEN(m_M_AXI_GP0_AWLEN_converter_signal);
|
||||
mp_M_AXI_GP0_transactor->AWQOS(M_AXI_GP0_AWQOS);
|
||||
mp_M_AXI_GP0_transactor->WSTRB(M_AXI_GP0_WSTRB);
|
||||
mp_M_AXI_GP0_transactor->ARREADY(M_AXI_GP0_ARREADY);
|
||||
mp_M_AXI_GP0_transactor->AWREADY(M_AXI_GP0_AWREADY);
|
||||
mp_M_AXI_GP0_transactor->BVALID(M_AXI_GP0_BVALID);
|
||||
mp_M_AXI_GP0_transactor->RLAST(M_AXI_GP0_RLAST);
|
||||
mp_M_AXI_GP0_transactor->RVALID(M_AXI_GP0_RVALID);
|
||||
mp_M_AXI_GP0_transactor->WREADY(M_AXI_GP0_WREADY);
|
||||
mp_M_AXI_GP0_transactor->BID(M_AXI_GP0_BID);
|
||||
mp_M_AXI_GP0_transactor->RID(M_AXI_GP0_RID);
|
||||
mp_M_AXI_GP0_transactor->BRESP(M_AXI_GP0_BRESP);
|
||||
mp_M_AXI_GP0_transactor->RRESP(M_AXI_GP0_RRESP);
|
||||
mp_M_AXI_GP0_transactor->RDATA(M_AXI_GP0_RDATA);
|
||||
mp_M_AXI_GP0_transactor->CLK(M_AXI_GP0_ACLK);
|
||||
m_M_AXI_GP0_transactor_rst_signal.write(1);
|
||||
mp_M_AXI_GP0_transactor->RST(m_M_AXI_GP0_transactor_rst_signal);
|
||||
|
||||
// M_AXI_GP0' transactor sockets
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // XM_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef RIVIERA
|
||||
system_processing_system7_0_0::system_processing_system7_0_0(const sc_core::sc_module_name& nm) : system_processing_system7_0_0_sc(nm), GPIO_I("GPIO_I"), GPIO_O("GPIO_O"), GPIO_T("GPIO_T"), M_AXI_GP0_ARVALID("M_AXI_GP0_ARVALID"), M_AXI_GP0_AWVALID("M_AXI_GP0_AWVALID"), M_AXI_GP0_BREADY("M_AXI_GP0_BREADY"), M_AXI_GP0_RREADY("M_AXI_GP0_RREADY"), M_AXI_GP0_WLAST("M_AXI_GP0_WLAST"), M_AXI_GP0_WVALID("M_AXI_GP0_WVALID"), M_AXI_GP0_ARID("M_AXI_GP0_ARID"), M_AXI_GP0_AWID("M_AXI_GP0_AWID"), M_AXI_GP0_WID("M_AXI_GP0_WID"), M_AXI_GP0_ARBURST("M_AXI_GP0_ARBURST"), M_AXI_GP0_ARLOCK("M_AXI_GP0_ARLOCK"), M_AXI_GP0_ARSIZE("M_AXI_GP0_ARSIZE"), M_AXI_GP0_AWBURST("M_AXI_GP0_AWBURST"), M_AXI_GP0_AWLOCK("M_AXI_GP0_AWLOCK"), M_AXI_GP0_AWSIZE("M_AXI_GP0_AWSIZE"), M_AXI_GP0_ARPROT("M_AXI_GP0_ARPROT"), M_AXI_GP0_AWPROT("M_AXI_GP0_AWPROT"), M_AXI_GP0_ARADDR("M_AXI_GP0_ARADDR"), M_AXI_GP0_AWADDR("M_AXI_GP0_AWADDR"), M_AXI_GP0_WDATA("M_AXI_GP0_WDATA"), M_AXI_GP0_ARCACHE("M_AXI_GP0_ARCACHE"), M_AXI_GP0_ARLEN("M_AXI_GP0_ARLEN"), M_AXI_GP0_ARQOS("M_AXI_GP0_ARQOS"), M_AXI_GP0_AWCACHE("M_AXI_GP0_AWCACHE"), M_AXI_GP0_AWLEN("M_AXI_GP0_AWLEN"), M_AXI_GP0_AWQOS("M_AXI_GP0_AWQOS"), M_AXI_GP0_WSTRB("M_AXI_GP0_WSTRB"), M_AXI_GP0_ACLK("M_AXI_GP0_ACLK"), M_AXI_GP0_ARREADY("M_AXI_GP0_ARREADY"), M_AXI_GP0_AWREADY("M_AXI_GP0_AWREADY"), M_AXI_GP0_BVALID("M_AXI_GP0_BVALID"), M_AXI_GP0_RLAST("M_AXI_GP0_RLAST"), M_AXI_GP0_RVALID("M_AXI_GP0_RVALID"), M_AXI_GP0_WREADY("M_AXI_GP0_WREADY"), M_AXI_GP0_BID("M_AXI_GP0_BID"), M_AXI_GP0_RID("M_AXI_GP0_RID"), M_AXI_GP0_BRESP("M_AXI_GP0_BRESP"), M_AXI_GP0_RRESP("M_AXI_GP0_RRESP"), M_AXI_GP0_RDATA("M_AXI_GP0_RDATA"), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
|
||||
{
|
||||
|
||||
// initialize pins
|
||||
mp_impl->GPIO_I(GPIO_I);
|
||||
mp_impl->GPIO_O(GPIO_O);
|
||||
mp_impl->GPIO_T(GPIO_T);
|
||||
mp_impl->M_AXI_GP0_ACLK(M_AXI_GP0_ACLK);
|
||||
mp_impl->FCLK_CLK0(FCLK_CLK0);
|
||||
mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
|
||||
mp_impl->MIO(MIO);
|
||||
mp_impl->DDR_CAS_n(DDR_CAS_n);
|
||||
mp_impl->DDR_CKE(DDR_CKE);
|
||||
mp_impl->DDR_Clk_n(DDR_Clk_n);
|
||||
mp_impl->DDR_Clk(DDR_Clk);
|
||||
mp_impl->DDR_CS_n(DDR_CS_n);
|
||||
mp_impl->DDR_DRSTB(DDR_DRSTB);
|
||||
mp_impl->DDR_ODT(DDR_ODT);
|
||||
mp_impl->DDR_RAS_n(DDR_RAS_n);
|
||||
mp_impl->DDR_WEB(DDR_WEB);
|
||||
mp_impl->DDR_BankAddr(DDR_BankAddr);
|
||||
mp_impl->DDR_Addr(DDR_Addr);
|
||||
mp_impl->DDR_VRN(DDR_VRN);
|
||||
mp_impl->DDR_VRP(DDR_VRP);
|
||||
mp_impl->DDR_DM(DDR_DM);
|
||||
mp_impl->DDR_DQ(DDR_DQ);
|
||||
mp_impl->DDR_DQS_n(DDR_DQS_n);
|
||||
mp_impl->DDR_DQS(DDR_DQS);
|
||||
mp_impl->PS_SRSTB(PS_SRSTB);
|
||||
mp_impl->PS_CLK(PS_CLK);
|
||||
mp_impl->PS_PORB(PS_PORB);
|
||||
|
||||
// initialize transactors
|
||||
mp_M_AXI_GP0_transactor = NULL;
|
||||
mp_M_AXI_GP0_ARLOCK_converter = NULL;
|
||||
mp_M_AXI_GP0_AWLOCK_converter = NULL;
|
||||
mp_M_AXI_GP0_ARLEN_converter = NULL;
|
||||
mp_M_AXI_GP0_AWLEN_converter = NULL;
|
||||
|
||||
}
|
||||
|
||||
void system_processing_system7_0_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'M_AXI_GP0' transactor
|
||||
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("system_processing_system7_0_0", "M_AXI_GP0_TLM_MODE") != 1)
|
||||
{
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// 'M_AXI_GP0' transactor parameters
|
||||
xsc::common_cpp::properties M_AXI_GP0_transactor_param_props;
|
||||
M_AXI_GP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_RESET", "0");
|
||||
M_AXI_GP0_transactor_param_props.addString("NUM_WRITE_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addString("NUM_READ_OUTSTANDING", "8");
|
||||
|
||||
mp_M_AXI_GP0_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>("M_AXI_GP0_transactor", M_AXI_GP0_transactor_param_props);
|
||||
|
||||
// M_AXI_GP0' transactor ports
|
||||
|
||||
mp_M_AXI_GP0_transactor->ARVALID(M_AXI_GP0_ARVALID);
|
||||
mp_M_AXI_GP0_transactor->AWVALID(M_AXI_GP0_AWVALID);
|
||||
mp_M_AXI_GP0_transactor->BREADY(M_AXI_GP0_BREADY);
|
||||
mp_M_AXI_GP0_transactor->RREADY(M_AXI_GP0_RREADY);
|
||||
mp_M_AXI_GP0_transactor->WLAST(M_AXI_GP0_WLAST);
|
||||
mp_M_AXI_GP0_transactor->WVALID(M_AXI_GP0_WVALID);
|
||||
mp_M_AXI_GP0_transactor->ARID(M_AXI_GP0_ARID);
|
||||
mp_M_AXI_GP0_transactor->AWID(M_AXI_GP0_AWID);
|
||||
mp_M_AXI_GP0_transactor->ARBURST(M_AXI_GP0_ARBURST);
|
||||
mp_M_AXI_GP0_ARLOCK_converter = new xsc::common::scalar2vectorN_converter<2>("M_AXI_GP0_ARLOCK_converter");
|
||||
mp_M_AXI_GP0_ARLOCK_converter->scalar_in(m_M_AXI_GP0_ARLOCK_converter_signal);
|
||||
mp_M_AXI_GP0_ARLOCK_converter->vector_out(M_AXI_GP0_ARLOCK);
|
||||
mp_M_AXI_GP0_transactor->ARLOCK(m_M_AXI_GP0_ARLOCK_converter_signal);
|
||||
mp_M_AXI_GP0_transactor->ARSIZE(M_AXI_GP0_ARSIZE);
|
||||
mp_M_AXI_GP0_transactor->AWBURST(M_AXI_GP0_AWBURST);
|
||||
mp_M_AXI_GP0_AWLOCK_converter = new xsc::common::scalar2vectorN_converter<2>("M_AXI_GP0_AWLOCK_converter");
|
||||
mp_M_AXI_GP0_AWLOCK_converter->scalar_in(m_M_AXI_GP0_AWLOCK_converter_signal);
|
||||
mp_M_AXI_GP0_AWLOCK_converter->vector_out(M_AXI_GP0_AWLOCK);
|
||||
mp_M_AXI_GP0_transactor->AWLOCK(m_M_AXI_GP0_AWLOCK_converter_signal);
|
||||
mp_M_AXI_GP0_transactor->AWSIZE(M_AXI_GP0_AWSIZE);
|
||||
mp_M_AXI_GP0_transactor->ARPROT(M_AXI_GP0_ARPROT);
|
||||
mp_M_AXI_GP0_transactor->AWPROT(M_AXI_GP0_AWPROT);
|
||||
mp_M_AXI_GP0_transactor->ARADDR(M_AXI_GP0_ARADDR);
|
||||
mp_M_AXI_GP0_transactor->AWADDR(M_AXI_GP0_AWADDR);
|
||||
mp_M_AXI_GP0_transactor->WDATA(M_AXI_GP0_WDATA);
|
||||
mp_M_AXI_GP0_transactor->ARCACHE(M_AXI_GP0_ARCACHE);
|
||||
mp_M_AXI_GP0_ARLEN_converter = new xsc::common::vector2vector_converter<8,4>("M_AXI_GP0_ARLEN_converter");
|
||||
mp_M_AXI_GP0_ARLEN_converter->vector_in(m_M_AXI_GP0_ARLEN_converter_signal);
|
||||
mp_M_AXI_GP0_ARLEN_converter->vector_out(M_AXI_GP0_ARLEN);
|
||||
mp_M_AXI_GP0_transactor->ARLEN(m_M_AXI_GP0_ARLEN_converter_signal);
|
||||
mp_M_AXI_GP0_transactor->ARQOS(M_AXI_GP0_ARQOS);
|
||||
mp_M_AXI_GP0_transactor->AWCACHE(M_AXI_GP0_AWCACHE);
|
||||
mp_M_AXI_GP0_AWLEN_converter = new xsc::common::vector2vector_converter<8,4>("M_AXI_GP0_AWLEN_converter");
|
||||
mp_M_AXI_GP0_AWLEN_converter->vector_in(m_M_AXI_GP0_AWLEN_converter_signal);
|
||||
mp_M_AXI_GP0_AWLEN_converter->vector_out(M_AXI_GP0_AWLEN);
|
||||
mp_M_AXI_GP0_transactor->AWLEN(m_M_AXI_GP0_AWLEN_converter_signal);
|
||||
mp_M_AXI_GP0_transactor->AWQOS(M_AXI_GP0_AWQOS);
|
||||
mp_M_AXI_GP0_transactor->WSTRB(M_AXI_GP0_WSTRB);
|
||||
mp_M_AXI_GP0_transactor->ARREADY(M_AXI_GP0_ARREADY);
|
||||
mp_M_AXI_GP0_transactor->AWREADY(M_AXI_GP0_AWREADY);
|
||||
mp_M_AXI_GP0_transactor->BVALID(M_AXI_GP0_BVALID);
|
||||
mp_M_AXI_GP0_transactor->RLAST(M_AXI_GP0_RLAST);
|
||||
mp_M_AXI_GP0_transactor->RVALID(M_AXI_GP0_RVALID);
|
||||
mp_M_AXI_GP0_transactor->WREADY(M_AXI_GP0_WREADY);
|
||||
mp_M_AXI_GP0_transactor->BID(M_AXI_GP0_BID);
|
||||
mp_M_AXI_GP0_transactor->RID(M_AXI_GP0_RID);
|
||||
mp_M_AXI_GP0_transactor->BRESP(M_AXI_GP0_BRESP);
|
||||
mp_M_AXI_GP0_transactor->RRESP(M_AXI_GP0_RRESP);
|
||||
mp_M_AXI_GP0_transactor->RDATA(M_AXI_GP0_RDATA);
|
||||
mp_M_AXI_GP0_transactor->CLK(M_AXI_GP0_ACLK);
|
||||
m_M_AXI_GP0_transactor_rst_signal.write(1);
|
||||
mp_M_AXI_GP0_transactor->RST(m_M_AXI_GP0_transactor_rst_signal);
|
||||
|
||||
// M_AXI_GP0' transactor sockets
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // RIVIERA
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef VCSSYSTEMC
|
||||
system_processing_system7_0_0::system_processing_system7_0_0(const sc_core::sc_module_name& nm) : system_processing_system7_0_0_sc(nm), GPIO_I("GPIO_I"), GPIO_O("GPIO_O"), GPIO_T("GPIO_T"), M_AXI_GP0_ARVALID("M_AXI_GP0_ARVALID"), M_AXI_GP0_AWVALID("M_AXI_GP0_AWVALID"), M_AXI_GP0_BREADY("M_AXI_GP0_BREADY"), M_AXI_GP0_RREADY("M_AXI_GP0_RREADY"), M_AXI_GP0_WLAST("M_AXI_GP0_WLAST"), M_AXI_GP0_WVALID("M_AXI_GP0_WVALID"), M_AXI_GP0_ARID("M_AXI_GP0_ARID"), M_AXI_GP0_AWID("M_AXI_GP0_AWID"), M_AXI_GP0_WID("M_AXI_GP0_WID"), M_AXI_GP0_ARBURST("M_AXI_GP0_ARBURST"), M_AXI_GP0_ARLOCK("M_AXI_GP0_ARLOCK"), M_AXI_GP0_ARSIZE("M_AXI_GP0_ARSIZE"), M_AXI_GP0_AWBURST("M_AXI_GP0_AWBURST"), M_AXI_GP0_AWLOCK("M_AXI_GP0_AWLOCK"), M_AXI_GP0_AWSIZE("M_AXI_GP0_AWSIZE"), M_AXI_GP0_ARPROT("M_AXI_GP0_ARPROT"), M_AXI_GP0_AWPROT("M_AXI_GP0_AWPROT"), M_AXI_GP0_ARADDR("M_AXI_GP0_ARADDR"), M_AXI_GP0_AWADDR("M_AXI_GP0_AWADDR"), M_AXI_GP0_WDATA("M_AXI_GP0_WDATA"), M_AXI_GP0_ARCACHE("M_AXI_GP0_ARCACHE"), M_AXI_GP0_ARLEN("M_AXI_GP0_ARLEN"), M_AXI_GP0_ARQOS("M_AXI_GP0_ARQOS"), M_AXI_GP0_AWCACHE("M_AXI_GP0_AWCACHE"), M_AXI_GP0_AWLEN("M_AXI_GP0_AWLEN"), M_AXI_GP0_AWQOS("M_AXI_GP0_AWQOS"), M_AXI_GP0_WSTRB("M_AXI_GP0_WSTRB"), M_AXI_GP0_ACLK("M_AXI_GP0_ACLK"), M_AXI_GP0_ARREADY("M_AXI_GP0_ARREADY"), M_AXI_GP0_AWREADY("M_AXI_GP0_AWREADY"), M_AXI_GP0_BVALID("M_AXI_GP0_BVALID"), M_AXI_GP0_RLAST("M_AXI_GP0_RLAST"), M_AXI_GP0_RVALID("M_AXI_GP0_RVALID"), M_AXI_GP0_WREADY("M_AXI_GP0_WREADY"), M_AXI_GP0_BID("M_AXI_GP0_BID"), M_AXI_GP0_RID("M_AXI_GP0_RID"), M_AXI_GP0_BRESP("M_AXI_GP0_BRESP"), M_AXI_GP0_RRESP("M_AXI_GP0_RRESP"), M_AXI_GP0_RDATA("M_AXI_GP0_RDATA"), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
|
||||
{
|
||||
// initialize pins
|
||||
mp_impl->GPIO_I(GPIO_I);
|
||||
mp_impl->GPIO_O(GPIO_O);
|
||||
mp_impl->GPIO_T(GPIO_T);
|
||||
mp_impl->M_AXI_GP0_ACLK(M_AXI_GP0_ACLK);
|
||||
mp_impl->FCLK_CLK0(FCLK_CLK0);
|
||||
mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
|
||||
mp_impl->MIO(MIO);
|
||||
mp_impl->DDR_CAS_n(DDR_CAS_n);
|
||||
mp_impl->DDR_CKE(DDR_CKE);
|
||||
mp_impl->DDR_Clk_n(DDR_Clk_n);
|
||||
mp_impl->DDR_Clk(DDR_Clk);
|
||||
mp_impl->DDR_CS_n(DDR_CS_n);
|
||||
mp_impl->DDR_DRSTB(DDR_DRSTB);
|
||||
mp_impl->DDR_ODT(DDR_ODT);
|
||||
mp_impl->DDR_RAS_n(DDR_RAS_n);
|
||||
mp_impl->DDR_WEB(DDR_WEB);
|
||||
mp_impl->DDR_BankAddr(DDR_BankAddr);
|
||||
mp_impl->DDR_Addr(DDR_Addr);
|
||||
mp_impl->DDR_VRN(DDR_VRN);
|
||||
mp_impl->DDR_VRP(DDR_VRP);
|
||||
mp_impl->DDR_DM(DDR_DM);
|
||||
mp_impl->DDR_DQ(DDR_DQ);
|
||||
mp_impl->DDR_DQS_n(DDR_DQS_n);
|
||||
mp_impl->DDR_DQS(DDR_DQS);
|
||||
mp_impl->PS_SRSTB(PS_SRSTB);
|
||||
mp_impl->PS_CLK(PS_CLK);
|
||||
mp_impl->PS_PORB(PS_PORB);
|
||||
|
||||
// initialize transactors
|
||||
mp_M_AXI_GP0_transactor = NULL;
|
||||
mp_M_AXI_GP0_ARLOCK_converter = NULL;
|
||||
mp_M_AXI_GP0_AWLOCK_converter = NULL;
|
||||
mp_M_AXI_GP0_ARLEN_converter = NULL;
|
||||
mp_M_AXI_GP0_AWLEN_converter = NULL;
|
||||
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// configure M_AXI_GP0_transactor
|
||||
xsc::common_cpp::properties M_AXI_GP0_transactor_param_props;
|
||||
M_AXI_GP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_RESET", "0");
|
||||
M_AXI_GP0_transactor_param_props.addString("NUM_WRITE_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addString("NUM_READ_OUTSTANDING", "8");
|
||||
|
||||
mp_M_AXI_GP0_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>("M_AXI_GP0_transactor", M_AXI_GP0_transactor_param_props);
|
||||
mp_M_AXI_GP0_transactor->ARVALID(M_AXI_GP0_ARVALID);
|
||||
mp_M_AXI_GP0_transactor->AWVALID(M_AXI_GP0_AWVALID);
|
||||
mp_M_AXI_GP0_transactor->BREADY(M_AXI_GP0_BREADY);
|
||||
mp_M_AXI_GP0_transactor->RREADY(M_AXI_GP0_RREADY);
|
||||
mp_M_AXI_GP0_transactor->WLAST(M_AXI_GP0_WLAST);
|
||||
mp_M_AXI_GP0_transactor->WVALID(M_AXI_GP0_WVALID);
|
||||
mp_M_AXI_GP0_transactor->ARID(M_AXI_GP0_ARID);
|
||||
mp_M_AXI_GP0_transactor->AWID(M_AXI_GP0_AWID);
|
||||
mp_M_AXI_GP0_transactor->ARBURST(M_AXI_GP0_ARBURST);
|
||||
mp_M_AXI_GP0_ARLOCK_converter = new xsc::common::scalar2vectorN_converter<2>("M_AXI_GP0_ARLOCK_converter");
|
||||
mp_M_AXI_GP0_ARLOCK_converter->scalar_in(m_M_AXI_GP0_ARLOCK_converter_signal);
|
||||
mp_M_AXI_GP0_ARLOCK_converter->vector_out(M_AXI_GP0_ARLOCK);
|
||||
mp_M_AXI_GP0_transactor->ARLOCK(m_M_AXI_GP0_ARLOCK_converter_signal);
|
||||
mp_M_AXI_GP0_transactor->ARSIZE(M_AXI_GP0_ARSIZE);
|
||||
mp_M_AXI_GP0_transactor->AWBURST(M_AXI_GP0_AWBURST);
|
||||
mp_M_AXI_GP0_AWLOCK_converter = new xsc::common::scalar2vectorN_converter<2>("M_AXI_GP0_AWLOCK_converter");
|
||||
mp_M_AXI_GP0_AWLOCK_converter->scalar_in(m_M_AXI_GP0_AWLOCK_converter_signal);
|
||||
mp_M_AXI_GP0_AWLOCK_converter->vector_out(M_AXI_GP0_AWLOCK);
|
||||
mp_M_AXI_GP0_transactor->AWLOCK(m_M_AXI_GP0_AWLOCK_converter_signal);
|
||||
mp_M_AXI_GP0_transactor->AWSIZE(M_AXI_GP0_AWSIZE);
|
||||
mp_M_AXI_GP0_transactor->ARPROT(M_AXI_GP0_ARPROT);
|
||||
mp_M_AXI_GP0_transactor->AWPROT(M_AXI_GP0_AWPROT);
|
||||
mp_M_AXI_GP0_transactor->ARADDR(M_AXI_GP0_ARADDR);
|
||||
mp_M_AXI_GP0_transactor->AWADDR(M_AXI_GP0_AWADDR);
|
||||
mp_M_AXI_GP0_transactor->WDATA(M_AXI_GP0_WDATA);
|
||||
mp_M_AXI_GP0_transactor->ARCACHE(M_AXI_GP0_ARCACHE);
|
||||
mp_M_AXI_GP0_ARLEN_converter = new xsc::common::vector2vector_converter<8,4>("M_AXI_GP0_ARLEN_converter");
|
||||
mp_M_AXI_GP0_ARLEN_converter->vector_in(m_M_AXI_GP0_ARLEN_converter_signal);
|
||||
mp_M_AXI_GP0_ARLEN_converter->vector_out(M_AXI_GP0_ARLEN);
|
||||
mp_M_AXI_GP0_transactor->ARLEN(m_M_AXI_GP0_ARLEN_converter_signal);
|
||||
mp_M_AXI_GP0_transactor->ARQOS(M_AXI_GP0_ARQOS);
|
||||
mp_M_AXI_GP0_transactor->AWCACHE(M_AXI_GP0_AWCACHE);
|
||||
mp_M_AXI_GP0_AWLEN_converter = new xsc::common::vector2vector_converter<8,4>("M_AXI_GP0_AWLEN_converter");
|
||||
mp_M_AXI_GP0_AWLEN_converter->vector_in(m_M_AXI_GP0_AWLEN_converter_signal);
|
||||
mp_M_AXI_GP0_AWLEN_converter->vector_out(M_AXI_GP0_AWLEN);
|
||||
mp_M_AXI_GP0_transactor->AWLEN(m_M_AXI_GP0_AWLEN_converter_signal);
|
||||
mp_M_AXI_GP0_transactor->AWQOS(M_AXI_GP0_AWQOS);
|
||||
mp_M_AXI_GP0_transactor->WSTRB(M_AXI_GP0_WSTRB);
|
||||
mp_M_AXI_GP0_transactor->ARREADY(M_AXI_GP0_ARREADY);
|
||||
mp_M_AXI_GP0_transactor->AWREADY(M_AXI_GP0_AWREADY);
|
||||
mp_M_AXI_GP0_transactor->BVALID(M_AXI_GP0_BVALID);
|
||||
mp_M_AXI_GP0_transactor->RLAST(M_AXI_GP0_RLAST);
|
||||
mp_M_AXI_GP0_transactor->RVALID(M_AXI_GP0_RVALID);
|
||||
mp_M_AXI_GP0_transactor->WREADY(M_AXI_GP0_WREADY);
|
||||
mp_M_AXI_GP0_transactor->BID(M_AXI_GP0_BID);
|
||||
mp_M_AXI_GP0_transactor->RID(M_AXI_GP0_RID);
|
||||
mp_M_AXI_GP0_transactor->BRESP(M_AXI_GP0_BRESP);
|
||||
mp_M_AXI_GP0_transactor->RRESP(M_AXI_GP0_RRESP);
|
||||
mp_M_AXI_GP0_transactor->RDATA(M_AXI_GP0_RDATA);
|
||||
mp_M_AXI_GP0_transactor->CLK(M_AXI_GP0_ACLK);
|
||||
m_M_AXI_GP0_transactor_rst_signal.write(1);
|
||||
mp_M_AXI_GP0_transactor->RST(m_M_AXI_GP0_transactor_rst_signal);
|
||||
|
||||
// initialize transactors stubs
|
||||
M_AXI_GP0_transactor_initiator_wr_socket_stub = nullptr;
|
||||
M_AXI_GP0_transactor_initiator_rd_socket_stub = nullptr;
|
||||
|
||||
}
|
||||
|
||||
void system_processing_system7_0_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'M_AXI_GP0' transactor
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("system_processing_system7_0_0", "M_AXI_GP0_TLM_MODE") != 1)
|
||||
{
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
M_AXI_GP0_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
|
||||
M_AXI_GP0_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_GP0_transactor->wr_socket));
|
||||
M_AXI_GP0_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
|
||||
M_AXI_GP0_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_GP0_transactor->rd_socket));
|
||||
mp_M_AXI_GP0_transactor->disable_transactor();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // VCSSYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
system_processing_system7_0_0::system_processing_system7_0_0(const sc_core::sc_module_name& nm) : system_processing_system7_0_0_sc(nm), GPIO_I("GPIO_I"), GPIO_O("GPIO_O"), GPIO_T("GPIO_T"), M_AXI_GP0_ARVALID("M_AXI_GP0_ARVALID"), M_AXI_GP0_AWVALID("M_AXI_GP0_AWVALID"), M_AXI_GP0_BREADY("M_AXI_GP0_BREADY"), M_AXI_GP0_RREADY("M_AXI_GP0_RREADY"), M_AXI_GP0_WLAST("M_AXI_GP0_WLAST"), M_AXI_GP0_WVALID("M_AXI_GP0_WVALID"), M_AXI_GP0_ARID("M_AXI_GP0_ARID"), M_AXI_GP0_AWID("M_AXI_GP0_AWID"), M_AXI_GP0_WID("M_AXI_GP0_WID"), M_AXI_GP0_ARBURST("M_AXI_GP0_ARBURST"), M_AXI_GP0_ARLOCK("M_AXI_GP0_ARLOCK"), M_AXI_GP0_ARSIZE("M_AXI_GP0_ARSIZE"), M_AXI_GP0_AWBURST("M_AXI_GP0_AWBURST"), M_AXI_GP0_AWLOCK("M_AXI_GP0_AWLOCK"), M_AXI_GP0_AWSIZE("M_AXI_GP0_AWSIZE"), M_AXI_GP0_ARPROT("M_AXI_GP0_ARPROT"), M_AXI_GP0_AWPROT("M_AXI_GP0_AWPROT"), M_AXI_GP0_ARADDR("M_AXI_GP0_ARADDR"), M_AXI_GP0_AWADDR("M_AXI_GP0_AWADDR"), M_AXI_GP0_WDATA("M_AXI_GP0_WDATA"), M_AXI_GP0_ARCACHE("M_AXI_GP0_ARCACHE"), M_AXI_GP0_ARLEN("M_AXI_GP0_ARLEN"), M_AXI_GP0_ARQOS("M_AXI_GP0_ARQOS"), M_AXI_GP0_AWCACHE("M_AXI_GP0_AWCACHE"), M_AXI_GP0_AWLEN("M_AXI_GP0_AWLEN"), M_AXI_GP0_AWQOS("M_AXI_GP0_AWQOS"), M_AXI_GP0_WSTRB("M_AXI_GP0_WSTRB"), M_AXI_GP0_ACLK("M_AXI_GP0_ACLK"), M_AXI_GP0_ARREADY("M_AXI_GP0_ARREADY"), M_AXI_GP0_AWREADY("M_AXI_GP0_AWREADY"), M_AXI_GP0_BVALID("M_AXI_GP0_BVALID"), M_AXI_GP0_RLAST("M_AXI_GP0_RLAST"), M_AXI_GP0_RVALID("M_AXI_GP0_RVALID"), M_AXI_GP0_WREADY("M_AXI_GP0_WREADY"), M_AXI_GP0_BID("M_AXI_GP0_BID"), M_AXI_GP0_RID("M_AXI_GP0_RID"), M_AXI_GP0_BRESP("M_AXI_GP0_BRESP"), M_AXI_GP0_RRESP("M_AXI_GP0_RRESP"), M_AXI_GP0_RDATA("M_AXI_GP0_RDATA"), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
|
||||
{
|
||||
// initialize pins
|
||||
mp_impl->GPIO_I(GPIO_I);
|
||||
mp_impl->GPIO_O(GPIO_O);
|
||||
mp_impl->GPIO_T(GPIO_T);
|
||||
mp_impl->M_AXI_GP0_ACLK(M_AXI_GP0_ACLK);
|
||||
mp_impl->FCLK_CLK0(FCLK_CLK0);
|
||||
mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
|
||||
mp_impl->MIO(MIO);
|
||||
mp_impl->DDR_CAS_n(DDR_CAS_n);
|
||||
mp_impl->DDR_CKE(DDR_CKE);
|
||||
mp_impl->DDR_Clk_n(DDR_Clk_n);
|
||||
mp_impl->DDR_Clk(DDR_Clk);
|
||||
mp_impl->DDR_CS_n(DDR_CS_n);
|
||||
mp_impl->DDR_DRSTB(DDR_DRSTB);
|
||||
mp_impl->DDR_ODT(DDR_ODT);
|
||||
mp_impl->DDR_RAS_n(DDR_RAS_n);
|
||||
mp_impl->DDR_WEB(DDR_WEB);
|
||||
mp_impl->DDR_BankAddr(DDR_BankAddr);
|
||||
mp_impl->DDR_Addr(DDR_Addr);
|
||||
mp_impl->DDR_VRN(DDR_VRN);
|
||||
mp_impl->DDR_VRP(DDR_VRP);
|
||||
mp_impl->DDR_DM(DDR_DM);
|
||||
mp_impl->DDR_DQ(DDR_DQ);
|
||||
mp_impl->DDR_DQS_n(DDR_DQS_n);
|
||||
mp_impl->DDR_DQS(DDR_DQS);
|
||||
mp_impl->PS_SRSTB(PS_SRSTB);
|
||||
mp_impl->PS_CLK(PS_CLK);
|
||||
mp_impl->PS_PORB(PS_PORB);
|
||||
|
||||
// initialize transactors
|
||||
mp_M_AXI_GP0_transactor = NULL;
|
||||
mp_M_AXI_GP0_ARLOCK_converter = NULL;
|
||||
mp_M_AXI_GP0_AWLOCK_converter = NULL;
|
||||
mp_M_AXI_GP0_ARLEN_converter = NULL;
|
||||
mp_M_AXI_GP0_AWLEN_converter = NULL;
|
||||
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// configure M_AXI_GP0_transactor
|
||||
xsc::common_cpp::properties M_AXI_GP0_transactor_param_props;
|
||||
M_AXI_GP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
M_AXI_GP0_transactor_param_props.addLong("HAS_RESET", "0");
|
||||
M_AXI_GP0_transactor_param_props.addString("NUM_WRITE_OUTSTANDING", "8");
|
||||
M_AXI_GP0_transactor_param_props.addString("NUM_READ_OUTSTANDING", "8");
|
||||
|
||||
mp_M_AXI_GP0_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>("M_AXI_GP0_transactor", M_AXI_GP0_transactor_param_props);
|
||||
mp_M_AXI_GP0_transactor->ARVALID(M_AXI_GP0_ARVALID);
|
||||
mp_M_AXI_GP0_transactor->AWVALID(M_AXI_GP0_AWVALID);
|
||||
mp_M_AXI_GP0_transactor->BREADY(M_AXI_GP0_BREADY);
|
||||
mp_M_AXI_GP0_transactor->RREADY(M_AXI_GP0_RREADY);
|
||||
mp_M_AXI_GP0_transactor->WLAST(M_AXI_GP0_WLAST);
|
||||
mp_M_AXI_GP0_transactor->WVALID(M_AXI_GP0_WVALID);
|
||||
mp_M_AXI_GP0_transactor->ARID(M_AXI_GP0_ARID);
|
||||
mp_M_AXI_GP0_transactor->AWID(M_AXI_GP0_AWID);
|
||||
mp_M_AXI_GP0_transactor->ARBURST(M_AXI_GP0_ARBURST);
|
||||
mp_M_AXI_GP0_ARLOCK_converter = new xsc::common::scalar2vectorN_converter<2>("M_AXI_GP0_ARLOCK_converter");
|
||||
mp_M_AXI_GP0_ARLOCK_converter->scalar_in(m_M_AXI_GP0_ARLOCK_converter_signal);
|
||||
mp_M_AXI_GP0_ARLOCK_converter->vector_out(M_AXI_GP0_ARLOCK);
|
||||
mp_M_AXI_GP0_transactor->ARLOCK(m_M_AXI_GP0_ARLOCK_converter_signal);
|
||||
mp_M_AXI_GP0_transactor->ARSIZE(M_AXI_GP0_ARSIZE);
|
||||
mp_M_AXI_GP0_transactor->AWBURST(M_AXI_GP0_AWBURST);
|
||||
mp_M_AXI_GP0_AWLOCK_converter = new xsc::common::scalar2vectorN_converter<2>("M_AXI_GP0_AWLOCK_converter");
|
||||
mp_M_AXI_GP0_AWLOCK_converter->scalar_in(m_M_AXI_GP0_AWLOCK_converter_signal);
|
||||
mp_M_AXI_GP0_AWLOCK_converter->vector_out(M_AXI_GP0_AWLOCK);
|
||||
mp_M_AXI_GP0_transactor->AWLOCK(m_M_AXI_GP0_AWLOCK_converter_signal);
|
||||
mp_M_AXI_GP0_transactor->AWSIZE(M_AXI_GP0_AWSIZE);
|
||||
mp_M_AXI_GP0_transactor->ARPROT(M_AXI_GP0_ARPROT);
|
||||
mp_M_AXI_GP0_transactor->AWPROT(M_AXI_GP0_AWPROT);
|
||||
mp_M_AXI_GP0_transactor->ARADDR(M_AXI_GP0_ARADDR);
|
||||
mp_M_AXI_GP0_transactor->AWADDR(M_AXI_GP0_AWADDR);
|
||||
mp_M_AXI_GP0_transactor->WDATA(M_AXI_GP0_WDATA);
|
||||
mp_M_AXI_GP0_transactor->ARCACHE(M_AXI_GP0_ARCACHE);
|
||||
mp_M_AXI_GP0_ARLEN_converter = new xsc::common::vector2vector_converter<8,4>("M_AXI_GP0_ARLEN_converter");
|
||||
mp_M_AXI_GP0_ARLEN_converter->vector_in(m_M_AXI_GP0_ARLEN_converter_signal);
|
||||
mp_M_AXI_GP0_ARLEN_converter->vector_out(M_AXI_GP0_ARLEN);
|
||||
mp_M_AXI_GP0_transactor->ARLEN(m_M_AXI_GP0_ARLEN_converter_signal);
|
||||
mp_M_AXI_GP0_transactor->ARQOS(M_AXI_GP0_ARQOS);
|
||||
mp_M_AXI_GP0_transactor->AWCACHE(M_AXI_GP0_AWCACHE);
|
||||
mp_M_AXI_GP0_AWLEN_converter = new xsc::common::vector2vector_converter<8,4>("M_AXI_GP0_AWLEN_converter");
|
||||
mp_M_AXI_GP0_AWLEN_converter->vector_in(m_M_AXI_GP0_AWLEN_converter_signal);
|
||||
mp_M_AXI_GP0_AWLEN_converter->vector_out(M_AXI_GP0_AWLEN);
|
||||
mp_M_AXI_GP0_transactor->AWLEN(m_M_AXI_GP0_AWLEN_converter_signal);
|
||||
mp_M_AXI_GP0_transactor->AWQOS(M_AXI_GP0_AWQOS);
|
||||
mp_M_AXI_GP0_transactor->WSTRB(M_AXI_GP0_WSTRB);
|
||||
mp_M_AXI_GP0_transactor->ARREADY(M_AXI_GP0_ARREADY);
|
||||
mp_M_AXI_GP0_transactor->AWREADY(M_AXI_GP0_AWREADY);
|
||||
mp_M_AXI_GP0_transactor->BVALID(M_AXI_GP0_BVALID);
|
||||
mp_M_AXI_GP0_transactor->RLAST(M_AXI_GP0_RLAST);
|
||||
mp_M_AXI_GP0_transactor->RVALID(M_AXI_GP0_RVALID);
|
||||
mp_M_AXI_GP0_transactor->WREADY(M_AXI_GP0_WREADY);
|
||||
mp_M_AXI_GP0_transactor->BID(M_AXI_GP0_BID);
|
||||
mp_M_AXI_GP0_transactor->RID(M_AXI_GP0_RID);
|
||||
mp_M_AXI_GP0_transactor->BRESP(M_AXI_GP0_BRESP);
|
||||
mp_M_AXI_GP0_transactor->RRESP(M_AXI_GP0_RRESP);
|
||||
mp_M_AXI_GP0_transactor->RDATA(M_AXI_GP0_RDATA);
|
||||
mp_M_AXI_GP0_transactor->CLK(M_AXI_GP0_ACLK);
|
||||
m_M_AXI_GP0_transactor_rst_signal.write(1);
|
||||
mp_M_AXI_GP0_transactor->RST(m_M_AXI_GP0_transactor_rst_signal);
|
||||
|
||||
// initialize transactors stubs
|
||||
M_AXI_GP0_transactor_initiator_wr_socket_stub = nullptr;
|
||||
M_AXI_GP0_transactor_initiator_rd_socket_stub = nullptr;
|
||||
|
||||
}
|
||||
|
||||
void system_processing_system7_0_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'M_AXI_GP0' transactor
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("system_processing_system7_0_0", "M_AXI_GP0_TLM_MODE") != 1)
|
||||
{
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
M_AXI_GP0_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
|
||||
M_AXI_GP0_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_GP0_transactor->wr_socket));
|
||||
M_AXI_GP0_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
|
||||
M_AXI_GP0_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_GP0_transactor->rd_socket));
|
||||
mp_M_AXI_GP0_transactor->disable_transactor();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // MTI_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
system_processing_system7_0_0::~system_processing_system7_0_0()
|
||||
{
|
||||
delete mp_M_AXI_GP0_transactor;
|
||||
delete mp_M_AXI_GP0_ARLOCK_converter;
|
||||
delete mp_M_AXI_GP0_AWLOCK_converter;
|
||||
delete mp_M_AXI_GP0_ARLEN_converter;
|
||||
delete mp_M_AXI_GP0_AWLEN_converter;
|
||||
|
||||
}
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
SC_MODULE_EXPORT(system_processing_system7_0_0);
|
||||
#endif
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
XMSC_MODULE_EXPORT(system_processing_system7_0_0);
|
||||
#endif
|
||||
|
||||
#ifdef RIVIERA
|
||||
SC_MODULE_EXPORT(system_processing_system7_0_0);
|
||||
SC_REGISTER_BV(54);
|
||||
#endif
|
||||
|
||||
+595
@@ -0,0 +1,595 @@
|
||||
#ifndef IP_SYSTEM_PROCESSING_SYSTEM7_0_0_H_
|
||||
#define IP_SYSTEM_PROCESSING_SYSTEM7_0_0_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
#include "system_processing_system7_0_0_sc.h"
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XILINX_SIMULATOR
|
||||
class DllExport system_processing_system7_0_0 : public system_processing_system7_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_processing_system7_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_processing_system7_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< sc_dt::sc_bv<33> > GPIO_I;
|
||||
sc_core::sc_out< sc_dt::sc_bv<33> > GPIO_O;
|
||||
sc_core::sc_out< sc_dt::sc_bv<33> > GPIO_T;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_BREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_RREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WLAST;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WVALID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ACLK;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_BVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RLAST;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_WREADY;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_out< bool > DDR_CAS_n;
|
||||
sc_core::sc_out< bool > DDR_CKE;
|
||||
sc_core::sc_out< bool > DDR_Clk_n;
|
||||
sc_core::sc_out< bool > DDR_Clk;
|
||||
sc_core::sc_out< bool > DDR_CS_n;
|
||||
sc_core::sc_out< bool > DDR_DRSTB;
|
||||
sc_core::sc_out< bool > DDR_ODT;
|
||||
sc_core::sc_out< bool > DDR_RAS_n;
|
||||
sc_core::sc_out< bool > DDR_WEB;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_out< bool > DDR_VRN;
|
||||
sc_core::sc_out< bool > DDR_VRP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_out< bool > PS_SRSTB;
|
||||
sc_core::sc_out< bool > PS_CLK;
|
||||
sc_core::sc_out< bool > PS_PORB;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
|
||||
|
||||
};
|
||||
#endif // XILINX_SIMULATOR
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
class DllExport system_processing_system7_0_0 : public system_processing_system7_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_processing_system7_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_processing_system7_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< sc_dt::sc_bv<33> > GPIO_I;
|
||||
sc_core::sc_out< sc_dt::sc_bv<33> > GPIO_O;
|
||||
sc_core::sc_out< sc_dt::sc_bv<33> > GPIO_T;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_BREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_RREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WLAST;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WVALID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ACLK;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_BVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RLAST;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_WREADY;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_inout< bool > DDR_CAS_n;
|
||||
sc_core::sc_inout< bool > DDR_CKE;
|
||||
sc_core::sc_inout< bool > DDR_Clk_n;
|
||||
sc_core::sc_inout< bool > DDR_Clk;
|
||||
sc_core::sc_inout< bool > DDR_CS_n;
|
||||
sc_core::sc_inout< bool > DDR_DRSTB;
|
||||
sc_core::sc_inout< bool > DDR_ODT;
|
||||
sc_core::sc_inout< bool > DDR_RAS_n;
|
||||
sc_core::sc_inout< bool > DDR_WEB;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_inout< bool > DDR_VRN;
|
||||
sc_core::sc_inout< bool > DDR_VRP;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_inout< bool > PS_SRSTB;
|
||||
sc_core::sc_inout< bool > PS_CLK;
|
||||
sc_core::sc_inout< bool > PS_PORB;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
|
||||
|
||||
};
|
||||
#endif // XM_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef RIVIERA
|
||||
class DllExport system_processing_system7_0_0 : public system_processing_system7_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_processing_system7_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_processing_system7_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< sc_dt::sc_bv<33> > GPIO_I;
|
||||
sc_core::sc_out< sc_dt::sc_bv<33> > GPIO_O;
|
||||
sc_core::sc_out< sc_dt::sc_bv<33> > GPIO_T;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_BREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_RREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WLAST;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WVALID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ACLK;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_BVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RLAST;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_WREADY;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_out< bool > DDR_CAS_n;
|
||||
sc_core::sc_out< bool > DDR_CKE;
|
||||
sc_core::sc_out< bool > DDR_Clk_n;
|
||||
sc_core::sc_out< bool > DDR_Clk;
|
||||
sc_core::sc_out< bool > DDR_CS_n;
|
||||
sc_core::sc_out< bool > DDR_DRSTB;
|
||||
sc_core::sc_out< bool > DDR_ODT;
|
||||
sc_core::sc_out< bool > DDR_RAS_n;
|
||||
sc_core::sc_out< bool > DDR_WEB;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_out< bool > DDR_VRN;
|
||||
sc_core::sc_out< bool > DDR_VRP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_out< bool > PS_SRSTB;
|
||||
sc_core::sc_out< bool > PS_CLK;
|
||||
sc_core::sc_out< bool > PS_PORB;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
|
||||
|
||||
};
|
||||
#endif // RIVIERA
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef VCSSYSTEMC
|
||||
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||
|
||||
class DllExport system_processing_system7_0_0 : public system_processing_system7_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_processing_system7_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_processing_system7_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< sc_dt::sc_bv<33> > GPIO_I;
|
||||
sc_core::sc_out< sc_dt::sc_bv<33> > GPIO_O;
|
||||
sc_core::sc_out< sc_dt::sc_bv<33> > GPIO_T;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_BREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_RREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WLAST;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WVALID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ACLK;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_BVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RLAST;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_WREADY;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_out< bool > DDR_CAS_n;
|
||||
sc_core::sc_out< bool > DDR_CKE;
|
||||
sc_core::sc_out< bool > DDR_Clk_n;
|
||||
sc_core::sc_out< bool > DDR_Clk;
|
||||
sc_core::sc_out< bool > DDR_CS_n;
|
||||
sc_core::sc_out< bool > DDR_DRSTB;
|
||||
sc_core::sc_out< bool > DDR_ODT;
|
||||
sc_core::sc_out< bool > DDR_RAS_n;
|
||||
sc_core::sc_out< bool > DDR_WEB;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_out< bool > DDR_VRN;
|
||||
sc_core::sc_out< bool > DDR_VRP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_out< bool > PS_SRSTB;
|
||||
sc_core::sc_out< bool > PS_CLK;
|
||||
sc_core::sc_out< bool > PS_PORB;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_GP0_transactor_initiator_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_GP0_transactor_initiator_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // VCSSYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||
|
||||
class DllExport system_processing_system7_0_0 : public system_processing_system7_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_processing_system7_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_processing_system7_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< sc_dt::sc_bv<33> > GPIO_I;
|
||||
sc_core::sc_out< sc_dt::sc_bv<33> > GPIO_O;
|
||||
sc_core::sc_out< sc_dt::sc_bv<33> > GPIO_T;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_BREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_RREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WLAST;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WVALID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ACLK;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_BVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RLAST;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_WREADY;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_out< bool > DDR_CAS_n;
|
||||
sc_core::sc_out< bool > DDR_CKE;
|
||||
sc_core::sc_out< bool > DDR_Clk_n;
|
||||
sc_core::sc_out< bool > DDR_Clk;
|
||||
sc_core::sc_out< bool > DDR_CS_n;
|
||||
sc_core::sc_out< bool > DDR_DRSTB;
|
||||
sc_core::sc_out< bool > DDR_ODT;
|
||||
sc_core::sc_out< bool > DDR_RAS_n;
|
||||
sc_core::sc_out< bool > DDR_WEB;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_out< bool > DDR_VRN;
|
||||
sc_core::sc_out< bool > DDR_VRP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_out< bool > PS_SRSTB;
|
||||
sc_core::sc_out< bool > PS_CLK;
|
||||
sc_core::sc_out< bool > PS_PORB;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_GP0_transactor_initiator_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_GP0_transactor_initiator_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // MTI_SYSTEMC
|
||||
#endif // IP_SYSTEM_PROCESSING_SYSTEM7_0_0_H_
|
||||
+1125
File diff suppressed because it is too large
Load Diff
+584
@@ -0,0 +1,584 @@
|
||||
|
||||
|
||||
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module system_processing_system7_0_0 (
|
||||
GPIO_I,
|
||||
GPIO_O,
|
||||
GPIO_T,
|
||||
M_AXI_GP0_ARVALID,
|
||||
M_AXI_GP0_AWVALID,
|
||||
M_AXI_GP0_BREADY,
|
||||
M_AXI_GP0_RREADY,
|
||||
M_AXI_GP0_WLAST,
|
||||
M_AXI_GP0_WVALID,
|
||||
M_AXI_GP0_ARID,
|
||||
M_AXI_GP0_AWID,
|
||||
M_AXI_GP0_WID,
|
||||
M_AXI_GP0_ARBURST,
|
||||
M_AXI_GP0_ARLOCK,
|
||||
M_AXI_GP0_ARSIZE,
|
||||
M_AXI_GP0_AWBURST,
|
||||
M_AXI_GP0_AWLOCK,
|
||||
M_AXI_GP0_AWSIZE,
|
||||
M_AXI_GP0_ARPROT,
|
||||
M_AXI_GP0_AWPROT,
|
||||
M_AXI_GP0_ARADDR,
|
||||
M_AXI_GP0_AWADDR,
|
||||
M_AXI_GP0_WDATA,
|
||||
M_AXI_GP0_ARCACHE,
|
||||
M_AXI_GP0_ARLEN,
|
||||
M_AXI_GP0_ARQOS,
|
||||
M_AXI_GP0_AWCACHE,
|
||||
M_AXI_GP0_AWLEN,
|
||||
M_AXI_GP0_AWQOS,
|
||||
M_AXI_GP0_WSTRB,
|
||||
M_AXI_GP0_ACLK,
|
||||
M_AXI_GP0_ARREADY,
|
||||
M_AXI_GP0_AWREADY,
|
||||
M_AXI_GP0_BVALID,
|
||||
M_AXI_GP0_RLAST,
|
||||
M_AXI_GP0_RVALID,
|
||||
M_AXI_GP0_WREADY,
|
||||
M_AXI_GP0_BID,
|
||||
M_AXI_GP0_RID,
|
||||
M_AXI_GP0_BRESP,
|
||||
M_AXI_GP0_RRESP,
|
||||
M_AXI_GP0_RDATA,
|
||||
FCLK_CLK0,
|
||||
FCLK_RESET0_N,
|
||||
MIO,
|
||||
DDR_CAS_n,
|
||||
DDR_CKE,
|
||||
DDR_Clk_n,
|
||||
DDR_Clk,
|
||||
DDR_CS_n,
|
||||
DDR_DRSTB,
|
||||
DDR_ODT,
|
||||
DDR_RAS_n,
|
||||
DDR_WEB,
|
||||
DDR_BankAddr,
|
||||
DDR_Addr,
|
||||
DDR_VRN,
|
||||
DDR_VRP,
|
||||
DDR_DM,
|
||||
DDR_DQ,
|
||||
DDR_DQS_n,
|
||||
DDR_DQS,
|
||||
PS_SRSTB,
|
||||
PS_CLK,
|
||||
PS_PORB
|
||||
);
|
||||
input [32 : 0] GPIO_I;
|
||||
output [32 : 0] GPIO_O;
|
||||
output [32 : 0] GPIO_T;
|
||||
output M_AXI_GP0_ARVALID;
|
||||
output M_AXI_GP0_AWVALID;
|
||||
output M_AXI_GP0_BREADY;
|
||||
output M_AXI_GP0_RREADY;
|
||||
output M_AXI_GP0_WLAST;
|
||||
output M_AXI_GP0_WVALID;
|
||||
output [11 : 0] M_AXI_GP0_ARID;
|
||||
output [11 : 0] M_AXI_GP0_AWID;
|
||||
output [11 : 0] M_AXI_GP0_WID;
|
||||
output [1 : 0] M_AXI_GP0_ARBURST;
|
||||
output [1 : 0] M_AXI_GP0_ARLOCK;
|
||||
output [2 : 0] M_AXI_GP0_ARSIZE;
|
||||
output [1 : 0] M_AXI_GP0_AWBURST;
|
||||
output [1 : 0] M_AXI_GP0_AWLOCK;
|
||||
output [2 : 0] M_AXI_GP0_AWSIZE;
|
||||
output [2 : 0] M_AXI_GP0_ARPROT;
|
||||
output [2 : 0] M_AXI_GP0_AWPROT;
|
||||
output [31 : 0] M_AXI_GP0_ARADDR;
|
||||
output [31 : 0] M_AXI_GP0_AWADDR;
|
||||
output [31 : 0] M_AXI_GP0_WDATA;
|
||||
output [3 : 0] M_AXI_GP0_ARCACHE;
|
||||
output [3 : 0] M_AXI_GP0_ARLEN;
|
||||
output [3 : 0] M_AXI_GP0_ARQOS;
|
||||
output [3 : 0] M_AXI_GP0_AWCACHE;
|
||||
output [3 : 0] M_AXI_GP0_AWLEN;
|
||||
output [3 : 0] M_AXI_GP0_AWQOS;
|
||||
output [3 : 0] M_AXI_GP0_WSTRB;
|
||||
input M_AXI_GP0_ACLK;
|
||||
input M_AXI_GP0_ARREADY;
|
||||
input M_AXI_GP0_AWREADY;
|
||||
input M_AXI_GP0_BVALID;
|
||||
input M_AXI_GP0_RLAST;
|
||||
input M_AXI_GP0_RVALID;
|
||||
input M_AXI_GP0_WREADY;
|
||||
input [11 : 0] M_AXI_GP0_BID;
|
||||
input [11 : 0] M_AXI_GP0_RID;
|
||||
input [1 : 0] M_AXI_GP0_BRESP;
|
||||
input [1 : 0] M_AXI_GP0_RRESP;
|
||||
input [31 : 0] M_AXI_GP0_RDATA;
|
||||
output FCLK_CLK0;
|
||||
output FCLK_RESET0_N;
|
||||
input [53 : 0] MIO;
|
||||
input DDR_CAS_n;
|
||||
input DDR_CKE;
|
||||
input DDR_Clk_n;
|
||||
input DDR_Clk;
|
||||
input DDR_CS_n;
|
||||
input DDR_DRSTB;
|
||||
input DDR_ODT;
|
||||
input DDR_RAS_n;
|
||||
input DDR_WEB;
|
||||
input [2 : 0] DDR_BankAddr;
|
||||
input [14 : 0] DDR_Addr;
|
||||
input DDR_VRN;
|
||||
input DDR_VRP;
|
||||
input [3 : 0] DDR_DM;
|
||||
input [31 : 0] DDR_DQ;
|
||||
input [3 : 0] DDR_DQS_n;
|
||||
input [3 : 0] DDR_DQS;
|
||||
input PS_SRSTB;
|
||||
input PS_CLK;
|
||||
input PS_PORB;
|
||||
|
||||
processing_system7_vip_v1_0_17 #(
|
||||
.C_USE_M_AXI_GP0(1),
|
||||
.C_USE_M_AXI_GP1(0),
|
||||
.C_USE_S_AXI_ACP(0),
|
||||
.C_USE_S_AXI_GP0(0),
|
||||
.C_USE_S_AXI_GP1(0),
|
||||
.C_USE_S_AXI_HP0(0),
|
||||
.C_USE_S_AXI_HP1(0),
|
||||
.C_USE_S_AXI_HP2(0),
|
||||
.C_USE_S_AXI_HP3(0),
|
||||
.C_S_AXI_HP0_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP1_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP2_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP3_DATA_WIDTH(64),
|
||||
.C_HIGH_OCM_EN(0),
|
||||
.C_FCLK_CLK0_FREQ(100.0),
|
||||
.C_FCLK_CLK1_FREQ(10.0),
|
||||
.C_FCLK_CLK2_FREQ(10.0),
|
||||
.C_FCLK_CLK3_FREQ(10.0),
|
||||
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
|
||||
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
|
||||
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
|
||||
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
|
||||
) inst (
|
||||
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
|
||||
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
|
||||
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
|
||||
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
|
||||
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
|
||||
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
|
||||
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
|
||||
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
|
||||
.M_AXI_GP0_WID(M_AXI_GP0_WID),
|
||||
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
|
||||
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
|
||||
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
|
||||
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
|
||||
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
|
||||
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
|
||||
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
|
||||
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
|
||||
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
|
||||
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
|
||||
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
|
||||
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
|
||||
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
|
||||
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
|
||||
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
|
||||
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
|
||||
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
|
||||
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
|
||||
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
|
||||
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
|
||||
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
|
||||
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
|
||||
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
|
||||
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
|
||||
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
|
||||
.M_AXI_GP0_BID(M_AXI_GP0_BID),
|
||||
.M_AXI_GP0_RID(M_AXI_GP0_RID),
|
||||
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
|
||||
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
|
||||
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
|
||||
.M_AXI_GP1_ARVALID(),
|
||||
.M_AXI_GP1_AWVALID(),
|
||||
.M_AXI_GP1_BREADY(),
|
||||
.M_AXI_GP1_RREADY(),
|
||||
.M_AXI_GP1_WLAST(),
|
||||
.M_AXI_GP1_WVALID(),
|
||||
.M_AXI_GP1_ARID(),
|
||||
.M_AXI_GP1_AWID(),
|
||||
.M_AXI_GP1_WID(),
|
||||
.M_AXI_GP1_ARBURST(),
|
||||
.M_AXI_GP1_ARLOCK(),
|
||||
.M_AXI_GP1_ARSIZE(),
|
||||
.M_AXI_GP1_AWBURST(),
|
||||
.M_AXI_GP1_AWLOCK(),
|
||||
.M_AXI_GP1_AWSIZE(),
|
||||
.M_AXI_GP1_ARPROT(),
|
||||
.M_AXI_GP1_AWPROT(),
|
||||
.M_AXI_GP1_ARADDR(),
|
||||
.M_AXI_GP1_AWADDR(),
|
||||
.M_AXI_GP1_WDATA(),
|
||||
.M_AXI_GP1_ARCACHE(),
|
||||
.M_AXI_GP1_ARLEN(),
|
||||
.M_AXI_GP1_ARQOS(),
|
||||
.M_AXI_GP1_AWCACHE(),
|
||||
.M_AXI_GP1_AWLEN(),
|
||||
.M_AXI_GP1_AWQOS(),
|
||||
.M_AXI_GP1_WSTRB(),
|
||||
.M_AXI_GP1_ACLK(1'B0),
|
||||
.M_AXI_GP1_ARREADY(1'B0),
|
||||
.M_AXI_GP1_AWREADY(1'B0),
|
||||
.M_AXI_GP1_BVALID(1'B0),
|
||||
.M_AXI_GP1_RLAST(1'B0),
|
||||
.M_AXI_GP1_RVALID(1'B0),
|
||||
.M_AXI_GP1_WREADY(1'B0),
|
||||
.M_AXI_GP1_BID(12'B0),
|
||||
.M_AXI_GP1_RID(12'B0),
|
||||
.M_AXI_GP1_BRESP(2'B0),
|
||||
.M_AXI_GP1_RRESP(2'B0),
|
||||
.M_AXI_GP1_RDATA(32'B0),
|
||||
.S_AXI_GP0_ARREADY(),
|
||||
.S_AXI_GP0_AWREADY(),
|
||||
.S_AXI_GP0_BVALID(),
|
||||
.S_AXI_GP0_RLAST(),
|
||||
.S_AXI_GP0_RVALID(),
|
||||
.S_AXI_GP0_WREADY(),
|
||||
.S_AXI_GP0_BRESP(),
|
||||
.S_AXI_GP0_RRESP(),
|
||||
.S_AXI_GP0_RDATA(),
|
||||
.S_AXI_GP0_BID(),
|
||||
.S_AXI_GP0_RID(),
|
||||
.S_AXI_GP0_ACLK(1'B0),
|
||||
.S_AXI_GP0_ARVALID(1'B0),
|
||||
.S_AXI_GP0_AWVALID(1'B0),
|
||||
.S_AXI_GP0_BREADY(1'B0),
|
||||
.S_AXI_GP0_RREADY(1'B0),
|
||||
.S_AXI_GP0_WLAST(1'B0),
|
||||
.S_AXI_GP0_WVALID(1'B0),
|
||||
.S_AXI_GP0_ARBURST(2'B0),
|
||||
.S_AXI_GP0_ARLOCK(2'B0),
|
||||
.S_AXI_GP0_ARSIZE(3'B0),
|
||||
.S_AXI_GP0_AWBURST(2'B0),
|
||||
.S_AXI_GP0_AWLOCK(2'B0),
|
||||
.S_AXI_GP0_AWSIZE(3'B0),
|
||||
.S_AXI_GP0_ARPROT(3'B0),
|
||||
.S_AXI_GP0_AWPROT(3'B0),
|
||||
.S_AXI_GP0_ARADDR(32'B0),
|
||||
.S_AXI_GP0_AWADDR(32'B0),
|
||||
.S_AXI_GP0_WDATA(32'B0),
|
||||
.S_AXI_GP0_ARCACHE(4'B0),
|
||||
.S_AXI_GP0_ARLEN(4'B0),
|
||||
.S_AXI_GP0_ARQOS(4'B0),
|
||||
.S_AXI_GP0_AWCACHE(4'B0),
|
||||
.S_AXI_GP0_AWLEN(4'B0),
|
||||
.S_AXI_GP0_AWQOS(4'B0),
|
||||
.S_AXI_GP0_WSTRB(4'B0),
|
||||
.S_AXI_GP0_ARID(6'B0),
|
||||
.S_AXI_GP0_AWID(6'B0),
|
||||
.S_AXI_GP0_WID(6'B0),
|
||||
.S_AXI_GP1_ARREADY(),
|
||||
.S_AXI_GP1_AWREADY(),
|
||||
.S_AXI_GP1_BVALID(),
|
||||
.S_AXI_GP1_RLAST(),
|
||||
.S_AXI_GP1_RVALID(),
|
||||
.S_AXI_GP1_WREADY(),
|
||||
.S_AXI_GP1_BRESP(),
|
||||
.S_AXI_GP1_RRESP(),
|
||||
.S_AXI_GP1_RDATA(),
|
||||
.S_AXI_GP1_BID(),
|
||||
.S_AXI_GP1_RID(),
|
||||
.S_AXI_GP1_ACLK(1'B0),
|
||||
.S_AXI_GP1_ARVALID(1'B0),
|
||||
.S_AXI_GP1_AWVALID(1'B0),
|
||||
.S_AXI_GP1_BREADY(1'B0),
|
||||
.S_AXI_GP1_RREADY(1'B0),
|
||||
.S_AXI_GP1_WLAST(1'B0),
|
||||
.S_AXI_GP1_WVALID(1'B0),
|
||||
.S_AXI_GP1_ARBURST(2'B0),
|
||||
.S_AXI_GP1_ARLOCK(2'B0),
|
||||
.S_AXI_GP1_ARSIZE(3'B0),
|
||||
.S_AXI_GP1_AWBURST(2'B0),
|
||||
.S_AXI_GP1_AWLOCK(2'B0),
|
||||
.S_AXI_GP1_AWSIZE(3'B0),
|
||||
.S_AXI_GP1_ARPROT(3'B0),
|
||||
.S_AXI_GP1_AWPROT(3'B0),
|
||||
.S_AXI_GP1_ARADDR(32'B0),
|
||||
.S_AXI_GP1_AWADDR(32'B0),
|
||||
.S_AXI_GP1_WDATA(32'B0),
|
||||
.S_AXI_GP1_ARCACHE(4'B0),
|
||||
.S_AXI_GP1_ARLEN(4'B0),
|
||||
.S_AXI_GP1_ARQOS(4'B0),
|
||||
.S_AXI_GP1_AWCACHE(4'B0),
|
||||
.S_AXI_GP1_AWLEN(4'B0),
|
||||
.S_AXI_GP1_AWQOS(4'B0),
|
||||
.S_AXI_GP1_WSTRB(4'B0),
|
||||
.S_AXI_GP1_ARID(6'B0),
|
||||
.S_AXI_GP1_AWID(6'B0),
|
||||
.S_AXI_GP1_WID(6'B0),
|
||||
.S_AXI_ACP_ARREADY(),
|
||||
.S_AXI_ACP_AWREADY(),
|
||||
.S_AXI_ACP_BVALID(),
|
||||
.S_AXI_ACP_RLAST(),
|
||||
.S_AXI_ACP_RVALID(),
|
||||
.S_AXI_ACP_WREADY(),
|
||||
.S_AXI_ACP_BRESP(),
|
||||
.S_AXI_ACP_RRESP(),
|
||||
.S_AXI_ACP_BID(),
|
||||
.S_AXI_ACP_RID(),
|
||||
.S_AXI_ACP_RDATA(),
|
||||
.S_AXI_ACP_ACLK(1'B0),
|
||||
.S_AXI_ACP_ARVALID(1'B0),
|
||||
.S_AXI_ACP_AWVALID(1'B0),
|
||||
.S_AXI_ACP_BREADY(1'B0),
|
||||
.S_AXI_ACP_RREADY(1'B0),
|
||||
.S_AXI_ACP_WLAST(1'B0),
|
||||
.S_AXI_ACP_WVALID(1'B0),
|
||||
.S_AXI_ACP_ARID(3'B0),
|
||||
.S_AXI_ACP_ARPROT(3'B0),
|
||||
.S_AXI_ACP_AWID(3'B0),
|
||||
.S_AXI_ACP_AWPROT(3'B0),
|
||||
.S_AXI_ACP_WID(3'B0),
|
||||
.S_AXI_ACP_ARADDR(32'B0),
|
||||
.S_AXI_ACP_AWADDR(32'B0),
|
||||
.S_AXI_ACP_ARCACHE(4'B0),
|
||||
.S_AXI_ACP_ARLEN(4'B0),
|
||||
.S_AXI_ACP_ARQOS(4'B0),
|
||||
.S_AXI_ACP_AWCACHE(4'B0),
|
||||
.S_AXI_ACP_AWLEN(4'B0),
|
||||
.S_AXI_ACP_AWQOS(4'B0),
|
||||
.S_AXI_ACP_ARBURST(2'B0),
|
||||
.S_AXI_ACP_ARLOCK(2'B0),
|
||||
.S_AXI_ACP_ARSIZE(3'B0),
|
||||
.S_AXI_ACP_AWBURST(2'B0),
|
||||
.S_AXI_ACP_AWLOCK(2'B0),
|
||||
.S_AXI_ACP_AWSIZE(3'B0),
|
||||
.S_AXI_ACP_ARUSER(5'B0),
|
||||
.S_AXI_ACP_AWUSER(5'B0),
|
||||
.S_AXI_ACP_WDATA(64'B0),
|
||||
.S_AXI_ACP_WSTRB(8'B0),
|
||||
.S_AXI_HP0_ARREADY(),
|
||||
.S_AXI_HP0_AWREADY(),
|
||||
.S_AXI_HP0_BVALID(),
|
||||
.S_AXI_HP0_RLAST(),
|
||||
.S_AXI_HP0_RVALID(),
|
||||
.S_AXI_HP0_WREADY(),
|
||||
.S_AXI_HP0_BRESP(),
|
||||
.S_AXI_HP0_RRESP(),
|
||||
.S_AXI_HP0_BID(),
|
||||
.S_AXI_HP0_RID(),
|
||||
.S_AXI_HP0_RDATA(),
|
||||
.S_AXI_HP0_ACLK(1'B0),
|
||||
.S_AXI_HP0_ARVALID(1'B0),
|
||||
.S_AXI_HP0_AWVALID(1'B0),
|
||||
.S_AXI_HP0_BREADY(1'B0),
|
||||
.S_AXI_HP0_RREADY(1'B0),
|
||||
.S_AXI_HP0_WLAST(1'B0),
|
||||
.S_AXI_HP0_WVALID(1'B0),
|
||||
.S_AXI_HP0_ARBURST(2'B0),
|
||||
.S_AXI_HP0_ARLOCK(2'B0),
|
||||
.S_AXI_HP0_ARSIZE(3'B0),
|
||||
.S_AXI_HP0_AWBURST(2'B0),
|
||||
.S_AXI_HP0_AWLOCK(2'B0),
|
||||
.S_AXI_HP0_AWSIZE(3'B0),
|
||||
.S_AXI_HP0_ARPROT(3'B0),
|
||||
.S_AXI_HP0_AWPROT(3'B0),
|
||||
.S_AXI_HP0_ARADDR(32'B0),
|
||||
.S_AXI_HP0_AWADDR(32'B0),
|
||||
.S_AXI_HP0_ARCACHE(4'B0),
|
||||
.S_AXI_HP0_ARLEN(4'B0),
|
||||
.S_AXI_HP0_ARQOS(4'B0),
|
||||
.S_AXI_HP0_AWCACHE(4'B0),
|
||||
.S_AXI_HP0_AWLEN(4'B0),
|
||||
.S_AXI_HP0_AWQOS(4'B0),
|
||||
.S_AXI_HP0_ARID(6'B0),
|
||||
.S_AXI_HP0_AWID(6'B0),
|
||||
.S_AXI_HP0_WID(6'B0),
|
||||
.S_AXI_HP0_WDATA(64'B0),
|
||||
.S_AXI_HP0_WSTRB(8'B0),
|
||||
.S_AXI_HP1_ARREADY(),
|
||||
.S_AXI_HP1_AWREADY(),
|
||||
.S_AXI_HP1_BVALID(),
|
||||
.S_AXI_HP1_RLAST(),
|
||||
.S_AXI_HP1_RVALID(),
|
||||
.S_AXI_HP1_WREADY(),
|
||||
.S_AXI_HP1_BRESP(),
|
||||
.S_AXI_HP1_RRESP(),
|
||||
.S_AXI_HP1_BID(),
|
||||
.S_AXI_HP1_RID(),
|
||||
.S_AXI_HP1_RDATA(),
|
||||
.S_AXI_HP1_ACLK(1'B0),
|
||||
.S_AXI_HP1_ARVALID(1'B0),
|
||||
.S_AXI_HP1_AWVALID(1'B0),
|
||||
.S_AXI_HP1_BREADY(1'B0),
|
||||
.S_AXI_HP1_RREADY(1'B0),
|
||||
.S_AXI_HP1_WLAST(1'B0),
|
||||
.S_AXI_HP1_WVALID(1'B0),
|
||||
.S_AXI_HP1_ARBURST(2'B0),
|
||||
.S_AXI_HP1_ARLOCK(2'B0),
|
||||
.S_AXI_HP1_ARSIZE(3'B0),
|
||||
.S_AXI_HP1_AWBURST(2'B0),
|
||||
.S_AXI_HP1_AWLOCK(2'B0),
|
||||
.S_AXI_HP1_AWSIZE(3'B0),
|
||||
.S_AXI_HP1_ARPROT(3'B0),
|
||||
.S_AXI_HP1_AWPROT(3'B0),
|
||||
.S_AXI_HP1_ARADDR(32'B0),
|
||||
.S_AXI_HP1_AWADDR(32'B0),
|
||||
.S_AXI_HP1_ARCACHE(4'B0),
|
||||
.S_AXI_HP1_ARLEN(4'B0),
|
||||
.S_AXI_HP1_ARQOS(4'B0),
|
||||
.S_AXI_HP1_AWCACHE(4'B0),
|
||||
.S_AXI_HP1_AWLEN(4'B0),
|
||||
.S_AXI_HP1_AWQOS(4'B0),
|
||||
.S_AXI_HP1_ARID(6'B0),
|
||||
.S_AXI_HP1_AWID(6'B0),
|
||||
.S_AXI_HP1_WID(6'B0),
|
||||
.S_AXI_HP1_WDATA(64'B0),
|
||||
.S_AXI_HP1_WSTRB(8'B0),
|
||||
.S_AXI_HP2_ARREADY(),
|
||||
.S_AXI_HP2_AWREADY(),
|
||||
.S_AXI_HP2_BVALID(),
|
||||
.S_AXI_HP2_RLAST(),
|
||||
.S_AXI_HP2_RVALID(),
|
||||
.S_AXI_HP2_WREADY(),
|
||||
.S_AXI_HP2_BRESP(),
|
||||
.S_AXI_HP2_RRESP(),
|
||||
.S_AXI_HP2_BID(),
|
||||
.S_AXI_HP2_RID(),
|
||||
.S_AXI_HP2_RDATA(),
|
||||
.S_AXI_HP2_ACLK(1'B0),
|
||||
.S_AXI_HP2_ARVALID(1'B0),
|
||||
.S_AXI_HP2_AWVALID(1'B0),
|
||||
.S_AXI_HP2_BREADY(1'B0),
|
||||
.S_AXI_HP2_RREADY(1'B0),
|
||||
.S_AXI_HP2_WLAST(1'B0),
|
||||
.S_AXI_HP2_WVALID(1'B0),
|
||||
.S_AXI_HP2_ARBURST(2'B0),
|
||||
.S_AXI_HP2_ARLOCK(2'B0),
|
||||
.S_AXI_HP2_ARSIZE(3'B0),
|
||||
.S_AXI_HP2_AWBURST(2'B0),
|
||||
.S_AXI_HP2_AWLOCK(2'B0),
|
||||
.S_AXI_HP2_AWSIZE(3'B0),
|
||||
.S_AXI_HP2_ARPROT(3'B0),
|
||||
.S_AXI_HP2_AWPROT(3'B0),
|
||||
.S_AXI_HP2_ARADDR(32'B0),
|
||||
.S_AXI_HP2_AWADDR(32'B0),
|
||||
.S_AXI_HP2_ARCACHE(4'B0),
|
||||
.S_AXI_HP2_ARLEN(4'B0),
|
||||
.S_AXI_HP2_ARQOS(4'B0),
|
||||
.S_AXI_HP2_AWCACHE(4'B0),
|
||||
.S_AXI_HP2_AWLEN(4'B0),
|
||||
.S_AXI_HP2_AWQOS(4'B0),
|
||||
.S_AXI_HP2_ARID(6'B0),
|
||||
.S_AXI_HP2_AWID(6'B0),
|
||||
.S_AXI_HP2_WID(6'B0),
|
||||
.S_AXI_HP2_WDATA(64'B0),
|
||||
.S_AXI_HP2_WSTRB(8'B0),
|
||||
.S_AXI_HP3_ARREADY(),
|
||||
.S_AXI_HP3_AWREADY(),
|
||||
.S_AXI_HP3_BVALID(),
|
||||
.S_AXI_HP3_RLAST(),
|
||||
.S_AXI_HP3_RVALID(),
|
||||
.S_AXI_HP3_WREADY(),
|
||||
.S_AXI_HP3_BRESP(),
|
||||
.S_AXI_HP3_RRESP(),
|
||||
.S_AXI_HP3_BID(),
|
||||
.S_AXI_HP3_RID(),
|
||||
.S_AXI_HP3_RDATA(),
|
||||
.S_AXI_HP3_ACLK(1'B0),
|
||||
.S_AXI_HP3_ARVALID(1'B0),
|
||||
.S_AXI_HP3_AWVALID(1'B0),
|
||||
.S_AXI_HP3_BREADY(1'B0),
|
||||
.S_AXI_HP3_RREADY(1'B0),
|
||||
.S_AXI_HP3_WLAST(1'B0),
|
||||
.S_AXI_HP3_WVALID(1'B0),
|
||||
.S_AXI_HP3_ARBURST(2'B0),
|
||||
.S_AXI_HP3_ARLOCK(2'B0),
|
||||
.S_AXI_HP3_ARSIZE(3'B0),
|
||||
.S_AXI_HP3_AWBURST(2'B0),
|
||||
.S_AXI_HP3_AWLOCK(2'B0),
|
||||
.S_AXI_HP3_AWSIZE(3'B0),
|
||||
.S_AXI_HP3_ARPROT(3'B0),
|
||||
.S_AXI_HP3_AWPROT(3'B0),
|
||||
.S_AXI_HP3_ARADDR(32'B0),
|
||||
.S_AXI_HP3_AWADDR(32'B0),
|
||||
.S_AXI_HP3_ARCACHE(4'B0),
|
||||
.S_AXI_HP3_ARLEN(4'B0),
|
||||
.S_AXI_HP3_ARQOS(4'B0),
|
||||
.S_AXI_HP3_AWCACHE(4'B0),
|
||||
.S_AXI_HP3_AWLEN(4'B0),
|
||||
.S_AXI_HP3_AWQOS(4'B0),
|
||||
.S_AXI_HP3_ARID(6'B0),
|
||||
.S_AXI_HP3_AWID(6'B0),
|
||||
.S_AXI_HP3_WID(6'B0),
|
||||
.S_AXI_HP3_WDATA(64'B0),
|
||||
.S_AXI_HP3_WSTRB(8'B0),
|
||||
.FCLK_CLK0(FCLK_CLK0),
|
||||
|
||||
.FCLK_CLK1(),
|
||||
|
||||
.FCLK_CLK2(),
|
||||
|
||||
.FCLK_CLK3(),
|
||||
.FCLK_RESET0_N(FCLK_RESET0_N),
|
||||
.FCLK_RESET1_N(),
|
||||
.FCLK_RESET2_N(),
|
||||
.FCLK_RESET3_N(),
|
||||
.IRQ_F2P(16'B0),
|
||||
.PS_SRSTB(PS_SRSTB),
|
||||
.PS_CLK(PS_CLK),
|
||||
.PS_PORB(PS_PORB)
|
||||
);
|
||||
endmodule
|
||||
+131
@@ -0,0 +1,131 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#include "system_processing_system7_0_0_sc.h"
|
||||
|
||||
#include "processing_system7_v5_5_tlm.h"
|
||||
|
||||
#include <map>
|
||||
#include <string>
|
||||
|
||||
system_processing_system7_0_0_sc::system_processing_system7_0_0_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
|
||||
{
|
||||
// configure connectivity manager
|
||||
xsc::utils::xsc_sim_manager::addInstance("system_processing_system7_0_0", this);
|
||||
|
||||
// initialize module
|
||||
xsc::common_cpp::properties model_param_props;
|
||||
model_param_props.addLong("C_EN_EMIO_PJTAG", "0");
|
||||
model_param_props.addLong("C_EN_EMIO_ENET0", "0");
|
||||
model_param_props.addLong("C_EN_EMIO_ENET1", "0");
|
||||
model_param_props.addLong("C_EN_EMIO_TRACE", "0");
|
||||
model_param_props.addLong("C_INCLUDE_TRACE_BUFFER", "0");
|
||||
model_param_props.addLong("C_TRACE_BUFFER_FIFO_SIZE", "128");
|
||||
model_param_props.addLong("USE_TRACE_DATA_EDGE_DETECTOR", "0");
|
||||
model_param_props.addLong("C_TRACE_PIPELINE_WIDTH", "8");
|
||||
model_param_props.addLong("C_TRACE_BUFFER_CLOCK_DELAY", "12");
|
||||
model_param_props.addLong("C_EMIO_GPIO_WIDTH", "33");
|
||||
model_param_props.addLong("C_INCLUDE_ACP_TRANS_CHECK", "0");
|
||||
model_param_props.addLong("C_USE_DEFAULT_ACP_USER_VAL", "0");
|
||||
model_param_props.addLong("C_S_AXI_ACP_ARUSER_VAL", "31");
|
||||
model_param_props.addLong("C_S_AXI_ACP_AWUSER_VAL", "31");
|
||||
model_param_props.addLong("C_M_AXI_GP0_ID_WIDTH", "12");
|
||||
model_param_props.addLong("C_M_AXI_GP0_ENABLE_STATIC_REMAP", "0");
|
||||
model_param_props.addLong("C_M_AXI_GP1_ID_WIDTH", "12");
|
||||
model_param_props.addLong("C_M_AXI_GP1_ENABLE_STATIC_REMAP", "0");
|
||||
model_param_props.addLong("C_S_AXI_GP0_ID_WIDTH", "6");
|
||||
model_param_props.addLong("C_S_AXI_GP1_ID_WIDTH", "6");
|
||||
model_param_props.addLong("C_S_AXI_ACP_ID_WIDTH", "3");
|
||||
model_param_props.addLong("C_S_AXI_HP0_ID_WIDTH", "6");
|
||||
model_param_props.addLong("C_S_AXI_HP0_DATA_WIDTH", "64");
|
||||
model_param_props.addLong("C_S_AXI_HP1_ID_WIDTH", "6");
|
||||
model_param_props.addLong("C_S_AXI_HP1_DATA_WIDTH", "64");
|
||||
model_param_props.addLong("C_S_AXI_HP2_ID_WIDTH", "6");
|
||||
model_param_props.addLong("C_S_AXI_HP2_DATA_WIDTH", "64");
|
||||
model_param_props.addLong("C_S_AXI_HP3_ID_WIDTH", "6");
|
||||
model_param_props.addLong("C_S_AXI_HP3_DATA_WIDTH", "64");
|
||||
model_param_props.addLong("C_M_AXI_GP0_THREAD_ID_WIDTH", "12");
|
||||
model_param_props.addLong("C_M_AXI_GP1_THREAD_ID_WIDTH", "12");
|
||||
model_param_props.addLong("C_NUM_F2P_INTR_INPUTS", "1");
|
||||
model_param_props.addLong("C_DQ_WIDTH", "32");
|
||||
model_param_props.addLong("C_DQS_WIDTH", "4");
|
||||
model_param_props.addLong("C_DM_WIDTH", "4");
|
||||
model_param_props.addLong("C_MIO_PRIMITIVE", "54");
|
||||
model_param_props.addLong("C_TRACE_INTERNAL_WIDTH", "2");
|
||||
model_param_props.addLong("C_USE_AXI_NONSECURE", "0");
|
||||
model_param_props.addLong("C_USE_M_AXI_GP0", "1");
|
||||
model_param_props.addLong("C_USE_M_AXI_GP1", "0");
|
||||
model_param_props.addLong("C_USE_S_AXI_GP0", "0");
|
||||
model_param_props.addLong("C_USE_S_AXI_GP1", "0");
|
||||
model_param_props.addLong("C_USE_S_AXI_HP0", "0");
|
||||
model_param_props.addLong("C_USE_S_AXI_HP1", "0");
|
||||
model_param_props.addLong("C_USE_S_AXI_HP2", "0");
|
||||
model_param_props.addLong("C_USE_S_AXI_HP3", "0");
|
||||
model_param_props.addLong("C_USE_S_AXI_ACP", "0");
|
||||
model_param_props.addLong("C_GP0_EN_MODIFIABLE_TXN", "1");
|
||||
model_param_props.addLong("C_GP1_EN_MODIFIABLE_TXN", "1");
|
||||
model_param_props.addString("C_IRQ_F2P_MODE", "DIRECT");
|
||||
model_param_props.addString("C_PS7_SI_REV", "PRODUCTION");
|
||||
model_param_props.addString("C_FCLK_CLK0_BUF", "TRUE");
|
||||
model_param_props.addString("C_FCLK_CLK1_BUF", "FALSE");
|
||||
model_param_props.addString("C_FCLK_CLK2_BUF", "FALSE");
|
||||
model_param_props.addString("C_FCLK_CLK3_BUF", "FALSE");
|
||||
model_param_props.addString("C_PACKAGE_NAME", "ffg676");
|
||||
model_param_props.addString("COMPONENT_NAME", "system_processing_system7_0_0");
|
||||
|
||||
mp_impl = new processing_system7_v5_5_tlm("inst", model_param_props);
|
||||
}
|
||||
|
||||
system_processing_system7_0_0_sc::~system_processing_system7_0_0_sc()
|
||||
{
|
||||
xsc::utils::xsc_sim_manager::clean();
|
||||
|
||||
delete mp_impl;
|
||||
}
|
||||
|
||||
+94
@@ -0,0 +1,94 @@
|
||||
#ifndef IP_SYSTEM_PROCESSING_SYSTEM7_0_0_SC_H_
|
||||
#define IP_SYSTEM_PROCESSING_SYSTEM7_0_0_SC_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
class processing_system7_v5_5_tlm;
|
||||
|
||||
class DllExport system_processing_system7_0_0_sc : public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
|
||||
system_processing_system7_0_0_sc(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_processing_system7_0_0_sc();
|
||||
|
||||
// module socket-to-socket AXI TLM interfaces
|
||||
|
||||
|
||||
// module socket-to-socket TLM interfaces
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
processing_system7_v5_5_tlm* mp_impl;
|
||||
|
||||
private:
|
||||
|
||||
system_processing_system7_0_0_sc(const system_processing_system7_0_0_sc&);
|
||||
const system_processing_system7_0_0_sc& operator=(const system_processing_system7_0_0_sc&);
|
||||
|
||||
};
|
||||
|
||||
#endif // IP_SYSTEM_PROCESSING_SYSTEM7_0_0_SC_H_
|
||||
+209
@@ -0,0 +1,209 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------------
|
||||
// Filename: system_processing_system7_0_0_stub.sv
|
||||
// Description: This HDL file is intended to be used with following simulators only:
|
||||
//
|
||||
// Vivado Simulator (XSim)
|
||||
// Cadence Xcelium Simulator
|
||||
//
|
||||
//------------------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`ifdef XILINX_SIMULATOR
|
||||
|
||||
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||
`define XILINX_SIMULATOR_BITASBOOL
|
||||
typedef bit bit_as_bool;
|
||||
`endif
|
||||
|
||||
(* SC_MODULE_EXPORT *)
|
||||
module system_processing_system7_0_0 (
|
||||
input bit [32 : 0] GPIO_I,
|
||||
output bit [32 : 0] GPIO_O,
|
||||
output bit [32 : 0] GPIO_T,
|
||||
output bit_as_bool M_AXI_GP0_ARVALID,
|
||||
output bit_as_bool M_AXI_GP0_AWVALID,
|
||||
output bit_as_bool M_AXI_GP0_BREADY,
|
||||
output bit_as_bool M_AXI_GP0_RREADY,
|
||||
output bit_as_bool M_AXI_GP0_WLAST,
|
||||
output bit_as_bool M_AXI_GP0_WVALID,
|
||||
output bit [11 : 0] M_AXI_GP0_ARID,
|
||||
output bit [11 : 0] M_AXI_GP0_AWID,
|
||||
output bit [11 : 0] M_AXI_GP0_WID,
|
||||
output bit [1 : 0] M_AXI_GP0_ARBURST,
|
||||
output bit [1 : 0] M_AXI_GP0_ARLOCK,
|
||||
output bit [2 : 0] M_AXI_GP0_ARSIZE,
|
||||
output bit [1 : 0] M_AXI_GP0_AWBURST,
|
||||
output bit [1 : 0] M_AXI_GP0_AWLOCK,
|
||||
output bit [2 : 0] M_AXI_GP0_AWSIZE,
|
||||
output bit [2 : 0] M_AXI_GP0_ARPROT,
|
||||
output bit [2 : 0] M_AXI_GP0_AWPROT,
|
||||
output bit [31 : 0] M_AXI_GP0_ARADDR,
|
||||
output bit [31 : 0] M_AXI_GP0_AWADDR,
|
||||
output bit [31 : 0] M_AXI_GP0_WDATA,
|
||||
output bit [3 : 0] M_AXI_GP0_ARCACHE,
|
||||
output bit [3 : 0] M_AXI_GP0_ARLEN,
|
||||
output bit [3 : 0] M_AXI_GP0_ARQOS,
|
||||
output bit [3 : 0] M_AXI_GP0_AWCACHE,
|
||||
output bit [3 : 0] M_AXI_GP0_AWLEN,
|
||||
output bit [3 : 0] M_AXI_GP0_AWQOS,
|
||||
output bit [3 : 0] M_AXI_GP0_WSTRB,
|
||||
input bit_as_bool M_AXI_GP0_ACLK,
|
||||
input bit_as_bool M_AXI_GP0_ARREADY,
|
||||
input bit_as_bool M_AXI_GP0_AWREADY,
|
||||
input bit_as_bool M_AXI_GP0_BVALID,
|
||||
input bit_as_bool M_AXI_GP0_RLAST,
|
||||
input bit_as_bool M_AXI_GP0_RVALID,
|
||||
input bit_as_bool M_AXI_GP0_WREADY,
|
||||
input bit [11 : 0] M_AXI_GP0_BID,
|
||||
input bit [11 : 0] M_AXI_GP0_RID,
|
||||
input bit [1 : 0] M_AXI_GP0_BRESP,
|
||||
input bit [1 : 0] M_AXI_GP0_RRESP,
|
||||
input bit [31 : 0] M_AXI_GP0_RDATA,
|
||||
output bit_as_bool FCLK_CLK0,
|
||||
output bit_as_bool FCLK_RESET0_N,
|
||||
output bit [53 : 0] MIO,
|
||||
output bit_as_bool DDR_CAS_n,
|
||||
output bit_as_bool DDR_CKE,
|
||||
output bit_as_bool DDR_Clk_n,
|
||||
output bit_as_bool DDR_Clk,
|
||||
output bit_as_bool DDR_CS_n,
|
||||
output bit_as_bool DDR_DRSTB,
|
||||
output bit_as_bool DDR_ODT,
|
||||
output bit_as_bool DDR_RAS_n,
|
||||
output bit_as_bool DDR_WEB,
|
||||
output bit [2 : 0] DDR_BankAddr,
|
||||
output bit [14 : 0] DDR_Addr,
|
||||
output bit_as_bool DDR_VRN,
|
||||
output bit_as_bool DDR_VRP,
|
||||
output bit [3 : 0] DDR_DM,
|
||||
output bit [31 : 0] DDR_DQ,
|
||||
output bit [3 : 0] DDR_DQS_n,
|
||||
output bit [3 : 0] DDR_DQS,
|
||||
output bit_as_bool PS_SRSTB,
|
||||
output bit_as_bool PS_CLK,
|
||||
output bit_as_bool PS_PORB
|
||||
);
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef XCELIUM
|
||||
(* XMSC_MODULE_EXPORT *)
|
||||
module system_processing_system7_0_0 (GPIO_I,GPIO_O,GPIO_T,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID,M_AXI_GP0_AWID,M_AXI_GP0_WID,M_AXI_GP0_ARBURST,M_AXI_GP0_ARLOCK,M_AXI_GP0_ARSIZE,M_AXI_GP0_AWBURST,M_AXI_GP0_AWLOCK,M_AXI_GP0_AWSIZE,M_AXI_GP0_ARPROT,M_AXI_GP0_AWPROT,M_AXI_GP0_ARADDR,M_AXI_GP0_AWADDR,M_AXI_GP0_WDATA,M_AXI_GP0_ARCACHE,M_AXI_GP0_ARLEN,M_AXI_GP0_ARQOS,M_AXI_GP0_AWCACHE,M_AXI_GP0_AWLEN,M_AXI_GP0_AWQOS,M_AXI_GP0_WSTRB,M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID,M_AXI_GP0_RID,M_AXI_GP0_BRESP,M_AXI_GP0_RRESP,M_AXI_GP0_RDATA,FCLK_CLK0,FCLK_RESET0_N,MIO,DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr,DDR_Addr,DDR_VRN,DDR_VRP,DDR_DM,DDR_DQ,DDR_DQS_n,DDR_DQS,PS_SRSTB,PS_CLK,PS_PORB)
|
||||
(* integer foreign = "SystemC";
|
||||
*);
|
||||
input bit [32 : 0] GPIO_I;
|
||||
output wire [32 : 0] GPIO_O;
|
||||
output wire [32 : 0] GPIO_T;
|
||||
output wire M_AXI_GP0_ARVALID;
|
||||
output wire M_AXI_GP0_AWVALID;
|
||||
output wire M_AXI_GP0_BREADY;
|
||||
output wire M_AXI_GP0_RREADY;
|
||||
output wire M_AXI_GP0_WLAST;
|
||||
output wire M_AXI_GP0_WVALID;
|
||||
output wire [11 : 0] M_AXI_GP0_ARID;
|
||||
output wire [11 : 0] M_AXI_GP0_AWID;
|
||||
output wire [11 : 0] M_AXI_GP0_WID;
|
||||
output wire [1 : 0] M_AXI_GP0_ARBURST;
|
||||
output wire [1 : 0] M_AXI_GP0_ARLOCK;
|
||||
output wire [2 : 0] M_AXI_GP0_ARSIZE;
|
||||
output wire [1 : 0] M_AXI_GP0_AWBURST;
|
||||
output wire [1 : 0] M_AXI_GP0_AWLOCK;
|
||||
output wire [2 : 0] M_AXI_GP0_AWSIZE;
|
||||
output wire [2 : 0] M_AXI_GP0_ARPROT;
|
||||
output wire [2 : 0] M_AXI_GP0_AWPROT;
|
||||
output wire [31 : 0] M_AXI_GP0_ARADDR;
|
||||
output wire [31 : 0] M_AXI_GP0_AWADDR;
|
||||
output wire [31 : 0] M_AXI_GP0_WDATA;
|
||||
output wire [3 : 0] M_AXI_GP0_ARCACHE;
|
||||
output wire [3 : 0] M_AXI_GP0_ARLEN;
|
||||
output wire [3 : 0] M_AXI_GP0_ARQOS;
|
||||
output wire [3 : 0] M_AXI_GP0_AWCACHE;
|
||||
output wire [3 : 0] M_AXI_GP0_AWLEN;
|
||||
output wire [3 : 0] M_AXI_GP0_AWQOS;
|
||||
output wire [3 : 0] M_AXI_GP0_WSTRB;
|
||||
input bit M_AXI_GP0_ACLK;
|
||||
input bit M_AXI_GP0_ARREADY;
|
||||
input bit M_AXI_GP0_AWREADY;
|
||||
input bit M_AXI_GP0_BVALID;
|
||||
input bit M_AXI_GP0_RLAST;
|
||||
input bit M_AXI_GP0_RVALID;
|
||||
input bit M_AXI_GP0_WREADY;
|
||||
input bit [11 : 0] M_AXI_GP0_BID;
|
||||
input bit [11 : 0] M_AXI_GP0_RID;
|
||||
input bit [1 : 0] M_AXI_GP0_BRESP;
|
||||
input bit [1 : 0] M_AXI_GP0_RRESP;
|
||||
input bit [31 : 0] M_AXI_GP0_RDATA;
|
||||
output wire FCLK_CLK0;
|
||||
output wire FCLK_RESET0_N;
|
||||
inout wire [53 : 0] MIO;
|
||||
inout wire DDR_CAS_n;
|
||||
inout wire DDR_CKE;
|
||||
inout wire DDR_Clk_n;
|
||||
inout wire DDR_Clk;
|
||||
inout wire DDR_CS_n;
|
||||
inout wire DDR_DRSTB;
|
||||
inout wire DDR_ODT;
|
||||
inout wire DDR_RAS_n;
|
||||
inout wire DDR_WEB;
|
||||
inout wire [2 : 0] DDR_BankAddr;
|
||||
inout wire [14 : 0] DDR_Addr;
|
||||
inout wire DDR_VRN;
|
||||
inout wire DDR_VRP;
|
||||
inout wire [3 : 0] DDR_DM;
|
||||
inout wire [31 : 0] DDR_DQ;
|
||||
inout wire [3 : 0] DDR_DQS_n;
|
||||
inout wire [3 : 0] DDR_DQS;
|
||||
inout wire PS_SRSTB;
|
||||
inout wire PS_CLK;
|
||||
inout wire PS_PORB;
|
||||
endmodule
|
||||
`endif
|
||||
+170
@@ -0,0 +1,170 @@
|
||||
// (c) Copyright(C) 2013 - 2018 by Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
#ifndef _B_TRANSPORT_CONVERTER_H_
|
||||
#define _B_TRANSPORT_CONVERTER_H_
|
||||
|
||||
#include <systemc>
|
||||
#include "tlm_utils/simple_target_socket.h"
|
||||
#include "tlm_utils/simple_initiator_socket.h"
|
||||
#include <utility>
|
||||
#include <vector>
|
||||
|
||||
template<int IN_WIDTH, int OUT_WIDTH>
|
||||
class b_transport_converter: public sc_core::sc_module
|
||||
{
|
||||
enum TLM_IF_TYPE
|
||||
{
|
||||
B_TRANSPORT = 0,
|
||||
NB_TRANSPORT,
|
||||
TRANSPORT_DBG,
|
||||
DMI_IF,
|
||||
INVALID_IF
|
||||
};
|
||||
typedef std::vector<std::pair<sc_dt::uint64, sc_dt::uint64>> addr_range_list;
|
||||
|
||||
public:
|
||||
SC_HAS_PROCESS(b_transport_converter);
|
||||
b_transport_converter<IN_WIDTH, OUT_WIDTH>(sc_core::sc_module_name name):
|
||||
sc_module(name)
|
||||
{
|
||||
target_socket.register_b_transport(
|
||||
this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::b_transport);
|
||||
initiator_socket.register_nb_transport_bw(
|
||||
this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::nb_transport_bw);
|
||||
|
||||
}
|
||||
|
||||
//simple tlm target/initiator socket...
|
||||
tlm_utils::simple_target_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, IN_WIDTH> target_socket;
|
||||
tlm_utils::simple_initiator_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, OUT_WIDTH> initiator_socket;
|
||||
|
||||
|
||||
public:
|
||||
void b_transport(tlm::tlm_generic_payload& payload, sc_core::sc_time& time)
|
||||
{
|
||||
tlm::tlm_phase phase = tlm::BEGIN_REQ; //for nb_transport_fw
|
||||
switch(get_tlm_if_type(payload.get_address()))
|
||||
{
|
||||
case B_TRANSPORT:
|
||||
initiator_socket->b_transport(payload, time);
|
||||
break;
|
||||
|
||||
case NB_TRANSPORT:
|
||||
initiator_socket->nb_transport_fw(payload, phase, time);
|
||||
wait(resp_complete_event); //! Wait for the response to complete
|
||||
break;
|
||||
|
||||
case TRANSPORT_DBG:
|
||||
initiator_socket->transport_dbg(payload);
|
||||
break;
|
||||
|
||||
case DMI_IF:
|
||||
break;
|
||||
|
||||
default:
|
||||
SC_REPORT_ERROR(this->name(), "Address not mapped to any of the TLM IF type");
|
||||
}
|
||||
}
|
||||
|
||||
tlm::tlm_sync_enum
|
||||
nb_transport_bw(tlm::tlm_generic_payload& payload,
|
||||
tlm::tlm_phase& phase, sc_core::sc_time& time)
|
||||
{
|
||||
if(phase == tlm::BEGIN_RESP) {
|
||||
resp_complete_event.notify();
|
||||
phase = tlm::END_RESP;
|
||||
return tlm::TLM_UPDATED;
|
||||
}
|
||||
return tlm::TLM_ACCEPTED;
|
||||
}
|
||||
|
||||
private:
|
||||
TLM_IF_TYPE get_tlm_if_type(unsigned long long address)
|
||||
{
|
||||
//check for b_transport addresses
|
||||
for(auto& addr_range: m_b_transport_addr_list) {
|
||||
if(address >= addr_range.first && address < addr_range.second) {
|
||||
return B_TRANSPORT;
|
||||
}
|
||||
}
|
||||
|
||||
//check for nb_transport addresses
|
||||
for(auto& addr_range: m_nb_transport_addr_list) {
|
||||
if(address >= addr_range.first && address < addr_range.second) {
|
||||
return NB_TRANSPORT;
|
||||
}
|
||||
}
|
||||
//check for dbg_transport addresses
|
||||
for(auto& addr_range: m_dbg_transport_addr_list) {
|
||||
if(address >= addr_range.first && address < addr_range.second) {
|
||||
return TRANSPORT_DBG;
|
||||
}
|
||||
}
|
||||
|
||||
//By default return NB_TRANSPORT
|
||||
return NB_TRANSPORT;
|
||||
}
|
||||
|
||||
//Start and End Address List for each of interfaces...
|
||||
static addr_range_list m_b_transport_addr_list;
|
||||
static addr_range_list m_nb_transport_addr_list;
|
||||
static addr_range_list m_dbg_transport_addr_list;
|
||||
|
||||
//event to notify completion of transaction
|
||||
sc_core::sc_event resp_complete_event;
|
||||
};
|
||||
|
||||
template<int IN_WIDTH, int OUT_WIDTH>
|
||||
typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_b_transport_addr_list = {std::make_pair(0, 0)};
|
||||
template<int IN_WIDTH, int OUT_WIDTH>
|
||||
typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_nb_transport_addr_list = {std::make_pair(0, 0)};
|
||||
template<int IN_WIDTH, int OUT_WIDTH>
|
||||
typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_dbg_transport_addr_list = {std::make_pair(0, 0)};
|
||||
|
||||
|
||||
#endif /* _B_TRANSPORT_CONVERTER_H_ */
|
||||
|
||||
+244
@@ -0,0 +1,244 @@
|
||||
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
#include"processing_system7_v5_5_tlm.h"
|
||||
#include<string>
|
||||
|
||||
template <int IN_WIDTH, int OUT_WIDTH>
|
||||
rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>::rptlm2xtlm_converter(sc_module_name name):sc_module(name)
|
||||
,target_socket("target_socket")
|
||||
,wr_socket("init_wr_socket",OUT_WIDTH)
|
||||
,rd_socket("init_rd_socket",OUT_WIDTH)
|
||||
,m_btrans_conv("b_transport_converter")
|
||||
,xtlm_bridge("tlm2xtlmbridge")
|
||||
{
|
||||
target_socket.bind(m_btrans_conv.target_socket);
|
||||
m_btrans_conv.initiator_socket.bind(xtlm_bridge.target_socket);
|
||||
xtlm_bridge.rd_socket->bind(rd_socket);
|
||||
xtlm_bridge.wr_socket->bind(wr_socket);
|
||||
}
|
||||
template <int IN_WIDTH, int OUT_WIDTH>
|
||||
void rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>::registerUserExtensionHandlerCallback(
|
||||
void (*callback)(xtlm::aximm_payload*,
|
||||
const tlm::tlm_generic_payload*)) {
|
||||
xtlm_bridge.registerUserExtensionHandlerCallback(callback);
|
||||
}
|
||||
|
||||
/***************************************************************************************
|
||||
* Global method, get registered with tlm2xtlm bridge
|
||||
* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
|
||||
*
|
||||
* caller: tlm2xtlm bridge
|
||||
* purpose: To get master id and other parameters out of genattr_extension
|
||||
* and use master id to AxUSER PIN of xtlm payload.
|
||||
*
|
||||
*
|
||||
***************************************************************************************/
|
||||
|
||||
void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp)
|
||||
{
|
||||
if((xtlm_pay == NULL) || (gp == NULL))
|
||||
return;
|
||||
if((gp->get_command() == tlm::TLM_WRITE_COMMAND) && (xtlm_pay->get_awuser_size() > 0))
|
||||
{
|
||||
genattr_extension* ext = NULL;
|
||||
gp->get_extension(ext);
|
||||
if(ext == NULL)
|
||||
return;
|
||||
//Portion of master ID(master_id[5:0]) are transfered on AxUSER bits(refere Zynq UltraScale+ TRM page.no:414)
|
||||
uint32_t val = ext->get_master_id() && 0x3F;
|
||||
unsigned char* ptr = xtlm_pay->get_awuser_ptr();
|
||||
unsigned int size = xtlm_pay->get_awuser_size();
|
||||
*ptr = (unsigned char)val;
|
||||
|
||||
}
|
||||
else if((gp->get_command() == tlm::TLM_READ_COMMAND) && (xtlm_pay->get_aruser_size() > 0))
|
||||
{
|
||||
genattr_extension* ext = NULL;
|
||||
gp->get_extension(ext);
|
||||
if(ext == NULL)
|
||||
return;
|
||||
//Portion of master ID(master_id[5:0]) are transfered on AxUSER bits(refere Zynq UltraScale+ TRM page.no:414)
|
||||
uint32_t val = ext->get_master_id() && 0x3F;
|
||||
unsigned char* ptr = xtlm_pay->get_aruser_ptr();
|
||||
unsigned int size = xtlm_pay->get_aruser_size();
|
||||
*ptr = (unsigned char)val;
|
||||
}
|
||||
}
|
||||
|
||||
/***************************************************************************************
|
||||
* Global method, get registered with xtlm2tlm bridge
|
||||
* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
|
||||
*
|
||||
* caller: xtlm2tlm bridge
|
||||
* purpose: To create and add master id and other parameters to genattr_extension.
|
||||
* Master id red from AxID PIN of xtlm payload.
|
||||
*
|
||||
*
|
||||
***************************************************************************************/
|
||||
void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp)
|
||||
{
|
||||
if(gp == NULL)
|
||||
return;
|
||||
uint8_t val = 0;
|
||||
if((gp->get_command() != tlm::TLM_WRITE_COMMAND) && (gp->get_command() != tlm::TLM_READ_COMMAND))
|
||||
return;
|
||||
//portion of master ID bits(master_id[5:0]) are derived from the AXI ID(AWID/ARID). (refere Zynq UltraScale+ TRM page.no:414,415)
|
||||
//val = (*(uint8_t*)(xtlm_pay->get_axi_id())) && 0x3F;
|
||||
genattr_extension* ext = new genattr_extension;
|
||||
ext->set_master_id(val);
|
||||
gp->set_extension(ext);
|
||||
gp->set_streaming_width(gp->get_data_length());
|
||||
if(gp->get_command() != tlm::TLM_WRITE_COMMAND)
|
||||
{
|
||||
gp->set_byte_enable_length(0);
|
||||
gp->set_byte_enable_ptr(0);
|
||||
}
|
||||
}
|
||||
|
||||
processing_system7_v5_5_tlm :: processing_system7_v5_5_tlm (sc_core::sc_module_name name,
|
||||
xsc::common_cpp::properties& _prop): sc_module(name)//registering module name with parent
|
||||
,GPIO_I("GPIO_I")
|
||||
,GPIO_O("GPIO_O")
|
||||
,GPIO_T("GPIO_T")
|
||||
,M_AXI_GP0_ACLK("M_AXI_GP0_ACLK")
|
||||
,FCLK_CLK0("FCLK_CLK0")
|
||||
,FCLK_RESET0_N("FCLK_RESET0_N")
|
||||
,MIO("MIO")
|
||||
,DDR_CAS_n("DDR_CAS_n")
|
||||
,DDR_CKE("DDR_CKE")
|
||||
,DDR_Clk_n("DDR_Clk_n")
|
||||
,DDR_Clk("DDR_Clk")
|
||||
,DDR_CS_n("DDR_CS_n")
|
||||
,DDR_DRSTB("DDR_DRSTB")
|
||||
,DDR_ODT("DDR_ODT")
|
||||
,DDR_RAS_n("DDR_RAS_n")
|
||||
,DDR_WEB("DDR_WEB")
|
||||
,DDR_BankAddr("DDR_BankAddr")
|
||||
,DDR_Addr("DDR_Addr")
|
||||
,DDR_VRN("DDR_VRN")
|
||||
,DDR_VRP("DDR_VRP")
|
||||
,DDR_DM("DDR_DM")
|
||||
,DDR_DQ("DDR_DQ")
|
||||
,DDR_DQS_n("DDR_DQS_n")
|
||||
,DDR_DQS("DDR_DQS")
|
||||
,PS_SRSTB("PS_SRSTB")
|
||||
,PS_CLK("PS_CLK")
|
||||
,PS_PORB("PS_PORB")
|
||||
,m_rp_bridge_M_AXI_GP0("m_rp_bridge_M_AXI_GP0")
|
||||
,FCLK_CLK0_clk("FCLK_CLK0_clk", sc_time(10000.0,sc_core::SC_PS))//clock period in picoseconds = 1000000/freq(in MZ)
|
||||
,prop(_prop)
|
||||
{
|
||||
//creating instances of xtlm slave sockets
|
||||
//creating instances of xtlm master sockets
|
||||
M_AXI_GP0_wr_socket = new xtlm::xtlm_aximm_initiator_socket("M_AXI_GP0_wr_socket", 32);
|
||||
M_AXI_GP0_rd_socket = new xtlm::xtlm_aximm_initiator_socket("M_AXI_GP0_rd_socket", 32);
|
||||
|
||||
char* unix_path = getenv("COSIM_MACHINE_PATH");
|
||||
char* tcpip_addr = getenv("COSIM_MACHINE_TCPIP_ADDRESS");
|
||||
char* dir_path_to_test_machine;
|
||||
bool unix_socket_en = false;
|
||||
if (unix_path != nullptr) {
|
||||
dir_path_to_test_machine = strdup(unix_path);
|
||||
unix_socket_en = true;
|
||||
}
|
||||
if ((unix_socket_en == false) && (tcpip_addr != nullptr)) {
|
||||
dir_path_to_test_machine = strdup(tcpip_addr);
|
||||
} else if (unix_socket_en == false) {
|
||||
printf(
|
||||
"ERROR: Environment Variables Either COSIM_MACHINE_TCPIP_ADDRESS or COSIM_MACHINE_PATH is not specified.\n 1. Specify COSIM_MACHINE_PATH for Unix Socket Communication.\n 2. Specify COSIM_MACHINE_TCPIP_ADDRESS for TCP Socket Communication.\n");
|
||||
exit(0);
|
||||
}
|
||||
std::string skt_name;
|
||||
if (unix_socket_en) {
|
||||
skt_name.append("unix:");
|
||||
skt_name.append(dir_path_to_test_machine);
|
||||
skt_name.append("//qemu-rport-_cosim@0");
|
||||
} else {
|
||||
skt_name.append(dir_path_to_test_machine);
|
||||
}
|
||||
|
||||
const char* skt = skt_name.c_str();
|
||||
m_zynq_tlm_model = new xilinx_zynq("xilinx_zynq",skt);
|
||||
|
||||
//instantiating TLM2XTLM bridge and stiching it between
|
||||
//s_axi_gp[0] initiator socket of zynq Qemu tlm wrapper to M_AXI_GP0_wr_socket/rd_socket sockets
|
||||
m_rp_bridge_M_AXI_GP0.wr_socket->bind(*M_AXI_GP0_wr_socket);
|
||||
m_rp_bridge_M_AXI_GP0.rd_socket->bind(*M_AXI_GP0_rd_socket);
|
||||
m_rp_bridge_M_AXI_GP0.target_socket.bind(*m_zynq_tlm_model->m_axi_gp[0]);
|
||||
|
||||
m_zynq_tlm_model->tie_off();
|
||||
|
||||
SC_METHOD(trigger_FCLK_CLK0_pin);
|
||||
sensitive << FCLK_CLK0_clk;
|
||||
dont_initialize();
|
||||
m_rp_bridge_M_AXI_GP0.registerUserExtensionHandlerCallback(&get_extensions_from_tlm);
|
||||
m_zynq_tlm_model->rst(qemu_rst);
|
||||
}
|
||||
processing_system7_v5_5_tlm :: ~processing_system7_v5_5_tlm() {
|
||||
//deleteing dynamically created objects
|
||||
delete M_AXI_GP0_wr_socket;
|
||||
delete M_AXI_GP0_rd_socket;
|
||||
}
|
||||
|
||||
//Method which is sentive to FCLK_CLK0_clk sc_clock object
|
||||
//FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
|
||||
void processing_system7_v5_5_tlm ::trigger_FCLK_CLK0_pin() {
|
||||
FCLK_CLK0.write(FCLK_CLK0_clk.read());
|
||||
}
|
||||
//ps2pl_rst[0] output reset pin
|
||||
void processing_system7_v5_5_tlm :: FCLK_RESET0_N_trigger() {
|
||||
FCLK_RESET0_N.write(m_zynq_tlm_model->ps2pl_rst[0].read());
|
||||
}
|
||||
void processing_system7_v5_5_tlm ::start_of_simulation()
|
||||
{
|
||||
//temporary fix to drive the enabled reset pin
|
||||
FCLK_RESET0_N.write(true);
|
||||
qemu_rst.write(false);
|
||||
}
|
||||
+219
@@ -0,0 +1,219 @@
|
||||
|
||||
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
|
||||
// IP Revision: 1
|
||||
#ifndef __PS7_H__
|
||||
#define __PS7_H__
|
||||
|
||||
#include "systemc.h"
|
||||
#include "xtlm.h"
|
||||
#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
|
||||
#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
|
||||
#include "tlm_utils/simple_initiator_socket.h"
|
||||
#include "tlm_utils/simple_target_socket.h"
|
||||
#include "genattr.h"
|
||||
#include "xilinx-zynq.h"
|
||||
#include "b_transport_converter.h"
|
||||
#include "utils/xtlm_aximm_fifo.h"
|
||||
|
||||
/***************************************************************************************
|
||||
*
|
||||
* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
|
||||
* calls to xTLM sockets bn_transport_x() calls..
|
||||
*
|
||||
* This is Only specific to remote-port so not creating seperate header for it.
|
||||
*
|
||||
***************************************************************************************/
|
||||
template <int IN_WIDTH, int OUT_WIDTH>
|
||||
class rptlm2xtlm_converter : public sc_module{
|
||||
public:
|
||||
tlm::tlm_target_socket<IN_WIDTH> target_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket wr_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket rd_socket;
|
||||
rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
|
||||
void registerUserExtensionHandlerCallback(
|
||||
void (*callback)(xtlm::aximm_payload*,
|
||||
const tlm::tlm_generic_payload*));
|
||||
|
||||
private:
|
||||
b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
|
||||
xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
|
||||
};
|
||||
|
||||
/***************************************************************************************
|
||||
* Global method, get registered with tlm2xtlm bridge
|
||||
* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
|
||||
*
|
||||
* caller: tlm2xtlm bridge
|
||||
* purpose: To get master id and other parameters out of genattr_extension
|
||||
* and use master id to AxUSER PIN of xtlm payload.
|
||||
*
|
||||
*
|
||||
***************************************************************************************/
|
||||
extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
|
||||
|
||||
/***************************************************************************************
|
||||
* Global method, get registered with xtlm2tlm bridge
|
||||
* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
|
||||
*
|
||||
* caller: xtlm2tlm bridge
|
||||
* purpose: To create and add master id and other parameters to genattr_extension.
|
||||
* Master id red from AxID PIN of xtlm payload.
|
||||
*
|
||||
*
|
||||
***************************************************************************************/
|
||||
extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// //
|
||||
// File: processing_system7_tlm.h //
|
||||
// //
|
||||
// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
|
||||
// xilinx_zynq qemu wrapper and Vivado generated systemc simulation ip wrapper. //
|
||||
// it's basically created for supporting tlm based xilinx_zynq from xtlm based vivado //
|
||||
// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
|
||||
// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynq wrapper. //
|
||||
// it fill the the gap between input/output ports of vivado generated wrapper to //
|
||||
// xilinx_zynq wrapper signals. This wrapper is auto generated by ttcl scripts //
|
||||
// based on IP configuration in vivado. //
|
||||
// //
|
||||
// //
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
class processing_system7_v5_5_tlm : public sc_core::sc_module {
|
||||
|
||||
public:
|
||||
// Non-AXI ports are declared here
|
||||
sc_core::sc_in<sc_dt::sc_bv<33> > GPIO_I;
|
||||
sc_core::sc_out<sc_dt::sc_bv<33> > GPIO_O;
|
||||
sc_core::sc_out<sc_dt::sc_bv<33> > GPIO_T;
|
||||
sc_core::sc_in<bool> M_AXI_GP0_ACLK;
|
||||
sc_core::sc_out<bool> FCLK_CLK0;
|
||||
sc_core::sc_out<bool> FCLK_RESET0_N;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_inout<bool> DDR_CAS_n;
|
||||
sc_core::sc_inout<bool> DDR_CKE;
|
||||
sc_core::sc_inout<bool> DDR_Clk_n;
|
||||
sc_core::sc_inout<bool> DDR_Clk;
|
||||
sc_core::sc_inout<bool> DDR_CS_n;
|
||||
sc_core::sc_inout<bool> DDR_DRSTB;
|
||||
sc_core::sc_inout<bool> DDR_ODT;
|
||||
sc_core::sc_inout<bool> DDR_RAS_n;
|
||||
sc_core::sc_inout<bool> DDR_WEB;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_inout<bool> DDR_VRN;
|
||||
sc_core::sc_inout<bool> DDR_VRP;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_inout<bool> PS_SRSTB;
|
||||
sc_core::sc_inout<bool> PS_CLK;
|
||||
sc_core::sc_inout<bool> PS_PORB;
|
||||
|
||||
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
|
||||
|
||||
//constructor having three paramters
|
||||
// 1. module name in sc_module_name objec,
|
||||
// 2. reference to map object of name and integer value pairs
|
||||
// 3. reference to map object of name and string value pairs
|
||||
// All the model parameters (integer and string) which are configuration parameters
|
||||
// of Processing System 7 IP propogated from Vivado
|
||||
processing_system7_v5_5_tlm(sc_core::sc_module_name name,
|
||||
xsc::common_cpp::properties&);
|
||||
|
||||
~processing_system7_v5_5_tlm();
|
||||
SC_HAS_PROCESS(processing_system7_v5_5_tlm);
|
||||
|
||||
private:
|
||||
|
||||
//zynq tlm wrapper provided by Edgar
|
||||
//module with interfaces of standard tlm
|
||||
//and input/output ports at signal level
|
||||
xilinx_zynq* m_zynq_tlm_model;
|
||||
|
||||
// Xtlm2tlm_t Bridges
|
||||
// Converts Xtlm transactions to tlm transactions
|
||||
// Bridge's Xtlm wr/rd target sockets binds with
|
||||
// xtlm initiator sockets of processing_system7_tlm and tlm simple initiator
|
||||
// socket with xilinx_zynq's target socket
|
||||
|
||||
// This Bridges converts b_transport to nb_transports and also
|
||||
// Converts tlm transactions to xtlm transactions.
|
||||
// Bridge's tlm simple target socket binds with
|
||||
// simple initiator socket of xilinx_zynqmp and xtlm
|
||||
// socket with xilinx_zynq's simple target socket
|
||||
rptlm2xtlm_converter<32, 32> m_rp_bridge_M_AXI_GP0;
|
||||
|
||||
// sc_clocks for generating pl clocks
|
||||
// output pins FCLK_CLK0..3 are drived by these clocks
|
||||
sc_core::sc_clock FCLK_CLK0_clk;
|
||||
|
||||
|
||||
//Method which is sentive to FCLK_CLK0_clk sc_clock object
|
||||
//FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
|
||||
void trigger_FCLK_CLK0_pin();
|
||||
|
||||
//FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
|
||||
//EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
|
||||
void FCLK_RESET0_N_trigger();
|
||||
|
||||
sc_signal<bool> qemu_rst;
|
||||
void start_of_simulation();
|
||||
|
||||
xsc::common_cpp::properties prop;
|
||||
|
||||
};
|
||||
#endif
|
||||
+106
@@ -0,0 +1,106 @@
|
||||
/*
|
||||
* Xilinx SystemC/TLM-2.0 Zynq Wrapper.
|
||||
*
|
||||
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
|
||||
*
|
||||
* Copyright (c) 2016, Xilinx Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define SC_INCLUDE_DYNAMIC_PROCESSES
|
||||
|
||||
#include <inttypes.h>
|
||||
|
||||
#include "tlm_utils/simple_initiator_socket.h"
|
||||
#include "tlm_utils/simple_target_socket.h"
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace std;
|
||||
|
||||
#include "xilinx-zynq.h"
|
||||
#include <sys/types.h>
|
||||
|
||||
//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr,
|
||||
// Iremoteport_tlm_sync *sync)
|
||||
// : remoteport_tlm(name, -1, sk_descr, sync),
|
||||
xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr)
|
||||
: remoteport_tlm(name, -1, sk_descr),
|
||||
rp_m_axi_gp0("rp_m_axi_gp0"),
|
||||
rp_m_axi_gp1("rp_m_axi_gp1"),
|
||||
rp_s_axi_gp0("rp_s_axi_gp0"),
|
||||
rp_s_axi_gp1("rp_s_axi_gp1"),
|
||||
rp_s_axi_hp0("rp_s_axi_hp0"),
|
||||
rp_s_axi_hp1("rp_s_axi_hp1"),
|
||||
rp_s_axi_hp2("rp_s_axi_hp2"),
|
||||
rp_s_axi_hp3("rp_s_axi_hp3"),
|
||||
rp_s_axi_acp("rp_s_axi_acp"),
|
||||
rp_wires_in("wires_in", 20, 0),
|
||||
rp_wires_out("wires_out", 0, 17),
|
||||
rp_irq_out("irq_out", 0, 28),
|
||||
pl2ps_irq("pl2ps_irq", 20),
|
||||
ps2pl_irq("ps2pl_irq", 28),
|
||||
ps2pl_rst("ps2pl_rst", 17)
|
||||
{
|
||||
int i;
|
||||
|
||||
m_axi_gp[0] = &rp_m_axi_gp0.sk;
|
||||
m_axi_gp[1] = &rp_m_axi_gp1.sk;
|
||||
|
||||
s_axi_gp[0] = &rp_s_axi_gp0.sk;
|
||||
s_axi_gp[1] = &rp_s_axi_gp1.sk;
|
||||
|
||||
s_axi_hp[0] = &rp_s_axi_hp0.sk;
|
||||
s_axi_hp[1] = &rp_s_axi_hp1.sk;
|
||||
s_axi_hp[2] = &rp_s_axi_hp2.sk;
|
||||
s_axi_hp[3] = &rp_s_axi_hp3.sk;
|
||||
s_axi_acp = &rp_s_axi_acp.sk;
|
||||
|
||||
/* PL to PS Interrupt signals. */
|
||||
for (i = 0; i < 20; i++) {
|
||||
rp_wires_in.wires_in[i](pl2ps_irq[i]);
|
||||
}
|
||||
|
||||
/* PS to PL Interrupt signals. */
|
||||
for (i = 0; i < 28; i++) {
|
||||
rp_irq_out.wires_out[i](ps2pl_irq[i]);
|
||||
}
|
||||
|
||||
/* PS to PL resets. */
|
||||
for (i = 0; i < 17; i++) {
|
||||
rp_wires_out.wires_out[i](ps2pl_rst[i]);
|
||||
}
|
||||
|
||||
register_dev(0, &rp_s_axi_gp0);
|
||||
register_dev(1, &rp_s_axi_gp1);
|
||||
|
||||
register_dev(2, &rp_s_axi_hp0);
|
||||
register_dev(3, &rp_s_axi_hp1);
|
||||
register_dev(4, &rp_s_axi_hp2);
|
||||
register_dev(5, &rp_s_axi_hp3);
|
||||
|
||||
register_dev(6, &rp_s_axi_acp);
|
||||
|
||||
register_dev(7, &rp_m_axi_gp0);
|
||||
register_dev(8, &rp_m_axi_gp1);
|
||||
register_dev(9, &rp_wires_in);
|
||||
register_dev(10, &rp_wires_out);
|
||||
register_dev(11, &rp_irq_out);
|
||||
}
|
||||
+104
@@ -0,0 +1,104 @@
|
||||
/*
|
||||
* Xilinx SystemC/TLM-2.0 Zynq Wrapper.
|
||||
*
|
||||
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
|
||||
*
|
||||
* Copyright (c) 2016, Xilinx Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "systemc.h"
|
||||
|
||||
#include "tlm_utils/simple_initiator_socket.h"
|
||||
#include "tlm_utils/simple_target_socket.h"
|
||||
#include "tlm_utils/tlm_quantumkeeper.h"
|
||||
|
||||
#include "remote-port-tlm.h"
|
||||
#include "remote-port-tlm-memory-master.h"
|
||||
#include "remote-port-tlm-memory-slave.h"
|
||||
#include "remote-port-tlm-wires.h"
|
||||
|
||||
class xilinx_zynq
|
||||
: public remoteport_tlm
|
||||
{
|
||||
private:
|
||||
remoteport_tlm_memory_master rp_m_axi_gp0;
|
||||
remoteport_tlm_memory_master rp_m_axi_gp1;
|
||||
|
||||
remoteport_tlm_memory_slave rp_s_axi_gp0;
|
||||
remoteport_tlm_memory_slave rp_s_axi_gp1;
|
||||
|
||||
remoteport_tlm_memory_slave rp_s_axi_hp0;
|
||||
remoteport_tlm_memory_slave rp_s_axi_hp1;
|
||||
remoteport_tlm_memory_slave rp_s_axi_hp2;
|
||||
remoteport_tlm_memory_slave rp_s_axi_hp3;
|
||||
|
||||
remoteport_tlm_memory_slave rp_s_axi_acp;
|
||||
|
||||
remoteport_tlm_wires rp_wires_in;
|
||||
remoteport_tlm_wires rp_wires_out;
|
||||
remoteport_tlm_wires rp_irq_out;
|
||||
|
||||
public:
|
||||
/*
|
||||
* M_AXI_GP 0 - 1.
|
||||
* These sockets represent the High speed PS to PL interfaces.
|
||||
* These are AXI Slave ports on the PS side and AXI Master ports
|
||||
* on the PL side.
|
||||
*
|
||||
* Used to transfer data from the PS to the PL.
|
||||
*/
|
||||
tlm_utils::simple_initiator_socket<remoteport_tlm_memory_master> *m_axi_gp[2];
|
||||
|
||||
/*
|
||||
* S_AXI_GP0 - 1.
|
||||
* These sockets represent the High speed IO Coherent PL to PS
|
||||
* interfaces.
|
||||
*
|
||||
* HP0 - 3.
|
||||
* These sockets represent the High performance dataflow PL to PS interfaces.
|
||||
*
|
||||
* ACP
|
||||
* Accelerator Coherency Port, used to transfered coherent data to
|
||||
* the PS via the Cortex-A9 subsystem.
|
||||
*
|
||||
* These are AXI Master ports on the PS side and AXI Slave ports
|
||||
* on the PL side.
|
||||
*
|
||||
* Used to transfer data from the PL to the PS.
|
||||
*/
|
||||
tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_gp[2];
|
||||
tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_hp[4];
|
||||
tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_acp;
|
||||
|
||||
/* PL (fabric) to PS interrupt signals. */
|
||||
sc_vector<sc_signal<bool> > pl2ps_irq;
|
||||
|
||||
/* PS to PL Interrupt signals. */
|
||||
sc_vector<sc_signal<bool> > ps2pl_irq;
|
||||
|
||||
/* FPGA out resets. */
|
||||
sc_vector<sc_signal<bool> > ps2pl_rst;
|
||||
|
||||
xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr);
|
||||
//xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr,
|
||||
// Iremoteport_tlm_sync *sync = NULL);
|
||||
};
|
||||
+997
@@ -0,0 +1,997 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:processing_system7:5.5
|
||||
// IP Revision: 6
|
||||
|
||||
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2023.2" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
|
||||
(* CORE_GENERATION_INFO = "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2023.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=33,C_INCLUDE_ACP_TRANS_CHEC\
|
||||
K=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M\
|
||||
_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_GP1=0,C_USE_S_AXI_HP0=0,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=TRUE,C_FCLK_CLK1_BUF=FALSE,C_FCLK_CLK2_BUF=FALSE,C_FCLK_CLK3_BUF=FALSE,C_PACKAGE_NAME=ffg676,C_GP0_EN_MODIFIABLE_TXN=\
|
||||
1,C_GP1_EN_MODIFIABLE_TXN=1}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_processing_system7_0_0 (
|
||||
GPIO_I,
|
||||
GPIO_O,
|
||||
GPIO_T,
|
||||
M_AXI_GP0_ARVALID,
|
||||
M_AXI_GP0_AWVALID,
|
||||
M_AXI_GP0_BREADY,
|
||||
M_AXI_GP0_RREADY,
|
||||
M_AXI_GP0_WLAST,
|
||||
M_AXI_GP0_WVALID,
|
||||
M_AXI_GP0_ARID,
|
||||
M_AXI_GP0_AWID,
|
||||
M_AXI_GP0_WID,
|
||||
M_AXI_GP0_ARBURST,
|
||||
M_AXI_GP0_ARLOCK,
|
||||
M_AXI_GP0_ARSIZE,
|
||||
M_AXI_GP0_AWBURST,
|
||||
M_AXI_GP0_AWLOCK,
|
||||
M_AXI_GP0_AWSIZE,
|
||||
M_AXI_GP0_ARPROT,
|
||||
M_AXI_GP0_AWPROT,
|
||||
M_AXI_GP0_ARADDR,
|
||||
M_AXI_GP0_AWADDR,
|
||||
M_AXI_GP0_WDATA,
|
||||
M_AXI_GP0_ARCACHE,
|
||||
M_AXI_GP0_ARLEN,
|
||||
M_AXI_GP0_ARQOS,
|
||||
M_AXI_GP0_AWCACHE,
|
||||
M_AXI_GP0_AWLEN,
|
||||
M_AXI_GP0_AWQOS,
|
||||
M_AXI_GP0_WSTRB,
|
||||
M_AXI_GP0_ACLK,
|
||||
M_AXI_GP0_ARREADY,
|
||||
M_AXI_GP0_AWREADY,
|
||||
M_AXI_GP0_BVALID,
|
||||
M_AXI_GP0_RLAST,
|
||||
M_AXI_GP0_RVALID,
|
||||
M_AXI_GP0_WREADY,
|
||||
M_AXI_GP0_BID,
|
||||
M_AXI_GP0_RID,
|
||||
M_AXI_GP0_BRESP,
|
||||
M_AXI_GP0_RRESP,
|
||||
M_AXI_GP0_RDATA,
|
||||
FCLK_CLK0,
|
||||
FCLK_RESET0_N,
|
||||
MIO,
|
||||
DDR_CAS_n,
|
||||
DDR_CKE,
|
||||
DDR_Clk_n,
|
||||
DDR_Clk,
|
||||
DDR_CS_n,
|
||||
DDR_DRSTB,
|
||||
DDR_ODT,
|
||||
DDR_RAS_n,
|
||||
DDR_WEB,
|
||||
DDR_BankAddr,
|
||||
DDR_Addr,
|
||||
DDR_VRN,
|
||||
DDR_VRP,
|
||||
DDR_DM,
|
||||
DDR_DQ,
|
||||
DDR_DQS_n,
|
||||
DDR_DQS,
|
||||
PS_SRSTB,
|
||||
PS_CLK,
|
||||
PS_PORB
|
||||
);
|
||||
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_I" *)
|
||||
input wire [32 : 0] GPIO_I;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_O" *)
|
||||
output wire [32 : 0] GPIO_O;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_T" *)
|
||||
output wire [32 : 0] GPIO_T;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
|
||||
output wire M_AXI_GP0_ARVALID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
|
||||
output wire M_AXI_GP0_AWVALID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
|
||||
output wire M_AXI_GP0_BREADY;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
|
||||
output wire M_AXI_GP0_RREADY;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
|
||||
output wire M_AXI_GP0_WLAST;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
|
||||
output wire M_AXI_GP0_WVALID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
|
||||
output wire [11 : 0] M_AXI_GP0_ARID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
|
||||
output wire [11 : 0] M_AXI_GP0_AWID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
|
||||
output wire [11 : 0] M_AXI_GP0_WID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
|
||||
output wire [1 : 0] M_AXI_GP0_ARBURST;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
|
||||
output wire [1 : 0] M_AXI_GP0_ARLOCK;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
|
||||
output wire [2 : 0] M_AXI_GP0_ARSIZE;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
|
||||
output wire [1 : 0] M_AXI_GP0_AWBURST;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
|
||||
output wire [1 : 0] M_AXI_GP0_AWLOCK;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
|
||||
output wire [2 : 0] M_AXI_GP0_AWSIZE;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
|
||||
output wire [2 : 0] M_AXI_GP0_ARPROT;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
|
||||
output wire [2 : 0] M_AXI_GP0_AWPROT;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
|
||||
output wire [31 : 0] M_AXI_GP0_ARADDR;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
|
||||
output wire [31 : 0] M_AXI_GP0_AWADDR;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
|
||||
output wire [31 : 0] M_AXI_GP0_WDATA;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
|
||||
output wire [3 : 0] M_AXI_GP0_ARCACHE;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
|
||||
output wire [3 : 0] M_AXI_GP0_ARLEN;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
|
||||
output wire [3 : 0] M_AXI_GP0_ARQOS;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
|
||||
output wire [3 : 0] M_AXI_GP0_AWCACHE;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
|
||||
output wire [3 : 0] M_AXI_GP0_AWLEN;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
|
||||
output wire [3 : 0] M_AXI_GP0_AWQOS;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
|
||||
output wire [3 : 0] M_AXI_GP0_WSTRB;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
|
||||
input wire M_AXI_GP0_ACLK;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
|
||||
input wire M_AXI_GP0_ARREADY;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
|
||||
input wire M_AXI_GP0_AWREADY;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
|
||||
input wire M_AXI_GP0_BVALID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
|
||||
input wire M_AXI_GP0_RLAST;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
|
||||
input wire M_AXI_GP0_RVALID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
|
||||
input wire M_AXI_GP0_WREADY;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
|
||||
input wire [11 : 0] M_AXI_GP0_BID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
|
||||
input wire [11 : 0] M_AXI_GP0_RID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
|
||||
input wire [1 : 0] M_AXI_GP0_BRESP;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
|
||||
input wire [1 : 0] M_AXI_GP0_RRESP;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
|
||||
S 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
|
||||
input wire [31 : 0] M_AXI_GP0_RDATA;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
|
||||
output wire FCLK_CLK0;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
|
||||
output wire FCLK_RESET0_N;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
|
||||
inout wire [53 : 0] MIO;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
|
||||
inout wire DDR_CAS_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
|
||||
inout wire DDR_CKE;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
|
||||
inout wire DDR_Clk_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
|
||||
inout wire DDR_Clk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
|
||||
inout wire DDR_CS_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
|
||||
inout wire DDR_DRSTB;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
|
||||
inout wire DDR_ODT;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
|
||||
inout wire DDR_RAS_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
|
||||
inout wire DDR_WEB;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
|
||||
inout wire [2 : 0] DDR_BankAddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
|
||||
inout wire [14 : 0] DDR_Addr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
|
||||
inout wire DDR_VRN;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
|
||||
inout wire DDR_VRP;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
|
||||
inout wire [3 : 0] DDR_DM;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
|
||||
inout wire [31 : 0] DDR_DQ;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
|
||||
inout wire [3 : 0] DDR_DQS_n;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
|
||||
inout wire [3 : 0] DDR_DQS;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
|
||||
inout wire PS_SRSTB;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
|
||||
inout wire PS_CLK;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
|
||||
inout wire PS_PORB;
|
||||
|
||||
processing_system7_v5_5_processing_system7 #(
|
||||
.C_EN_EMIO_PJTAG(0),
|
||||
.C_EN_EMIO_ENET0(0),
|
||||
.C_EN_EMIO_ENET1(0),
|
||||
.C_EN_EMIO_TRACE(0),
|
||||
.C_INCLUDE_TRACE_BUFFER(0),
|
||||
.C_TRACE_BUFFER_FIFO_SIZE(128),
|
||||
.USE_TRACE_DATA_EDGE_DETECTOR(0),
|
||||
.C_TRACE_PIPELINE_WIDTH(8),
|
||||
.C_TRACE_BUFFER_CLOCK_DELAY(12),
|
||||
.C_EMIO_GPIO_WIDTH(33),
|
||||
.C_INCLUDE_ACP_TRANS_CHECK(0),
|
||||
.C_USE_DEFAULT_ACP_USER_VAL(0),
|
||||
.C_S_AXI_ACP_ARUSER_VAL(31),
|
||||
.C_S_AXI_ACP_AWUSER_VAL(31),
|
||||
.C_M_AXI_GP0_ID_WIDTH(12),
|
||||
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
|
||||
.C_M_AXI_GP1_ID_WIDTH(12),
|
||||
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
|
||||
.C_S_AXI_GP0_ID_WIDTH(6),
|
||||
.C_S_AXI_GP1_ID_WIDTH(6),
|
||||
.C_S_AXI_ACP_ID_WIDTH(3),
|
||||
.C_S_AXI_HP0_ID_WIDTH(6),
|
||||
.C_S_AXI_HP0_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP1_ID_WIDTH(6),
|
||||
.C_S_AXI_HP1_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP2_ID_WIDTH(6),
|
||||
.C_S_AXI_HP2_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP3_ID_WIDTH(6),
|
||||
.C_S_AXI_HP3_DATA_WIDTH(64),
|
||||
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
|
||||
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
|
||||
.C_NUM_F2P_INTR_INPUTS(1),
|
||||
.C_IRQ_F2P_MODE("DIRECT"),
|
||||
.C_DQ_WIDTH(32),
|
||||
.C_DQS_WIDTH(4),
|
||||
.C_DM_WIDTH(4),
|
||||
.C_MIO_PRIMITIVE(54),
|
||||
.C_TRACE_INTERNAL_WIDTH(2),
|
||||
.C_USE_AXI_NONSECURE(0),
|
||||
.C_USE_M_AXI_GP0(1),
|
||||
.C_USE_M_AXI_GP1(0),
|
||||
.C_USE_S_AXI_GP0(0),
|
||||
.C_USE_S_AXI_GP1(0),
|
||||
.C_USE_S_AXI_HP0(0),
|
||||
.C_USE_S_AXI_HP1(0),
|
||||
.C_USE_S_AXI_HP2(0),
|
||||
.C_USE_S_AXI_HP3(0),
|
||||
.C_USE_S_AXI_ACP(0),
|
||||
.C_PS7_SI_REV("PRODUCTION"),
|
||||
.C_FCLK_CLK0_BUF("TRUE"),
|
||||
.C_FCLK_CLK1_BUF("FALSE"),
|
||||
.C_FCLK_CLK2_BUF("FALSE"),
|
||||
.C_FCLK_CLK3_BUF("FALSE"),
|
||||
.C_PACKAGE_NAME("ffg676"),
|
||||
.C_GP0_EN_MODIFIABLE_TXN(1),
|
||||
.C_GP1_EN_MODIFIABLE_TXN(1)
|
||||
) inst (
|
||||
.CAN0_PHY_TX(),
|
||||
.CAN0_PHY_RX(1'B0),
|
||||
.CAN1_PHY_TX(),
|
||||
.CAN1_PHY_RX(1'B0),
|
||||
.ENET0_GMII_TX_EN(),
|
||||
.ENET0_GMII_TX_ER(),
|
||||
.ENET0_MDIO_MDC(),
|
||||
.ENET0_MDIO_O(),
|
||||
.ENET0_MDIO_T(),
|
||||
.ENET0_PTP_DELAY_REQ_RX(),
|
||||
.ENET0_PTP_DELAY_REQ_TX(),
|
||||
.ENET0_PTP_PDELAY_REQ_RX(),
|
||||
.ENET0_PTP_PDELAY_REQ_TX(),
|
||||
.ENET0_PTP_PDELAY_RESP_RX(),
|
||||
.ENET0_PTP_PDELAY_RESP_TX(),
|
||||
.ENET0_PTP_SYNC_FRAME_RX(),
|
||||
.ENET0_PTP_SYNC_FRAME_TX(),
|
||||
.ENET0_SOF_RX(),
|
||||
.ENET0_SOF_TX(),
|
||||
.ENET0_GMII_TXD(),
|
||||
.ENET0_GMII_COL(1'B0),
|
||||
.ENET0_GMII_CRS(1'B0),
|
||||
.ENET0_GMII_RX_CLK(1'B0),
|
||||
.ENET0_GMII_RX_DV(1'B0),
|
||||
.ENET0_GMII_RX_ER(1'B0),
|
||||
.ENET0_GMII_TX_CLK(1'B0),
|
||||
.ENET0_MDIO_I(1'B0),
|
||||
.ENET0_EXT_INTIN(1'B0),
|
||||
.ENET0_GMII_RXD(8'B0),
|
||||
.ENET1_GMII_TX_EN(),
|
||||
.ENET1_GMII_TX_ER(),
|
||||
.ENET1_MDIO_MDC(),
|
||||
.ENET1_MDIO_O(),
|
||||
.ENET1_MDIO_T(),
|
||||
.ENET1_PTP_DELAY_REQ_RX(),
|
||||
.ENET1_PTP_DELAY_REQ_TX(),
|
||||
.ENET1_PTP_PDELAY_REQ_RX(),
|
||||
.ENET1_PTP_PDELAY_REQ_TX(),
|
||||
.ENET1_PTP_PDELAY_RESP_RX(),
|
||||
.ENET1_PTP_PDELAY_RESP_TX(),
|
||||
.ENET1_PTP_SYNC_FRAME_RX(),
|
||||
.ENET1_PTP_SYNC_FRAME_TX(),
|
||||
.ENET1_SOF_RX(),
|
||||
.ENET1_SOF_TX(),
|
||||
.ENET1_GMII_TXD(),
|
||||
.ENET1_GMII_COL(1'B0),
|
||||
.ENET1_GMII_CRS(1'B0),
|
||||
.ENET1_GMII_RX_CLK(1'B0),
|
||||
.ENET1_GMII_RX_DV(1'B0),
|
||||
.ENET1_GMII_RX_ER(1'B0),
|
||||
.ENET1_GMII_TX_CLK(1'B0),
|
||||
.ENET1_MDIO_I(1'B0),
|
||||
.ENET1_EXT_INTIN(1'B0),
|
||||
.ENET1_GMII_RXD(8'B0),
|
||||
.GPIO_I(GPIO_I),
|
||||
.GPIO_O(GPIO_O),
|
||||
.GPIO_T(GPIO_T),
|
||||
.I2C0_SDA_I(1'B0),
|
||||
.I2C0_SDA_O(),
|
||||
.I2C0_SDA_T(),
|
||||
.I2C0_SCL_I(1'B0),
|
||||
.I2C0_SCL_O(),
|
||||
.I2C0_SCL_T(),
|
||||
.I2C1_SDA_I(1'B0),
|
||||
.I2C1_SDA_O(),
|
||||
.I2C1_SDA_T(),
|
||||
.I2C1_SCL_I(1'B0),
|
||||
.I2C1_SCL_O(),
|
||||
.I2C1_SCL_T(),
|
||||
.PJTAG_TCK(1'B0),
|
||||
.PJTAG_TMS(1'B0),
|
||||
.PJTAG_TDI(1'B0),
|
||||
.PJTAG_TDO(),
|
||||
.SDIO0_CLK(),
|
||||
.SDIO0_CLK_FB(1'B0),
|
||||
.SDIO0_CMD_O(),
|
||||
.SDIO0_CMD_I(1'B0),
|
||||
.SDIO0_CMD_T(),
|
||||
.SDIO0_DATA_I(4'B0),
|
||||
.SDIO0_DATA_O(),
|
||||
.SDIO0_DATA_T(),
|
||||
.SDIO0_LED(),
|
||||
.SDIO0_CDN(1'B0),
|
||||
.SDIO0_WP(1'B0),
|
||||
.SDIO0_BUSPOW(),
|
||||
.SDIO0_BUSVOLT(),
|
||||
.SDIO1_CLK(),
|
||||
.SDIO1_CLK_FB(1'B0),
|
||||
.SDIO1_CMD_O(),
|
||||
.SDIO1_CMD_I(1'B0),
|
||||
.SDIO1_CMD_T(),
|
||||
.SDIO1_DATA_I(4'B0),
|
||||
.SDIO1_DATA_O(),
|
||||
.SDIO1_DATA_T(),
|
||||
.SDIO1_LED(),
|
||||
.SDIO1_CDN(1'B0),
|
||||
.SDIO1_WP(1'B0),
|
||||
.SDIO1_BUSPOW(),
|
||||
.SDIO1_BUSVOLT(),
|
||||
.SPI0_SCLK_I(1'B0),
|
||||
.SPI0_SCLK_O(),
|
||||
.SPI0_SCLK_T(),
|
||||
.SPI0_MOSI_I(1'B0),
|
||||
.SPI0_MOSI_O(),
|
||||
.SPI0_MOSI_T(),
|
||||
.SPI0_MISO_I(1'B0),
|
||||
.SPI0_MISO_O(),
|
||||
.SPI0_MISO_T(),
|
||||
.SPI0_SS_I(1'B0),
|
||||
.SPI0_SS_O(),
|
||||
.SPI0_SS1_O(),
|
||||
.SPI0_SS2_O(),
|
||||
.SPI0_SS_T(),
|
||||
.SPI1_SCLK_I(1'B0),
|
||||
.SPI1_SCLK_O(),
|
||||
.SPI1_SCLK_T(),
|
||||
.SPI1_MOSI_I(1'B0),
|
||||
.SPI1_MOSI_O(),
|
||||
.SPI1_MOSI_T(),
|
||||
.SPI1_MISO_I(1'B0),
|
||||
.SPI1_MISO_O(),
|
||||
.SPI1_MISO_T(),
|
||||
.SPI1_SS_I(1'B0),
|
||||
.SPI1_SS_O(),
|
||||
.SPI1_SS1_O(),
|
||||
.SPI1_SS2_O(),
|
||||
.SPI1_SS_T(),
|
||||
.UART0_DTRN(),
|
||||
.UART0_RTSN(),
|
||||
.UART0_TX(),
|
||||
.UART0_CTSN(1'B0),
|
||||
.UART0_DCDN(1'B0),
|
||||
.UART0_DSRN(1'B0),
|
||||
.UART0_RIN(1'B0),
|
||||
.UART0_RX(1'B1),
|
||||
.UART1_DTRN(),
|
||||
.UART1_RTSN(),
|
||||
.UART1_TX(),
|
||||
.UART1_CTSN(1'B0),
|
||||
.UART1_DCDN(1'B0),
|
||||
.UART1_DSRN(1'B0),
|
||||
.UART1_RIN(1'B0),
|
||||
.UART1_RX(1'B1),
|
||||
.TTC0_WAVE0_OUT(),
|
||||
.TTC0_WAVE1_OUT(),
|
||||
.TTC0_WAVE2_OUT(),
|
||||
.TTC0_CLK0_IN(1'B0),
|
||||
.TTC0_CLK1_IN(1'B0),
|
||||
.TTC0_CLK2_IN(1'B0),
|
||||
.TTC1_WAVE0_OUT(),
|
||||
.TTC1_WAVE1_OUT(),
|
||||
.TTC1_WAVE2_OUT(),
|
||||
.TTC1_CLK0_IN(1'B0),
|
||||
.TTC1_CLK1_IN(1'B0),
|
||||
.TTC1_CLK2_IN(1'B0),
|
||||
.WDT_CLK_IN(1'B0),
|
||||
.WDT_RST_OUT(),
|
||||
.TRACE_CLK(1'B0),
|
||||
.TRACE_CLK_OUT(),
|
||||
.TRACE_CTL(),
|
||||
.TRACE_DATA(),
|
||||
.USB0_PORT_INDCTL(),
|
||||
.USB0_VBUS_PWRSELECT(),
|
||||
.USB0_VBUS_PWRFAULT(1'B0),
|
||||
.USB1_PORT_INDCTL(),
|
||||
.USB1_VBUS_PWRSELECT(),
|
||||
.USB1_VBUS_PWRFAULT(1'B0),
|
||||
.SRAM_INTIN(1'B0),
|
||||
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
|
||||
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
|
||||
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
|
||||
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
|
||||
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
|
||||
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
|
||||
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
|
||||
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
|
||||
.M_AXI_GP0_WID(M_AXI_GP0_WID),
|
||||
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
|
||||
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
|
||||
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
|
||||
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
|
||||
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
|
||||
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
|
||||
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
|
||||
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
|
||||
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
|
||||
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
|
||||
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
|
||||
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
|
||||
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
|
||||
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
|
||||
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
|
||||
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
|
||||
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
|
||||
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
|
||||
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
|
||||
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
|
||||
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
|
||||
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
|
||||
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
|
||||
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
|
||||
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
|
||||
.M_AXI_GP0_BID(M_AXI_GP0_BID),
|
||||
.M_AXI_GP0_RID(M_AXI_GP0_RID),
|
||||
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
|
||||
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
|
||||
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
|
||||
.M_AXI_GP1_ARVALID(),
|
||||
.M_AXI_GP1_AWVALID(),
|
||||
.M_AXI_GP1_BREADY(),
|
||||
.M_AXI_GP1_RREADY(),
|
||||
.M_AXI_GP1_WLAST(),
|
||||
.M_AXI_GP1_WVALID(),
|
||||
.M_AXI_GP1_ARID(),
|
||||
.M_AXI_GP1_AWID(),
|
||||
.M_AXI_GP1_WID(),
|
||||
.M_AXI_GP1_ARBURST(),
|
||||
.M_AXI_GP1_ARLOCK(),
|
||||
.M_AXI_GP1_ARSIZE(),
|
||||
.M_AXI_GP1_AWBURST(),
|
||||
.M_AXI_GP1_AWLOCK(),
|
||||
.M_AXI_GP1_AWSIZE(),
|
||||
.M_AXI_GP1_ARPROT(),
|
||||
.M_AXI_GP1_AWPROT(),
|
||||
.M_AXI_GP1_ARADDR(),
|
||||
.M_AXI_GP1_AWADDR(),
|
||||
.M_AXI_GP1_WDATA(),
|
||||
.M_AXI_GP1_ARCACHE(),
|
||||
.M_AXI_GP1_ARLEN(),
|
||||
.M_AXI_GP1_ARQOS(),
|
||||
.M_AXI_GP1_AWCACHE(),
|
||||
.M_AXI_GP1_AWLEN(),
|
||||
.M_AXI_GP1_AWQOS(),
|
||||
.M_AXI_GP1_WSTRB(),
|
||||
.M_AXI_GP1_ACLK(1'B0),
|
||||
.M_AXI_GP1_ARREADY(1'B0),
|
||||
.M_AXI_GP1_AWREADY(1'B0),
|
||||
.M_AXI_GP1_BVALID(1'B0),
|
||||
.M_AXI_GP1_RLAST(1'B0),
|
||||
.M_AXI_GP1_RVALID(1'B0),
|
||||
.M_AXI_GP1_WREADY(1'B0),
|
||||
.M_AXI_GP1_BID(12'B0),
|
||||
.M_AXI_GP1_RID(12'B0),
|
||||
.M_AXI_GP1_BRESP(2'B0),
|
||||
.M_AXI_GP1_RRESP(2'B0),
|
||||
.M_AXI_GP1_RDATA(32'B0),
|
||||
.S_AXI_GP0_ARREADY(),
|
||||
.S_AXI_GP0_AWREADY(),
|
||||
.S_AXI_GP0_BVALID(),
|
||||
.S_AXI_GP0_RLAST(),
|
||||
.S_AXI_GP0_RVALID(),
|
||||
.S_AXI_GP0_WREADY(),
|
||||
.S_AXI_GP0_BRESP(),
|
||||
.S_AXI_GP0_RRESP(),
|
||||
.S_AXI_GP0_RDATA(),
|
||||
.S_AXI_GP0_BID(),
|
||||
.S_AXI_GP0_RID(),
|
||||
.S_AXI_GP0_ACLK(1'B0),
|
||||
.S_AXI_GP0_ARVALID(1'B0),
|
||||
.S_AXI_GP0_AWVALID(1'B0),
|
||||
.S_AXI_GP0_BREADY(1'B0),
|
||||
.S_AXI_GP0_RREADY(1'B0),
|
||||
.S_AXI_GP0_WLAST(1'B0),
|
||||
.S_AXI_GP0_WVALID(1'B0),
|
||||
.S_AXI_GP0_ARBURST(2'B0),
|
||||
.S_AXI_GP0_ARLOCK(2'B0),
|
||||
.S_AXI_GP0_ARSIZE(3'B0),
|
||||
.S_AXI_GP0_AWBURST(2'B0),
|
||||
.S_AXI_GP0_AWLOCK(2'B0),
|
||||
.S_AXI_GP0_AWSIZE(3'B0),
|
||||
.S_AXI_GP0_ARPROT(3'B0),
|
||||
.S_AXI_GP0_AWPROT(3'B0),
|
||||
.S_AXI_GP0_ARADDR(32'B0),
|
||||
.S_AXI_GP0_AWADDR(32'B0),
|
||||
.S_AXI_GP0_WDATA(32'B0),
|
||||
.S_AXI_GP0_ARCACHE(4'B0),
|
||||
.S_AXI_GP0_ARLEN(4'B0),
|
||||
.S_AXI_GP0_ARQOS(4'B0),
|
||||
.S_AXI_GP0_AWCACHE(4'B0),
|
||||
.S_AXI_GP0_AWLEN(4'B0),
|
||||
.S_AXI_GP0_AWQOS(4'B0),
|
||||
.S_AXI_GP0_WSTRB(4'B0),
|
||||
.S_AXI_GP0_ARID(6'B0),
|
||||
.S_AXI_GP0_AWID(6'B0),
|
||||
.S_AXI_GP0_WID(6'B0),
|
||||
.S_AXI_GP1_ARREADY(),
|
||||
.S_AXI_GP1_AWREADY(),
|
||||
.S_AXI_GP1_BVALID(),
|
||||
.S_AXI_GP1_RLAST(),
|
||||
.S_AXI_GP1_RVALID(),
|
||||
.S_AXI_GP1_WREADY(),
|
||||
.S_AXI_GP1_BRESP(),
|
||||
.S_AXI_GP1_RRESP(),
|
||||
.S_AXI_GP1_RDATA(),
|
||||
.S_AXI_GP1_BID(),
|
||||
.S_AXI_GP1_RID(),
|
||||
.S_AXI_GP1_ACLK(1'B0),
|
||||
.S_AXI_GP1_ARVALID(1'B0),
|
||||
.S_AXI_GP1_AWVALID(1'B0),
|
||||
.S_AXI_GP1_BREADY(1'B0),
|
||||
.S_AXI_GP1_RREADY(1'B0),
|
||||
.S_AXI_GP1_WLAST(1'B0),
|
||||
.S_AXI_GP1_WVALID(1'B0),
|
||||
.S_AXI_GP1_ARBURST(2'B0),
|
||||
.S_AXI_GP1_ARLOCK(2'B0),
|
||||
.S_AXI_GP1_ARSIZE(3'B0),
|
||||
.S_AXI_GP1_AWBURST(2'B0),
|
||||
.S_AXI_GP1_AWLOCK(2'B0),
|
||||
.S_AXI_GP1_AWSIZE(3'B0),
|
||||
.S_AXI_GP1_ARPROT(3'B0),
|
||||
.S_AXI_GP1_AWPROT(3'B0),
|
||||
.S_AXI_GP1_ARADDR(32'B0),
|
||||
.S_AXI_GP1_AWADDR(32'B0),
|
||||
.S_AXI_GP1_WDATA(32'B0),
|
||||
.S_AXI_GP1_ARCACHE(4'B0),
|
||||
.S_AXI_GP1_ARLEN(4'B0),
|
||||
.S_AXI_GP1_ARQOS(4'B0),
|
||||
.S_AXI_GP1_AWCACHE(4'B0),
|
||||
.S_AXI_GP1_AWLEN(4'B0),
|
||||
.S_AXI_GP1_AWQOS(4'B0),
|
||||
.S_AXI_GP1_WSTRB(4'B0),
|
||||
.S_AXI_GP1_ARID(6'B0),
|
||||
.S_AXI_GP1_AWID(6'B0),
|
||||
.S_AXI_GP1_WID(6'B0),
|
||||
.S_AXI_ACP_ARREADY(),
|
||||
.S_AXI_ACP_AWREADY(),
|
||||
.S_AXI_ACP_BVALID(),
|
||||
.S_AXI_ACP_RLAST(),
|
||||
.S_AXI_ACP_RVALID(),
|
||||
.S_AXI_ACP_WREADY(),
|
||||
.S_AXI_ACP_BRESP(),
|
||||
.S_AXI_ACP_RRESP(),
|
||||
.S_AXI_ACP_BID(),
|
||||
.S_AXI_ACP_RID(),
|
||||
.S_AXI_ACP_RDATA(),
|
||||
.S_AXI_ACP_ACLK(1'B0),
|
||||
.S_AXI_ACP_ARVALID(1'B0),
|
||||
.S_AXI_ACP_AWVALID(1'B0),
|
||||
.S_AXI_ACP_BREADY(1'B0),
|
||||
.S_AXI_ACP_RREADY(1'B0),
|
||||
.S_AXI_ACP_WLAST(1'B0),
|
||||
.S_AXI_ACP_WVALID(1'B0),
|
||||
.S_AXI_ACP_ARID(3'B0),
|
||||
.S_AXI_ACP_ARPROT(3'B0),
|
||||
.S_AXI_ACP_AWID(3'B0),
|
||||
.S_AXI_ACP_AWPROT(3'B0),
|
||||
.S_AXI_ACP_WID(3'B0),
|
||||
.S_AXI_ACP_ARADDR(32'B0),
|
||||
.S_AXI_ACP_AWADDR(32'B0),
|
||||
.S_AXI_ACP_ARCACHE(4'B0),
|
||||
.S_AXI_ACP_ARLEN(4'B0),
|
||||
.S_AXI_ACP_ARQOS(4'B0),
|
||||
.S_AXI_ACP_AWCACHE(4'B0),
|
||||
.S_AXI_ACP_AWLEN(4'B0),
|
||||
.S_AXI_ACP_AWQOS(4'B0),
|
||||
.S_AXI_ACP_ARBURST(2'B0),
|
||||
.S_AXI_ACP_ARLOCK(2'B0),
|
||||
.S_AXI_ACP_ARSIZE(3'B0),
|
||||
.S_AXI_ACP_AWBURST(2'B0),
|
||||
.S_AXI_ACP_AWLOCK(2'B0),
|
||||
.S_AXI_ACP_AWSIZE(3'B0),
|
||||
.S_AXI_ACP_ARUSER(5'B0),
|
||||
.S_AXI_ACP_AWUSER(5'B0),
|
||||
.S_AXI_ACP_WDATA(64'B0),
|
||||
.S_AXI_ACP_WSTRB(8'B0),
|
||||
.S_AXI_HP0_ARREADY(),
|
||||
.S_AXI_HP0_AWREADY(),
|
||||
.S_AXI_HP0_BVALID(),
|
||||
.S_AXI_HP0_RLAST(),
|
||||
.S_AXI_HP0_RVALID(),
|
||||
.S_AXI_HP0_WREADY(),
|
||||
.S_AXI_HP0_BRESP(),
|
||||
.S_AXI_HP0_RRESP(),
|
||||
.S_AXI_HP0_BID(),
|
||||
.S_AXI_HP0_RID(),
|
||||
.S_AXI_HP0_RDATA(),
|
||||
.S_AXI_HP0_RCOUNT(),
|
||||
.S_AXI_HP0_WCOUNT(),
|
||||
.S_AXI_HP0_RACOUNT(),
|
||||
.S_AXI_HP0_WACOUNT(),
|
||||
.S_AXI_HP0_ACLK(1'B0),
|
||||
.S_AXI_HP0_ARVALID(1'B0),
|
||||
.S_AXI_HP0_AWVALID(1'B0),
|
||||
.S_AXI_HP0_BREADY(1'B0),
|
||||
.S_AXI_HP0_RDISSUECAP1_EN(1'B0),
|
||||
.S_AXI_HP0_RREADY(1'B0),
|
||||
.S_AXI_HP0_WLAST(1'B0),
|
||||
.S_AXI_HP0_WRISSUECAP1_EN(1'B0),
|
||||
.S_AXI_HP0_WVALID(1'B0),
|
||||
.S_AXI_HP0_ARBURST(2'B0),
|
||||
.S_AXI_HP0_ARLOCK(2'B0),
|
||||
.S_AXI_HP0_ARSIZE(3'B0),
|
||||
.S_AXI_HP0_AWBURST(2'B0),
|
||||
.S_AXI_HP0_AWLOCK(2'B0),
|
||||
.S_AXI_HP0_AWSIZE(3'B0),
|
||||
.S_AXI_HP0_ARPROT(3'B0),
|
||||
.S_AXI_HP0_AWPROT(3'B0),
|
||||
.S_AXI_HP0_ARADDR(32'B0),
|
||||
.S_AXI_HP0_AWADDR(32'B0),
|
||||
.S_AXI_HP0_ARCACHE(4'B0),
|
||||
.S_AXI_HP0_ARLEN(4'B0),
|
||||
.S_AXI_HP0_ARQOS(4'B0),
|
||||
.S_AXI_HP0_AWCACHE(4'B0),
|
||||
.S_AXI_HP0_AWLEN(4'B0),
|
||||
.S_AXI_HP0_AWQOS(4'B0),
|
||||
.S_AXI_HP0_ARID(6'B0),
|
||||
.S_AXI_HP0_AWID(6'B0),
|
||||
.S_AXI_HP0_WID(6'B0),
|
||||
.S_AXI_HP0_WDATA(64'B0),
|
||||
.S_AXI_HP0_WSTRB(8'B0),
|
||||
.S_AXI_HP1_ARREADY(),
|
||||
.S_AXI_HP1_AWREADY(),
|
||||
.S_AXI_HP1_BVALID(),
|
||||
.S_AXI_HP1_RLAST(),
|
||||
.S_AXI_HP1_RVALID(),
|
||||
.S_AXI_HP1_WREADY(),
|
||||
.S_AXI_HP1_BRESP(),
|
||||
.S_AXI_HP1_RRESP(),
|
||||
.S_AXI_HP1_BID(),
|
||||
.S_AXI_HP1_RID(),
|
||||
.S_AXI_HP1_RDATA(),
|
||||
.S_AXI_HP1_RCOUNT(),
|
||||
.S_AXI_HP1_WCOUNT(),
|
||||
.S_AXI_HP1_RACOUNT(),
|
||||
.S_AXI_HP1_WACOUNT(),
|
||||
.S_AXI_HP1_ACLK(1'B0),
|
||||
.S_AXI_HP1_ARVALID(1'B0),
|
||||
.S_AXI_HP1_AWVALID(1'B0),
|
||||
.S_AXI_HP1_BREADY(1'B0),
|
||||
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
|
||||
.S_AXI_HP1_RREADY(1'B0),
|
||||
.S_AXI_HP1_WLAST(1'B0),
|
||||
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
|
||||
.S_AXI_HP1_WVALID(1'B0),
|
||||
.S_AXI_HP1_ARBURST(2'B0),
|
||||
.S_AXI_HP1_ARLOCK(2'B0),
|
||||
.S_AXI_HP1_ARSIZE(3'B0),
|
||||
.S_AXI_HP1_AWBURST(2'B0),
|
||||
.S_AXI_HP1_AWLOCK(2'B0),
|
||||
.S_AXI_HP1_AWSIZE(3'B0),
|
||||
.S_AXI_HP1_ARPROT(3'B0),
|
||||
.S_AXI_HP1_AWPROT(3'B0),
|
||||
.S_AXI_HP1_ARADDR(32'B0),
|
||||
.S_AXI_HP1_AWADDR(32'B0),
|
||||
.S_AXI_HP1_ARCACHE(4'B0),
|
||||
.S_AXI_HP1_ARLEN(4'B0),
|
||||
.S_AXI_HP1_ARQOS(4'B0),
|
||||
.S_AXI_HP1_AWCACHE(4'B0),
|
||||
.S_AXI_HP1_AWLEN(4'B0),
|
||||
.S_AXI_HP1_AWQOS(4'B0),
|
||||
.S_AXI_HP1_ARID(6'B0),
|
||||
.S_AXI_HP1_AWID(6'B0),
|
||||
.S_AXI_HP1_WID(6'B0),
|
||||
.S_AXI_HP1_WDATA(64'B0),
|
||||
.S_AXI_HP1_WSTRB(8'B0),
|
||||
.S_AXI_HP2_ARREADY(),
|
||||
.S_AXI_HP2_AWREADY(),
|
||||
.S_AXI_HP2_BVALID(),
|
||||
.S_AXI_HP2_RLAST(),
|
||||
.S_AXI_HP2_RVALID(),
|
||||
.S_AXI_HP2_WREADY(),
|
||||
.S_AXI_HP2_BRESP(),
|
||||
.S_AXI_HP2_RRESP(),
|
||||
.S_AXI_HP2_BID(),
|
||||
.S_AXI_HP2_RID(),
|
||||
.S_AXI_HP2_RDATA(),
|
||||
.S_AXI_HP2_RCOUNT(),
|
||||
.S_AXI_HP2_WCOUNT(),
|
||||
.S_AXI_HP2_RACOUNT(),
|
||||
.S_AXI_HP2_WACOUNT(),
|
||||
.S_AXI_HP2_ACLK(1'B0),
|
||||
.S_AXI_HP2_ARVALID(1'B0),
|
||||
.S_AXI_HP2_AWVALID(1'B0),
|
||||
.S_AXI_HP2_BREADY(1'B0),
|
||||
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
|
||||
.S_AXI_HP2_RREADY(1'B0),
|
||||
.S_AXI_HP2_WLAST(1'B0),
|
||||
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
|
||||
.S_AXI_HP2_WVALID(1'B0),
|
||||
.S_AXI_HP2_ARBURST(2'B0),
|
||||
.S_AXI_HP2_ARLOCK(2'B0),
|
||||
.S_AXI_HP2_ARSIZE(3'B0),
|
||||
.S_AXI_HP2_AWBURST(2'B0),
|
||||
.S_AXI_HP2_AWLOCK(2'B0),
|
||||
.S_AXI_HP2_AWSIZE(3'B0),
|
||||
.S_AXI_HP2_ARPROT(3'B0),
|
||||
.S_AXI_HP2_AWPROT(3'B0),
|
||||
.S_AXI_HP2_ARADDR(32'B0),
|
||||
.S_AXI_HP2_AWADDR(32'B0),
|
||||
.S_AXI_HP2_ARCACHE(4'B0),
|
||||
.S_AXI_HP2_ARLEN(4'B0),
|
||||
.S_AXI_HP2_ARQOS(4'B0),
|
||||
.S_AXI_HP2_AWCACHE(4'B0),
|
||||
.S_AXI_HP2_AWLEN(4'B0),
|
||||
.S_AXI_HP2_AWQOS(4'B0),
|
||||
.S_AXI_HP2_ARID(6'B0),
|
||||
.S_AXI_HP2_AWID(6'B0),
|
||||
.S_AXI_HP2_WID(6'B0),
|
||||
.S_AXI_HP2_WDATA(64'B0),
|
||||
.S_AXI_HP2_WSTRB(8'B0),
|
||||
.S_AXI_HP3_ARREADY(),
|
||||
.S_AXI_HP3_AWREADY(),
|
||||
.S_AXI_HP3_BVALID(),
|
||||
.S_AXI_HP3_RLAST(),
|
||||
.S_AXI_HP3_RVALID(),
|
||||
.S_AXI_HP3_WREADY(),
|
||||
.S_AXI_HP3_BRESP(),
|
||||
.S_AXI_HP3_RRESP(),
|
||||
.S_AXI_HP3_BID(),
|
||||
.S_AXI_HP3_RID(),
|
||||
.S_AXI_HP3_RDATA(),
|
||||
.S_AXI_HP3_RCOUNT(),
|
||||
.S_AXI_HP3_WCOUNT(),
|
||||
.S_AXI_HP3_RACOUNT(),
|
||||
.S_AXI_HP3_WACOUNT(),
|
||||
.S_AXI_HP3_ACLK(1'B0),
|
||||
.S_AXI_HP3_ARVALID(1'B0),
|
||||
.S_AXI_HP3_AWVALID(1'B0),
|
||||
.S_AXI_HP3_BREADY(1'B0),
|
||||
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
|
||||
.S_AXI_HP3_RREADY(1'B0),
|
||||
.S_AXI_HP3_WLAST(1'B0),
|
||||
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
|
||||
.S_AXI_HP3_WVALID(1'B0),
|
||||
.S_AXI_HP3_ARBURST(2'B0),
|
||||
.S_AXI_HP3_ARLOCK(2'B0),
|
||||
.S_AXI_HP3_ARSIZE(3'B0),
|
||||
.S_AXI_HP3_AWBURST(2'B0),
|
||||
.S_AXI_HP3_AWLOCK(2'B0),
|
||||
.S_AXI_HP3_AWSIZE(3'B0),
|
||||
.S_AXI_HP3_ARPROT(3'B0),
|
||||
.S_AXI_HP3_AWPROT(3'B0),
|
||||
.S_AXI_HP3_ARADDR(32'B0),
|
||||
.S_AXI_HP3_AWADDR(32'B0),
|
||||
.S_AXI_HP3_ARCACHE(4'B0),
|
||||
.S_AXI_HP3_ARLEN(4'B0),
|
||||
.S_AXI_HP3_ARQOS(4'B0),
|
||||
.S_AXI_HP3_AWCACHE(4'B0),
|
||||
.S_AXI_HP3_AWLEN(4'B0),
|
||||
.S_AXI_HP3_AWQOS(4'B0),
|
||||
.S_AXI_HP3_ARID(6'B0),
|
||||
.S_AXI_HP3_AWID(6'B0),
|
||||
.S_AXI_HP3_WID(6'B0),
|
||||
.S_AXI_HP3_WDATA(64'B0),
|
||||
.S_AXI_HP3_WSTRB(8'B0),
|
||||
.IRQ_P2F_DMAC_ABORT(),
|
||||
.IRQ_P2F_DMAC0(),
|
||||
.IRQ_P2F_DMAC1(),
|
||||
.IRQ_P2F_DMAC2(),
|
||||
.IRQ_P2F_DMAC3(),
|
||||
.IRQ_P2F_DMAC4(),
|
||||
.IRQ_P2F_DMAC5(),
|
||||
.IRQ_P2F_DMAC6(),
|
||||
.IRQ_P2F_DMAC7(),
|
||||
.IRQ_P2F_SMC(),
|
||||
.IRQ_P2F_QSPI(),
|
||||
.IRQ_P2F_CTI(),
|
||||
.IRQ_P2F_GPIO(),
|
||||
.IRQ_P2F_USB0(),
|
||||
.IRQ_P2F_ENET0(),
|
||||
.IRQ_P2F_ENET_WAKE0(),
|
||||
.IRQ_P2F_SDIO0(),
|
||||
.IRQ_P2F_I2C0(),
|
||||
.IRQ_P2F_SPI0(),
|
||||
.IRQ_P2F_UART0(),
|
||||
.IRQ_P2F_CAN0(),
|
||||
.IRQ_P2F_USB1(),
|
||||
.IRQ_P2F_ENET1(),
|
||||
.IRQ_P2F_ENET_WAKE1(),
|
||||
.IRQ_P2F_SDIO1(),
|
||||
.IRQ_P2F_I2C1(),
|
||||
.IRQ_P2F_SPI1(),
|
||||
.IRQ_P2F_UART1(),
|
||||
.IRQ_P2F_CAN1(),
|
||||
.IRQ_F2P(1'B0),
|
||||
.Core0_nFIQ(1'B0),
|
||||
.Core0_nIRQ(1'B0),
|
||||
.Core1_nFIQ(1'B0),
|
||||
.Core1_nIRQ(1'B0),
|
||||
.DMA0_DATYPE(),
|
||||
.DMA0_DAVALID(),
|
||||
.DMA0_DRREADY(),
|
||||
.DMA1_DATYPE(),
|
||||
.DMA1_DAVALID(),
|
||||
.DMA1_DRREADY(),
|
||||
.DMA2_DATYPE(),
|
||||
.DMA2_DAVALID(),
|
||||
.DMA2_DRREADY(),
|
||||
.DMA3_DATYPE(),
|
||||
.DMA3_DAVALID(),
|
||||
.DMA3_DRREADY(),
|
||||
.DMA0_ACLK(1'B0),
|
||||
.DMA0_DAREADY(1'B0),
|
||||
.DMA0_DRLAST(1'B0),
|
||||
.DMA0_DRVALID(1'B0),
|
||||
.DMA1_ACLK(1'B0),
|
||||
.DMA1_DAREADY(1'B0),
|
||||
.DMA1_DRLAST(1'B0),
|
||||
.DMA1_DRVALID(1'B0),
|
||||
.DMA2_ACLK(1'B0),
|
||||
.DMA2_DAREADY(1'B0),
|
||||
.DMA2_DRLAST(1'B0),
|
||||
.DMA2_DRVALID(1'B0),
|
||||
.DMA3_ACLK(1'B0),
|
||||
.DMA3_DAREADY(1'B0),
|
||||
.DMA3_DRLAST(1'B0),
|
||||
.DMA3_DRVALID(1'B0),
|
||||
.DMA0_DRTYPE(2'B0),
|
||||
.DMA1_DRTYPE(2'B0),
|
||||
.DMA2_DRTYPE(2'B0),
|
||||
.DMA3_DRTYPE(2'B0),
|
||||
.FCLK_CLK0(FCLK_CLK0),
|
||||
.FCLK_CLK1(),
|
||||
.FCLK_CLK2(),
|
||||
.FCLK_CLK3(),
|
||||
.FCLK_CLKTRIG0_N(1'B0),
|
||||
.FCLK_CLKTRIG1_N(1'B0),
|
||||
.FCLK_CLKTRIG2_N(1'B0),
|
||||
.FCLK_CLKTRIG3_N(1'B0),
|
||||
.FCLK_RESET0_N(FCLK_RESET0_N),
|
||||
.FCLK_RESET1_N(),
|
||||
.FCLK_RESET2_N(),
|
||||
.FCLK_RESET3_N(),
|
||||
.FTMD_TRACEIN_DATA(32'B0),
|
||||
.FTMD_TRACEIN_VALID(1'B0),
|
||||
.FTMD_TRACEIN_CLK(1'B0),
|
||||
.FTMD_TRACEIN_ATID(4'B0),
|
||||
.FTMT_F2P_TRIG_0(1'B0),
|
||||
.FTMT_F2P_TRIGACK_0(),
|
||||
.FTMT_F2P_TRIG_1(1'B0),
|
||||
.FTMT_F2P_TRIGACK_1(),
|
||||
.FTMT_F2P_TRIG_2(1'B0),
|
||||
.FTMT_F2P_TRIGACK_2(),
|
||||
.FTMT_F2P_TRIG_3(1'B0),
|
||||
.FTMT_F2P_TRIGACK_3(),
|
||||
.FTMT_F2P_DEBUG(32'B0),
|
||||
.FTMT_P2F_TRIGACK_0(1'B0),
|
||||
.FTMT_P2F_TRIG_0(),
|
||||
.FTMT_P2F_TRIGACK_1(1'B0),
|
||||
.FTMT_P2F_TRIG_1(),
|
||||
.FTMT_P2F_TRIGACK_2(1'B0),
|
||||
.FTMT_P2F_TRIG_2(),
|
||||
.FTMT_P2F_TRIGACK_3(1'B0),
|
||||
.FTMT_P2F_TRIG_3(),
|
||||
.FTMT_P2F_DEBUG(),
|
||||
.FPGA_IDLE_N(1'B0),
|
||||
.EVENT_EVENTO(),
|
||||
.EVENT_STANDBYWFE(),
|
||||
.EVENT_STANDBYWFI(),
|
||||
.EVENT_EVENTI(1'B0),
|
||||
.DDR_ARB(4'B0),
|
||||
.MIO(MIO),
|
||||
.DDR_CAS_n(DDR_CAS_n),
|
||||
.DDR_CKE(DDR_CKE),
|
||||
.DDR_Clk_n(DDR_Clk_n),
|
||||
.DDR_Clk(DDR_Clk),
|
||||
.DDR_CS_n(DDR_CS_n),
|
||||
.DDR_DRSTB(DDR_DRSTB),
|
||||
.DDR_ODT(DDR_ODT),
|
||||
.DDR_RAS_n(DDR_RAS_n),
|
||||
.DDR_WEB(DDR_WEB),
|
||||
.DDR_BankAddr(DDR_BankAddr),
|
||||
.DDR_Addr(DDR_Addr),
|
||||
.DDR_VRN(DDR_VRN),
|
||||
.DDR_VRP(DDR_VRP),
|
||||
.DDR_DM(DDR_DM),
|
||||
.DDR_DQ(DDR_DQ),
|
||||
.DDR_DQS_n(DDR_DQS_n),
|
||||
.DDR_DQS(DDR_DQS),
|
||||
.PS_SRSTB(PS_SRSTB),
|
||||
.PS_CLK(PS_CLK),
|
||||
.PS_PORB(PS_PORB)
|
||||
);
|
||||
endmodule
|
||||
+541
@@ -0,0 +1,541 @@
|
||||
############################################################################
|
||||
##
|
||||
## Xilinx, Inc. 2006 www.xilinx.com
|
||||
############################################################################
|
||||
## File name : ps7_constraints.xdc
|
||||
##
|
||||
## Details : Constraints file
|
||||
## FPGA family: zynq
|
||||
## FPGA: xc7z035ffg676-2
|
||||
## Device Size: xc7z035
|
||||
## Package: ffg676
|
||||
## Speedgrade: -2
|
||||
##
|
||||
##
|
||||
############################################################################
|
||||
############################################################################
|
||||
############################################################################
|
||||
# Clock constraints #
|
||||
############################################################################
|
||||
create_clock -name clk_fpga_0 -period "10" [get_pins "PS7_i/FCLKCLK[0]"]
|
||||
set_input_jitter clk_fpga_0 0.3
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
|
||||
|
||||
############################################################################
|
||||
# I/O STANDARDS and Location Constraints #
|
||||
############################################################################
|
||||
|
||||
# Enet 0 / mdio / MIO[53]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[53]"]
|
||||
set_property PACKAGE_PIN "A19" [get_ports "MIO[53]"]
|
||||
set_property slew "slow" [get_ports "MIO[53]"]
|
||||
set_property drive "8" [get_ports "MIO[53]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[53]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[53]"]
|
||||
# Enet 0 / mdc / MIO[52]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[52]"]
|
||||
set_property PACKAGE_PIN "A20" [get_ports "MIO[52]"]
|
||||
set_property slew "slow" [get_ports "MIO[52]"]
|
||||
set_property drive "8" [get_ports "MIO[52]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[52]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[52]"]
|
||||
# UART 1 / rx / MIO[49]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[49]"]
|
||||
set_property PACKAGE_PIN "A18" [get_ports "MIO[49]"]
|
||||
set_property slew "slow" [get_ports "MIO[49]"]
|
||||
set_property drive "8" [get_ports "MIO[49]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[49]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[49]"]
|
||||
# UART 1 / tx / MIO[48]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[48]"]
|
||||
set_property PACKAGE_PIN "B21" [get_ports "MIO[48]"]
|
||||
set_property slew "slow" [get_ports "MIO[48]"]
|
||||
set_property drive "8" [get_ports "MIO[48]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[48]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[48]"]
|
||||
# SD 0 / cd / MIO[47]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[47]"]
|
||||
set_property PACKAGE_PIN "B19" [get_ports "MIO[47]"]
|
||||
set_property slew "slow" [get_ports "MIO[47]"]
|
||||
set_property drive "8" [get_ports "MIO[47]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[47]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[47]"]
|
||||
# SD 0 / wp / MIO[46]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[46]"]
|
||||
set_property PACKAGE_PIN "E17" [get_ports "MIO[46]"]
|
||||
set_property slew "slow" [get_ports "MIO[46]"]
|
||||
set_property drive "8" [get_ports "MIO[46]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[46]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[46]"]
|
||||
# SD 0 / data[3] / MIO[45]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[45]"]
|
||||
set_property PACKAGE_PIN "C18" [get_ports "MIO[45]"]
|
||||
set_property slew "slow" [get_ports "MIO[45]"]
|
||||
set_property drive "8" [get_ports "MIO[45]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[45]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[45]"]
|
||||
# SD 0 / data[2] / MIO[44]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[44]"]
|
||||
set_property PACKAGE_PIN "E18" [get_ports "MIO[44]"]
|
||||
set_property slew "slow" [get_ports "MIO[44]"]
|
||||
set_property drive "8" [get_ports "MIO[44]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[44]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[44]"]
|
||||
# SD 0 / data[1] / MIO[43]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[43]"]
|
||||
set_property PACKAGE_PIN "D18" [get_ports "MIO[43]"]
|
||||
set_property slew "slow" [get_ports "MIO[43]"]
|
||||
set_property drive "8" [get_ports "MIO[43]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[43]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[43]"]
|
||||
# SD 0 / data[0] / MIO[42]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[42]"]
|
||||
set_property PACKAGE_PIN "F17" [get_ports "MIO[42]"]
|
||||
set_property slew "slow" [get_ports "MIO[42]"]
|
||||
set_property drive "8" [get_ports "MIO[42]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[42]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[42]"]
|
||||
# SD 0 / cmd / MIO[41]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[41]"]
|
||||
set_property PACKAGE_PIN "C19" [get_ports "MIO[41]"]
|
||||
set_property slew "slow" [get_ports "MIO[41]"]
|
||||
set_property drive "8" [get_ports "MIO[41]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[41]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[41]"]
|
||||
# SD 0 / clk / MIO[40]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[40]"]
|
||||
set_property PACKAGE_PIN "C22" [get_ports "MIO[40]"]
|
||||
set_property slew "slow" [get_ports "MIO[40]"]
|
||||
set_property drive "8" [get_ports "MIO[40]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[40]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[40]"]
|
||||
# Enet 0 / rx_ctl / MIO[27]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[27]"]
|
||||
set_property PACKAGE_PIN "F18" [get_ports "MIO[27]"]
|
||||
set_property slew "slow" [get_ports "MIO[27]"]
|
||||
set_property drive "8" [get_ports "MIO[27]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[27]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[27]"]
|
||||
# Enet 0 / rxd[3] / MIO[26]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[26]"]
|
||||
set_property PACKAGE_PIN "H17" [get_ports "MIO[26]"]
|
||||
set_property slew "slow" [get_ports "MIO[26]"]
|
||||
set_property drive "8" [get_ports "MIO[26]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[26]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[26]"]
|
||||
# Enet 0 / rxd[2] / MIO[25]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[25]"]
|
||||
set_property PACKAGE_PIN "F19" [get_ports "MIO[25]"]
|
||||
set_property slew "slow" [get_ports "MIO[25]"]
|
||||
set_property drive "8" [get_ports "MIO[25]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[25]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[25]"]
|
||||
# Enet 0 / rxd[1] / MIO[24]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[24]"]
|
||||
set_property PACKAGE_PIN "J19" [get_ports "MIO[24]"]
|
||||
set_property slew "slow" [get_ports "MIO[24]"]
|
||||
set_property drive "8" [get_ports "MIO[24]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[24]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[24]"]
|
||||
# Enet 0 / rxd[0] / MIO[23]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[23]"]
|
||||
set_property PACKAGE_PIN "F20" [get_ports "MIO[23]"]
|
||||
set_property slew "slow" [get_ports "MIO[23]"]
|
||||
set_property drive "8" [get_ports "MIO[23]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[23]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[23]"]
|
||||
# Enet 0 / rx_clk / MIO[22]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[22]"]
|
||||
set_property PACKAGE_PIN "G22" [get_ports "MIO[22]"]
|
||||
set_property slew "slow" [get_ports "MIO[22]"]
|
||||
set_property drive "8" [get_ports "MIO[22]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[22]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[22]"]
|
||||
# Enet 0 / tx_ctl / MIO[21]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[21]"]
|
||||
set_property PACKAGE_PIN "F22" [get_ports "MIO[21]"]
|
||||
set_property slew "slow" [get_ports "MIO[21]"]
|
||||
set_property drive "8" [get_ports "MIO[21]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[21]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[21]"]
|
||||
# Enet 0 / txd[3] / MIO[20]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[20]"]
|
||||
set_property PACKAGE_PIN "H19" [get_ports "MIO[20]"]
|
||||
set_property slew "slow" [get_ports "MIO[20]"]
|
||||
set_property drive "8" [get_ports "MIO[20]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[20]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[20]"]
|
||||
# Enet 0 / txd[2] / MIO[19]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[19]"]
|
||||
set_property PACKAGE_PIN "G19" [get_ports "MIO[19]"]
|
||||
set_property slew "slow" [get_ports "MIO[19]"]
|
||||
set_property drive "8" [get_ports "MIO[19]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[19]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[19]"]
|
||||
# Enet 0 / txd[1] / MIO[18]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[18]"]
|
||||
set_property PACKAGE_PIN "G20" [get_ports "MIO[18]"]
|
||||
set_property slew "slow" [get_ports "MIO[18]"]
|
||||
set_property drive "8" [get_ports "MIO[18]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[18]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[18]"]
|
||||
# Enet 0 / txd[0] / MIO[17]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[17]"]
|
||||
set_property PACKAGE_PIN "G17" [get_ports "MIO[17]"]
|
||||
set_property slew "slow" [get_ports "MIO[17]"]
|
||||
set_property drive "8" [get_ports "MIO[17]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[17]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[17]"]
|
||||
# Enet 0 / tx_clk / MIO[16]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[16]"]
|
||||
set_property PACKAGE_PIN "G21" [get_ports "MIO[16]"]
|
||||
set_property slew "slow" [get_ports "MIO[16]"]
|
||||
set_property drive "8" [get_ports "MIO[16]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[16]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[16]"]
|
||||
# Quad SPI Flash / qspi_fbclk / MIO[8]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[8]"]
|
||||
set_property PACKAGE_PIN "A24" [get_ports "MIO[8]"]
|
||||
set_property slew "slow" [get_ports "MIO[8]"]
|
||||
set_property drive "8" [get_ports "MIO[8]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[8]"]
|
||||
# Quad SPI Flash / qspi0_sclk / MIO[6]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[6]"]
|
||||
set_property PACKAGE_PIN "F23" [get_ports "MIO[6]"]
|
||||
set_property slew "slow" [get_ports "MIO[6]"]
|
||||
set_property drive "8" [get_ports "MIO[6]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[6]"]
|
||||
# Quad SPI Flash / qspi0_io[3]/HOLD_B / MIO[5]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[5]"]
|
||||
set_property PACKAGE_PIN "C26" [get_ports "MIO[5]"]
|
||||
set_property slew "slow" [get_ports "MIO[5]"]
|
||||
set_property drive "8" [get_ports "MIO[5]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[5]"]
|
||||
# Quad SPI Flash / qspi0_io[2] / MIO[4]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[4]"]
|
||||
set_property PACKAGE_PIN "F24" [get_ports "MIO[4]"]
|
||||
set_property slew "slow" [get_ports "MIO[4]"]
|
||||
set_property drive "8" [get_ports "MIO[4]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[4]"]
|
||||
# Quad SPI Flash / qspi0_io[1] / MIO[3]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[3]"]
|
||||
set_property PACKAGE_PIN "D25" [get_ports "MIO[3]"]
|
||||
set_property slew "slow" [get_ports "MIO[3]"]
|
||||
set_property drive "8" [get_ports "MIO[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[3]"]
|
||||
# Quad SPI Flash / qspi0_io[0] / MIO[2]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[2]"]
|
||||
set_property PACKAGE_PIN "E25" [get_ports "MIO[2]"]
|
||||
set_property slew "slow" [get_ports "MIO[2]"]
|
||||
set_property drive "8" [get_ports "MIO[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[2]"]
|
||||
# Quad SPI Flash / qspi0_ss_b / MIO[1]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[1]"]
|
||||
set_property PACKAGE_PIN "D26" [get_ports "MIO[1]"]
|
||||
set_property slew "slow" [get_ports "MIO[1]"]
|
||||
set_property drive "8" [get_ports "MIO[1]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[1]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[1]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRP"]
|
||||
set_property PACKAGE_PIN "W21" [get_ports "DDR_VRP"]
|
||||
set_property slew "FAST" [get_ports "DDR_VRP"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRP"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRN"]
|
||||
set_property PACKAGE_PIN "V21" [get_ports "DDR_VRN"]
|
||||
set_property slew "FAST" [get_ports "DDR_VRN"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRN"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_WEB"]
|
||||
set_property PACKAGE_PIN "V22" [get_ports "DDR_WEB"]
|
||||
set_property slew "SLOW" [get_ports "DDR_WEB"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_WEB"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_RAS_n"]
|
||||
set_property PACKAGE_PIN "V23" [get_ports "DDR_RAS_n"]
|
||||
set_property slew "SLOW" [get_ports "DDR_RAS_n"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_RAS_n"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_ODT"]
|
||||
set_property PACKAGE_PIN "Y22" [get_ports "DDR_ODT"]
|
||||
set_property slew "SLOW" [get_ports "DDR_ODT"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_ODT"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_DRSTB"]
|
||||
set_property PACKAGE_PIN "H22" [get_ports "DDR_DRSTB"]
|
||||
set_property slew "FAST" [get_ports "DDR_DRSTB"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DRSTB"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[3]"]
|
||||
set_property PACKAGE_PIN "W24" [get_ports "DDR_DQS[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[3]"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[2]"]
|
||||
set_property PACKAGE_PIN "P25" [get_ports "DDR_DQS[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[2]"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[1]"]
|
||||
set_property PACKAGE_PIN "L24" [get_ports "DDR_DQS[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[1]"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[0]"]
|
||||
set_property PACKAGE_PIN "H24" [get_ports "DDR_DQS[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[0]"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property PACKAGE_PIN "W25" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property PACKAGE_PIN "R25" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property PACKAGE_PIN "L25" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property PACKAGE_PIN "G25" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[9]"]
|
||||
set_property PACKAGE_PIN "L23" [get_ports "DDR_DQ[9]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[9]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[9]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[8]"]
|
||||
set_property PACKAGE_PIN "K26" [get_ports "DDR_DQ[8]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[8]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[8]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[7]"]
|
||||
set_property PACKAGE_PIN "J23" [get_ports "DDR_DQ[7]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[7]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[7]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[6]"]
|
||||
set_property PACKAGE_PIN "J24" [get_ports "DDR_DQ[6]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[6]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[6]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[5]"]
|
||||
set_property PACKAGE_PIN "H23" [get_ports "DDR_DQ[5]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[5]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[5]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[4]"]
|
||||
set_property PACKAGE_PIN "H26" [get_ports "DDR_DQ[4]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[4]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[4]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[3]"]
|
||||
set_property PACKAGE_PIN "G26" [get_ports "DDR_DQ[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[3]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[31]"]
|
||||
set_property PACKAGE_PIN "W23" [get_ports "DDR_DQ[31]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[31]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[31]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[30]"]
|
||||
set_property PACKAGE_PIN "Y26" [get_ports "DDR_DQ[30]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[30]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[30]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[2]"]
|
||||
set_property PACKAGE_PIN "J25" [get_ports "DDR_DQ[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[2]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[29]"]
|
||||
set_property PACKAGE_PIN "Y25" [get_ports "DDR_DQ[29]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[29]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[29]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[28]"]
|
||||
set_property PACKAGE_PIN "W26" [get_ports "DDR_DQ[28]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[28]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[28]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[27]"]
|
||||
set_property PACKAGE_PIN "U25" [get_ports "DDR_DQ[27]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[27]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[27]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[26]"]
|
||||
set_property PACKAGE_PIN "U24" [get_ports "DDR_DQ[26]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[26]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[26]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[25]"]
|
||||
set_property PACKAGE_PIN "U26" [get_ports "DDR_DQ[25]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[25]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[25]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[24]"]
|
||||
set_property PACKAGE_PIN "V24" [get_ports "DDR_DQ[24]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[24]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[24]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[23]"]
|
||||
set_property PACKAGE_PIN "R23" [get_ports "DDR_DQ[23]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[23]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[23]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[22]"]
|
||||
set_property PACKAGE_PIN "T23" [get_ports "DDR_DQ[22]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[22]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[22]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[21]"]
|
||||
set_property PACKAGE_PIN "T25" [get_ports "DDR_DQ[21]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[21]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[21]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[20]"]
|
||||
set_property PACKAGE_PIN "T24" [get_ports "DDR_DQ[20]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[20]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[20]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[1]"]
|
||||
set_property PACKAGE_PIN "F25" [get_ports "DDR_DQ[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[1]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[19]"]
|
||||
set_property PACKAGE_PIN "P23" [get_ports "DDR_DQ[19]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[19]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[19]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[18]"]
|
||||
set_property PACKAGE_PIN "N26" [get_ports "DDR_DQ[18]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[18]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[18]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[17]"]
|
||||
set_property PACKAGE_PIN "P24" [get_ports "DDR_DQ[17]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[17]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[17]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[16]"]
|
||||
set_property PACKAGE_PIN "R26" [get_ports "DDR_DQ[16]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[16]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[16]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[15]"]
|
||||
set_property PACKAGE_PIN "N23" [get_ports "DDR_DQ[15]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[15]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[15]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[14]"]
|
||||
set_property PACKAGE_PIN "M24" [get_ports "DDR_DQ[14]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[14]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[14]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[13]"]
|
||||
set_property PACKAGE_PIN "N24" [get_ports "DDR_DQ[13]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[13]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[13]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[12]"]
|
||||
set_property PACKAGE_PIN "M25" [get_ports "DDR_DQ[12]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[12]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[12]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[11]"]
|
||||
set_property PACKAGE_PIN "K23" [get_ports "DDR_DQ[11]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[11]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[11]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[10]"]
|
||||
set_property PACKAGE_PIN "M26" [get_ports "DDR_DQ[10]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[10]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[10]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[0]"]
|
||||
set_property PACKAGE_PIN "J26" [get_ports "DDR_DQ[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[0]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[3]"]
|
||||
set_property PACKAGE_PIN "V26" [get_ports "DDR_DM[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[3]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[2]"]
|
||||
set_property PACKAGE_PIN "P26" [get_ports "DDR_DM[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[2]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[1]"]
|
||||
set_property PACKAGE_PIN "K25" [get_ports "DDR_DM[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[1]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[0]"]
|
||||
set_property PACKAGE_PIN "G24" [get_ports "DDR_DM[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[0]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_CS_n"]
|
||||
set_property PACKAGE_PIN "Y21" [get_ports "DDR_CS_n"]
|
||||
set_property slew "SLOW" [get_ports "DDR_CS_n"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CS_n"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_CKE"]
|
||||
set_property PACKAGE_PIN "U21" [get_ports "DDR_CKE"]
|
||||
set_property slew "SLOW" [get_ports "DDR_CKE"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CKE"]
|
||||
set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk"]
|
||||
set_property PACKAGE_PIN "R21" [get_ports "DDR_Clk"]
|
||||
set_property slew "FAST" [get_ports "DDR_Clk"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk"]
|
||||
set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk_n"]
|
||||
set_property PACKAGE_PIN "P21" [get_ports "DDR_Clk_n"]
|
||||
set_property slew "FAST" [get_ports "DDR_Clk_n"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk_n"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_CAS_n"]
|
||||
set_property PACKAGE_PIN "Y23" [get_ports "DDR_CAS_n"]
|
||||
set_property slew "SLOW" [get_ports "DDR_CAS_n"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CAS_n"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property PACKAGE_PIN "R22" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property PACKAGE_PIN "T22" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property PACKAGE_PIN "U22" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[9]"]
|
||||
set_property PACKAGE_PIN "U20" [get_ports "DDR_Addr[9]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[9]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[9]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[8]"]
|
||||
set_property PACKAGE_PIN "T20" [get_ports "DDR_Addr[8]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[8]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[8]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[7]"]
|
||||
set_property PACKAGE_PIN "J21" [get_ports "DDR_Addr[7]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[7]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[7]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[6]"]
|
||||
set_property PACKAGE_PIN "L20" [get_ports "DDR_Addr[6]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[6]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[6]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[5]"]
|
||||
set_property PACKAGE_PIN "N22" [get_ports "DDR_Addr[5]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[5]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[5]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[4]"]
|
||||
set_property PACKAGE_PIN "M20" [get_ports "DDR_Addr[4]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[4]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[4]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[3]"]
|
||||
set_property PACKAGE_PIN "L22" [get_ports "DDR_Addr[3]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[3]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[3]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[2]"]
|
||||
set_property PACKAGE_PIN "N21" [get_ports "DDR_Addr[2]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[2]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[2]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[1]"]
|
||||
set_property PACKAGE_PIN "K20" [get_ports "DDR_Addr[1]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[1]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[1]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[14]"]
|
||||
set_property PACKAGE_PIN "R20" [get_ports "DDR_Addr[14]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[14]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[14]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[13]"]
|
||||
set_property PACKAGE_PIN "J20" [get_ports "DDR_Addr[13]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[13]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[13]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[12]"]
|
||||
set_property PACKAGE_PIN "P20" [get_ports "DDR_Addr[12]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[12]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[12]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[11]"]
|
||||
set_property PACKAGE_PIN "H21" [get_ports "DDR_Addr[11]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[11]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[11]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[10]"]
|
||||
set_property PACKAGE_PIN "M22" [get_ports "DDR_Addr[10]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[10]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[10]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[0]"]
|
||||
set_property PACKAGE_PIN "K22" [get_ports "DDR_Addr[0]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[0]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[0]"]
|
||||
set_property iostandard "LVCMOS33" [get_ports "PS_PORB"]
|
||||
set_property PACKAGE_PIN "C23" [get_ports "PS_PORB"]
|
||||
set_property slew "fast" [get_ports "PS_PORB"]
|
||||
set_property iostandard "LVCMOS18" [get_ports "PS_SRSTB"]
|
||||
set_property PACKAGE_PIN "A22" [get_ports "PS_SRSTB"]
|
||||
set_property slew "fast" [get_ports "PS_SRSTB"]
|
||||
set_property iostandard "LVCMOS33" [get_ports "PS_CLK"]
|
||||
set_property PACKAGE_PIN "B24" [get_ports "PS_CLK"]
|
||||
set_property slew "fast" [get_ports "PS_CLK"]
|
||||
|
||||
+39724
File diff suppressed because it is too large
Load Diff
+1644
File diff suppressed because it is too large
Load Diff
+147
@@ -0,0 +1,147 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
|
||||
-- IP Revision: 14
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY proc_sys_reset_v5_0_14;
|
||||
USE proc_sys_reset_v5_0_14.proc_sys_reset;
|
||||
|
||||
ENTITY system_rst_ps7_0_100M_1 IS
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END system_rst_ps7_0_100M_1;
|
||||
|
||||
ARCHITECTURE system_rst_ps7_0_100M_1_arch OF system_rst_ps7_0_100M_1 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rst_ps7_0_100M_1_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT proc_sys_reset IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_EXT_RST_WIDTH : INTEGER;
|
||||
C_AUX_RST_WIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : STD_LOGIC;
|
||||
C_AUX_RESET_HIGH : STD_LOGIC;
|
||||
C_NUM_BUS_RST : INTEGER;
|
||||
C_NUM_PERP_RST : INTEGER;
|
||||
C_NUM_INTERCONNECT_ARESETN : INTEGER;
|
||||
C_NUM_PERP_ARESETN : INTEGER
|
||||
);
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_EXT_RST_WIDTH => 4,
|
||||
C_AUX_RST_WIDTH => 4,
|
||||
C_EXT_RESET_HIGH => '0',
|
||||
C_AUX_RESET_HIGH => '0',
|
||||
C_NUM_BUS_RST => 1,
|
||||
C_NUM_PERP_RST => 1,
|
||||
C_NUM_INTERCONNECT_ARESETN => 1,
|
||||
C_NUM_PERP_ARESETN => 1
|
||||
)
|
||||
PORT MAP (
|
||||
slowest_sync_clk => slowest_sync_clk,
|
||||
ext_reset_in => ext_reset_in,
|
||||
aux_reset_in => aux_reset_in,
|
||||
mb_debug_sys_rst => mb_debug_sys_rst,
|
||||
dcm_locked => dcm_locked,
|
||||
mb_reset => mb_reset,
|
||||
bus_struct_reset => bus_struct_reset,
|
||||
peripheral_reset => peripheral_reset,
|
||||
interconnect_aresetn => interconnect_aresetn,
|
||||
peripheral_aresetn => peripheral_aresetn
|
||||
);
|
||||
END system_rst_ps7_0_100M_1_arch;
|
||||
+153
@@ -0,0 +1,153 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
|
||||
-- IP Revision: 14
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY proc_sys_reset_v5_0_14;
|
||||
USE proc_sys_reset_v5_0_14.proc_sys_reset;
|
||||
|
||||
ENTITY system_rst_ps7_0_100M_1 IS
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END system_rst_ps7_0_100M_1;
|
||||
|
||||
ARCHITECTURE system_rst_ps7_0_100M_1_arch OF system_rst_ps7_0_100M_1 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rst_ps7_0_100M_1_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT proc_sys_reset IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_EXT_RST_WIDTH : INTEGER;
|
||||
C_AUX_RST_WIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : STD_LOGIC;
|
||||
C_AUX_RESET_HIGH : STD_LOGIC;
|
||||
C_NUM_BUS_RST : INTEGER;
|
||||
C_NUM_PERP_RST : INTEGER;
|
||||
C_NUM_INTERCONNECT_ARESETN : INTEGER;
|
||||
C_NUM_PERP_ARESETN : INTEGER
|
||||
);
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_rst_ps7_0_100M_1_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2023.2";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rst_ps7_0_100M_1_arch : ARCHITECTURE IS "system_rst_ps7_0_100M_1,proc_sys_reset,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_rst_ps7_0_100M_1_arch: ARCHITECTURE IS "system_rst_ps7_0_100M_1,proc_sys_reset,{x_ipProduct=Vivado 2023.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_EXT_RST_WIDTH => 4,
|
||||
C_AUX_RST_WIDTH => 4,
|
||||
C_EXT_RESET_HIGH => '0',
|
||||
C_AUX_RESET_HIGH => '0',
|
||||
C_NUM_BUS_RST => 1,
|
||||
C_NUM_PERP_RST => 1,
|
||||
C_NUM_INTERCONNECT_ARESETN => 1,
|
||||
C_NUM_PERP_ARESETN => 1
|
||||
)
|
||||
PORT MAP (
|
||||
slowest_sync_clk => slowest_sync_clk,
|
||||
ext_reset_in => ext_reset_in,
|
||||
aux_reset_in => aux_reset_in,
|
||||
mb_debug_sys_rst => mb_debug_sys_rst,
|
||||
dcm_locked => dcm_locked,
|
||||
mb_reset => mb_reset,
|
||||
bus_struct_reset => bus_struct_reset,
|
||||
peripheral_reset => peripheral_reset,
|
||||
interconnect_aresetn => interconnect_aresetn,
|
||||
peripheral_aresetn => peripheral_aresetn
|
||||
);
|
||||
END system_rst_ps7_0_100M_1_arch;
|
||||
+53
@@ -0,0 +1,53 @@
|
||||
|
||||
# file: system_rst_ps7_0_100M_1.xdc
|
||||
# (c) Copyright 2009 - 2013 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Advanced Micro Devices, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
set_false_path -to [get_pins -hier *cdc_to*/D]
|
||||
create_waiver -type CDC -id {CDC-11} -user "proc_sys_reset" -desc "Timing uncritical paths" -tags "1171415" -scope -internal \
|
||||
-to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to}]]
|
||||
|
||||
|
||||
+924
@@ -0,0 +1,924 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>system_rst_ps7_0_100M_1</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>clock</spirit:name>
|
||||
<spirit:displayName>Clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>slowest_sync_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET">mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:displayName>Slowest Sync clock frequency</spirit:displayName>
|
||||
<spirit:description>Slowest Synchronous clock frequency</spirit:description>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">100000000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.PHASE">0.000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">system_processing_system7_0_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ext_reset</spirit:name>
|
||||
<spirit:displayName>Ext_Reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ext_reset_in</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:presence>required</xilinx:presence>
|
||||
</xilinx:enablement>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aux_reset</spirit:name>
|
||||
<spirit:displayName>aux_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aux_reset_in</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>dbg_reset</spirit:name>
|
||||
<spirit:displayName>DBG_Reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mb_debug_sys_rst</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.DBG_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.DBG_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>mb_rst</spirit:name>
|
||||
<spirit:displayName>MB_rst</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mb_reset</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.MB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TYPE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.MB_RST.TYPE">PROCESSOR</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MB_RST.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>bus_struct_reset</spirit:name>
|
||||
<spirit:displayName>bus_struct_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>bus_struct_reset</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TYPE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE">INTERCONNECT</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>interconnect_low_rst</spirit:name>
|
||||
<spirit:displayName>interconnect_low_rst</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>interconnect_aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TYPE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE">INTERCONNECT</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>peripheral_high_rst</spirit:name>
|
||||
<spirit:displayName>peripheral_high_rst</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>peripheral_reset</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY">ACTIVE_HIGH</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TYPE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.TYPE">PERIPHERAL</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>peripheral_low_rst</spirit:name>
|
||||
<spirit:displayName>peripheral_low_rst</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>peripheral_aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TYPE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.TYPE">PERIPHERAL</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_implementation</spirit:name>
|
||||
<spirit:displayName>Implementation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:implementation</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_implementation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon May 25 06:51:56 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:1038b797</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_synthesisconstraints_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon May 25 06:51:56 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:1038b797</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlbehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>proc_sys_reset</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon May 25 06:51:56 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:170f9ed9</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>system_rst_ps7_0_100M_1</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon May 25 06:51:56 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:170f9ed9</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>proc_sys_reset</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon May 25 06:51:56 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:1038b797</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>system_rst_ps7_0_100M_1</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon May 25 06:51:56 UTC 2026</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:1038b797</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>slowest_sync_clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ext_reset_in</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>aux_reset_in</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>mb_debug_sys_rst</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>dcm_locked</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>mb_reset</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>bus_struct_reset</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_BUS_RST')) - 1)">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>peripheral_reset</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_PERP_RST')) - 1)">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>interconnect_aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN')) - 1)">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>peripheral_aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_PERP_ARESETN')) - 1)">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
|
||||
<spirit:name>C_FAMILY</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_EXT_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Ext Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RST_WIDTH" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_AUX_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Aux Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RST_WIDTH" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="std_logic">
|
||||
<spirit:name>C_EXT_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Ext Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="std_logic">
|
||||
<spirit:name>C_AUX_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Aux Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RESET_HIGH" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_NUM_BUS_RST</spirit:name>
|
||||
<spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_BUS_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_NUM_PERP_RST</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_NUM_PERP_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_ARESETN" spirit:minimum="1" spirit:maximum="31" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_ac75ef1e</spirit:name>
|
||||
<spirit:enumeration>Custom</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_implementation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>system_rst_ps7_0_100M_1_board.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_board</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_synthesisconstraints_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>system_rst_ps7_0_100M_1_ooc.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
|
||||
<spirit:logicalName>lib_cdc_v1_0_2</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="lib_cdc" xilinx:version="1.0" xilinx:isGenerated="true" xilinx:checksum="726cb4eb">
|
||||
<xilinx:mode xilinx:name="copy_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
|
||||
<spirit:logicalName>proc_sys_reset_v5_0_14</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/system_rst_ps7_0_100M_1.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>lib_cdc_v1_0_2</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="lib_cdc" xilinx:version="1.0" xilinx:isGenerated="true" xilinx:checksum="726cb4eb">
|
||||
<xilinx:mode xilinx:name="copy_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>proc_sys_reset_v5_0_14</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>system_rst_ps7_0_100M_1.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/system_rst_ps7_0_100M_1.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>Processor Reset System</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_PERP_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_ARESETN" spirit:order="1800" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:order="1700" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_PERP_RST</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_RST" spirit:order="1600" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_BUS_RST</spirit:name>
|
||||
<spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_BUS_RST" spirit:order="1500" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_AUX_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Aux Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RESET_HIGH" spirit:order="1400" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_EXT_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Ext Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RESET_HIGH" spirit:order="1300" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_AUX_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Aux Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RST_WIDTH" spirit:order="1200" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_EXT_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Ext Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RST_WIDTH" spirit:order="1100" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">system_rst_ps7_0_100M_1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>USE_BOARD_FLOW</spirit:name>
|
||||
<spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="2">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>RESET_BOARD_INTERFACE</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="3">Custom</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>Processor System Reset</xilinx:displayName>
|
||||
<xilinx:coreRevision>14</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_PORT" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DBG_RESET.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="26169568"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="a1ed0379"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="f2ac9635"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="404de108"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="8319b917"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
#--------------------Physical Constraints-----------------
|
||||
|
||||
+57
@@ -0,0 +1,57 @@
|
||||
# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of AMD and is protected under U.S. and international copyright
|
||||
# and other intellectual property laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 10 -name slowest_sync_clk [get_ports slowest_sync_clk]
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,632 @@
|
||||
// (c) Copyright 2016, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
//
|
||||
// AXI VIP wrapper
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// axi_vip
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||
module axi_vip_v1_1_15_top #
|
||||
(
|
||||
parameter C_AXI_PROTOCOL = 0,
|
||||
parameter C_AXI_INTERFACE_MODE = 1, //master, slave and bypass
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
parameter integer C_AXI_WDATA_WIDTH = 32,
|
||||
parameter integer C_AXI_RDATA_WIDTH = 32,
|
||||
parameter integer C_AXI_WID_WIDTH = 0,
|
||||
parameter integer C_AXI_RID_WIDTH = 0,
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_ARUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_WUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_RUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_BUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_SUPPORTS_NARROW = 1,
|
||||
parameter integer C_AXI_HAS_BURST = 1,
|
||||
parameter integer C_AXI_HAS_LOCK = 1,
|
||||
parameter integer C_AXI_HAS_CACHE = 1,
|
||||
parameter integer C_AXI_HAS_REGION = 1,
|
||||
parameter integer C_AXI_HAS_PROT = 1,
|
||||
parameter integer C_AXI_HAS_QOS = 1,
|
||||
parameter integer C_AXI_HAS_WSTRB = 1,
|
||||
parameter integer C_AXI_HAS_BRESP = 1,
|
||||
parameter integer C_AXI_HAS_RRESP = 1,
|
||||
parameter integer C_AXI_HAS_ARESETN = 1
|
||||
)
|
||||
(
|
||||
//NOTE: C_AXI_INTERFACE_MODE =0 means MASTER MODE, 1 means PASS-THROUGH MODE and 2 means SLAVE MODE
|
||||
//Please refer xgui tcl and coreinfo.yml
|
||||
|
||||
// System Signals
|
||||
input wire aclk,
|
||||
input wire aclken,
|
||||
input wire aresetn,
|
||||
|
||||
// Slave Interface Write Address Ports
|
||||
input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_awid,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
|
||||
input wire [3-1:0] s_axi_awsize,
|
||||
input wire [2-1:0] s_axi_awburst,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
|
||||
input wire [4-1:0] s_axi_awcache,
|
||||
input wire [3-1:0] s_axi_awprot,
|
||||
input wire [4-1:0] s_axi_awregion,
|
||||
input wire [4-1:0] s_axi_awqos,
|
||||
input wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
|
||||
input wire s_axi_awvalid,
|
||||
output wire s_axi_awready,
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_wid,
|
||||
input wire [C_AXI_WDATA_WIDTH-1:0] s_axi_wdata,
|
||||
input wire [C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0] s_axi_wstrb,
|
||||
input wire s_axi_wlast,
|
||||
input wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
|
||||
input wire s_axi_wvalid,
|
||||
output wire s_axi_wready,
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_bid,
|
||||
output wire [2-1:0] s_axi_bresp,
|
||||
output wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
|
||||
output wire s_axi_bvalid,
|
||||
input wire s_axi_bready,
|
||||
|
||||
// Slave Interface Read Address Ports
|
||||
input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_arid,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
|
||||
input wire [3-1:0] s_axi_arsize,
|
||||
input wire [2-1:0] s_axi_arburst,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
|
||||
input wire [4-1:0] s_axi_arcache,
|
||||
input wire [3-1:0] s_axi_arprot,
|
||||
input wire [4-1:0] s_axi_arregion,
|
||||
input wire [4-1:0] s_axi_arqos,
|
||||
input wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
|
||||
input wire s_axi_arvalid,
|
||||
output wire s_axi_arready,
|
||||
|
||||
// Slave Interface Read Data Ports
|
||||
output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_rid,
|
||||
output wire [C_AXI_RDATA_WIDTH-1:0] s_axi_rdata,
|
||||
output wire [2-1:0] s_axi_rresp,
|
||||
output wire s_axi_rlast,
|
||||
output wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
|
||||
output wire s_axi_rvalid,
|
||||
input wire s_axi_rready,
|
||||
|
||||
// Master Interface Write Address Port
|
||||
output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_awid,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
|
||||
output wire [3-1:0] m_axi_awsize,
|
||||
output wire [2-1:0] m_axi_awburst,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
|
||||
output wire [4-1:0] m_axi_awcache,
|
||||
output wire [3-1:0] m_axi_awprot,
|
||||
output wire [4-1:0] m_axi_awregion,
|
||||
output wire [4-1:0] m_axi_awqos,
|
||||
output wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
|
||||
output wire m_axi_awvalid,
|
||||
input wire m_axi_awready,
|
||||
|
||||
// Master Interface Write Data Ports
|
||||
output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_wid,
|
||||
output wire [C_AXI_WDATA_WIDTH-1:0] m_axi_wdata,
|
||||
output wire [C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0] m_axi_wstrb,
|
||||
output wire m_axi_wlast,
|
||||
output wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
|
||||
output wire m_axi_wvalid,
|
||||
input wire m_axi_wready,
|
||||
|
||||
// Master Interface Write Response Ports
|
||||
input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_bid,
|
||||
input wire [2-1:0] m_axi_bresp,
|
||||
input wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
|
||||
input wire m_axi_bvalid,
|
||||
output wire m_axi_bready,
|
||||
|
||||
// Master Interface Read Address Port
|
||||
output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_arid,
|
||||
output wire [ C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
|
||||
output wire [3-1:0] m_axi_arsize,
|
||||
output wire [2-1:0] m_axi_arburst,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
|
||||
output wire [4-1:0] m_axi_arcache,
|
||||
output wire [3-1:0] m_axi_arprot,
|
||||
output wire [4-1:0] m_axi_arregion,
|
||||
output wire [4-1:0] m_axi_arqos,
|
||||
output wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
|
||||
output wire m_axi_arvalid,
|
||||
input wire m_axi_arready,
|
||||
|
||||
// Master Interface Read Data Ports
|
||||
input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_rid,
|
||||
input wire [C_AXI_RDATA_WIDTH-1:0] m_axi_rdata,
|
||||
input wire [2-1:0] m_axi_rresp,
|
||||
input wire m_axi_rlast,
|
||||
input wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
|
||||
input wire m_axi_rvalid,
|
||||
output wire m_axi_rready
|
||||
);
|
||||
|
||||
/**********************************************************************************************
|
||||
* NOTE:
|
||||
* C_AXI_INTERFACE_MODE =0 -- MASTER MODE,
|
||||
* C_AXI_INTERFACE_MODE =1 -- PASS-THROUGH MODE
|
||||
* C_AXI_INTERFACE_MODE =2 -- SLAVE MODE
|
||||
* Please refer xgui tcl and coreinfo.yml
|
||||
* User can change PASS_THROUGH VIP to run time master mode or run time slave mode during
|
||||
* the simulation
|
||||
*********************************************************************************************/
|
||||
|
||||
/**********************************************************************************************
|
||||
* Master_mode means that either the dut is statically being configured to be in master mode
|
||||
* or it statically being configured to be pass-through mode and switched to be in master mode
|
||||
* in run time.
|
||||
|
||||
* Slave mode means that either the dut is statically being configured to be in slave mode
|
||||
* or it statically being configured to be pass-through mode and switched to be in slave mode
|
||||
* in run time.
|
||||
|
||||
* Pass-through mode means that either the dut is statically being configured to be in
|
||||
* pass-through mode or it statically being configured to be pass-through mode and switched
|
||||
* to be in master/slave mode and then switch back to be in pass-through mode in run time
|
||||
*********************************************************************************************/
|
||||
|
||||
logic runtime_master =0;
|
||||
logic runtime_slave =0;
|
||||
|
||||
wire run_slave_mode;
|
||||
wire run_master_mode;
|
||||
wire run_passth_mode;
|
||||
wire compile_master_mode;
|
||||
wire compile_slave_mode;
|
||||
wire master_mode;
|
||||
wire slave_mode;
|
||||
|
||||
assign run_master_mode = (C_AXI_INTERFACE_MODE ==1 && runtime_master ==1 &&runtime_slave ==0);
|
||||
assign run_slave_mode = C_AXI_INTERFACE_MODE ==1 && runtime_slave ==1 && runtime_master ==0;
|
||||
assign run_passth_mode = (runtime_slave ==0 && runtime_master ==0);
|
||||
|
||||
assign compile_master_mode = (C_AXI_INTERFACE_MODE ==0 || C_AXI_INTERFACE_MODE ==1 )&& run_passth_mode ;
|
||||
assign compile_slave_mode = (C_AXI_INTERFACE_MODE ==2 || C_AXI_INTERFACE_MODE ==1) && run_passth_mode ;
|
||||
|
||||
assign master_mode = compile_master_mode || run_master_mode;
|
||||
assign slave_mode = compile_slave_mode || run_slave_mode;
|
||||
|
||||
// Slave Interface Write Address Ports Internal
|
||||
assign IF.AWID = slave_mode? s_axi_awid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
|
||||
assign IF.AWADDR = slave_mode? s_axi_awaddr : {C_AXI_ADDR_WIDTH{1'bz}};
|
||||
assign IF.AWLEN = slave_mode? s_axi_awlen : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}};
|
||||
assign IF.AWSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_awsize): {3{1'bz}};
|
||||
assign IF.AWBURST = slave_mode? s_axi_awburst : {2{1'bz}};
|
||||
assign IF.AWLOCK = slave_mode? s_axi_awlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}};
|
||||
assign IF.AWCACHE = slave_mode? s_axi_awcache : {4{1'bz}};
|
||||
assign IF.AWPROT = slave_mode? s_axi_awprot : {3{1'bz}};
|
||||
assign IF.AWREGION = slave_mode? s_axi_awregion : {4{1'bz}};
|
||||
assign IF.AWQOS = slave_mode? s_axi_awqos : {4{1'bz}};
|
||||
assign IF.AWUSER = slave_mode? s_axi_awuser : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'bz}};
|
||||
assign IF.AWVALID = slave_mode? s_axi_awvalid : {1'bz};
|
||||
assign s_axi_awready = slave_mode? IF.AWREADY : {1'b0};
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
assign IF.WID = slave_mode? s_axi_wid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
|
||||
assign IF.WDATA = slave_mode? s_axi_wdata : {C_AXI_WDATA_WIDTH{1'bz}};
|
||||
assign IF.WSTRB = slave_mode? s_axi_wstrb : {(C_AXI_WDATA_WIDTH/8){1'bz}};
|
||||
assign IF.WLAST = slave_mode? s_axi_wlast: {1'bz};
|
||||
assign IF.WUSER = slave_mode? s_axi_wuser : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'bz}};
|
||||
assign IF.WVALID = slave_mode? s_axi_wvalid : {1'bz};
|
||||
assign s_axi_wready = slave_mode? IF.WREADY : {1'b0};
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
assign s_axi_bid = slave_mode? IF.BID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
|
||||
assign s_axi_bresp = slave_mode? IF.BRESP : {2{1'b0}};
|
||||
assign s_axi_buser = slave_mode? IF.BUSER : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'b0}};
|
||||
assign s_axi_bvalid = slave_mode? IF.BVALID : {1{1'b0}};
|
||||
assign IF.BREADY = slave_mode? s_axi_bready :{1{1'bz}};
|
||||
|
||||
// Slave Interface Read Address Ports
|
||||
assign IF.ARID = slave_mode? s_axi_arid :{C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}};
|
||||
assign IF.ARADDR = slave_mode? s_axi_araddr : {C_AXI_ADDR_WIDTH{1'bz}} ;
|
||||
assign IF.ARLEN = slave_mode? s_axi_arlen: {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}};
|
||||
assign IF.ARSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_arsize) : {3{1'bz}};
|
||||
assign IF.ARBURST = slave_mode? s_axi_arburst : {2{1'bz}};
|
||||
assign IF.ARLOCK = slave_mode? s_axi_arlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}};
|
||||
assign IF.ARCACHE = slave_mode? s_axi_arcache : {4{1'bz}};
|
||||
assign IF.ARPROT = slave_mode? s_axi_arprot : {3{1'bz}};
|
||||
assign IF.ARREGION = slave_mode? s_axi_arregion :{4{1'bz}} ;
|
||||
assign IF.ARQOS = slave_mode? s_axi_arqos : {4{1'bz}};
|
||||
assign IF.ARUSER = slave_mode? s_axi_aruser :{C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'bz}};
|
||||
assign IF.ARVALID = slave_mode? s_axi_arvalid : {1'bz};
|
||||
assign s_axi_arready = slave_mode? IF.ARREADY : {1'b0};
|
||||
|
||||
//Slave Interface Read Data Ports
|
||||
assign s_axi_rid = slave_mode? IF.RID: {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}};
|
||||
assign s_axi_rdata = slave_mode? IF.RDATA : {C_AXI_RDATA_WIDTH{1'b0}};
|
||||
assign s_axi_rresp = slave_mode? IF.RRESP : {2{1'b0}};
|
||||
assign s_axi_rlast = slave_mode? IF.RLAST : {{1'b0}};
|
||||
assign s_axi_ruser = slave_mode? IF.RUSER : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'b0}};
|
||||
assign s_axi_rvalid = slave_mode? IF.RVALID : {{1'b0}};
|
||||
assign IF.RREADY = slave_mode? s_axi_rready:{{1'bz}};
|
||||
|
||||
// Master Interface Write Address Port
|
||||
assign m_axi_awid = master_mode? IF.AWID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
|
||||
assign m_axi_awaddr = master_mode? IF.AWADDR : {C_AXI_ADDR_WIDTH{1'b0}};
|
||||
assign m_axi_awlen = master_mode? IF.AWLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}};
|
||||
assign m_axi_awsize = master_mode? IF.AWSIZE : {3{1'b0}};
|
||||
assign m_axi_awburst = master_mode? IF.AWBURST : {2{1'b0}};
|
||||
assign m_axi_awlock = master_mode? IF.AWLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}};
|
||||
assign m_axi_awcache = master_mode? IF.AWCACHE : {4{1'b0}};
|
||||
assign m_axi_awprot = master_mode? IF.AWPROT : {3{1'b0}};
|
||||
assign m_axi_awregion = master_mode? IF.AWREGION : {4{1'b0}};
|
||||
assign m_axi_awqos = master_mode? IF.AWQOS : {4{1'b0}};
|
||||
assign m_axi_awuser = master_mode? IF.AWUSER : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'b0}};
|
||||
assign m_axi_awvalid = master_mode? IF.AWVALID :{1'b0};
|
||||
assign IF.AWREADY = master_mode? m_axi_awready :{1'bz};
|
||||
|
||||
// Master Interface Write Data Ports Internal
|
||||
assign m_axi_wid = master_mode? IF.WID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
|
||||
assign m_axi_wdata = master_mode? IF.WDATA : {C_AXI_WDATA_WIDTH{1'b0}};
|
||||
assign m_axi_wstrb = master_mode? IF.WSTRB : {(C_AXI_WDATA_WIDTH/8){1'b0}};
|
||||
assign m_axi_wlast = master_mode? IF.WLAST : {1'b0};
|
||||
assign m_axi_wuser = master_mode? IF.WUSER : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'b0}};
|
||||
assign m_axi_wvalid = master_mode? IF.WVALID : {1'b0};
|
||||
assign IF.WREADY = master_mode? m_axi_wready : {1'bz};
|
||||
|
||||
// Master Interface Write Response Ports Internal
|
||||
assign IF.BID = master_mode? m_axi_bid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
|
||||
assign IF.BRESP = master_mode? m_axi_bresp : {2{1'bz}};
|
||||
assign IF.BUSER = master_mode? m_axi_buser : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'bz}};
|
||||
assign IF.BVALID = master_mode? m_axi_bvalid : 1'bz;
|
||||
assign m_axi_bready = master_mode? IF.BREADY : 1'b0;
|
||||
|
||||
// Master Interface Read Address Port Internal
|
||||
assign m_axi_arid = master_mode? IF.ARID : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}};
|
||||
assign m_axi_araddr = master_mode? IF.ARADDR : {C_AXI_ADDR_WIDTH{1'b0}};
|
||||
assign m_axi_arlen = master_mode? IF.ARLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}};
|
||||
assign m_axi_arsize = master_mode? IF.ARSIZE : {3{1'b0}};
|
||||
assign m_axi_arburst = master_mode? IF.ARBURST : {2{1'b0}};
|
||||
assign m_axi_arlock = master_mode? IF.ARLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}};
|
||||
assign m_axi_arcache = master_mode?IF.ARCACHE : {4{1'b0}};
|
||||
assign m_axi_arprot = master_mode? IF.ARPROT : {3{1'b0}};
|
||||
assign m_axi_arregion = master_mode? IF.ARREGION : {4{1'b0}};
|
||||
assign m_axi_arqos = master_mode? IF.ARQOS : {4{1'b0}};
|
||||
assign m_axi_aruser = master_mode? IF.ARUSER : {C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'b0}};
|
||||
assign m_axi_arvalid = master_mode? IF.ARVALID :{1'b0};
|
||||
assign IF.ARREADY = master_mode? m_axi_arready : {1{1'bz}};
|
||||
|
||||
// Master Interface Read Data Ports Internal
|
||||
assign IF.RID = master_mode? m_axi_rid : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}};
|
||||
assign IF.RDATA = master_mode? m_axi_rdata : {C_AXI_RDATA_WIDTH{1'bz}};
|
||||
assign IF.RRESP = master_mode? m_axi_rresp : {2{1'bz}};
|
||||
assign IF.RLAST = master_mode? m_axi_rlast : {1{1'bz}};
|
||||
assign IF.RUSER = master_mode? m_axi_ruser : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'bz}};
|
||||
assign IF.RVALID = master_mode? m_axi_rvalid : {1{1'bz}};
|
||||
assign m_axi_rready = master_mode? IF.RREADY : {1{1'b0}};
|
||||
|
||||
axi_vip_if #(
|
||||
.C_AXI_PROTOCOL(C_AXI_PROTOCOL),
|
||||
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH ),
|
||||
.C_AXI_WDATA_WIDTH(C_AXI_WDATA_WIDTH ),
|
||||
.C_AXI_RDATA_WIDTH(C_AXI_RDATA_WIDTH ),
|
||||
.C_AXI_WID_WIDTH(C_AXI_WID_WIDTH ),
|
||||
.C_AXI_RID_WIDTH(C_AXI_RID_WIDTH ),
|
||||
.C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH ),
|
||||
.C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH ),
|
||||
.C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH ),
|
||||
.C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH ),
|
||||
.C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH ),
|
||||
.C_AXI_SUPPORTS_NARROW(C_AXI_SUPPORTS_NARROW),
|
||||
.C_AXI_HAS_BURST(C_AXI_HAS_BURST),
|
||||
.C_AXI_HAS_LOCK(C_AXI_HAS_LOCK),
|
||||
.C_AXI_HAS_CACHE(C_AXI_HAS_CACHE),
|
||||
.C_AXI_HAS_REGION(C_AXI_HAS_REGION),
|
||||
.C_AXI_HAS_PROT(C_AXI_HAS_PROT),
|
||||
.C_AXI_HAS_QOS(C_AXI_HAS_QOS),
|
||||
.C_AXI_HAS_WSTRB(C_AXI_HAS_WSTRB),
|
||||
.C_AXI_HAS_BRESP(C_AXI_HAS_BRESP),
|
||||
.C_AXI_HAS_RRESP(C_AXI_HAS_RRESP),
|
||||
.C_AXI_HAS_ARESETN(C_AXI_HAS_ARESETN)
|
||||
) IF (
|
||||
.ACLK(aclk),
|
||||
.ARESET_N(aresetn),
|
||||
.ACLKEN(aclken)
|
||||
);
|
||||
|
||||
|
||||
//synthesis translate_off
|
||||
initial begin
|
||||
$display("XilinxAXIVIP: Found at Path: %m");
|
||||
end
|
||||
|
||||
//set IF mode to be in the correct mode according to C_AXI_INTERFACE_MODE,Default is monitor mode
|
||||
generate
|
||||
initial begin
|
||||
if(C_AXI_INTERFACE_MODE ==0) begin
|
||||
IF.set_intf_master;
|
||||
end else if(C_AXI_INTERFACE_MODE ==2) begin
|
||||
IF.set_intf_slave;
|
||||
end else if(C_AXI_INTERFACE_MODE ==1) begin
|
||||
$display("This AXI VIP is in passthrough mode");
|
||||
end else begin
|
||||
$fatal(0,"This AXI VIP's mode is out of range");
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
/*
|
||||
Function: set_passthrough_mode
|
||||
Sets AXI VIP passthrough into run time passthrough mode
|
||||
*/
|
||||
function void set_passthrough_mode();
|
||||
if (C_AXI_INTERFACE_MODE == 1) begin
|
||||
runtime_master = 0;
|
||||
runtime_slave = 0;
|
||||
IF.set_intf_monitor();
|
||||
end else begin
|
||||
$fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_passthrough_mode in the testbench. Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP");
|
||||
end
|
||||
endfunction: set_passthrough_mode
|
||||
|
||||
/*
|
||||
Function: set_master_mode
|
||||
Sets AXI VIP passthrough into run time master mode
|
||||
*/
|
||||
function void set_master_mode();
|
||||
if (C_AXI_INTERFACE_MODE == 1) begin
|
||||
runtime_master = 1;
|
||||
runtime_slave = 0;
|
||||
IF.set_intf_master();
|
||||
end else begin
|
||||
$fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_master_mode in the testbench .Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP ");
|
||||
end
|
||||
endfunction : set_master_mode
|
||||
|
||||
/*
|
||||
Function: set_slave_mode
|
||||
Sets AXI VIP passthrough into run time slave mode
|
||||
*/
|
||||
function void set_slave_mode();
|
||||
if (C_AXI_INTERFACE_MODE == 1) begin
|
||||
runtime_master = 0;
|
||||
runtime_slave = 1;
|
||||
IF.set_intf_slave();
|
||||
end else begin
|
||||
$fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_slave_mode in the testbench.Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP");
|
||||
end
|
||||
endfunction : set_slave_mode
|
||||
|
||||
/*
|
||||
Function: set_xilinx_slave_ready_check
|
||||
Sets xilinx_slave_ready_check_enable of IF to be 1
|
||||
*/
|
||||
function void set_xilinx_slave_ready_check();
|
||||
IF.xilinx_slave_ready_check_enable = 1;
|
||||
endfunction
|
||||
|
||||
/*
|
||||
Function: clr_xilinx_slave_ready_check
|
||||
Sets xilinx_slave_ready_check_enable of IF to be 0
|
||||
*/
|
||||
function void clr_xilinx_slave_ready_check();
|
||||
IF.xilinx_slave_ready_check_enable = 0;
|
||||
endfunction
|
||||
|
||||
/*
|
||||
Function: set_max_aw_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_aw_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_aw_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_aw_wait_cycles = new_num;
|
||||
endfunction : set_max_aw_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_ar_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_ar_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_ar_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_ar_wait_cycles = new_num;
|
||||
endfunction : set_max_ar_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_r_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_r_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_r_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_r_wait_cycles = new_num;
|
||||
endfunction : set_max_r_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_b_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_b_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_b_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_b_wait_cycles = new_num;
|
||||
endfunction : set_max_b_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_w_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_w_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_w_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_w_wait_cycles = new_num;
|
||||
endfunction : set_max_w_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_wlast_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_wlast_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_wlast_to_awvalid_wait_cycles = new_num;
|
||||
endfunction : set_max_wlast_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_rtransfer_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_rtransfer_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_rtransfers_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_rtransfers_wait_cycles = new_num;
|
||||
endfunction : set_max_rtransfers_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_wtransfer_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_wtransfer_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_wtransfers_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_wtransfers_wait_cycles = new_num;
|
||||
endfunction : set_max_wtransfers_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_wlcmd_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_wlcmd_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_wlcmd_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_wlcmd_wait_cycles = new_num;
|
||||
endfunction : set_max_wlcmd_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_aw_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_aw_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_aw_wait_cycles();
|
||||
return(IF.PC.max_aw_wait_cycles);
|
||||
endfunction : get_max_aw_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_ar_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_ar_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_ar_wait_cycles();
|
||||
return(IF.PC.max_ar_wait_cycles);
|
||||
endfunction : get_max_ar_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_r_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_r_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_r_wait_cycles();
|
||||
return(IF.PC.max_r_wait_cycles);
|
||||
endfunction : get_max_r_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_b_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_b_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_b_wait_cycles();
|
||||
return(IF.PC.max_b_wait_cycles);
|
||||
endfunction : get_max_b_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_w_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_w_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_w_wait_cycles();
|
||||
return(IF.PC.max_w_wait_cycles);
|
||||
endfunction :get_max_w_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_wlast_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_wlast_wait_cycles();
|
||||
return(IF.PC.max_wlast_to_awvalid_wait_cycles);
|
||||
endfunction :get_max_wlast_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_rtransfer_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_rtransfer_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_rtransfers_wait_cycles();
|
||||
return(IF.PC.max_rtransfers_wait_cycles);
|
||||
endfunction :get_max_rtransfers_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_wtransfer_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_wtransfer_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_wtransfers_wait_cycles();
|
||||
return(IF.PC.max_wtransfers_wait_cycles);
|
||||
endfunction :get_max_wtransfers_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_wlcmd_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_wlcmd_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_wlcmd_wait_cycles();
|
||||
return(IF.PC.max_wlcmd_wait_cycles);
|
||||
endfunction :get_max_wlcmd_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_fatal_to_warnings (not available in VIVADO Simulator)
|
||||
Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 1
|
||||
*/
|
||||
function void set_fatal_to_warnings();
|
||||
IF.PC.fatal_to_warnings = 1;
|
||||
endfunction : set_fatal_to_warnings
|
||||
|
||||
/*
|
||||
Function: clr_fatal_to_warnings (not available in VIVADO Simulator)
|
||||
Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 0
|
||||
*/
|
||||
function void clr_fatal_to_warnings();
|
||||
IF.PC.fatal_to_warnings = 0;
|
||||
endfunction : clr_fatal_to_warnings
|
||||
//synthesis translate_on
|
||||
|
||||
endmodule // axi_vip_v1_1_15_top
|
||||
|
||||
|
||||
+867
@@ -0,0 +1,867 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_17_apis.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Set of Zynq VIP APIs that are used for writing tests.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* API for setting the STOP_ON_ERROR*/
|
||||
task automatic set_stop_on_error;
|
||||
input LEVEL;
|
||||
begin
|
||||
$display("[%0d] : %0s : Setting Stop On Error as %0b",$time, DISP_INFO, LEVEL);
|
||||
STOP_ON_ERROR = LEVEL;
|
||||
// M_AXI_GP0.master.set_stop_on_error(LEVEL);
|
||||
// M_AXI_GP1.master.set_stop_on_error(LEVEL);
|
||||
// S_AXI_GP0.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_GP1.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_HP0.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_HP1.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_HP2.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_HP3.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_ACP.slave.set_stop_on_error(LEVEL);
|
||||
M_AXI_GP0.STOP_ON_ERROR = LEVEL;
|
||||
M_AXI_GP1.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_GP0.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_GP1.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_HP0.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_HP1.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_HP2.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_HP3.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_ACP.STOP_ON_ERROR = LEVEL;
|
||||
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for setting the verbosity for channel level info*/
|
||||
task automatic set_channel_level_info;
|
||||
input [1023:0] name;
|
||||
input LEVEL;
|
||||
begin
|
||||
$display("[%0d] : [%0s] : %0s Port/s : Setting Channel Level Info as %0b",$time, DISP_INFO, name , LEVEL);
|
||||
case(name)
|
||||
// "M_AXI_GP0" : M_AXI_GP0.master.set_channel_level_info(LEVEL);
|
||||
// "M_AXI_GP1" : M_AXI_GP1.master.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_GP0" : S_AXI_GP0.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_GP1" : S_AXI_GP1.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_HP0" : S_AXI_HP0.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_HP1" : S_AXI_HP1.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_HP2" : S_AXI_HP2.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_HP3" : S_AXI_HP3.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_ACP" : S_AXI_ACP.slave.set_channel_level_info(LEVEL);
|
||||
"ALL" : begin
|
||||
// M_AXI_GP0.master.set_channel_level_info(LEVEL);
|
||||
// M_AXI_GP1.master.set_channel_level_info(LEVEL);
|
||||
// S_AXI_GP0.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_GP1.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_HP0.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_HP1.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_HP2.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_HP3.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_ACP.slave.set_channel_level_info(LEVEL);
|
||||
end
|
||||
default : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name);
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for setting the verbosity for function level info*/
|
||||
task automatic set_function_level_info;
|
||||
input [1023:0] name;
|
||||
input LEVEL;
|
||||
begin
|
||||
$display("[%0d] : [%0s] : %0s Port/s : Setting Function Level Info as %0b",$time, DISP_INFO, name , LEVEL);
|
||||
case(name)
|
||||
// "M_AXI_GP0" : M_AXI_GP0.master.set_function_level_info(LEVEL);
|
||||
// "M_AXI_GP1" : M_AXI_GP1.master.set_function_level_info(LEVEL);
|
||||
// "S_AXI_GP0" : S_AXI_GP0.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_GP1" : S_AXI_GP1.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_HP0" : S_AXI_HP0.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_HP1" : S_AXI_HP1.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_HP2" : S_AXI_HP2.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_HP3" : S_AXI_HP3.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_ACP" : S_AXI_ACP.slave.set_function_level_info(LEVEL);
|
||||
"ALL" : begin
|
||||
// M_AXI_GP0.master.set_function_level_info(LEVEL);
|
||||
// M_AXI_GP1.master.set_function_level_info(LEVEL);
|
||||
// S_AXI_GP0.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_GP1.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_HP0.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_HP1.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_HP2.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_HP3.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_ACP.slave.set_function_level_info(LEVEL);
|
||||
end
|
||||
default : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name);
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for setting the Message verbosity */
|
||||
task automatic set_debug_level_info;
|
||||
input LEVEL;
|
||||
begin
|
||||
$display("[%0d] : %0s : Setting Debug Level Info as %0b",$time, DISP_INFO, LEVEL);
|
||||
DEBUG_INFO = LEVEL;
|
||||
M_AXI_GP0.DEBUG_INFO = LEVEL;
|
||||
M_AXI_GP1.DEBUG_INFO = LEVEL;
|
||||
S_AXI_GP0.DEBUG_INFO = LEVEL;
|
||||
S_AXI_GP1.DEBUG_INFO = LEVEL;
|
||||
S_AXI_HP0.DEBUG_INFO = LEVEL;
|
||||
S_AXI_HP1.DEBUG_INFO = LEVEL;
|
||||
S_AXI_HP2.DEBUG_INFO = LEVEL;
|
||||
S_AXI_HP3.DEBUG_INFO = LEVEL;
|
||||
S_AXI_ACP.DEBUG_INFO = LEVEL;
|
||||
|
||||
ddrc.ddr.DEBUG_INFO = LEVEL;
|
||||
ddrc.ddr_write_ports.DEBUG_INFO = LEVEL;
|
||||
ddrc.ddr_read_ports.DEBUG_INFO = LEVEL;
|
||||
|
||||
ocmc.ocm_write_ports.DEBUG_INFO = LEVEL;
|
||||
ocmc.ocm_read_ports.DEBUG_INFO = LEVEL;
|
||||
|
||||
icm.ssw.ocm_wr_hp.DEBUG_INFO = LEVEL;
|
||||
icm.ssw.ocm_rd_hp.DEBUG_INFO = LEVEL;
|
||||
icm.ssw.ddr_hp01.ddr_hp_wr.DEBUG_INFO = LEVEL;
|
||||
icm.ssw.ddr_hp01.ddr_hp_rd.DEBUG_INFO = LEVEL;
|
||||
icm.ssw.ddr_hp23.ddr_hp_wr.DEBUG_INFO = LEVEL;
|
||||
icm.ssw.ddr_hp23.ddr_hp_rd.DEBUG_INFO = LEVEL;
|
||||
|
||||
icm.fmsw.ocm_gp_wr.DEBUG_INFO = LEVEL;
|
||||
icm.fmsw.ddr_gp_wr.DEBUG_INFO = LEVEL;
|
||||
icm.fmsw.ocm_gp_rd.DEBUG_INFO = LEVEL;
|
||||
icm.fmsw.ddr_gp_rd.DEBUG_INFO = LEVEL;
|
||||
icm.fmsw.reg_gp_rd.DEBUG_INFO = LEVEL;
|
||||
|
||||
icm.osw_wr.DEBUG_INFO = LEVEL;
|
||||
icm.osw_rd.DEBUG_INFO = LEVEL;
|
||||
|
||||
regc.reg_read_ports.DEBUG_INFO = LEVEL;
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for setting ARQos Values */
|
||||
task automatic set_arqos;
|
||||
input [1023:0] name;
|
||||
input [axi_qos_width-1:0] value;
|
||||
begin
|
||||
$display("[%0d] : [%0s] : %0s Port/s : Setting AWQOS as %0b",$time, DISP_INFO, name , value);
|
||||
case(name)
|
||||
"S_AXI_GP0" : S_AXI_GP0.set_arqos(value);
|
||||
"S_AXI_GP1" : S_AXI_GP1.set_arqos(value);
|
||||
"S_AXI_HP0" : S_AXI_HP0.set_arqos(value);
|
||||
"S_AXI_HP1" : S_AXI_HP1.set_arqos(value);
|
||||
"S_AXI_HP2" : S_AXI_HP2.set_arqos(value);
|
||||
"S_AXI_HP3" : S_AXI_HP3.set_arqos(value);
|
||||
"S_AXI_ACP" : S_AXI_ACP.set_arqos(value);
|
||||
default : $display("[%0d] : %0s : Invalid Slave Port name (%0s)",$time, DISP_ERR, name);
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for setting AWQos Values */
|
||||
task automatic set_awqos;
|
||||
input [1023:0] name;
|
||||
input [axi_qos_width-1:0] value;
|
||||
begin
|
||||
$display("[%0d] : [%0s] : %0s Port/s : Setting ARQOS as %0b",$time, DISP_INFO, name , value);
|
||||
case(name)
|
||||
"S_AXI_GP0" : S_AXI_GP0.set_awqos(value);
|
||||
"S_AXI_GP1" : S_AXI_GP1.set_awqos(value);
|
||||
"S_AXI_HP0" : S_AXI_HP0.set_awqos(value);
|
||||
"S_AXI_HP1" : S_AXI_HP1.set_awqos(value);
|
||||
"S_AXI_HP2" : S_AXI_HP2.set_awqos(value);
|
||||
"S_AXI_HP3" : S_AXI_HP3.set_awqos(value);
|
||||
"S_AXI_ACP" : S_AXI_ACP.set_awqos(value);
|
||||
default : $display("[%0d] : %0s : Invalid Slave Port (%0s)",$time, DISP_ERR, name);
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for soft reset control */
|
||||
task automatic fpga_soft_reset;
|
||||
input[data_width-1:0] reset_ctrl;
|
||||
begin
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : FPGA Soft Reset called for 0x%0h",$time, DISP_INFO, reset_ctrl);
|
||||
gen_rst.fpga_soft_reset(reset_ctrl);
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for por and strb reset control */
|
||||
// task automatic por_srstb_reset;
|
||||
// input por_reset_ctrl;
|
||||
// begin
|
||||
// if(DEBUG_INFO) $display("[%0d] : %0s : POR and STRB Reset called for 0x%0h",$time, DISP_INFO, por_reset_ctrl);
|
||||
// // gen_rst.por_srstb_reset(por_reset_ctrl);
|
||||
// gen_rst.por_srstb_reset(por_reset_ctrl);
|
||||
//
|
||||
// end
|
||||
// endtask
|
||||
|
||||
/* API for pre-loading memories from (DDR/OCM model) */
|
||||
task automatic pre_load_mem_from_file;
|
||||
input [(max_chars*8)-1:0] file_name;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [int_width-1:0] no_of_bytes;
|
||||
reg [1:0] mem_type;
|
||||
integer succ;
|
||||
begin
|
||||
mem_type = decode_address(start_addr);
|
||||
succ = $fopen(file_name,"r");
|
||||
if(succ == 0) begin
|
||||
$display("[%0d] : %0s : '%0s' doesn't exist. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR, file_name);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
else if(check_addr_aligned(start_addr)) begin
|
||||
case(mem_type)
|
||||
OCM_MEM : begin
|
||||
if (!C_HIGH_OCM_EN)
|
||||
ocmc.ocm.pre_load_mem_from_file(file_name,start_addr,no_of_bytes);
|
||||
else
|
||||
ocmc.ocm.pre_load_mem_from_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
|
||||
end
|
||||
DDR_MEM : begin
|
||||
ddrc.ddr.pre_load_mem_from_file(file_name,start_addr,no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
|
||||
end
|
||||
default : begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem_from_file' call failed ...",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR)
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for pre-loading memories (DDR/OCM) */
|
||||
task automatic pre_load_mem;
|
||||
input [1:0] data_type;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [int_width-1:0] no_of_bytes;
|
||||
reg [1:0] mem_type;
|
||||
begin
|
||||
mem_type = decode_address(start_addr);
|
||||
if(check_addr_aligned(start_addr)) begin
|
||||
case(mem_type)
|
||||
OCM_MEM : begin
|
||||
if (!C_HIGH_OCM_EN)
|
||||
ocmc.ocm.pre_load_mem(data_type,start_addr,no_of_bytes);
|
||||
else
|
||||
ocmc.ocm.pre_load_mem(data_type,(start_addr - high_ocm_start_addr),no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
DDR_MEM : begin
|
||||
ddrc.ddr.pre_load_mem(data_type,start_addr,no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
default : begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem' call failed ...",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for backdoor write to memories (DDR/OCM) */
|
||||
task automatic write_mem;
|
||||
input [max_burst_bits-1 :0] data;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [max_burst_bytes_width:0] no_of_bytes;
|
||||
reg [1:0] mem_type;
|
||||
integer succ;
|
||||
begin
|
||||
mem_type = decode_address(start_addr);
|
||||
if(check_addr_aligned(start_addr)) begin
|
||||
case(mem_type)
|
||||
OCM_MEM : begin
|
||||
if (!C_HIGH_OCM_EN)
|
||||
ocmc.ocm.write_mem(data,start_addr,no_of_bytes,all_strb_valid);
|
||||
else
|
||||
ocmc.ocm.write_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes,all_strb_valid);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to OCM Memory",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
DDR_MEM : begin
|
||||
ddrc.ddr.write_mem(data,start_addr,no_of_bytes,all_strb_valid);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to DDR Memory",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
default : begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'write_mem' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_mem' call failed ...",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR)
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* read_memory */
|
||||
task automatic read_mem;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [max_burst_bytes_width :0] no_of_bytes;
|
||||
output[max_burst_bits-1 :0] data;
|
||||
reg [1:0] mem_type;
|
||||
integer succ;
|
||||
begin
|
||||
mem_type = decode_address(start_addr);
|
||||
if(check_addr_aligned(start_addr)) begin
|
||||
case(mem_type)
|
||||
OCM_MEM : begin
|
||||
if (!C_HIGH_OCM_EN)
|
||||
ocmc.ocm.read_mem(data,start_addr,no_of_bytes);
|
||||
else
|
||||
ocmc.ocm.read_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from OCM Memory ",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
DDR_MEM : begin
|
||||
ddrc.ddr.read_mem(data,start_addr,no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from DDR Memory",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
default : begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'read_mem' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_mem' call failed ...",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR)
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for backdoor read to memories (DDR/OCM) */
|
||||
task automatic peek_mem_to_file;
|
||||
input [(max_chars*8)-1:0] file_name;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [int_width-1:0] no_of_bytes;
|
||||
reg [1:0] mem_type;
|
||||
integer succ;
|
||||
begin
|
||||
mem_type = decode_address(start_addr);
|
||||
if(check_addr_aligned(start_addr)) begin
|
||||
case(mem_type)
|
||||
OCM_MEM : begin
|
||||
if (!C_HIGH_OCM_EN)
|
||||
ocmc.ocm.peek_mem_to_file(file_name,start_addr,no_of_bytes);
|
||||
else
|
||||
ocmc.ocm.peek_mem_to_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from OCM Memory to file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
|
||||
end
|
||||
DDR_MEM : begin
|
||||
ddrc.ddr.peek_mem_to_file(file_name,start_addr,no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from DDR Memory to file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
|
||||
end
|
||||
default : begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'peek_mem_to_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'peek_mem_to_file' call failed ...",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR)
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to read interrupt status */
|
||||
task automatic read_interrupt;
|
||||
output[irq_width-1:0] irq_status;
|
||||
begin
|
||||
irq_status = IRQ_F2P;
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : Reading Interrupt Status as 0x%0h",$time, DISP_INFO, irq_status);
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to wait on interrup */
|
||||
task automatic wait_interrupt;
|
||||
input [3:0] irq;
|
||||
output[irq_width-1:0] irq_status;
|
||||
begin
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : Waiting on Interrupt irq[%0d]",$time, DISP_INFO, irq);
|
||||
|
||||
case(irq)
|
||||
0 : wait(IRQ_F2P[0] === 1'b1);
|
||||
1 : wait(IRQ_F2P[1] === 1'b1);
|
||||
2 : wait(IRQ_F2P[2] === 1'b1);
|
||||
3 : wait(IRQ_F2P[3] === 1'b1);
|
||||
4 : wait(IRQ_F2P[4] === 1'b1);
|
||||
5 : wait(IRQ_F2P[5] === 1'b1);
|
||||
6 : wait(IRQ_F2P[6] === 1'b1);
|
||||
7 : wait(IRQ_F2P[7] === 1'b1);
|
||||
8 : wait(IRQ_F2P[8] === 1'b1);
|
||||
9 : wait(IRQ_F2P[9] === 1'b1);
|
||||
10: wait(IRQ_F2P[10] === 1'b1);
|
||||
11: wait(IRQ_F2P[11] === 1'b1);
|
||||
12: wait(IRQ_F2P[12] === 1'b1);
|
||||
13: wait(IRQ_F2P[13] === 1'b1);
|
||||
14: wait(IRQ_F2P[14] === 1'b1);
|
||||
15: wait(IRQ_F2P[15] === 1'b1);
|
||||
default : $display("[%0d] : %0s : Only 16 Interrupt lines (irq_fp0:irq_fp15) are supported",$time, DISP_ERR);
|
||||
endcase
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : Received Interrupt irq[%0d]",$time, DISP_INFO, irq);
|
||||
irq_status = IRQ_F2P;
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to wait for a certain match pattern*/
|
||||
task automatic wait_mem_update;
|
||||
input[addr_width-1:0] address;
|
||||
input[data_width-1:0] data_in;
|
||||
output[data_width-1:0] data_out;
|
||||
reg[data_width-1:0] datao;
|
||||
begin
|
||||
if(mem_update_key) begin
|
||||
mem_update_key = 0;
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : 'wait_mem_update' called for Address(0x%0h) , Match Pattern(0x%0h) \n",$time, DISP_INFO, address, data_in);
|
||||
if(check_addr_aligned(address)) begin
|
||||
ddrc.ddr.wait_mem_update(address, datao);
|
||||
if(datao != data_in)begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN MATCH FAILED, Expected data = 0x%0h, Received data = 0x%0h \n",$time, DISP_ERR, address, data_in,datao);
|
||||
$stop;
|
||||
end else
|
||||
$display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN(0x%0h) MATCHED \n",$time, DISP_INFO, address, data_in);
|
||||
data_out = datao;
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'wait_mem_update' call failed ...\n",$time, DISP_ERR, address);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
mem_update_key = 1;
|
||||
end else
|
||||
$display("[%0d] : %0s : One instance of 'wait_mem_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN);
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
/* API to initiate a WRITE transaction on one of the AXI-Master ports*/
|
||||
task automatic write_from_file;
|
||||
input [(max_chars*8)-1:0] file_name;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [int_width-1:0] wr_size;
|
||||
output [axi_rsp_width-1:0] response;
|
||||
integer succ;
|
||||
begin
|
||||
succ = $fopen(file_name,"r");
|
||||
if(succ == 0) begin
|
||||
$display("[%0d] : %0s : '%0s' doesn't exist. 'write_from_file' call failed ...\n",$time, DISP_ERR, file_name);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
else if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(check_addr_aligned(start_addr)) begin
|
||||
$fclose(succ);
|
||||
// case(start_addr[31:30])
|
||||
if (start_addr[31:30] === 2'b01) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO, start_addr, wr_size, file_name);
|
||||
M_AXI_GP0.write_from_file(file_name,start_addr,wr_size,response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
|
||||
end else if(start_addr[31:30] === 2'b10) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO, start_addr, wr_size, file_name);
|
||||
M_AXI_GP1.write_from_file(file_name,start_addr,wr_size,response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'write_from_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
// endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_from_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to initiate a READ transaction on one of the AXI-Master ports*/
|
||||
task automatic read_to_file;
|
||||
input [(max_chars*8)-1:0] file_name;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [int_width-1:0] rd_size;
|
||||
output [axi_rsp_width-1:0] response;
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR , start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(check_addr_aligned(start_addr)) begin
|
||||
// case(start_addr[31:30])
|
||||
if (start_addr[31:30] === 2'b01) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO, start_addr, rd_size, file_name);
|
||||
M_AXI_GP0.read_to_file(file_name,start_addr,rd_size,response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
|
||||
end else if(start_addr[31:30] === 2'b10) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO, start_addr, rd_size, file_name);
|
||||
M_AXI_GP1.read_to_file(file_name,start_addr,rd_size,response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
|
||||
// end
|
||||
// default : $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_to_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
// endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_to_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to initiate a WRITE transaction(<= 128 bytes) on one of the AXI-Master ports*/
|
||||
task automatic write_data;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [max_transfer_bytes_width:0] wr_size;
|
||||
input [(max_transfer_bytes*8)-1:0] w_data;
|
||||
output [axi_rsp_width-1:0] response;
|
||||
reg[511:0] rsp;
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_data' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(wr_size > max_transfer_bytes) begin
|
||||
$display("[%0d] : %0s : Byte Size supported is 128 bytes only. 'write_data' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(start_addr[31:30] === GP_M0) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, wr_size);
|
||||
M_AXI_GP0.write_data(start_addr,wr_size,w_data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else if(start_addr[31:30] === GP_M1) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, wr_size);
|
||||
M_AXI_GP1.write_data(start_addr,wr_size,w_data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'write_data' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to initiate a READ transaction(<= 128 bytes) on one of the AXI-Master ports*/
|
||||
task automatic read_data;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [max_transfer_bytes_width:0] rd_size;
|
||||
output[(max_transfer_bytes*8)-1:0] rd_data;
|
||||
output [axi_rsp_width-1:0] response;
|
||||
reg[511:0] rsp;
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range 'read_data' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(rd_size > max_transfer_bytes) begin
|
||||
$display("[%0d] : %0s : Byte Size supported is 128 bytes only.'read_data' call failed ... \n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(start_addr[31:30] === GP_M0) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO, start_addr, rd_size);
|
||||
M_AXI_GP0.read_data(start_addr,rd_size,rd_data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else if(start_addr[31:30] === GP_M1) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO, start_addr, rd_size);
|
||||
M_AXI_GP1.read_data(start_addr,rd_size,rd_data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'read_data' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
/* Hooks to call to VIP APIs */
|
||||
task automatic write_burst(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
|
||||
reg[511:0] rsp;
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(start_addr[31:30] === 2'b01) begin
|
||||
// end else if(start_addr[31:30] === GP_M0) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
|
||||
M_AXI_GP0.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else if(start_addr[31:30] === 2'b10) begin
|
||||
// end else if(start_addr[31:30] === GP_M1) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
|
||||
M_AXI_GP1.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst' call failed ... \n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
task automatic write_burst_concurrent(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
|
||||
reg[511:0] rsp; /// string for response
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst_concurrent' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(start_addr[31:30] === 2'b01) begin
|
||||
// end else if(start_addr[31:30] === GP_M0) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
|
||||
M_AXI_GP0.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else if(start_addr[31:30] === 2'b10) begin
|
||||
// end else if(start_addr[31:30] === GP_M1) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
|
||||
M_AXI_GP1.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst_concurrent' call failed ... \n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
task automatic read_burst;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [axi_len_width-1:0] len;
|
||||
input [axi_size_width-1:0] siz;
|
||||
input [axi_brst_type_width-1:0] burst;
|
||||
input [axi_lock_width-1:0] lck;
|
||||
input [axi_cache_width-1:0] cache;
|
||||
input [axi_prot_width-1:0] prot;
|
||||
output [(axi_mgp_data_width*axi_burst_len)-1:0] data;
|
||||
output [(axi_rsp_width*axi_burst_len)-1:0] response;
|
||||
reg[511:0] rsp;
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'read_burst' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(start_addr[31:30] === 2'b01) begin
|
||||
// end else if(start_addr[31:30] === GP_M0) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO, start_addr);
|
||||
M_AXI_GP0.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else if(start_addr[31:30] === 2'b10) begin
|
||||
// end else if(start_addr[31:30] === GP_M1) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO, start_addr);
|
||||
M_AXI_GP1.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'read_burst' call failed ... \n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
task automatic wait_reg_update;
|
||||
input [addr_width-1:0] addr;
|
||||
input [data_width-1:0] data_i;
|
||||
input [data_width-1:0] mask_i;
|
||||
input [int_width-1:0] time_interval;
|
||||
input [int_width-1:0] time_out;
|
||||
output [data_width-1:0] data_o;
|
||||
|
||||
reg upd_done0;
|
||||
reg upd_done1;
|
||||
begin
|
||||
if(!check_master_address(addr)) begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out of range. 'wait_reg_update' call failed ...\n",$time, DISP_ERR, addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(addr[31:30] === 2'b01) begin
|
||||
// end else if(addr[31:30] === GP_M0) begin
|
||||
if(reg_update_key_0) begin
|
||||
reg_update_key_0 = 0;
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i);
|
||||
M_AXI_GP0.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done0);
|
||||
if(DEBUG_INFO && upd_done0)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr);
|
||||
reg_update_key_0 = 1;
|
||||
end else
|
||||
$display("[%0d] : M_AXI_GP0 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN);
|
||||
end else if(addr[31:30] === 2'b10) begin
|
||||
// end else if(addr[31:30] === GP_M1) begin
|
||||
if(reg_update_key_1) begin
|
||||
reg_update_key_1 = 0;
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i);
|
||||
M_AXI_GP1.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done1);
|
||||
if(DEBUG_INFO && upd_done1)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr);
|
||||
reg_update_key_1 = 1;
|
||||
end else
|
||||
$display("[%0d] : M_AXI_GP1 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'wait_reg_update' call failed ... \n",$time, DISP_ERR, addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to read register map */
|
||||
task read_register_map;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [max_regs_width:0] no_of_registers;
|
||||
output[max_burst_bits-1 :0] data;
|
||||
reg [max_regs_width:0] no_of_regs;
|
||||
begin
|
||||
no_of_regs = no_of_registers;
|
||||
if(no_of_registers > 32) begin
|
||||
$display("[%0d] : %0s : No_of_Registers(%0d) exceeds the supported number (32).\n Only 32 registers will be read.",$time, DISP_ERR, start_addr);
|
||||
no_of_regs = 32;
|
||||
end
|
||||
if(check_addr_aligned(start_addr)) begin
|
||||
if(decode_address(start_addr) == REG_MEM) begin
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : Reading Registers starting address (0x%0h) -> %0d registers",$time, DISP_INFO, start_addr,no_of_regs );
|
||||
regc.regm.read_reg_mem(data,start_addr,no_of_regs*4); /// as each register is of 4 bytes
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : DONE -> Reading Registers starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INFO, start_addr, data );
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
end else begin
|
||||
data = 0;
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to read single register */
|
||||
task read_register;
|
||||
input [addr_width-1:0] addr;
|
||||
output[data_width-1:0] data;
|
||||
begin
|
||||
if(check_addr_aligned(addr)) begin
|
||||
if(decode_address(addr) == REG_MEM) begin
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : Reading Register (0x%0h) ",$time, DISP_INFO, addr );
|
||||
regc.regm.get_data(addr >> 2, data);
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : DONE -> Reading Register (0x%0h), Data returned(0x%0h)",$time, DISP_INFO, addr, data );
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register' call failed ...",$time, DISP_ERR, addr);
|
||||
end
|
||||
end else begin
|
||||
data = 0;
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register' call failed ...",$time, DISP_ERR, addr);
|
||||
end
|
||||
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to set the AXI-Slave profile*/
|
||||
task automatic set_slave_profile;
|
||||
input[1023:0] name;
|
||||
input[1:0] latency ;
|
||||
begin
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : %0s Port/s : Setting Slave profile",$time, DISP_INFO, name);
|
||||
case(name)
|
||||
"S_AXI_GP0" : S_AXI_GP0.set_latency_type(latency);
|
||||
"S_AXI_GP1" : S_AXI_GP1.set_latency_type(latency);
|
||||
"S_AXI_HP0" : S_AXI_HP0.set_latency_type(latency);
|
||||
"S_AXI_HP1" : S_AXI_HP1.set_latency_type(latency);
|
||||
"S_AXI_HP2" : S_AXI_HP2.set_latency_type(latency);
|
||||
"S_AXI_HP3" : S_AXI_HP3.set_latency_type(latency);
|
||||
"S_AXI_ACP" : S_AXI_ACP.set_latency_type(latency);
|
||||
"ALL" : begin
|
||||
S_AXI_GP0.set_latency_type(latency);
|
||||
S_AXI_GP1.set_latency_type(latency);
|
||||
S_AXI_HP0.set_latency_type(latency);
|
||||
S_AXI_HP1.set_latency_type(latency);
|
||||
S_AXI_HP2.set_latency_type(latency);
|
||||
S_AXI_HP3.set_latency_type(latency);
|
||||
S_AXI_ACP.set_latency_type(latency);
|
||||
end
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
/*------------------------------ LOCAL APIs ------------------------------------------------ */
|
||||
|
||||
/* local API for address decoding*/
|
||||
function automatic [1:0] decode_address;
|
||||
input [addr_width-1:0] address;
|
||||
begin
|
||||
if(!C_HIGH_OCM_EN && (address < ocm_end_addr || address >= ocm_low_addr ))
|
||||
decode_address = OCM_MEM; /// OCM
|
||||
else if(address >= ddr_start_addr && address <= ddr_end_addr)
|
||||
decode_address = DDR_MEM; /// DDR
|
||||
else if(C_HIGH_OCM_EN && address >= high_ocm_start_addr)
|
||||
decode_address = OCM_MEM; /// OCM
|
||||
else if(address >= reg_start_addr && reg_start_addr <= reg_end_addr)
|
||||
decode_address = REG_MEM; /// Register Map
|
||||
else
|
||||
decode_address = INVALID_MEM_TYPE; /// ERROR in Address
|
||||
end
|
||||
endfunction
|
||||
|
||||
/* local API for checking address is 32-bit (4-byte) aligned */
|
||||
function automatic check_addr_aligned;
|
||||
input [addr_width-1:0] address;
|
||||
begin
|
||||
if((address%4) !=0 ) begin //
|
||||
check_addr_aligned = 0; ///not_aligned
|
||||
end else
|
||||
check_addr_aligned = 1;
|
||||
end
|
||||
endfunction
|
||||
|
||||
/* local API to check address for GP Masters */
|
||||
function check_master_address;
|
||||
input [addr_width-1:0] address;
|
||||
begin
|
||||
if(address >= m_axi_gp0_baseaddr && address <= m_axi_gp0_highaddr)
|
||||
check_master_address = 1'b1;
|
||||
else if(address >= m_axi_gp1_baseaddr && address <= m_axi_gp1_highaddr)
|
||||
check_master_address = 1'b1;
|
||||
else
|
||||
check_master_address = 1'b0; /// ERROR in Address
|
||||
end
|
||||
endfunction
|
||||
|
||||
/* Response decode */
|
||||
function automatic [511:0] get_resp;
|
||||
input[axi_rsp_width-1:0] response;
|
||||
begin
|
||||
case(response)
|
||||
2'b00 : get_resp = "OKAY";
|
||||
2'b01 : get_resp = "EXOKAY";
|
||||
2'b10 : get_resp = "SLVERR";
|
||||
2'b11 : get_resp = "DECERR";
|
||||
endcase
|
||||
end
|
||||
endfunction
|
||||
+94
@@ -0,0 +1,94 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_17_axi_acp.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Connections for ACP port
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* AXI Slave ACP */
|
||||
processing_system7_vip_v1_0_17_axi_slave_acp #( C_USE_S_AXI_ACP, // enable
|
||||
axi_acp_name, // name
|
||||
axi_acp_data_width, // data width
|
||||
addr_width, /// address width
|
||||
axi_acp_id_width, // ID width
|
||||
C_S_AXI_ACP_BASEADDR, // slave base address
|
||||
C_S_AXI_ACP_HIGHADDR,// slave size
|
||||
axi_acp_outstanding, // outstanding transactions // 7 Reads and 3 Writes
|
||||
axi_slv_excl_support, // Exclusive access support
|
||||
axi_acp_wr_outstanding,
|
||||
axi_acp_rd_outstanding)
|
||||
S_AXI_ACP(.S_RESETN (net_axi_acp_rstn),
|
||||
.S_ACLK (S_AXI_ACP_ACLK),
|
||||
// Write Address Channel
|
||||
.S_AWID (S_AXI_ACP_AWID),
|
||||
.S_AWADDR (S_AXI_ACP_AWADDR),
|
||||
.S_AWLEN (S_AXI_ACP_AWLEN),
|
||||
.S_AWSIZE (S_AXI_ACP_AWSIZE),
|
||||
.S_AWBURST (S_AXI_ACP_AWBURST),
|
||||
.S_AWLOCK (S_AXI_ACP_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_ACP_AWCACHE),
|
||||
.S_AWPROT (S_AXI_ACP_AWPROT),
|
||||
.S_AWVALID (S_AXI_ACP_AWVALID),
|
||||
.S_AWREADY (S_AXI_ACP_AWREADY),
|
||||
// Write Data Channel Signals.
|
||||
.S_WID (S_AXI_ACP_WID),
|
||||
.S_WDATA (S_AXI_ACP_WDATA),
|
||||
.S_WSTRB (S_AXI_ACP_WSTRB),
|
||||
.S_WLAST (S_AXI_ACP_WLAST),
|
||||
.S_WVALID (S_AXI_ACP_WVALID),
|
||||
.S_WREADY (S_AXI_ACP_WREADY),
|
||||
// Write Response Channel Signals.
|
||||
.S_BID (S_AXI_ACP_BID),
|
||||
.S_BRESP (S_AXI_ACP_BRESP),
|
||||
.S_BVALID (S_AXI_ACP_BVALID),
|
||||
.S_BREADY (S_AXI_ACP_BREADY),
|
||||
// Read Address Channel Signals.
|
||||
.S_ARID (S_AXI_ACP_ARID),
|
||||
.S_ARADDR (S_AXI_ACP_ARADDR),
|
||||
.S_ARLEN (S_AXI_ACP_ARLEN),
|
||||
.S_ARSIZE (S_AXI_ACP_ARSIZE),
|
||||
.S_ARBURST (S_AXI_ACP_ARBURST),
|
||||
.S_ARLOCK (S_AXI_ACP_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_ACP_ARCACHE),
|
||||
.S_ARPROT (S_AXI_ACP_ARPROT),
|
||||
.S_ARVALID (S_AXI_ACP_ARVALID),
|
||||
.S_ARREADY (S_AXI_ACP_ARREADY),
|
||||
// Read Data Channel Signals.
|
||||
.S_RID (S_AXI_ACP_RID),
|
||||
.S_RDATA (S_AXI_ACP_RDATA),
|
||||
.S_RRESP (S_AXI_ACP_RRESP),
|
||||
.S_RLAST (S_AXI_ACP_RLAST),
|
||||
.S_RVALID (S_AXI_ACP_RVALID),
|
||||
.S_RREADY (S_AXI_ACP_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_ACP_AWQOS),
|
||||
.S_ARQOS (S_AXI_ACP_ARQOS), // Side band signals
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
/* This goes to port 0 of DDR and port 0 of OCM , port 0 of REG*/
|
||||
.WR_DATA_ACK_DDR (ddr_wr_ack_port0),
|
||||
.WR_DATA_ACK_OCM (ocm_wr_ack_port0),
|
||||
.WR_DATA (net_wr_data_acp),
|
||||
.WR_DATA_STRB (net_wr_strb_acp),
|
||||
.WR_ADDR (net_wr_addr_acp),
|
||||
.WR_BYTES (net_wr_bytes_acp),
|
||||
.WR_DATA_VALID_DDR (ddr_wr_dv_port0),
|
||||
.WR_DATA_VALID_OCM (ocm_wr_dv_port0),
|
||||
.WR_QOS (net_wr_qos_acp),
|
||||
|
||||
.RD_REQ_DDR (ddr_rd_req_port0),
|
||||
.RD_REQ_OCM (ocm_rd_req_port0),
|
||||
.RD_REQ_REG (reg_rd_req_port0),
|
||||
.RD_ADDR (net_rd_addr_acp),
|
||||
.RD_DATA_DDR (ddr_rd_data_port0),
|
||||
.RD_DATA_OCM (ocm_rd_data_port0),
|
||||
.RD_DATA_REG (reg_rd_data_port0),
|
||||
.RD_BYTES (net_rd_bytes_acp),
|
||||
.RD_DATA_VALID_DDR (ddr_rd_dv_port0),
|
||||
.RD_DATA_VALID_OCM (ocm_rd_dv_port0),
|
||||
.RD_DATA_VALID_REG (reg_rd_dv_port0),
|
||||
.RD_QOS (net_rd_qos_acp)
|
||||
|
||||
);
|
||||
+311
@@ -0,0 +1,311 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_17_axi_gp.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Connections for AXI GP ports
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* IDs for Masters
|
||||
// l2m1 (CPU000)
|
||||
12'b11_000_000_00_00
|
||||
12'b11_010_000_00_00
|
||||
12'b11_011_000_00_00
|
||||
12'b11_100_000_00_00
|
||||
12'b11_101_000_00_00
|
||||
12'b11_110_000_00_00
|
||||
12'b11_111_000_00_00
|
||||
// l2m1 (CPU001)
|
||||
12'b11_000_001_00_00
|
||||
12'b11_010_001_00_00
|
||||
12'b11_011_001_00_00
|
||||
12'b11_100_001_00_00
|
||||
12'b11_101_001_00_00
|
||||
12'b11_110_001_00_00
|
||||
12'b11_111_001_00_00
|
||||
*/
|
||||
|
||||
/* AXI -Master GP0 */
|
||||
processing_system7_vip_v1_0_17_axi_master #(C_USE_M_AXI_GP0, // enable
|
||||
axi_mgp0_name,// name
|
||||
axi_mgp_data_width, /// Data Width
|
||||
addr_width, /// Address width
|
||||
axi_mgp_id_width, //// ID Width
|
||||
axi_mgp_outstanding, //// Outstanding transactions
|
||||
axi_mst_excl_support, // EXCL Access Support
|
||||
axi_mgp_wr_id, //WR_ID
|
||||
axi_mgp_rd_id) //RD_ID
|
||||
M_AXI_GP0(.M_RESETN (net_axi_mgp0_rstn),
|
||||
.M_ACLK (M_AXI_GP0_ACLK),
|
||||
// Write Address Channel
|
||||
.M_AWID (M_AXI_GP0_AWID_FULL),
|
||||
.M_AWADDR (M_AXI_GP0_AWADDR),
|
||||
.M_AWLEN (M_AXI_GP0_AWLEN),
|
||||
.M_AWSIZE (M_AXI_GP0_AWSIZE),
|
||||
.M_AWBURST (M_AXI_GP0_AWBURST),
|
||||
.M_AWLOCK (M_AXI_GP0_AWLOCK),
|
||||
.M_AWCACHE (M_AXI_GP0_AWCACHE),
|
||||
.M_AWPROT (M_AXI_GP0_AWPROT),
|
||||
.M_AWVALID (M_AXI_GP0_AWVALID),
|
||||
.M_AWREADY (M_AXI_GP0_AWREADY),
|
||||
// Write Data Channel Signals.
|
||||
.M_WID (M_AXI_GP0_WID_FULL),
|
||||
.M_WDATA (M_AXI_GP0_WDATA),
|
||||
.M_WSTRB (M_AXI_GP0_WSTRB),
|
||||
.M_WLAST (M_AXI_GP0_WLAST),
|
||||
.M_WVALID (M_AXI_GP0_WVALID),
|
||||
.M_WREADY (M_AXI_GP0_WREADY),
|
||||
// Write Response Channel Signals.
|
||||
.M_BID (M_AXI_GP0_BID_FULL),
|
||||
.M_BRESP (M_AXI_GP0_BRESP),
|
||||
.M_BVALID (M_AXI_GP0_BVALID),
|
||||
.M_BREADY (M_AXI_GP0_BREADY),
|
||||
// Read Address Channel Signals.
|
||||
.M_ARID (M_AXI_GP0_ARID_FULL),
|
||||
.M_ARADDR (M_AXI_GP0_ARADDR),
|
||||
.M_ARLEN (M_AXI_GP0_ARLEN),
|
||||
.M_ARSIZE (M_AXI_GP0_ARSIZE),
|
||||
.M_ARBURST (M_AXI_GP0_ARBURST),
|
||||
.M_ARLOCK (M_AXI_GP0_ARLOCK),
|
||||
.M_ARCACHE (M_AXI_GP0_ARCACHE),
|
||||
.M_ARPROT (M_AXI_GP0_ARPROT),
|
||||
.M_ARVALID (M_AXI_GP0_ARVALID),
|
||||
.M_ARREADY (M_AXI_GP0_ARREADY),
|
||||
// Read Data Channel Signals.
|
||||
.M_RID (M_AXI_GP0_RID_FULL),
|
||||
.M_RDATA (M_AXI_GP0_RDATA),
|
||||
.M_RRESP (M_AXI_GP0_RRESP),
|
||||
.M_RLAST (M_AXI_GP0_RLAST),
|
||||
.M_RVALID (M_AXI_GP0_RVALID),
|
||||
.M_RREADY (M_AXI_GP0_RREADY),
|
||||
// Side band signals
|
||||
.M_AWQOS (M_AXI_GP0_AWQOS),
|
||||
.M_ARQOS (M_AXI_GP0_ARQOS)
|
||||
);
|
||||
|
||||
/* AXI Master GP1 */
|
||||
processing_system7_vip_v1_0_17_axi_master #(C_USE_M_AXI_GP1, // enable
|
||||
axi_mgp1_name,// name
|
||||
axi_mgp_data_width, /// Data Width
|
||||
addr_width, /// Address width
|
||||
axi_mgp_id_width, //// ID Width
|
||||
axi_mgp_outstanding, //// Outstanding transactions
|
||||
axi_mst_excl_support, // EXCL Access Support
|
||||
axi_mgp_wr_id, //WR_ID
|
||||
axi_mgp_rd_id) //RD_ID
|
||||
M_AXI_GP1(.M_RESETN (net_axi_mgp1_rstn),
|
||||
.M_ACLK (M_AXI_GP1_ACLK),
|
||||
// Write Address Channel
|
||||
.M_AWID (M_AXI_GP1_AWID_FULL),
|
||||
.M_AWADDR (M_AXI_GP1_AWADDR),
|
||||
.M_AWLEN (M_AXI_GP1_AWLEN),
|
||||
.M_AWSIZE (M_AXI_GP1_AWSIZE),
|
||||
.M_AWBURST (M_AXI_GP1_AWBURST),
|
||||
.M_AWLOCK (M_AXI_GP1_AWLOCK),
|
||||
.M_AWCACHE (M_AXI_GP1_AWCACHE),
|
||||
.M_AWPROT (M_AXI_GP1_AWPROT),
|
||||
.M_AWVALID (M_AXI_GP1_AWVALID),
|
||||
.M_AWREADY (M_AXI_GP1_AWREADY),
|
||||
// Write Data Channel Signals.
|
||||
.M_WID (M_AXI_GP1_WID_FULL),
|
||||
.M_WDATA (M_AXI_GP1_WDATA),
|
||||
.M_WSTRB (M_AXI_GP1_WSTRB),
|
||||
.M_WLAST (M_AXI_GP1_WLAST),
|
||||
.M_WVALID (M_AXI_GP1_WVALID),
|
||||
.M_WREADY (M_AXI_GP1_WREADY),
|
||||
// Write Response Channel Signals.
|
||||
.M_BID (M_AXI_GP1_BID_FULL),
|
||||
.M_BRESP (M_AXI_GP1_BRESP),
|
||||
.M_BVALID (M_AXI_GP1_BVALID),
|
||||
.M_BREADY (M_AXI_GP1_BREADY),
|
||||
// Read Address Channel Signals.
|
||||
.M_ARID (M_AXI_GP1_ARID_FULL),
|
||||
.M_ARADDR (M_AXI_GP1_ARADDR),
|
||||
.M_ARLEN (M_AXI_GP1_ARLEN),
|
||||
.M_ARSIZE (M_AXI_GP1_ARSIZE),
|
||||
.M_ARBURST (M_AXI_GP1_ARBURST),
|
||||
.M_ARLOCK (M_AXI_GP1_ARLOCK),
|
||||
.M_ARCACHE (M_AXI_GP1_ARCACHE),
|
||||
.M_ARPROT (M_AXI_GP1_ARPROT),
|
||||
.M_ARVALID (M_AXI_GP1_ARVALID),
|
||||
.M_ARREADY (M_AXI_GP1_ARREADY),
|
||||
// Read Data Channel Signals.
|
||||
.M_RID (M_AXI_GP1_RID_FULL),
|
||||
.M_RDATA (M_AXI_GP1_RDATA),
|
||||
.M_RRESP (M_AXI_GP1_RRESP),
|
||||
.M_RLAST (M_AXI_GP1_RLAST),
|
||||
.M_RVALID (M_AXI_GP1_RVALID),
|
||||
.M_RREADY (M_AXI_GP1_RREADY),
|
||||
// Side band signals
|
||||
.M_AWQOS (M_AXI_GP1_AWQOS),
|
||||
.M_ARQOS (M_AXI_GP1_ARQOS)
|
||||
);
|
||||
|
||||
/* AXI Slave GP0 */
|
||||
processing_system7_vip_v1_0_17_axi_slave #(C_USE_S_AXI_GP0, /// enable
|
||||
axi_sgp0_name, //name
|
||||
axi_sgp_data_width, /// data width
|
||||
addr_width, /// address width
|
||||
axi_sgp_id_width, /// ID width
|
||||
C_S_AXI_GP0_BASEADDR,//// base address
|
||||
C_S_AXI_GP0_HIGHADDR,/// Memory size (high_addr - base_addr)
|
||||
axi_sgp_outstanding, // outstanding transactions
|
||||
axi_slv_excl_support, // exclusive access not supported
|
||||
axi_sgp_wr_outstanding,
|
||||
axi_sgp_rd_outstanding)
|
||||
S_AXI_GP0(.S_RESETN (net_axi_gp0_rstn),
|
||||
.S_ACLK (S_AXI_GP0_ACLK),
|
||||
// Write Address Channel
|
||||
.S_AWID (S_AXI_GP0_AWID),
|
||||
.S_AWADDR (S_AXI_GP0_AWADDR),
|
||||
.S_AWLEN (S_AXI_GP0_AWLEN),
|
||||
.S_AWSIZE (S_AXI_GP0_AWSIZE),
|
||||
.S_AWBURST (S_AXI_GP0_AWBURST),
|
||||
.S_AWLOCK (S_AXI_GP0_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_GP0_AWCACHE),
|
||||
.S_AWPROT (S_AXI_GP0_AWPROT),
|
||||
.S_AWVALID (S_AXI_GP0_AWVALID),
|
||||
.S_AWREADY (S_AXI_GP0_AWREADY),
|
||||
// Write Data Channel Signals.
|
||||
.S_WID (S_AXI_GP0_WID),
|
||||
.S_WDATA (S_AXI_GP0_WDATA),
|
||||
.S_WSTRB (S_AXI_GP0_WSTRB),
|
||||
.S_WLAST (S_AXI_GP0_WLAST),
|
||||
.S_WVALID (S_AXI_GP0_WVALID),
|
||||
.S_WREADY (S_AXI_GP0_WREADY),
|
||||
// Write Response Channel Signals.
|
||||
.S_BID (S_AXI_GP0_BID),
|
||||
.S_BRESP (S_AXI_GP0_BRESP),
|
||||
.S_BVALID (S_AXI_GP0_BVALID),
|
||||
.S_BREADY (S_AXI_GP0_BREADY),
|
||||
// Read Address Channel Signals.
|
||||
.S_ARID (S_AXI_GP0_ARID),
|
||||
.S_ARADDR (S_AXI_GP0_ARADDR),
|
||||
.S_ARLEN (S_AXI_GP0_ARLEN),
|
||||
.S_ARSIZE (S_AXI_GP0_ARSIZE),
|
||||
.S_ARBURST (S_AXI_GP0_ARBURST),
|
||||
.S_ARLOCK (S_AXI_GP0_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_GP0_ARCACHE),
|
||||
.S_ARPROT (S_AXI_GP0_ARPROT),
|
||||
.S_ARVALID (S_AXI_GP0_ARVALID),
|
||||
.S_ARREADY (S_AXI_GP0_ARREADY),
|
||||
// Read Data Channel Signals.
|
||||
.S_RID (S_AXI_GP0_RID),
|
||||
.S_RDATA (S_AXI_GP0_RDATA),
|
||||
.S_RRESP (S_AXI_GP0_RRESP),
|
||||
.S_RLAST (S_AXI_GP0_RLAST),
|
||||
.S_RVALID (S_AXI_GP0_RVALID),
|
||||
.S_RREADY (S_AXI_GP0_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_GP0_AWQOS),
|
||||
.S_ARQOS (S_AXI_GP0_ARQOS),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_gp0),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_gp0),
|
||||
.WR_DATA (net_wr_data_gp0),
|
||||
.WR_DATA_STRB (net_wr_strb_gp0),
|
||||
.WR_ADDR (net_wr_addr_gp0),
|
||||
.WR_BYTES (net_wr_bytes_gp0),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_gp0),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_gp0),
|
||||
.WR_QOS (net_wr_qos_gp0),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_gp0),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_gp0),
|
||||
.RD_REQ_REG (net_rd_req_reg_gp0),
|
||||
.RD_ADDR (net_rd_addr_gp0),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_gp0),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_gp0),
|
||||
.RD_DATA_REG (net_rd_data_reg_gp0),
|
||||
.RD_BYTES (net_rd_bytes_gp0),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_gp0),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_gp0),
|
||||
.RD_DATA_VALID_REG (net_rd_dv_reg_gp0),
|
||||
.RD_QOS (net_rd_qos_gp0)
|
||||
|
||||
);
|
||||
|
||||
/* AXI Slave GP1 */
|
||||
processing_system7_vip_v1_0_17_axi_slave #(C_USE_S_AXI_GP1, /// enable
|
||||
axi_sgp1_name, //name
|
||||
axi_sgp_data_width, /// data width
|
||||
addr_width, /// address width
|
||||
axi_sgp_id_width, /// ID width
|
||||
C_S_AXI_GP1_BASEADDR,//// base address
|
||||
C_S_AXI_GP1_HIGHADDR,/// HIGh_addr
|
||||
axi_sgp_outstanding, // outstanding transactions
|
||||
axi_slv_excl_support, // exclusive access
|
||||
axi_sgp_wr_outstanding,
|
||||
axi_sgp_rd_outstanding)
|
||||
S_AXI_GP1(.S_RESETN (net_axi_gp1_rstn),
|
||||
.S_ACLK (S_AXI_GP1_ACLK),
|
||||
// Write Address Channel
|
||||
.S_AWID (S_AXI_GP1_AWID),
|
||||
.S_AWADDR (S_AXI_GP1_AWADDR),
|
||||
.S_AWLEN (S_AXI_GP1_AWLEN),
|
||||
.S_AWSIZE (S_AXI_GP1_AWSIZE),
|
||||
.S_AWBURST (S_AXI_GP1_AWBURST),
|
||||
.S_AWLOCK (S_AXI_GP1_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_GP1_AWCACHE),
|
||||
.S_AWPROT (S_AXI_GP1_AWPROT),
|
||||
.S_AWVALID (S_AXI_GP1_AWVALID),
|
||||
.S_AWREADY (S_AXI_GP1_AWREADY),
|
||||
// Write Data Channel Signals.
|
||||
.S_WID (S_AXI_GP1_WID),
|
||||
.S_WDATA (S_AXI_GP1_WDATA),
|
||||
.S_WSTRB (S_AXI_GP1_WSTRB),
|
||||
.S_WLAST (S_AXI_GP1_WLAST),
|
||||
.S_WVALID (S_AXI_GP1_WVALID),
|
||||
.S_WREADY (S_AXI_GP1_WREADY),
|
||||
// Write Response Channel Signals.
|
||||
.S_BID (S_AXI_GP1_BID),
|
||||
.S_BRESP (S_AXI_GP1_BRESP),
|
||||
.S_BVALID (S_AXI_GP1_BVALID),
|
||||
.S_BREADY (S_AXI_GP1_BREADY),
|
||||
// Read Address Channel Signals.
|
||||
.S_ARID (S_AXI_GP1_ARID),
|
||||
.S_ARADDR (S_AXI_GP1_ARADDR),
|
||||
.S_ARLEN (S_AXI_GP1_ARLEN),
|
||||
.S_ARSIZE (S_AXI_GP1_ARSIZE),
|
||||
.S_ARBURST (S_AXI_GP1_ARBURST),
|
||||
.S_ARLOCK (S_AXI_GP1_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_GP1_ARCACHE),
|
||||
.S_ARPROT (S_AXI_GP1_ARPROT),
|
||||
.S_ARVALID (S_AXI_GP1_ARVALID),
|
||||
.S_ARREADY (S_AXI_GP1_ARREADY),
|
||||
// Read Data Channel Signals.
|
||||
.S_RID (S_AXI_GP1_RID),
|
||||
.S_RDATA (S_AXI_GP1_RDATA),
|
||||
.S_RRESP (S_AXI_GP1_RRESP),
|
||||
.S_RLAST (S_AXI_GP1_RLAST),
|
||||
.S_RVALID (S_AXI_GP1_RVALID),
|
||||
.S_RREADY (S_AXI_GP1_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_GP1_AWQOS),
|
||||
.S_ARQOS (S_AXI_GP1_ARQOS),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_gp1),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_gp1),
|
||||
.WR_DATA (net_wr_data_gp1),
|
||||
.WR_DATA_STRB (net_wr_strb_gp1),
|
||||
.WR_ADDR (net_wr_addr_gp1),
|
||||
.WR_BYTES (net_wr_bytes_gp1),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_gp1),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_gp1),
|
||||
.WR_QOS (net_wr_qos_gp1),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_gp1),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_gp1),
|
||||
.RD_REQ_REG (net_rd_req_reg_gp1),
|
||||
.RD_ADDR (net_rd_addr_gp1),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_gp1),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_gp1),
|
||||
.RD_DATA_REG (net_rd_data_reg_gp1),
|
||||
.RD_BYTES (net_rd_bytes_gp1),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_gp1),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_gp1),
|
||||
.RD_DATA_VALID_REG (net_rd_dv_reg_gp1),
|
||||
.RD_QOS (net_rd_qos_gp1)
|
||||
|
||||
);
|
||||
+350
@@ -0,0 +1,350 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_17_axi_hp.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Connections for AXI HP ports
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* AXI Slave HP0 */
|
||||
processing_system7_vip_v1_0_17_afi_slave #( C_USE_S_AXI_HP0, // enable
|
||||
axi_hp0_name, // name
|
||||
C_S_AXI_HP0_DATA_WIDTH, // data width
|
||||
addr_width, /// address width
|
||||
axi_hp_id_width, // ID width
|
||||
C_S_AXI_HP0_BASEADDR, // slave base address
|
||||
C_S_AXI_HP0_HIGHADDR, // slave size
|
||||
axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
|
||||
axi_slv_excl_support) // Exclusive access support
|
||||
S_AXI_HP0(.S_RESETN (net_axi_hp0_rstn),
|
||||
.S_ACLK (S_AXI_HP0_ACLK),
|
||||
// Write Address channel
|
||||
.S_AWID (S_AXI_HP0_AWID),
|
||||
.S_AWADDR (S_AXI_HP0_AWADDR),
|
||||
.S_AWLEN (S_AXI_HP0_AWLEN),
|
||||
.S_AWSIZE (S_AXI_HP0_AWSIZE),
|
||||
.S_AWBURST (S_AXI_HP0_AWBURST),
|
||||
.S_AWLOCK (S_AXI_HP0_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_HP0_AWCACHE),
|
||||
.S_AWPROT (S_AXI_HP0_AWPROT),
|
||||
.S_AWVALID (S_AXI_HP0_AWVALID),
|
||||
.S_AWREADY (S_AXI_HP0_AWREADY),
|
||||
// Write Data channel signals.
|
||||
.S_WID (S_AXI_HP0_WID),
|
||||
.S_WDATA (S_AXI_HP0_WDATA),
|
||||
.S_WSTRB (S_AXI_HP0_WSTRB),
|
||||
.S_WLAST (S_AXI_HP0_WLAST),
|
||||
.S_WVALID (S_AXI_HP0_WVALID),
|
||||
.S_WREADY (S_AXI_HP0_WREADY),
|
||||
// Write Response channel signals.
|
||||
.S_BID (S_AXI_HP0_BID),
|
||||
.S_BRESP (S_AXI_HP0_BRESP),
|
||||
.S_BVALID (S_AXI_HP0_BVALID),
|
||||
.S_BREADY (S_AXI_HP0_BREADY),
|
||||
// Read Address channel signals.
|
||||
.S_ARID (S_AXI_HP0_ARID),
|
||||
.S_ARADDR (S_AXI_HP0_ARADDR),
|
||||
.S_ARLEN (S_AXI_HP0_ARLEN),
|
||||
.S_ARSIZE (S_AXI_HP0_ARSIZE),
|
||||
.S_ARBURST (S_AXI_HP0_ARBURST),
|
||||
.S_ARLOCK (S_AXI_HP0_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_HP0_ARCACHE),
|
||||
.S_ARPROT (S_AXI_HP0_ARPROT),
|
||||
.S_ARVALID (S_AXI_HP0_ARVALID),
|
||||
.S_ARREADY (S_AXI_HP0_ARREADY),
|
||||
// Read Data channel signals.
|
||||
.S_RID (S_AXI_HP0_RID),
|
||||
.S_RDATA (S_AXI_HP0_RDATA),
|
||||
.S_RRESP (S_AXI_HP0_RRESP),
|
||||
.S_RLAST (S_AXI_HP0_RLAST),
|
||||
.S_RVALID (S_AXI_HP0_RVALID),
|
||||
.S_RREADY (S_AXI_HP0_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_HP0_AWQOS),
|
||||
.S_ARQOS (S_AXI_HP0_ARQOS),
|
||||
// these are needed only for HP ports
|
||||
.S_RDISSUECAP1_EN (S_AXI_HP0_RDISSUECAP1_EN),
|
||||
.S_WRISSUECAP1_EN (S_AXI_HP0_WRISSUECAP1_EN),
|
||||
.S_RCOUNT (S_AXI_HP0_RCOUNT),
|
||||
.S_WCOUNT (S_AXI_HP0_WCOUNT),
|
||||
.S_RACOUNT (S_AXI_HP0_RACOUNT),
|
||||
.S_WACOUNT (S_AXI_HP0_WACOUNT),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_hp0),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_hp0),
|
||||
.WR_DATA (net_wr_data_hp0),
|
||||
.WR_DATA_STRB (net_wr_strb_hp0),
|
||||
.WR_ADDR (net_wr_addr_hp0),
|
||||
.WR_BYTES (net_wr_bytes_hp0),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_hp0),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_hp0),
|
||||
.WR_QOS (net_wr_qos_hp0),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_hp0),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_hp0),
|
||||
.RD_ADDR (net_rd_addr_hp0),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_hp0),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_hp0),
|
||||
.RD_BYTES (net_rd_bytes_hp0),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_hp0),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_hp0),
|
||||
.RD_QOS (net_rd_qos_hp0)
|
||||
);
|
||||
|
||||
/* AXI Slave HP1 */
|
||||
processing_system7_vip_v1_0_17_afi_slave #( C_USE_S_AXI_HP1, // enable
|
||||
axi_hp1_name, // name
|
||||
C_S_AXI_HP1_DATA_WIDTH, // data width
|
||||
addr_width, /// address width
|
||||
axi_hp_id_width, // ID width
|
||||
C_S_AXI_HP1_BASEADDR, // slave base address
|
||||
C_S_AXI_HP1_HIGHADDR, // Slave size
|
||||
axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
|
||||
axi_slv_excl_support) // Exclusive access support
|
||||
S_AXI_HP1(.S_RESETN (net_axi_hp1_rstn),
|
||||
.S_ACLK (S_AXI_HP1_ACLK),
|
||||
// Write Address channel
|
||||
.S_AWID (S_AXI_HP1_AWID),
|
||||
.S_AWADDR (S_AXI_HP1_AWADDR),
|
||||
.S_AWLEN (S_AXI_HP1_AWLEN),
|
||||
.S_AWSIZE (S_AXI_HP1_AWSIZE),
|
||||
.S_AWBURST (S_AXI_HP1_AWBURST),
|
||||
.S_AWLOCK (S_AXI_HP1_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_HP1_AWCACHE),
|
||||
.S_AWPROT (S_AXI_HP1_AWPROT),
|
||||
.S_AWVALID (S_AXI_HP1_AWVALID),
|
||||
.S_AWREADY (S_AXI_HP1_AWREADY),
|
||||
// Write Data channel signals.
|
||||
.S_WID (S_AXI_HP1_WID),
|
||||
.S_WDATA (S_AXI_HP1_WDATA),
|
||||
.S_WSTRB (S_AXI_HP1_WSTRB),
|
||||
.S_WLAST (S_AXI_HP1_WLAST),
|
||||
.S_WVALID (S_AXI_HP1_WVALID),
|
||||
.S_WREADY (S_AXI_HP1_WREADY),
|
||||
// Write Response channel signals.
|
||||
.S_BID (S_AXI_HP1_BID),
|
||||
.S_BRESP (S_AXI_HP1_BRESP),
|
||||
.S_BVALID (S_AXI_HP1_BVALID),
|
||||
.S_BREADY (S_AXI_HP1_BREADY),
|
||||
// Read Address channel signals.
|
||||
.S_ARID (S_AXI_HP1_ARID),
|
||||
.S_ARADDR (S_AXI_HP1_ARADDR),
|
||||
.S_ARLEN (S_AXI_HP1_ARLEN),
|
||||
.S_ARSIZE (S_AXI_HP1_ARSIZE),
|
||||
.S_ARBURST (S_AXI_HP1_ARBURST),
|
||||
.S_ARLOCK (S_AXI_HP1_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_HP1_ARCACHE),
|
||||
.S_ARPROT (S_AXI_HP1_ARPROT),
|
||||
.S_ARVALID (S_AXI_HP1_ARVALID),
|
||||
.S_ARREADY (S_AXI_HP1_ARREADY),
|
||||
// Read Data channel signals.
|
||||
.S_RID (S_AXI_HP1_RID),
|
||||
.S_RDATA (S_AXI_HP1_RDATA),
|
||||
.S_RRESP (S_AXI_HP1_RRESP),
|
||||
.S_RLAST (S_AXI_HP1_RLAST),
|
||||
.S_RVALID (S_AXI_HP1_RVALID),
|
||||
.S_RREADY (S_AXI_HP1_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_HP1_AWQOS),
|
||||
.S_ARQOS (S_AXI_HP1_ARQOS),
|
||||
// these are needed only for HP ports
|
||||
.S_RDISSUECAP1_EN (S_AXI_HP1_RDISSUECAP1_EN),
|
||||
.S_WRISSUECAP1_EN (S_AXI_HP1_WRISSUECAP1_EN),
|
||||
.S_RCOUNT (S_AXI_HP1_RCOUNT),
|
||||
.S_WCOUNT (S_AXI_HP1_WCOUNT),
|
||||
.S_RACOUNT (S_AXI_HP1_RACOUNT),
|
||||
.S_WACOUNT (S_AXI_HP1_WACOUNT),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_hp1),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_hp1),
|
||||
.WR_DATA (net_wr_data_hp1),
|
||||
.WR_DATA_STRB (net_wr_strb_hp1),
|
||||
.WR_ADDR (net_wr_addr_hp1),
|
||||
.WR_BYTES (net_wr_bytes_hp1),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_hp1),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_hp1),
|
||||
.WR_QOS (net_wr_qos_hp1),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_hp1),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_hp1),
|
||||
.RD_ADDR (net_rd_addr_hp1),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_hp1),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_hp1),
|
||||
.RD_BYTES (net_rd_bytes_hp1),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_hp1),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_hp1),
|
||||
.RD_QOS (net_rd_qos_hp1)
|
||||
|
||||
);
|
||||
|
||||
/* AXI Slave HP2 */
|
||||
processing_system7_vip_v1_0_17_afi_slave #( C_USE_S_AXI_HP2, // enable
|
||||
axi_hp2_name, // name
|
||||
C_S_AXI_HP2_DATA_WIDTH, // data width
|
||||
addr_width, /// address width
|
||||
axi_hp_id_width, // ID width
|
||||
C_S_AXI_HP2_BASEADDR, // slave base address
|
||||
C_S_AXI_HP2_HIGHADDR, // SLave size
|
||||
axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
|
||||
axi_slv_excl_support) // Exclusive access support
|
||||
S_AXI_HP2(.S_RESETN (net_axi_hp2_rstn),
|
||||
.S_ACLK (S_AXI_HP2_ACLK),
|
||||
// Write Address channel
|
||||
.S_AWID (S_AXI_HP2_AWID),
|
||||
.S_AWADDR (S_AXI_HP2_AWADDR),
|
||||
.S_AWLEN (S_AXI_HP2_AWLEN),
|
||||
.S_AWSIZE (S_AXI_HP2_AWSIZE),
|
||||
.S_AWBURST (S_AXI_HP2_AWBURST),
|
||||
.S_AWLOCK (S_AXI_HP2_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_HP2_AWCACHE),
|
||||
.S_AWPROT (S_AXI_HP2_AWPROT),
|
||||
.S_AWVALID (S_AXI_HP2_AWVALID),
|
||||
.S_AWREADY (S_AXI_HP2_AWREADY),
|
||||
// Write Data channel signals.
|
||||
.S_WID (S_AXI_HP2_WID),
|
||||
.S_WDATA (S_AXI_HP2_WDATA),
|
||||
.S_WSTRB (S_AXI_HP2_WSTRB),
|
||||
.S_WLAST (S_AXI_HP2_WLAST),
|
||||
.S_WVALID (S_AXI_HP2_WVALID),
|
||||
.S_WREADY (S_AXI_HP2_WREADY),
|
||||
// Write Response channel signals.
|
||||
.S_BID (S_AXI_HP2_BID),
|
||||
.S_BRESP (S_AXI_HP2_BRESP),
|
||||
.S_BVALID (S_AXI_HP2_BVALID),
|
||||
.S_BREADY (S_AXI_HP2_BREADY),
|
||||
// Read Address channel signals.
|
||||
.S_ARID (S_AXI_HP2_ARID),
|
||||
.S_ARADDR (S_AXI_HP2_ARADDR),
|
||||
.S_ARLEN (S_AXI_HP2_ARLEN),
|
||||
.S_ARSIZE (S_AXI_HP2_ARSIZE),
|
||||
.S_ARBURST (S_AXI_HP2_ARBURST),
|
||||
.S_ARLOCK (S_AXI_HP2_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_HP2_ARCACHE),
|
||||
.S_ARPROT (S_AXI_HP2_ARPROT),
|
||||
.S_ARVALID (S_AXI_HP2_ARVALID),
|
||||
.S_ARREADY (S_AXI_HP2_ARREADY),
|
||||
// Read Data channel signals.
|
||||
.S_RID (S_AXI_HP2_RID),
|
||||
.S_RDATA (S_AXI_HP2_RDATA),
|
||||
.S_RRESP (S_AXI_HP2_RRESP),
|
||||
.S_RLAST (S_AXI_HP2_RLAST),
|
||||
.S_RVALID (S_AXI_HP2_RVALID),
|
||||
.S_RREADY (S_AXI_HP2_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_HP2_AWQOS),
|
||||
.S_ARQOS (S_AXI_HP2_ARQOS),
|
||||
// these are needed only for HP ports
|
||||
.S_RDISSUECAP1_EN (S_AXI_HP2_RDISSUECAP1_EN),
|
||||
.S_WRISSUECAP1_EN (S_AXI_HP2_WRISSUECAP1_EN),
|
||||
.S_RCOUNT (S_AXI_HP2_RCOUNT),
|
||||
.S_WCOUNT (S_AXI_HP2_WCOUNT),
|
||||
.S_RACOUNT (S_AXI_HP2_RACOUNT),
|
||||
.S_WACOUNT (S_AXI_HP2_WACOUNT),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_hp2),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_hp2),
|
||||
.WR_DATA (net_wr_data_hp2),
|
||||
.WR_DATA_STRB (net_wr_strb_hp2),
|
||||
.WR_ADDR (net_wr_addr_hp2),
|
||||
.WR_BYTES (net_wr_bytes_hp2),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_hp2),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_hp2),
|
||||
.WR_QOS (net_wr_qos_hp2),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_hp2),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_hp2),
|
||||
.RD_ADDR (net_rd_addr_hp2),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_hp2),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_hp2),
|
||||
.RD_BYTES (net_rd_bytes_hp2),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_hp2),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_hp2),
|
||||
.RD_QOS (net_rd_qos_hp2)
|
||||
|
||||
);
|
||||
|
||||
/* AXI Slave HP3 */
|
||||
processing_system7_vip_v1_0_17_afi_slave #( C_USE_S_AXI_HP3, // enable
|
||||
axi_hp3_name, // name
|
||||
C_S_AXI_HP3_DATA_WIDTH, // data width
|
||||
addr_width, /// address width
|
||||
axi_hp_id_width, // ID width
|
||||
C_S_AXI_HP3_BASEADDR, // slave base address
|
||||
C_S_AXI_HP3_HIGHADDR, // SLave size
|
||||
axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
|
||||
axi_slv_excl_support) // Exclusive access support
|
||||
S_AXI_HP3(.S_RESETN (net_axi_hp3_rstn),
|
||||
.S_ACLK (S_AXI_HP3_ACLK),
|
||||
// Write ADDRESS CHANNEL
|
||||
.S_AWID (S_AXI_HP3_AWID),
|
||||
.S_AWADDR (S_AXI_HP3_AWADDR),
|
||||
.S_AWLEN (S_AXI_HP3_AWLEN),
|
||||
.S_AWSIZE (S_AXI_HP3_AWSIZE),
|
||||
.S_AWBURST (S_AXI_HP3_AWBURST),
|
||||
.S_AWLOCK (S_AXI_HP3_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_HP3_AWCACHE),
|
||||
.S_AWPROT (S_AXI_HP3_AWPROT),
|
||||
.S_AWVALID (S_AXI_HP3_AWVALID),
|
||||
.S_AWREADY (S_AXI_HP3_AWREADY),
|
||||
// Write Data channel signals.
|
||||
.S_WID (S_AXI_HP3_WID),
|
||||
.S_WDATA (S_AXI_HP3_WDATA),
|
||||
.S_WSTRB (S_AXI_HP3_WSTRB),
|
||||
.S_WLAST (S_AXI_HP3_WLAST),
|
||||
.S_WVALID (S_AXI_HP3_WVALID),
|
||||
.S_WREADY (S_AXI_HP3_WREADY),
|
||||
// Write Response channel signals.
|
||||
.S_BID (S_AXI_HP3_BID),
|
||||
.S_BRESP (S_AXI_HP3_BRESP),
|
||||
.S_BVALID (S_AXI_HP3_BVALID),
|
||||
.S_BREADY (S_AXI_HP3_BREADY),
|
||||
// Read Address channel signals.
|
||||
.S_ARID (S_AXI_HP3_ARID),
|
||||
.S_ARADDR (S_AXI_HP3_ARADDR),
|
||||
.S_ARLEN (S_AXI_HP3_ARLEN),
|
||||
.S_ARSIZE (S_AXI_HP3_ARSIZE),
|
||||
.S_ARBURST (S_AXI_HP3_ARBURST),
|
||||
.S_ARLOCK (S_AXI_HP3_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_HP3_ARCACHE),
|
||||
.S_ARPROT (S_AXI_HP3_ARPROT),
|
||||
.S_ARVALID (S_AXI_HP3_ARVALID),
|
||||
.S_ARREADY (S_AXI_HP3_ARREADY),
|
||||
// Read Data channel signals.
|
||||
.S_RID (S_AXI_HP3_RID),
|
||||
.S_RDATA (S_AXI_HP3_RDATA),
|
||||
.S_RRESP (S_AXI_HP3_RRESP),
|
||||
.S_RLAST (S_AXI_HP3_RLAST),
|
||||
.S_RVALID (S_AXI_HP3_RVALID),
|
||||
.S_RREADY (S_AXI_HP3_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_HP3_AWQOS),
|
||||
.S_ARQOS (S_AXI_HP3_ARQOS),
|
||||
// these are needed only for HP ports
|
||||
.S_RDISSUECAP1_EN (S_AXI_HP3_RDISSUECAP1_EN),
|
||||
.S_WRISSUECAP1_EN (S_AXI_HP3_WRISSUECAP1_EN),
|
||||
.S_RCOUNT (S_AXI_HP3_RCOUNT),
|
||||
.S_WCOUNT (S_AXI_HP3_WCOUNT),
|
||||
.S_RACOUNT (S_AXI_HP3_RACOUNT),
|
||||
.S_WACOUNT (S_AXI_HP3_WACOUNT),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_hp3),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_hp3),
|
||||
.WR_DATA (net_wr_data_hp3),
|
||||
.WR_DATA_STRB (net_wr_strb_hp3),
|
||||
.WR_ADDR (net_wr_addr_hp3),
|
||||
.WR_BYTES (net_wr_bytes_hp3),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_hp3),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_hp3),
|
||||
.WR_QOS (net_wr_qos_hp3),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_hp3),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_hp3),
|
||||
.RD_ADDR (net_rd_addr_hp3),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_hp3),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_hp3),
|
||||
.RD_BYTES (net_rd_bytes_hp3),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_hp3),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_hp3),
|
||||
.RD_QOS (net_rd_qos_hp3)
|
||||
);
|
||||
+244
@@ -0,0 +1,244 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_17_local_params.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Parameters used in Zynq VIP
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
/* local */
|
||||
parameter m_axi_gp0_baseaddr = 32'h4000_0000;
|
||||
parameter m_axi_gp1_baseaddr = 32'h8000_0000;
|
||||
parameter m_axi_gp0_highaddr = 32'h7FFF_FFFF;
|
||||
parameter m_axi_gp1_highaddr = 32'hBFFF_FFFF;
|
||||
|
||||
parameter addr_width = 32; // maximum address width
|
||||
parameter data_width = 32; // maximum data width.
|
||||
parameter max_chars = 128; // max characters for file name
|
||||
parameter mem_width = data_width/8; /// memory width in bytes
|
||||
parameter shft_addr_bits = clogb2(mem_width); /// Address to be right shifted
|
||||
parameter int_width = 32; //integre width
|
||||
|
||||
/* for internal read/write APIs used for data transfers */
|
||||
parameter max_burst_len = 16; /// maximum brst length on axi
|
||||
parameter max_data_width = 64; // maximum data width for internal AXI bursts
|
||||
parameter max_burst_bits = (max_data_width * max_burst_len); // maximum data width for internal AXI bursts
|
||||
parameter max_burst_bytes = (max_burst_bits)/8; // maximum data bytes in each transfer
|
||||
parameter max_burst_bytes_width = clogb2(max_burst_bytes); // maximum data width for internal AXI bursts
|
||||
|
||||
parameter max_registers = 32;
|
||||
parameter max_regs_width = clogb2(max_registers);
|
||||
|
||||
parameter REG_MEM = 2'b00, DDR_MEM = 2'b01, OCM_MEM = 2'b10, INVALID_MEM_TYPE = 2'b11;
|
||||
|
||||
/* Interrupt bits supported */
|
||||
parameter irq_width = 16;
|
||||
|
||||
/* GP Master0 & Master1 address decode */
|
||||
parameter GP_M0 = 2'b01;
|
||||
parameter GP_M1 = 2'b10;
|
||||
|
||||
parameter ALL_RANDOM= 2'b00;
|
||||
parameter ALL_ZEROS = 2'b01;
|
||||
parameter ALL_ONES = 2'b10;
|
||||
|
||||
parameter ddr_start_addr = 32'h0008_0000;
|
||||
parameter ddr_end_addr = 32'h7FFF_FFFF;
|
||||
|
||||
parameter ocm_start_addr = 32'h0000_0000;
|
||||
parameter ocm_end_addr = 32'h0003_FFFF;
|
||||
parameter high_ocm_start_addr = 32'hFFFC_0000;
|
||||
parameter high_ocm_end_addr = 32'hFFFF_FFFF;
|
||||
parameter ocm_low_addr = 32'hFFFF_0000;
|
||||
|
||||
parameter reg_start_addr = 32'hE000_0000;
|
||||
parameter reg_end_addr = 32'hF8F0_2F80;
|
||||
|
||||
|
||||
/* for Master port APIs and AXI protocol related signal widths*/
|
||||
parameter axi_burst_len = 16;
|
||||
parameter axi_len_width = clogb2(axi_burst_len);
|
||||
parameter axi_size_width = 3;
|
||||
parameter axi_brst_type_width = 2;
|
||||
parameter axi_lock_width = 2;
|
||||
parameter axi_cache_width = 4;
|
||||
parameter axi_prot_width = 3;
|
||||
parameter axi_rsp_width = 2;
|
||||
parameter axi_mgp_data_width = 32;
|
||||
parameter axi_mgp_id_width = 12;
|
||||
parameter axi_mgp_outstanding = 8;
|
||||
parameter axi_mgp_wr_id = 12'hC00;
|
||||
parameter axi_mgp_rd_id = 12'hC0C;
|
||||
parameter axi_mgp0_name = "M_AXI_GP0";
|
||||
parameter axi_mgp1_name = "M_AXI_GP1";
|
||||
parameter axi_qos_width = 4;
|
||||
parameter max_transfer_bytes = 256; // For Master APIs.
|
||||
parameter max_transfer_bytes_width = clogb2(max_transfer_bytes); // For Master APIs.
|
||||
|
||||
|
||||
/* for GP slave ports*/
|
||||
parameter axi_sgp_data_width = 32;
|
||||
parameter axi_sgp_id_width = 6;
|
||||
parameter axi_sgp_rd_outstanding = 8;
|
||||
parameter axi_sgp_wr_outstanding = 8;
|
||||
parameter axi_sgp_outstanding = axi_sgp_rd_outstanding + axi_sgp_wr_outstanding;
|
||||
parameter axi_sgp0_name = "S_AXI_GP0";
|
||||
parameter axi_sgp1_name = "S_AXI_GP1";
|
||||
|
||||
/* for ACP slave ports*/
|
||||
parameter axi_acp_data_width = 64;
|
||||
parameter axi_acp_id_width = 3;
|
||||
parameter axi_acp_rd_outstanding = 7;
|
||||
parameter axi_acp_wr_outstanding = 3;
|
||||
parameter axi_acp_outstanding = axi_acp_rd_outstanding + axi_acp_wr_outstanding;
|
||||
parameter axi_acp_name = "S_AXI_ACP";
|
||||
|
||||
/* for HP slave ports*/
|
||||
parameter axi_hp_id_width = 6;
|
||||
parameter axi_hp_outstanding = 256; /// dynamic based on RCOUNT, WCOUNT ..
|
||||
parameter axi_hp0_name = "S_AXI_HP0";
|
||||
parameter axi_hp1_name = "S_AXI_HP1";
|
||||
parameter axi_hp2_name = "S_AXI_HP2";
|
||||
parameter axi_hp3_name = "S_AXI_HP3";
|
||||
|
||||
|
||||
parameter axi_slv_excl_support = 0; // For Slave ports EXCL access is not supported
|
||||
parameter axi_mst_excl_support = 1; // For Master ports EXCL access is supported
|
||||
|
||||
/* AXI transfer types */
|
||||
parameter AXI_FIXED = 2'b00;
|
||||
parameter AXI_INCR = 2'b01;
|
||||
parameter AXI_WRAP = 2'b10;
|
||||
|
||||
/* Exclusive Access */
|
||||
parameter AXI_NRML = 2'b00;
|
||||
parameter AXI_EXCL = 2'b01;
|
||||
parameter AXI_LOCK = 2'b10;
|
||||
|
||||
/* AXI Response types */
|
||||
parameter AXI_OK = 2'b00;
|
||||
parameter AXI_EXCL_OK = 2'b01;
|
||||
parameter AXI_SLV_ERR = 2'b10;
|
||||
parameter AXI_DEC_ERR = 2'b11;
|
||||
|
||||
function automatic integer clogb2;
|
||||
input [31:0] value;
|
||||
begin
|
||||
value = value - 1;
|
||||
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin
|
||||
value = value >> 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
/* needed only for AFI modules and axi_slave modules for internal WRITE FIFOs and RESP FIFOs and interconnect fifo models */
|
||||
/* WR FIFO data */
|
||||
// parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1);
|
||||
// parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1);
|
||||
// parameter wr_fifo_data_bits = ((data_bus_width/8)*axi_burst_len) + (data_bus_width*axi_burst_len) + axi_qos_width + addr_width + (max_burst_bytes_width+1);
|
||||
// parameter wr_bytes_lsb = 0;
|
||||
// parameter wr_bytes_msb = max_burst_bytes_width;
|
||||
// parameter wr_addr_lsb = wr_bytes_msb + 1;
|
||||
// parameter wr_addr_msb = wr_addr_lsb + addr_width-1;
|
||||
// parameter wr_data_lsb = wr_addr_msb + 1;
|
||||
// parameter wr_data_msb = wr_data_lsb + max_burst_bits-1;
|
||||
// parameter wr_data_msb = wr_data_lsb + (data_bus_width*axi_burst_len)-1;
|
||||
// parameter wr_qos_lsb = wr_data_msb + 1;
|
||||
// `parameter wr_qos_msb = wr_qos_lsb + axi_qos_width-1;
|
||||
|
||||
/* WR AFI FIFO data */
|
||||
/* ID - 1071:1066
|
||||
Resp - 1065:1064
|
||||
data - 1063:40
|
||||
address - 39:8
|
||||
valid_bytes - 7:0
|
||||
*/
|
||||
// parameter wr_afi_fifo_data_bits = axi_qos_width + axi_len_width + axi_hp_id_width + axi_rsp_width + max_burst_bits + addr_width + (max_burst_bytes_width+1);
|
||||
// parameter wr_afi_bytes_lsb = 0;
|
||||
// parameter wr_afi_bytes_msb = max_burst_bytes_width;
|
||||
// parameter wr_afi_addr_lsb = wr_afi_bytes_msb + 1;
|
||||
// parameter wr_afi_addr_msb = wr_afi_addr_lsb + addr_width-1;
|
||||
// parameter wr_afi_data_lsb = wr_afi_addr_msb + 1;
|
||||
// parameter wr_afi_rsp_msb = wr_afi_rsp_lsb + axi_rsp_width-1;
|
||||
// parameter wr_afi_id_lsb = wr_afi_rsp_msb + 1;
|
||||
// parameter wr_afi_id_msb = wr_afi_id_lsb + axi_hp_id_width-1;
|
||||
// parameter wr_afi_ln_lsb = wr_afi_id_msb + 1;
|
||||
// parameter wr_afi_ln_msb = wr_afi_ln_lsb + axi_len_width-1;
|
||||
// parameter wr_afi_qos_lsb = wr_afi_ln_msb + 1;
|
||||
// parameter wr_afi_qos_msb = wr_afi_qos_lsb + axi_qos_width-1;
|
||||
|
||||
|
||||
parameter afi_fifo_size = 1024; /// AFI FIFO is stored as 1024-bytes
|
||||
parameter afi_fifo_databits = 64; /// AFI FIFO is stored as 64-bits i.e 8 bytes per location (8 bytes(64-bits) * 128 locations = 1024 bytes)
|
||||
parameter afi_fifo_locations= afi_fifo_size/(afi_fifo_databits/8); /// AFI FIFO is stored as 128-locations with 8 bytes per location
|
||||
|
||||
/* for interconnect fifo models */
|
||||
parameter intr_max_outstanding = 8;
|
||||
parameter intr_cnt_width = clogb2(intr_max_outstanding)+1;
|
||||
parameter rd_info_bits = addr_width + axi_size_width + axi_brst_type_width + axi_len_width + axi_hp_id_width + axi_rsp_width + (max_burst_bytes_width+1);
|
||||
parameter rd_afi_fifo_bits = max_burst_bits + rd_info_bits ;
|
||||
|
||||
//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes
|
||||
parameter rd_afi_bytes_lsb = 0;
|
||||
parameter rd_afi_bytes_msb = max_burst_bytes_width;
|
||||
parameter rd_afi_rsp_lsb = rd_afi_bytes_msb + 1;
|
||||
parameter rd_afi_rsp_msb = rd_afi_rsp_lsb + axi_rsp_width-1;
|
||||
parameter rd_afi_id_lsb = rd_afi_rsp_msb + 1;
|
||||
parameter rd_afi_id_msb = rd_afi_id_lsb + axi_hp_id_width-1;
|
||||
parameter rd_afi_ln_lsb = rd_afi_id_msb + 1;
|
||||
parameter rd_afi_ln_msb = rd_afi_ln_lsb + axi_len_width-1;
|
||||
parameter rd_afi_brst_lsb = rd_afi_ln_msb + 1;
|
||||
parameter rd_afi_brst_msb = rd_afi_brst_lsb + axi_brst_type_width-1;
|
||||
parameter rd_afi_siz_lsb = rd_afi_brst_msb + 1;
|
||||
parameter rd_afi_siz_msb = rd_afi_siz_lsb + axi_size_width-1;
|
||||
parameter rd_afi_addr_lsb = rd_afi_siz_msb + 1;
|
||||
parameter rd_afi_addr_msb = rd_afi_addr_lsb + addr_width-1;
|
||||
parameter rd_afi_data_lsb = rd_afi_addr_msb + 1;
|
||||
parameter rd_afi_data_msb = rd_afi_data_lsb + max_burst_bits-1;
|
||||
|
||||
|
||||
/* Latency types */
|
||||
parameter BEST_CASE = 0;
|
||||
parameter AVG_CASE = 1;
|
||||
parameter WORST_CASE = 2;
|
||||
parameter RANDOM_CASE = 3;
|
||||
|
||||
/* Latency Parameters ACP */
|
||||
parameter acp_wr_min = 21;
|
||||
parameter acp_wr_avg = 16;
|
||||
parameter acp_wr_max = 27;
|
||||
parameter acp_rd_min = 34;
|
||||
parameter acp_rd_avg = 125;
|
||||
parameter acp_rd_max = 130;
|
||||
|
||||
/* Latency Parameters GP */
|
||||
parameter gp_wr_min = 21;
|
||||
parameter gp_wr_avg = 16;
|
||||
parameter gp_wr_max = 46;
|
||||
parameter gp_rd_min = 38;
|
||||
parameter gp_rd_avg = 125;
|
||||
parameter gp_rd_max = 130;
|
||||
|
||||
/* Latency Parameters HP */
|
||||
parameter afi_wr_min = 37;
|
||||
parameter afi_wr_avg = 41;
|
||||
parameter afi_wr_max = 42;
|
||||
parameter afi_rd_min = 41;
|
||||
parameter afi_rd_avg = 221;
|
||||
parameter afi_rd_max = 229;
|
||||
|
||||
/* ID VALID and INVALID */
|
||||
parameter secure_access_enabled = 0;
|
||||
parameter id_invalid = 0;
|
||||
parameter id_valid = 1;
|
||||
|
||||
/* Display */
|
||||
parameter DISP_INFO = "*ZYNQ_VIP_INFO";
|
||||
parameter DISP_WARN = "*ZYNQ_VIP_WARNING";
|
||||
parameter DISP_ERR = "*ZYNQ_VIP_ERROR";
|
||||
parameter DISP_INT_INFO = "ZYNQ_VIP_INT_INFO";
|
||||
|
||||
parameter all_strb_valid = 2048'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
|
||||
|
||||
+2924
File diff suppressed because it is too large
Load Diff
+10519
File diff suppressed because it is too large
Load Diff
+433
@@ -0,0 +1,433 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_17_unused_ports.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Semantic checks for unused ports.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* CAN */
|
||||
assign CAN0_PHY_TX = 0;
|
||||
assign CAN1_PHY_TX = 0;
|
||||
always @(CAN0_PHY_RX or CAN1_PHY_RX)
|
||||
begin
|
||||
if(CAN0_PHY_RX | CAN1_PHY_RX)
|
||||
$display("[%0d] : %0s : CAN Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* ETHERNET */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign ENET0_GMII_TX_EN = 0;
|
||||
assign ENET0_GMII_TX_ER = 0;
|
||||
assign ENET0_MDIO_MDC = 0;
|
||||
assign ENET0_MDIO_O = 0; /// confirm
|
||||
assign ENET0_MDIO_T = 0;
|
||||
assign ENET0_PTP_DELAY_REQ_RX = 0;
|
||||
assign ENET0_PTP_DELAY_REQ_TX = 0;
|
||||
assign ENET0_PTP_PDELAY_REQ_RX = 0;
|
||||
assign ENET0_PTP_PDELAY_REQ_TX = 0;
|
||||
assign ENET0_PTP_PDELAY_RESP_RX = 0;
|
||||
assign ENET0_PTP_PDELAY_RESP_TX = 0;
|
||||
assign ENET0_PTP_SYNC_FRAME_RX = 0;
|
||||
assign ENET0_PTP_SYNC_FRAME_TX = 0;
|
||||
assign ENET0_SOF_RX = 0;
|
||||
assign ENET0_SOF_TX = 0;
|
||||
assign ENET0_GMII_TXD = 0;
|
||||
always@(ENET0_GMII_COL or ENET0_GMII_CRS or ENET0_EXT_INTIN or
|
||||
ENET0_GMII_RX_CLK or ENET0_GMII_RX_DV or ENET0_GMII_RX_ER or
|
||||
ENET0_GMII_TX_CLK or ENET0_MDIO_I or ENET0_GMII_RXD)
|
||||
begin
|
||||
if(ENET0_GMII_COL | ENET0_GMII_CRS | ENET0_EXT_INTIN |
|
||||
ENET0_GMII_RX_CLK | ENET0_GMII_RX_DV | ENET0_GMII_RX_ER |
|
||||
ENET0_GMII_TX_CLK | ENET0_MDIO_I )
|
||||
$display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign ENET1_GMII_TX_EN = 0;
|
||||
assign ENET1_GMII_TX_ER = 0;
|
||||
assign ENET1_MDIO_MDC = 0;
|
||||
assign ENET1_MDIO_O = 0;/// confirm
|
||||
assign ENET1_MDIO_T = 0;
|
||||
assign ENET1_PTP_DELAY_REQ_RX = 0;
|
||||
assign ENET1_PTP_DELAY_REQ_TX = 0;
|
||||
assign ENET1_PTP_PDELAY_REQ_RX = 0;
|
||||
assign ENET1_PTP_PDELAY_REQ_TX = 0;
|
||||
assign ENET1_PTP_PDELAY_RESP_RX = 0;
|
||||
assign ENET1_PTP_PDELAY_RESP_TX = 0;
|
||||
assign ENET1_PTP_SYNC_FRAME_RX = 0;
|
||||
assign ENET1_PTP_SYNC_FRAME_TX = 0;
|
||||
assign ENET1_SOF_RX = 0;
|
||||
assign ENET1_SOF_TX = 0;
|
||||
assign ENET1_GMII_TXD = 0;
|
||||
always@(ENET1_GMII_COL or ENET1_GMII_CRS or ENET1_EXT_INTIN or
|
||||
ENET1_GMII_RX_CLK or ENET1_GMII_RX_DV or ENET1_GMII_RX_ER or
|
||||
ENET1_GMII_TX_CLK or ENET1_MDIO_I or ENET1_GMII_RXD)
|
||||
begin
|
||||
if(ENET1_GMII_COL | ENET1_GMII_CRS | ENET1_EXT_INTIN |
|
||||
ENET1_GMII_RX_CLK | ENET1_GMII_RX_DV | ENET1_GMII_RX_ER |
|
||||
ENET1_GMII_TX_CLK | ENET1_MDIO_I )
|
||||
$display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* GPIO */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign GPIO_O = 0;
|
||||
assign GPIO_T = 0;
|
||||
always@(GPIO_I)
|
||||
begin
|
||||
// if(GPIO_I !== 0)
|
||||
// $display("[%0d] : %0s : GPIO Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* I2C */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign I2C0_SDA_O = 0;
|
||||
assign I2C0_SDA_T = 0;
|
||||
assign I2C0_SCL_O = 0;
|
||||
assign I2C0_SCL_T = 0;
|
||||
assign I2C1_SDA_O = 0;
|
||||
assign I2C1_SDA_T = 0;
|
||||
assign I2C1_SCL_O = 0;
|
||||
assign I2C1_SCL_T = 0;
|
||||
always@(I2C0_SDA_I or I2C0_SCL_I or I2C1_SDA_I or I2C1_SCL_I )
|
||||
begin
|
||||
if(I2C0_SDA_I | I2C0_SCL_I | I2C1_SDA_I | I2C1_SCL_I)
|
||||
$display("[%0d] : %0s : I2C Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* JTAG */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign PJTAG_TD_T = 0;
|
||||
assign PJTAG_TD_O = 0;
|
||||
always@(PJTAG_TCK or PJTAG_TMS or PJTAG_TD_I)
|
||||
begin
|
||||
if(PJTAG_TCK | PJTAG_TMS | PJTAG_TD_I)
|
||||
$display("[%0d] : %0s : JTAG Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* SDIO */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign SDIO0_CLK = 0;
|
||||
assign SDIO0_CMD_O = 0;
|
||||
assign SDIO0_CMD_T = 0;
|
||||
assign SDIO0_DATA_O = 0;
|
||||
assign SDIO0_DATA_T = 0;
|
||||
assign SDIO0_LED = 0;
|
||||
assign SDIO0_BUSPOW = 0;
|
||||
assign SDIO0_BUSVOLT = 0;
|
||||
always@(SDIO0_CLK_FB or SDIO0_CMD_I or SDIO0_DATA_I or SDIO0_CDN or SDIO0_WP )
|
||||
begin
|
||||
if(SDIO0_CLK_FB | SDIO0_CMD_I | SDIO0_CDN | SDIO0_WP )
|
||||
$display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign SDIO1_CLK = 0;
|
||||
assign SDIO1_CMD_O = 0;
|
||||
assign SDIO1_CMD_T = 0;
|
||||
assign SDIO1_DATA_O = 0;
|
||||
assign SDIO1_DATA_T = 0;
|
||||
assign SDIO1_LED = 0;
|
||||
assign SDIO1_BUSPOW = 0;
|
||||
assign SDIO1_BUSVOLT = 0;
|
||||
always@(SDIO1_CLK_FB or SDIO1_CMD_I or SDIO1_DATA_I or SDIO1_CDN or SDIO1_WP )
|
||||
begin
|
||||
if(SDIO1_CLK_FB | SDIO1_CMD_I | SDIO1_CDN | SDIO1_WP )
|
||||
$display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* SPI */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign SPI0_SCLK_O = 0;
|
||||
assign SPI0_SCLK_T = 0;
|
||||
assign SPI0_MOSI_O = 0;
|
||||
assign SPI0_MOSI_T = 0;
|
||||
assign SPI0_MISO_O = 0;
|
||||
assign SPI0_MISO_T = 0;
|
||||
assign SPI0_SS_O = 0; /// confirm
|
||||
assign SPI0_SS1_O = 0;/// confirm
|
||||
assign SPI0_SS2_O = 0;/// confirm
|
||||
assign SPI0_SS_T = 0;
|
||||
always@(SPI0_SCLK_I or SPI0_MOSI_I or SPI0_MISO_I or SPI0_SS_I)
|
||||
begin
|
||||
if(SPI0_SCLK_I | SPI0_MOSI_I | SPI0_MISO_I | SPI0_SS_I)
|
||||
$display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign SPI1_SCLK_O = 0;
|
||||
assign SPI1_SCLK_T = 0;
|
||||
assign SPI1_MOSI_O = 0;
|
||||
assign SPI1_MOSI_T = 0;
|
||||
assign SPI1_MISO_O = 0;
|
||||
assign SPI1_MISO_T = 0;
|
||||
assign SPI1_SS_O = 0;
|
||||
assign SPI1_SS1_O = 0;
|
||||
assign SPI1_SS2_O = 0;
|
||||
assign SPI1_SS_T = 0;
|
||||
always@(SPI1_SCLK_I or SPI1_MOSI_I or SPI1_MISO_I or SPI1_SS_I)
|
||||
begin
|
||||
if(SPI1_SCLK_I | SPI1_MOSI_I | SPI1_MISO_I | SPI1_SS_I)
|
||||
$display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* UART */
|
||||
/* ------------------------------------------- */
|
||||
/// confirm
|
||||
assign UART0_DTRN = 0;
|
||||
assign UART0_RTSN = 0;
|
||||
assign UART0_TX = 0;
|
||||
always@(UART0_CTSN or UART0_DCDN or UART0_DSRN or UART0_RIN or UART0_RX)
|
||||
begin
|
||||
if(UART0_CTSN | UART0_DCDN | UART0_DSRN | UART0_RIN | UART0_RX)
|
||||
$display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign UART1_DTRN = 0;
|
||||
assign UART1_RTSN = 0;
|
||||
assign UART1_TX = 0;
|
||||
always@(UART1_CTSN or UART1_DCDN or UART1_DSRN or UART1_RIN or UART1_RX)
|
||||
begin
|
||||
if(UART1_CTSN | UART1_DCDN | UART1_DSRN | UART1_RIN | UART1_RX)
|
||||
$display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* TTC */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign TTC0_WAVE0_OUT = 0;
|
||||
assign TTC0_WAVE1_OUT = 0;
|
||||
assign TTC0_WAVE2_OUT = 0;
|
||||
always@(TTC0_CLK0_IN or TTC0_CLK1_IN or TTC0_CLK2_IN)
|
||||
begin
|
||||
if(TTC0_CLK0_IN | TTC0_CLK1_IN | TTC0_CLK2_IN)
|
||||
$display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign TTC1_WAVE0_OUT = 0;
|
||||
assign TTC1_WAVE1_OUT = 0;
|
||||
assign TTC1_WAVE2_OUT = 0;
|
||||
always@(TTC1_CLK0_IN or TTC1_CLK1_IN or TTC1_CLK2_IN)
|
||||
begin
|
||||
if(TTC1_CLK0_IN | TTC1_CLK1_IN | TTC1_CLK2_IN)
|
||||
$display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* WDT */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign WDT_RST_OUT = 0;
|
||||
always@(WDT_CLK_IN)
|
||||
begin
|
||||
if(WDT_CLK_IN)
|
||||
$display("[%0d] : %0s : WDT Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* TRACE */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign TRACE_CTL = 0;
|
||||
assign TRACE_DATA = 0;
|
||||
always@(TRACE_CLK)
|
||||
begin
|
||||
if(TRACE_CLK)
|
||||
$display("[%0d] : %0s : TRACE Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* USB */
|
||||
/* ------------------------------------------- */
|
||||
assign USB0_PORT_INDCTL = 0;
|
||||
assign USB0_VBUS_PWRSELECT = 0;
|
||||
always@(USB0_VBUS_PWRFAULT)
|
||||
begin
|
||||
if(USB0_VBUS_PWRFAULT)
|
||||
$display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign USB1_PORT_INDCTL = 0;
|
||||
assign USB1_VBUS_PWRSELECT = 0;
|
||||
always@(USB1_VBUS_PWRFAULT)
|
||||
begin
|
||||
if(USB1_VBUS_PWRFAULT)
|
||||
$display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
always@(SRAM_INTIN)
|
||||
begin
|
||||
if(SRAM_INTIN)
|
||||
$display("[%0d] : %0s : SRAM_INTIN is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* DMA */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign DMA0_DATYPE = 0;
|
||||
assign DMA0_DAVALID = 0;
|
||||
assign DMA0_DRREADY = 0;
|
||||
assign DMA0_RSTN = 0;
|
||||
always@(DMA0_ACLK or DMA0_DAREADY or DMA0_DRLAST or DMA0_DRVALID or DMA0_DRTYPE)
|
||||
begin
|
||||
if(DMA0_ACLK | DMA0_DAREADY | DMA0_DRLAST | DMA0_DRVALID | DMA0_DRTYPE)
|
||||
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign DMA1_DATYPE = 0;
|
||||
assign DMA1_DAVALID = 0;
|
||||
assign DMA1_DRREADY = 0;
|
||||
assign DMA1_RSTN = 0;
|
||||
always@(DMA1_ACLK or DMA1_DAREADY or DMA1_DRLAST or DMA1_DRVALID or DMA1_DRTYPE)
|
||||
begin
|
||||
if(DMA1_ACLK | DMA1_DAREADY | DMA1_DRLAST | DMA1_DRVALID | DMA1_DRTYPE)
|
||||
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign DMA2_DATYPE = 0;
|
||||
assign DMA2_DAVALID = 0;
|
||||
assign DMA2_DRREADY = 0;
|
||||
assign DMA2_RSTN = 0;
|
||||
always@(DMA2_ACLK or DMA2_DAREADY or DMA2_DRLAST or DMA2_DRVALID or DMA2_DRTYPE)
|
||||
begin
|
||||
if(DMA2_ACLK | DMA2_DAREADY | DMA2_DRLAST | DMA2_DRVALID | DMA2_DRTYPE)
|
||||
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign DMA3_DATYPE = 0;
|
||||
assign DMA3_DAVALID = 0;
|
||||
assign DMA3_DRREADY = 0;
|
||||
assign DMA3_RSTN = 0;
|
||||
always@(DMA3_ACLK or DMA3_DAREADY or DMA3_DRLAST or DMA3_DRVALID or DMA3_DRTYPE)
|
||||
begin
|
||||
if(DMA3_ACLK | DMA3_DAREADY | DMA3_DRLAST | DMA3_DRVALID | DMA3_DRTYPE)
|
||||
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* FTM */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign FTMT_F2P_TRIGACK = 0;
|
||||
assign FTMT_P2F_TRIG = 0;
|
||||
assign FTMT_P2F_DEBUG = 0;
|
||||
always@(FTMD_TRACEIN_DATA or FTMD_TRACEIN_VALID or FTMD_TRACEIN_CLK or
|
||||
FTMD_TRACEIN_ATID or FTMT_F2P_TRIG or FTMT_F2P_DEBUG or FTMT_P2F_TRIGACK)
|
||||
begin
|
||||
if(FTMD_TRACEIN_DATA | FTMD_TRACEIN_VALID | FTMD_TRACEIN_CLK | FTMD_TRACEIN_ATID | FTMT_F2P_TRIG | FTMT_F2P_DEBUG | FTMT_P2F_TRIGACK)
|
||||
$display("[%0d] : %0s : FTM Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* EVENT */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign EVENT_EVENTO = 0;
|
||||
assign EVENT_STANDBYWFE = 0;
|
||||
assign EVENT_STANDBYWFI = 0;
|
||||
always@(EVENT_EVENTI)
|
||||
begin
|
||||
if(EVENT_EVENTI)
|
||||
$display("[%0d] : %0s : EVENT Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* MIO */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
always@(MIO)
|
||||
begin
|
||||
// if(MIO !== 0)
|
||||
// $display("[%0d] : %0s : MIO is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* FCLK_TRIG */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
always@(FCLK_CLKTRIG3_N or FCLK_CLKTRIG2_N or FCLK_CLKTRIG1_N or FCLK_CLKTRIG0_N )
|
||||
begin
|
||||
if(FCLK_CLKTRIG3_N | FCLK_CLKTRIG2_N | FCLK_CLKTRIG1_N | FCLK_CLKTRIG0_N )
|
||||
$display("[%0d] : %0s : FCLK_TRIG is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* MISC */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
always@(FPGA_IDLE_N)
|
||||
begin
|
||||
if(FPGA_IDLE_N)
|
||||
$display("[%0d] : %0s : FPGA_IDLE_N is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
always@(DDR_ARB)
|
||||
begin
|
||||
// if(DDR_ARB !== 0)
|
||||
// $display("[%0d] : %0s : DDR_ARB is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
always@(Core0_nFIQ or Core0_nIRQ or Core1_nFIQ or Core1_nIRQ )
|
||||
begin
|
||||
if(Core0_nFIQ | Core0_nIRQ | Core1_nFIQ | Core1_nIRQ)
|
||||
$display("[%0d] : %0s : CORE FIQ,IRQ is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* DDR */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign DDR_WEB = 0;
|
||||
always@(DDR_Clk or DDR_CS_n)
|
||||
begin
|
||||
if(!DDR_CS_n)
|
||||
$display("[%0d] : %0s : EXTERNAL DDR is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* IRQ_P2F */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign IRQ_P2F_DMAC_ABORT = 0;
|
||||
assign IRQ_P2F_DMAC0 = 0;
|
||||
assign IRQ_P2F_DMAC1 = 0;
|
||||
assign IRQ_P2F_DMAC2 = 0;
|
||||
assign IRQ_P2F_DMAC3 = 0;
|
||||
assign IRQ_P2F_DMAC4 = 0;
|
||||
assign IRQ_P2F_DMAC5 = 0;
|
||||
assign IRQ_P2F_DMAC6 = 0;
|
||||
assign IRQ_P2F_DMAC7 = 0;
|
||||
assign IRQ_P2F_SMC = 0;
|
||||
assign IRQ_P2F_QSPI = 0;
|
||||
assign IRQ_P2F_CTI = 0;
|
||||
assign IRQ_P2F_GPIO = 0;
|
||||
assign IRQ_P2F_USB0 = 0;
|
||||
assign IRQ_P2F_ENET0 = 0;
|
||||
assign IRQ_P2F_ENET_WAKE0 = 0;
|
||||
assign IRQ_P2F_SDIO0 = 0;
|
||||
assign IRQ_P2F_I2C0 = 0;
|
||||
assign IRQ_P2F_SPI0 = 0;
|
||||
assign IRQ_P2F_UART0 = 0;
|
||||
assign IRQ_P2F_CAN0 = 0;
|
||||
assign IRQ_P2F_USB1 = 0;
|
||||
assign IRQ_P2F_ENET1 = 0;
|
||||
assign IRQ_P2F_ENET_WAKE1 = 0;
|
||||
assign IRQ_P2F_SDIO1 = 0;
|
||||
assign IRQ_P2F_I2C1 = 0;
|
||||
assign IRQ_P2F_SPI1 = 0;
|
||||
assign IRQ_P2F_UART1 = 0;
|
||||
assign IRQ_P2F_CAN1 = 0;
|
||||
+13885
File diff suppressed because it is too large
Load Diff
+409
@@ -0,0 +1,409 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
|
||||
//--
|
||||
//-- This file contains confidential and proprietary information
|
||||
//-- of Xilinx, Inc. and is protected under U.S. and
|
||||
//-- international copyright and other intellectual property
|
||||
//-- laws.
|
||||
//--
|
||||
//-- DISCLAIMER
|
||||
//-- This disclaimer is not a license and does not grant any
|
||||
//-- rights to the materials distributed herewith. Except as
|
||||
//-- otherwise provided in a valid license issued to you by
|
||||
//-- Xilinx, and to the maximum extent permitted by applicable
|
||||
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
//-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
//-- including negligence, or under any other theory of
|
||||
//-- liability) for any loss or damage of any kind or nature
|
||||
//-- related to, arising under or in connection with these
|
||||
//-- materials, including for any direct, or any indirect,
|
||||
//-- special, incidental, or consequential loss or damage
|
||||
//-- (including loss of data, profits, goodwill, or any type of
|
||||
//-- loss or damage suffered as a result of any action brought
|
||||
//-- by a third party) even if such damage or loss was
|
||||
//-- reasonably foreseeable or Xilinx had been advised of the
|
||||
//-- possibility of the same.
|
||||
//--
|
||||
//-- CRITICAL APPLICATIONS
|
||||
//-- Xilinx products are not designed or intended to be fail-
|
||||
//-- safe, or for use in any application requiring fail-safe
|
||||
//-- performance, such as life-support or safety devices or
|
||||
//-- systems, Class III medical devices, nuclear facilities,
|
||||
//-- applications related to the deployment of airbags, or any
|
||||
//-- other applications that could lead to death, personal
|
||||
//-- injury, or severe property or environmental damage
|
||||
//-- (individually and collectively, "Critical
|
||||
//-- Applications"). Customer assumes the sole risk and
|
||||
//-- liability of any use of Xilinx products in Critical
|
||||
//-- Applications, subject only to applicable laws and
|
||||
//-- regulations governing limitations on product liability.
|
||||
//--
|
||||
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
//-- PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Description: ACP Transaction Checker
|
||||
//
|
||||
// Check for optimized ACP transactions and flag if they are broken.
|
||||
//
|
||||
//
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// atc
|
||||
// aw_atc
|
||||
// w_atc
|
||||
// b_atc
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
module processing_system7_v5_5_atc #
|
||||
(
|
||||
parameter C_FAMILY = "rtl",
|
||||
// FPGA Family. Current version: virtex6, spartan6 or later.
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
// Width of all ID signals on SI and MI side of checker.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
// Width of all ADDR signals on SI and MI side of checker.
|
||||
// Range: 32.
|
||||
parameter integer C_AXI_DATA_WIDTH = 64,
|
||||
// Width of all DATA signals on SI and MI side of checker.
|
||||
// Range: 64.
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 1,
|
||||
// Width of AWUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_ARUSER_WIDTH = 1,
|
||||
// Width of ARUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_WUSER_WIDTH = 1,
|
||||
// Width of WUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_RUSER_WIDTH = 1,
|
||||
// Width of RUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_BUSER_WIDTH = 1
|
||||
// Width of BUSER signals.
|
||||
// Range: >= 1.
|
||||
)
|
||||
(
|
||||
// Global Signals
|
||||
input wire ACLK,
|
||||
input wire ARESETN,
|
||||
|
||||
// Slave Interface Write Address Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
|
||||
input wire [4-1:0] S_AXI_AWLEN,
|
||||
input wire [3-1:0] S_AXI_AWSIZE,
|
||||
input wire [2-1:0] S_AXI_AWBURST,
|
||||
input wire [2-1:0] S_AXI_AWLOCK,
|
||||
input wire [4-1:0] S_AXI_AWCACHE,
|
||||
input wire [3-1:0] S_AXI_AWPROT,
|
||||
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
|
||||
input wire S_AXI_AWVALID,
|
||||
output wire S_AXI_AWREADY,
|
||||
// Slave Interface Write Data Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
|
||||
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
|
||||
input wire S_AXI_WLAST,
|
||||
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
|
||||
input wire S_AXI_WVALID,
|
||||
output wire S_AXI_WREADY,
|
||||
// Slave Interface Write Response Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
|
||||
output wire [2-1:0] S_AXI_BRESP,
|
||||
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
|
||||
output wire S_AXI_BVALID,
|
||||
input wire S_AXI_BREADY,
|
||||
// Slave Interface Read Address Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
|
||||
input wire [4-1:0] S_AXI_ARLEN,
|
||||
input wire [3-1:0] S_AXI_ARSIZE,
|
||||
input wire [2-1:0] S_AXI_ARBURST,
|
||||
input wire [2-1:0] S_AXI_ARLOCK,
|
||||
input wire [4-1:0] S_AXI_ARCACHE,
|
||||
input wire [3-1:0] S_AXI_ARPROT,
|
||||
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
|
||||
input wire S_AXI_ARVALID,
|
||||
output wire S_AXI_ARREADY,
|
||||
// Slave Interface Read Data Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
|
||||
output wire [2-1:0] S_AXI_RRESP,
|
||||
output wire S_AXI_RLAST,
|
||||
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
|
||||
output wire S_AXI_RVALID,
|
||||
input wire S_AXI_RREADY,
|
||||
|
||||
// Master Interface Write Address Port
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
|
||||
output wire [4-1:0] M_AXI_AWLEN,
|
||||
output wire [3-1:0] M_AXI_AWSIZE,
|
||||
output wire [2-1:0] M_AXI_AWBURST,
|
||||
output wire [2-1:0] M_AXI_AWLOCK,
|
||||
output wire [4-1:0] M_AXI_AWCACHE,
|
||||
output wire [3-1:0] M_AXI_AWPROT,
|
||||
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
|
||||
output wire M_AXI_AWVALID,
|
||||
input wire M_AXI_AWREADY,
|
||||
// Master Interface Write Data Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
|
||||
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
|
||||
output wire M_AXI_WLAST,
|
||||
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
|
||||
output wire M_AXI_WVALID,
|
||||
input wire M_AXI_WREADY,
|
||||
// Master Interface Write Response Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
|
||||
input wire [2-1:0] M_AXI_BRESP,
|
||||
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
|
||||
input wire M_AXI_BVALID,
|
||||
output wire M_AXI_BREADY,
|
||||
// Master Interface Read Address Port
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
|
||||
output wire [4-1:0] M_AXI_ARLEN,
|
||||
output wire [3-1:0] M_AXI_ARSIZE,
|
||||
output wire [2-1:0] M_AXI_ARBURST,
|
||||
output wire [2-1:0] M_AXI_ARLOCK,
|
||||
output wire [4-1:0] M_AXI_ARCACHE,
|
||||
output wire [3-1:0] M_AXI_ARPROT,
|
||||
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
|
||||
output wire M_AXI_ARVALID,
|
||||
input wire M_AXI_ARREADY,
|
||||
// Master Interface Read Data Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
|
||||
input wire [2-1:0] M_AXI_RRESP,
|
||||
input wire M_AXI_RLAST,
|
||||
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
|
||||
input wire M_AXI_RVALID,
|
||||
output wire M_AXI_RREADY,
|
||||
|
||||
output wire ERROR_TRIGGER,
|
||||
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
|
||||
);
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Local params
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
localparam C_FIFO_DEPTH_LOG = 4;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Internal signals
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Internal reset.
|
||||
reg ARESET;
|
||||
|
||||
// AW->W command queue signals.
|
||||
wire cmd_w_valid;
|
||||
wire cmd_w_check;
|
||||
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
|
||||
wire cmd_w_ready;
|
||||
|
||||
// W->B command queue signals.
|
||||
wire cmd_b_push;
|
||||
wire cmd_b_error;
|
||||
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
|
||||
wire cmd_b_full;
|
||||
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
|
||||
wire cmd_b_ready;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Handle Internal Reset
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
always @ (posedge ACLK) begin
|
||||
ARESET <= !ARESETN;
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Handle Write Channels (AW/W/B)
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Write Address Channel.
|
||||
processing_system7_v5_5_aw_atc #
|
||||
(
|
||||
.C_FAMILY (C_FAMILY),
|
||||
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
|
||||
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
|
||||
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
|
||||
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
|
||||
) write_addr_inst
|
||||
(
|
||||
// Global Signals
|
||||
.ARESET (ARESET),
|
||||
.ACLK (ACLK),
|
||||
|
||||
// Command Interface (Out)
|
||||
.cmd_w_valid (cmd_w_valid),
|
||||
.cmd_w_check (cmd_w_check),
|
||||
.cmd_w_id (cmd_w_id),
|
||||
.cmd_w_ready (cmd_w_ready),
|
||||
.cmd_b_addr (cmd_b_addr),
|
||||
.cmd_b_ready (cmd_b_ready),
|
||||
|
||||
// Slave Interface Write Address Ports
|
||||
.S_AXI_AWID (S_AXI_AWID),
|
||||
.S_AXI_AWADDR (S_AXI_AWADDR),
|
||||
.S_AXI_AWLEN (S_AXI_AWLEN),
|
||||
.S_AXI_AWSIZE (S_AXI_AWSIZE),
|
||||
.S_AXI_AWBURST (S_AXI_AWBURST),
|
||||
.S_AXI_AWLOCK (S_AXI_AWLOCK),
|
||||
.S_AXI_AWCACHE (S_AXI_AWCACHE),
|
||||
.S_AXI_AWPROT (S_AXI_AWPROT),
|
||||
.S_AXI_AWUSER (S_AXI_AWUSER),
|
||||
.S_AXI_AWVALID (S_AXI_AWVALID),
|
||||
.S_AXI_AWREADY (S_AXI_AWREADY),
|
||||
|
||||
// Master Interface Write Address Port
|
||||
.M_AXI_AWID (M_AXI_AWID),
|
||||
.M_AXI_AWADDR (M_AXI_AWADDR),
|
||||
.M_AXI_AWLEN (M_AXI_AWLEN),
|
||||
.M_AXI_AWSIZE (M_AXI_AWSIZE),
|
||||
.M_AXI_AWBURST (M_AXI_AWBURST),
|
||||
.M_AXI_AWLOCK (M_AXI_AWLOCK),
|
||||
.M_AXI_AWCACHE (M_AXI_AWCACHE),
|
||||
.M_AXI_AWPROT (M_AXI_AWPROT),
|
||||
.M_AXI_AWUSER (M_AXI_AWUSER),
|
||||
.M_AXI_AWVALID (M_AXI_AWVALID),
|
||||
.M_AXI_AWREADY (M_AXI_AWREADY)
|
||||
);
|
||||
|
||||
// Write Data channel.
|
||||
processing_system7_v5_5_w_atc #
|
||||
(
|
||||
.C_FAMILY (C_FAMILY),
|
||||
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
|
||||
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
|
||||
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
|
||||
) write_data_inst
|
||||
(
|
||||
// Global Signals
|
||||
.ARESET (ARESET),
|
||||
.ACLK (ACLK),
|
||||
|
||||
// Command Interface (In)
|
||||
.cmd_w_valid (cmd_w_valid),
|
||||
.cmd_w_check (cmd_w_check),
|
||||
.cmd_w_id (cmd_w_id),
|
||||
.cmd_w_ready (cmd_w_ready),
|
||||
|
||||
// Command Interface (Out)
|
||||
.cmd_b_push (cmd_b_push),
|
||||
.cmd_b_error (cmd_b_error),
|
||||
.cmd_b_id (cmd_b_id),
|
||||
.cmd_b_full (cmd_b_full),
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
.S_AXI_WID (S_AXI_WID),
|
||||
.S_AXI_WDATA (S_AXI_WDATA),
|
||||
.S_AXI_WSTRB (S_AXI_WSTRB),
|
||||
.S_AXI_WLAST (S_AXI_WLAST),
|
||||
.S_AXI_WUSER (S_AXI_WUSER),
|
||||
.S_AXI_WVALID (S_AXI_WVALID),
|
||||
.S_AXI_WREADY (S_AXI_WREADY),
|
||||
|
||||
// Master Interface Write Data Ports
|
||||
.M_AXI_WID (M_AXI_WID),
|
||||
.M_AXI_WDATA (M_AXI_WDATA),
|
||||
.M_AXI_WSTRB (M_AXI_WSTRB),
|
||||
.M_AXI_WLAST (M_AXI_WLAST),
|
||||
.M_AXI_WUSER (M_AXI_WUSER),
|
||||
.M_AXI_WVALID (M_AXI_WVALID),
|
||||
.M_AXI_WREADY (M_AXI_WREADY)
|
||||
);
|
||||
|
||||
// Write Response channel.
|
||||
processing_system7_v5_5_b_atc #
|
||||
(
|
||||
.C_FAMILY (C_FAMILY),
|
||||
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
|
||||
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
|
||||
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
|
||||
) write_response_inst
|
||||
(
|
||||
// Global Signals
|
||||
.ARESET (ARESET),
|
||||
.ACLK (ACLK),
|
||||
|
||||
// Command Interface (In)
|
||||
.cmd_b_push (cmd_b_push),
|
||||
.cmd_b_error (cmd_b_error),
|
||||
.cmd_b_id (cmd_b_id),
|
||||
.cmd_b_full (cmd_b_full),
|
||||
.cmd_b_addr (cmd_b_addr),
|
||||
.cmd_b_ready (cmd_b_ready),
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
.S_AXI_BID (S_AXI_BID),
|
||||
.S_AXI_BRESP (S_AXI_BRESP),
|
||||
.S_AXI_BUSER (S_AXI_BUSER),
|
||||
.S_AXI_BVALID (S_AXI_BVALID),
|
||||
.S_AXI_BREADY (S_AXI_BREADY),
|
||||
|
||||
// Master Interface Write Response Ports
|
||||
.M_AXI_BID (M_AXI_BID),
|
||||
.M_AXI_BRESP (M_AXI_BRESP),
|
||||
.M_AXI_BUSER (M_AXI_BUSER),
|
||||
.M_AXI_BVALID (M_AXI_BVALID),
|
||||
.M_AXI_BREADY (M_AXI_BREADY),
|
||||
|
||||
// Trigger detection
|
||||
.ERROR_TRIGGER (ERROR_TRIGGER),
|
||||
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
|
||||
);
|
||||
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Handle Read Channels (AR/R)
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Read Address Port
|
||||
assign M_AXI_ARID = S_AXI_ARID;
|
||||
assign M_AXI_ARADDR = S_AXI_ARADDR;
|
||||
assign M_AXI_ARLEN = S_AXI_ARLEN;
|
||||
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
|
||||
assign M_AXI_ARBURST = S_AXI_ARBURST;
|
||||
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
|
||||
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
|
||||
assign M_AXI_ARPROT = S_AXI_ARPROT;
|
||||
assign M_AXI_ARUSER = S_AXI_ARUSER;
|
||||
assign M_AXI_ARVALID = S_AXI_ARVALID;
|
||||
assign S_AXI_ARREADY = M_AXI_ARREADY;
|
||||
|
||||
// Read Data Port
|
||||
assign S_AXI_RID = M_AXI_RID;
|
||||
assign S_AXI_RDATA = M_AXI_RDATA;
|
||||
assign S_AXI_RRESP = M_AXI_RRESP;
|
||||
assign S_AXI_RLAST = M_AXI_RLAST;
|
||||
assign S_AXI_RUSER = M_AXI_RUSER;
|
||||
assign S_AXI_RVALID = M_AXI_RVALID;
|
||||
assign M_AXI_RREADY = S_AXI_RREADY;
|
||||
|
||||
|
||||
endmodule
|
||||
`default_nettype wire
|
||||
+298
@@ -0,0 +1,298 @@
|
||||
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
|
||||
// --
|
||||
// -- This file contains confidential and proprietary information
|
||||
// -- of Xilinx, Inc. and is protected under U.S. and
|
||||
// -- international copyright and other intellectual property
|
||||
// -- laws.
|
||||
// --
|
||||
// -- DISCLAIMER
|
||||
// -- This disclaimer is not a license and does not grant any
|
||||
// -- rights to the materials distributed herewith. Except as
|
||||
// -- otherwise provided in a valid license issued to you by
|
||||
// -- Xilinx, and to the maximum extent permitted by applicable
|
||||
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// -- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// -- including negligence, or under any other theory of
|
||||
// -- liability) for any loss or damage of any kind or nature
|
||||
// -- related to, arising under or in connection with these
|
||||
// -- materials, including for any direct, or any indirect,
|
||||
// -- special, incidental, or consequential loss or damage
|
||||
// -- (including loss of data, profits, goodwill, or any type of
|
||||
// -- loss or damage suffered as a result of any action brought
|
||||
// -- by a third party) even if such damage or loss was
|
||||
// -- reasonably foreseeable or Xilinx had been advised of the
|
||||
// -- possibility of the same.
|
||||
// --
|
||||
// -- CRITICAL APPLICATIONS
|
||||
// -- Xilinx products are not designed or intended to be fail-
|
||||
// -- safe, or for use in any application requiring fail-safe
|
||||
// -- performance, such as life-support or safety devices or
|
||||
// -- systems, Class III medical devices, nuclear facilities,
|
||||
// -- applications related to the deployment of airbags, or any
|
||||
// -- other applications that could lead to death, personal
|
||||
// -- injury, or severe property or environmental damage
|
||||
// -- (individually and collectively, "Critical
|
||||
// -- Applications"). Customer assumes the sole risk and
|
||||
// -- liability of any use of Xilinx products in Critical
|
||||
// -- Applications, subject only to applicable laws and
|
||||
// -- regulations governing limitations on product liability.
|
||||
// --
|
||||
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// -- PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Description: Address Write Channel for ATC
|
||||
//
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// aw_atc
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
|
||||
module processing_system7_v5_5_aw_atc #
|
||||
(
|
||||
parameter C_FAMILY = "rtl",
|
||||
// FPGA Family. Current version: virtex6, spartan6 or later.
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
// Width of all ID signals on SI and MI side of checker.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
// Width of all ADDR signals on SI and MI side of checker.
|
||||
// Range: 32.
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 1,
|
||||
// Width of AWUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_FIFO_DEPTH_LOG = 4
|
||||
)
|
||||
(
|
||||
// Global Signals
|
||||
input wire ARESET,
|
||||
input wire ACLK,
|
||||
|
||||
// Command Interface
|
||||
output reg cmd_w_valid,
|
||||
output wire cmd_w_check,
|
||||
output wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
|
||||
input wire cmd_w_ready,
|
||||
input wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
|
||||
input wire cmd_b_ready,
|
||||
|
||||
// Slave Interface Write Address Port
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
|
||||
input wire [4-1:0] S_AXI_AWLEN,
|
||||
input wire [3-1:0] S_AXI_AWSIZE,
|
||||
input wire [2-1:0] S_AXI_AWBURST,
|
||||
input wire [2-1:0] S_AXI_AWLOCK,
|
||||
input wire [4-1:0] S_AXI_AWCACHE,
|
||||
input wire [3-1:0] S_AXI_AWPROT,
|
||||
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
|
||||
input wire S_AXI_AWVALID,
|
||||
output wire S_AXI_AWREADY,
|
||||
|
||||
// Master Interface Write Address Port
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
|
||||
output wire [4-1:0] M_AXI_AWLEN,
|
||||
output wire [3-1:0] M_AXI_AWSIZE,
|
||||
output wire [2-1:0] M_AXI_AWBURST,
|
||||
output wire [2-1:0] M_AXI_AWLOCK,
|
||||
output wire [4-1:0] M_AXI_AWCACHE,
|
||||
output wire [3-1:0] M_AXI_AWPROT,
|
||||
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
|
||||
output wire M_AXI_AWVALID,
|
||||
input wire M_AXI_AWREADY
|
||||
);
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Local params
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Constants for burst types.
|
||||
localparam [2-1:0] C_FIX_BURST = 2'b00;
|
||||
localparam [2-1:0] C_INCR_BURST = 2'b01;
|
||||
localparam [2-1:0] C_WRAP_BURST = 2'b10;
|
||||
|
||||
// Constants for size.
|
||||
localparam [3-1:0] C_OPTIMIZED_SIZE = 3'b011;
|
||||
|
||||
// Constants for length.
|
||||
localparam [4-1:0] C_OPTIMIZED_LEN = 4'b0011;
|
||||
|
||||
// Constants for cacheline address.
|
||||
localparam [4-1:0] C_NO_ADDR_OFFSET = 5'b0;
|
||||
|
||||
// Command FIFO settings
|
||||
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
|
||||
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Variables for generating parameter controlled instances.
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
integer index;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Internal signals
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Transaction properties.
|
||||
wire access_is_incr;
|
||||
wire access_is_wrap;
|
||||
wire access_is_coherent;
|
||||
wire access_optimized_size;
|
||||
wire incr_addr_boundary;
|
||||
wire incr_is_optimized;
|
||||
wire wrap_is_optimized;
|
||||
wire access_is_optimized;
|
||||
|
||||
// Command FIFO.
|
||||
wire cmd_w_push;
|
||||
reg cmd_full;
|
||||
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
|
||||
wire [C_FIFO_DEPTH_LOG-1:0] all_addr_ptr;
|
||||
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Transaction Decode:
|
||||
//
|
||||
// Detect if transaction is of correct typ, size and length to qualify as
|
||||
// an optimized transaction that has to be checked for errors.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Transaction burst type.
|
||||
assign access_is_incr = ( S_AXI_AWBURST == C_INCR_BURST );
|
||||
assign access_is_wrap = ( S_AXI_AWBURST == C_WRAP_BURST );
|
||||
|
||||
// Transaction has to be Coherent.
|
||||
assign access_is_coherent = ( S_AXI_AWUSER[0] == 1'b1 ) &
|
||||
( S_AXI_AWCACHE[1] == 1'b1 );
|
||||
|
||||
// Transaction cacheline boundary address.
|
||||
assign incr_addr_boundary = ( S_AXI_AWADDR[4:0] == C_NO_ADDR_OFFSET );
|
||||
|
||||
// Transaction length & size.
|
||||
assign access_optimized_size = ( S_AXI_AWSIZE == C_OPTIMIZED_SIZE ) &
|
||||
( S_AXI_AWLEN == C_OPTIMIZED_LEN );
|
||||
|
||||
// Transaction is optimized.
|
||||
assign incr_is_optimized = access_is_incr & access_is_coherent & access_optimized_size & incr_addr_boundary;
|
||||
assign wrap_is_optimized = access_is_wrap & access_is_coherent & access_optimized_size;
|
||||
assign access_is_optimized = ( incr_is_optimized | wrap_is_optimized );
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Command FIFO:
|
||||
//
|
||||
// Since supported write interleaving is only 1, it is safe to use only a
|
||||
// simple SRL based FIFO as a command queue.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Determine when transaction infromation is pushed to the FIFO.
|
||||
assign cmd_w_push = S_AXI_AWVALID & M_AXI_AWREADY & ~cmd_full;
|
||||
|
||||
// SRL FIFO Pointer.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
|
||||
end else begin
|
||||
if ( cmd_w_push & ~cmd_w_ready ) begin
|
||||
addr_ptr <= addr_ptr + 1;
|
||||
end else if ( ~cmd_w_push & cmd_w_ready ) begin
|
||||
addr_ptr <= addr_ptr - 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Total number of buffered commands.
|
||||
assign all_addr_ptr = addr_ptr + cmd_b_addr + 2;
|
||||
|
||||
// FIFO Flags.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
cmd_full <= 1'b0;
|
||||
cmd_w_valid <= 1'b0;
|
||||
end else begin
|
||||
if ( cmd_w_push & ~cmd_w_ready ) begin
|
||||
cmd_w_valid <= 1'b1;
|
||||
end else if ( ~cmd_w_push & cmd_w_ready ) begin
|
||||
cmd_w_valid <= ( addr_ptr != 0 );
|
||||
end
|
||||
if ( cmd_w_push & ~cmd_b_ready ) begin
|
||||
// Going to full.
|
||||
cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-3 );
|
||||
end else if ( ~cmd_w_push & cmd_b_ready ) begin
|
||||
// Pop in middle of queue doesn't affect full status.
|
||||
cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-2 );
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Infere SRL for storage.
|
||||
always @ (posedge ACLK) begin
|
||||
if ( cmd_w_push ) begin
|
||||
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
|
||||
data_srl[index+1] <= data_srl[index];
|
||||
end
|
||||
data_srl[0] <= {access_is_optimized, S_AXI_AWID};
|
||||
end
|
||||
end
|
||||
|
||||
// Get current transaction info.
|
||||
assign {cmd_w_check, cmd_w_id} = data_srl[addr_ptr];
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Transaction Throttling:
|
||||
//
|
||||
// Stall commands if FIFO is full.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Propagate masked valid.
|
||||
assign M_AXI_AWVALID = S_AXI_AWVALID & ~cmd_full;
|
||||
|
||||
// Return ready with push back.
|
||||
assign S_AXI_AWREADY = M_AXI_AWREADY & ~cmd_full;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Address Write propagation:
|
||||
//
|
||||
// All information is simply forwarded on from the SI- to MI-Side untouched.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// 1:1 mapping.
|
||||
assign M_AXI_AWID = S_AXI_AWID;
|
||||
assign M_AXI_AWADDR = S_AXI_AWADDR;
|
||||
assign M_AXI_AWLEN = S_AXI_AWLEN;
|
||||
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
|
||||
assign M_AXI_AWBURST = S_AXI_AWBURST;
|
||||
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
|
||||
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
|
||||
assign M_AXI_AWPROT = S_AXI_AWPROT;
|
||||
assign M_AXI_AWUSER = S_AXI_AWUSER;
|
||||
|
||||
|
||||
endmodule
|
||||
+413
@@ -0,0 +1,413 @@
|
||||
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
|
||||
// --
|
||||
// -- This file contains confidential and proprietary information
|
||||
// -- of Xilinx, Inc. and is protected under U.S. and
|
||||
// -- international copyright and other intellectual property
|
||||
// -- laws.
|
||||
// --
|
||||
// -- DISCLAIMER
|
||||
// -- This disclaimer is not a license and does not grant any
|
||||
// -- rights to the materials distributed herewith. Except as
|
||||
// -- otherwise provided in a valid license issued to you by
|
||||
// -- Xilinx, and to the maximum extent permitted by applicable
|
||||
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// -- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// -- including negligence, or under any other theory of
|
||||
// -- liability) for any loss or damage of any kind or nature
|
||||
// -- related to, arising under or in connection with these
|
||||
// -- materials, including for any direct, or any indirect,
|
||||
// -- special, incidental, or consequential loss or damage
|
||||
// -- (including loss of data, profits, goodwill, or any type of
|
||||
// -- loss or damage suffered as a result of any action brought
|
||||
// -- by a third party) even if such damage or loss was
|
||||
// -- reasonably foreseeable or Xilinx had been advised of the
|
||||
// -- possibility of the same.
|
||||
// --
|
||||
// -- CRITICAL APPLICATIONS
|
||||
// -- Xilinx products are not designed or intended to be fail-
|
||||
// -- safe, or for use in any application requiring fail-safe
|
||||
// -- performance, such as life-support or safety devices or
|
||||
// -- systems, Class III medical devices, nuclear facilities,
|
||||
// -- applications related to the deployment of airbags, or any
|
||||
// -- other applications that could lead to death, personal
|
||||
// -- injury, or severe property or environmental damage
|
||||
// -- (individually and collectively, "Critical
|
||||
// -- Applications"). Customer assumes the sole risk and
|
||||
// -- liability of any use of Xilinx products in Critical
|
||||
// -- Applications, subject only to applicable laws and
|
||||
// -- regulations governing limitations on product liability.
|
||||
// --
|
||||
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// -- PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Description: Write Response Channel for ATC
|
||||
//
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// b_atc
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
|
||||
module processing_system7_v5_5_b_atc #
|
||||
(
|
||||
parameter C_FAMILY = "rtl",
|
||||
// FPGA Family. Current version: virtex6, spartan6 or later.
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
// Width of all ID signals on SI and MI side of checker.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_BUSER_WIDTH = 1,
|
||||
// Width of AWUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_FIFO_DEPTH_LOG = 4
|
||||
)
|
||||
(
|
||||
// Global Signals
|
||||
input wire ARESET,
|
||||
input wire ACLK,
|
||||
|
||||
// Command Interface
|
||||
input wire cmd_b_push,
|
||||
input wire cmd_b_error,
|
||||
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
|
||||
output wire cmd_b_ready,
|
||||
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
|
||||
output reg cmd_b_full,
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
|
||||
output reg [2-1:0] S_AXI_BRESP,
|
||||
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
|
||||
output wire S_AXI_BVALID,
|
||||
input wire S_AXI_BREADY,
|
||||
|
||||
// Master Interface Write Response Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
|
||||
input wire [2-1:0] M_AXI_BRESP,
|
||||
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
|
||||
input wire M_AXI_BVALID,
|
||||
output wire M_AXI_BREADY,
|
||||
|
||||
// Trigger detection
|
||||
output reg ERROR_TRIGGER,
|
||||
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
|
||||
);
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Local params
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Constants for packing levels.
|
||||
localparam [2-1:0] C_RESP_OKAY = 2'b00;
|
||||
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
|
||||
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
|
||||
localparam [2-1:0] C_RESP_DECERR = 2'b11;
|
||||
|
||||
// Command FIFO settings
|
||||
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
|
||||
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Variables for generating parameter controlled instances.
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
integer index;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Internal signals
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Command Queue.
|
||||
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
|
||||
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
|
||||
reg cmd_b_valid;
|
||||
wire cmd_b_ready_i;
|
||||
wire inject_error;
|
||||
wire [C_AXI_ID_WIDTH-1:0] current_id;
|
||||
|
||||
// Search command.
|
||||
wire found_match;
|
||||
wire use_match;
|
||||
wire matching_id;
|
||||
|
||||
// Manage valid command.
|
||||
wire write_valid_cmd;
|
||||
reg [C_FIFO_DEPTH-2:0] valid_cmd;
|
||||
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
|
||||
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
|
||||
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
|
||||
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
|
||||
|
||||
// Pipelined data
|
||||
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
|
||||
reg [2-1:0] M_AXI_BRESP_I;
|
||||
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
|
||||
reg M_AXI_BVALID_I;
|
||||
wire M_AXI_BREADY_I;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Command Queue:
|
||||
//
|
||||
// Keep track of depth of Queue to generate full flag.
|
||||
//
|
||||
// Also generate valid to mark pressence of commands in Queue.
|
||||
//
|
||||
// Maintain Queue and extract data from currently searched entry.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// SRL FIFO Pointer.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
|
||||
end else begin
|
||||
if ( cmd_b_push & ~cmd_b_ready_i ) begin
|
||||
// Pushing data increase length/addr.
|
||||
addr_ptr <= addr_ptr + 1;
|
||||
end else if ( cmd_b_ready_i ) begin
|
||||
// Collapse addr when data is popped.
|
||||
addr_ptr <= collapsed_addr_ptr;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// FIFO Flags.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
cmd_b_full <= 1'b0;
|
||||
cmd_b_valid <= 1'b0;
|
||||
end else begin
|
||||
if ( cmd_b_push & ~cmd_b_ready_i ) begin
|
||||
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
|
||||
cmd_b_valid <= 1'b1;
|
||||
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
|
||||
cmd_b_full <= 1'b0;
|
||||
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Infere SRL for storage.
|
||||
always @ (posedge ACLK) begin
|
||||
if ( cmd_b_push ) begin
|
||||
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
|
||||
data_srl[index+1] <= data_srl[index];
|
||||
end
|
||||
data_srl[0] <= {cmd_b_error, cmd_b_id};
|
||||
end
|
||||
end
|
||||
|
||||
// Get current transaction info.
|
||||
assign {inject_error, current_id} = data_srl[search_addr_ptr];
|
||||
|
||||
// Assign outputs.
|
||||
assign cmd_b_addr = collapsed_addr_ptr;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Search Command Queue:
|
||||
//
|
||||
// Search for matching valid command in queue.
|
||||
//
|
||||
// A command is found when an valid entry with correct ID is found. The queue
|
||||
// is search from the oldest entry, i.e. from a high value.
|
||||
// When new commands are pushed the search address has to be updated to always
|
||||
// start the search from the oldest available.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Handle search addr.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
|
||||
end else begin
|
||||
if ( cmd_b_ready_i ) begin
|
||||
// Collapse addr when data is popped.
|
||||
search_addr_ptr <= collapsed_addr_ptr;
|
||||
|
||||
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
|
||||
// Skip non valid command.
|
||||
search_addr_ptr <= search_addr_ptr - 1;
|
||||
|
||||
end else if ( cmd_b_push ) begin
|
||||
search_addr_ptr <= search_addr_ptr + 1;
|
||||
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Check if searched command is valid and match ID (for existing response on MI side).
|
||||
assign matching_id = ( M_AXI_BID_I == current_id );
|
||||
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
|
||||
assign use_match = found_match & S_AXI_BREADY;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Track Used Commands:
|
||||
//
|
||||
// Actions that affect Valid Command:
|
||||
// * When a new command is pushed
|
||||
// => Shift valid vector one step
|
||||
// * When a command is used
|
||||
// => Clear corresponding valid bit
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Valid command status is updated when a command is used or a new one is pushed.
|
||||
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
|
||||
|
||||
// Update the used command valid bit.
|
||||
always @ *
|
||||
begin
|
||||
updated_valid_cmd = valid_cmd;
|
||||
updated_valid_cmd[search_addr_ptr] = ~use_match;
|
||||
end
|
||||
|
||||
// Shift valid vector when command is pushed.
|
||||
always @ *
|
||||
begin
|
||||
if ( cmd_b_push ) begin
|
||||
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
|
||||
end else begin
|
||||
next_valid_cmd = updated_valid_cmd;
|
||||
end
|
||||
end
|
||||
|
||||
// Valid signals for next cycle.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
|
||||
end else if ( write_valid_cmd ) begin
|
||||
valid_cmd <= next_valid_cmd;
|
||||
end
|
||||
end
|
||||
|
||||
// Detect oldest available command in Queue.
|
||||
always @ *
|
||||
begin
|
||||
// Default to empty.
|
||||
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
|
||||
|
||||
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
|
||||
if ( next_valid_cmd[index] ) begin
|
||||
collapsed_addr_ptr = index;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Pipe incoming data:
|
||||
//
|
||||
// The B channel is piped to improve timing and avoid impact in search
|
||||
// mechanism due to late arriving signals.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Clock data.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
|
||||
M_AXI_BRESP_I <= 2'b00;
|
||||
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
|
||||
M_AXI_BVALID_I <= 1'b0;
|
||||
end else begin
|
||||
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
|
||||
M_AXI_BVALID_I <= 1'b0;
|
||||
end
|
||||
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
|
||||
M_AXI_BID_I <= M_AXI_BID;
|
||||
M_AXI_BRESP_I <= M_AXI_BRESP;
|
||||
M_AXI_BUSER_I <= M_AXI_BUSER;
|
||||
M_AXI_BVALID_I <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Generate ready to get new transaction.
|
||||
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Inject Error:
|
||||
//
|
||||
// BRESP is modified according to command information.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Inject error in response.
|
||||
always @ *
|
||||
begin
|
||||
if ( inject_error ) begin
|
||||
S_AXI_BRESP = C_RESP_SLVERROR;
|
||||
end else begin
|
||||
S_AXI_BRESP = M_AXI_BRESP_I;
|
||||
end
|
||||
end
|
||||
|
||||
// Handle interrupt generation.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
ERROR_TRIGGER <= 1'b0;
|
||||
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
|
||||
end else begin
|
||||
if ( inject_error & cmd_b_ready_i ) begin
|
||||
ERROR_TRIGGER <= 1'b1;
|
||||
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
|
||||
end else begin
|
||||
ERROR_TRIGGER <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Transaction Throttling:
|
||||
//
|
||||
// Response is passed forward when a matching entry has been found in queue.
|
||||
// Both ready and valid are set when the command is completed.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Propagate masked valid.
|
||||
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
|
||||
|
||||
// Return ready with push back.
|
||||
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
|
||||
|
||||
// Command has been handled.
|
||||
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
|
||||
assign cmd_b_ready = cmd_b_ready_i;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Write Response Propagation:
|
||||
//
|
||||
// All information is simply forwarded on from MI- to SI-Side untouched.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// 1:1 mapping.
|
||||
assign S_AXI_BID = M_AXI_BID_I;
|
||||
assign S_AXI_BUSER = M_AXI_BUSER_I;
|
||||
|
||||
|
||||
endmodule
|
||||
+310
@@ -0,0 +1,310 @@
|
||||
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
|
||||
// --
|
||||
// -- This file contains confidential and proprietary information
|
||||
// -- of Xilinx, Inc. and is protected under U.S. and
|
||||
// -- international copyright and other intellectual property
|
||||
// -- laws.
|
||||
// --
|
||||
// -- DISCLAIMER
|
||||
// -- This disclaimer is not a license and does not grant any
|
||||
// -- rights to the materials distributed herewith. Except as
|
||||
// -- otherwise provided in a valid license issued to you by
|
||||
// -- Xilinx, and to the maximum extent permitted by applicable
|
||||
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// -- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// -- including negligence, or under any other theory of
|
||||
// -- liability) for any loss or damage of any kind or nature
|
||||
// -- related to, arising under or in connection with these
|
||||
// -- materials, including for any direct, or any indirect,
|
||||
// -- special, incidental, or consequential loss or damage
|
||||
// -- (including loss of data, profits, goodwill, or any type of
|
||||
// -- loss or damage suffered as a result of any action brought
|
||||
// -- by a third party) even if such damage or loss was
|
||||
// -- reasonably foreseeable or Xilinx had been advised of the
|
||||
// -- possibility of the same.
|
||||
// --
|
||||
// -- CRITICAL APPLICATIONS
|
||||
// -- Xilinx products are not designed or intended to be fail-
|
||||
// -- safe, or for use in any application requiring fail-safe
|
||||
// -- performance, such as life-support or safety devices or
|
||||
// -- systems, Class III medical devices, nuclear facilities,
|
||||
// -- applications related to the deployment of airbags, or any
|
||||
// -- other applications that could lead to death, personal
|
||||
// -- injury, or severe property or environmental damage
|
||||
// -- (individually and collectively, "Critical
|
||||
// -- Applications"). Customer assumes the sole risk and
|
||||
// -- liability of any use of Xilinx products in Critical
|
||||
// -- Applications, subject only to applicable laws and
|
||||
// -- regulations governing limitations on product liability.
|
||||
// --
|
||||
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// -- PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
// Filename: trace_buffer.v
|
||||
// Description: Trace port buffer
|
||||
//-----------------------------------------------------------------------------
|
||||
// Structure: This section shows the hierarchical structure of
|
||||
// pss_wrapper.
|
||||
//
|
||||
// --processing_system7
|
||||
// |
|
||||
// --trace_buffer
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
module processing_system7_v5_5_trace_buffer #
|
||||
(
|
||||
parameter integer FIFO_SIZE = 128,
|
||||
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
|
||||
parameter integer C_DELAY_CLKS = 12
|
||||
)
|
||||
(
|
||||
input wire TRACE_CLK,
|
||||
input wire RST,
|
||||
input wire TRACE_VALID_IN,
|
||||
input wire [3:0] TRACE_ATID_IN,
|
||||
input wire [31:0] TRACE_DATA_IN,
|
||||
output wire TRACE_VALID_OUT,
|
||||
output wire [3:0] TRACE_ATID_OUT,
|
||||
output wire [31:0] TRACE_DATA_OUT
|
||||
);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Architecture section
|
||||
//------------------------------------------------------------
|
||||
|
||||
// function called clogb2 that returns an integer which has the
|
||||
// value of the ceiling of the log base 2.
|
||||
|
||||
function integer clogb2 (input integer bit_depth);
|
||||
integer i;
|
||||
integer temp_log;
|
||||
begin
|
||||
temp_log = 0;
|
||||
for(i=bit_depth; i > 0; i = i>>1)
|
||||
clogb2 = temp_log;
|
||||
temp_log=temp_log+1;
|
||||
end
|
||||
endfunction
|
||||
|
||||
localparam DEPTH = clogb2(FIFO_SIZE-1);
|
||||
|
||||
wire [31:0] reset_zeros;
|
||||
reg [31:0] trace_pedge; // write enable for FIFO
|
||||
reg [31:0] ti;
|
||||
reg [31:0] tom;
|
||||
|
||||
reg [3:0] atid;
|
||||
|
||||
reg [31:0] trace_fifo [FIFO_SIZE-1:0];//Memory
|
||||
|
||||
reg [4:0] dly_ctr;
|
||||
reg [DEPTH-1:0] fifo_wp;
|
||||
reg [DEPTH-1:0] fifo_rp;
|
||||
|
||||
reg fifo_re;
|
||||
wire fifo_empty;
|
||||
wire fifo_full;
|
||||
reg fifo_full_reg;
|
||||
|
||||
assign reset_zeros = 32'h0;
|
||||
|
||||
|
||||
// Pipeline Stage for Traceport ATID ports
|
||||
always @(posedge TRACE_CLK) begin
|
||||
// process pedge_ti
|
||||
// rising clock edge
|
||||
if((RST == 1'b1)) begin
|
||||
atid <= reset_zeros;
|
||||
end
|
||||
else begin
|
||||
atid <= TRACE_ATID_IN;
|
||||
end
|
||||
end
|
||||
|
||||
assign TRACE_ATID_OUT = atid;
|
||||
|
||||
/////////////////////////////////////////////
|
||||
// Generate FIFO data based on TRACE_VALID_IN
|
||||
/////////////////////////////////////////////
|
||||
generate
|
||||
if (USE_TRACE_DATA_EDGE_DETECTOR == 0) begin : gen_no_data_edge_detector
|
||||
/////////////////////////////////////////////
|
||||
|
||||
// memory update process
|
||||
// Update memory when positive edge detected and FIFO not full
|
||||
always @(posedge TRACE_CLK) begin
|
||||
if (TRACE_VALID_IN == 1'b1 && fifo_full_reg != 1'b1) begin
|
||||
trace_fifo[fifo_wp] <= TRACE_DATA_IN;
|
||||
end
|
||||
end
|
||||
|
||||
// fifo write pointer
|
||||
always @(posedge TRACE_CLK) begin
|
||||
// process
|
||||
if(RST == 1'b1) begin
|
||||
fifo_wp <= {DEPTH{1'b0}};
|
||||
end
|
||||
else if(TRACE_VALID_IN ) begin
|
||||
if(fifo_wp == (FIFO_SIZE - 1)) begin
|
||||
if (fifo_empty) begin
|
||||
fifo_wp <= {DEPTH{1'b0}};
|
||||
end
|
||||
end
|
||||
else begin
|
||||
fifo_wp <= fifo_wp + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////////////
|
||||
// Generate FIFO data based on data edge
|
||||
/////////////////////////////////////////////
|
||||
end else begin : gen_data_edge_detector
|
||||
/////////////////////////////////////////////
|
||||
|
||||
|
||||
// purpose: check for pos edge on any trace input
|
||||
always @(posedge TRACE_CLK) begin
|
||||
// process pedge_ti
|
||||
// rising clock edge
|
||||
if((RST == 1'b1)) begin
|
||||
ti <= reset_zeros;
|
||||
trace_pedge <= reset_zeros;
|
||||
end
|
||||
else begin
|
||||
ti <= TRACE_DATA_IN;
|
||||
trace_pedge <= (~ti & TRACE_DATA_IN);
|
||||
//trace_pedge <= ((~ti ^ TRACE_DATA_IN)) & ~ti;
|
||||
// posedge only
|
||||
end
|
||||
end
|
||||
|
||||
// memory update process
|
||||
// Update memory when positive edge detected and FIFO not full
|
||||
always @(posedge TRACE_CLK) begin
|
||||
if(|(trace_pedge) == 1'b1 && fifo_full_reg != 1'b1) begin
|
||||
trace_fifo[fifo_wp] <= trace_pedge;
|
||||
end
|
||||
end
|
||||
|
||||
// fifo write pointer
|
||||
always @(posedge TRACE_CLK) begin
|
||||
// process
|
||||
if(RST == 1'b1) begin
|
||||
fifo_wp <= {DEPTH{1'b0}};
|
||||
end
|
||||
else if(|(trace_pedge) == 1'b1) begin
|
||||
if(fifo_wp == (FIFO_SIZE - 1)) begin
|
||||
if (fifo_empty) begin
|
||||
fifo_wp <= {DEPTH{1'b0}};
|
||||
end
|
||||
end
|
||||
else begin
|
||||
fifo_wp <= fifo_wp + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
always @(posedge TRACE_CLK) begin
|
||||
tom <= trace_fifo[fifo_rp] ;
|
||||
end
|
||||
|
||||
|
||||
// // fifo write pointer
|
||||
// always @(posedge TRACE_CLK) begin
|
||||
// // process
|
||||
// if(RST == 1'b1) begin
|
||||
// fifo_wp <= {DEPTH{1'b0}};
|
||||
// end
|
||||
// else if(|(trace_pedge) == 1'b1) begin
|
||||
// if(fifo_wp == (FIFO_SIZE - 1)) begin
|
||||
// fifo_wp <= {DEPTH{1'b0}};
|
||||
// end
|
||||
// else begin
|
||||
// fifo_wp <= fifo_wp + 1;
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
|
||||
|
||||
// fifo read pointer update
|
||||
always @(posedge TRACE_CLK) begin
|
||||
if(RST == 1'b1) begin
|
||||
fifo_rp <= {DEPTH{1'b0}};
|
||||
fifo_re <= 1'b0;
|
||||
end
|
||||
else if(fifo_empty != 1'b1 && dly_ctr == 5'b00000 && fifo_re == 1'b0) begin
|
||||
fifo_re <= 1'b1;
|
||||
if(fifo_rp == (FIFO_SIZE - 1)) begin
|
||||
fifo_rp <= {DEPTH{1'b0}};
|
||||
end
|
||||
else begin
|
||||
fifo_rp <= fifo_rp + 1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
fifo_re <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// delay counter update
|
||||
always @(posedge TRACE_CLK) begin
|
||||
if(RST == 1'b1) begin
|
||||
dly_ctr <= 5'h0;
|
||||
end
|
||||
else if (fifo_re == 1'b1) begin
|
||||
dly_ctr <= C_DELAY_CLKS-1;
|
||||
end
|
||||
else if(dly_ctr != 5'h0) begin
|
||||
dly_ctr <= dly_ctr - 1;
|
||||
end
|
||||
end
|
||||
|
||||
// fifo empty update
|
||||
assign fifo_empty = (fifo_wp == fifo_rp) ? 1'b1 : 1'b0;
|
||||
|
||||
// fifo full update
|
||||
assign fifo_full = (fifo_wp == FIFO_SIZE-1)? 1'b1 : 1'b0;
|
||||
|
||||
always @(posedge TRACE_CLK) begin
|
||||
if(RST == 1'b1) begin
|
||||
fifo_full_reg <= 1'b0;
|
||||
end
|
||||
else if (fifo_empty) begin
|
||||
fifo_full_reg <= 1'b0;
|
||||
end else begin
|
||||
fifo_full_reg <= fifo_full;
|
||||
end
|
||||
end
|
||||
|
||||
// always @(posedge TRACE_CLK) begin
|
||||
// if(RST == 1'b1) begin
|
||||
// fifo_full_reg <= 1'b0;
|
||||
// end
|
||||
// else if ((fifo_wp == FIFO_SIZE-1) && (|(trace_pedge) == 1'b1)) begin
|
||||
// fifo_full_reg <= 1'b1;
|
||||
// end
|
||||
// else begin
|
||||
// fifo_full_reg <= 1'b0;
|
||||
// end
|
||||
// end
|
||||
//
|
||||
assign TRACE_DATA_OUT = tom;
|
||||
|
||||
assign TRACE_VALID_OUT = fifo_re;
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+244
@@ -0,0 +1,244 @@
|
||||
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
|
||||
// --
|
||||
// -- This file contains confidential and proprietary information
|
||||
// -- of Xilinx, Inc. and is protected under U.S. and
|
||||
// -- international copyright and other intellectual property
|
||||
// -- laws.
|
||||
// --
|
||||
// -- DISCLAIMER
|
||||
// -- This disclaimer is not a license and does not grant any
|
||||
// -- rights to the materials distributed herewith. Except as
|
||||
// -- otherwise provided in a valid license issued to you by
|
||||
// -- Xilinx, and to the maximum extent permitted by applicable
|
||||
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// -- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// -- including negligence, or under any other theory of
|
||||
// -- liability) for any loss or damage of any kind or nature
|
||||
// -- related to, arising under or in connection with these
|
||||
// -- materials, including for any direct, or any indirect,
|
||||
// -- special, incidental, or consequential loss or damage
|
||||
// -- (including loss of data, profits, goodwill, or any type of
|
||||
// -- loss or damage suffered as a result of any action brought
|
||||
// -- by a third party) even if such damage or loss was
|
||||
// -- reasonably foreseeable or Xilinx had been advised of the
|
||||
// -- possibility of the same.
|
||||
// --
|
||||
// -- CRITICAL APPLICATIONS
|
||||
// -- Xilinx products are not designed or intended to be fail-
|
||||
// -- safe, or for use in any application requiring fail-safe
|
||||
// -- performance, such as life-support or safety devices or
|
||||
// -- systems, Class III medical devices, nuclear facilities,
|
||||
// -- applications related to the deployment of airbags, or any
|
||||
// -- other applications that could lead to death, personal
|
||||
// -- injury, or severe property or environmental damage
|
||||
// -- (individually and collectively, "Critical
|
||||
// -- Applications"). Customer assumes the sole risk and
|
||||
// -- liability of any use of Xilinx products in Critical
|
||||
// -- Applications, subject only to applicable laws and
|
||||
// -- regulations governing limitations on product liability.
|
||||
// --
|
||||
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// -- PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Description: Write Channel for ATC
|
||||
//
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// w_atc
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
|
||||
module processing_system7_v5_5_w_atc #
|
||||
(
|
||||
parameter C_FAMILY = "rtl",
|
||||
// FPGA Family. Current version: virtex6, spartan6 or later.
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
// Width of all ID signals on SI and MI side of checker.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_DATA_WIDTH = 64,
|
||||
// Width of all DATA signals on SI and MI side of checker.
|
||||
// Range: 64.
|
||||
parameter integer C_AXI_WUSER_WIDTH = 1
|
||||
// Width of AWUSER signals.
|
||||
// Range: >= 1.
|
||||
)
|
||||
(
|
||||
// Global Signals
|
||||
input wire ARESET,
|
||||
input wire ACLK,
|
||||
|
||||
// Command Interface (In)
|
||||
input wire cmd_w_valid,
|
||||
input wire cmd_w_check,
|
||||
input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
|
||||
output wire cmd_w_ready,
|
||||
|
||||
// Command Interface (Out)
|
||||
output wire cmd_b_push,
|
||||
output wire cmd_b_error,
|
||||
output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id,
|
||||
input wire cmd_b_full,
|
||||
|
||||
// Slave Interface Write Port
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
|
||||
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
|
||||
input wire S_AXI_WLAST,
|
||||
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
|
||||
input wire S_AXI_WVALID,
|
||||
output wire S_AXI_WREADY,
|
||||
|
||||
// Master Interface Write Address Port
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
|
||||
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
|
||||
output wire M_AXI_WLAST,
|
||||
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
|
||||
output wire M_AXI_WVALID,
|
||||
input wire M_AXI_WREADY
|
||||
);
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Local params
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Variables for generating parameter controlled instances.
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Internal signals
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Detecttion.
|
||||
wire any_strb_deasserted;
|
||||
wire incoming_strb_issue;
|
||||
reg first_word;
|
||||
reg strb_issue;
|
||||
|
||||
// Data flow.
|
||||
wire data_pop;
|
||||
wire cmd_b_push_blocked;
|
||||
reg cmd_b_push_i;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Detect error:
|
||||
//
|
||||
// Detect and accumulate error when a transaction shall be scanned for
|
||||
// potential issues.
|
||||
// Accumulation of error is restarted for each ne transaction.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Check stobe information
|
||||
assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
|
||||
assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
|
||||
|
||||
// Keep track of first word in a transaction.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
first_word <= 1'b1;
|
||||
end else if ( data_pop ) begin
|
||||
first_word <= S_AXI_WLAST;
|
||||
end
|
||||
end
|
||||
|
||||
// Keep track of error status.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
strb_issue <= 1'b0;
|
||||
cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}};
|
||||
end else if ( data_pop ) begin
|
||||
if ( first_word ) begin
|
||||
strb_issue <= incoming_strb_issue;
|
||||
end else begin
|
||||
strb_issue <= incoming_strb_issue | strb_issue;
|
||||
end
|
||||
cmd_b_id <= cmd_w_id;
|
||||
end
|
||||
end
|
||||
|
||||
assign cmd_b_error = strb_issue;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Control command queue to B:
|
||||
//
|
||||
// Push command to B queue when all data for the transaction has flowed
|
||||
// through.
|
||||
// Delay pipelined command until there is room in the Queue.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Detect when data is popped.
|
||||
assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
|
||||
|
||||
// Push command when last word in transfered (pipelined).
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
cmd_b_push_i <= 1'b0;
|
||||
end else begin
|
||||
cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
|
||||
end
|
||||
end
|
||||
|
||||
// Detect if pipelined push is blocked.
|
||||
assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
|
||||
|
||||
// Assign output.
|
||||
assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Transaction Throttling:
|
||||
//
|
||||
// Stall commands if FIFO is full or there is no valid command information
|
||||
// from AW.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Propagate masked valid.
|
||||
assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
|
||||
|
||||
// Return ready with push back.
|
||||
assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
|
||||
|
||||
// End of burst.
|
||||
assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Write propagation:
|
||||
//
|
||||
// All information is simply forwarded on from the SI- to MI-Side untouched.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// 1:1 mapping.
|
||||
assign M_AXI_WID = S_AXI_WID;
|
||||
assign M_AXI_WDATA = S_AXI_WDATA;
|
||||
assign M_AXI_WSTRB = S_AXI_WSTRB;
|
||||
assign M_AXI_WLAST = S_AXI_WLAST;
|
||||
assign M_AXI_WUSER = S_AXI_WUSER;
|
||||
|
||||
|
||||
endmodule
|
||||
+6066
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
+31715
File diff suppressed because it is too large
Load Diff
+10519
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,138 @@
|
||||
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Generic Functions used by AXI Infrastructure Modules
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
// Global Parameters:
|
||||
//
|
||||
// Functions:
|
||||
//
|
||||
// Tasks:
|
||||
//--------------------------------------------------------------------------
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN Global Parameters
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
localparam G_AXI_AWADDR_INDEX = 0;
|
||||
localparam G_AXI_AWADDR_WIDTH = C_AXI_ADDR_WIDTH;
|
||||
localparam G_AXI_AWPROT_INDEX = G_AXI_AWADDR_INDEX + G_AXI_AWADDR_WIDTH;
|
||||
localparam G_AXI_AWPROT_WIDTH = 3;
|
||||
localparam G_AXI_AWSIZE_INDEX = G_AXI_AWPROT_INDEX + G_AXI_AWPROT_WIDTH;
|
||||
localparam G_AXI_AWSIZE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 3;
|
||||
localparam G_AXI_AWBURST_INDEX = G_AXI_AWSIZE_INDEX + G_AXI_AWSIZE_WIDTH;
|
||||
localparam G_AXI_AWBURST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 2;
|
||||
localparam G_AXI_AWCACHE_INDEX = G_AXI_AWBURST_INDEX + G_AXI_AWBURST_WIDTH;
|
||||
localparam G_AXI_AWCACHE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4;
|
||||
localparam G_AXI_AWLEN_INDEX = G_AXI_AWCACHE_INDEX + G_AXI_AWCACHE_WIDTH;
|
||||
localparam G_AXI_AWLEN_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8;
|
||||
localparam G_AXI_AWLOCK_INDEX = G_AXI_AWLEN_INDEX + G_AXI_AWLEN_WIDTH;
|
||||
localparam G_AXI_AWLOCK_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1;
|
||||
localparam G_AXI_AWID_INDEX = G_AXI_AWLOCK_INDEX + G_AXI_AWLOCK_WIDTH;
|
||||
localparam G_AXI_AWID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
|
||||
localparam G_AXI_AWQOS_INDEX = G_AXI_AWID_INDEX + G_AXI_AWID_WIDTH;
|
||||
localparam G_AXI_AWQOS_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4;
|
||||
localparam G_AXI_AWREGION_INDEX = G_AXI_AWQOS_INDEX + G_AXI_AWQOS_WIDTH;
|
||||
localparam G_AXI_AWREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4;
|
||||
localparam G_AXI_AWUSER_INDEX = G_AXI_AWREGION_INDEX + G_AXI_AWREGION_WIDTH;
|
||||
localparam G_AXI_AWUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_AWUSER_WIDTH;
|
||||
localparam G_AXI_AWPAYLOAD_WIDTH = G_AXI_AWUSER_INDEX + G_AXI_AWUSER_WIDTH;
|
||||
localparam G_AXI_ARADDR_INDEX = 0;
|
||||
localparam G_AXI_ARADDR_WIDTH = C_AXI_ADDR_WIDTH;
|
||||
localparam G_AXI_ARPROT_INDEX = G_AXI_ARADDR_INDEX + G_AXI_ARADDR_WIDTH;
|
||||
localparam G_AXI_ARPROT_WIDTH = 3;
|
||||
localparam G_AXI_ARSIZE_INDEX = G_AXI_ARPROT_INDEX + G_AXI_ARPROT_WIDTH;
|
||||
localparam G_AXI_ARSIZE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 3;
|
||||
localparam G_AXI_ARBURST_INDEX = G_AXI_ARSIZE_INDEX + G_AXI_ARSIZE_WIDTH;
|
||||
localparam G_AXI_ARBURST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 2;
|
||||
localparam G_AXI_ARCACHE_INDEX = G_AXI_ARBURST_INDEX + G_AXI_ARBURST_WIDTH;
|
||||
localparam G_AXI_ARCACHE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4;
|
||||
localparam G_AXI_ARLEN_INDEX = G_AXI_ARCACHE_INDEX + G_AXI_ARCACHE_WIDTH;
|
||||
localparam G_AXI_ARLEN_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8;
|
||||
localparam G_AXI_ARLOCK_INDEX = G_AXI_ARLEN_INDEX + G_AXI_ARLEN_WIDTH;
|
||||
localparam G_AXI_ARLOCK_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1;
|
||||
localparam G_AXI_ARID_INDEX = G_AXI_ARLOCK_INDEX + G_AXI_ARLOCK_WIDTH;
|
||||
localparam G_AXI_ARID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
|
||||
localparam G_AXI_ARQOS_INDEX = G_AXI_ARID_INDEX + G_AXI_ARID_WIDTH;
|
||||
localparam G_AXI_ARQOS_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4;
|
||||
localparam G_AXI_ARREGION_INDEX = G_AXI_ARQOS_INDEX + G_AXI_ARQOS_WIDTH;
|
||||
localparam G_AXI_ARREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4;
|
||||
localparam G_AXI_ARUSER_INDEX = G_AXI_ARREGION_INDEX + G_AXI_ARREGION_WIDTH;
|
||||
localparam G_AXI_ARUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_ARUSER_WIDTH;
|
||||
localparam G_AXI_ARPAYLOAD_WIDTH = G_AXI_ARUSER_INDEX + G_AXI_ARUSER_WIDTH;
|
||||
// Write channel widths
|
||||
localparam G_AXI_WDATA_INDEX = 0;
|
||||
localparam G_AXI_WDATA_WIDTH = C_AXI_DATA_WIDTH;
|
||||
localparam G_AXI_WSTRB_INDEX = G_AXI_WDATA_INDEX + G_AXI_WDATA_WIDTH;
|
||||
localparam G_AXI_WSTRB_WIDTH = C_AXI_DATA_WIDTH / 8;
|
||||
localparam G_AXI_WLAST_INDEX = G_AXI_WSTRB_INDEX + G_AXI_WSTRB_WIDTH;
|
||||
localparam G_AXI_WLAST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 1;
|
||||
localparam G_AXI_WID_INDEX = G_AXI_WLAST_INDEX + G_AXI_WLAST_WIDTH;
|
||||
localparam G_AXI_WID_WIDTH = (C_AXI_PROTOCOL != 1) ? 0 : C_AXI_ID_WIDTH;
|
||||
localparam G_AXI_WUSER_INDEX = G_AXI_WID_INDEX + G_AXI_WID_WIDTH;
|
||||
localparam G_AXI_WUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_WUSER_WIDTH;
|
||||
localparam G_AXI_WPAYLOAD_WIDTH = G_AXI_WUSER_INDEX + G_AXI_WUSER_WIDTH;
|
||||
// Write Response channel Widths
|
||||
localparam G_AXI_BRESP_INDEX = 0;
|
||||
localparam G_AXI_BRESP_WIDTH = 2;
|
||||
localparam G_AXI_BID_INDEX = G_AXI_BRESP_INDEX + G_AXI_BRESP_WIDTH;
|
||||
localparam G_AXI_BID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
|
||||
localparam G_AXI_BUSER_INDEX = G_AXI_BID_INDEX + G_AXI_BID_WIDTH;
|
||||
localparam G_AXI_BUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_BUSER_WIDTH;
|
||||
localparam G_AXI_BPAYLOAD_WIDTH = G_AXI_BUSER_INDEX + G_AXI_BUSER_WIDTH;
|
||||
// Read channel widths
|
||||
localparam G_AXI_RDATA_INDEX = 0;
|
||||
localparam G_AXI_RDATA_WIDTH = C_AXI_DATA_WIDTH;
|
||||
localparam G_AXI_RRESP_INDEX = G_AXI_RDATA_INDEX + G_AXI_RDATA_WIDTH;
|
||||
localparam G_AXI_RRESP_WIDTH = 2;
|
||||
localparam G_AXI_RLAST_INDEX = G_AXI_RRESP_INDEX + G_AXI_RRESP_WIDTH;
|
||||
localparam G_AXI_RLAST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 1;
|
||||
localparam G_AXI_RID_INDEX = G_AXI_RLAST_INDEX + G_AXI_RLAST_WIDTH;
|
||||
localparam G_AXI_RID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
|
||||
localparam G_AXI_RUSER_INDEX = G_AXI_RID_INDEX + G_AXI_RID_WIDTH;
|
||||
localparam G_AXI_RUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_RUSER_WIDTH;
|
||||
localparam G_AXI_RPAYLOAD_WIDTH = G_AXI_RUSER_INDEX + G_AXI_RUSER_WIDTH;
|
||||
@@ -0,0 +1,670 @@
|
||||
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// axis to vector
|
||||
// A generic module to merge all axi signals into one signal called payload.
|
||||
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||
module axi_infrastructure_v1_1_0_axi2vector #
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Parameter Definitions
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
parameter integer C_AXI_PROTOCOL = 0,
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
parameter integer C_AXI_DATA_WIDTH = 32,
|
||||
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
|
||||
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_WUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_BUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_ARUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_RUSER_WIDTH = 1,
|
||||
parameter integer C_AWPAYLOAD_WIDTH = 61,
|
||||
parameter integer C_WPAYLOAD_WIDTH = 73,
|
||||
parameter integer C_BPAYLOAD_WIDTH = 6,
|
||||
parameter integer C_ARPAYLOAD_WIDTH = 61,
|
||||
parameter integer C_RPAYLOAD_WIDTH = 69
|
||||
)
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Port Declarations
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Slave Interface Write Address Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
|
||||
input wire [3-1:0] s_axi_awsize,
|
||||
input wire [2-1:0] s_axi_awburst,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
|
||||
input wire [4-1:0] s_axi_awcache,
|
||||
input wire [3-1:0] s_axi_awprot,
|
||||
input wire [4-1:0] s_axi_awregion,
|
||||
input wire [4-1:0] s_axi_awqos,
|
||||
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
|
||||
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
|
||||
input wire s_axi_wlast,
|
||||
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
|
||||
output wire [2-1:0] s_axi_bresp,
|
||||
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
|
||||
|
||||
// Slave Interface Read Address Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
|
||||
input wire [3-1:0] s_axi_arsize,
|
||||
input wire [2-1:0] s_axi_arburst,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
|
||||
input wire [4-1:0] s_axi_arcache,
|
||||
input wire [3-1:0] s_axi_arprot,
|
||||
input wire [4-1:0] s_axi_arregion,
|
||||
input wire [4-1:0] s_axi_arqos,
|
||||
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
|
||||
|
||||
// Slave Interface Read Data Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
|
||||
output wire [2-1:0] s_axi_rresp,
|
||||
output wire s_axi_rlast,
|
||||
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
|
||||
|
||||
// payloads
|
||||
output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload,
|
||||
output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload,
|
||||
input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload,
|
||||
output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload,
|
||||
input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
`include "axi_infrastructure_v1_1_0.vh"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Local parameters
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Wires/Reg declarations
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN RTL
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// AXI4, AXI4LITE, AXI3 packing
|
||||
assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;
|
||||
assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;
|
||||
|
||||
assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;
|
||||
assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;
|
||||
|
||||
assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];
|
||||
|
||||
assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;
|
||||
assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;
|
||||
|
||||
assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];
|
||||
assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];
|
||||
|
||||
generate
|
||||
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
|
||||
assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize;
|
||||
assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;
|
||||
assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;
|
||||
assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen;
|
||||
assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock;
|
||||
assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid;
|
||||
assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos;
|
||||
|
||||
assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast;
|
||||
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
|
||||
assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid;
|
||||
end
|
||||
else begin : gen_no_axi3_wid_packing
|
||||
end
|
||||
|
||||
assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];
|
||||
|
||||
assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize;
|
||||
assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;
|
||||
assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;
|
||||
assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen;
|
||||
assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock;
|
||||
assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid;
|
||||
assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos;
|
||||
|
||||
assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];
|
||||
assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];
|
||||
|
||||
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
|
||||
assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;
|
||||
assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;
|
||||
end
|
||||
else begin : gen_no_region_signals
|
||||
end
|
||||
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
|
||||
assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;
|
||||
assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser;
|
||||
assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];
|
||||
assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;
|
||||
assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];
|
||||
end
|
||||
else begin : gen_no_user_signals
|
||||
assign s_axi_buser = 'b0;
|
||||
assign s_axi_ruser = 'b0;
|
||||
end
|
||||
end
|
||||
else begin : gen_axi4lite_packing
|
||||
assign s_axi_bid = 'b0;
|
||||
assign s_axi_buser = 'b0;
|
||||
|
||||
assign s_axi_rlast = 1'b1;
|
||||
assign s_axi_rid = 'b0;
|
||||
assign s_axi_ruser = 'b0;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
|
||||
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
// Description: SRL based FIFO for AXIS/AXI Channels.
|
||||
//--------------------------------------------------------------------------
|
||||
|
||||
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||
module axi_infrastructure_v1_1_0_axic_srl_fifo #(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Parameter Definitions
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
parameter C_FAMILY = "virtex7",
|
||||
parameter integer C_PAYLOAD_WIDTH = 1,
|
||||
parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
|
||||
)
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Port Declarations
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
input wire aclk, // Clock
|
||||
input wire aresetn, // Reset
|
||||
input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data
|
||||
input wire s_valid, // Input data valid
|
||||
output reg s_ready, // Input data ready
|
||||
output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data
|
||||
output reg m_valid, // Output data valid
|
||||
input wire m_ready // Output data ready
|
||||
);
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// ceiling logb2
|
||||
function integer f_clogb2 (input integer size);
|
||||
integer s;
|
||||
begin
|
||||
s = size;
|
||||
s = s - 1;
|
||||
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
|
||||
s = s >> 1;
|
||||
end
|
||||
endfunction // clogb2
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Local parameters
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Wires/Reg declarations
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index;
|
||||
wire [4-1:0] fifo_addr;
|
||||
wire push;
|
||||
wire pop ;
|
||||
reg areset_r1;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN RTL
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
always @(posedge aclk) begin
|
||||
areset_r1 <= ~aresetn;
|
||||
end
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (~aresetn) begin
|
||||
fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
|
||||
end
|
||||
else begin
|
||||
fifo_index <= push & ~pop ? fifo_index + 1'b1 :
|
||||
~push & pop ? fifo_index - 1'b1 :
|
||||
fifo_index;
|
||||
end
|
||||
end
|
||||
|
||||
assign push = s_valid & s_ready;
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (~aresetn) begin
|
||||
s_ready <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
s_ready <= areset_r1 ? 1'b1 :
|
||||
push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
|
||||
~push & pop ? 1'b1 :
|
||||
s_ready;
|
||||
end
|
||||
end
|
||||
|
||||
assign pop = m_valid & m_ready;
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (~aresetn) begin
|
||||
m_valid <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
|
||||
push & ~pop ? 1'b1 :
|
||||
m_valid;
|
||||
end
|
||||
end
|
||||
|
||||
generate
|
||||
if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
|
||||
assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
|
||||
assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
|
||||
end
|
||||
else begin : gen_fifo_addr
|
||||
assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
|
||||
SRL16E
|
||||
u_srl_fifo(
|
||||
.Q ( m_payload[i] ) ,
|
||||
.A0 ( fifo_addr[0] ) ,
|
||||
.A1 ( fifo_addr[1] ) ,
|
||||
.A2 ( fifo_addr[2] ) ,
|
||||
.A3 ( fifo_addr[3] ) ,
|
||||
.CE ( push ) ,
|
||||
.CLK ( aclk ) ,
|
||||
.D ( s_payload[i] )
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
|
||||
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// axi to vector
|
||||
// A generic module to merge all axi signals into one signal called payload.
|
||||
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||
module axi_infrastructure_v1_1_0_vector2axi #
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Parameter Definitions
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
parameter integer C_AXI_PROTOCOL = 0,
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
parameter integer C_AXI_DATA_WIDTH = 32,
|
||||
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
|
||||
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_WUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_BUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_ARUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_RUSER_WIDTH = 1,
|
||||
parameter integer C_AWPAYLOAD_WIDTH = 61,
|
||||
parameter integer C_WPAYLOAD_WIDTH = 73,
|
||||
parameter integer C_BPAYLOAD_WIDTH = 6,
|
||||
parameter integer C_ARPAYLOAD_WIDTH = 61,
|
||||
parameter integer C_RPAYLOAD_WIDTH = 69
|
||||
)
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Port Declarations
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Slave Interface Write Address Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
|
||||
output wire [3-1:0] m_axi_awsize,
|
||||
output wire [2-1:0] m_axi_awburst,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
|
||||
output wire [4-1:0] m_axi_awcache,
|
||||
output wire [3-1:0] m_axi_awprot,
|
||||
output wire [4-1:0] m_axi_awregion,
|
||||
output wire [4-1:0] m_axi_awqos,
|
||||
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
|
||||
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
|
||||
output wire m_axi_wlast,
|
||||
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
|
||||
input wire [2-1:0] m_axi_bresp,
|
||||
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
|
||||
|
||||
// Slave Interface Read Address Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
|
||||
output wire [3-1:0] m_axi_arsize,
|
||||
output wire [2-1:0] m_axi_arburst,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
|
||||
output wire [4-1:0] m_axi_arcache,
|
||||
output wire [3-1:0] m_axi_arprot,
|
||||
output wire [4-1:0] m_axi_arregion,
|
||||
output wire [4-1:0] m_axi_arqos,
|
||||
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
|
||||
|
||||
// Slave Interface Read Data Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
|
||||
input wire [2-1:0] m_axi_rresp,
|
||||
input wire m_axi_rlast,
|
||||
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
|
||||
|
||||
// payloads
|
||||
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
|
||||
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
|
||||
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
|
||||
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
|
||||
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
`include "axi_infrastructure_v1_1_0.vh"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Local parameters
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Wires/Reg declarations
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN RTL
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// AXI4, AXI4LITE, AXI3 packing
|
||||
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
|
||||
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
|
||||
|
||||
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
|
||||
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
|
||||
|
||||
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
|
||||
|
||||
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
|
||||
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
|
||||
|
||||
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
|
||||
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
|
||||
|
||||
generate
|
||||
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
|
||||
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
|
||||
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
|
||||
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
|
||||
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
|
||||
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
|
||||
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
|
||||
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
|
||||
|
||||
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
|
||||
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
|
||||
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
|
||||
end
|
||||
else begin : gen_no_axi3_wid_packing
|
||||
assign m_axi_wid = 1'b0;
|
||||
end
|
||||
|
||||
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
|
||||
|
||||
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
|
||||
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
|
||||
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
|
||||
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
|
||||
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
|
||||
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
|
||||
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
|
||||
|
||||
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
|
||||
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
|
||||
|
||||
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
|
||||
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
|
||||
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
|
||||
end
|
||||
else begin : gen_no_region_signals
|
||||
assign m_axi_awregion = 'b0;
|
||||
assign m_axi_arregion = 'b0;
|
||||
end
|
||||
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
|
||||
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
|
||||
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
|
||||
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
|
||||
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
|
||||
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
|
||||
end
|
||||
else begin : gen_no_user_signals
|
||||
assign m_axi_awuser = 'b0;
|
||||
assign m_axi_wuser = 'b0;
|
||||
assign m_axi_aruser = 'b0;
|
||||
end
|
||||
end
|
||||
else begin : gen_axi4lite_packing
|
||||
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
|
||||
assign m_axi_awburst = 'b0;
|
||||
assign m_axi_awcache = 'b0;
|
||||
assign m_axi_awlen = 'b0;
|
||||
assign m_axi_awlock = 'b0;
|
||||
assign m_axi_awid = 'b0;
|
||||
assign m_axi_awqos = 'b0;
|
||||
|
||||
assign m_axi_wlast = 1'b1;
|
||||
assign m_axi_wid = 'b0;
|
||||
|
||||
|
||||
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
|
||||
assign m_axi_arburst = 'b0;
|
||||
assign m_axi_arcache = 'b0;
|
||||
assign m_axi_arlen = 'b0;
|
||||
assign m_axi_arlock = 'b0;
|
||||
assign m_axi_arid = 'b0;
|
||||
assign m_axi_arqos = 'b0;
|
||||
|
||||
assign m_axi_awregion = 'b0;
|
||||
assign m_axi_arregion = 'b0;
|
||||
|
||||
assign m_axi_awuser = 'b0;
|
||||
assign m_axi_wuser = 'b0;
|
||||
assign m_axi_aruser = 'b0;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,292 @@
|
||||
{
|
||||
"version": "1.0",
|
||||
"modules": {
|
||||
"system": {
|
||||
"proto_instances": {
|
||||
"/mydna_read_v1_0_0/s00_axi": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "s00_axi_aclk"},
|
||||
"ARADDR": { "actual": "s00_axi_araddr[3:0]"},
|
||||
"ARESETN": { "actual": "s00_axi_aresetn"},
|
||||
"ARPROT": { "actual": "s00_axi_arprot[2:0]"},
|
||||
"ARREADY": { "actual": "s00_axi_arready"},
|
||||
"ARVALID": { "actual": "s00_axi_arvalid"},
|
||||
"AWADDR": { "actual": "s00_axi_awaddr[3:0]"},
|
||||
"AWPROT": { "actual": "s00_axi_awprot[2:0]"},
|
||||
"AWREADY": { "actual": "s00_axi_awready"},
|
||||
"AWVALID": { "actual": "s00_axi_awvalid"},
|
||||
"BREADY": { "actual": "s00_axi_bready"},
|
||||
"BRESP": { "actual": "s00_axi_bresp[1:0]"},
|
||||
"BVALID": { "actual": "s00_axi_bvalid"},
|
||||
"RDATA": { "actual": "s00_axi_rdata[31:0]"},
|
||||
"RREADY": { "actual": "s00_axi_rready"},
|
||||
"RRESP": { "actual": "s00_axi_rresp[1:0]"},
|
||||
"RVALID": { "actual": "s00_axi_rvalid"},
|
||||
"WDATA": { "actual": "s00_axi_wdata[31:0]"},
|
||||
"WREADY": { "actual": "s00_axi_wready"},
|
||||
"WSTRB": { "actual": "s00_axi_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "s00_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/processing_system7_0/M_AXI_GP0": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "M_AXI_GP0_ACLK"},
|
||||
"ARADDR": { "actual": "M_AXI_GP0_ARADDR[31:0]"},
|
||||
"ARBURST": { "actual": "M_AXI_GP0_ARBURST[1:0]"},
|
||||
"ARCACHE": { "actual": "M_AXI_GP0_ARCACHE[3:0]"},
|
||||
"ARID": { "actual": "M_AXI_GP0_ARID[11:0]"},
|
||||
"ARLEN": { "actual": "M_AXI_GP0_ARLEN[3:0]"},
|
||||
"ARLOCK": { "actual": "M_AXI_GP0_ARLOCK[1:0]"},
|
||||
"ARPROT": { "actual": "M_AXI_GP0_ARPROT[2:0]"},
|
||||
"ARQOS": { "actual": "M_AXI_GP0_ARQOS[3:0]"},
|
||||
"ARREADY": { "actual": "M_AXI_GP0_ARREADY"},
|
||||
"ARSIZE": { "actual": "M_AXI_GP0_ARSIZE[2:0]"},
|
||||
"ARVALID": { "actual": "M_AXI_GP0_ARVALID"},
|
||||
"AWADDR": { "actual": "M_AXI_GP0_AWADDR[31:0]"},
|
||||
"AWBURST": { "actual": "M_AXI_GP0_AWBURST[1:0]"},
|
||||
"AWCACHE": { "actual": "M_AXI_GP0_AWCACHE[3:0]"},
|
||||
"AWID": { "actual": "M_AXI_GP0_AWID[11:0]"},
|
||||
"AWLEN": { "actual": "M_AXI_GP0_AWLEN[3:0]"},
|
||||
"AWLOCK": { "actual": "M_AXI_GP0_AWLOCK[1:0]"},
|
||||
"AWPROT": { "actual": "M_AXI_GP0_AWPROT[2:0]"},
|
||||
"AWQOS": { "actual": "M_AXI_GP0_AWQOS[3:0]"},
|
||||
"AWREADY": { "actual": "M_AXI_GP0_AWREADY"},
|
||||
"AWSIZE": { "actual": "M_AXI_GP0_AWSIZE[2:0]"},
|
||||
"AWVALID": { "actual": "M_AXI_GP0_AWVALID"},
|
||||
"BID": { "actual": "M_AXI_GP0_BID[11:0]"},
|
||||
"BREADY": { "actual": "M_AXI_GP0_BREADY"},
|
||||
"BRESP": { "actual": "M_AXI_GP0_BRESP[1:0]"},
|
||||
"BVALID": { "actual": "M_AXI_GP0_BVALID"},
|
||||
"RDATA": { "actual": "M_AXI_GP0_RDATA[31:0]"},
|
||||
"RID": { "actual": "M_AXI_GP0_RID[11:0]"},
|
||||
"RLAST": { "actual": "M_AXI_GP0_RLAST"},
|
||||
"RREADY": { "actual": "M_AXI_GP0_RREADY"},
|
||||
"RRESP": { "actual": "M_AXI_GP0_RRESP[1:0]"},
|
||||
"RVALID": { "actual": "M_AXI_GP0_RVALID"},
|
||||
"WDATA": { "actual": "M_AXI_GP0_WDATA[31:0]"},
|
||||
"WID": { "actual": "M_AXI_GP0_WID[11:0]"},
|
||||
"WLAST": { "actual": "M_AXI_GP0_WLAST"},
|
||||
"WREADY": { "actual": "M_AXI_GP0_WREADY"},
|
||||
"WSTRB": { "actual": "M_AXI_GP0_WSTRB[3:0]"},
|
||||
"WVALID": { "actual": "M_AXI_GP0_WVALID"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/M00_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "M00_ACLK"},
|
||||
"ARADDR": { "actual": "M00_AXI_araddr[31:0]"},
|
||||
"ARESETN": { "actual": "ARESETN"},
|
||||
"ARPROT": { "actual": "M00_AXI_arprot[2:0]"},
|
||||
"ARREADY": { "actual": "M00_AXI_arready"},
|
||||
"ARVALID": { "actual": "M00_AXI_arvalid"},
|
||||
"AWADDR": { "actual": "M00_AXI_awaddr[31:0]"},
|
||||
"AWPROT": { "actual": "M00_AXI_awprot[2:0]"},
|
||||
"AWREADY": { "actual": "M00_AXI_awready"},
|
||||
"AWVALID": { "actual": "M00_AXI_awvalid"},
|
||||
"BREADY": { "actual": "M00_AXI_bready"},
|
||||
"BRESP": { "actual": "M00_AXI_bresp[1:0]"},
|
||||
"BVALID": { "actual": "M00_AXI_bvalid"},
|
||||
"RDATA": { "actual": "M00_AXI_rdata[31:0]"},
|
||||
"RREADY": { "actual": "M00_AXI_rready"},
|
||||
"RRESP": { "actual": "M00_AXI_rresp[1:0]"},
|
||||
"RVALID": { "actual": "M00_AXI_rvalid"},
|
||||
"WDATA": { "actual": "M00_AXI_wdata[31:0]"},
|
||||
"WREADY": { "actual": "M00_AXI_wready"},
|
||||
"WSTRB": { "actual": "M00_AXI_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "M00_AXI_wvalid"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/S00_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "S00_ACLK"},
|
||||
"ARADDR": { "actual": "S00_AXI_araddr[31:0]"},
|
||||
"ARBURST": { "actual": "S00_AXI_arburst[1:0]"},
|
||||
"ARCACHE": { "actual": "S00_AXI_arcache[3:0]"},
|
||||
"ARESETN": { "actual": "ARESETN"},
|
||||
"ARID": { "actual": "S00_AXI_arid[11:0]"},
|
||||
"ARLEN": { "actual": "S00_AXI_arlen[3:0]"},
|
||||
"ARLOCK": { "actual": "S00_AXI_arlock[1:0]"},
|
||||
"ARPROT": { "actual": "S00_AXI_arprot[2:0]"},
|
||||
"ARQOS": { "actual": "S00_AXI_arqos[3:0]"},
|
||||
"ARREADY": { "actual": "S00_AXI_arready"},
|
||||
"ARSIZE": { "actual": "S00_AXI_arsize[2:0]"},
|
||||
"ARVALID": { "actual": "S00_AXI_arvalid"},
|
||||
"AWADDR": { "actual": "S00_AXI_awaddr[31:0]"},
|
||||
"AWBURST": { "actual": "S00_AXI_awburst[1:0]"},
|
||||
"AWCACHE": { "actual": "S00_AXI_awcache[3:0]"},
|
||||
"AWID": { "actual": "S00_AXI_awid[11:0]"},
|
||||
"AWLEN": { "actual": "S00_AXI_awlen[3:0]"},
|
||||
"AWLOCK": { "actual": "S00_AXI_awlock[1:0]"},
|
||||
"AWPROT": { "actual": "S00_AXI_awprot[2:0]"},
|
||||
"AWQOS": { "actual": "S00_AXI_awqos[3:0]"},
|
||||
"AWREADY": { "actual": "S00_AXI_awready"},
|
||||
"AWSIZE": { "actual": "S00_AXI_awsize[2:0]"},
|
||||
"AWVALID": { "actual": "S00_AXI_awvalid"},
|
||||
"BID": { "actual": "S00_AXI_bid[11:0]"},
|
||||
"BREADY": { "actual": "S00_AXI_bready"},
|
||||
"BRESP": { "actual": "S00_AXI_bresp[1:0]"},
|
||||
"BVALID": { "actual": "S00_AXI_bvalid"},
|
||||
"RDATA": { "actual": "S00_AXI_rdata[31:0]"},
|
||||
"RID": { "actual": "S00_AXI_rid[11:0]"},
|
||||
"RLAST": { "actual": "S00_AXI_rlast"},
|
||||
"RREADY": { "actual": "S00_AXI_rready"},
|
||||
"RRESP": { "actual": "S00_AXI_rresp[1:0]"},
|
||||
"RVALID": { "actual": "S00_AXI_rvalid"},
|
||||
"WDATA": { "actual": "S00_AXI_wdata[31:0]"},
|
||||
"WID": { "actual": "S00_AXI_wid[11:0]"},
|
||||
"WLAST": { "actual": "S00_AXI_wlast"},
|
||||
"WREADY": { "actual": "S00_AXI_wready"},
|
||||
"WSTRB": { "actual": "S00_AXI_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "S00_AXI_wvalid"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/s00_couplers/M_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "M_ACLK"},
|
||||
"ARADDR": { "actual": "M_AXI_araddr[31:0]"},
|
||||
"ARESETN": { "actual": "M_ARESETN"},
|
||||
"ARPROT": { "actual": "M_AXI_arprot[2:0]"},
|
||||
"ARREADY": { "actual": "M_AXI_arready"},
|
||||
"ARVALID": { "actual": "M_AXI_arvalid"},
|
||||
"AWADDR": { "actual": "M_AXI_awaddr[31:0]"},
|
||||
"AWPROT": { "actual": "M_AXI_awprot[2:0]"},
|
||||
"AWREADY": { "actual": "M_AXI_awready"},
|
||||
"AWVALID": { "actual": "M_AXI_awvalid"},
|
||||
"BREADY": { "actual": "M_AXI_bready"},
|
||||
"BRESP": { "actual": "M_AXI_bresp[1:0]"},
|
||||
"BVALID": { "actual": "M_AXI_bvalid"},
|
||||
"RDATA": { "actual": "M_AXI_rdata[31:0]"},
|
||||
"RREADY": { "actual": "M_AXI_rready"},
|
||||
"RRESP": { "actual": "M_AXI_rresp[1:0]"},
|
||||
"RVALID": { "actual": "M_AXI_rvalid"},
|
||||
"WDATA": { "actual": "M_AXI_wdata[31:0]"},
|
||||
"WREADY": { "actual": "M_AXI_wready"},
|
||||
"WSTRB": { "actual": "M_AXI_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "M_AXI_wvalid"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/s00_couplers/S_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "S_ACLK"},
|
||||
"ARADDR": { "actual": "S_AXI_araddr[31:0]"},
|
||||
"ARBURST": { "actual": "S_AXI_arburst[1:0]"},
|
||||
"ARCACHE": { "actual": "S_AXI_arcache[3:0]"},
|
||||
"ARESETN": { "actual": "S_ARESETN"},
|
||||
"ARID": { "actual": "S_AXI_arid[11:0]"},
|
||||
"ARLEN": { "actual": "S_AXI_arlen[3:0]"},
|
||||
"ARLOCK": { "actual": "S_AXI_arlock[1:0]"},
|
||||
"ARPROT": { "actual": "S_AXI_arprot[2:0]"},
|
||||
"ARQOS": { "actual": "S_AXI_arqos[3:0]"},
|
||||
"ARREADY": { "actual": "S_AXI_arready"},
|
||||
"ARSIZE": { "actual": "S_AXI_arsize[2:0]"},
|
||||
"ARVALID": { "actual": "S_AXI_arvalid"},
|
||||
"AWADDR": { "actual": "S_AXI_awaddr[31:0]"},
|
||||
"AWBURST": { "actual": "S_AXI_awburst[1:0]"},
|
||||
"AWCACHE": { "actual": "S_AXI_awcache[3:0]"},
|
||||
"AWID": { "actual": "S_AXI_awid[11:0]"},
|
||||
"AWLEN": { "actual": "S_AXI_awlen[3:0]"},
|
||||
"AWLOCK": { "actual": "S_AXI_awlock[1:0]"},
|
||||
"AWPROT": { "actual": "S_AXI_awprot[2:0]"},
|
||||
"AWQOS": { "actual": "S_AXI_awqos[3:0]"},
|
||||
"AWREADY": { "actual": "S_AXI_awready"},
|
||||
"AWSIZE": { "actual": "S_AXI_awsize[2:0]"},
|
||||
"AWVALID": { "actual": "S_AXI_awvalid"},
|
||||
"BID": { "actual": "S_AXI_bid[11:0]"},
|
||||
"BREADY": { "actual": "S_AXI_bready"},
|
||||
"BRESP": { "actual": "S_AXI_bresp[1:0]"},
|
||||
"BVALID": { "actual": "S_AXI_bvalid"},
|
||||
"RDATA": { "actual": "S_AXI_rdata[31:0]"},
|
||||
"RID": { "actual": "S_AXI_rid[11:0]"},
|
||||
"RLAST": { "actual": "S_AXI_rlast"},
|
||||
"RREADY": { "actual": "S_AXI_rready"},
|
||||
"RRESP": { "actual": "S_AXI_rresp[1:0]"},
|
||||
"RVALID": { "actual": "S_AXI_rvalid"},
|
||||
"WDATA": { "actual": "S_AXI_wdata[31:0]"},
|
||||
"WID": { "actual": "S_AXI_wid[11:0]"},
|
||||
"WLAST": { "actual": "S_AXI_wlast"},
|
||||
"WREADY": { "actual": "S_AXI_wready"},
|
||||
"WSTRB": { "actual": "S_AXI_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "S_AXI_wvalid"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/s00_couplers/auto_pc/M_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "m_axi_araddr[31:0]"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARPROT": { "actual": "m_axi_arprot[2:0]"},
|
||||
"ARREADY": { "actual": "m_axi_arready"},
|
||||
"ARVALID": { "actual": "m_axi_arvalid"},
|
||||
"AWADDR": { "actual": "m_axi_awaddr[31:0]"},
|
||||
"AWPROT": { "actual": "m_axi_awprot[2:0]"},
|
||||
"AWREADY": { "actual": "m_axi_awready"},
|
||||
"AWVALID": { "actual": "m_axi_awvalid"},
|
||||
"BREADY": { "actual": "m_axi_bready"},
|
||||
"BRESP": { "actual": "m_axi_bresp[1:0]"},
|
||||
"BVALID": { "actual": "m_axi_bvalid"},
|
||||
"RDATA": { "actual": "m_axi_rdata[31:0]"},
|
||||
"RREADY": { "actual": "m_axi_rready"},
|
||||
"RRESP": { "actual": "m_axi_rresp[1:0]"},
|
||||
"RVALID": { "actual": "m_axi_rvalid"},
|
||||
"WDATA": { "actual": "m_axi_wdata[31:0]"},
|
||||
"WREADY": { "actual": "m_axi_wready"},
|
||||
"WSTRB": { "actual": "m_axi_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "m_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/s00_couplers/auto_pc/S_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "s_axi_araddr[31:0]"},
|
||||
"ARBURST": { "actual": "s_axi_arburst[1:0]"},
|
||||
"ARCACHE": { "actual": "s_axi_arcache[3:0]"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARID": { "actual": "s_axi_arid[11:0]"},
|
||||
"ARLEN": { "actual": "s_axi_arlen[3:0]"},
|
||||
"ARLOCK": { "actual": "s_axi_arlock[1:0]"},
|
||||
"ARPROT": { "actual": "s_axi_arprot[2:0]"},
|
||||
"ARQOS": { "actual": "s_axi_arqos[3:0]"},
|
||||
"ARREADY": { "actual": "s_axi_arready"},
|
||||
"ARSIZE": { "actual": "s_axi_arsize[2:0]"},
|
||||
"ARVALID": { "actual": "s_axi_arvalid"},
|
||||
"AWADDR": { "actual": "s_axi_awaddr[31:0]"},
|
||||
"AWBURST": { "actual": "s_axi_awburst[1:0]"},
|
||||
"AWCACHE": { "actual": "s_axi_awcache[3:0]"},
|
||||
"AWID": { "actual": "s_axi_awid[11:0]"},
|
||||
"AWLEN": { "actual": "s_axi_awlen[3:0]"},
|
||||
"AWLOCK": { "actual": "s_axi_awlock[1:0]"},
|
||||
"AWPROT": { "actual": "s_axi_awprot[2:0]"},
|
||||
"AWQOS": { "actual": "s_axi_awqos[3:0]"},
|
||||
"AWREADY": { "actual": "s_axi_awready"},
|
||||
"AWSIZE": { "actual": "s_axi_awsize[2:0]"},
|
||||
"AWVALID": { "actual": "s_axi_awvalid"},
|
||||
"BID": { "actual": "s_axi_bid[11:0]"},
|
||||
"BREADY": { "actual": "s_axi_bready"},
|
||||
"BRESP": { "actual": "s_axi_bresp[1:0]"},
|
||||
"BVALID": { "actual": "s_axi_bvalid"},
|
||||
"RDATA": { "actual": "s_axi_rdata[31:0]"},
|
||||
"RID": { "actual": "s_axi_rid[11:0]"},
|
||||
"RLAST": { "actual": "s_axi_rlast"},
|
||||
"RREADY": { "actual": "s_axi_rready"},
|
||||
"RRESP": { "actual": "s_axi_rresp[1:0]"},
|
||||
"RVALID": { "actual": "s_axi_rvalid"},
|
||||
"WDATA": { "actual": "s_axi_wdata[31:0]"},
|
||||
"WID": { "actual": "s_axi_wid[11:0]"},
|
||||
"WLAST": { "actual": "s_axi_wlast"},
|
||||
"WREADY": { "actual": "s_axi_wready"},
|
||||
"WSTRB": { "actual": "s_axi_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "s_axi_wvalid"}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,945 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
//Date : Mon May 25 14:51:47 2026
|
||||
//Host : mkb running 64-bit unknown
|
||||
//Command : generate_target system.bd
|
||||
//Design : system
|
||||
//Purpose : IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module s00_couplers_imp_11SE3QO
|
||||
(M_ACLK,
|
||||
M_ARESETN,
|
||||
M_AXI_araddr,
|
||||
M_AXI_arprot,
|
||||
M_AXI_arready,
|
||||
M_AXI_arvalid,
|
||||
M_AXI_awaddr,
|
||||
M_AXI_awprot,
|
||||
M_AXI_awready,
|
||||
M_AXI_awvalid,
|
||||
M_AXI_bready,
|
||||
M_AXI_bresp,
|
||||
M_AXI_bvalid,
|
||||
M_AXI_rdata,
|
||||
M_AXI_rready,
|
||||
M_AXI_rresp,
|
||||
M_AXI_rvalid,
|
||||
M_AXI_wdata,
|
||||
M_AXI_wready,
|
||||
M_AXI_wstrb,
|
||||
M_AXI_wvalid,
|
||||
S_ACLK,
|
||||
S_ARESETN,
|
||||
S_AXI_araddr,
|
||||
S_AXI_arburst,
|
||||
S_AXI_arcache,
|
||||
S_AXI_arid,
|
||||
S_AXI_arlen,
|
||||
S_AXI_arlock,
|
||||
S_AXI_arprot,
|
||||
S_AXI_arqos,
|
||||
S_AXI_arready,
|
||||
S_AXI_arsize,
|
||||
S_AXI_arvalid,
|
||||
S_AXI_awaddr,
|
||||
S_AXI_awburst,
|
||||
S_AXI_awcache,
|
||||
S_AXI_awid,
|
||||
S_AXI_awlen,
|
||||
S_AXI_awlock,
|
||||
S_AXI_awprot,
|
||||
S_AXI_awqos,
|
||||
S_AXI_awready,
|
||||
S_AXI_awsize,
|
||||
S_AXI_awvalid,
|
||||
S_AXI_bid,
|
||||
S_AXI_bready,
|
||||
S_AXI_bresp,
|
||||
S_AXI_bvalid,
|
||||
S_AXI_rdata,
|
||||
S_AXI_rid,
|
||||
S_AXI_rlast,
|
||||
S_AXI_rready,
|
||||
S_AXI_rresp,
|
||||
S_AXI_rvalid,
|
||||
S_AXI_wdata,
|
||||
S_AXI_wid,
|
||||
S_AXI_wlast,
|
||||
S_AXI_wready,
|
||||
S_AXI_wstrb,
|
||||
S_AXI_wvalid);
|
||||
input M_ACLK;
|
||||
input M_ARESETN;
|
||||
output [31:0]M_AXI_araddr;
|
||||
output [2:0]M_AXI_arprot;
|
||||
input M_AXI_arready;
|
||||
output M_AXI_arvalid;
|
||||
output [31:0]M_AXI_awaddr;
|
||||
output [2:0]M_AXI_awprot;
|
||||
input M_AXI_awready;
|
||||
output M_AXI_awvalid;
|
||||
output M_AXI_bready;
|
||||
input [1:0]M_AXI_bresp;
|
||||
input M_AXI_bvalid;
|
||||
input [31:0]M_AXI_rdata;
|
||||
output M_AXI_rready;
|
||||
input [1:0]M_AXI_rresp;
|
||||
input M_AXI_rvalid;
|
||||
output [31:0]M_AXI_wdata;
|
||||
input M_AXI_wready;
|
||||
output [3:0]M_AXI_wstrb;
|
||||
output M_AXI_wvalid;
|
||||
input S_ACLK;
|
||||
input S_ARESETN;
|
||||
input [31:0]S_AXI_araddr;
|
||||
input [1:0]S_AXI_arburst;
|
||||
input [3:0]S_AXI_arcache;
|
||||
input [11:0]S_AXI_arid;
|
||||
input [3:0]S_AXI_arlen;
|
||||
input [1:0]S_AXI_arlock;
|
||||
input [2:0]S_AXI_arprot;
|
||||
input [3:0]S_AXI_arqos;
|
||||
output S_AXI_arready;
|
||||
input [2:0]S_AXI_arsize;
|
||||
input S_AXI_arvalid;
|
||||
input [31:0]S_AXI_awaddr;
|
||||
input [1:0]S_AXI_awburst;
|
||||
input [3:0]S_AXI_awcache;
|
||||
input [11:0]S_AXI_awid;
|
||||
input [3:0]S_AXI_awlen;
|
||||
input [1:0]S_AXI_awlock;
|
||||
input [2:0]S_AXI_awprot;
|
||||
input [3:0]S_AXI_awqos;
|
||||
output S_AXI_awready;
|
||||
input [2:0]S_AXI_awsize;
|
||||
input S_AXI_awvalid;
|
||||
output [11:0]S_AXI_bid;
|
||||
input S_AXI_bready;
|
||||
output [1:0]S_AXI_bresp;
|
||||
output S_AXI_bvalid;
|
||||
output [31:0]S_AXI_rdata;
|
||||
output [11:0]S_AXI_rid;
|
||||
output S_AXI_rlast;
|
||||
input S_AXI_rready;
|
||||
output [1:0]S_AXI_rresp;
|
||||
output S_AXI_rvalid;
|
||||
input [31:0]S_AXI_wdata;
|
||||
input [11:0]S_AXI_wid;
|
||||
input S_AXI_wlast;
|
||||
output S_AXI_wready;
|
||||
input [3:0]S_AXI_wstrb;
|
||||
input S_AXI_wvalid;
|
||||
|
||||
wire S_ACLK_1;
|
||||
wire S_ARESETN_1;
|
||||
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
|
||||
wire [2:0]auto_pc_to_s00_couplers_ARPROT;
|
||||
wire auto_pc_to_s00_couplers_ARREADY;
|
||||
wire auto_pc_to_s00_couplers_ARVALID;
|
||||
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
|
||||
wire [2:0]auto_pc_to_s00_couplers_AWPROT;
|
||||
wire auto_pc_to_s00_couplers_AWREADY;
|
||||
wire auto_pc_to_s00_couplers_AWVALID;
|
||||
wire auto_pc_to_s00_couplers_BREADY;
|
||||
wire [1:0]auto_pc_to_s00_couplers_BRESP;
|
||||
wire auto_pc_to_s00_couplers_BVALID;
|
||||
wire [31:0]auto_pc_to_s00_couplers_RDATA;
|
||||
wire auto_pc_to_s00_couplers_RREADY;
|
||||
wire [1:0]auto_pc_to_s00_couplers_RRESP;
|
||||
wire auto_pc_to_s00_couplers_RVALID;
|
||||
wire [31:0]auto_pc_to_s00_couplers_WDATA;
|
||||
wire auto_pc_to_s00_couplers_WREADY;
|
||||
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
|
||||
wire auto_pc_to_s00_couplers_WVALID;
|
||||
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
|
||||
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
|
||||
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
|
||||
wire [11:0]s00_couplers_to_auto_pc_ARID;
|
||||
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
|
||||
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
|
||||
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
|
||||
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
|
||||
wire s00_couplers_to_auto_pc_ARREADY;
|
||||
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
|
||||
wire s00_couplers_to_auto_pc_ARVALID;
|
||||
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
|
||||
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
|
||||
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
|
||||
wire [11:0]s00_couplers_to_auto_pc_AWID;
|
||||
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
|
||||
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
|
||||
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
|
||||
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
|
||||
wire s00_couplers_to_auto_pc_AWREADY;
|
||||
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
|
||||
wire s00_couplers_to_auto_pc_AWVALID;
|
||||
wire [11:0]s00_couplers_to_auto_pc_BID;
|
||||
wire s00_couplers_to_auto_pc_BREADY;
|
||||
wire [1:0]s00_couplers_to_auto_pc_BRESP;
|
||||
wire s00_couplers_to_auto_pc_BVALID;
|
||||
wire [31:0]s00_couplers_to_auto_pc_RDATA;
|
||||
wire [11:0]s00_couplers_to_auto_pc_RID;
|
||||
wire s00_couplers_to_auto_pc_RLAST;
|
||||
wire s00_couplers_to_auto_pc_RREADY;
|
||||
wire [1:0]s00_couplers_to_auto_pc_RRESP;
|
||||
wire s00_couplers_to_auto_pc_RVALID;
|
||||
wire [31:0]s00_couplers_to_auto_pc_WDATA;
|
||||
wire [11:0]s00_couplers_to_auto_pc_WID;
|
||||
wire s00_couplers_to_auto_pc_WLAST;
|
||||
wire s00_couplers_to_auto_pc_WREADY;
|
||||
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
|
||||
wire s00_couplers_to_auto_pc_WVALID;
|
||||
|
||||
assign M_AXI_araddr[31:0] = auto_pc_to_s00_couplers_ARADDR;
|
||||
assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT;
|
||||
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
|
||||
assign M_AXI_awaddr[31:0] = auto_pc_to_s00_couplers_AWADDR;
|
||||
assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT;
|
||||
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
|
||||
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
|
||||
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
|
||||
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
|
||||
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
|
||||
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
|
||||
assign S_ACLK_1 = S_ACLK;
|
||||
assign S_ARESETN_1 = S_ARESETN;
|
||||
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
|
||||
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
|
||||
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
|
||||
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
|
||||
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
|
||||
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
|
||||
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
|
||||
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
|
||||
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
|
||||
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
|
||||
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
|
||||
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
|
||||
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
|
||||
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
|
||||
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
|
||||
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
|
||||
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
|
||||
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
|
||||
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
|
||||
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
|
||||
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
|
||||
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
|
||||
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
|
||||
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
|
||||
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
|
||||
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
|
||||
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
|
||||
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
|
||||
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
|
||||
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
|
||||
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
|
||||
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
|
||||
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
|
||||
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
|
||||
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
|
||||
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
|
||||
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
|
||||
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
|
||||
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
|
||||
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
|
||||
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
|
||||
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
|
||||
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
|
||||
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
|
||||
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
|
||||
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
|
||||
system_auto_pc_0 auto_pc
|
||||
(.aclk(S_ACLK_1),
|
||||
.aresetn(S_ARESETN_1),
|
||||
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
|
||||
.m_axi_arprot(auto_pc_to_s00_couplers_ARPROT),
|
||||
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
|
||||
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
|
||||
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
|
||||
.m_axi_awprot(auto_pc_to_s00_couplers_AWPROT),
|
||||
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
|
||||
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
|
||||
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
|
||||
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
|
||||
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
|
||||
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
|
||||
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
|
||||
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
|
||||
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
|
||||
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
|
||||
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
|
||||
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
|
||||
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
|
||||
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
|
||||
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
|
||||
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
|
||||
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
|
||||
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
|
||||
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
|
||||
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
|
||||
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
|
||||
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
|
||||
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
|
||||
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
|
||||
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
|
||||
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
|
||||
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
|
||||
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
|
||||
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
|
||||
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
|
||||
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
|
||||
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
|
||||
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
|
||||
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
|
||||
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
|
||||
.s_axi_bid(s00_couplers_to_auto_pc_BID),
|
||||
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
|
||||
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
|
||||
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
|
||||
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
|
||||
.s_axi_rid(s00_couplers_to_auto_pc_RID),
|
||||
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
|
||||
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
|
||||
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
|
||||
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
|
||||
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
|
||||
.s_axi_wid(s00_couplers_to_auto_pc_WID),
|
||||
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
|
||||
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
|
||||
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
|
||||
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
|
||||
endmodule
|
||||
|
||||
(* CORE_GENERATION_INFO = "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=7,numReposBlks=5,numNonXlnxBlks=0,numHierBlks=2,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=2,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=2,da_clkrst_cnt=2,da_ps7_cnt=1,synth_mode=None}" *) (* HW_HANDOFF = "system.hwdef" *)
|
||||
module system
|
||||
(DDR_addr,
|
||||
DDR_ba,
|
||||
DDR_cas_n,
|
||||
DDR_ck_n,
|
||||
DDR_ck_p,
|
||||
DDR_cke,
|
||||
DDR_cs_n,
|
||||
DDR_dm,
|
||||
DDR_dq,
|
||||
DDR_dqs_n,
|
||||
DDR_dqs_p,
|
||||
DDR_odt,
|
||||
DDR_ras_n,
|
||||
DDR_reset_n,
|
||||
DDR_we_n,
|
||||
EMIO_0_tri_i,
|
||||
EMIO_0_tri_o,
|
||||
EMIO_0_tri_t,
|
||||
FIXED_IO_ddr_vrn,
|
||||
FIXED_IO_ddr_vrp,
|
||||
FIXED_IO_mio,
|
||||
FIXED_IO_ps_clk,
|
||||
FIXED_IO_ps_porb,
|
||||
FIXED_IO_ps_srstb);
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) inout [14:0]DDR_addr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_ba;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_cas_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_ck_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_ck_p;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_cke;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_cs_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_dm;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_dq;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_dqs_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_dqs_p;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_odt;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_ras_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_reset_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_we_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 EMIO_0 TRI_I" *) input [32:0]EMIO_0_tri_i;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 EMIO_0 TRI_O" *) output [32:0]EMIO_0_tri_o;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 EMIO_0 TRI_T" *) output [32:0]EMIO_0_tri_t;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout FIXED_IO_ddr_vrn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout FIXED_IO_ddr_vrp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]FIXED_IO_mio;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout FIXED_IO_ps_clk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout FIXED_IO_ps_porb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout FIXED_IO_ps_srstb;
|
||||
|
||||
wire [56:0]dna_port_read_0_dna_port;
|
||||
wire dna_port_read_0_read_vld;
|
||||
wire mydna_read_v1_0_0_start_vld;
|
||||
wire [14:0]processing_system7_0_DDR_ADDR;
|
||||
wire [2:0]processing_system7_0_DDR_BA;
|
||||
wire processing_system7_0_DDR_CAS_N;
|
||||
wire processing_system7_0_DDR_CKE;
|
||||
wire processing_system7_0_DDR_CK_N;
|
||||
wire processing_system7_0_DDR_CK_P;
|
||||
wire processing_system7_0_DDR_CS_N;
|
||||
wire [3:0]processing_system7_0_DDR_DM;
|
||||
wire [31:0]processing_system7_0_DDR_DQ;
|
||||
wire [3:0]processing_system7_0_DDR_DQS_N;
|
||||
wire [3:0]processing_system7_0_DDR_DQS_P;
|
||||
wire processing_system7_0_DDR_ODT;
|
||||
wire processing_system7_0_DDR_RAS_N;
|
||||
wire processing_system7_0_DDR_RESET_N;
|
||||
wire processing_system7_0_DDR_WE_N;
|
||||
wire processing_system7_0_FCLK_CLK0;
|
||||
wire processing_system7_0_FCLK_RESET0_N;
|
||||
wire processing_system7_0_FIXED_IO_DDR_VRN;
|
||||
wire processing_system7_0_FIXED_IO_DDR_VRP;
|
||||
wire [53:0]processing_system7_0_FIXED_IO_MIO;
|
||||
wire processing_system7_0_FIXED_IO_PS_CLK;
|
||||
wire processing_system7_0_FIXED_IO_PS_PORB;
|
||||
wire processing_system7_0_FIXED_IO_PS_SRSTB;
|
||||
wire [32:0]processing_system7_0_GPIO_0_TRI_I;
|
||||
wire [32:0]processing_system7_0_GPIO_0_TRI_O;
|
||||
wire [32:0]processing_system7_0_GPIO_0_TRI_T;
|
||||
wire [31:0]processing_system7_0_M_AXI_GP0_ARADDR;
|
||||
wire [1:0]processing_system7_0_M_AXI_GP0_ARBURST;
|
||||
wire [3:0]processing_system7_0_M_AXI_GP0_ARCACHE;
|
||||
wire [11:0]processing_system7_0_M_AXI_GP0_ARID;
|
||||
wire [3:0]processing_system7_0_M_AXI_GP0_ARLEN;
|
||||
wire [1:0]processing_system7_0_M_AXI_GP0_ARLOCK;
|
||||
wire [2:0]processing_system7_0_M_AXI_GP0_ARPROT;
|
||||
wire [3:0]processing_system7_0_M_AXI_GP0_ARQOS;
|
||||
wire processing_system7_0_M_AXI_GP0_ARREADY;
|
||||
wire [2:0]processing_system7_0_M_AXI_GP0_ARSIZE;
|
||||
wire processing_system7_0_M_AXI_GP0_ARVALID;
|
||||
wire [31:0]processing_system7_0_M_AXI_GP0_AWADDR;
|
||||
wire [1:0]processing_system7_0_M_AXI_GP0_AWBURST;
|
||||
wire [3:0]processing_system7_0_M_AXI_GP0_AWCACHE;
|
||||
wire [11:0]processing_system7_0_M_AXI_GP0_AWID;
|
||||
wire [3:0]processing_system7_0_M_AXI_GP0_AWLEN;
|
||||
wire [1:0]processing_system7_0_M_AXI_GP0_AWLOCK;
|
||||
wire [2:0]processing_system7_0_M_AXI_GP0_AWPROT;
|
||||
wire [3:0]processing_system7_0_M_AXI_GP0_AWQOS;
|
||||
wire processing_system7_0_M_AXI_GP0_AWREADY;
|
||||
wire [2:0]processing_system7_0_M_AXI_GP0_AWSIZE;
|
||||
wire processing_system7_0_M_AXI_GP0_AWVALID;
|
||||
wire [11:0]processing_system7_0_M_AXI_GP0_BID;
|
||||
wire processing_system7_0_M_AXI_GP0_BREADY;
|
||||
wire [1:0]processing_system7_0_M_AXI_GP0_BRESP;
|
||||
wire processing_system7_0_M_AXI_GP0_BVALID;
|
||||
wire [31:0]processing_system7_0_M_AXI_GP0_RDATA;
|
||||
wire [11:0]processing_system7_0_M_AXI_GP0_RID;
|
||||
wire processing_system7_0_M_AXI_GP0_RLAST;
|
||||
wire processing_system7_0_M_AXI_GP0_RREADY;
|
||||
wire [1:0]processing_system7_0_M_AXI_GP0_RRESP;
|
||||
wire processing_system7_0_M_AXI_GP0_RVALID;
|
||||
wire [31:0]processing_system7_0_M_AXI_GP0_WDATA;
|
||||
wire [11:0]processing_system7_0_M_AXI_GP0_WID;
|
||||
wire processing_system7_0_M_AXI_GP0_WLAST;
|
||||
wire processing_system7_0_M_AXI_GP0_WREADY;
|
||||
wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB;
|
||||
wire processing_system7_0_M_AXI_GP0_WVALID;
|
||||
wire [31:0]ps7_0_axi_periph_M00_AXI_ARADDR;
|
||||
wire [2:0]ps7_0_axi_periph_M00_AXI_ARPROT;
|
||||
wire ps7_0_axi_periph_M00_AXI_ARREADY;
|
||||
wire ps7_0_axi_periph_M00_AXI_ARVALID;
|
||||
wire [31:0]ps7_0_axi_periph_M00_AXI_AWADDR;
|
||||
wire [2:0]ps7_0_axi_periph_M00_AXI_AWPROT;
|
||||
wire ps7_0_axi_periph_M00_AXI_AWREADY;
|
||||
wire ps7_0_axi_periph_M00_AXI_AWVALID;
|
||||
wire ps7_0_axi_periph_M00_AXI_BREADY;
|
||||
wire [1:0]ps7_0_axi_periph_M00_AXI_BRESP;
|
||||
wire ps7_0_axi_periph_M00_AXI_BVALID;
|
||||
wire [31:0]ps7_0_axi_periph_M00_AXI_RDATA;
|
||||
wire ps7_0_axi_periph_M00_AXI_RREADY;
|
||||
wire [1:0]ps7_0_axi_periph_M00_AXI_RRESP;
|
||||
wire ps7_0_axi_periph_M00_AXI_RVALID;
|
||||
wire [31:0]ps7_0_axi_periph_M00_AXI_WDATA;
|
||||
wire ps7_0_axi_periph_M00_AXI_WREADY;
|
||||
wire [3:0]ps7_0_axi_periph_M00_AXI_WSTRB;
|
||||
wire ps7_0_axi_periph_M00_AXI_WVALID;
|
||||
wire [0:0]rst_ps7_0_100M_interconnect_aresetn;
|
||||
wire [0:0]rst_ps7_0_100M_peripheral_aresetn;
|
||||
|
||||
assign EMIO_0_tri_o[32:0] = processing_system7_0_GPIO_0_TRI_O;
|
||||
assign EMIO_0_tri_t[32:0] = processing_system7_0_GPIO_0_TRI_T;
|
||||
assign processing_system7_0_GPIO_0_TRI_I = EMIO_0_tri_i[32:0];
|
||||
system_dna_port_read_0_0 dna_port_read_0
|
||||
(.clk(processing_system7_0_FCLK_CLK0),
|
||||
.dna_port(dna_port_read_0_dna_port),
|
||||
.read_vld(dna_port_read_0_read_vld),
|
||||
.rst_n(rst_ps7_0_100M_peripheral_aresetn),
|
||||
.start_vld(mydna_read_v1_0_0_start_vld));
|
||||
system_mydna_read_v1_0_0_0 mydna_read_v1_0_0
|
||||
(.dna_port(dna_port_read_0_dna_port),
|
||||
.read_vld(dna_port_read_0_read_vld),
|
||||
.s00_axi_aclk(processing_system7_0_FCLK_CLK0),
|
||||
.s00_axi_araddr(ps7_0_axi_periph_M00_AXI_ARADDR[3:0]),
|
||||
.s00_axi_aresetn(rst_ps7_0_100M_peripheral_aresetn),
|
||||
.s00_axi_arprot(ps7_0_axi_periph_M00_AXI_ARPROT),
|
||||
.s00_axi_arready(ps7_0_axi_periph_M00_AXI_ARREADY),
|
||||
.s00_axi_arvalid(ps7_0_axi_periph_M00_AXI_ARVALID),
|
||||
.s00_axi_awaddr(ps7_0_axi_periph_M00_AXI_AWADDR[3:0]),
|
||||
.s00_axi_awprot(ps7_0_axi_periph_M00_AXI_AWPROT),
|
||||
.s00_axi_awready(ps7_0_axi_periph_M00_AXI_AWREADY),
|
||||
.s00_axi_awvalid(ps7_0_axi_periph_M00_AXI_AWVALID),
|
||||
.s00_axi_bready(ps7_0_axi_periph_M00_AXI_BREADY),
|
||||
.s00_axi_bresp(ps7_0_axi_periph_M00_AXI_BRESP),
|
||||
.s00_axi_bvalid(ps7_0_axi_periph_M00_AXI_BVALID),
|
||||
.s00_axi_rdata(ps7_0_axi_periph_M00_AXI_RDATA),
|
||||
.s00_axi_rready(ps7_0_axi_periph_M00_AXI_RREADY),
|
||||
.s00_axi_rresp(ps7_0_axi_periph_M00_AXI_RRESP),
|
||||
.s00_axi_rvalid(ps7_0_axi_periph_M00_AXI_RVALID),
|
||||
.s00_axi_wdata(ps7_0_axi_periph_M00_AXI_WDATA),
|
||||
.s00_axi_wready(ps7_0_axi_periph_M00_AXI_WREADY),
|
||||
.s00_axi_wstrb(ps7_0_axi_periph_M00_AXI_WSTRB),
|
||||
.s00_axi_wvalid(ps7_0_axi_periph_M00_AXI_WVALID),
|
||||
.start_vld(mydna_read_v1_0_0_start_vld));
|
||||
system_processing_system7_0_0 processing_system7_0
|
||||
(.DDR_Addr(DDR_addr[14:0]),
|
||||
.DDR_BankAddr(DDR_ba[2:0]),
|
||||
.DDR_CAS_n(DDR_cas_n),
|
||||
.DDR_CKE(DDR_cke),
|
||||
.DDR_CS_n(DDR_cs_n),
|
||||
.DDR_Clk(DDR_ck_p),
|
||||
.DDR_Clk_n(DDR_ck_n),
|
||||
.DDR_DM(DDR_dm[3:0]),
|
||||
.DDR_DQ(DDR_dq[31:0]),
|
||||
.DDR_DQS(DDR_dqs_p[3:0]),
|
||||
.DDR_DQS_n(DDR_dqs_n[3:0]),
|
||||
.DDR_DRSTB(DDR_reset_n),
|
||||
.DDR_ODT(DDR_odt),
|
||||
.DDR_RAS_n(DDR_ras_n),
|
||||
.DDR_VRN(FIXED_IO_ddr_vrn),
|
||||
.DDR_VRP(FIXED_IO_ddr_vrp),
|
||||
.DDR_WEB(DDR_we_n),
|
||||
.FCLK_CLK0(processing_system7_0_FCLK_CLK0),
|
||||
.FCLK_RESET0_N(processing_system7_0_FCLK_RESET0_N),
|
||||
.GPIO_I(processing_system7_0_GPIO_0_TRI_I),
|
||||
.GPIO_O(processing_system7_0_GPIO_0_TRI_O),
|
||||
.GPIO_T(processing_system7_0_GPIO_0_TRI_T),
|
||||
.MIO(FIXED_IO_mio[53:0]),
|
||||
.M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0),
|
||||
.M_AXI_GP0_ARADDR(processing_system7_0_M_AXI_GP0_ARADDR),
|
||||
.M_AXI_GP0_ARBURST(processing_system7_0_M_AXI_GP0_ARBURST),
|
||||
.M_AXI_GP0_ARCACHE(processing_system7_0_M_AXI_GP0_ARCACHE),
|
||||
.M_AXI_GP0_ARID(processing_system7_0_M_AXI_GP0_ARID),
|
||||
.M_AXI_GP0_ARLEN(processing_system7_0_M_AXI_GP0_ARLEN),
|
||||
.M_AXI_GP0_ARLOCK(processing_system7_0_M_AXI_GP0_ARLOCK),
|
||||
.M_AXI_GP0_ARPROT(processing_system7_0_M_AXI_GP0_ARPROT),
|
||||
.M_AXI_GP0_ARQOS(processing_system7_0_M_AXI_GP0_ARQOS),
|
||||
.M_AXI_GP0_ARREADY(processing_system7_0_M_AXI_GP0_ARREADY),
|
||||
.M_AXI_GP0_ARSIZE(processing_system7_0_M_AXI_GP0_ARSIZE),
|
||||
.M_AXI_GP0_ARVALID(processing_system7_0_M_AXI_GP0_ARVALID),
|
||||
.M_AXI_GP0_AWADDR(processing_system7_0_M_AXI_GP0_AWADDR),
|
||||
.M_AXI_GP0_AWBURST(processing_system7_0_M_AXI_GP0_AWBURST),
|
||||
.M_AXI_GP0_AWCACHE(processing_system7_0_M_AXI_GP0_AWCACHE),
|
||||
.M_AXI_GP0_AWID(processing_system7_0_M_AXI_GP0_AWID),
|
||||
.M_AXI_GP0_AWLEN(processing_system7_0_M_AXI_GP0_AWLEN),
|
||||
.M_AXI_GP0_AWLOCK(processing_system7_0_M_AXI_GP0_AWLOCK),
|
||||
.M_AXI_GP0_AWPROT(processing_system7_0_M_AXI_GP0_AWPROT),
|
||||
.M_AXI_GP0_AWQOS(processing_system7_0_M_AXI_GP0_AWQOS),
|
||||
.M_AXI_GP0_AWREADY(processing_system7_0_M_AXI_GP0_AWREADY),
|
||||
.M_AXI_GP0_AWSIZE(processing_system7_0_M_AXI_GP0_AWSIZE),
|
||||
.M_AXI_GP0_AWVALID(processing_system7_0_M_AXI_GP0_AWVALID),
|
||||
.M_AXI_GP0_BID(processing_system7_0_M_AXI_GP0_BID),
|
||||
.M_AXI_GP0_BREADY(processing_system7_0_M_AXI_GP0_BREADY),
|
||||
.M_AXI_GP0_BRESP(processing_system7_0_M_AXI_GP0_BRESP),
|
||||
.M_AXI_GP0_BVALID(processing_system7_0_M_AXI_GP0_BVALID),
|
||||
.M_AXI_GP0_RDATA(processing_system7_0_M_AXI_GP0_RDATA),
|
||||
.M_AXI_GP0_RID(processing_system7_0_M_AXI_GP0_RID),
|
||||
.M_AXI_GP0_RLAST(processing_system7_0_M_AXI_GP0_RLAST),
|
||||
.M_AXI_GP0_RREADY(processing_system7_0_M_AXI_GP0_RREADY),
|
||||
.M_AXI_GP0_RRESP(processing_system7_0_M_AXI_GP0_RRESP),
|
||||
.M_AXI_GP0_RVALID(processing_system7_0_M_AXI_GP0_RVALID),
|
||||
.M_AXI_GP0_WDATA(processing_system7_0_M_AXI_GP0_WDATA),
|
||||
.M_AXI_GP0_WID(processing_system7_0_M_AXI_GP0_WID),
|
||||
.M_AXI_GP0_WLAST(processing_system7_0_M_AXI_GP0_WLAST),
|
||||
.M_AXI_GP0_WREADY(processing_system7_0_M_AXI_GP0_WREADY),
|
||||
.M_AXI_GP0_WSTRB(processing_system7_0_M_AXI_GP0_WSTRB),
|
||||
.M_AXI_GP0_WVALID(processing_system7_0_M_AXI_GP0_WVALID),
|
||||
.PS_CLK(FIXED_IO_ps_clk),
|
||||
.PS_PORB(FIXED_IO_ps_porb),
|
||||
.PS_SRSTB(FIXED_IO_ps_srstb));
|
||||
system_ps7_0_axi_periph_1 ps7_0_axi_periph
|
||||
(.ACLK(processing_system7_0_FCLK_CLK0),
|
||||
.ARESETN(rst_ps7_0_100M_interconnect_aresetn),
|
||||
.M00_ACLK(processing_system7_0_FCLK_CLK0),
|
||||
.M00_ARESETN(rst_ps7_0_100M_peripheral_aresetn),
|
||||
.M00_AXI_araddr(ps7_0_axi_periph_M00_AXI_ARADDR),
|
||||
.M00_AXI_arprot(ps7_0_axi_periph_M00_AXI_ARPROT),
|
||||
.M00_AXI_arready(ps7_0_axi_periph_M00_AXI_ARREADY),
|
||||
.M00_AXI_arvalid(ps7_0_axi_periph_M00_AXI_ARVALID),
|
||||
.M00_AXI_awaddr(ps7_0_axi_periph_M00_AXI_AWADDR),
|
||||
.M00_AXI_awprot(ps7_0_axi_periph_M00_AXI_AWPROT),
|
||||
.M00_AXI_awready(ps7_0_axi_periph_M00_AXI_AWREADY),
|
||||
.M00_AXI_awvalid(ps7_0_axi_periph_M00_AXI_AWVALID),
|
||||
.M00_AXI_bready(ps7_0_axi_periph_M00_AXI_BREADY),
|
||||
.M00_AXI_bresp(ps7_0_axi_periph_M00_AXI_BRESP),
|
||||
.M00_AXI_bvalid(ps7_0_axi_periph_M00_AXI_BVALID),
|
||||
.M00_AXI_rdata(ps7_0_axi_periph_M00_AXI_RDATA),
|
||||
.M00_AXI_rready(ps7_0_axi_periph_M00_AXI_RREADY),
|
||||
.M00_AXI_rresp(ps7_0_axi_periph_M00_AXI_RRESP),
|
||||
.M00_AXI_rvalid(ps7_0_axi_periph_M00_AXI_RVALID),
|
||||
.M00_AXI_wdata(ps7_0_axi_periph_M00_AXI_WDATA),
|
||||
.M00_AXI_wready(ps7_0_axi_periph_M00_AXI_WREADY),
|
||||
.M00_AXI_wstrb(ps7_0_axi_periph_M00_AXI_WSTRB),
|
||||
.M00_AXI_wvalid(ps7_0_axi_periph_M00_AXI_WVALID),
|
||||
.S00_ACLK(processing_system7_0_FCLK_CLK0),
|
||||
.S00_ARESETN(rst_ps7_0_100M_peripheral_aresetn),
|
||||
.S00_AXI_araddr(processing_system7_0_M_AXI_GP0_ARADDR),
|
||||
.S00_AXI_arburst(processing_system7_0_M_AXI_GP0_ARBURST),
|
||||
.S00_AXI_arcache(processing_system7_0_M_AXI_GP0_ARCACHE),
|
||||
.S00_AXI_arid(processing_system7_0_M_AXI_GP0_ARID),
|
||||
.S00_AXI_arlen(processing_system7_0_M_AXI_GP0_ARLEN),
|
||||
.S00_AXI_arlock(processing_system7_0_M_AXI_GP0_ARLOCK),
|
||||
.S00_AXI_arprot(processing_system7_0_M_AXI_GP0_ARPROT),
|
||||
.S00_AXI_arqos(processing_system7_0_M_AXI_GP0_ARQOS),
|
||||
.S00_AXI_arready(processing_system7_0_M_AXI_GP0_ARREADY),
|
||||
.S00_AXI_arsize(processing_system7_0_M_AXI_GP0_ARSIZE),
|
||||
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP0_ARVALID),
|
||||
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP0_AWADDR),
|
||||
.S00_AXI_awburst(processing_system7_0_M_AXI_GP0_AWBURST),
|
||||
.S00_AXI_awcache(processing_system7_0_M_AXI_GP0_AWCACHE),
|
||||
.S00_AXI_awid(processing_system7_0_M_AXI_GP0_AWID),
|
||||
.S00_AXI_awlen(processing_system7_0_M_AXI_GP0_AWLEN),
|
||||
.S00_AXI_awlock(processing_system7_0_M_AXI_GP0_AWLOCK),
|
||||
.S00_AXI_awprot(processing_system7_0_M_AXI_GP0_AWPROT),
|
||||
.S00_AXI_awqos(processing_system7_0_M_AXI_GP0_AWQOS),
|
||||
.S00_AXI_awready(processing_system7_0_M_AXI_GP0_AWREADY),
|
||||
.S00_AXI_awsize(processing_system7_0_M_AXI_GP0_AWSIZE),
|
||||
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP0_AWVALID),
|
||||
.S00_AXI_bid(processing_system7_0_M_AXI_GP0_BID),
|
||||
.S00_AXI_bready(processing_system7_0_M_AXI_GP0_BREADY),
|
||||
.S00_AXI_bresp(processing_system7_0_M_AXI_GP0_BRESP),
|
||||
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP0_BVALID),
|
||||
.S00_AXI_rdata(processing_system7_0_M_AXI_GP0_RDATA),
|
||||
.S00_AXI_rid(processing_system7_0_M_AXI_GP0_RID),
|
||||
.S00_AXI_rlast(processing_system7_0_M_AXI_GP0_RLAST),
|
||||
.S00_AXI_rready(processing_system7_0_M_AXI_GP0_RREADY),
|
||||
.S00_AXI_rresp(processing_system7_0_M_AXI_GP0_RRESP),
|
||||
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP0_RVALID),
|
||||
.S00_AXI_wdata(processing_system7_0_M_AXI_GP0_WDATA),
|
||||
.S00_AXI_wid(processing_system7_0_M_AXI_GP0_WID),
|
||||
.S00_AXI_wlast(processing_system7_0_M_AXI_GP0_WLAST),
|
||||
.S00_AXI_wready(processing_system7_0_M_AXI_GP0_WREADY),
|
||||
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP0_WSTRB),
|
||||
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP0_WVALID));
|
||||
system_rst_ps7_0_100M_1 rst_ps7_0_100M
|
||||
(.aux_reset_in(1'b1),
|
||||
.dcm_locked(1'b1),
|
||||
.ext_reset_in(processing_system7_0_FCLK_RESET0_N),
|
||||
.interconnect_aresetn(rst_ps7_0_100M_interconnect_aresetn),
|
||||
.mb_debug_sys_rst(1'b0),
|
||||
.peripheral_aresetn(rst_ps7_0_100M_peripheral_aresetn),
|
||||
.slowest_sync_clk(processing_system7_0_FCLK_CLK0));
|
||||
endmodule
|
||||
|
||||
module system_ps7_0_axi_periph_1
|
||||
(ACLK,
|
||||
ARESETN,
|
||||
M00_ACLK,
|
||||
M00_ARESETN,
|
||||
M00_AXI_araddr,
|
||||
M00_AXI_arprot,
|
||||
M00_AXI_arready,
|
||||
M00_AXI_arvalid,
|
||||
M00_AXI_awaddr,
|
||||
M00_AXI_awprot,
|
||||
M00_AXI_awready,
|
||||
M00_AXI_awvalid,
|
||||
M00_AXI_bready,
|
||||
M00_AXI_bresp,
|
||||
M00_AXI_bvalid,
|
||||
M00_AXI_rdata,
|
||||
M00_AXI_rready,
|
||||
M00_AXI_rresp,
|
||||
M00_AXI_rvalid,
|
||||
M00_AXI_wdata,
|
||||
M00_AXI_wready,
|
||||
M00_AXI_wstrb,
|
||||
M00_AXI_wvalid,
|
||||
S00_ACLK,
|
||||
S00_ARESETN,
|
||||
S00_AXI_araddr,
|
||||
S00_AXI_arburst,
|
||||
S00_AXI_arcache,
|
||||
S00_AXI_arid,
|
||||
S00_AXI_arlen,
|
||||
S00_AXI_arlock,
|
||||
S00_AXI_arprot,
|
||||
S00_AXI_arqos,
|
||||
S00_AXI_arready,
|
||||
S00_AXI_arsize,
|
||||
S00_AXI_arvalid,
|
||||
S00_AXI_awaddr,
|
||||
S00_AXI_awburst,
|
||||
S00_AXI_awcache,
|
||||
S00_AXI_awid,
|
||||
S00_AXI_awlen,
|
||||
S00_AXI_awlock,
|
||||
S00_AXI_awprot,
|
||||
S00_AXI_awqos,
|
||||
S00_AXI_awready,
|
||||
S00_AXI_awsize,
|
||||
S00_AXI_awvalid,
|
||||
S00_AXI_bid,
|
||||
S00_AXI_bready,
|
||||
S00_AXI_bresp,
|
||||
S00_AXI_bvalid,
|
||||
S00_AXI_rdata,
|
||||
S00_AXI_rid,
|
||||
S00_AXI_rlast,
|
||||
S00_AXI_rready,
|
||||
S00_AXI_rresp,
|
||||
S00_AXI_rvalid,
|
||||
S00_AXI_wdata,
|
||||
S00_AXI_wid,
|
||||
S00_AXI_wlast,
|
||||
S00_AXI_wready,
|
||||
S00_AXI_wstrb,
|
||||
S00_AXI_wvalid);
|
||||
input ACLK;
|
||||
input ARESETN;
|
||||
input M00_ACLK;
|
||||
input M00_ARESETN;
|
||||
output [31:0]M00_AXI_araddr;
|
||||
output [2:0]M00_AXI_arprot;
|
||||
input M00_AXI_arready;
|
||||
output M00_AXI_arvalid;
|
||||
output [31:0]M00_AXI_awaddr;
|
||||
output [2:0]M00_AXI_awprot;
|
||||
input M00_AXI_awready;
|
||||
output M00_AXI_awvalid;
|
||||
output M00_AXI_bready;
|
||||
input [1:0]M00_AXI_bresp;
|
||||
input M00_AXI_bvalid;
|
||||
input [31:0]M00_AXI_rdata;
|
||||
output M00_AXI_rready;
|
||||
input [1:0]M00_AXI_rresp;
|
||||
input M00_AXI_rvalid;
|
||||
output [31:0]M00_AXI_wdata;
|
||||
input M00_AXI_wready;
|
||||
output [3:0]M00_AXI_wstrb;
|
||||
output M00_AXI_wvalid;
|
||||
input S00_ACLK;
|
||||
input S00_ARESETN;
|
||||
input [31:0]S00_AXI_araddr;
|
||||
input [1:0]S00_AXI_arburst;
|
||||
input [3:0]S00_AXI_arcache;
|
||||
input [11:0]S00_AXI_arid;
|
||||
input [3:0]S00_AXI_arlen;
|
||||
input [1:0]S00_AXI_arlock;
|
||||
input [2:0]S00_AXI_arprot;
|
||||
input [3:0]S00_AXI_arqos;
|
||||
output S00_AXI_arready;
|
||||
input [2:0]S00_AXI_arsize;
|
||||
input S00_AXI_arvalid;
|
||||
input [31:0]S00_AXI_awaddr;
|
||||
input [1:0]S00_AXI_awburst;
|
||||
input [3:0]S00_AXI_awcache;
|
||||
input [11:0]S00_AXI_awid;
|
||||
input [3:0]S00_AXI_awlen;
|
||||
input [1:0]S00_AXI_awlock;
|
||||
input [2:0]S00_AXI_awprot;
|
||||
input [3:0]S00_AXI_awqos;
|
||||
output S00_AXI_awready;
|
||||
input [2:0]S00_AXI_awsize;
|
||||
input S00_AXI_awvalid;
|
||||
output [11:0]S00_AXI_bid;
|
||||
input S00_AXI_bready;
|
||||
output [1:0]S00_AXI_bresp;
|
||||
output S00_AXI_bvalid;
|
||||
output [31:0]S00_AXI_rdata;
|
||||
output [11:0]S00_AXI_rid;
|
||||
output S00_AXI_rlast;
|
||||
input S00_AXI_rready;
|
||||
output [1:0]S00_AXI_rresp;
|
||||
output S00_AXI_rvalid;
|
||||
input [31:0]S00_AXI_wdata;
|
||||
input [11:0]S00_AXI_wid;
|
||||
input S00_AXI_wlast;
|
||||
output S00_AXI_wready;
|
||||
input [3:0]S00_AXI_wstrb;
|
||||
input S00_AXI_wvalid;
|
||||
|
||||
wire S00_ACLK_1;
|
||||
wire S00_ARESETN_1;
|
||||
wire ps7_0_axi_periph_ACLK_net;
|
||||
wire ps7_0_axi_periph_ARESETN_net;
|
||||
wire [31:0]ps7_0_axi_periph_to_s00_couplers_ARADDR;
|
||||
wire [1:0]ps7_0_axi_periph_to_s00_couplers_ARBURST;
|
||||
wire [3:0]ps7_0_axi_periph_to_s00_couplers_ARCACHE;
|
||||
wire [11:0]ps7_0_axi_periph_to_s00_couplers_ARID;
|
||||
wire [3:0]ps7_0_axi_periph_to_s00_couplers_ARLEN;
|
||||
wire [1:0]ps7_0_axi_periph_to_s00_couplers_ARLOCK;
|
||||
wire [2:0]ps7_0_axi_periph_to_s00_couplers_ARPROT;
|
||||
wire [3:0]ps7_0_axi_periph_to_s00_couplers_ARQOS;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_ARREADY;
|
||||
wire [2:0]ps7_0_axi_periph_to_s00_couplers_ARSIZE;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_ARVALID;
|
||||
wire [31:0]ps7_0_axi_periph_to_s00_couplers_AWADDR;
|
||||
wire [1:0]ps7_0_axi_periph_to_s00_couplers_AWBURST;
|
||||
wire [3:0]ps7_0_axi_periph_to_s00_couplers_AWCACHE;
|
||||
wire [11:0]ps7_0_axi_periph_to_s00_couplers_AWID;
|
||||
wire [3:0]ps7_0_axi_periph_to_s00_couplers_AWLEN;
|
||||
wire [1:0]ps7_0_axi_periph_to_s00_couplers_AWLOCK;
|
||||
wire [2:0]ps7_0_axi_periph_to_s00_couplers_AWPROT;
|
||||
wire [3:0]ps7_0_axi_periph_to_s00_couplers_AWQOS;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_AWREADY;
|
||||
wire [2:0]ps7_0_axi_periph_to_s00_couplers_AWSIZE;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_AWVALID;
|
||||
wire [11:0]ps7_0_axi_periph_to_s00_couplers_BID;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_BREADY;
|
||||
wire [1:0]ps7_0_axi_periph_to_s00_couplers_BRESP;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_BVALID;
|
||||
wire [31:0]ps7_0_axi_periph_to_s00_couplers_RDATA;
|
||||
wire [11:0]ps7_0_axi_periph_to_s00_couplers_RID;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_RLAST;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_RREADY;
|
||||
wire [1:0]ps7_0_axi_periph_to_s00_couplers_RRESP;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_RVALID;
|
||||
wire [31:0]ps7_0_axi_periph_to_s00_couplers_WDATA;
|
||||
wire [11:0]ps7_0_axi_periph_to_s00_couplers_WID;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_WLAST;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_WREADY;
|
||||
wire [3:0]ps7_0_axi_periph_to_s00_couplers_WSTRB;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_WVALID;
|
||||
wire [31:0]s00_couplers_to_ps7_0_axi_periph_ARADDR;
|
||||
wire [2:0]s00_couplers_to_ps7_0_axi_periph_ARPROT;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_ARREADY;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_ARVALID;
|
||||
wire [31:0]s00_couplers_to_ps7_0_axi_periph_AWADDR;
|
||||
wire [2:0]s00_couplers_to_ps7_0_axi_periph_AWPROT;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_AWREADY;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_AWVALID;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_BREADY;
|
||||
wire [1:0]s00_couplers_to_ps7_0_axi_periph_BRESP;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_BVALID;
|
||||
wire [31:0]s00_couplers_to_ps7_0_axi_periph_RDATA;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_RREADY;
|
||||
wire [1:0]s00_couplers_to_ps7_0_axi_periph_RRESP;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_RVALID;
|
||||
wire [31:0]s00_couplers_to_ps7_0_axi_periph_WDATA;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_WREADY;
|
||||
wire [3:0]s00_couplers_to_ps7_0_axi_periph_WSTRB;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_WVALID;
|
||||
|
||||
assign M00_AXI_araddr[31:0] = s00_couplers_to_ps7_0_axi_periph_ARADDR;
|
||||
assign M00_AXI_arprot[2:0] = s00_couplers_to_ps7_0_axi_periph_ARPROT;
|
||||
assign M00_AXI_arvalid = s00_couplers_to_ps7_0_axi_periph_ARVALID;
|
||||
assign M00_AXI_awaddr[31:0] = s00_couplers_to_ps7_0_axi_periph_AWADDR;
|
||||
assign M00_AXI_awprot[2:0] = s00_couplers_to_ps7_0_axi_periph_AWPROT;
|
||||
assign M00_AXI_awvalid = s00_couplers_to_ps7_0_axi_periph_AWVALID;
|
||||
assign M00_AXI_bready = s00_couplers_to_ps7_0_axi_periph_BREADY;
|
||||
assign M00_AXI_rready = s00_couplers_to_ps7_0_axi_periph_RREADY;
|
||||
assign M00_AXI_wdata[31:0] = s00_couplers_to_ps7_0_axi_periph_WDATA;
|
||||
assign M00_AXI_wstrb[3:0] = s00_couplers_to_ps7_0_axi_periph_WSTRB;
|
||||
assign M00_AXI_wvalid = s00_couplers_to_ps7_0_axi_periph_WVALID;
|
||||
assign S00_ACLK_1 = S00_ACLK;
|
||||
assign S00_ARESETN_1 = S00_ARESETN;
|
||||
assign S00_AXI_arready = ps7_0_axi_periph_to_s00_couplers_ARREADY;
|
||||
assign S00_AXI_awready = ps7_0_axi_periph_to_s00_couplers_AWREADY;
|
||||
assign S00_AXI_bid[11:0] = ps7_0_axi_periph_to_s00_couplers_BID;
|
||||
assign S00_AXI_bresp[1:0] = ps7_0_axi_periph_to_s00_couplers_BRESP;
|
||||
assign S00_AXI_bvalid = ps7_0_axi_periph_to_s00_couplers_BVALID;
|
||||
assign S00_AXI_rdata[31:0] = ps7_0_axi_periph_to_s00_couplers_RDATA;
|
||||
assign S00_AXI_rid[11:0] = ps7_0_axi_periph_to_s00_couplers_RID;
|
||||
assign S00_AXI_rlast = ps7_0_axi_periph_to_s00_couplers_RLAST;
|
||||
assign S00_AXI_rresp[1:0] = ps7_0_axi_periph_to_s00_couplers_RRESP;
|
||||
assign S00_AXI_rvalid = ps7_0_axi_periph_to_s00_couplers_RVALID;
|
||||
assign S00_AXI_wready = ps7_0_axi_periph_to_s00_couplers_WREADY;
|
||||
assign ps7_0_axi_periph_ACLK_net = M00_ACLK;
|
||||
assign ps7_0_axi_periph_ARESETN_net = M00_ARESETN;
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARID = S00_AXI_arid[11:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARVALID = S00_AXI_arvalid;
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWID = S00_AXI_awid[11:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWVALID = S00_AXI_awvalid;
|
||||
assign ps7_0_axi_periph_to_s00_couplers_BREADY = S00_AXI_bready;
|
||||
assign ps7_0_axi_periph_to_s00_couplers_RREADY = S00_AXI_rready;
|
||||
assign ps7_0_axi_periph_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_WID = S00_AXI_wid[11:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_WLAST = S00_AXI_wlast;
|
||||
assign ps7_0_axi_periph_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_WVALID = S00_AXI_wvalid;
|
||||
assign s00_couplers_to_ps7_0_axi_periph_ARREADY = M00_AXI_arready;
|
||||
assign s00_couplers_to_ps7_0_axi_periph_AWREADY = M00_AXI_awready;
|
||||
assign s00_couplers_to_ps7_0_axi_periph_BRESP = M00_AXI_bresp[1:0];
|
||||
assign s00_couplers_to_ps7_0_axi_periph_BVALID = M00_AXI_bvalid;
|
||||
assign s00_couplers_to_ps7_0_axi_periph_RDATA = M00_AXI_rdata[31:0];
|
||||
assign s00_couplers_to_ps7_0_axi_periph_RRESP = M00_AXI_rresp[1:0];
|
||||
assign s00_couplers_to_ps7_0_axi_periph_RVALID = M00_AXI_rvalid;
|
||||
assign s00_couplers_to_ps7_0_axi_periph_WREADY = M00_AXI_wready;
|
||||
s00_couplers_imp_11SE3QO s00_couplers
|
||||
(.M_ACLK(ps7_0_axi_periph_ACLK_net),
|
||||
.M_ARESETN(ps7_0_axi_periph_ARESETN_net),
|
||||
.M_AXI_araddr(s00_couplers_to_ps7_0_axi_periph_ARADDR),
|
||||
.M_AXI_arprot(s00_couplers_to_ps7_0_axi_periph_ARPROT),
|
||||
.M_AXI_arready(s00_couplers_to_ps7_0_axi_periph_ARREADY),
|
||||
.M_AXI_arvalid(s00_couplers_to_ps7_0_axi_periph_ARVALID),
|
||||
.M_AXI_awaddr(s00_couplers_to_ps7_0_axi_periph_AWADDR),
|
||||
.M_AXI_awprot(s00_couplers_to_ps7_0_axi_periph_AWPROT),
|
||||
.M_AXI_awready(s00_couplers_to_ps7_0_axi_periph_AWREADY),
|
||||
.M_AXI_awvalid(s00_couplers_to_ps7_0_axi_periph_AWVALID),
|
||||
.M_AXI_bready(s00_couplers_to_ps7_0_axi_periph_BREADY),
|
||||
.M_AXI_bresp(s00_couplers_to_ps7_0_axi_periph_BRESP),
|
||||
.M_AXI_bvalid(s00_couplers_to_ps7_0_axi_periph_BVALID),
|
||||
.M_AXI_rdata(s00_couplers_to_ps7_0_axi_periph_RDATA),
|
||||
.M_AXI_rready(s00_couplers_to_ps7_0_axi_periph_RREADY),
|
||||
.M_AXI_rresp(s00_couplers_to_ps7_0_axi_periph_RRESP),
|
||||
.M_AXI_rvalid(s00_couplers_to_ps7_0_axi_periph_RVALID),
|
||||
.M_AXI_wdata(s00_couplers_to_ps7_0_axi_periph_WDATA),
|
||||
.M_AXI_wready(s00_couplers_to_ps7_0_axi_periph_WREADY),
|
||||
.M_AXI_wstrb(s00_couplers_to_ps7_0_axi_periph_WSTRB),
|
||||
.M_AXI_wvalid(s00_couplers_to_ps7_0_axi_periph_WVALID),
|
||||
.S_ACLK(S00_ACLK_1),
|
||||
.S_ARESETN(S00_ARESETN_1),
|
||||
.S_AXI_araddr(ps7_0_axi_periph_to_s00_couplers_ARADDR),
|
||||
.S_AXI_arburst(ps7_0_axi_periph_to_s00_couplers_ARBURST),
|
||||
.S_AXI_arcache(ps7_0_axi_periph_to_s00_couplers_ARCACHE),
|
||||
.S_AXI_arid(ps7_0_axi_periph_to_s00_couplers_ARID),
|
||||
.S_AXI_arlen(ps7_0_axi_periph_to_s00_couplers_ARLEN),
|
||||
.S_AXI_arlock(ps7_0_axi_periph_to_s00_couplers_ARLOCK),
|
||||
.S_AXI_arprot(ps7_0_axi_periph_to_s00_couplers_ARPROT),
|
||||
.S_AXI_arqos(ps7_0_axi_periph_to_s00_couplers_ARQOS),
|
||||
.S_AXI_arready(ps7_0_axi_periph_to_s00_couplers_ARREADY),
|
||||
.S_AXI_arsize(ps7_0_axi_periph_to_s00_couplers_ARSIZE),
|
||||
.S_AXI_arvalid(ps7_0_axi_periph_to_s00_couplers_ARVALID),
|
||||
.S_AXI_awaddr(ps7_0_axi_periph_to_s00_couplers_AWADDR),
|
||||
.S_AXI_awburst(ps7_0_axi_periph_to_s00_couplers_AWBURST),
|
||||
.S_AXI_awcache(ps7_0_axi_periph_to_s00_couplers_AWCACHE),
|
||||
.S_AXI_awid(ps7_0_axi_periph_to_s00_couplers_AWID),
|
||||
.S_AXI_awlen(ps7_0_axi_periph_to_s00_couplers_AWLEN),
|
||||
.S_AXI_awlock(ps7_0_axi_periph_to_s00_couplers_AWLOCK),
|
||||
.S_AXI_awprot(ps7_0_axi_periph_to_s00_couplers_AWPROT),
|
||||
.S_AXI_awqos(ps7_0_axi_periph_to_s00_couplers_AWQOS),
|
||||
.S_AXI_awready(ps7_0_axi_periph_to_s00_couplers_AWREADY),
|
||||
.S_AXI_awsize(ps7_0_axi_periph_to_s00_couplers_AWSIZE),
|
||||
.S_AXI_awvalid(ps7_0_axi_periph_to_s00_couplers_AWVALID),
|
||||
.S_AXI_bid(ps7_0_axi_periph_to_s00_couplers_BID),
|
||||
.S_AXI_bready(ps7_0_axi_periph_to_s00_couplers_BREADY),
|
||||
.S_AXI_bresp(ps7_0_axi_periph_to_s00_couplers_BRESP),
|
||||
.S_AXI_bvalid(ps7_0_axi_periph_to_s00_couplers_BVALID),
|
||||
.S_AXI_rdata(ps7_0_axi_periph_to_s00_couplers_RDATA),
|
||||
.S_AXI_rid(ps7_0_axi_periph_to_s00_couplers_RID),
|
||||
.S_AXI_rlast(ps7_0_axi_periph_to_s00_couplers_RLAST),
|
||||
.S_AXI_rready(ps7_0_axi_periph_to_s00_couplers_RREADY),
|
||||
.S_AXI_rresp(ps7_0_axi_periph_to_s00_couplers_RRESP),
|
||||
.S_AXI_rvalid(ps7_0_axi_periph_to_s00_couplers_RVALID),
|
||||
.S_AXI_wdata(ps7_0_axi_periph_to_s00_couplers_WDATA),
|
||||
.S_AXI_wid(ps7_0_axi_periph_to_s00_couplers_WID),
|
||||
.S_AXI_wlast(ps7_0_axi_periph_to_s00_couplers_WLAST),
|
||||
.S_AXI_wready(ps7_0_axi_periph_to_s00_couplers_WREADY),
|
||||
.S_AXI_wstrb(ps7_0_axi_periph_to_s00_couplers_WSTRB),
|
||||
.S_AXI_wvalid(ps7_0_axi_periph_to_s00_couplers_WVALID));
|
||||
endmodule
|
||||
Binary file not shown.
@@ -0,0 +1,945 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
//Date : Mon May 25 14:51:47 2026
|
||||
//Host : mkb running 64-bit unknown
|
||||
//Command : generate_target system.bd
|
||||
//Design : system
|
||||
//Purpose : IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module s00_couplers_imp_11SE3QO
|
||||
(M_ACLK,
|
||||
M_ARESETN,
|
||||
M_AXI_araddr,
|
||||
M_AXI_arprot,
|
||||
M_AXI_arready,
|
||||
M_AXI_arvalid,
|
||||
M_AXI_awaddr,
|
||||
M_AXI_awprot,
|
||||
M_AXI_awready,
|
||||
M_AXI_awvalid,
|
||||
M_AXI_bready,
|
||||
M_AXI_bresp,
|
||||
M_AXI_bvalid,
|
||||
M_AXI_rdata,
|
||||
M_AXI_rready,
|
||||
M_AXI_rresp,
|
||||
M_AXI_rvalid,
|
||||
M_AXI_wdata,
|
||||
M_AXI_wready,
|
||||
M_AXI_wstrb,
|
||||
M_AXI_wvalid,
|
||||
S_ACLK,
|
||||
S_ARESETN,
|
||||
S_AXI_araddr,
|
||||
S_AXI_arburst,
|
||||
S_AXI_arcache,
|
||||
S_AXI_arid,
|
||||
S_AXI_arlen,
|
||||
S_AXI_arlock,
|
||||
S_AXI_arprot,
|
||||
S_AXI_arqos,
|
||||
S_AXI_arready,
|
||||
S_AXI_arsize,
|
||||
S_AXI_arvalid,
|
||||
S_AXI_awaddr,
|
||||
S_AXI_awburst,
|
||||
S_AXI_awcache,
|
||||
S_AXI_awid,
|
||||
S_AXI_awlen,
|
||||
S_AXI_awlock,
|
||||
S_AXI_awprot,
|
||||
S_AXI_awqos,
|
||||
S_AXI_awready,
|
||||
S_AXI_awsize,
|
||||
S_AXI_awvalid,
|
||||
S_AXI_bid,
|
||||
S_AXI_bready,
|
||||
S_AXI_bresp,
|
||||
S_AXI_bvalid,
|
||||
S_AXI_rdata,
|
||||
S_AXI_rid,
|
||||
S_AXI_rlast,
|
||||
S_AXI_rready,
|
||||
S_AXI_rresp,
|
||||
S_AXI_rvalid,
|
||||
S_AXI_wdata,
|
||||
S_AXI_wid,
|
||||
S_AXI_wlast,
|
||||
S_AXI_wready,
|
||||
S_AXI_wstrb,
|
||||
S_AXI_wvalid);
|
||||
input M_ACLK;
|
||||
input M_ARESETN;
|
||||
output [31:0]M_AXI_araddr;
|
||||
output [2:0]M_AXI_arprot;
|
||||
input M_AXI_arready;
|
||||
output M_AXI_arvalid;
|
||||
output [31:0]M_AXI_awaddr;
|
||||
output [2:0]M_AXI_awprot;
|
||||
input M_AXI_awready;
|
||||
output M_AXI_awvalid;
|
||||
output M_AXI_bready;
|
||||
input [1:0]M_AXI_bresp;
|
||||
input M_AXI_bvalid;
|
||||
input [31:0]M_AXI_rdata;
|
||||
output M_AXI_rready;
|
||||
input [1:0]M_AXI_rresp;
|
||||
input M_AXI_rvalid;
|
||||
output [31:0]M_AXI_wdata;
|
||||
input M_AXI_wready;
|
||||
output [3:0]M_AXI_wstrb;
|
||||
output M_AXI_wvalid;
|
||||
input S_ACLK;
|
||||
input S_ARESETN;
|
||||
input [31:0]S_AXI_araddr;
|
||||
input [1:0]S_AXI_arburst;
|
||||
input [3:0]S_AXI_arcache;
|
||||
input [11:0]S_AXI_arid;
|
||||
input [3:0]S_AXI_arlen;
|
||||
input [1:0]S_AXI_arlock;
|
||||
input [2:0]S_AXI_arprot;
|
||||
input [3:0]S_AXI_arqos;
|
||||
output S_AXI_arready;
|
||||
input [2:0]S_AXI_arsize;
|
||||
input S_AXI_arvalid;
|
||||
input [31:0]S_AXI_awaddr;
|
||||
input [1:0]S_AXI_awburst;
|
||||
input [3:0]S_AXI_awcache;
|
||||
input [11:0]S_AXI_awid;
|
||||
input [3:0]S_AXI_awlen;
|
||||
input [1:0]S_AXI_awlock;
|
||||
input [2:0]S_AXI_awprot;
|
||||
input [3:0]S_AXI_awqos;
|
||||
output S_AXI_awready;
|
||||
input [2:0]S_AXI_awsize;
|
||||
input S_AXI_awvalid;
|
||||
output [11:0]S_AXI_bid;
|
||||
input S_AXI_bready;
|
||||
output [1:0]S_AXI_bresp;
|
||||
output S_AXI_bvalid;
|
||||
output [31:0]S_AXI_rdata;
|
||||
output [11:0]S_AXI_rid;
|
||||
output S_AXI_rlast;
|
||||
input S_AXI_rready;
|
||||
output [1:0]S_AXI_rresp;
|
||||
output S_AXI_rvalid;
|
||||
input [31:0]S_AXI_wdata;
|
||||
input [11:0]S_AXI_wid;
|
||||
input S_AXI_wlast;
|
||||
output S_AXI_wready;
|
||||
input [3:0]S_AXI_wstrb;
|
||||
input S_AXI_wvalid;
|
||||
|
||||
wire S_ACLK_1;
|
||||
wire S_ARESETN_1;
|
||||
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
|
||||
wire [2:0]auto_pc_to_s00_couplers_ARPROT;
|
||||
wire auto_pc_to_s00_couplers_ARREADY;
|
||||
wire auto_pc_to_s00_couplers_ARVALID;
|
||||
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
|
||||
wire [2:0]auto_pc_to_s00_couplers_AWPROT;
|
||||
wire auto_pc_to_s00_couplers_AWREADY;
|
||||
wire auto_pc_to_s00_couplers_AWVALID;
|
||||
wire auto_pc_to_s00_couplers_BREADY;
|
||||
wire [1:0]auto_pc_to_s00_couplers_BRESP;
|
||||
wire auto_pc_to_s00_couplers_BVALID;
|
||||
wire [31:0]auto_pc_to_s00_couplers_RDATA;
|
||||
wire auto_pc_to_s00_couplers_RREADY;
|
||||
wire [1:0]auto_pc_to_s00_couplers_RRESP;
|
||||
wire auto_pc_to_s00_couplers_RVALID;
|
||||
wire [31:0]auto_pc_to_s00_couplers_WDATA;
|
||||
wire auto_pc_to_s00_couplers_WREADY;
|
||||
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
|
||||
wire auto_pc_to_s00_couplers_WVALID;
|
||||
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
|
||||
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
|
||||
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
|
||||
wire [11:0]s00_couplers_to_auto_pc_ARID;
|
||||
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
|
||||
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
|
||||
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
|
||||
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
|
||||
wire s00_couplers_to_auto_pc_ARREADY;
|
||||
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
|
||||
wire s00_couplers_to_auto_pc_ARVALID;
|
||||
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
|
||||
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
|
||||
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
|
||||
wire [11:0]s00_couplers_to_auto_pc_AWID;
|
||||
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
|
||||
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
|
||||
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
|
||||
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
|
||||
wire s00_couplers_to_auto_pc_AWREADY;
|
||||
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
|
||||
wire s00_couplers_to_auto_pc_AWVALID;
|
||||
wire [11:0]s00_couplers_to_auto_pc_BID;
|
||||
wire s00_couplers_to_auto_pc_BREADY;
|
||||
wire [1:0]s00_couplers_to_auto_pc_BRESP;
|
||||
wire s00_couplers_to_auto_pc_BVALID;
|
||||
wire [31:0]s00_couplers_to_auto_pc_RDATA;
|
||||
wire [11:0]s00_couplers_to_auto_pc_RID;
|
||||
wire s00_couplers_to_auto_pc_RLAST;
|
||||
wire s00_couplers_to_auto_pc_RREADY;
|
||||
wire [1:0]s00_couplers_to_auto_pc_RRESP;
|
||||
wire s00_couplers_to_auto_pc_RVALID;
|
||||
wire [31:0]s00_couplers_to_auto_pc_WDATA;
|
||||
wire [11:0]s00_couplers_to_auto_pc_WID;
|
||||
wire s00_couplers_to_auto_pc_WLAST;
|
||||
wire s00_couplers_to_auto_pc_WREADY;
|
||||
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
|
||||
wire s00_couplers_to_auto_pc_WVALID;
|
||||
|
||||
assign M_AXI_araddr[31:0] = auto_pc_to_s00_couplers_ARADDR;
|
||||
assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT;
|
||||
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
|
||||
assign M_AXI_awaddr[31:0] = auto_pc_to_s00_couplers_AWADDR;
|
||||
assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT;
|
||||
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
|
||||
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
|
||||
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
|
||||
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
|
||||
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
|
||||
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
|
||||
assign S_ACLK_1 = S_ACLK;
|
||||
assign S_ARESETN_1 = S_ARESETN;
|
||||
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
|
||||
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
|
||||
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
|
||||
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
|
||||
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
|
||||
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
|
||||
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
|
||||
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
|
||||
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
|
||||
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
|
||||
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
|
||||
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
|
||||
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
|
||||
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
|
||||
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
|
||||
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
|
||||
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
|
||||
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
|
||||
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
|
||||
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
|
||||
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
|
||||
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
|
||||
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
|
||||
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
|
||||
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
|
||||
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
|
||||
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
|
||||
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
|
||||
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
|
||||
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
|
||||
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
|
||||
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
|
||||
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
|
||||
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
|
||||
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
|
||||
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
|
||||
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
|
||||
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
|
||||
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
|
||||
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
|
||||
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
|
||||
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
|
||||
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
|
||||
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
|
||||
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
|
||||
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
|
||||
system_auto_pc_0 auto_pc
|
||||
(.aclk(S_ACLK_1),
|
||||
.aresetn(S_ARESETN_1),
|
||||
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
|
||||
.m_axi_arprot(auto_pc_to_s00_couplers_ARPROT),
|
||||
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
|
||||
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
|
||||
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
|
||||
.m_axi_awprot(auto_pc_to_s00_couplers_AWPROT),
|
||||
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
|
||||
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
|
||||
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
|
||||
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
|
||||
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
|
||||
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
|
||||
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
|
||||
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
|
||||
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
|
||||
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
|
||||
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
|
||||
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
|
||||
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
|
||||
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
|
||||
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
|
||||
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
|
||||
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
|
||||
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
|
||||
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
|
||||
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
|
||||
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
|
||||
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
|
||||
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
|
||||
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
|
||||
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
|
||||
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
|
||||
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
|
||||
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
|
||||
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
|
||||
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
|
||||
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
|
||||
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
|
||||
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
|
||||
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
|
||||
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
|
||||
.s_axi_bid(s00_couplers_to_auto_pc_BID),
|
||||
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
|
||||
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
|
||||
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
|
||||
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
|
||||
.s_axi_rid(s00_couplers_to_auto_pc_RID),
|
||||
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
|
||||
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
|
||||
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
|
||||
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
|
||||
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
|
||||
.s_axi_wid(s00_couplers_to_auto_pc_WID),
|
||||
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
|
||||
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
|
||||
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
|
||||
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
|
||||
endmodule
|
||||
|
||||
(* CORE_GENERATION_INFO = "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=7,numReposBlks=5,numNonXlnxBlks=0,numHierBlks=2,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=2,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=2,da_clkrst_cnt=2,da_ps7_cnt=1,synth_mode=None}" *) (* HW_HANDOFF = "system.hwdef" *)
|
||||
module system
|
||||
(DDR_addr,
|
||||
DDR_ba,
|
||||
DDR_cas_n,
|
||||
DDR_ck_n,
|
||||
DDR_ck_p,
|
||||
DDR_cke,
|
||||
DDR_cs_n,
|
||||
DDR_dm,
|
||||
DDR_dq,
|
||||
DDR_dqs_n,
|
||||
DDR_dqs_p,
|
||||
DDR_odt,
|
||||
DDR_ras_n,
|
||||
DDR_reset_n,
|
||||
DDR_we_n,
|
||||
EMIO_0_tri_i,
|
||||
EMIO_0_tri_o,
|
||||
EMIO_0_tri_t,
|
||||
FIXED_IO_ddr_vrn,
|
||||
FIXED_IO_ddr_vrp,
|
||||
FIXED_IO_mio,
|
||||
FIXED_IO_ps_clk,
|
||||
FIXED_IO_ps_porb,
|
||||
FIXED_IO_ps_srstb);
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) inout [14:0]DDR_addr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_ba;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_cas_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_ck_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_ck_p;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_cke;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_cs_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_dm;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_dq;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_dqs_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_dqs_p;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_odt;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_ras_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_reset_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_we_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 EMIO_0 TRI_I" *) input [32:0]EMIO_0_tri_i;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 EMIO_0 TRI_O" *) output [32:0]EMIO_0_tri_o;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 EMIO_0 TRI_T" *) output [32:0]EMIO_0_tri_t;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout FIXED_IO_ddr_vrn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout FIXED_IO_ddr_vrp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]FIXED_IO_mio;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout FIXED_IO_ps_clk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout FIXED_IO_ps_porb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout FIXED_IO_ps_srstb;
|
||||
|
||||
wire [56:0]dna_port_read_0_dna_port;
|
||||
wire dna_port_read_0_read_vld;
|
||||
wire mydna_read_v1_0_0_start_vld;
|
||||
wire [14:0]processing_system7_0_DDR_ADDR;
|
||||
wire [2:0]processing_system7_0_DDR_BA;
|
||||
wire processing_system7_0_DDR_CAS_N;
|
||||
wire processing_system7_0_DDR_CKE;
|
||||
wire processing_system7_0_DDR_CK_N;
|
||||
wire processing_system7_0_DDR_CK_P;
|
||||
wire processing_system7_0_DDR_CS_N;
|
||||
wire [3:0]processing_system7_0_DDR_DM;
|
||||
wire [31:0]processing_system7_0_DDR_DQ;
|
||||
wire [3:0]processing_system7_0_DDR_DQS_N;
|
||||
wire [3:0]processing_system7_0_DDR_DQS_P;
|
||||
wire processing_system7_0_DDR_ODT;
|
||||
wire processing_system7_0_DDR_RAS_N;
|
||||
wire processing_system7_0_DDR_RESET_N;
|
||||
wire processing_system7_0_DDR_WE_N;
|
||||
wire processing_system7_0_FCLK_CLK0;
|
||||
wire processing_system7_0_FCLK_RESET0_N;
|
||||
wire processing_system7_0_FIXED_IO_DDR_VRN;
|
||||
wire processing_system7_0_FIXED_IO_DDR_VRP;
|
||||
wire [53:0]processing_system7_0_FIXED_IO_MIO;
|
||||
wire processing_system7_0_FIXED_IO_PS_CLK;
|
||||
wire processing_system7_0_FIXED_IO_PS_PORB;
|
||||
wire processing_system7_0_FIXED_IO_PS_SRSTB;
|
||||
wire [32:0]processing_system7_0_GPIO_0_TRI_I;
|
||||
wire [32:0]processing_system7_0_GPIO_0_TRI_O;
|
||||
wire [32:0]processing_system7_0_GPIO_0_TRI_T;
|
||||
wire [31:0]processing_system7_0_M_AXI_GP0_ARADDR;
|
||||
wire [1:0]processing_system7_0_M_AXI_GP0_ARBURST;
|
||||
wire [3:0]processing_system7_0_M_AXI_GP0_ARCACHE;
|
||||
wire [11:0]processing_system7_0_M_AXI_GP0_ARID;
|
||||
wire [3:0]processing_system7_0_M_AXI_GP0_ARLEN;
|
||||
wire [1:0]processing_system7_0_M_AXI_GP0_ARLOCK;
|
||||
wire [2:0]processing_system7_0_M_AXI_GP0_ARPROT;
|
||||
wire [3:0]processing_system7_0_M_AXI_GP0_ARQOS;
|
||||
wire processing_system7_0_M_AXI_GP0_ARREADY;
|
||||
wire [2:0]processing_system7_0_M_AXI_GP0_ARSIZE;
|
||||
wire processing_system7_0_M_AXI_GP0_ARVALID;
|
||||
wire [31:0]processing_system7_0_M_AXI_GP0_AWADDR;
|
||||
wire [1:0]processing_system7_0_M_AXI_GP0_AWBURST;
|
||||
wire [3:0]processing_system7_0_M_AXI_GP0_AWCACHE;
|
||||
wire [11:0]processing_system7_0_M_AXI_GP0_AWID;
|
||||
wire [3:0]processing_system7_0_M_AXI_GP0_AWLEN;
|
||||
wire [1:0]processing_system7_0_M_AXI_GP0_AWLOCK;
|
||||
wire [2:0]processing_system7_0_M_AXI_GP0_AWPROT;
|
||||
wire [3:0]processing_system7_0_M_AXI_GP0_AWQOS;
|
||||
wire processing_system7_0_M_AXI_GP0_AWREADY;
|
||||
wire [2:0]processing_system7_0_M_AXI_GP0_AWSIZE;
|
||||
wire processing_system7_0_M_AXI_GP0_AWVALID;
|
||||
wire [11:0]processing_system7_0_M_AXI_GP0_BID;
|
||||
wire processing_system7_0_M_AXI_GP0_BREADY;
|
||||
wire [1:0]processing_system7_0_M_AXI_GP0_BRESP;
|
||||
wire processing_system7_0_M_AXI_GP0_BVALID;
|
||||
wire [31:0]processing_system7_0_M_AXI_GP0_RDATA;
|
||||
wire [11:0]processing_system7_0_M_AXI_GP0_RID;
|
||||
wire processing_system7_0_M_AXI_GP0_RLAST;
|
||||
wire processing_system7_0_M_AXI_GP0_RREADY;
|
||||
wire [1:0]processing_system7_0_M_AXI_GP0_RRESP;
|
||||
wire processing_system7_0_M_AXI_GP0_RVALID;
|
||||
wire [31:0]processing_system7_0_M_AXI_GP0_WDATA;
|
||||
wire [11:0]processing_system7_0_M_AXI_GP0_WID;
|
||||
wire processing_system7_0_M_AXI_GP0_WLAST;
|
||||
wire processing_system7_0_M_AXI_GP0_WREADY;
|
||||
wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB;
|
||||
wire processing_system7_0_M_AXI_GP0_WVALID;
|
||||
wire [31:0]ps7_0_axi_periph_M00_AXI_ARADDR;
|
||||
wire [2:0]ps7_0_axi_periph_M00_AXI_ARPROT;
|
||||
wire ps7_0_axi_periph_M00_AXI_ARREADY;
|
||||
wire ps7_0_axi_periph_M00_AXI_ARVALID;
|
||||
wire [31:0]ps7_0_axi_periph_M00_AXI_AWADDR;
|
||||
wire [2:0]ps7_0_axi_periph_M00_AXI_AWPROT;
|
||||
wire ps7_0_axi_periph_M00_AXI_AWREADY;
|
||||
wire ps7_0_axi_periph_M00_AXI_AWVALID;
|
||||
wire ps7_0_axi_periph_M00_AXI_BREADY;
|
||||
wire [1:0]ps7_0_axi_periph_M00_AXI_BRESP;
|
||||
wire ps7_0_axi_periph_M00_AXI_BVALID;
|
||||
wire [31:0]ps7_0_axi_periph_M00_AXI_RDATA;
|
||||
wire ps7_0_axi_periph_M00_AXI_RREADY;
|
||||
wire [1:0]ps7_0_axi_periph_M00_AXI_RRESP;
|
||||
wire ps7_0_axi_periph_M00_AXI_RVALID;
|
||||
wire [31:0]ps7_0_axi_periph_M00_AXI_WDATA;
|
||||
wire ps7_0_axi_periph_M00_AXI_WREADY;
|
||||
wire [3:0]ps7_0_axi_periph_M00_AXI_WSTRB;
|
||||
wire ps7_0_axi_periph_M00_AXI_WVALID;
|
||||
wire [0:0]rst_ps7_0_100M_interconnect_aresetn;
|
||||
wire [0:0]rst_ps7_0_100M_peripheral_aresetn;
|
||||
|
||||
assign EMIO_0_tri_o[32:0] = processing_system7_0_GPIO_0_TRI_O;
|
||||
assign EMIO_0_tri_t[32:0] = processing_system7_0_GPIO_0_TRI_T;
|
||||
assign processing_system7_0_GPIO_0_TRI_I = EMIO_0_tri_i[32:0];
|
||||
system_dna_port_read_0_0 dna_port_read_0
|
||||
(.clk(processing_system7_0_FCLK_CLK0),
|
||||
.dna_port(dna_port_read_0_dna_port),
|
||||
.read_vld(dna_port_read_0_read_vld),
|
||||
.rst_n(rst_ps7_0_100M_peripheral_aresetn),
|
||||
.start_vld(mydna_read_v1_0_0_start_vld));
|
||||
system_mydna_read_v1_0_0_0 mydna_read_v1_0_0
|
||||
(.dna_port(dna_port_read_0_dna_port),
|
||||
.read_vld(dna_port_read_0_read_vld),
|
||||
.s00_axi_aclk(processing_system7_0_FCLK_CLK0),
|
||||
.s00_axi_araddr(ps7_0_axi_periph_M00_AXI_ARADDR[3:0]),
|
||||
.s00_axi_aresetn(rst_ps7_0_100M_peripheral_aresetn),
|
||||
.s00_axi_arprot(ps7_0_axi_periph_M00_AXI_ARPROT),
|
||||
.s00_axi_arready(ps7_0_axi_periph_M00_AXI_ARREADY),
|
||||
.s00_axi_arvalid(ps7_0_axi_periph_M00_AXI_ARVALID),
|
||||
.s00_axi_awaddr(ps7_0_axi_periph_M00_AXI_AWADDR[3:0]),
|
||||
.s00_axi_awprot(ps7_0_axi_periph_M00_AXI_AWPROT),
|
||||
.s00_axi_awready(ps7_0_axi_periph_M00_AXI_AWREADY),
|
||||
.s00_axi_awvalid(ps7_0_axi_periph_M00_AXI_AWVALID),
|
||||
.s00_axi_bready(ps7_0_axi_periph_M00_AXI_BREADY),
|
||||
.s00_axi_bresp(ps7_0_axi_periph_M00_AXI_BRESP),
|
||||
.s00_axi_bvalid(ps7_0_axi_periph_M00_AXI_BVALID),
|
||||
.s00_axi_rdata(ps7_0_axi_periph_M00_AXI_RDATA),
|
||||
.s00_axi_rready(ps7_0_axi_periph_M00_AXI_RREADY),
|
||||
.s00_axi_rresp(ps7_0_axi_periph_M00_AXI_RRESP),
|
||||
.s00_axi_rvalid(ps7_0_axi_periph_M00_AXI_RVALID),
|
||||
.s00_axi_wdata(ps7_0_axi_periph_M00_AXI_WDATA),
|
||||
.s00_axi_wready(ps7_0_axi_periph_M00_AXI_WREADY),
|
||||
.s00_axi_wstrb(ps7_0_axi_periph_M00_AXI_WSTRB),
|
||||
.s00_axi_wvalid(ps7_0_axi_periph_M00_AXI_WVALID),
|
||||
.start_vld(mydna_read_v1_0_0_start_vld));
|
||||
system_processing_system7_0_0 processing_system7_0
|
||||
(.DDR_Addr(DDR_addr[14:0]),
|
||||
.DDR_BankAddr(DDR_ba[2:0]),
|
||||
.DDR_CAS_n(DDR_cas_n),
|
||||
.DDR_CKE(DDR_cke),
|
||||
.DDR_CS_n(DDR_cs_n),
|
||||
.DDR_Clk(DDR_ck_p),
|
||||
.DDR_Clk_n(DDR_ck_n),
|
||||
.DDR_DM(DDR_dm[3:0]),
|
||||
.DDR_DQ(DDR_dq[31:0]),
|
||||
.DDR_DQS(DDR_dqs_p[3:0]),
|
||||
.DDR_DQS_n(DDR_dqs_n[3:0]),
|
||||
.DDR_DRSTB(DDR_reset_n),
|
||||
.DDR_ODT(DDR_odt),
|
||||
.DDR_RAS_n(DDR_ras_n),
|
||||
.DDR_VRN(FIXED_IO_ddr_vrn),
|
||||
.DDR_VRP(FIXED_IO_ddr_vrp),
|
||||
.DDR_WEB(DDR_we_n),
|
||||
.FCLK_CLK0(processing_system7_0_FCLK_CLK0),
|
||||
.FCLK_RESET0_N(processing_system7_0_FCLK_RESET0_N),
|
||||
.GPIO_I(processing_system7_0_GPIO_0_TRI_I),
|
||||
.GPIO_O(processing_system7_0_GPIO_0_TRI_O),
|
||||
.GPIO_T(processing_system7_0_GPIO_0_TRI_T),
|
||||
.MIO(FIXED_IO_mio[53:0]),
|
||||
.M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0),
|
||||
.M_AXI_GP0_ARADDR(processing_system7_0_M_AXI_GP0_ARADDR),
|
||||
.M_AXI_GP0_ARBURST(processing_system7_0_M_AXI_GP0_ARBURST),
|
||||
.M_AXI_GP0_ARCACHE(processing_system7_0_M_AXI_GP0_ARCACHE),
|
||||
.M_AXI_GP0_ARID(processing_system7_0_M_AXI_GP0_ARID),
|
||||
.M_AXI_GP0_ARLEN(processing_system7_0_M_AXI_GP0_ARLEN),
|
||||
.M_AXI_GP0_ARLOCK(processing_system7_0_M_AXI_GP0_ARLOCK),
|
||||
.M_AXI_GP0_ARPROT(processing_system7_0_M_AXI_GP0_ARPROT),
|
||||
.M_AXI_GP0_ARQOS(processing_system7_0_M_AXI_GP0_ARQOS),
|
||||
.M_AXI_GP0_ARREADY(processing_system7_0_M_AXI_GP0_ARREADY),
|
||||
.M_AXI_GP0_ARSIZE(processing_system7_0_M_AXI_GP0_ARSIZE),
|
||||
.M_AXI_GP0_ARVALID(processing_system7_0_M_AXI_GP0_ARVALID),
|
||||
.M_AXI_GP0_AWADDR(processing_system7_0_M_AXI_GP0_AWADDR),
|
||||
.M_AXI_GP0_AWBURST(processing_system7_0_M_AXI_GP0_AWBURST),
|
||||
.M_AXI_GP0_AWCACHE(processing_system7_0_M_AXI_GP0_AWCACHE),
|
||||
.M_AXI_GP0_AWID(processing_system7_0_M_AXI_GP0_AWID),
|
||||
.M_AXI_GP0_AWLEN(processing_system7_0_M_AXI_GP0_AWLEN),
|
||||
.M_AXI_GP0_AWLOCK(processing_system7_0_M_AXI_GP0_AWLOCK),
|
||||
.M_AXI_GP0_AWPROT(processing_system7_0_M_AXI_GP0_AWPROT),
|
||||
.M_AXI_GP0_AWQOS(processing_system7_0_M_AXI_GP0_AWQOS),
|
||||
.M_AXI_GP0_AWREADY(processing_system7_0_M_AXI_GP0_AWREADY),
|
||||
.M_AXI_GP0_AWSIZE(processing_system7_0_M_AXI_GP0_AWSIZE),
|
||||
.M_AXI_GP0_AWVALID(processing_system7_0_M_AXI_GP0_AWVALID),
|
||||
.M_AXI_GP0_BID(processing_system7_0_M_AXI_GP0_BID),
|
||||
.M_AXI_GP0_BREADY(processing_system7_0_M_AXI_GP0_BREADY),
|
||||
.M_AXI_GP0_BRESP(processing_system7_0_M_AXI_GP0_BRESP),
|
||||
.M_AXI_GP0_BVALID(processing_system7_0_M_AXI_GP0_BVALID),
|
||||
.M_AXI_GP0_RDATA(processing_system7_0_M_AXI_GP0_RDATA),
|
||||
.M_AXI_GP0_RID(processing_system7_0_M_AXI_GP0_RID),
|
||||
.M_AXI_GP0_RLAST(processing_system7_0_M_AXI_GP0_RLAST),
|
||||
.M_AXI_GP0_RREADY(processing_system7_0_M_AXI_GP0_RREADY),
|
||||
.M_AXI_GP0_RRESP(processing_system7_0_M_AXI_GP0_RRESP),
|
||||
.M_AXI_GP0_RVALID(processing_system7_0_M_AXI_GP0_RVALID),
|
||||
.M_AXI_GP0_WDATA(processing_system7_0_M_AXI_GP0_WDATA),
|
||||
.M_AXI_GP0_WID(processing_system7_0_M_AXI_GP0_WID),
|
||||
.M_AXI_GP0_WLAST(processing_system7_0_M_AXI_GP0_WLAST),
|
||||
.M_AXI_GP0_WREADY(processing_system7_0_M_AXI_GP0_WREADY),
|
||||
.M_AXI_GP0_WSTRB(processing_system7_0_M_AXI_GP0_WSTRB),
|
||||
.M_AXI_GP0_WVALID(processing_system7_0_M_AXI_GP0_WVALID),
|
||||
.PS_CLK(FIXED_IO_ps_clk),
|
||||
.PS_PORB(FIXED_IO_ps_porb),
|
||||
.PS_SRSTB(FIXED_IO_ps_srstb));
|
||||
system_ps7_0_axi_periph_1 ps7_0_axi_periph
|
||||
(.ACLK(processing_system7_0_FCLK_CLK0),
|
||||
.ARESETN(rst_ps7_0_100M_interconnect_aresetn),
|
||||
.M00_ACLK(processing_system7_0_FCLK_CLK0),
|
||||
.M00_ARESETN(rst_ps7_0_100M_peripheral_aresetn),
|
||||
.M00_AXI_araddr(ps7_0_axi_periph_M00_AXI_ARADDR),
|
||||
.M00_AXI_arprot(ps7_0_axi_periph_M00_AXI_ARPROT),
|
||||
.M00_AXI_arready(ps7_0_axi_periph_M00_AXI_ARREADY),
|
||||
.M00_AXI_arvalid(ps7_0_axi_periph_M00_AXI_ARVALID),
|
||||
.M00_AXI_awaddr(ps7_0_axi_periph_M00_AXI_AWADDR),
|
||||
.M00_AXI_awprot(ps7_0_axi_periph_M00_AXI_AWPROT),
|
||||
.M00_AXI_awready(ps7_0_axi_periph_M00_AXI_AWREADY),
|
||||
.M00_AXI_awvalid(ps7_0_axi_periph_M00_AXI_AWVALID),
|
||||
.M00_AXI_bready(ps7_0_axi_periph_M00_AXI_BREADY),
|
||||
.M00_AXI_bresp(ps7_0_axi_periph_M00_AXI_BRESP),
|
||||
.M00_AXI_bvalid(ps7_0_axi_periph_M00_AXI_BVALID),
|
||||
.M00_AXI_rdata(ps7_0_axi_periph_M00_AXI_RDATA),
|
||||
.M00_AXI_rready(ps7_0_axi_periph_M00_AXI_RREADY),
|
||||
.M00_AXI_rresp(ps7_0_axi_periph_M00_AXI_RRESP),
|
||||
.M00_AXI_rvalid(ps7_0_axi_periph_M00_AXI_RVALID),
|
||||
.M00_AXI_wdata(ps7_0_axi_periph_M00_AXI_WDATA),
|
||||
.M00_AXI_wready(ps7_0_axi_periph_M00_AXI_WREADY),
|
||||
.M00_AXI_wstrb(ps7_0_axi_periph_M00_AXI_WSTRB),
|
||||
.M00_AXI_wvalid(ps7_0_axi_periph_M00_AXI_WVALID),
|
||||
.S00_ACLK(processing_system7_0_FCLK_CLK0),
|
||||
.S00_ARESETN(rst_ps7_0_100M_peripheral_aresetn),
|
||||
.S00_AXI_araddr(processing_system7_0_M_AXI_GP0_ARADDR),
|
||||
.S00_AXI_arburst(processing_system7_0_M_AXI_GP0_ARBURST),
|
||||
.S00_AXI_arcache(processing_system7_0_M_AXI_GP0_ARCACHE),
|
||||
.S00_AXI_arid(processing_system7_0_M_AXI_GP0_ARID),
|
||||
.S00_AXI_arlen(processing_system7_0_M_AXI_GP0_ARLEN),
|
||||
.S00_AXI_arlock(processing_system7_0_M_AXI_GP0_ARLOCK),
|
||||
.S00_AXI_arprot(processing_system7_0_M_AXI_GP0_ARPROT),
|
||||
.S00_AXI_arqos(processing_system7_0_M_AXI_GP0_ARQOS),
|
||||
.S00_AXI_arready(processing_system7_0_M_AXI_GP0_ARREADY),
|
||||
.S00_AXI_arsize(processing_system7_0_M_AXI_GP0_ARSIZE),
|
||||
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP0_ARVALID),
|
||||
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP0_AWADDR),
|
||||
.S00_AXI_awburst(processing_system7_0_M_AXI_GP0_AWBURST),
|
||||
.S00_AXI_awcache(processing_system7_0_M_AXI_GP0_AWCACHE),
|
||||
.S00_AXI_awid(processing_system7_0_M_AXI_GP0_AWID),
|
||||
.S00_AXI_awlen(processing_system7_0_M_AXI_GP0_AWLEN),
|
||||
.S00_AXI_awlock(processing_system7_0_M_AXI_GP0_AWLOCK),
|
||||
.S00_AXI_awprot(processing_system7_0_M_AXI_GP0_AWPROT),
|
||||
.S00_AXI_awqos(processing_system7_0_M_AXI_GP0_AWQOS),
|
||||
.S00_AXI_awready(processing_system7_0_M_AXI_GP0_AWREADY),
|
||||
.S00_AXI_awsize(processing_system7_0_M_AXI_GP0_AWSIZE),
|
||||
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP0_AWVALID),
|
||||
.S00_AXI_bid(processing_system7_0_M_AXI_GP0_BID),
|
||||
.S00_AXI_bready(processing_system7_0_M_AXI_GP0_BREADY),
|
||||
.S00_AXI_bresp(processing_system7_0_M_AXI_GP0_BRESP),
|
||||
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP0_BVALID),
|
||||
.S00_AXI_rdata(processing_system7_0_M_AXI_GP0_RDATA),
|
||||
.S00_AXI_rid(processing_system7_0_M_AXI_GP0_RID),
|
||||
.S00_AXI_rlast(processing_system7_0_M_AXI_GP0_RLAST),
|
||||
.S00_AXI_rready(processing_system7_0_M_AXI_GP0_RREADY),
|
||||
.S00_AXI_rresp(processing_system7_0_M_AXI_GP0_RRESP),
|
||||
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP0_RVALID),
|
||||
.S00_AXI_wdata(processing_system7_0_M_AXI_GP0_WDATA),
|
||||
.S00_AXI_wid(processing_system7_0_M_AXI_GP0_WID),
|
||||
.S00_AXI_wlast(processing_system7_0_M_AXI_GP0_WLAST),
|
||||
.S00_AXI_wready(processing_system7_0_M_AXI_GP0_WREADY),
|
||||
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP0_WSTRB),
|
||||
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP0_WVALID));
|
||||
system_rst_ps7_0_100M_1 rst_ps7_0_100M
|
||||
(.aux_reset_in(1'b1),
|
||||
.dcm_locked(1'b1),
|
||||
.ext_reset_in(processing_system7_0_FCLK_RESET0_N),
|
||||
.interconnect_aresetn(rst_ps7_0_100M_interconnect_aresetn),
|
||||
.mb_debug_sys_rst(1'b0),
|
||||
.peripheral_aresetn(rst_ps7_0_100M_peripheral_aresetn),
|
||||
.slowest_sync_clk(processing_system7_0_FCLK_CLK0));
|
||||
endmodule
|
||||
|
||||
module system_ps7_0_axi_periph_1
|
||||
(ACLK,
|
||||
ARESETN,
|
||||
M00_ACLK,
|
||||
M00_ARESETN,
|
||||
M00_AXI_araddr,
|
||||
M00_AXI_arprot,
|
||||
M00_AXI_arready,
|
||||
M00_AXI_arvalid,
|
||||
M00_AXI_awaddr,
|
||||
M00_AXI_awprot,
|
||||
M00_AXI_awready,
|
||||
M00_AXI_awvalid,
|
||||
M00_AXI_bready,
|
||||
M00_AXI_bresp,
|
||||
M00_AXI_bvalid,
|
||||
M00_AXI_rdata,
|
||||
M00_AXI_rready,
|
||||
M00_AXI_rresp,
|
||||
M00_AXI_rvalid,
|
||||
M00_AXI_wdata,
|
||||
M00_AXI_wready,
|
||||
M00_AXI_wstrb,
|
||||
M00_AXI_wvalid,
|
||||
S00_ACLK,
|
||||
S00_ARESETN,
|
||||
S00_AXI_araddr,
|
||||
S00_AXI_arburst,
|
||||
S00_AXI_arcache,
|
||||
S00_AXI_arid,
|
||||
S00_AXI_arlen,
|
||||
S00_AXI_arlock,
|
||||
S00_AXI_arprot,
|
||||
S00_AXI_arqos,
|
||||
S00_AXI_arready,
|
||||
S00_AXI_arsize,
|
||||
S00_AXI_arvalid,
|
||||
S00_AXI_awaddr,
|
||||
S00_AXI_awburst,
|
||||
S00_AXI_awcache,
|
||||
S00_AXI_awid,
|
||||
S00_AXI_awlen,
|
||||
S00_AXI_awlock,
|
||||
S00_AXI_awprot,
|
||||
S00_AXI_awqos,
|
||||
S00_AXI_awready,
|
||||
S00_AXI_awsize,
|
||||
S00_AXI_awvalid,
|
||||
S00_AXI_bid,
|
||||
S00_AXI_bready,
|
||||
S00_AXI_bresp,
|
||||
S00_AXI_bvalid,
|
||||
S00_AXI_rdata,
|
||||
S00_AXI_rid,
|
||||
S00_AXI_rlast,
|
||||
S00_AXI_rready,
|
||||
S00_AXI_rresp,
|
||||
S00_AXI_rvalid,
|
||||
S00_AXI_wdata,
|
||||
S00_AXI_wid,
|
||||
S00_AXI_wlast,
|
||||
S00_AXI_wready,
|
||||
S00_AXI_wstrb,
|
||||
S00_AXI_wvalid);
|
||||
input ACLK;
|
||||
input ARESETN;
|
||||
input M00_ACLK;
|
||||
input M00_ARESETN;
|
||||
output [31:0]M00_AXI_araddr;
|
||||
output [2:0]M00_AXI_arprot;
|
||||
input M00_AXI_arready;
|
||||
output M00_AXI_arvalid;
|
||||
output [31:0]M00_AXI_awaddr;
|
||||
output [2:0]M00_AXI_awprot;
|
||||
input M00_AXI_awready;
|
||||
output M00_AXI_awvalid;
|
||||
output M00_AXI_bready;
|
||||
input [1:0]M00_AXI_bresp;
|
||||
input M00_AXI_bvalid;
|
||||
input [31:0]M00_AXI_rdata;
|
||||
output M00_AXI_rready;
|
||||
input [1:0]M00_AXI_rresp;
|
||||
input M00_AXI_rvalid;
|
||||
output [31:0]M00_AXI_wdata;
|
||||
input M00_AXI_wready;
|
||||
output [3:0]M00_AXI_wstrb;
|
||||
output M00_AXI_wvalid;
|
||||
input S00_ACLK;
|
||||
input S00_ARESETN;
|
||||
input [31:0]S00_AXI_araddr;
|
||||
input [1:0]S00_AXI_arburst;
|
||||
input [3:0]S00_AXI_arcache;
|
||||
input [11:0]S00_AXI_arid;
|
||||
input [3:0]S00_AXI_arlen;
|
||||
input [1:0]S00_AXI_arlock;
|
||||
input [2:0]S00_AXI_arprot;
|
||||
input [3:0]S00_AXI_arqos;
|
||||
output S00_AXI_arready;
|
||||
input [2:0]S00_AXI_arsize;
|
||||
input S00_AXI_arvalid;
|
||||
input [31:0]S00_AXI_awaddr;
|
||||
input [1:0]S00_AXI_awburst;
|
||||
input [3:0]S00_AXI_awcache;
|
||||
input [11:0]S00_AXI_awid;
|
||||
input [3:0]S00_AXI_awlen;
|
||||
input [1:0]S00_AXI_awlock;
|
||||
input [2:0]S00_AXI_awprot;
|
||||
input [3:0]S00_AXI_awqos;
|
||||
output S00_AXI_awready;
|
||||
input [2:0]S00_AXI_awsize;
|
||||
input S00_AXI_awvalid;
|
||||
output [11:0]S00_AXI_bid;
|
||||
input S00_AXI_bready;
|
||||
output [1:0]S00_AXI_bresp;
|
||||
output S00_AXI_bvalid;
|
||||
output [31:0]S00_AXI_rdata;
|
||||
output [11:0]S00_AXI_rid;
|
||||
output S00_AXI_rlast;
|
||||
input S00_AXI_rready;
|
||||
output [1:0]S00_AXI_rresp;
|
||||
output S00_AXI_rvalid;
|
||||
input [31:0]S00_AXI_wdata;
|
||||
input [11:0]S00_AXI_wid;
|
||||
input S00_AXI_wlast;
|
||||
output S00_AXI_wready;
|
||||
input [3:0]S00_AXI_wstrb;
|
||||
input S00_AXI_wvalid;
|
||||
|
||||
wire S00_ACLK_1;
|
||||
wire S00_ARESETN_1;
|
||||
wire ps7_0_axi_periph_ACLK_net;
|
||||
wire ps7_0_axi_periph_ARESETN_net;
|
||||
wire [31:0]ps7_0_axi_periph_to_s00_couplers_ARADDR;
|
||||
wire [1:0]ps7_0_axi_periph_to_s00_couplers_ARBURST;
|
||||
wire [3:0]ps7_0_axi_periph_to_s00_couplers_ARCACHE;
|
||||
wire [11:0]ps7_0_axi_periph_to_s00_couplers_ARID;
|
||||
wire [3:0]ps7_0_axi_periph_to_s00_couplers_ARLEN;
|
||||
wire [1:0]ps7_0_axi_periph_to_s00_couplers_ARLOCK;
|
||||
wire [2:0]ps7_0_axi_periph_to_s00_couplers_ARPROT;
|
||||
wire [3:0]ps7_0_axi_periph_to_s00_couplers_ARQOS;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_ARREADY;
|
||||
wire [2:0]ps7_0_axi_periph_to_s00_couplers_ARSIZE;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_ARVALID;
|
||||
wire [31:0]ps7_0_axi_periph_to_s00_couplers_AWADDR;
|
||||
wire [1:0]ps7_0_axi_periph_to_s00_couplers_AWBURST;
|
||||
wire [3:0]ps7_0_axi_periph_to_s00_couplers_AWCACHE;
|
||||
wire [11:0]ps7_0_axi_periph_to_s00_couplers_AWID;
|
||||
wire [3:0]ps7_0_axi_periph_to_s00_couplers_AWLEN;
|
||||
wire [1:0]ps7_0_axi_periph_to_s00_couplers_AWLOCK;
|
||||
wire [2:0]ps7_0_axi_periph_to_s00_couplers_AWPROT;
|
||||
wire [3:0]ps7_0_axi_periph_to_s00_couplers_AWQOS;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_AWREADY;
|
||||
wire [2:0]ps7_0_axi_periph_to_s00_couplers_AWSIZE;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_AWVALID;
|
||||
wire [11:0]ps7_0_axi_periph_to_s00_couplers_BID;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_BREADY;
|
||||
wire [1:0]ps7_0_axi_periph_to_s00_couplers_BRESP;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_BVALID;
|
||||
wire [31:0]ps7_0_axi_periph_to_s00_couplers_RDATA;
|
||||
wire [11:0]ps7_0_axi_periph_to_s00_couplers_RID;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_RLAST;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_RREADY;
|
||||
wire [1:0]ps7_0_axi_periph_to_s00_couplers_RRESP;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_RVALID;
|
||||
wire [31:0]ps7_0_axi_periph_to_s00_couplers_WDATA;
|
||||
wire [11:0]ps7_0_axi_periph_to_s00_couplers_WID;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_WLAST;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_WREADY;
|
||||
wire [3:0]ps7_0_axi_periph_to_s00_couplers_WSTRB;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_WVALID;
|
||||
wire [31:0]s00_couplers_to_ps7_0_axi_periph_ARADDR;
|
||||
wire [2:0]s00_couplers_to_ps7_0_axi_periph_ARPROT;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_ARREADY;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_ARVALID;
|
||||
wire [31:0]s00_couplers_to_ps7_0_axi_periph_AWADDR;
|
||||
wire [2:0]s00_couplers_to_ps7_0_axi_periph_AWPROT;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_AWREADY;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_AWVALID;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_BREADY;
|
||||
wire [1:0]s00_couplers_to_ps7_0_axi_periph_BRESP;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_BVALID;
|
||||
wire [31:0]s00_couplers_to_ps7_0_axi_periph_RDATA;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_RREADY;
|
||||
wire [1:0]s00_couplers_to_ps7_0_axi_periph_RRESP;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_RVALID;
|
||||
wire [31:0]s00_couplers_to_ps7_0_axi_periph_WDATA;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_WREADY;
|
||||
wire [3:0]s00_couplers_to_ps7_0_axi_periph_WSTRB;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_WVALID;
|
||||
|
||||
assign M00_AXI_araddr[31:0] = s00_couplers_to_ps7_0_axi_periph_ARADDR;
|
||||
assign M00_AXI_arprot[2:0] = s00_couplers_to_ps7_0_axi_periph_ARPROT;
|
||||
assign M00_AXI_arvalid = s00_couplers_to_ps7_0_axi_periph_ARVALID;
|
||||
assign M00_AXI_awaddr[31:0] = s00_couplers_to_ps7_0_axi_periph_AWADDR;
|
||||
assign M00_AXI_awprot[2:0] = s00_couplers_to_ps7_0_axi_periph_AWPROT;
|
||||
assign M00_AXI_awvalid = s00_couplers_to_ps7_0_axi_periph_AWVALID;
|
||||
assign M00_AXI_bready = s00_couplers_to_ps7_0_axi_periph_BREADY;
|
||||
assign M00_AXI_rready = s00_couplers_to_ps7_0_axi_periph_RREADY;
|
||||
assign M00_AXI_wdata[31:0] = s00_couplers_to_ps7_0_axi_periph_WDATA;
|
||||
assign M00_AXI_wstrb[3:0] = s00_couplers_to_ps7_0_axi_periph_WSTRB;
|
||||
assign M00_AXI_wvalid = s00_couplers_to_ps7_0_axi_periph_WVALID;
|
||||
assign S00_ACLK_1 = S00_ACLK;
|
||||
assign S00_ARESETN_1 = S00_ARESETN;
|
||||
assign S00_AXI_arready = ps7_0_axi_periph_to_s00_couplers_ARREADY;
|
||||
assign S00_AXI_awready = ps7_0_axi_periph_to_s00_couplers_AWREADY;
|
||||
assign S00_AXI_bid[11:0] = ps7_0_axi_periph_to_s00_couplers_BID;
|
||||
assign S00_AXI_bresp[1:0] = ps7_0_axi_periph_to_s00_couplers_BRESP;
|
||||
assign S00_AXI_bvalid = ps7_0_axi_periph_to_s00_couplers_BVALID;
|
||||
assign S00_AXI_rdata[31:0] = ps7_0_axi_periph_to_s00_couplers_RDATA;
|
||||
assign S00_AXI_rid[11:0] = ps7_0_axi_periph_to_s00_couplers_RID;
|
||||
assign S00_AXI_rlast = ps7_0_axi_periph_to_s00_couplers_RLAST;
|
||||
assign S00_AXI_rresp[1:0] = ps7_0_axi_periph_to_s00_couplers_RRESP;
|
||||
assign S00_AXI_rvalid = ps7_0_axi_periph_to_s00_couplers_RVALID;
|
||||
assign S00_AXI_wready = ps7_0_axi_periph_to_s00_couplers_WREADY;
|
||||
assign ps7_0_axi_periph_ACLK_net = M00_ACLK;
|
||||
assign ps7_0_axi_periph_ARESETN_net = M00_ARESETN;
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARID = S00_AXI_arid[11:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARVALID = S00_AXI_arvalid;
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWID = S00_AXI_awid[11:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWVALID = S00_AXI_awvalid;
|
||||
assign ps7_0_axi_periph_to_s00_couplers_BREADY = S00_AXI_bready;
|
||||
assign ps7_0_axi_periph_to_s00_couplers_RREADY = S00_AXI_rready;
|
||||
assign ps7_0_axi_periph_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_WID = S00_AXI_wid[11:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_WLAST = S00_AXI_wlast;
|
||||
assign ps7_0_axi_periph_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_WVALID = S00_AXI_wvalid;
|
||||
assign s00_couplers_to_ps7_0_axi_periph_ARREADY = M00_AXI_arready;
|
||||
assign s00_couplers_to_ps7_0_axi_periph_AWREADY = M00_AXI_awready;
|
||||
assign s00_couplers_to_ps7_0_axi_periph_BRESP = M00_AXI_bresp[1:0];
|
||||
assign s00_couplers_to_ps7_0_axi_periph_BVALID = M00_AXI_bvalid;
|
||||
assign s00_couplers_to_ps7_0_axi_periph_RDATA = M00_AXI_rdata[31:0];
|
||||
assign s00_couplers_to_ps7_0_axi_periph_RRESP = M00_AXI_rresp[1:0];
|
||||
assign s00_couplers_to_ps7_0_axi_periph_RVALID = M00_AXI_rvalid;
|
||||
assign s00_couplers_to_ps7_0_axi_periph_WREADY = M00_AXI_wready;
|
||||
s00_couplers_imp_11SE3QO s00_couplers
|
||||
(.M_ACLK(ps7_0_axi_periph_ACLK_net),
|
||||
.M_ARESETN(ps7_0_axi_periph_ARESETN_net),
|
||||
.M_AXI_araddr(s00_couplers_to_ps7_0_axi_periph_ARADDR),
|
||||
.M_AXI_arprot(s00_couplers_to_ps7_0_axi_periph_ARPROT),
|
||||
.M_AXI_arready(s00_couplers_to_ps7_0_axi_periph_ARREADY),
|
||||
.M_AXI_arvalid(s00_couplers_to_ps7_0_axi_periph_ARVALID),
|
||||
.M_AXI_awaddr(s00_couplers_to_ps7_0_axi_periph_AWADDR),
|
||||
.M_AXI_awprot(s00_couplers_to_ps7_0_axi_periph_AWPROT),
|
||||
.M_AXI_awready(s00_couplers_to_ps7_0_axi_periph_AWREADY),
|
||||
.M_AXI_awvalid(s00_couplers_to_ps7_0_axi_periph_AWVALID),
|
||||
.M_AXI_bready(s00_couplers_to_ps7_0_axi_periph_BREADY),
|
||||
.M_AXI_bresp(s00_couplers_to_ps7_0_axi_periph_BRESP),
|
||||
.M_AXI_bvalid(s00_couplers_to_ps7_0_axi_periph_BVALID),
|
||||
.M_AXI_rdata(s00_couplers_to_ps7_0_axi_periph_RDATA),
|
||||
.M_AXI_rready(s00_couplers_to_ps7_0_axi_periph_RREADY),
|
||||
.M_AXI_rresp(s00_couplers_to_ps7_0_axi_periph_RRESP),
|
||||
.M_AXI_rvalid(s00_couplers_to_ps7_0_axi_periph_RVALID),
|
||||
.M_AXI_wdata(s00_couplers_to_ps7_0_axi_periph_WDATA),
|
||||
.M_AXI_wready(s00_couplers_to_ps7_0_axi_periph_WREADY),
|
||||
.M_AXI_wstrb(s00_couplers_to_ps7_0_axi_periph_WSTRB),
|
||||
.M_AXI_wvalid(s00_couplers_to_ps7_0_axi_periph_WVALID),
|
||||
.S_ACLK(S00_ACLK_1),
|
||||
.S_ARESETN(S00_ARESETN_1),
|
||||
.S_AXI_araddr(ps7_0_axi_periph_to_s00_couplers_ARADDR),
|
||||
.S_AXI_arburst(ps7_0_axi_periph_to_s00_couplers_ARBURST),
|
||||
.S_AXI_arcache(ps7_0_axi_periph_to_s00_couplers_ARCACHE),
|
||||
.S_AXI_arid(ps7_0_axi_periph_to_s00_couplers_ARID),
|
||||
.S_AXI_arlen(ps7_0_axi_periph_to_s00_couplers_ARLEN),
|
||||
.S_AXI_arlock(ps7_0_axi_periph_to_s00_couplers_ARLOCK),
|
||||
.S_AXI_arprot(ps7_0_axi_periph_to_s00_couplers_ARPROT),
|
||||
.S_AXI_arqos(ps7_0_axi_periph_to_s00_couplers_ARQOS),
|
||||
.S_AXI_arready(ps7_0_axi_periph_to_s00_couplers_ARREADY),
|
||||
.S_AXI_arsize(ps7_0_axi_periph_to_s00_couplers_ARSIZE),
|
||||
.S_AXI_arvalid(ps7_0_axi_periph_to_s00_couplers_ARVALID),
|
||||
.S_AXI_awaddr(ps7_0_axi_periph_to_s00_couplers_AWADDR),
|
||||
.S_AXI_awburst(ps7_0_axi_periph_to_s00_couplers_AWBURST),
|
||||
.S_AXI_awcache(ps7_0_axi_periph_to_s00_couplers_AWCACHE),
|
||||
.S_AXI_awid(ps7_0_axi_periph_to_s00_couplers_AWID),
|
||||
.S_AXI_awlen(ps7_0_axi_periph_to_s00_couplers_AWLEN),
|
||||
.S_AXI_awlock(ps7_0_axi_periph_to_s00_couplers_AWLOCK),
|
||||
.S_AXI_awprot(ps7_0_axi_periph_to_s00_couplers_AWPROT),
|
||||
.S_AXI_awqos(ps7_0_axi_periph_to_s00_couplers_AWQOS),
|
||||
.S_AXI_awready(ps7_0_axi_periph_to_s00_couplers_AWREADY),
|
||||
.S_AXI_awsize(ps7_0_axi_periph_to_s00_couplers_AWSIZE),
|
||||
.S_AXI_awvalid(ps7_0_axi_periph_to_s00_couplers_AWVALID),
|
||||
.S_AXI_bid(ps7_0_axi_periph_to_s00_couplers_BID),
|
||||
.S_AXI_bready(ps7_0_axi_periph_to_s00_couplers_BREADY),
|
||||
.S_AXI_bresp(ps7_0_axi_periph_to_s00_couplers_BRESP),
|
||||
.S_AXI_bvalid(ps7_0_axi_periph_to_s00_couplers_BVALID),
|
||||
.S_AXI_rdata(ps7_0_axi_periph_to_s00_couplers_RDATA),
|
||||
.S_AXI_rid(ps7_0_axi_periph_to_s00_couplers_RID),
|
||||
.S_AXI_rlast(ps7_0_axi_periph_to_s00_couplers_RLAST),
|
||||
.S_AXI_rready(ps7_0_axi_periph_to_s00_couplers_RREADY),
|
||||
.S_AXI_rresp(ps7_0_axi_periph_to_s00_couplers_RRESP),
|
||||
.S_AXI_rvalid(ps7_0_axi_periph_to_s00_couplers_RVALID),
|
||||
.S_AXI_wdata(ps7_0_axi_periph_to_s00_couplers_WDATA),
|
||||
.S_AXI_wid(ps7_0_axi_periph_to_s00_couplers_WID),
|
||||
.S_AXI_wlast(ps7_0_axi_periph_to_s00_couplers_WLAST),
|
||||
.S_AXI_wready(ps7_0_axi_periph_to_s00_couplers_WREADY),
|
||||
.S_AXI_wstrb(ps7_0_axi_periph_to_s00_couplers_WSTRB),
|
||||
.S_AXI_wvalid(ps7_0_axi_periph_to_s00_couplers_WVALID));
|
||||
endmodule
|
||||
@@ -0,0 +1,226 @@
|
||||
{
|
||||
"graphjs": {
|
||||
"version": "1.0",
|
||||
"keys": [
|
||||
{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
"type": "int",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VT",
|
||||
"name": "vert_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BA",
|
||||
"name": "base_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HA",
|
||||
"name": "high_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BP",
|
||||
"name": "base_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HP",
|
||||
"name": "high_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MX",
|
||||
"name": "master_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MI",
|
||||
"name": "master_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MS",
|
||||
"name": "master_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MV",
|
||||
"name": "master_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SX",
|
||||
"name": "slave_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SI",
|
||||
"name": "slave_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MM",
|
||||
"name": "slave_memmap",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SS",
|
||||
"name": "slave_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SV",
|
||||
"name": "slave_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TM",
|
||||
"name": "memory_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TU",
|
||||
"name": "usage_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "LT",
|
||||
"name": "lock_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BT",
|
||||
"name": "boot_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
|
||||
"type": "int",
|
||||
"for": "edge"
|
||||
}
|
||||
],
|
||||
"vertice_type_order": [
|
||||
{
|
||||
"abrv": "BC",
|
||||
"desc": "Block Container"
|
||||
},
|
||||
{
|
||||
"abrv": "PR",
|
||||
"desc": "Parital Reference"
|
||||
},
|
||||
{
|
||||
"abrv": "VR",
|
||||
"desc": "Variant"
|
||||
},
|
||||
{
|
||||
"abrv": "PM",
|
||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
},
|
||||
{
|
||||
"abrv": "AC",
|
||||
"desc": "Assignment Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "ACE",
|
||||
"desc": "Excluded Assign Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "APX",
|
||||
"desc": "Boundary Aperture"
|
||||
},
|
||||
{
|
||||
"abrv": "CIP",
|
||||
"desc": "High level Processing System"
|
||||
}
|
||||
],
|
||||
"vertices": {
|
||||
"V0": {
|
||||
"VM": "system",
|
||||
"VT": "BC"
|
||||
},
|
||||
"V1": {
|
||||
"VH": "2",
|
||||
"VM": "system",
|
||||
"VT": "VR"
|
||||
},
|
||||
"V2": {
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
},
|
||||
"V3": {
|
||||
"VT": "AC",
|
||||
"BA": "0x43C00000",
|
||||
"HA": "0x43C0FFFF",
|
||||
"BP": "C_BASEADDR",
|
||||
"HP": "C_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7_0",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_mydna_read_v1_0_0_reg0",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/mydna_read_v1_0_0",
|
||||
"SI": "s00_axi",
|
||||
"SS": "reg0",
|
||||
"SV": "xilinx.com:module_ref:mydna_read_v1_0:1.0",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
},
|
||||
{
|
||||
"src": "V3",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,57 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="43">
|
||||
<CompositeFile CompositeFileTopName="system" CanBeSetAsTop="true" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1779695252"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1779695252"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1779695252"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1779695252"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth/system.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim/system.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="system_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim/system.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff/system.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="system.bda">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth/system.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
@@ -0,0 +1,11 @@
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
create_clock -name processing_system7_0_FCLK_CLK0 -period 10 [get_pins processing_system7_0/FCLK_CLK0]
|
||||
|
||||
################################################################################
|
||||
Reference in New Issue
Block a user