Add CPLD DC Processing

Vitis_Classic/.analytics

@@ -12,3 +12,14 @@ timestamp=[2026-05-28 18:36:02], mode=BUILD, duration=0:00:02.193, duration_ms=2
 timestamp=[2026-05-28 18:36:10], mode=BUILD, duration=0:00:06.939, duration_ms=6939, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
 timestamp=[2026-05-28 18:36:18], mode=BUILD, duration=0:00:01.197, duration_ms=1197, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
 timestamp=[2026-05-28 18:36:25], mode=BUILD, duration=0:00:06.800, duration_ms=6800, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
+timestamp=[2026-05-29 12:11:21], mode=BUILD, duration=0:00:01.756, duration_ms=1756, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
+timestamp=[2026-05-29 12:12:30], mode=BUILD, duration=0:00:01.836, duration_ms=1836, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
+timestamp=[2026-05-29 12:12:40], mode=BUILD, duration=0:00:10.066, duration_ms=10066, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
+timestamp=[2026-05-29 14:01:44], mode=BUILD, duration=0:00:01.237, duration_ms=1237, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
+timestamp=[2026-05-29 14:01:51], mode=BUILD, duration=0:00:07.132, duration_ms=7132, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
+timestamp=[2026-05-29 14:04:09], mode=BUILD, duration=0:00:01.170, duration_ms=1170, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
+timestamp=[2026-05-29 14:04:16], mode=BUILD, duration=0:00:06.969, duration_ms=6969, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
+timestamp=[2026-05-29 14:06:00], mode=BUILD, duration=0:00:01.181, duration_ms=1181, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
+timestamp=[2026-05-29 14:06:07], mode=BUILD, duration=0:00:06.894, duration_ms=6894, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}
+timestamp=[2026-05-29 14:10:02], mode=BUILD, duration=0:00:01.176, duration_ms=1176, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false}
+timestamp=[2026-05-29 14:10:09], mode=BUILD, duration=0:00:06.854, duration_ms=6854, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false}

Vitis_Classic/NewInstrCalBoard/src/GPIO_Driv.c

@@ -26,7 +26,7 @@ int EMIO_config(void)
 		}
 		else
 		{
-			xil_printf("[I] Successfully Find PS GPIO!\r\n");
+			xil_printf("[D] Successfully Find PS GPIO!\r\n");
 		}
 
 		xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);

Vitis_Classic/NewInstrCalBoard/src/cal_meas.c

@@ -9,7 +9,7 @@
 #include "SPI_Driv.h"
 char     sw_config_data[3] = {0x00,0x00,0x00};
 
-int Command_Parser(u8* recvbuffer)
+int Command_Parser(u8* recvbuffer, u8 len)
 {
 	switch (recvbuffer[0])
 	{
@@ -22,25 +22,172 @@ int Command_Parser(u8* recvbuffer)
 			xil_printf("[I] CPLD RST Done\r\n");
 			break;
 		}
-		case 0xA1:			//PMU Cal
+		case 0xA1:			//DC Cal
 		{
+			xil_printf("[D] Matched Command DC Cal\r\n");
+			//Command Len Sanity Check
+			if (len != DC_CMD_LEN + 1)		//Do NOT forget the command header
+			{
+				xil_printf("[E] \r\n");
+				return XST_INVALID_PARAM;
+			}
+			DC_Control(recvbuffer + 1);		//Op-out the command header
 			break;
 		}
 		case 0xA2:			//Freq Cal
 		{
-
+			xil_printf("[D] Matched Command Freq Cal\r\n");
+			if (len > Freq_CMD_LEN + 1)		//Do NOT forget the command header
+			{
+				/* code */
+				xil_printf("[E] \r\n");
+				return XST_INVALID_PARAM;
+			}
+			sw_config(recvbuffer + 1);		//Op-out the command header
 			break;
 		}
 		
 		default:
 		{
 			xil_printf("[E] Command Header No Match! \r\n[D] Received Command Header:0x%02X Check Command!\r\n",recvbuffer[0]);
-			break;
+			return XST_NO_FEATURE;
 		}
 		
 	}
 }
 
+int DC_Control(u8* idata)
+{
+	//Comannd Parse Variables
+	u8  u_slot       = 0x0;
+	u8  u_m_fun      = 0x0;			//PMU/DPS Sel
+	u16 u_ch_Num     = 0x0;			
+	u8  u_vi_Sel     = 0x0;			//DMM Connection Config
+	u8  u_rLoad      = 0x0;			//rLoadSel
+
+	//CPLD Variables
+	u8 reg_addr		= 0x0;
+	u32 reg_data 	= 0x0;
+
+	//Flags
+	int Status = -255;
+	int cmdValid = 1;
+
+	//We already did length check, so no need to do again here
+
+	u_slot = idata[0];										//1-4
+	u_m_fun = idata[1];										//1:PMU/2:DPS
+	u_ch_Num = (((u16)(idata[2])) << 8) | idata[3];
+	u_vi_Sel = idata[4];										//1:V/2:I
+	u_rLoad = idata[5];										//1~18: Refer to SCH/Protocol
+
+	//Let's do some sanity check
+	if ((u_slot > 4) || (u_slot == 0))
+	{
+		xil_printf("[E] Illege Slot Num check Command! (Slot:1-4)\r\n");
+		cmdValid = -1;
+	}
+	if ((u_m_fun > 2) || (u_m_fun == 0))
+	{
+		xil_printf("[E] Illege Dev Select check Command! (1:PMU/2:DPS)\r\n");
+		cmdValid = -2;
+	}
+	if ((u_vi_Sel > 2) || (u_vi_Sel == 0))
+	{
+		xil_printf("[E] Illege V/I Config check Command! (1:V/2:I)\r\n");
+		cmdValid = -3;
+	}
+	if ((u_rLoad > 18) || (u_rLoad == 0))
+	{
+		xil_printf("[E] Illege RLoad Select check Command! (RLoad:1-18)\r\n");
+		cmdValid = -4;
+	}
+	if (cmdValid != 1)
+	{
+		/* code */
+		return XST_INVALID_PARAM;
+	}
+	
+	//Sanity Check Done
+	//Let's format the CPLD Reg Data
+	//Note here as the CPLD_Write() will smartly set the R/W bit to 1'b1, so no need to handle that here, addr is addr
+	switch (u_rLoad)
+	{
+		case 1:
+		{
+			reg_addr = 0x06;
+			break;
+		}
+		case 2:
+		{
+			reg_addr = 0x07;
+			break;
+		}
+		case 3:
+		{
+			reg_addr = 0x08;
+			break;
+		}
+		case 4:
+		{
+			reg_addr = 0x09;
+			break;
+		}
+		default:				//You should be here
+		{
+			xil_printf("[E] Error Reaching Invaild Slot CPLD Formatting, Check PS Code!\r\n");
+			return XST_FAILURE;
+		}
+	}
+
+	//As the structure of DC regs are the same, we can format the data uniformly
+	//Dev Sel
+	if (u_m_fun == 0x2)
+	{
+		reg_data = 0x800000;			//1:DPS/0:PMU
+		
+	}
+	//V/I Sel
+	if (u_vi_Sel == 0x2)
+	{
+		/* code */
+		reg_data = reg_data | 0x400000;	//1:I/0:V
+	}
+	//RLoad Sel
+	reg_data = reg_data | (((u32)u_rLoad)<<20);
+	//Channel Sel
+	reg_data = reg_data | u_ch_Num;
+
+	Status = CPLD_Write(reg_addr, reg_data);
+
+	if (Status != XST_SUCCESS)
+	{
+		/* code */
+		xil_printf("[E] Error Writing CPLD Reg! Check Log ABOVE!\r\n");
+		return XST_FAILURE;
+	}
+	
+	else
+	{
+		xil_printf("[D] CPLD Write Successfully Done!\r\n");
+	}
+	
+	Status = CPLD_exec();
+
+	if (Status != XST_SUCCESS)
+	{
+		xil_printf("[E] Error Exec CPLD ! Check Log ABOVE!\r\n");
+		return XST_FAILURE;
+	}
+
+	else
+	{
+		xil_printf("[D] CPLD Exec Successfully Done!\r\n");
+	}
+
+	return XST_SUCCESS;
+}
+
 int CPLD_Write(u8 addr,u32 data)
 {
 	u16 reg_addr = addr | 0x80;				//Write bit set to 1'b1
@@ -49,11 +196,13 @@ int CPLD_Write(u8 addr,u32 data)
 	{
 		/* code */
 		xil_printf("[E] CPLD data length should within 24 bits!\r\n");
-		return XST_FAILURE;
+		return XST_INVALID_PARAM;
 	}
 	spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U1);
 	spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U2);
 	spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U3);
+
+	return XST_SUCCESS;
 }
 
 int CPLD_exec()

Vitis_Classic/NewInstrCalBoard/src/cal_meas.h

@@ -10,15 +10,22 @@
 
 #include "sleep.h"
 #include "stdio.h"
+#include "xstatus.h"
 #include "xgpiops.h"
+
 #include "SPI_Driv.h"
 #include "GPIO_Driv.h"
 
 
 #define    dat_width     3
+#define DC_CMD_LEN 6
+#define Freq_CMD_LEN 7      //TODO: Update sw_config()!
 
+int Command_Parser(u8 *recvbuffer, u8 len);
+int DC_Control(u8* idata);
+int CPLD_Write(u8 addr,u32 data);
+int CPLD_exec();
 void sw_config(char *slot_start);
-int Command_Parser(u8 *recvbuffer);
 
 
 #endif /* SRC_CAL_MEAS_H_ */

Vitis_Classic/NewInstrCalBoard/src/main.c

@@ -77,7 +77,7 @@ int main()
 		}
 		else if (Status > 0)
 		{
-			Command_Parser(recvbuffer);
+			Command_Parser(recvbuffer,Status);		//Here Status should equal to length
 		}
 		
 	}