127 lines
6.7 KiB
Plaintext
127 lines
6.7 KiB
Plaintext
[ START MERGED ]
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i_rst_n_c_i i_rst_n_c
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/dec0_wre3 RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_en
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2.CN jtaghub16_jtck
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jrstn_i jtaghub16_jrstn
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w.CN jtaghub16_jtck
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jrstn_i jtaghub16_jrstn
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/jtck_i jtaghub16_jtck
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/jrstn_i jtaghub16_jrstn
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xo2chub/cdn.CN jtaghub16_jtck
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xo2chub/jrstn_i jtaghub16_jrstn
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[ END MERGED ]
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[ START CLIPPED ]
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xo2chub/GND
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/popfeedthru_unused
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/scuba_vlo
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/scuba_vhi
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren_jtck
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/VCC
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_te[2]
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xo2chub/VCC
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xo2chub/bit_count_cry_0_COUT[3]
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xo2chub/rom_rd_addr_cry_0_S0[0]
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xo2chub/N_2
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xo2chub/rom_rd_addr_s_0_S1[7]
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xo2chub/rom_rd_addr_s_0_COUT[7]
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xo2chub/jtdo2_int_prm_16_0_0_S1
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xo2chub/jtdo2_int_prm_16_0_0_S0
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xo2chub/N_3
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xo2chub/er2_tdo[14]
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xo2chub/er2_tdo[15]
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xo2chub/jtdo2_int_prm_15_0_0_S1
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xo2chub/jtdo2_int_prm_15_0_0_S0
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xo2chub/er2_tdo[12]
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xo2chub/er2_tdo[13]
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xo2chub/jtdo2_int_prm_13_0_0_S1
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xo2chub/jtdo2_int_prm_13_0_0_S0
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xo2chub/er2_tdo[10]
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xo2chub/er2_tdo[11]
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xo2chub/jtdo2_int_prm_11_0_0_S1
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xo2chub/jtdo2_int_prm_11_0_0_S0
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xo2chub/er2_tdo[8]
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xo2chub/er2_tdo[9]
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xo2chub/jtdo2_int_prm_9_0_0_S1
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xo2chub/jtdo2_int_prm_9_0_0_S0
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xo2chub/er2_tdo[6]
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xo2chub/er2_tdo[7]
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xo2chub/jtdo2_int_prm_7_0_0_S1
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xo2chub/jtdo2_int_prm_7_0_0_S0
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xo2chub/er2_tdo[4]
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xo2chub/er2_tdo[5]
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xo2chub/jtdo2_int_prm_5_0_0_S1
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xo2chub/jtdo2_int_prm_5_0_0_S0
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xo2chub/er2_tdo[2]
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xo2chub/er2_tdo[3]
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xo2chub/jtdo2_int_prm_3_0_0_S1
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xo2chub/jtdo2_int_prm_3_0_0_S0
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xo2chub/er2_tdo[1]
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xo2chub/jtdo2_int_prm_1_0_0_S0
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xo2chub/jtdo2_int_prm_1_0_0_COUT
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xo2chub/ip_enable[15]
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xo2chub/genblk7.un1_jtagf_u_1
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xo2chub/genblk7.un1_jtagf_u
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xo2chub/tdoa
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xo2chub/tdia
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xo2chub/tmsa
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xo2chub/tcka
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xo2chub/cdn
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xo2chub/bit_count_cry_0_S0[0]
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xo2chub/N_1
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VCC
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/VCC
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/GND
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0_COUT[9]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0_S0[0]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_2
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0_COUT[9]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0_S0[0]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_3
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0_COUT[9]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0_S0[0]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_4
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0_COUT[9]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0_S0[0]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_1
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0_S0[0]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s_0_S1[5]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s_0_COUT[5]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0_S0[0]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0_COUT[5]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/VCC
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/GND
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[4]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0_S0[0]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_1
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s_0_S1[15]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s_0_COUT[15]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/mem_0_0/DO2
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/mem_0_0/DO3
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[3]
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[ END CLIPPED ]
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[ START DESIGN PREFS ]
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SCHEMATIC START ;
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# map: version Diamond (64-bit) 3.14.0.75.2 -- WARNING: Map write only section -- Tue May 26 15:55:16 2026
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SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
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LOCATE COMP "o_miso" SITE "AA14" ;
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LOCATE COMP "i_sys_clk" SITE "B9" ;
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LOCATE COMP "o_err" SITE "AB16" ;
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LOCATE COMP "o_PMU_RC[3]" SITE "P18" ;
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LOCATE COMP "o_PMU_RC[2]" SITE "P19" ;
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LOCATE COMP "o_PMU_RC[1]" SITE "N18" ;
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LOCATE COMP "o_PMU_RC[0]" SITE "V2" ;
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LOCATE COMP "i_cs" SITE "AB11" ;
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LOCATE COMP "i_mosi" SITE "AB12" ;
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LOCATE COMP "i_sclk" SITE "AA10" ;
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LOCATE COMP "i_rst_n" SITE "Y14" ;
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SCHEMATIC END ;
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[ END DESIGN PREFS ]
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