64 lines
3.5 KiB
Plaintext
64 lines
3.5 KiB
Plaintext
<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD2/debug.rvl" Date="2026-05-29">
|
|
<IP Version="1_6_042617"/>
|
|
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD2"/>
|
|
<Core InsertDataset="0" Insert="1" Reveal_sig="695936542" Name="RelayConTop_LA0" ID="0">
|
|
<Setting>
|
|
<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
|
|
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
|
|
<Capture Mode="0" MinSamplesPerTrig="8"/>
|
|
<Event CntEnable="0" MaxEventCnt="8"/>
|
|
<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_RelayConTop_LA0_net"/>
|
|
<DistRAM Disable="0"/>
|
|
</Setting>
|
|
<Dataset Name="Base">
|
|
<Trace>
|
|
<Sig Type="SIG" Name="i_rst_n"/>
|
|
<Sig Type="SIG" Name="CPLD_Con_2/i_con_exec"/>
|
|
<Sig Type="SIG" Name="BUS_Con_2/err_flag"/>
|
|
<Sig Type="SIG" Name="CPLD_Con_2/err_flag"/>
|
|
<Sig Type="SIG" Name="CPLD_Reg_2/err_flag"/>
|
|
<Bus Name="o_PMU_OC_1">
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:0"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:1"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:2"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:3"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:4"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:5"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:6"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:7"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:8"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:9"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:10"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:11"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:12"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:13"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:14"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:15"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:16"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:17"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:18"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:19"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:20"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:21"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:22"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:23"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:24"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:25"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:26"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:27"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:28"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:29"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:30"/>
|
|
<Sig Type="SIG" Name="o_PMU_OC_1:31"/>
|
|
</Bus>
|
|
</Trace>
|
|
<Trigger>
|
|
<TU Serialbits="0" Type="0" ID="1" Sig="i_cs,"/>
|
|
<TU Serialbits="0" Type="0" ID="2" Sig="i_rst_n,"/>
|
|
<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
|
|
<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
|
|
</Trigger>
|
|
</Dataset>
|
|
</Core>
|
|
</Project>
|