yuysh 0d459342ae Add Support for RLoad Open

2026-06-18 10:50:39 +08:00

CPLD1

Add Support for RLoad Open

2026-06-18 10:50:39 +08:00

CPLD2

Fix CPLD1: PMU Logic bug

2026-06-16 14:59:46 +08:00

CPLD3

Fix: CPLD3: Fix PMU4 AD5522 Reset Pin defination

2026-06-16 16:50:40 +08:00

.gitignore

Update ignored items

2026-05-28 10:41:25 +08:00

S

Description

新仪表校准版CPLD仓库

3.3 MiB

Releases 2

v1.1.2

Latest

2026-06-16 07:01:32 +00:00

Languages

Verilog 49.3%

SystemVerilog 38.9%

TeX 11.8%